Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM SystemControl |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_SystemControl_COMPONENT_ |
| 35 | #ifndef _HRI_SystemControl_E54_H_INCLUDED_ |
| 36 | #define _HRI_SystemControl_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_SystemControl_CRITICAL_SECTIONS) |
| 46 | #define SystemControl_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define SystemControl_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define SystemControl_CRITICAL_SECTION_ENTER() |
| 50 | #define SystemControl_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint32_t hri_systemcontrol_actlr_reg_t; |
| 54 | typedef uint32_t hri_systemcontrol_adr_reg_t; |
| 55 | typedef uint32_t hri_systemcontrol_afsr_reg_t; |
| 56 | typedef uint32_t hri_systemcontrol_aircr_reg_t; |
| 57 | typedef uint32_t hri_systemcontrol_bfar_reg_t; |
| 58 | typedef uint32_t hri_systemcontrol_ccr_reg_t; |
| 59 | typedef uint32_t hri_systemcontrol_cfsr_reg_t; |
| 60 | typedef uint32_t hri_systemcontrol_cpacr_reg_t; |
| 61 | typedef uint32_t hri_systemcontrol_cpuid_reg_t; |
| 62 | typedef uint32_t hri_systemcontrol_dfr_reg_t; |
| 63 | typedef uint32_t hri_systemcontrol_dfsr_reg_t; |
| 64 | typedef uint32_t hri_systemcontrol_hfsr_reg_t; |
| 65 | typedef uint32_t hri_systemcontrol_icsr_reg_t; |
| 66 | typedef uint32_t hri_systemcontrol_ictr_reg_t; |
| 67 | typedef uint32_t hri_systemcontrol_isar_reg_t; |
| 68 | typedef uint32_t hri_systemcontrol_mmfar_reg_t; |
| 69 | typedef uint32_t hri_systemcontrol_mmfr_reg_t; |
| 70 | typedef uint32_t hri_systemcontrol_pfr_reg_t; |
| 71 | typedef uint32_t hri_systemcontrol_scr_reg_t; |
| 72 | typedef uint32_t hri_systemcontrol_shcsr_reg_t; |
| 73 | typedef uint32_t hri_systemcontrol_shpr1_reg_t; |
| 74 | typedef uint32_t hri_systemcontrol_shpr2_reg_t; |
| 75 | typedef uint32_t hri_systemcontrol_shpr3_reg_t; |
| 76 | typedef uint32_t hri_systemcontrol_vtor_reg_t; |
| 77 | |
| 78 | static inline hri_systemcontrol_ictr_reg_t hri_systemcontrol_get_ICTR_INTLINESNUM_bf(const void *const hw, |
| 79 | hri_systemcontrol_ictr_reg_t mask) |
| 80 | { |
| 81 | return (((Systemcontrol *)hw)->ICTR.reg & SystemControl_ICTR_INTLINESNUM(mask)) >> 0; |
| 82 | } |
| 83 | |
| 84 | static inline hri_systemcontrol_ictr_reg_t hri_systemcontrol_read_ICTR_INTLINESNUM_bf(const void *const hw) |
| 85 | { |
| 86 | return (((Systemcontrol *)hw)->ICTR.reg & SystemControl_ICTR_INTLINESNUM_Msk) >> 0; |
| 87 | } |
| 88 | |
| 89 | static inline hri_systemcontrol_ictr_reg_t hri_systemcontrol_get_ICTR_reg(const void *const hw, |
| 90 | hri_systemcontrol_ictr_reg_t mask) |
| 91 | { |
| 92 | uint32_t tmp; |
| 93 | tmp = ((Systemcontrol *)hw)->ICTR.reg; |
| 94 | tmp &= mask; |
| 95 | return tmp; |
| 96 | } |
| 97 | |
| 98 | static inline hri_systemcontrol_ictr_reg_t hri_systemcontrol_read_ICTR_reg(const void *const hw) |
| 99 | { |
| 100 | return ((Systemcontrol *)hw)->ICTR.reg; |
| 101 | } |
| 102 | |
| 103 | static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_REVISION_bf(const void *const hw, |
| 104 | hri_systemcontrol_cpuid_reg_t mask) |
| 105 | { |
| 106 | return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_REVISION(mask)) >> 0; |
| 107 | } |
| 108 | |
| 109 | static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_REVISION_bf(const void *const hw) |
| 110 | { |
| 111 | return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_REVISION_Msk) >> 0; |
| 112 | } |
| 113 | |
| 114 | static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_PARTNO_bf(const void *const hw, |
| 115 | hri_systemcontrol_cpuid_reg_t mask) |
| 116 | { |
| 117 | return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_PARTNO(mask)) >> 4; |
| 118 | } |
| 119 | |
| 120 | static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_PARTNO_bf(const void *const hw) |
| 121 | { |
| 122 | return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_PARTNO_Msk) >> 4; |
| 123 | } |
| 124 | |
| 125 | static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_CONSTANT_bf(const void *const hw, |
| 126 | hri_systemcontrol_cpuid_reg_t mask) |
| 127 | { |
| 128 | return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_CONSTANT(mask)) >> 16; |
| 129 | } |
| 130 | |
| 131 | static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_CONSTANT_bf(const void *const hw) |
| 132 | { |
| 133 | return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_CONSTANT_Msk) >> 16; |
| 134 | } |
| 135 | |
| 136 | static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_VARIANT_bf(const void *const hw, |
| 137 | hri_systemcontrol_cpuid_reg_t mask) |
| 138 | { |
| 139 | return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_VARIANT(mask)) >> 20; |
| 140 | } |
| 141 | |
| 142 | static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_VARIANT_bf(const void *const hw) |
| 143 | { |
| 144 | return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_VARIANT_Msk) >> 20; |
| 145 | } |
| 146 | |
| 147 | static inline hri_systemcontrol_cpuid_reg_t |
| 148 | hri_systemcontrol_get_CPUID_IMPLEMENTER_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) |
| 149 | { |
| 150 | return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_IMPLEMENTER(mask)) >> 24; |
| 151 | } |
| 152 | |
| 153 | static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_IMPLEMENTER_bf(const void *const hw) |
| 154 | { |
| 155 | return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_IMPLEMENTER_Msk) >> 24; |
| 156 | } |
| 157 | |
| 158 | static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_reg(const void *const hw, |
| 159 | hri_systemcontrol_cpuid_reg_t mask) |
| 160 | { |
| 161 | uint32_t tmp; |
| 162 | tmp = ((Systemcontrol *)hw)->CPUID.reg; |
| 163 | tmp &= mask; |
| 164 | return tmp; |
| 165 | } |
| 166 | |
| 167 | static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_reg(const void *const hw) |
| 168 | { |
| 169 | return ((Systemcontrol *)hw)->CPUID.reg; |
| 170 | } |
| 171 | |
| 172 | static inline hri_systemcontrol_dfr_reg_t hri_systemcontrol_get_DFR_reg(const void *const hw, |
| 173 | hri_systemcontrol_dfr_reg_t mask) |
| 174 | { |
| 175 | uint32_t tmp; |
| 176 | tmp = ((Systemcontrol *)hw)->DFR.reg; |
| 177 | tmp &= mask; |
| 178 | return tmp; |
| 179 | } |
| 180 | |
| 181 | static inline hri_systemcontrol_dfr_reg_t hri_systemcontrol_read_DFR_reg(const void *const hw) |
| 182 | { |
| 183 | return ((Systemcontrol *)hw)->DFR.reg; |
| 184 | } |
| 185 | |
| 186 | static inline hri_systemcontrol_adr_reg_t hri_systemcontrol_get_ADR_reg(const void *const hw, |
| 187 | hri_systemcontrol_adr_reg_t mask) |
| 188 | { |
| 189 | uint32_t tmp; |
| 190 | tmp = ((Systemcontrol *)hw)->ADR.reg; |
| 191 | tmp &= mask; |
| 192 | return tmp; |
| 193 | } |
| 194 | |
| 195 | static inline hri_systemcontrol_adr_reg_t hri_systemcontrol_read_ADR_reg(const void *const hw) |
| 196 | { |
| 197 | return ((Systemcontrol *)hw)->ADR.reg; |
| 198 | } |
| 199 | |
| 200 | static inline hri_systemcontrol_mmfr_reg_t hri_systemcontrol_get_MMFR_reg(const void *const hw, uint8_t index, |
| 201 | hri_systemcontrol_mmfr_reg_t mask) |
| 202 | { |
| 203 | uint32_t tmp; |
| 204 | tmp = ((Systemcontrol *)hw)->MMFR[index].reg; |
| 205 | tmp &= mask; |
| 206 | return tmp; |
| 207 | } |
| 208 | |
| 209 | static inline hri_systemcontrol_mmfr_reg_t hri_systemcontrol_read_MMFR_reg(const void *const hw, uint8_t index) |
| 210 | { |
| 211 | return ((Systemcontrol *)hw)->MMFR[index].reg; |
| 212 | } |
| 213 | |
| 214 | static inline hri_systemcontrol_isar_reg_t hri_systemcontrol_get_ISAR_reg(const void *const hw, uint8_t index, |
| 215 | hri_systemcontrol_isar_reg_t mask) |
| 216 | { |
| 217 | uint32_t tmp; |
| 218 | tmp = ((Systemcontrol *)hw)->ISAR[index].reg; |
| 219 | tmp &= mask; |
| 220 | return tmp; |
| 221 | } |
| 222 | |
| 223 | static inline hri_systemcontrol_isar_reg_t hri_systemcontrol_read_ISAR_reg(const void *const hw, uint8_t index) |
| 224 | { |
| 225 | return ((Systemcontrol *)hw)->ISAR[index].reg; |
| 226 | } |
| 227 | |
| 228 | static inline void hri_systemcontrol_set_ACTLR_reg(const void *const hw, hri_systemcontrol_actlr_reg_t mask) |
| 229 | { |
| 230 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 231 | ((Systemcontrol *)hw)->ACTLR.reg |= mask; |
| 232 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 233 | } |
| 234 | |
| 235 | static inline hri_systemcontrol_actlr_reg_t hri_systemcontrol_get_ACTLR_reg(const void *const hw, |
| 236 | hri_systemcontrol_actlr_reg_t mask) |
| 237 | { |
| 238 | uint32_t tmp; |
| 239 | tmp = ((Systemcontrol *)hw)->ACTLR.reg; |
| 240 | tmp &= mask; |
| 241 | return tmp; |
| 242 | } |
| 243 | |
| 244 | static inline void hri_systemcontrol_write_ACTLR_reg(const void *const hw, hri_systemcontrol_actlr_reg_t data) |
| 245 | { |
| 246 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 247 | ((Systemcontrol *)hw)->ACTLR.reg = data; |
| 248 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 249 | } |
| 250 | |
| 251 | static inline void hri_systemcontrol_clear_ACTLR_reg(const void *const hw, hri_systemcontrol_actlr_reg_t mask) |
| 252 | { |
| 253 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 254 | ((Systemcontrol *)hw)->ACTLR.reg &= ~mask; |
| 255 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 256 | } |
| 257 | |
| 258 | static inline void hri_systemcontrol_toggle_ACTLR_reg(const void *const hw, hri_systemcontrol_actlr_reg_t mask) |
| 259 | { |
| 260 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 261 | ((Systemcontrol *)hw)->ACTLR.reg ^= mask; |
| 262 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 263 | } |
| 264 | |
| 265 | static inline hri_systemcontrol_actlr_reg_t hri_systemcontrol_read_ACTLR_reg(const void *const hw) |
| 266 | { |
| 267 | return ((Systemcontrol *)hw)->ACTLR.reg; |
| 268 | } |
| 269 | |
| 270 | static inline void hri_systemcontrol_set_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask) |
| 271 | { |
| 272 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 273 | ((Systemcontrol *)hw)->ICSR.reg |= mask; |
| 274 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 275 | } |
| 276 | |
| 277 | static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_get_ICSR_reg(const void *const hw, |
| 278 | hri_systemcontrol_icsr_reg_t mask) |
| 279 | { |
| 280 | uint32_t tmp; |
| 281 | tmp = ((Systemcontrol *)hw)->ICSR.reg; |
| 282 | tmp &= mask; |
| 283 | return tmp; |
| 284 | } |
| 285 | |
| 286 | static inline void hri_systemcontrol_write_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t data) |
| 287 | { |
| 288 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 289 | ((Systemcontrol *)hw)->ICSR.reg = data; |
| 290 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 291 | } |
| 292 | |
| 293 | static inline void hri_systemcontrol_clear_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask) |
| 294 | { |
| 295 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 296 | ((Systemcontrol *)hw)->ICSR.reg &= ~mask; |
| 297 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 298 | } |
| 299 | |
| 300 | static inline void hri_systemcontrol_toggle_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask) |
| 301 | { |
| 302 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 303 | ((Systemcontrol *)hw)->ICSR.reg ^= mask; |
| 304 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 305 | } |
| 306 | |
| 307 | static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_read_ICSR_reg(const void *const hw) |
| 308 | { |
| 309 | return ((Systemcontrol *)hw)->ICSR.reg; |
| 310 | } |
| 311 | |
| 312 | static inline void hri_systemcontrol_set_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask) |
| 313 | { |
| 314 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 315 | ((Systemcontrol *)hw)->VTOR.reg |= mask; |
| 316 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 317 | } |
| 318 | |
| 319 | static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_get_VTOR_reg(const void *const hw, |
| 320 | hri_systemcontrol_vtor_reg_t mask) |
| 321 | { |
| 322 | uint32_t tmp; |
| 323 | tmp = ((Systemcontrol *)hw)->VTOR.reg; |
| 324 | tmp &= mask; |
| 325 | return tmp; |
| 326 | } |
| 327 | |
| 328 | static inline void hri_systemcontrol_write_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t data) |
| 329 | { |
| 330 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 331 | ((Systemcontrol *)hw)->VTOR.reg = data; |
| 332 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 333 | } |
| 334 | |
| 335 | static inline void hri_systemcontrol_clear_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask) |
| 336 | { |
| 337 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 338 | ((Systemcontrol *)hw)->VTOR.reg &= ~mask; |
| 339 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 340 | } |
| 341 | |
| 342 | static inline void hri_systemcontrol_toggle_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask) |
| 343 | { |
| 344 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 345 | ((Systemcontrol *)hw)->VTOR.reg ^= mask; |
| 346 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 347 | } |
| 348 | |
| 349 | static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_read_VTOR_reg(const void *const hw) |
| 350 | { |
| 351 | return ((Systemcontrol *)hw)->VTOR.reg; |
| 352 | } |
| 353 | |
| 354 | static inline void hri_systemcontrol_set_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask) |
| 355 | { |
| 356 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 357 | ((Systemcontrol *)hw)->AIRCR.reg |= mask; |
| 358 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 359 | } |
| 360 | |
| 361 | static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_get_AIRCR_reg(const void *const hw, |
| 362 | hri_systemcontrol_aircr_reg_t mask) |
| 363 | { |
| 364 | uint32_t tmp; |
| 365 | tmp = ((Systemcontrol *)hw)->AIRCR.reg; |
| 366 | tmp &= mask; |
| 367 | return tmp; |
| 368 | } |
| 369 | |
| 370 | static inline void hri_systemcontrol_write_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t data) |
| 371 | { |
| 372 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 373 | ((Systemcontrol *)hw)->AIRCR.reg = data; |
| 374 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 375 | } |
| 376 | |
| 377 | static inline void hri_systemcontrol_clear_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask) |
| 378 | { |
| 379 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 380 | ((Systemcontrol *)hw)->AIRCR.reg &= ~mask; |
| 381 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 382 | } |
| 383 | |
| 384 | static inline void hri_systemcontrol_toggle_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask) |
| 385 | { |
| 386 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 387 | ((Systemcontrol *)hw)->AIRCR.reg ^= mask; |
| 388 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 389 | } |
| 390 | |
| 391 | static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_read_AIRCR_reg(const void *const hw) |
| 392 | { |
| 393 | return ((Systemcontrol *)hw)->AIRCR.reg; |
| 394 | } |
| 395 | |
| 396 | static inline void hri_systemcontrol_set_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask) |
| 397 | { |
| 398 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 399 | ((Systemcontrol *)hw)->SCR.reg |= mask; |
| 400 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 401 | } |
| 402 | |
| 403 | static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_get_SCR_reg(const void *const hw, |
| 404 | hri_systemcontrol_scr_reg_t mask) |
| 405 | { |
| 406 | uint32_t tmp; |
| 407 | tmp = ((Systemcontrol *)hw)->SCR.reg; |
| 408 | tmp &= mask; |
| 409 | return tmp; |
| 410 | } |
| 411 | |
| 412 | static inline void hri_systemcontrol_write_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t data) |
| 413 | { |
| 414 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 415 | ((Systemcontrol *)hw)->SCR.reg = data; |
| 416 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 417 | } |
| 418 | |
| 419 | static inline void hri_systemcontrol_clear_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask) |
| 420 | { |
| 421 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 422 | ((Systemcontrol *)hw)->SCR.reg &= ~mask; |
| 423 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 424 | } |
| 425 | |
| 426 | static inline void hri_systemcontrol_toggle_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask) |
| 427 | { |
| 428 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 429 | ((Systemcontrol *)hw)->SCR.reg ^= mask; |
| 430 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 431 | } |
| 432 | |
| 433 | static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_read_SCR_reg(const void *const hw) |
| 434 | { |
| 435 | return ((Systemcontrol *)hw)->SCR.reg; |
| 436 | } |
| 437 | |
| 438 | static inline void hri_systemcontrol_set_CCR_reg(const void *const hw, hri_systemcontrol_ccr_reg_t mask) |
| 439 | { |
| 440 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 441 | ((Systemcontrol *)hw)->CCR.reg |= mask; |
| 442 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 443 | } |
| 444 | |
| 445 | static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_get_CCR_reg(const void *const hw, |
| 446 | hri_systemcontrol_ccr_reg_t mask) |
| 447 | { |
| 448 | uint32_t tmp; |
| 449 | tmp = ((Systemcontrol *)hw)->CCR.reg; |
| 450 | tmp &= mask; |
| 451 | return tmp; |
| 452 | } |
| 453 | |
| 454 | static inline void hri_systemcontrol_write_CCR_reg(const void *const hw, hri_systemcontrol_ccr_reg_t data) |
| 455 | { |
| 456 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 457 | ((Systemcontrol *)hw)->CCR.reg = data; |
| 458 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 459 | } |
| 460 | |
| 461 | static inline void hri_systemcontrol_clear_CCR_reg(const void *const hw, hri_systemcontrol_ccr_reg_t mask) |
| 462 | { |
| 463 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 464 | ((Systemcontrol *)hw)->CCR.reg &= ~mask; |
| 465 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 466 | } |
| 467 | |
| 468 | static inline void hri_systemcontrol_toggle_CCR_reg(const void *const hw, hri_systemcontrol_ccr_reg_t mask) |
| 469 | { |
| 470 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 471 | ((Systemcontrol *)hw)->CCR.reg ^= mask; |
| 472 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 473 | } |
| 474 | |
| 475 | static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_read_CCR_reg(const void *const hw) |
| 476 | { |
| 477 | return ((Systemcontrol *)hw)->CCR.reg; |
| 478 | } |
| 479 | |
| 480 | static inline void hri_systemcontrol_set_SHPR1_reg(const void *const hw, hri_systemcontrol_shpr1_reg_t mask) |
| 481 | { |
| 482 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 483 | ((Systemcontrol *)hw)->SHPR1.reg |= mask; |
| 484 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 485 | } |
| 486 | |
| 487 | static inline hri_systemcontrol_shpr1_reg_t hri_systemcontrol_get_SHPR1_reg(const void *const hw, |
| 488 | hri_systemcontrol_shpr1_reg_t mask) |
| 489 | { |
| 490 | uint32_t tmp; |
| 491 | tmp = ((Systemcontrol *)hw)->SHPR1.reg; |
| 492 | tmp &= mask; |
| 493 | return tmp; |
| 494 | } |
| 495 | |
| 496 | static inline void hri_systemcontrol_write_SHPR1_reg(const void *const hw, hri_systemcontrol_shpr1_reg_t data) |
| 497 | { |
| 498 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 499 | ((Systemcontrol *)hw)->SHPR1.reg = data; |
| 500 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 501 | } |
| 502 | |
| 503 | static inline void hri_systemcontrol_clear_SHPR1_reg(const void *const hw, hri_systemcontrol_shpr1_reg_t mask) |
| 504 | { |
| 505 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 506 | ((Systemcontrol *)hw)->SHPR1.reg &= ~mask; |
| 507 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 508 | } |
| 509 | |
| 510 | static inline void hri_systemcontrol_toggle_SHPR1_reg(const void *const hw, hri_systemcontrol_shpr1_reg_t mask) |
| 511 | { |
| 512 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 513 | ((Systemcontrol *)hw)->SHPR1.reg ^= mask; |
| 514 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 515 | } |
| 516 | |
| 517 | static inline hri_systemcontrol_shpr1_reg_t hri_systemcontrol_read_SHPR1_reg(const void *const hw) |
| 518 | { |
| 519 | return ((Systemcontrol *)hw)->SHPR1.reg; |
| 520 | } |
| 521 | |
| 522 | static inline void hri_systemcontrol_set_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) |
| 523 | { |
| 524 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 525 | ((Systemcontrol *)hw)->SHPR2.reg |= mask; |
| 526 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 527 | } |
| 528 | |
| 529 | static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_get_SHPR2_reg(const void *const hw, |
| 530 | hri_systemcontrol_shpr2_reg_t mask) |
| 531 | { |
| 532 | uint32_t tmp; |
| 533 | tmp = ((Systemcontrol *)hw)->SHPR2.reg; |
| 534 | tmp &= mask; |
| 535 | return tmp; |
| 536 | } |
| 537 | |
| 538 | static inline void hri_systemcontrol_write_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t data) |
| 539 | { |
| 540 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 541 | ((Systemcontrol *)hw)->SHPR2.reg = data; |
| 542 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 543 | } |
| 544 | |
| 545 | static inline void hri_systemcontrol_clear_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) |
| 546 | { |
| 547 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 548 | ((Systemcontrol *)hw)->SHPR2.reg &= ~mask; |
| 549 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 550 | } |
| 551 | |
| 552 | static inline void hri_systemcontrol_toggle_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) |
| 553 | { |
| 554 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 555 | ((Systemcontrol *)hw)->SHPR2.reg ^= mask; |
| 556 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 557 | } |
| 558 | |
| 559 | static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_read_SHPR2_reg(const void *const hw) |
| 560 | { |
| 561 | return ((Systemcontrol *)hw)->SHPR2.reg; |
| 562 | } |
| 563 | |
| 564 | static inline void hri_systemcontrol_set_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) |
| 565 | { |
| 566 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 567 | ((Systemcontrol *)hw)->SHPR3.reg |= mask; |
| 568 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 569 | } |
| 570 | |
| 571 | static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_get_SHPR3_reg(const void *const hw, |
| 572 | hri_systemcontrol_shpr3_reg_t mask) |
| 573 | { |
| 574 | uint32_t tmp; |
| 575 | tmp = ((Systemcontrol *)hw)->SHPR3.reg; |
| 576 | tmp &= mask; |
| 577 | return tmp; |
| 578 | } |
| 579 | |
| 580 | static inline void hri_systemcontrol_write_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t data) |
| 581 | { |
| 582 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 583 | ((Systemcontrol *)hw)->SHPR3.reg = data; |
| 584 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 585 | } |
| 586 | |
| 587 | static inline void hri_systemcontrol_clear_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) |
| 588 | { |
| 589 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 590 | ((Systemcontrol *)hw)->SHPR3.reg &= ~mask; |
| 591 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 592 | } |
| 593 | |
| 594 | static inline void hri_systemcontrol_toggle_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) |
| 595 | { |
| 596 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 597 | ((Systemcontrol *)hw)->SHPR3.reg ^= mask; |
| 598 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 599 | } |
| 600 | |
| 601 | static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_read_SHPR3_reg(const void *const hw) |
| 602 | { |
| 603 | return ((Systemcontrol *)hw)->SHPR3.reg; |
| 604 | } |
| 605 | |
| 606 | static inline void hri_systemcontrol_set_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask) |
| 607 | { |
| 608 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 609 | ((Systemcontrol *)hw)->SHCSR.reg |= mask; |
| 610 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 611 | } |
| 612 | |
| 613 | static inline hri_systemcontrol_shcsr_reg_t hri_systemcontrol_get_SHCSR_reg(const void *const hw, |
| 614 | hri_systemcontrol_shcsr_reg_t mask) |
| 615 | { |
| 616 | uint32_t tmp; |
| 617 | tmp = ((Systemcontrol *)hw)->SHCSR.reg; |
| 618 | tmp &= mask; |
| 619 | return tmp; |
| 620 | } |
| 621 | |
| 622 | static inline void hri_systemcontrol_write_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t data) |
| 623 | { |
| 624 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 625 | ((Systemcontrol *)hw)->SHCSR.reg = data; |
| 626 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 627 | } |
| 628 | |
| 629 | static inline void hri_systemcontrol_clear_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask) |
| 630 | { |
| 631 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 632 | ((Systemcontrol *)hw)->SHCSR.reg &= ~mask; |
| 633 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 634 | } |
| 635 | |
| 636 | static inline void hri_systemcontrol_toggle_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask) |
| 637 | { |
| 638 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 639 | ((Systemcontrol *)hw)->SHCSR.reg ^= mask; |
| 640 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 641 | } |
| 642 | |
| 643 | static inline hri_systemcontrol_shcsr_reg_t hri_systemcontrol_read_SHCSR_reg(const void *const hw) |
| 644 | { |
| 645 | return ((Systemcontrol *)hw)->SHCSR.reg; |
| 646 | } |
| 647 | |
| 648 | static inline void hri_systemcontrol_set_CFSR_reg(const void *const hw, hri_systemcontrol_cfsr_reg_t mask) |
| 649 | { |
| 650 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 651 | ((Systemcontrol *)hw)->CFSR.reg |= mask; |
| 652 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 653 | } |
| 654 | |
| 655 | static inline hri_systemcontrol_cfsr_reg_t hri_systemcontrol_get_CFSR_reg(const void *const hw, |
| 656 | hri_systemcontrol_cfsr_reg_t mask) |
| 657 | { |
| 658 | uint32_t tmp; |
| 659 | tmp = ((Systemcontrol *)hw)->CFSR.reg; |
| 660 | tmp &= mask; |
| 661 | return tmp; |
| 662 | } |
| 663 | |
| 664 | static inline void hri_systemcontrol_write_CFSR_reg(const void *const hw, hri_systemcontrol_cfsr_reg_t data) |
| 665 | { |
| 666 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 667 | ((Systemcontrol *)hw)->CFSR.reg = data; |
| 668 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 669 | } |
| 670 | |
| 671 | static inline void hri_systemcontrol_clear_CFSR_reg(const void *const hw, hri_systemcontrol_cfsr_reg_t mask) |
| 672 | { |
| 673 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 674 | ((Systemcontrol *)hw)->CFSR.reg &= ~mask; |
| 675 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 676 | } |
| 677 | |
| 678 | static inline void hri_systemcontrol_toggle_CFSR_reg(const void *const hw, hri_systemcontrol_cfsr_reg_t mask) |
| 679 | { |
| 680 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 681 | ((Systemcontrol *)hw)->CFSR.reg ^= mask; |
| 682 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 683 | } |
| 684 | |
| 685 | static inline hri_systemcontrol_cfsr_reg_t hri_systemcontrol_read_CFSR_reg(const void *const hw) |
| 686 | { |
| 687 | return ((Systemcontrol *)hw)->CFSR.reg; |
| 688 | } |
| 689 | |
| 690 | static inline void hri_systemcontrol_set_HFSR_reg(const void *const hw, hri_systemcontrol_hfsr_reg_t mask) |
| 691 | { |
| 692 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 693 | ((Systemcontrol *)hw)->HFSR.reg |= mask; |
| 694 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 695 | } |
| 696 | |
| 697 | static inline hri_systemcontrol_hfsr_reg_t hri_systemcontrol_get_HFSR_reg(const void *const hw, |
| 698 | hri_systemcontrol_hfsr_reg_t mask) |
| 699 | { |
| 700 | uint32_t tmp; |
| 701 | tmp = ((Systemcontrol *)hw)->HFSR.reg; |
| 702 | tmp &= mask; |
| 703 | return tmp; |
| 704 | } |
| 705 | |
| 706 | static inline void hri_systemcontrol_write_HFSR_reg(const void *const hw, hri_systemcontrol_hfsr_reg_t data) |
| 707 | { |
| 708 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 709 | ((Systemcontrol *)hw)->HFSR.reg = data; |
| 710 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 711 | } |
| 712 | |
| 713 | static inline void hri_systemcontrol_clear_HFSR_reg(const void *const hw, hri_systemcontrol_hfsr_reg_t mask) |
| 714 | { |
| 715 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 716 | ((Systemcontrol *)hw)->HFSR.reg &= ~mask; |
| 717 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 718 | } |
| 719 | |
| 720 | static inline void hri_systemcontrol_toggle_HFSR_reg(const void *const hw, hri_systemcontrol_hfsr_reg_t mask) |
| 721 | { |
| 722 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 723 | ((Systemcontrol *)hw)->HFSR.reg ^= mask; |
| 724 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 725 | } |
| 726 | |
| 727 | static inline hri_systemcontrol_hfsr_reg_t hri_systemcontrol_read_HFSR_reg(const void *const hw) |
| 728 | { |
| 729 | return ((Systemcontrol *)hw)->HFSR.reg; |
| 730 | } |
| 731 | |
| 732 | static inline void hri_systemcontrol_set_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask) |
| 733 | { |
| 734 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 735 | ((Systemcontrol *)hw)->DFSR.reg |= mask; |
| 736 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 737 | } |
| 738 | |
| 739 | static inline hri_systemcontrol_dfsr_reg_t hri_systemcontrol_get_DFSR_reg(const void *const hw, |
| 740 | hri_systemcontrol_dfsr_reg_t mask) |
| 741 | { |
| 742 | uint32_t tmp; |
| 743 | tmp = ((Systemcontrol *)hw)->DFSR.reg; |
| 744 | tmp &= mask; |
| 745 | return tmp; |
| 746 | } |
| 747 | |
| 748 | static inline void hri_systemcontrol_write_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t data) |
| 749 | { |
| 750 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 751 | ((Systemcontrol *)hw)->DFSR.reg = data; |
| 752 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 753 | } |
| 754 | |
| 755 | static inline void hri_systemcontrol_clear_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask) |
| 756 | { |
| 757 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 758 | ((Systemcontrol *)hw)->DFSR.reg &= ~mask; |
| 759 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 760 | } |
| 761 | |
| 762 | static inline void hri_systemcontrol_toggle_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask) |
| 763 | { |
| 764 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 765 | ((Systemcontrol *)hw)->DFSR.reg ^= mask; |
| 766 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 767 | } |
| 768 | |
| 769 | static inline hri_systemcontrol_dfsr_reg_t hri_systemcontrol_read_DFSR_reg(const void *const hw) |
| 770 | { |
| 771 | return ((Systemcontrol *)hw)->DFSR.reg; |
| 772 | } |
| 773 | |
| 774 | static inline void hri_systemcontrol_set_MMFAR_reg(const void *const hw, hri_systemcontrol_mmfar_reg_t mask) |
| 775 | { |
| 776 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 777 | ((Systemcontrol *)hw)->MMFAR.reg |= mask; |
| 778 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 779 | } |
| 780 | |
| 781 | static inline hri_systemcontrol_mmfar_reg_t hri_systemcontrol_get_MMFAR_reg(const void *const hw, |
| 782 | hri_systemcontrol_mmfar_reg_t mask) |
| 783 | { |
| 784 | uint32_t tmp; |
| 785 | tmp = ((Systemcontrol *)hw)->MMFAR.reg; |
| 786 | tmp &= mask; |
| 787 | return tmp; |
| 788 | } |
| 789 | |
| 790 | static inline void hri_systemcontrol_write_MMFAR_reg(const void *const hw, hri_systemcontrol_mmfar_reg_t data) |
| 791 | { |
| 792 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 793 | ((Systemcontrol *)hw)->MMFAR.reg = data; |
| 794 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 795 | } |
| 796 | |
| 797 | static inline void hri_systemcontrol_clear_MMFAR_reg(const void *const hw, hri_systemcontrol_mmfar_reg_t mask) |
| 798 | { |
| 799 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 800 | ((Systemcontrol *)hw)->MMFAR.reg &= ~mask; |
| 801 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 802 | } |
| 803 | |
| 804 | static inline void hri_systemcontrol_toggle_MMFAR_reg(const void *const hw, hri_systemcontrol_mmfar_reg_t mask) |
| 805 | { |
| 806 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 807 | ((Systemcontrol *)hw)->MMFAR.reg ^= mask; |
| 808 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 809 | } |
| 810 | |
| 811 | static inline hri_systemcontrol_mmfar_reg_t hri_systemcontrol_read_MMFAR_reg(const void *const hw) |
| 812 | { |
| 813 | return ((Systemcontrol *)hw)->MMFAR.reg; |
| 814 | } |
| 815 | |
| 816 | static inline void hri_systemcontrol_set_BFAR_reg(const void *const hw, hri_systemcontrol_bfar_reg_t mask) |
| 817 | { |
| 818 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 819 | ((Systemcontrol *)hw)->BFAR.reg |= mask; |
| 820 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 821 | } |
| 822 | |
| 823 | static inline hri_systemcontrol_bfar_reg_t hri_systemcontrol_get_BFAR_reg(const void *const hw, |
| 824 | hri_systemcontrol_bfar_reg_t mask) |
| 825 | { |
| 826 | uint32_t tmp; |
| 827 | tmp = ((Systemcontrol *)hw)->BFAR.reg; |
| 828 | tmp &= mask; |
| 829 | return tmp; |
| 830 | } |
| 831 | |
| 832 | static inline void hri_systemcontrol_write_BFAR_reg(const void *const hw, hri_systemcontrol_bfar_reg_t data) |
| 833 | { |
| 834 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 835 | ((Systemcontrol *)hw)->BFAR.reg = data; |
| 836 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 837 | } |
| 838 | |
| 839 | static inline void hri_systemcontrol_clear_BFAR_reg(const void *const hw, hri_systemcontrol_bfar_reg_t mask) |
| 840 | { |
| 841 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 842 | ((Systemcontrol *)hw)->BFAR.reg &= ~mask; |
| 843 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 844 | } |
| 845 | |
| 846 | static inline void hri_systemcontrol_toggle_BFAR_reg(const void *const hw, hri_systemcontrol_bfar_reg_t mask) |
| 847 | { |
| 848 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 849 | ((Systemcontrol *)hw)->BFAR.reg ^= mask; |
| 850 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 851 | } |
| 852 | |
| 853 | static inline hri_systemcontrol_bfar_reg_t hri_systemcontrol_read_BFAR_reg(const void *const hw) |
| 854 | { |
| 855 | return ((Systemcontrol *)hw)->BFAR.reg; |
| 856 | } |
| 857 | |
| 858 | static inline void hri_systemcontrol_set_AFSR_reg(const void *const hw, hri_systemcontrol_afsr_reg_t mask) |
| 859 | { |
| 860 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 861 | ((Systemcontrol *)hw)->AFSR.reg |= mask; |
| 862 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 863 | } |
| 864 | |
| 865 | static inline hri_systemcontrol_afsr_reg_t hri_systemcontrol_get_AFSR_reg(const void *const hw, |
| 866 | hri_systemcontrol_afsr_reg_t mask) |
| 867 | { |
| 868 | uint32_t tmp; |
| 869 | tmp = ((Systemcontrol *)hw)->AFSR.reg; |
| 870 | tmp &= mask; |
| 871 | return tmp; |
| 872 | } |
| 873 | |
| 874 | static inline void hri_systemcontrol_write_AFSR_reg(const void *const hw, hri_systemcontrol_afsr_reg_t data) |
| 875 | { |
| 876 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 877 | ((Systemcontrol *)hw)->AFSR.reg = data; |
| 878 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 879 | } |
| 880 | |
| 881 | static inline void hri_systemcontrol_clear_AFSR_reg(const void *const hw, hri_systemcontrol_afsr_reg_t mask) |
| 882 | { |
| 883 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 884 | ((Systemcontrol *)hw)->AFSR.reg &= ~mask; |
| 885 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 886 | } |
| 887 | |
| 888 | static inline void hri_systemcontrol_toggle_AFSR_reg(const void *const hw, hri_systemcontrol_afsr_reg_t mask) |
| 889 | { |
| 890 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 891 | ((Systemcontrol *)hw)->AFSR.reg ^= mask; |
| 892 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 893 | } |
| 894 | |
| 895 | static inline hri_systemcontrol_afsr_reg_t hri_systemcontrol_read_AFSR_reg(const void *const hw) |
| 896 | { |
| 897 | return ((Systemcontrol *)hw)->AFSR.reg; |
| 898 | } |
| 899 | |
| 900 | static inline void hri_systemcontrol_set_PFR_reg(const void *const hw, uint8_t index, hri_systemcontrol_pfr_reg_t mask) |
| 901 | { |
| 902 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 903 | ((Systemcontrol *)hw)->PFR[index].reg |= mask; |
| 904 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 905 | } |
| 906 | |
| 907 | static inline hri_systemcontrol_pfr_reg_t hri_systemcontrol_get_PFR_reg(const void *const hw, uint8_t index, |
| 908 | hri_systemcontrol_pfr_reg_t mask) |
| 909 | { |
| 910 | uint32_t tmp; |
| 911 | tmp = ((Systemcontrol *)hw)->PFR[index].reg; |
| 912 | tmp &= mask; |
| 913 | return tmp; |
| 914 | } |
| 915 | |
| 916 | static inline void hri_systemcontrol_write_PFR_reg(const void *const hw, uint8_t index, |
| 917 | hri_systemcontrol_pfr_reg_t data) |
| 918 | { |
| 919 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 920 | ((Systemcontrol *)hw)->PFR[index].reg = data; |
| 921 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 922 | } |
| 923 | |
| 924 | static inline void hri_systemcontrol_clear_PFR_reg(const void *const hw, uint8_t index, |
| 925 | hri_systemcontrol_pfr_reg_t mask) |
| 926 | { |
| 927 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 928 | ((Systemcontrol *)hw)->PFR[index].reg &= ~mask; |
| 929 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 930 | } |
| 931 | |
| 932 | static inline void hri_systemcontrol_toggle_PFR_reg(const void *const hw, uint8_t index, |
| 933 | hri_systemcontrol_pfr_reg_t mask) |
| 934 | { |
| 935 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 936 | ((Systemcontrol *)hw)->PFR[index].reg ^= mask; |
| 937 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 938 | } |
| 939 | |
| 940 | static inline hri_systemcontrol_pfr_reg_t hri_systemcontrol_read_PFR_reg(const void *const hw, uint8_t index) |
| 941 | { |
| 942 | return ((Systemcontrol *)hw)->PFR[index].reg; |
| 943 | } |
| 944 | |
| 945 | static inline void hri_systemcontrol_set_CPACR_reg(const void *const hw, hri_systemcontrol_cpacr_reg_t mask) |
| 946 | { |
| 947 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 948 | ((Systemcontrol *)hw)->CPACR.reg |= mask; |
| 949 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 950 | } |
| 951 | |
| 952 | static inline hri_systemcontrol_cpacr_reg_t hri_systemcontrol_get_CPACR_reg(const void *const hw, |
| 953 | hri_systemcontrol_cpacr_reg_t mask) |
| 954 | { |
| 955 | uint32_t tmp; |
| 956 | tmp = ((Systemcontrol *)hw)->CPACR.reg; |
| 957 | tmp &= mask; |
| 958 | return tmp; |
| 959 | } |
| 960 | |
| 961 | static inline void hri_systemcontrol_write_CPACR_reg(const void *const hw, hri_systemcontrol_cpacr_reg_t data) |
| 962 | { |
| 963 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 964 | ((Systemcontrol *)hw)->CPACR.reg = data; |
| 965 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 966 | } |
| 967 | |
| 968 | static inline void hri_systemcontrol_clear_CPACR_reg(const void *const hw, hri_systemcontrol_cpacr_reg_t mask) |
| 969 | { |
| 970 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 971 | ((Systemcontrol *)hw)->CPACR.reg &= ~mask; |
| 972 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 973 | } |
| 974 | |
| 975 | static inline void hri_systemcontrol_toggle_CPACR_reg(const void *const hw, hri_systemcontrol_cpacr_reg_t mask) |
| 976 | { |
| 977 | SystemControl_CRITICAL_SECTION_ENTER(); |
| 978 | ((Systemcontrol *)hw)->CPACR.reg ^= mask; |
| 979 | SystemControl_CRITICAL_SECTION_LEAVE(); |
| 980 | } |
| 981 | |
| 982 | static inline hri_systemcontrol_cpacr_reg_t hri_systemcontrol_read_CPACR_reg(const void *const hw) |
| 983 | { |
| 984 | return ((Systemcontrol *)hw)->CPACR.reg; |
| 985 | } |
| 986 | |
| 987 | #ifdef __cplusplus |
| 988 | } |
| 989 | #endif |
| 990 | |
| 991 | #endif /* _HRI_SystemControl_E54_H_INCLUDED */ |
| 992 | #endif /* _SAME54_SystemControl_COMPONENT_ */ |