Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM ICM |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_ICM_COMPONENT_ |
| 35 | #ifndef _HRI_ICM_E54_H_INCLUDED_ |
| 36 | #define _HRI_ICM_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_ICM_CRITICAL_SECTIONS) |
| 46 | #define ICM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define ICM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define ICM_CRITICAL_SECTION_ENTER() |
| 50 | #define ICM_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint32_t hri_icm_cfg_reg_t; |
| 54 | typedef uint32_t hri_icm_ctrl_reg_t; |
| 55 | typedef uint32_t hri_icm_dscr_reg_t; |
| 56 | typedef uint32_t hri_icm_hash_reg_t; |
| 57 | typedef uint32_t hri_icm_imr_reg_t; |
| 58 | typedef uint32_t hri_icm_isr_reg_t; |
| 59 | typedef uint32_t hri_icm_sr_reg_t; |
| 60 | typedef uint32_t hri_icm_uasr_reg_t; |
| 61 | typedef uint32_t hri_icm_uihval_reg_t; |
| 62 | typedef uint32_t hri_icmdescriptor_raddr_reg_t; |
| 63 | typedef uint32_t hri_icmdescriptor_rcfg_reg_t; |
| 64 | typedef uint32_t hri_icmdescriptor_rctrl_reg_t; |
| 65 | typedef uint32_t hri_icmdescriptor_rnext_reg_t; |
| 66 | |
| 67 | static inline void hri_icmdescriptor_set_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask) |
| 68 | { |
| 69 | ICM_CRITICAL_SECTION_ENTER(); |
| 70 | ((IcmDescriptor *)hw)->RADDR.reg |= mask; |
| 71 | ICM_CRITICAL_SECTION_LEAVE(); |
| 72 | } |
| 73 | |
| 74 | static inline hri_icmdescriptor_raddr_reg_t hri_icmdescriptor_get_RADDR_reg(const void *const hw, |
| 75 | hri_icmdescriptor_raddr_reg_t mask) |
| 76 | { |
| 77 | uint32_t tmp; |
| 78 | tmp = ((IcmDescriptor *)hw)->RADDR.reg; |
| 79 | tmp &= mask; |
| 80 | return tmp; |
| 81 | } |
| 82 | |
| 83 | static inline void hri_icmdescriptor_write_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t data) |
| 84 | { |
| 85 | ICM_CRITICAL_SECTION_ENTER(); |
| 86 | ((IcmDescriptor *)hw)->RADDR.reg = data; |
| 87 | ICM_CRITICAL_SECTION_LEAVE(); |
| 88 | } |
| 89 | |
| 90 | static inline void hri_icmdescriptor_clear_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask) |
| 91 | { |
| 92 | ICM_CRITICAL_SECTION_ENTER(); |
| 93 | ((IcmDescriptor *)hw)->RADDR.reg &= ~mask; |
| 94 | ICM_CRITICAL_SECTION_LEAVE(); |
| 95 | } |
| 96 | |
| 97 | static inline void hri_icmdescriptor_toggle_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask) |
| 98 | { |
| 99 | ICM_CRITICAL_SECTION_ENTER(); |
| 100 | ((IcmDescriptor *)hw)->RADDR.reg ^= mask; |
| 101 | ICM_CRITICAL_SECTION_LEAVE(); |
| 102 | } |
| 103 | |
| 104 | static inline hri_icmdescriptor_raddr_reg_t hri_icmdescriptor_read_RADDR_reg(const void *const hw) |
| 105 | { |
| 106 | return ((IcmDescriptor *)hw)->RADDR.reg; |
| 107 | } |
| 108 | |
| 109 | static inline void hri_icmdescriptor_set_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask) |
| 110 | { |
| 111 | ICM_CRITICAL_SECTION_ENTER(); |
| 112 | ((IcmDescriptor *)hw)->RCFG.reg |= mask; |
| 113 | ICM_CRITICAL_SECTION_LEAVE(); |
| 114 | } |
| 115 | |
| 116 | static inline hri_icmdescriptor_rcfg_reg_t hri_icmdescriptor_get_RCFG_reg(const void *const hw, |
| 117 | hri_icmdescriptor_rcfg_reg_t mask) |
| 118 | { |
| 119 | uint32_t tmp; |
| 120 | tmp = ((IcmDescriptor *)hw)->RCFG.reg; |
| 121 | tmp &= mask; |
| 122 | return tmp; |
| 123 | } |
| 124 | |
| 125 | static inline void hri_icmdescriptor_write_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t data) |
| 126 | { |
| 127 | ICM_CRITICAL_SECTION_ENTER(); |
| 128 | ((IcmDescriptor *)hw)->RCFG.reg = data; |
| 129 | ICM_CRITICAL_SECTION_LEAVE(); |
| 130 | } |
| 131 | |
| 132 | static inline void hri_icmdescriptor_clear_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask) |
| 133 | { |
| 134 | ICM_CRITICAL_SECTION_ENTER(); |
| 135 | ((IcmDescriptor *)hw)->RCFG.reg &= ~mask; |
| 136 | ICM_CRITICAL_SECTION_LEAVE(); |
| 137 | } |
| 138 | |
| 139 | static inline void hri_icmdescriptor_toggle_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask) |
| 140 | { |
| 141 | ICM_CRITICAL_SECTION_ENTER(); |
| 142 | ((IcmDescriptor *)hw)->RCFG.reg ^= mask; |
| 143 | ICM_CRITICAL_SECTION_LEAVE(); |
| 144 | } |
| 145 | |
| 146 | static inline hri_icmdescriptor_rcfg_reg_t hri_icmdescriptor_read_RCFG_reg(const void *const hw) |
| 147 | { |
| 148 | return ((IcmDescriptor *)hw)->RCFG.reg; |
| 149 | } |
| 150 | |
| 151 | static inline void hri_icmdescriptor_set_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask) |
| 152 | { |
| 153 | ICM_CRITICAL_SECTION_ENTER(); |
| 154 | ((IcmDescriptor *)hw)->RCTRL.reg |= mask; |
| 155 | ICM_CRITICAL_SECTION_LEAVE(); |
| 156 | } |
| 157 | |
| 158 | static inline hri_icmdescriptor_rctrl_reg_t hri_icmdescriptor_get_RCTRL_reg(const void *const hw, |
| 159 | hri_icmdescriptor_rctrl_reg_t mask) |
| 160 | { |
| 161 | uint32_t tmp; |
| 162 | tmp = ((IcmDescriptor *)hw)->RCTRL.reg; |
| 163 | tmp &= mask; |
| 164 | return tmp; |
| 165 | } |
| 166 | |
| 167 | static inline void hri_icmdescriptor_write_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t data) |
| 168 | { |
| 169 | ICM_CRITICAL_SECTION_ENTER(); |
| 170 | ((IcmDescriptor *)hw)->RCTRL.reg = data; |
| 171 | ICM_CRITICAL_SECTION_LEAVE(); |
| 172 | } |
| 173 | |
| 174 | static inline void hri_icmdescriptor_clear_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask) |
| 175 | { |
| 176 | ICM_CRITICAL_SECTION_ENTER(); |
| 177 | ((IcmDescriptor *)hw)->RCTRL.reg &= ~mask; |
| 178 | ICM_CRITICAL_SECTION_LEAVE(); |
| 179 | } |
| 180 | |
| 181 | static inline void hri_icmdescriptor_toggle_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask) |
| 182 | { |
| 183 | ICM_CRITICAL_SECTION_ENTER(); |
| 184 | ((IcmDescriptor *)hw)->RCTRL.reg ^= mask; |
| 185 | ICM_CRITICAL_SECTION_LEAVE(); |
| 186 | } |
| 187 | |
| 188 | static inline hri_icmdescriptor_rctrl_reg_t hri_icmdescriptor_read_RCTRL_reg(const void *const hw) |
| 189 | { |
| 190 | return ((IcmDescriptor *)hw)->RCTRL.reg; |
| 191 | } |
| 192 | |
| 193 | static inline void hri_icmdescriptor_set_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask) |
| 194 | { |
| 195 | ICM_CRITICAL_SECTION_ENTER(); |
| 196 | ((IcmDescriptor *)hw)->RNEXT.reg |= mask; |
| 197 | ICM_CRITICAL_SECTION_LEAVE(); |
| 198 | } |
| 199 | |
| 200 | static inline hri_icmdescriptor_rnext_reg_t hri_icmdescriptor_get_RNEXT_reg(const void *const hw, |
| 201 | hri_icmdescriptor_rnext_reg_t mask) |
| 202 | { |
| 203 | uint32_t tmp; |
| 204 | tmp = ((IcmDescriptor *)hw)->RNEXT.reg; |
| 205 | tmp &= mask; |
| 206 | return tmp; |
| 207 | } |
| 208 | |
| 209 | static inline void hri_icmdescriptor_write_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t data) |
| 210 | { |
| 211 | ICM_CRITICAL_SECTION_ENTER(); |
| 212 | ((IcmDescriptor *)hw)->RNEXT.reg = data; |
| 213 | ICM_CRITICAL_SECTION_LEAVE(); |
| 214 | } |
| 215 | |
| 216 | static inline void hri_icmdescriptor_clear_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask) |
| 217 | { |
| 218 | ICM_CRITICAL_SECTION_ENTER(); |
| 219 | ((IcmDescriptor *)hw)->RNEXT.reg &= ~mask; |
| 220 | ICM_CRITICAL_SECTION_LEAVE(); |
| 221 | } |
| 222 | |
| 223 | static inline void hri_icmdescriptor_toggle_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask) |
| 224 | { |
| 225 | ICM_CRITICAL_SECTION_ENTER(); |
| 226 | ((IcmDescriptor *)hw)->RNEXT.reg ^= mask; |
| 227 | ICM_CRITICAL_SECTION_LEAVE(); |
| 228 | } |
| 229 | |
| 230 | static inline hri_icmdescriptor_rnext_reg_t hri_icmdescriptor_read_RNEXT_reg(const void *const hw) |
| 231 | { |
| 232 | return ((IcmDescriptor *)hw)->RNEXT.reg; |
| 233 | } |
| 234 | |
| 235 | static inline void hri_icm_set_IMR_URAD_bit(const void *const hw) |
| 236 | { |
| 237 | ((Icm *)hw)->IER.reg = ICM_IMR_URAD; |
| 238 | } |
| 239 | |
| 240 | static inline bool hri_icm_get_IMR_URAD_bit(const void *const hw) |
| 241 | { |
| 242 | return (((Icm *)hw)->IMR.reg & ICM_IMR_URAD) >> ICM_IMR_URAD_Pos; |
| 243 | } |
| 244 | |
| 245 | static inline void hri_icm_write_IMR_URAD_bit(const void *const hw, bool value) |
| 246 | { |
| 247 | if (value == 0x0) { |
| 248 | ((Icm *)hw)->IDR.reg = ICM_IMR_URAD; |
| 249 | } else { |
| 250 | ((Icm *)hw)->IER.reg = ICM_IMR_URAD; |
| 251 | } |
| 252 | } |
| 253 | |
| 254 | static inline void hri_icm_clear_IMR_URAD_bit(const void *const hw) |
| 255 | { |
| 256 | ((Icm *)hw)->IDR.reg = ICM_IMR_URAD; |
| 257 | } |
| 258 | |
| 259 | static inline void hri_icm_set_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) |
| 260 | { |
| 261 | ((Icm *)hw)->IER.reg = ICM_IMR_RHC(mask); |
| 262 | } |
| 263 | |
| 264 | static inline hri_icm_imr_reg_t hri_icm_get_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) |
| 265 | { |
| 266 | uint32_t tmp; |
| 267 | tmp = ((Icm *)hw)->IMR.reg; |
| 268 | tmp = (tmp & ICM_IMR_RHC(mask)) >> ICM_IMR_RHC_Pos; |
| 269 | return tmp; |
| 270 | } |
| 271 | |
| 272 | static inline hri_icm_imr_reg_t hri_icm_read_IMR_RHC_bf(const void *const hw) |
| 273 | { |
| 274 | uint32_t tmp; |
| 275 | tmp = ((Icm *)hw)->IMR.reg; |
| 276 | tmp = (tmp & ICM_IMR_RHC_Msk) >> ICM_IMR_RHC_Pos; |
| 277 | return tmp; |
| 278 | } |
| 279 | |
| 280 | static inline void hri_icm_write_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t data) |
| 281 | { |
| 282 | ((Icm *)hw)->IER.reg = ICM_IMR_RHC(data); |
| 283 | ((Icm *)hw)->IDR.reg = ~ICM_IMR_RHC(data); |
| 284 | } |
| 285 | |
| 286 | static inline void hri_icm_clear_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) |
| 287 | { |
| 288 | ((Icm *)hw)->IDR.reg = ICM_IMR_RHC(mask); |
| 289 | } |
| 290 | |
| 291 | static inline void hri_icm_set_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) |
| 292 | { |
| 293 | ((Icm *)hw)->IER.reg = ICM_IMR_RDM(mask); |
| 294 | } |
| 295 | |
| 296 | static inline hri_icm_imr_reg_t hri_icm_get_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) |
| 297 | { |
| 298 | uint32_t tmp; |
| 299 | tmp = ((Icm *)hw)->IMR.reg; |
| 300 | tmp = (tmp & ICM_IMR_RDM(mask)) >> ICM_IMR_RDM_Pos; |
| 301 | return tmp; |
| 302 | } |
| 303 | |
| 304 | static inline hri_icm_imr_reg_t hri_icm_read_IMR_RDM_bf(const void *const hw) |
| 305 | { |
| 306 | uint32_t tmp; |
| 307 | tmp = ((Icm *)hw)->IMR.reg; |
| 308 | tmp = (tmp & ICM_IMR_RDM_Msk) >> ICM_IMR_RDM_Pos; |
| 309 | return tmp; |
| 310 | } |
| 311 | |
| 312 | static inline void hri_icm_write_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t data) |
| 313 | { |
| 314 | ((Icm *)hw)->IER.reg = ICM_IMR_RDM(data); |
| 315 | ((Icm *)hw)->IDR.reg = ~ICM_IMR_RDM(data); |
| 316 | } |
| 317 | |
| 318 | static inline void hri_icm_clear_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) |
| 319 | { |
| 320 | ((Icm *)hw)->IDR.reg = ICM_IMR_RDM(mask); |
| 321 | } |
| 322 | |
| 323 | static inline void hri_icm_set_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) |
| 324 | { |
| 325 | ((Icm *)hw)->IER.reg = ICM_IMR_RBE(mask); |
| 326 | } |
| 327 | |
| 328 | static inline hri_icm_imr_reg_t hri_icm_get_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) |
| 329 | { |
| 330 | uint32_t tmp; |
| 331 | tmp = ((Icm *)hw)->IMR.reg; |
| 332 | tmp = (tmp & ICM_IMR_RBE(mask)) >> ICM_IMR_RBE_Pos; |
| 333 | return tmp; |
| 334 | } |
| 335 | |
| 336 | static inline hri_icm_imr_reg_t hri_icm_read_IMR_RBE_bf(const void *const hw) |
| 337 | { |
| 338 | uint32_t tmp; |
| 339 | tmp = ((Icm *)hw)->IMR.reg; |
| 340 | tmp = (tmp & ICM_IMR_RBE_Msk) >> ICM_IMR_RBE_Pos; |
| 341 | return tmp; |
| 342 | } |
| 343 | |
| 344 | static inline void hri_icm_write_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t data) |
| 345 | { |
| 346 | ((Icm *)hw)->IER.reg = ICM_IMR_RBE(data); |
| 347 | ((Icm *)hw)->IDR.reg = ~ICM_IMR_RBE(data); |
| 348 | } |
| 349 | |
| 350 | static inline void hri_icm_clear_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) |
| 351 | { |
| 352 | ((Icm *)hw)->IDR.reg = ICM_IMR_RBE(mask); |
| 353 | } |
| 354 | |
| 355 | static inline void hri_icm_set_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) |
| 356 | { |
| 357 | ((Icm *)hw)->IER.reg = ICM_IMR_RWC(mask); |
| 358 | } |
| 359 | |
| 360 | static inline hri_icm_imr_reg_t hri_icm_get_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) |
| 361 | { |
| 362 | uint32_t tmp; |
| 363 | tmp = ((Icm *)hw)->IMR.reg; |
| 364 | tmp = (tmp & ICM_IMR_RWC(mask)) >> ICM_IMR_RWC_Pos; |
| 365 | return tmp; |
| 366 | } |
| 367 | |
| 368 | static inline hri_icm_imr_reg_t hri_icm_read_IMR_RWC_bf(const void *const hw) |
| 369 | { |
| 370 | uint32_t tmp; |
| 371 | tmp = ((Icm *)hw)->IMR.reg; |
| 372 | tmp = (tmp & ICM_IMR_RWC_Msk) >> ICM_IMR_RWC_Pos; |
| 373 | return tmp; |
| 374 | } |
| 375 | |
| 376 | static inline void hri_icm_write_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t data) |
| 377 | { |
| 378 | ((Icm *)hw)->IER.reg = ICM_IMR_RWC(data); |
| 379 | ((Icm *)hw)->IDR.reg = ~ICM_IMR_RWC(data); |
| 380 | } |
| 381 | |
| 382 | static inline void hri_icm_clear_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) |
| 383 | { |
| 384 | ((Icm *)hw)->IDR.reg = ICM_IMR_RWC(mask); |
| 385 | } |
| 386 | |
| 387 | static inline void hri_icm_set_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) |
| 388 | { |
| 389 | ((Icm *)hw)->IER.reg = ICM_IMR_REC(mask); |
| 390 | } |
| 391 | |
| 392 | static inline hri_icm_imr_reg_t hri_icm_get_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) |
| 393 | { |
| 394 | uint32_t tmp; |
| 395 | tmp = ((Icm *)hw)->IMR.reg; |
| 396 | tmp = (tmp & ICM_IMR_REC(mask)) >> ICM_IMR_REC_Pos; |
| 397 | return tmp; |
| 398 | } |
| 399 | |
| 400 | static inline hri_icm_imr_reg_t hri_icm_read_IMR_REC_bf(const void *const hw) |
| 401 | { |
| 402 | uint32_t tmp; |
| 403 | tmp = ((Icm *)hw)->IMR.reg; |
| 404 | tmp = (tmp & ICM_IMR_REC_Msk) >> ICM_IMR_REC_Pos; |
| 405 | return tmp; |
| 406 | } |
| 407 | |
| 408 | static inline void hri_icm_write_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t data) |
| 409 | { |
| 410 | ((Icm *)hw)->IER.reg = ICM_IMR_REC(data); |
| 411 | ((Icm *)hw)->IDR.reg = ~ICM_IMR_REC(data); |
| 412 | } |
| 413 | |
| 414 | static inline void hri_icm_clear_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) |
| 415 | { |
| 416 | ((Icm *)hw)->IDR.reg = ICM_IMR_REC(mask); |
| 417 | } |
| 418 | |
| 419 | static inline void hri_icm_set_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) |
| 420 | { |
| 421 | ((Icm *)hw)->IER.reg = ICM_IMR_RSU(mask); |
| 422 | } |
| 423 | |
| 424 | static inline hri_icm_imr_reg_t hri_icm_get_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) |
| 425 | { |
| 426 | uint32_t tmp; |
| 427 | tmp = ((Icm *)hw)->IMR.reg; |
| 428 | tmp = (tmp & ICM_IMR_RSU(mask)) >> ICM_IMR_RSU_Pos; |
| 429 | return tmp; |
| 430 | } |
| 431 | |
| 432 | static inline hri_icm_imr_reg_t hri_icm_read_IMR_RSU_bf(const void *const hw) |
| 433 | { |
| 434 | uint32_t tmp; |
| 435 | tmp = ((Icm *)hw)->IMR.reg; |
| 436 | tmp = (tmp & ICM_IMR_RSU_Msk) >> ICM_IMR_RSU_Pos; |
| 437 | return tmp; |
| 438 | } |
| 439 | |
| 440 | static inline void hri_icm_write_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t data) |
| 441 | { |
| 442 | ((Icm *)hw)->IER.reg = ICM_IMR_RSU(data); |
| 443 | ((Icm *)hw)->IDR.reg = ~ICM_IMR_RSU(data); |
| 444 | } |
| 445 | |
| 446 | static inline void hri_icm_clear_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) |
| 447 | { |
| 448 | ((Icm *)hw)->IDR.reg = ICM_IMR_RSU(mask); |
| 449 | } |
| 450 | |
| 451 | static inline void hri_icm_set_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) |
| 452 | { |
| 453 | ((Icm *)hw)->IER.reg = mask; |
| 454 | } |
| 455 | |
| 456 | static inline hri_icm_imr_reg_t hri_icm_get_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) |
| 457 | { |
| 458 | uint32_t tmp; |
| 459 | tmp = ((Icm *)hw)->IMR.reg; |
| 460 | tmp &= mask; |
| 461 | return tmp; |
| 462 | } |
| 463 | |
| 464 | static inline hri_icm_imr_reg_t hri_icm_read_IMR_reg(const void *const hw) |
| 465 | { |
| 466 | return ((Icm *)hw)->IMR.reg; |
| 467 | } |
| 468 | |
| 469 | static inline void hri_icm_write_IMR_reg(const void *const hw, hri_icm_imr_reg_t data) |
| 470 | { |
| 471 | ((Icm *)hw)->IER.reg = data; |
| 472 | ((Icm *)hw)->IDR.reg = ~data; |
| 473 | } |
| 474 | |
| 475 | static inline void hri_icm_clear_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) |
| 476 | { |
| 477 | ((Icm *)hw)->IDR.reg = mask; |
| 478 | } |
| 479 | |
| 480 | static inline bool hri_icm_get_SR_ENABLE_bit(const void *const hw) |
| 481 | { |
| 482 | return (((Icm *)hw)->SR.reg & ICM_SR_ENABLE) >> ICM_SR_ENABLE_Pos; |
| 483 | } |
| 484 | |
| 485 | static inline hri_icm_sr_reg_t hri_icm_get_SR_RAWRMDIS_bf(const void *const hw, hri_icm_sr_reg_t mask) |
| 486 | { |
| 487 | return (((Icm *)hw)->SR.reg & ICM_SR_RAWRMDIS(mask)) >> ICM_SR_RAWRMDIS_Pos; |
| 488 | } |
| 489 | |
| 490 | static inline hri_icm_sr_reg_t hri_icm_read_SR_RAWRMDIS_bf(const void *const hw) |
| 491 | { |
| 492 | return (((Icm *)hw)->SR.reg & ICM_SR_RAWRMDIS_Msk) >> ICM_SR_RAWRMDIS_Pos; |
| 493 | } |
| 494 | |
| 495 | static inline hri_icm_sr_reg_t hri_icm_get_SR_RMDIS_bf(const void *const hw, hri_icm_sr_reg_t mask) |
| 496 | { |
| 497 | return (((Icm *)hw)->SR.reg & ICM_SR_RMDIS(mask)) >> ICM_SR_RMDIS_Pos; |
| 498 | } |
| 499 | |
| 500 | static inline hri_icm_sr_reg_t hri_icm_read_SR_RMDIS_bf(const void *const hw) |
| 501 | { |
| 502 | return (((Icm *)hw)->SR.reg & ICM_SR_RMDIS_Msk) >> ICM_SR_RMDIS_Pos; |
| 503 | } |
| 504 | |
| 505 | static inline hri_icm_sr_reg_t hri_icm_get_SR_reg(const void *const hw, hri_icm_sr_reg_t mask) |
| 506 | { |
| 507 | uint32_t tmp; |
| 508 | tmp = ((Icm *)hw)->SR.reg; |
| 509 | tmp &= mask; |
| 510 | return tmp; |
| 511 | } |
| 512 | |
| 513 | static inline hri_icm_sr_reg_t hri_icm_read_SR_reg(const void *const hw) |
| 514 | { |
| 515 | return ((Icm *)hw)->SR.reg; |
| 516 | } |
| 517 | |
| 518 | static inline bool hri_icm_get_ISR_URAD_bit(const void *const hw) |
| 519 | { |
| 520 | return (((Icm *)hw)->ISR.reg & ICM_ISR_URAD) >> ICM_ISR_URAD_Pos; |
| 521 | } |
| 522 | |
| 523 | static inline hri_icm_isr_reg_t hri_icm_get_ISR_RHC_bf(const void *const hw, hri_icm_isr_reg_t mask) |
| 524 | { |
| 525 | return (((Icm *)hw)->ISR.reg & ICM_ISR_RHC(mask)) >> ICM_ISR_RHC_Pos; |
| 526 | } |
| 527 | |
| 528 | static inline hri_icm_isr_reg_t hri_icm_read_ISR_RHC_bf(const void *const hw) |
| 529 | { |
| 530 | return (((Icm *)hw)->ISR.reg & ICM_ISR_RHC_Msk) >> ICM_ISR_RHC_Pos; |
| 531 | } |
| 532 | |
| 533 | static inline hri_icm_isr_reg_t hri_icm_get_ISR_RDM_bf(const void *const hw, hri_icm_isr_reg_t mask) |
| 534 | { |
| 535 | return (((Icm *)hw)->ISR.reg & ICM_ISR_RDM(mask)) >> ICM_ISR_RDM_Pos; |
| 536 | } |
| 537 | |
| 538 | static inline hri_icm_isr_reg_t hri_icm_read_ISR_RDM_bf(const void *const hw) |
| 539 | { |
| 540 | return (((Icm *)hw)->ISR.reg & ICM_ISR_RDM_Msk) >> ICM_ISR_RDM_Pos; |
| 541 | } |
| 542 | |
| 543 | static inline hri_icm_isr_reg_t hri_icm_get_ISR_RBE_bf(const void *const hw, hri_icm_isr_reg_t mask) |
| 544 | { |
| 545 | return (((Icm *)hw)->ISR.reg & ICM_ISR_RBE(mask)) >> ICM_ISR_RBE_Pos; |
| 546 | } |
| 547 | |
| 548 | static inline hri_icm_isr_reg_t hri_icm_read_ISR_RBE_bf(const void *const hw) |
| 549 | { |
| 550 | return (((Icm *)hw)->ISR.reg & ICM_ISR_RBE_Msk) >> ICM_ISR_RBE_Pos; |
| 551 | } |
| 552 | |
| 553 | static inline hri_icm_isr_reg_t hri_icm_get_ISR_RWC_bf(const void *const hw, hri_icm_isr_reg_t mask) |
| 554 | { |
| 555 | return (((Icm *)hw)->ISR.reg & ICM_ISR_RWC(mask)) >> ICM_ISR_RWC_Pos; |
| 556 | } |
| 557 | |
| 558 | static inline hri_icm_isr_reg_t hri_icm_read_ISR_RWC_bf(const void *const hw) |
| 559 | { |
| 560 | return (((Icm *)hw)->ISR.reg & ICM_ISR_RWC_Msk) >> ICM_ISR_RWC_Pos; |
| 561 | } |
| 562 | |
| 563 | static inline hri_icm_isr_reg_t hri_icm_get_ISR_REC_bf(const void *const hw, hri_icm_isr_reg_t mask) |
| 564 | { |
| 565 | return (((Icm *)hw)->ISR.reg & ICM_ISR_REC(mask)) >> ICM_ISR_REC_Pos; |
| 566 | } |
| 567 | |
| 568 | static inline hri_icm_isr_reg_t hri_icm_read_ISR_REC_bf(const void *const hw) |
| 569 | { |
| 570 | return (((Icm *)hw)->ISR.reg & ICM_ISR_REC_Msk) >> ICM_ISR_REC_Pos; |
| 571 | } |
| 572 | |
| 573 | static inline hri_icm_isr_reg_t hri_icm_get_ISR_RSU_bf(const void *const hw, hri_icm_isr_reg_t mask) |
| 574 | { |
| 575 | return (((Icm *)hw)->ISR.reg & ICM_ISR_RSU(mask)) >> ICM_ISR_RSU_Pos; |
| 576 | } |
| 577 | |
| 578 | static inline hri_icm_isr_reg_t hri_icm_read_ISR_RSU_bf(const void *const hw) |
| 579 | { |
| 580 | return (((Icm *)hw)->ISR.reg & ICM_ISR_RSU_Msk) >> ICM_ISR_RSU_Pos; |
| 581 | } |
| 582 | |
| 583 | static inline hri_icm_isr_reg_t hri_icm_get_ISR_reg(const void *const hw, hri_icm_isr_reg_t mask) |
| 584 | { |
| 585 | uint32_t tmp; |
| 586 | tmp = ((Icm *)hw)->ISR.reg; |
| 587 | tmp &= mask; |
| 588 | return tmp; |
| 589 | } |
| 590 | |
| 591 | static inline hri_icm_isr_reg_t hri_icm_read_ISR_reg(const void *const hw) |
| 592 | { |
| 593 | return ((Icm *)hw)->ISR.reg; |
| 594 | } |
| 595 | |
| 596 | static inline hri_icm_uasr_reg_t hri_icm_get_UASR_URAT_bf(const void *const hw, hri_icm_uasr_reg_t mask) |
| 597 | { |
| 598 | return (((Icm *)hw)->UASR.reg & ICM_UASR_URAT(mask)) >> ICM_UASR_URAT_Pos; |
| 599 | } |
| 600 | |
| 601 | static inline hri_icm_uasr_reg_t hri_icm_read_UASR_URAT_bf(const void *const hw) |
| 602 | { |
| 603 | return (((Icm *)hw)->UASR.reg & ICM_UASR_URAT_Msk) >> ICM_UASR_URAT_Pos; |
| 604 | } |
| 605 | |
| 606 | static inline hri_icm_uasr_reg_t hri_icm_get_UASR_reg(const void *const hw, hri_icm_uasr_reg_t mask) |
| 607 | { |
| 608 | uint32_t tmp; |
| 609 | tmp = ((Icm *)hw)->UASR.reg; |
| 610 | tmp &= mask; |
| 611 | return tmp; |
| 612 | } |
| 613 | |
| 614 | static inline hri_icm_uasr_reg_t hri_icm_read_UASR_reg(const void *const hw) |
| 615 | { |
| 616 | return ((Icm *)hw)->UASR.reg; |
| 617 | } |
| 618 | |
| 619 | static inline void hri_icm_set_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) |
| 620 | { |
| 621 | ICM_CRITICAL_SECTION_ENTER(); |
| 622 | ((Icm *)hw)->CFG.reg |= mask; |
| 623 | ICM_CRITICAL_SECTION_LEAVE(); |
| 624 | } |
| 625 | |
| 626 | static inline hri_icm_cfg_reg_t hri_icm_get_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) |
| 627 | { |
| 628 | uint32_t tmp; |
| 629 | tmp = ((Icm *)hw)->CFG.reg; |
| 630 | tmp &= mask; |
| 631 | return tmp; |
| 632 | } |
| 633 | |
| 634 | static inline void hri_icm_write_CFG_reg(const void *const hw, hri_icm_cfg_reg_t data) |
| 635 | { |
| 636 | ICM_CRITICAL_SECTION_ENTER(); |
| 637 | ((Icm *)hw)->CFG.reg = data; |
| 638 | ICM_CRITICAL_SECTION_LEAVE(); |
| 639 | } |
| 640 | |
| 641 | static inline void hri_icm_clear_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) |
| 642 | { |
| 643 | ICM_CRITICAL_SECTION_ENTER(); |
| 644 | ((Icm *)hw)->CFG.reg &= ~mask; |
| 645 | ICM_CRITICAL_SECTION_LEAVE(); |
| 646 | } |
| 647 | |
| 648 | static inline void hri_icm_toggle_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) |
| 649 | { |
| 650 | ICM_CRITICAL_SECTION_ENTER(); |
| 651 | ((Icm *)hw)->CFG.reg ^= mask; |
| 652 | ICM_CRITICAL_SECTION_LEAVE(); |
| 653 | } |
| 654 | |
| 655 | static inline hri_icm_cfg_reg_t hri_icm_read_CFG_reg(const void *const hw) |
| 656 | { |
| 657 | return ((Icm *)hw)->CFG.reg; |
| 658 | } |
| 659 | |
| 660 | static inline void hri_icm_set_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) |
| 661 | { |
| 662 | ICM_CRITICAL_SECTION_ENTER(); |
| 663 | ((Icm *)hw)->DSCR.reg |= mask; |
| 664 | ICM_CRITICAL_SECTION_LEAVE(); |
| 665 | } |
| 666 | |
| 667 | static inline hri_icm_dscr_reg_t hri_icm_get_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) |
| 668 | { |
| 669 | uint32_t tmp; |
| 670 | tmp = ((Icm *)hw)->DSCR.reg; |
| 671 | tmp &= mask; |
| 672 | return tmp; |
| 673 | } |
| 674 | |
| 675 | static inline void hri_icm_write_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t data) |
| 676 | { |
| 677 | ICM_CRITICAL_SECTION_ENTER(); |
| 678 | ((Icm *)hw)->DSCR.reg = data; |
| 679 | ICM_CRITICAL_SECTION_LEAVE(); |
| 680 | } |
| 681 | |
| 682 | static inline void hri_icm_clear_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) |
| 683 | { |
| 684 | ICM_CRITICAL_SECTION_ENTER(); |
| 685 | ((Icm *)hw)->DSCR.reg &= ~mask; |
| 686 | ICM_CRITICAL_SECTION_LEAVE(); |
| 687 | } |
| 688 | |
| 689 | static inline void hri_icm_toggle_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) |
| 690 | { |
| 691 | ICM_CRITICAL_SECTION_ENTER(); |
| 692 | ((Icm *)hw)->DSCR.reg ^= mask; |
| 693 | ICM_CRITICAL_SECTION_LEAVE(); |
| 694 | } |
| 695 | |
| 696 | static inline hri_icm_dscr_reg_t hri_icm_read_DSCR_reg(const void *const hw) |
| 697 | { |
| 698 | return ((Icm *)hw)->DSCR.reg; |
| 699 | } |
| 700 | |
| 701 | static inline void hri_icm_set_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) |
| 702 | { |
| 703 | ICM_CRITICAL_SECTION_ENTER(); |
| 704 | ((Icm *)hw)->HASH.reg |= mask; |
| 705 | ICM_CRITICAL_SECTION_LEAVE(); |
| 706 | } |
| 707 | |
| 708 | static inline hri_icm_hash_reg_t hri_icm_get_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) |
| 709 | { |
| 710 | uint32_t tmp; |
| 711 | tmp = ((Icm *)hw)->HASH.reg; |
| 712 | tmp &= mask; |
| 713 | return tmp; |
| 714 | } |
| 715 | |
| 716 | static inline void hri_icm_write_HASH_reg(const void *const hw, hri_icm_hash_reg_t data) |
| 717 | { |
| 718 | ICM_CRITICAL_SECTION_ENTER(); |
| 719 | ((Icm *)hw)->HASH.reg = data; |
| 720 | ICM_CRITICAL_SECTION_LEAVE(); |
| 721 | } |
| 722 | |
| 723 | static inline void hri_icm_clear_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) |
| 724 | { |
| 725 | ICM_CRITICAL_SECTION_ENTER(); |
| 726 | ((Icm *)hw)->HASH.reg &= ~mask; |
| 727 | ICM_CRITICAL_SECTION_LEAVE(); |
| 728 | } |
| 729 | |
| 730 | static inline void hri_icm_toggle_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) |
| 731 | { |
| 732 | ICM_CRITICAL_SECTION_ENTER(); |
| 733 | ((Icm *)hw)->HASH.reg ^= mask; |
| 734 | ICM_CRITICAL_SECTION_LEAVE(); |
| 735 | } |
| 736 | |
| 737 | static inline hri_icm_hash_reg_t hri_icm_read_HASH_reg(const void *const hw) |
| 738 | { |
| 739 | return ((Icm *)hw)->HASH.reg; |
| 740 | } |
| 741 | |
| 742 | static inline void hri_icm_write_CTRL_reg(const void *const hw, hri_icm_ctrl_reg_t data) |
| 743 | { |
| 744 | ICM_CRITICAL_SECTION_ENTER(); |
| 745 | ((Icm *)hw)->CTRL.reg = data; |
| 746 | ICM_CRITICAL_SECTION_LEAVE(); |
| 747 | } |
| 748 | |
| 749 | static inline void hri_icm_write_UIHVAL_reg(const void *const hw, uint8_t index, hri_icm_uihval_reg_t data) |
| 750 | { |
| 751 | ICM_CRITICAL_SECTION_ENTER(); |
| 752 | ((Icm *)hw)->UIHVAL[index].reg = data; |
| 753 | ICM_CRITICAL_SECTION_LEAVE(); |
| 754 | } |
| 755 | |
| 756 | #ifdef __cplusplus |
| 757 | } |
| 758 | #endif |
| 759 | |
| 760 | #endif /* _HRI_ICM_E54_H_INCLUDED */ |
| 761 | #endif /* _SAME54_ICM_COMPONENT_ */ |