Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM DMAC |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_DMAC_COMPONENT_ |
| 35 | #ifndef _HRI_DMAC_E54_H_INCLUDED_ |
| 36 | #define _HRI_DMAC_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_DMAC_CRITICAL_SECTIONS) |
| 46 | #define DMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define DMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define DMAC_CRITICAL_SECTION_ENTER() |
| 50 | #define DMAC_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint16_t hri_dmac_crcctrl_reg_t; |
| 54 | typedef uint16_t hri_dmac_ctrl_reg_t; |
| 55 | typedef uint16_t hri_dmac_intpend_reg_t; |
| 56 | typedef uint16_t hri_dmacdescriptor_btcnt_reg_t; |
| 57 | typedef uint16_t hri_dmacdescriptor_btctrl_reg_t; |
| 58 | typedef uint32_t hri_dmac_active_reg_t; |
| 59 | typedef uint32_t hri_dmac_baseaddr_reg_t; |
| 60 | typedef uint32_t hri_dmac_busych_reg_t; |
| 61 | typedef uint32_t hri_dmac_chctrla_reg_t; |
| 62 | typedef uint32_t hri_dmac_crcchksum_reg_t; |
| 63 | typedef uint32_t hri_dmac_crcdatain_reg_t; |
| 64 | typedef uint32_t hri_dmac_intstatus_reg_t; |
| 65 | typedef uint32_t hri_dmac_pendch_reg_t; |
| 66 | typedef uint32_t hri_dmac_prictrl0_reg_t; |
| 67 | typedef uint32_t hri_dmac_swtrigctrl_reg_t; |
| 68 | typedef uint32_t hri_dmac_wrbaddr_reg_t; |
| 69 | typedef uint32_t hri_dmacchannel_chctrla_reg_t; |
| 70 | typedef uint32_t hri_dmacdescriptor_descaddr_reg_t; |
| 71 | typedef uint32_t hri_dmacdescriptor_dstaddr_reg_t; |
| 72 | typedef uint32_t hri_dmacdescriptor_srcaddr_reg_t; |
| 73 | typedef uint8_t hri_dmac_chctrlb_reg_t; |
| 74 | typedef uint8_t hri_dmac_chevctrl_reg_t; |
| 75 | typedef uint8_t hri_dmac_chintenset_reg_t; |
| 76 | typedef uint8_t hri_dmac_chintflag_reg_t; |
| 77 | typedef uint8_t hri_dmac_chprilvl_reg_t; |
| 78 | typedef uint8_t hri_dmac_chstatus_reg_t; |
| 79 | typedef uint8_t hri_dmac_crcstatus_reg_t; |
| 80 | typedef uint8_t hri_dmac_dbgctrl_reg_t; |
| 81 | typedef uint8_t hri_dmacchannel_chctrlb_reg_t; |
| 82 | typedef uint8_t hri_dmacchannel_chevctrl_reg_t; |
| 83 | typedef uint8_t hri_dmacchannel_chintenset_reg_t; |
| 84 | typedef uint8_t hri_dmacchannel_chintflag_reg_t; |
| 85 | typedef uint8_t hri_dmacchannel_chprilvl_reg_t; |
| 86 | typedef uint8_t hri_dmacchannel_chstatus_reg_t; |
| 87 | |
| 88 | static inline bool hri_dmac_get_INTSTATUS_CHINT0_bit(const void *const hw) |
| 89 | { |
| 90 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0) >> DMAC_INTSTATUS_CHINT0_Pos; |
| 91 | } |
| 92 | |
| 93 | static inline bool hri_dmac_get_INTSTATUS_CHINT1_bit(const void *const hw) |
| 94 | { |
| 95 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1) >> DMAC_INTSTATUS_CHINT1_Pos; |
| 96 | } |
| 97 | |
| 98 | static inline bool hri_dmac_get_INTSTATUS_CHINT2_bit(const void *const hw) |
| 99 | { |
| 100 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2) >> DMAC_INTSTATUS_CHINT2_Pos; |
| 101 | } |
| 102 | |
| 103 | static inline bool hri_dmac_get_INTSTATUS_CHINT3_bit(const void *const hw) |
| 104 | { |
| 105 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3) >> DMAC_INTSTATUS_CHINT3_Pos; |
| 106 | } |
| 107 | |
| 108 | static inline bool hri_dmac_get_INTSTATUS_CHINT4_bit(const void *const hw) |
| 109 | { |
| 110 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4) >> DMAC_INTSTATUS_CHINT4_Pos; |
| 111 | } |
| 112 | |
| 113 | static inline bool hri_dmac_get_INTSTATUS_CHINT5_bit(const void *const hw) |
| 114 | { |
| 115 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5) >> DMAC_INTSTATUS_CHINT5_Pos; |
| 116 | } |
| 117 | |
| 118 | static inline bool hri_dmac_get_INTSTATUS_CHINT6_bit(const void *const hw) |
| 119 | { |
| 120 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6) >> DMAC_INTSTATUS_CHINT6_Pos; |
| 121 | } |
| 122 | |
| 123 | static inline bool hri_dmac_get_INTSTATUS_CHINT7_bit(const void *const hw) |
| 124 | { |
| 125 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7) >> DMAC_INTSTATUS_CHINT7_Pos; |
| 126 | } |
| 127 | |
| 128 | static inline bool hri_dmac_get_INTSTATUS_CHINT8_bit(const void *const hw) |
| 129 | { |
| 130 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT8) >> DMAC_INTSTATUS_CHINT8_Pos; |
| 131 | } |
| 132 | |
| 133 | static inline bool hri_dmac_get_INTSTATUS_CHINT9_bit(const void *const hw) |
| 134 | { |
| 135 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT9) >> DMAC_INTSTATUS_CHINT9_Pos; |
| 136 | } |
| 137 | |
| 138 | static inline bool hri_dmac_get_INTSTATUS_CHINT10_bit(const void *const hw) |
| 139 | { |
| 140 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT10) >> DMAC_INTSTATUS_CHINT10_Pos; |
| 141 | } |
| 142 | |
| 143 | static inline bool hri_dmac_get_INTSTATUS_CHINT11_bit(const void *const hw) |
| 144 | { |
| 145 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT11) >> DMAC_INTSTATUS_CHINT11_Pos; |
| 146 | } |
| 147 | |
| 148 | static inline bool hri_dmac_get_INTSTATUS_CHINT12_bit(const void *const hw) |
| 149 | { |
| 150 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT12) >> DMAC_INTSTATUS_CHINT12_Pos; |
| 151 | } |
| 152 | |
| 153 | static inline bool hri_dmac_get_INTSTATUS_CHINT13_bit(const void *const hw) |
| 154 | { |
| 155 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT13) >> DMAC_INTSTATUS_CHINT13_Pos; |
| 156 | } |
| 157 | |
| 158 | static inline bool hri_dmac_get_INTSTATUS_CHINT14_bit(const void *const hw) |
| 159 | { |
| 160 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT14) >> DMAC_INTSTATUS_CHINT14_Pos; |
| 161 | } |
| 162 | |
| 163 | static inline bool hri_dmac_get_INTSTATUS_CHINT15_bit(const void *const hw) |
| 164 | { |
| 165 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT15) >> DMAC_INTSTATUS_CHINT15_Pos; |
| 166 | } |
| 167 | |
| 168 | static inline bool hri_dmac_get_INTSTATUS_CHINT16_bit(const void *const hw) |
| 169 | { |
| 170 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT16) >> DMAC_INTSTATUS_CHINT16_Pos; |
| 171 | } |
| 172 | |
| 173 | static inline bool hri_dmac_get_INTSTATUS_CHINT17_bit(const void *const hw) |
| 174 | { |
| 175 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT17) >> DMAC_INTSTATUS_CHINT17_Pos; |
| 176 | } |
| 177 | |
| 178 | static inline bool hri_dmac_get_INTSTATUS_CHINT18_bit(const void *const hw) |
| 179 | { |
| 180 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT18) >> DMAC_INTSTATUS_CHINT18_Pos; |
| 181 | } |
| 182 | |
| 183 | static inline bool hri_dmac_get_INTSTATUS_CHINT19_bit(const void *const hw) |
| 184 | { |
| 185 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT19) >> DMAC_INTSTATUS_CHINT19_Pos; |
| 186 | } |
| 187 | |
| 188 | static inline bool hri_dmac_get_INTSTATUS_CHINT20_bit(const void *const hw) |
| 189 | { |
| 190 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT20) >> DMAC_INTSTATUS_CHINT20_Pos; |
| 191 | } |
| 192 | |
| 193 | static inline bool hri_dmac_get_INTSTATUS_CHINT21_bit(const void *const hw) |
| 194 | { |
| 195 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT21) >> DMAC_INTSTATUS_CHINT21_Pos; |
| 196 | } |
| 197 | |
| 198 | static inline bool hri_dmac_get_INTSTATUS_CHINT22_bit(const void *const hw) |
| 199 | { |
| 200 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT22) >> DMAC_INTSTATUS_CHINT22_Pos; |
| 201 | } |
| 202 | |
| 203 | static inline bool hri_dmac_get_INTSTATUS_CHINT23_bit(const void *const hw) |
| 204 | { |
| 205 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT23) >> DMAC_INTSTATUS_CHINT23_Pos; |
| 206 | } |
| 207 | |
| 208 | static inline bool hri_dmac_get_INTSTATUS_CHINT24_bit(const void *const hw) |
| 209 | { |
| 210 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT24) >> DMAC_INTSTATUS_CHINT24_Pos; |
| 211 | } |
| 212 | |
| 213 | static inline bool hri_dmac_get_INTSTATUS_CHINT25_bit(const void *const hw) |
| 214 | { |
| 215 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT25) >> DMAC_INTSTATUS_CHINT25_Pos; |
| 216 | } |
| 217 | |
| 218 | static inline bool hri_dmac_get_INTSTATUS_CHINT26_bit(const void *const hw) |
| 219 | { |
| 220 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT26) >> DMAC_INTSTATUS_CHINT26_Pos; |
| 221 | } |
| 222 | |
| 223 | static inline bool hri_dmac_get_INTSTATUS_CHINT27_bit(const void *const hw) |
| 224 | { |
| 225 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT27) >> DMAC_INTSTATUS_CHINT27_Pos; |
| 226 | } |
| 227 | |
| 228 | static inline bool hri_dmac_get_INTSTATUS_CHINT28_bit(const void *const hw) |
| 229 | { |
| 230 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT28) >> DMAC_INTSTATUS_CHINT28_Pos; |
| 231 | } |
| 232 | |
| 233 | static inline bool hri_dmac_get_INTSTATUS_CHINT29_bit(const void *const hw) |
| 234 | { |
| 235 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT29) >> DMAC_INTSTATUS_CHINT29_Pos; |
| 236 | } |
| 237 | |
| 238 | static inline bool hri_dmac_get_INTSTATUS_CHINT30_bit(const void *const hw) |
| 239 | { |
| 240 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT30) >> DMAC_INTSTATUS_CHINT30_Pos; |
| 241 | } |
| 242 | |
| 243 | static inline bool hri_dmac_get_INTSTATUS_CHINT31_bit(const void *const hw) |
| 244 | { |
| 245 | return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT31) >> DMAC_INTSTATUS_CHINT31_Pos; |
| 246 | } |
| 247 | |
| 248 | static inline hri_dmac_intstatus_reg_t hri_dmac_get_INTSTATUS_reg(const void *const hw, hri_dmac_intstatus_reg_t mask) |
| 249 | { |
| 250 | uint32_t tmp; |
| 251 | tmp = ((Dmac *)hw)->INTSTATUS.reg; |
| 252 | tmp &= mask; |
| 253 | return tmp; |
| 254 | } |
| 255 | |
| 256 | static inline hri_dmac_intstatus_reg_t hri_dmac_read_INTSTATUS_reg(const void *const hw) |
| 257 | { |
| 258 | return ((Dmac *)hw)->INTSTATUS.reg; |
| 259 | } |
| 260 | |
| 261 | static inline bool hri_dmac_get_BUSYCH_BUSYCH0_bit(const void *const hw) |
| 262 | { |
| 263 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH0) >> DMAC_BUSYCH_BUSYCH0_Pos; |
| 264 | } |
| 265 | |
| 266 | static inline bool hri_dmac_get_BUSYCH_BUSYCH1_bit(const void *const hw) |
| 267 | { |
| 268 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH1) >> DMAC_BUSYCH_BUSYCH1_Pos; |
| 269 | } |
| 270 | |
| 271 | static inline bool hri_dmac_get_BUSYCH_BUSYCH2_bit(const void *const hw) |
| 272 | { |
| 273 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH2) >> DMAC_BUSYCH_BUSYCH2_Pos; |
| 274 | } |
| 275 | |
| 276 | static inline bool hri_dmac_get_BUSYCH_BUSYCH3_bit(const void *const hw) |
| 277 | { |
| 278 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH3) >> DMAC_BUSYCH_BUSYCH3_Pos; |
| 279 | } |
| 280 | |
| 281 | static inline bool hri_dmac_get_BUSYCH_BUSYCH4_bit(const void *const hw) |
| 282 | { |
| 283 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH4) >> DMAC_BUSYCH_BUSYCH4_Pos; |
| 284 | } |
| 285 | |
| 286 | static inline bool hri_dmac_get_BUSYCH_BUSYCH5_bit(const void *const hw) |
| 287 | { |
| 288 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH5) >> DMAC_BUSYCH_BUSYCH5_Pos; |
| 289 | } |
| 290 | |
| 291 | static inline bool hri_dmac_get_BUSYCH_BUSYCH6_bit(const void *const hw) |
| 292 | { |
| 293 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH6) >> DMAC_BUSYCH_BUSYCH6_Pos; |
| 294 | } |
| 295 | |
| 296 | static inline bool hri_dmac_get_BUSYCH_BUSYCH7_bit(const void *const hw) |
| 297 | { |
| 298 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH7) >> DMAC_BUSYCH_BUSYCH7_Pos; |
| 299 | } |
| 300 | |
| 301 | static inline bool hri_dmac_get_BUSYCH_BUSYCH8_bit(const void *const hw) |
| 302 | { |
| 303 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH8) >> DMAC_BUSYCH_BUSYCH8_Pos; |
| 304 | } |
| 305 | |
| 306 | static inline bool hri_dmac_get_BUSYCH_BUSYCH9_bit(const void *const hw) |
| 307 | { |
| 308 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH9) >> DMAC_BUSYCH_BUSYCH9_Pos; |
| 309 | } |
| 310 | |
| 311 | static inline bool hri_dmac_get_BUSYCH_BUSYCH10_bit(const void *const hw) |
| 312 | { |
| 313 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH10) >> DMAC_BUSYCH_BUSYCH10_Pos; |
| 314 | } |
| 315 | |
| 316 | static inline bool hri_dmac_get_BUSYCH_BUSYCH11_bit(const void *const hw) |
| 317 | { |
| 318 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH11) >> DMAC_BUSYCH_BUSYCH11_Pos; |
| 319 | } |
| 320 | |
| 321 | static inline bool hri_dmac_get_BUSYCH_BUSYCH12_bit(const void *const hw) |
| 322 | { |
| 323 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH12) >> DMAC_BUSYCH_BUSYCH12_Pos; |
| 324 | } |
| 325 | |
| 326 | static inline bool hri_dmac_get_BUSYCH_BUSYCH13_bit(const void *const hw) |
| 327 | { |
| 328 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH13) >> DMAC_BUSYCH_BUSYCH13_Pos; |
| 329 | } |
| 330 | |
| 331 | static inline bool hri_dmac_get_BUSYCH_BUSYCH14_bit(const void *const hw) |
| 332 | { |
| 333 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH14) >> DMAC_BUSYCH_BUSYCH14_Pos; |
| 334 | } |
| 335 | |
| 336 | static inline bool hri_dmac_get_BUSYCH_BUSYCH15_bit(const void *const hw) |
| 337 | { |
| 338 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH15) >> DMAC_BUSYCH_BUSYCH15_Pos; |
| 339 | } |
| 340 | |
| 341 | static inline bool hri_dmac_get_BUSYCH_BUSYCH16_bit(const void *const hw) |
| 342 | { |
| 343 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH16) >> DMAC_BUSYCH_BUSYCH16_Pos; |
| 344 | } |
| 345 | |
| 346 | static inline bool hri_dmac_get_BUSYCH_BUSYCH17_bit(const void *const hw) |
| 347 | { |
| 348 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH17) >> DMAC_BUSYCH_BUSYCH17_Pos; |
| 349 | } |
| 350 | |
| 351 | static inline bool hri_dmac_get_BUSYCH_BUSYCH18_bit(const void *const hw) |
| 352 | { |
| 353 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH18) >> DMAC_BUSYCH_BUSYCH18_Pos; |
| 354 | } |
| 355 | |
| 356 | static inline bool hri_dmac_get_BUSYCH_BUSYCH19_bit(const void *const hw) |
| 357 | { |
| 358 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH19) >> DMAC_BUSYCH_BUSYCH19_Pos; |
| 359 | } |
| 360 | |
| 361 | static inline bool hri_dmac_get_BUSYCH_BUSYCH20_bit(const void *const hw) |
| 362 | { |
| 363 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH20) >> DMAC_BUSYCH_BUSYCH20_Pos; |
| 364 | } |
| 365 | |
| 366 | static inline bool hri_dmac_get_BUSYCH_BUSYCH21_bit(const void *const hw) |
| 367 | { |
| 368 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH21) >> DMAC_BUSYCH_BUSYCH21_Pos; |
| 369 | } |
| 370 | |
| 371 | static inline bool hri_dmac_get_BUSYCH_BUSYCH22_bit(const void *const hw) |
| 372 | { |
| 373 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH22) >> DMAC_BUSYCH_BUSYCH22_Pos; |
| 374 | } |
| 375 | |
| 376 | static inline bool hri_dmac_get_BUSYCH_BUSYCH23_bit(const void *const hw) |
| 377 | { |
| 378 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH23) >> DMAC_BUSYCH_BUSYCH23_Pos; |
| 379 | } |
| 380 | |
| 381 | static inline bool hri_dmac_get_BUSYCH_BUSYCH24_bit(const void *const hw) |
| 382 | { |
| 383 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH24) >> DMAC_BUSYCH_BUSYCH24_Pos; |
| 384 | } |
| 385 | |
| 386 | static inline bool hri_dmac_get_BUSYCH_BUSYCH25_bit(const void *const hw) |
| 387 | { |
| 388 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH25) >> DMAC_BUSYCH_BUSYCH25_Pos; |
| 389 | } |
| 390 | |
| 391 | static inline bool hri_dmac_get_BUSYCH_BUSYCH26_bit(const void *const hw) |
| 392 | { |
| 393 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH26) >> DMAC_BUSYCH_BUSYCH26_Pos; |
| 394 | } |
| 395 | |
| 396 | static inline bool hri_dmac_get_BUSYCH_BUSYCH27_bit(const void *const hw) |
| 397 | { |
| 398 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH27) >> DMAC_BUSYCH_BUSYCH27_Pos; |
| 399 | } |
| 400 | |
| 401 | static inline bool hri_dmac_get_BUSYCH_BUSYCH28_bit(const void *const hw) |
| 402 | { |
| 403 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH28) >> DMAC_BUSYCH_BUSYCH28_Pos; |
| 404 | } |
| 405 | |
| 406 | static inline bool hri_dmac_get_BUSYCH_BUSYCH29_bit(const void *const hw) |
| 407 | { |
| 408 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH29) >> DMAC_BUSYCH_BUSYCH29_Pos; |
| 409 | } |
| 410 | |
| 411 | static inline bool hri_dmac_get_BUSYCH_BUSYCH30_bit(const void *const hw) |
| 412 | { |
| 413 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH30) >> DMAC_BUSYCH_BUSYCH30_Pos; |
| 414 | } |
| 415 | |
| 416 | static inline bool hri_dmac_get_BUSYCH_BUSYCH31_bit(const void *const hw) |
| 417 | { |
| 418 | return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH31) >> DMAC_BUSYCH_BUSYCH31_Pos; |
| 419 | } |
| 420 | |
| 421 | static inline hri_dmac_busych_reg_t hri_dmac_get_BUSYCH_reg(const void *const hw, hri_dmac_busych_reg_t mask) |
| 422 | { |
| 423 | uint32_t tmp; |
| 424 | tmp = ((Dmac *)hw)->BUSYCH.reg; |
| 425 | tmp &= mask; |
| 426 | return tmp; |
| 427 | } |
| 428 | |
| 429 | static inline hri_dmac_busych_reg_t hri_dmac_read_BUSYCH_reg(const void *const hw) |
| 430 | { |
| 431 | return ((Dmac *)hw)->BUSYCH.reg; |
| 432 | } |
| 433 | |
| 434 | static inline bool hri_dmac_get_PENDCH_PENDCH0_bit(const void *const hw) |
| 435 | { |
| 436 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH0) >> DMAC_PENDCH_PENDCH0_Pos; |
| 437 | } |
| 438 | |
| 439 | static inline bool hri_dmac_get_PENDCH_PENDCH1_bit(const void *const hw) |
| 440 | { |
| 441 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH1) >> DMAC_PENDCH_PENDCH1_Pos; |
| 442 | } |
| 443 | |
| 444 | static inline bool hri_dmac_get_PENDCH_PENDCH2_bit(const void *const hw) |
| 445 | { |
| 446 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH2) >> DMAC_PENDCH_PENDCH2_Pos; |
| 447 | } |
| 448 | |
| 449 | static inline bool hri_dmac_get_PENDCH_PENDCH3_bit(const void *const hw) |
| 450 | { |
| 451 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH3) >> DMAC_PENDCH_PENDCH3_Pos; |
| 452 | } |
| 453 | |
| 454 | static inline bool hri_dmac_get_PENDCH_PENDCH4_bit(const void *const hw) |
| 455 | { |
| 456 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH4) >> DMAC_PENDCH_PENDCH4_Pos; |
| 457 | } |
| 458 | |
| 459 | static inline bool hri_dmac_get_PENDCH_PENDCH5_bit(const void *const hw) |
| 460 | { |
| 461 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH5) >> DMAC_PENDCH_PENDCH5_Pos; |
| 462 | } |
| 463 | |
| 464 | static inline bool hri_dmac_get_PENDCH_PENDCH6_bit(const void *const hw) |
| 465 | { |
| 466 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH6) >> DMAC_PENDCH_PENDCH6_Pos; |
| 467 | } |
| 468 | |
| 469 | static inline bool hri_dmac_get_PENDCH_PENDCH7_bit(const void *const hw) |
| 470 | { |
| 471 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH7) >> DMAC_PENDCH_PENDCH7_Pos; |
| 472 | } |
| 473 | |
| 474 | static inline bool hri_dmac_get_PENDCH_PENDCH8_bit(const void *const hw) |
| 475 | { |
| 476 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH8) >> DMAC_PENDCH_PENDCH8_Pos; |
| 477 | } |
| 478 | |
| 479 | static inline bool hri_dmac_get_PENDCH_PENDCH9_bit(const void *const hw) |
| 480 | { |
| 481 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH9) >> DMAC_PENDCH_PENDCH9_Pos; |
| 482 | } |
| 483 | |
| 484 | static inline bool hri_dmac_get_PENDCH_PENDCH10_bit(const void *const hw) |
| 485 | { |
| 486 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH10) >> DMAC_PENDCH_PENDCH10_Pos; |
| 487 | } |
| 488 | |
| 489 | static inline bool hri_dmac_get_PENDCH_PENDCH11_bit(const void *const hw) |
| 490 | { |
| 491 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH11) >> DMAC_PENDCH_PENDCH11_Pos; |
| 492 | } |
| 493 | |
| 494 | static inline bool hri_dmac_get_PENDCH_PENDCH12_bit(const void *const hw) |
| 495 | { |
| 496 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH12) >> DMAC_PENDCH_PENDCH12_Pos; |
| 497 | } |
| 498 | |
| 499 | static inline bool hri_dmac_get_PENDCH_PENDCH13_bit(const void *const hw) |
| 500 | { |
| 501 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH13) >> DMAC_PENDCH_PENDCH13_Pos; |
| 502 | } |
| 503 | |
| 504 | static inline bool hri_dmac_get_PENDCH_PENDCH14_bit(const void *const hw) |
| 505 | { |
| 506 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH14) >> DMAC_PENDCH_PENDCH14_Pos; |
| 507 | } |
| 508 | |
| 509 | static inline bool hri_dmac_get_PENDCH_PENDCH15_bit(const void *const hw) |
| 510 | { |
| 511 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH15) >> DMAC_PENDCH_PENDCH15_Pos; |
| 512 | } |
| 513 | |
| 514 | static inline bool hri_dmac_get_PENDCH_PENDCH16_bit(const void *const hw) |
| 515 | { |
| 516 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH16) >> DMAC_PENDCH_PENDCH16_Pos; |
| 517 | } |
| 518 | |
| 519 | static inline bool hri_dmac_get_PENDCH_PENDCH17_bit(const void *const hw) |
| 520 | { |
| 521 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH17) >> DMAC_PENDCH_PENDCH17_Pos; |
| 522 | } |
| 523 | |
| 524 | static inline bool hri_dmac_get_PENDCH_PENDCH18_bit(const void *const hw) |
| 525 | { |
| 526 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH18) >> DMAC_PENDCH_PENDCH18_Pos; |
| 527 | } |
| 528 | |
| 529 | static inline bool hri_dmac_get_PENDCH_PENDCH19_bit(const void *const hw) |
| 530 | { |
| 531 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH19) >> DMAC_PENDCH_PENDCH19_Pos; |
| 532 | } |
| 533 | |
| 534 | static inline bool hri_dmac_get_PENDCH_PENDCH20_bit(const void *const hw) |
| 535 | { |
| 536 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH20) >> DMAC_PENDCH_PENDCH20_Pos; |
| 537 | } |
| 538 | |
| 539 | static inline bool hri_dmac_get_PENDCH_PENDCH21_bit(const void *const hw) |
| 540 | { |
| 541 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH21) >> DMAC_PENDCH_PENDCH21_Pos; |
| 542 | } |
| 543 | |
| 544 | static inline bool hri_dmac_get_PENDCH_PENDCH22_bit(const void *const hw) |
| 545 | { |
| 546 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH22) >> DMAC_PENDCH_PENDCH22_Pos; |
| 547 | } |
| 548 | |
| 549 | static inline bool hri_dmac_get_PENDCH_PENDCH23_bit(const void *const hw) |
| 550 | { |
| 551 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH23) >> DMAC_PENDCH_PENDCH23_Pos; |
| 552 | } |
| 553 | |
| 554 | static inline bool hri_dmac_get_PENDCH_PENDCH24_bit(const void *const hw) |
| 555 | { |
| 556 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH24) >> DMAC_PENDCH_PENDCH24_Pos; |
| 557 | } |
| 558 | |
| 559 | static inline bool hri_dmac_get_PENDCH_PENDCH25_bit(const void *const hw) |
| 560 | { |
| 561 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH25) >> DMAC_PENDCH_PENDCH25_Pos; |
| 562 | } |
| 563 | |
| 564 | static inline bool hri_dmac_get_PENDCH_PENDCH26_bit(const void *const hw) |
| 565 | { |
| 566 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH26) >> DMAC_PENDCH_PENDCH26_Pos; |
| 567 | } |
| 568 | |
| 569 | static inline bool hri_dmac_get_PENDCH_PENDCH27_bit(const void *const hw) |
| 570 | { |
| 571 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH27) >> DMAC_PENDCH_PENDCH27_Pos; |
| 572 | } |
| 573 | |
| 574 | static inline bool hri_dmac_get_PENDCH_PENDCH28_bit(const void *const hw) |
| 575 | { |
| 576 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH28) >> DMAC_PENDCH_PENDCH28_Pos; |
| 577 | } |
| 578 | |
| 579 | static inline bool hri_dmac_get_PENDCH_PENDCH29_bit(const void *const hw) |
| 580 | { |
| 581 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH29) >> DMAC_PENDCH_PENDCH29_Pos; |
| 582 | } |
| 583 | |
| 584 | static inline bool hri_dmac_get_PENDCH_PENDCH30_bit(const void *const hw) |
| 585 | { |
| 586 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH30) >> DMAC_PENDCH_PENDCH30_Pos; |
| 587 | } |
| 588 | |
| 589 | static inline bool hri_dmac_get_PENDCH_PENDCH31_bit(const void *const hw) |
| 590 | { |
| 591 | return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH31) >> DMAC_PENDCH_PENDCH31_Pos; |
| 592 | } |
| 593 | |
| 594 | static inline hri_dmac_pendch_reg_t hri_dmac_get_PENDCH_reg(const void *const hw, hri_dmac_pendch_reg_t mask) |
| 595 | { |
| 596 | uint32_t tmp; |
| 597 | tmp = ((Dmac *)hw)->PENDCH.reg; |
| 598 | tmp &= mask; |
| 599 | return tmp; |
| 600 | } |
| 601 | |
| 602 | static inline hri_dmac_pendch_reg_t hri_dmac_read_PENDCH_reg(const void *const hw) |
| 603 | { |
| 604 | return ((Dmac *)hw)->PENDCH.reg; |
| 605 | } |
| 606 | |
| 607 | static inline bool hri_dmac_get_ACTIVE_LVLEX0_bit(const void *const hw) |
| 608 | { |
| 609 | return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX0) >> DMAC_ACTIVE_LVLEX0_Pos; |
| 610 | } |
| 611 | |
| 612 | static inline bool hri_dmac_get_ACTIVE_LVLEX1_bit(const void *const hw) |
| 613 | { |
| 614 | return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX1) >> DMAC_ACTIVE_LVLEX1_Pos; |
| 615 | } |
| 616 | |
| 617 | static inline bool hri_dmac_get_ACTIVE_LVLEX2_bit(const void *const hw) |
| 618 | { |
| 619 | return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX2) >> DMAC_ACTIVE_LVLEX2_Pos; |
| 620 | } |
| 621 | |
| 622 | static inline bool hri_dmac_get_ACTIVE_LVLEX3_bit(const void *const hw) |
| 623 | { |
| 624 | return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX3) >> DMAC_ACTIVE_LVLEX3_Pos; |
| 625 | } |
| 626 | |
| 627 | static inline bool hri_dmac_get_ACTIVE_ABUSY_bit(const void *const hw) |
| 628 | { |
| 629 | return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ABUSY) >> DMAC_ACTIVE_ABUSY_Pos; |
| 630 | } |
| 631 | |
| 632 | static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_ID_bf(const void *const hw, hri_dmac_active_reg_t mask) |
| 633 | { |
| 634 | return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID(mask)) >> DMAC_ACTIVE_ID_Pos; |
| 635 | } |
| 636 | |
| 637 | static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_ID_bf(const void *const hw) |
| 638 | { |
| 639 | return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID_Msk) >> DMAC_ACTIVE_ID_Pos; |
| 640 | } |
| 641 | |
| 642 | static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_BTCNT_bf(const void *const hw, hri_dmac_active_reg_t mask) |
| 643 | { |
| 644 | return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT(mask)) >> DMAC_ACTIVE_BTCNT_Pos; |
| 645 | } |
| 646 | |
| 647 | static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_BTCNT_bf(const void *const hw) |
| 648 | { |
| 649 | return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT_Msk) >> DMAC_ACTIVE_BTCNT_Pos; |
| 650 | } |
| 651 | |
| 652 | static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_reg(const void *const hw, hri_dmac_active_reg_t mask) |
| 653 | { |
| 654 | uint32_t tmp; |
| 655 | tmp = ((Dmac *)hw)->ACTIVE.reg; |
| 656 | tmp &= mask; |
| 657 | return tmp; |
| 658 | } |
| 659 | |
| 660 | static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_reg(const void *const hw) |
| 661 | { |
| 662 | return ((Dmac *)hw)->ACTIVE.reg; |
| 663 | } |
| 664 | |
| 665 | static inline void hri_dmac_set_CTRL_SWRST_bit(const void *const hw) |
| 666 | { |
| 667 | DMAC_CRITICAL_SECTION_ENTER(); |
| 668 | ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_SWRST; |
| 669 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 670 | } |
| 671 | |
| 672 | static inline bool hri_dmac_get_CTRL_SWRST_bit(const void *const hw) |
| 673 | { |
| 674 | uint16_t tmp; |
| 675 | tmp = ((Dmac *)hw)->CTRL.reg; |
| 676 | tmp = (tmp & DMAC_CTRL_SWRST) >> DMAC_CTRL_SWRST_Pos; |
| 677 | return (bool)tmp; |
| 678 | } |
| 679 | |
| 680 | static inline void hri_dmac_set_CTRL_DMAENABLE_bit(const void *const hw) |
| 681 | { |
| 682 | DMAC_CRITICAL_SECTION_ENTER(); |
| 683 | ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_DMAENABLE; |
| 684 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 685 | } |
| 686 | |
| 687 | static inline bool hri_dmac_get_CTRL_DMAENABLE_bit(const void *const hw) |
| 688 | { |
| 689 | uint16_t tmp; |
| 690 | tmp = ((Dmac *)hw)->CTRL.reg; |
| 691 | tmp = (tmp & DMAC_CTRL_DMAENABLE) >> DMAC_CTRL_DMAENABLE_Pos; |
| 692 | return (bool)tmp; |
| 693 | } |
| 694 | |
| 695 | static inline void hri_dmac_write_CTRL_DMAENABLE_bit(const void *const hw, bool value) |
| 696 | { |
| 697 | uint16_t tmp; |
| 698 | DMAC_CRITICAL_SECTION_ENTER(); |
| 699 | tmp = ((Dmac *)hw)->CTRL.reg; |
| 700 | tmp &= ~DMAC_CTRL_DMAENABLE; |
| 701 | tmp |= value << DMAC_CTRL_DMAENABLE_Pos; |
| 702 | ((Dmac *)hw)->CTRL.reg = tmp; |
| 703 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 704 | } |
| 705 | |
| 706 | static inline void hri_dmac_clear_CTRL_DMAENABLE_bit(const void *const hw) |
| 707 | { |
| 708 | DMAC_CRITICAL_SECTION_ENTER(); |
| 709 | ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_DMAENABLE; |
| 710 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 711 | } |
| 712 | |
| 713 | static inline void hri_dmac_toggle_CTRL_DMAENABLE_bit(const void *const hw) |
| 714 | { |
| 715 | DMAC_CRITICAL_SECTION_ENTER(); |
| 716 | ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_DMAENABLE; |
| 717 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 718 | } |
| 719 | |
| 720 | static inline void hri_dmac_set_CTRL_LVLEN0_bit(const void *const hw) |
| 721 | { |
| 722 | DMAC_CRITICAL_SECTION_ENTER(); |
| 723 | ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN0; |
| 724 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 725 | } |
| 726 | |
| 727 | static inline bool hri_dmac_get_CTRL_LVLEN0_bit(const void *const hw) |
| 728 | { |
| 729 | uint16_t tmp; |
| 730 | tmp = ((Dmac *)hw)->CTRL.reg; |
| 731 | tmp = (tmp & DMAC_CTRL_LVLEN0) >> DMAC_CTRL_LVLEN0_Pos; |
| 732 | return (bool)tmp; |
| 733 | } |
| 734 | |
| 735 | static inline void hri_dmac_write_CTRL_LVLEN0_bit(const void *const hw, bool value) |
| 736 | { |
| 737 | uint16_t tmp; |
| 738 | DMAC_CRITICAL_SECTION_ENTER(); |
| 739 | tmp = ((Dmac *)hw)->CTRL.reg; |
| 740 | tmp &= ~DMAC_CTRL_LVLEN0; |
| 741 | tmp |= value << DMAC_CTRL_LVLEN0_Pos; |
| 742 | ((Dmac *)hw)->CTRL.reg = tmp; |
| 743 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 744 | } |
| 745 | |
| 746 | static inline void hri_dmac_clear_CTRL_LVLEN0_bit(const void *const hw) |
| 747 | { |
| 748 | DMAC_CRITICAL_SECTION_ENTER(); |
| 749 | ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN0; |
| 750 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 751 | } |
| 752 | |
| 753 | static inline void hri_dmac_toggle_CTRL_LVLEN0_bit(const void *const hw) |
| 754 | { |
| 755 | DMAC_CRITICAL_SECTION_ENTER(); |
| 756 | ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN0; |
| 757 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 758 | } |
| 759 | |
| 760 | static inline void hri_dmac_set_CTRL_LVLEN1_bit(const void *const hw) |
| 761 | { |
| 762 | DMAC_CRITICAL_SECTION_ENTER(); |
| 763 | ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN1; |
| 764 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 765 | } |
| 766 | |
| 767 | static inline bool hri_dmac_get_CTRL_LVLEN1_bit(const void *const hw) |
| 768 | { |
| 769 | uint16_t tmp; |
| 770 | tmp = ((Dmac *)hw)->CTRL.reg; |
| 771 | tmp = (tmp & DMAC_CTRL_LVLEN1) >> DMAC_CTRL_LVLEN1_Pos; |
| 772 | return (bool)tmp; |
| 773 | } |
| 774 | |
| 775 | static inline void hri_dmac_write_CTRL_LVLEN1_bit(const void *const hw, bool value) |
| 776 | { |
| 777 | uint16_t tmp; |
| 778 | DMAC_CRITICAL_SECTION_ENTER(); |
| 779 | tmp = ((Dmac *)hw)->CTRL.reg; |
| 780 | tmp &= ~DMAC_CTRL_LVLEN1; |
| 781 | tmp |= value << DMAC_CTRL_LVLEN1_Pos; |
| 782 | ((Dmac *)hw)->CTRL.reg = tmp; |
| 783 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 784 | } |
| 785 | |
| 786 | static inline void hri_dmac_clear_CTRL_LVLEN1_bit(const void *const hw) |
| 787 | { |
| 788 | DMAC_CRITICAL_SECTION_ENTER(); |
| 789 | ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN1; |
| 790 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 791 | } |
| 792 | |
| 793 | static inline void hri_dmac_toggle_CTRL_LVLEN1_bit(const void *const hw) |
| 794 | { |
| 795 | DMAC_CRITICAL_SECTION_ENTER(); |
| 796 | ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN1; |
| 797 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 798 | } |
| 799 | |
| 800 | static inline void hri_dmac_set_CTRL_LVLEN2_bit(const void *const hw) |
| 801 | { |
| 802 | DMAC_CRITICAL_SECTION_ENTER(); |
| 803 | ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN2; |
| 804 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 805 | } |
| 806 | |
| 807 | static inline bool hri_dmac_get_CTRL_LVLEN2_bit(const void *const hw) |
| 808 | { |
| 809 | uint16_t tmp; |
| 810 | tmp = ((Dmac *)hw)->CTRL.reg; |
| 811 | tmp = (tmp & DMAC_CTRL_LVLEN2) >> DMAC_CTRL_LVLEN2_Pos; |
| 812 | return (bool)tmp; |
| 813 | } |
| 814 | |
| 815 | static inline void hri_dmac_write_CTRL_LVLEN2_bit(const void *const hw, bool value) |
| 816 | { |
| 817 | uint16_t tmp; |
| 818 | DMAC_CRITICAL_SECTION_ENTER(); |
| 819 | tmp = ((Dmac *)hw)->CTRL.reg; |
| 820 | tmp &= ~DMAC_CTRL_LVLEN2; |
| 821 | tmp |= value << DMAC_CTRL_LVLEN2_Pos; |
| 822 | ((Dmac *)hw)->CTRL.reg = tmp; |
| 823 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 824 | } |
| 825 | |
| 826 | static inline void hri_dmac_clear_CTRL_LVLEN2_bit(const void *const hw) |
| 827 | { |
| 828 | DMAC_CRITICAL_SECTION_ENTER(); |
| 829 | ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN2; |
| 830 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 831 | } |
| 832 | |
| 833 | static inline void hri_dmac_toggle_CTRL_LVLEN2_bit(const void *const hw) |
| 834 | { |
| 835 | DMAC_CRITICAL_SECTION_ENTER(); |
| 836 | ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN2; |
| 837 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 838 | } |
| 839 | |
| 840 | static inline void hri_dmac_set_CTRL_LVLEN3_bit(const void *const hw) |
| 841 | { |
| 842 | DMAC_CRITICAL_SECTION_ENTER(); |
| 843 | ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN3; |
| 844 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 845 | } |
| 846 | |
| 847 | static inline bool hri_dmac_get_CTRL_LVLEN3_bit(const void *const hw) |
| 848 | { |
| 849 | uint16_t tmp; |
| 850 | tmp = ((Dmac *)hw)->CTRL.reg; |
| 851 | tmp = (tmp & DMAC_CTRL_LVLEN3) >> DMAC_CTRL_LVLEN3_Pos; |
| 852 | return (bool)tmp; |
| 853 | } |
| 854 | |
| 855 | static inline void hri_dmac_write_CTRL_LVLEN3_bit(const void *const hw, bool value) |
| 856 | { |
| 857 | uint16_t tmp; |
| 858 | DMAC_CRITICAL_SECTION_ENTER(); |
| 859 | tmp = ((Dmac *)hw)->CTRL.reg; |
| 860 | tmp &= ~DMAC_CTRL_LVLEN3; |
| 861 | tmp |= value << DMAC_CTRL_LVLEN3_Pos; |
| 862 | ((Dmac *)hw)->CTRL.reg = tmp; |
| 863 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 864 | } |
| 865 | |
| 866 | static inline void hri_dmac_clear_CTRL_LVLEN3_bit(const void *const hw) |
| 867 | { |
| 868 | DMAC_CRITICAL_SECTION_ENTER(); |
| 869 | ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN3; |
| 870 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 871 | } |
| 872 | |
| 873 | static inline void hri_dmac_toggle_CTRL_LVLEN3_bit(const void *const hw) |
| 874 | { |
| 875 | DMAC_CRITICAL_SECTION_ENTER(); |
| 876 | ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN3; |
| 877 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 878 | } |
| 879 | |
| 880 | static inline void hri_dmac_set_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) |
| 881 | { |
| 882 | DMAC_CRITICAL_SECTION_ENTER(); |
| 883 | ((Dmac *)hw)->CTRL.reg |= mask; |
| 884 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 885 | } |
| 886 | |
| 887 | static inline hri_dmac_ctrl_reg_t hri_dmac_get_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) |
| 888 | { |
| 889 | uint16_t tmp; |
| 890 | tmp = ((Dmac *)hw)->CTRL.reg; |
| 891 | tmp &= mask; |
| 892 | return tmp; |
| 893 | } |
| 894 | |
| 895 | static inline void hri_dmac_write_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t data) |
| 896 | { |
| 897 | DMAC_CRITICAL_SECTION_ENTER(); |
| 898 | ((Dmac *)hw)->CTRL.reg = data; |
| 899 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 900 | } |
| 901 | |
| 902 | static inline void hri_dmac_clear_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) |
| 903 | { |
| 904 | DMAC_CRITICAL_SECTION_ENTER(); |
| 905 | ((Dmac *)hw)->CTRL.reg &= ~mask; |
| 906 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 907 | } |
| 908 | |
| 909 | static inline void hri_dmac_toggle_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) |
| 910 | { |
| 911 | DMAC_CRITICAL_SECTION_ENTER(); |
| 912 | ((Dmac *)hw)->CTRL.reg ^= mask; |
| 913 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 914 | } |
| 915 | |
| 916 | static inline hri_dmac_ctrl_reg_t hri_dmac_read_CTRL_reg(const void *const hw) |
| 917 | { |
| 918 | return ((Dmac *)hw)->CTRL.reg; |
| 919 | } |
| 920 | |
| 921 | static inline void hri_dmac_set_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) |
| 922 | { |
| 923 | DMAC_CRITICAL_SECTION_ENTER(); |
| 924 | ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCBEATSIZE(mask); |
| 925 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 926 | } |
| 927 | |
| 928 | static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, |
| 929 | hri_dmac_crcctrl_reg_t mask) |
| 930 | { |
| 931 | uint16_t tmp; |
| 932 | tmp = ((Dmac *)hw)->CRCCTRL.reg; |
| 933 | tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE(mask)) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; |
| 934 | return tmp; |
| 935 | } |
| 936 | |
| 937 | static inline void hri_dmac_write_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) |
| 938 | { |
| 939 | uint16_t tmp; |
| 940 | DMAC_CRITICAL_SECTION_ENTER(); |
| 941 | tmp = ((Dmac *)hw)->CRCCTRL.reg; |
| 942 | tmp &= ~DMAC_CRCCTRL_CRCBEATSIZE_Msk; |
| 943 | tmp |= DMAC_CRCCTRL_CRCBEATSIZE(data); |
| 944 | ((Dmac *)hw)->CRCCTRL.reg = tmp; |
| 945 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 946 | } |
| 947 | |
| 948 | static inline void hri_dmac_clear_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) |
| 949 | { |
| 950 | DMAC_CRITICAL_SECTION_ENTER(); |
| 951 | ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCBEATSIZE(mask); |
| 952 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 953 | } |
| 954 | |
| 955 | static inline void hri_dmac_toggle_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) |
| 956 | { |
| 957 | DMAC_CRITICAL_SECTION_ENTER(); |
| 958 | ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCBEATSIZE(mask); |
| 959 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 960 | } |
| 961 | |
| 962 | static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCBEATSIZE_bf(const void *const hw) |
| 963 | { |
| 964 | uint16_t tmp; |
| 965 | tmp = ((Dmac *)hw)->CRCCTRL.reg; |
| 966 | tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE_Msk) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; |
| 967 | return tmp; |
| 968 | } |
| 969 | |
| 970 | static inline void hri_dmac_set_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) |
| 971 | { |
| 972 | DMAC_CRITICAL_SECTION_ENTER(); |
| 973 | ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCPOLY(mask); |
| 974 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 975 | } |
| 976 | |
| 977 | static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) |
| 978 | { |
| 979 | uint16_t tmp; |
| 980 | tmp = ((Dmac *)hw)->CRCCTRL.reg; |
| 981 | tmp = (tmp & DMAC_CRCCTRL_CRCPOLY(mask)) >> DMAC_CRCCTRL_CRCPOLY_Pos; |
| 982 | return tmp; |
| 983 | } |
| 984 | |
| 985 | static inline void hri_dmac_write_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) |
| 986 | { |
| 987 | uint16_t tmp; |
| 988 | DMAC_CRITICAL_SECTION_ENTER(); |
| 989 | tmp = ((Dmac *)hw)->CRCCTRL.reg; |
| 990 | tmp &= ~DMAC_CRCCTRL_CRCPOLY_Msk; |
| 991 | tmp |= DMAC_CRCCTRL_CRCPOLY(data); |
| 992 | ((Dmac *)hw)->CRCCTRL.reg = tmp; |
| 993 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 994 | } |
| 995 | |
| 996 | static inline void hri_dmac_clear_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) |
| 997 | { |
| 998 | DMAC_CRITICAL_SECTION_ENTER(); |
| 999 | ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCPOLY(mask); |
| 1000 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1001 | } |
| 1002 | |
| 1003 | static inline void hri_dmac_toggle_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) |
| 1004 | { |
| 1005 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1006 | ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCPOLY(mask); |
| 1007 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1008 | } |
| 1009 | |
| 1010 | static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCPOLY_bf(const void *const hw) |
| 1011 | { |
| 1012 | uint16_t tmp; |
| 1013 | tmp = ((Dmac *)hw)->CRCCTRL.reg; |
| 1014 | tmp = (tmp & DMAC_CRCCTRL_CRCPOLY_Msk) >> DMAC_CRCCTRL_CRCPOLY_Pos; |
| 1015 | return tmp; |
| 1016 | } |
| 1017 | |
| 1018 | static inline void hri_dmac_set_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) |
| 1019 | { |
| 1020 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1021 | ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCSRC(mask); |
| 1022 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1023 | } |
| 1024 | |
| 1025 | static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) |
| 1026 | { |
| 1027 | uint16_t tmp; |
| 1028 | tmp = ((Dmac *)hw)->CRCCTRL.reg; |
| 1029 | tmp = (tmp & DMAC_CRCCTRL_CRCSRC(mask)) >> DMAC_CRCCTRL_CRCSRC_Pos; |
| 1030 | return tmp; |
| 1031 | } |
| 1032 | |
| 1033 | static inline void hri_dmac_write_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) |
| 1034 | { |
| 1035 | uint16_t tmp; |
| 1036 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1037 | tmp = ((Dmac *)hw)->CRCCTRL.reg; |
| 1038 | tmp &= ~DMAC_CRCCTRL_CRCSRC_Msk; |
| 1039 | tmp |= DMAC_CRCCTRL_CRCSRC(data); |
| 1040 | ((Dmac *)hw)->CRCCTRL.reg = tmp; |
| 1041 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1042 | } |
| 1043 | |
| 1044 | static inline void hri_dmac_clear_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) |
| 1045 | { |
| 1046 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1047 | ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCSRC(mask); |
| 1048 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1049 | } |
| 1050 | |
| 1051 | static inline void hri_dmac_toggle_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) |
| 1052 | { |
| 1053 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1054 | ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCSRC(mask); |
| 1055 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1056 | } |
| 1057 | |
| 1058 | static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCSRC_bf(const void *const hw) |
| 1059 | { |
| 1060 | uint16_t tmp; |
| 1061 | tmp = ((Dmac *)hw)->CRCCTRL.reg; |
| 1062 | tmp = (tmp & DMAC_CRCCTRL_CRCSRC_Msk) >> DMAC_CRCCTRL_CRCSRC_Pos; |
| 1063 | return tmp; |
| 1064 | } |
| 1065 | |
| 1066 | static inline void hri_dmac_set_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) |
| 1067 | { |
| 1068 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1069 | ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCMODE(mask); |
| 1070 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1071 | } |
| 1072 | |
| 1073 | static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) |
| 1074 | { |
| 1075 | uint16_t tmp; |
| 1076 | tmp = ((Dmac *)hw)->CRCCTRL.reg; |
| 1077 | tmp = (tmp & DMAC_CRCCTRL_CRCMODE(mask)) >> DMAC_CRCCTRL_CRCMODE_Pos; |
| 1078 | return tmp; |
| 1079 | } |
| 1080 | |
| 1081 | static inline void hri_dmac_write_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) |
| 1082 | { |
| 1083 | uint16_t tmp; |
| 1084 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1085 | tmp = ((Dmac *)hw)->CRCCTRL.reg; |
| 1086 | tmp &= ~DMAC_CRCCTRL_CRCMODE_Msk; |
| 1087 | tmp |= DMAC_CRCCTRL_CRCMODE(data); |
| 1088 | ((Dmac *)hw)->CRCCTRL.reg = tmp; |
| 1089 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1090 | } |
| 1091 | |
| 1092 | static inline void hri_dmac_clear_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) |
| 1093 | { |
| 1094 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1095 | ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCMODE(mask); |
| 1096 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1097 | } |
| 1098 | |
| 1099 | static inline void hri_dmac_toggle_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) |
| 1100 | { |
| 1101 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1102 | ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCMODE(mask); |
| 1103 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1104 | } |
| 1105 | |
| 1106 | static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCMODE_bf(const void *const hw) |
| 1107 | { |
| 1108 | uint16_t tmp; |
| 1109 | tmp = ((Dmac *)hw)->CRCCTRL.reg; |
| 1110 | tmp = (tmp & DMAC_CRCCTRL_CRCMODE_Msk) >> DMAC_CRCCTRL_CRCMODE_Pos; |
| 1111 | return tmp; |
| 1112 | } |
| 1113 | |
| 1114 | static inline void hri_dmac_set_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) |
| 1115 | { |
| 1116 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1117 | ((Dmac *)hw)->CRCCTRL.reg |= mask; |
| 1118 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1119 | } |
| 1120 | |
| 1121 | static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) |
| 1122 | { |
| 1123 | uint16_t tmp; |
| 1124 | tmp = ((Dmac *)hw)->CRCCTRL.reg; |
| 1125 | tmp &= mask; |
| 1126 | return tmp; |
| 1127 | } |
| 1128 | |
| 1129 | static inline void hri_dmac_write_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t data) |
| 1130 | { |
| 1131 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1132 | ((Dmac *)hw)->CRCCTRL.reg = data; |
| 1133 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1134 | } |
| 1135 | |
| 1136 | static inline void hri_dmac_clear_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) |
| 1137 | { |
| 1138 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1139 | ((Dmac *)hw)->CRCCTRL.reg &= ~mask; |
| 1140 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1141 | } |
| 1142 | |
| 1143 | static inline void hri_dmac_toggle_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) |
| 1144 | { |
| 1145 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1146 | ((Dmac *)hw)->CRCCTRL.reg ^= mask; |
| 1147 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1148 | } |
| 1149 | |
| 1150 | static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_reg(const void *const hw) |
| 1151 | { |
| 1152 | return ((Dmac *)hw)->CRCCTRL.reg; |
| 1153 | } |
| 1154 | |
| 1155 | static inline void hri_dmac_set_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) |
| 1156 | { |
| 1157 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1158 | ((Dmac *)hw)->CRCDATAIN.reg |= DMAC_CRCDATAIN_CRCDATAIN(mask); |
| 1159 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1160 | } |
| 1161 | |
| 1162 | static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_CRCDATAIN_bf(const void *const hw, |
| 1163 | hri_dmac_crcdatain_reg_t mask) |
| 1164 | { |
| 1165 | uint32_t tmp; |
| 1166 | tmp = ((Dmac *)hw)->CRCDATAIN.reg; |
| 1167 | tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN(mask)) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; |
| 1168 | return tmp; |
| 1169 | } |
| 1170 | |
| 1171 | static inline void hri_dmac_write_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t data) |
| 1172 | { |
| 1173 | uint32_t tmp; |
| 1174 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1175 | tmp = ((Dmac *)hw)->CRCDATAIN.reg; |
| 1176 | tmp &= ~DMAC_CRCDATAIN_CRCDATAIN_Msk; |
| 1177 | tmp |= DMAC_CRCDATAIN_CRCDATAIN(data); |
| 1178 | ((Dmac *)hw)->CRCDATAIN.reg = tmp; |
| 1179 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1180 | } |
| 1181 | |
| 1182 | static inline void hri_dmac_clear_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) |
| 1183 | { |
| 1184 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1185 | ((Dmac *)hw)->CRCDATAIN.reg &= ~DMAC_CRCDATAIN_CRCDATAIN(mask); |
| 1186 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1187 | } |
| 1188 | |
| 1189 | static inline void hri_dmac_toggle_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) |
| 1190 | { |
| 1191 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1192 | ((Dmac *)hw)->CRCDATAIN.reg ^= DMAC_CRCDATAIN_CRCDATAIN(mask); |
| 1193 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1194 | } |
| 1195 | |
| 1196 | static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_CRCDATAIN_bf(const void *const hw) |
| 1197 | { |
| 1198 | uint32_t tmp; |
| 1199 | tmp = ((Dmac *)hw)->CRCDATAIN.reg; |
| 1200 | tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN_Msk) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; |
| 1201 | return tmp; |
| 1202 | } |
| 1203 | |
| 1204 | static inline void hri_dmac_set_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) |
| 1205 | { |
| 1206 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1207 | ((Dmac *)hw)->CRCDATAIN.reg |= mask; |
| 1208 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1209 | } |
| 1210 | |
| 1211 | static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) |
| 1212 | { |
| 1213 | uint32_t tmp; |
| 1214 | tmp = ((Dmac *)hw)->CRCDATAIN.reg; |
| 1215 | tmp &= mask; |
| 1216 | return tmp; |
| 1217 | } |
| 1218 | |
| 1219 | static inline void hri_dmac_write_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t data) |
| 1220 | { |
| 1221 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1222 | ((Dmac *)hw)->CRCDATAIN.reg = data; |
| 1223 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1224 | } |
| 1225 | |
| 1226 | static inline void hri_dmac_clear_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) |
| 1227 | { |
| 1228 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1229 | ((Dmac *)hw)->CRCDATAIN.reg &= ~mask; |
| 1230 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1231 | } |
| 1232 | |
| 1233 | static inline void hri_dmac_toggle_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) |
| 1234 | { |
| 1235 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1236 | ((Dmac *)hw)->CRCDATAIN.reg ^= mask; |
| 1237 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1238 | } |
| 1239 | |
| 1240 | static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_reg(const void *const hw) |
| 1241 | { |
| 1242 | return ((Dmac *)hw)->CRCDATAIN.reg; |
| 1243 | } |
| 1244 | |
| 1245 | static inline void hri_dmac_set_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) |
| 1246 | { |
| 1247 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1248 | ((Dmac *)hw)->CRCCHKSUM.reg |= DMAC_CRCCHKSUM_CRCCHKSUM(mask); |
| 1249 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1250 | } |
| 1251 | |
| 1252 | static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, |
| 1253 | hri_dmac_crcchksum_reg_t mask) |
| 1254 | { |
| 1255 | uint32_t tmp; |
| 1256 | tmp = ((Dmac *)hw)->CRCCHKSUM.reg; |
| 1257 | tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM(mask)) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; |
| 1258 | return tmp; |
| 1259 | } |
| 1260 | |
| 1261 | static inline void hri_dmac_write_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t data) |
| 1262 | { |
| 1263 | uint32_t tmp; |
| 1264 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1265 | tmp = ((Dmac *)hw)->CRCCHKSUM.reg; |
| 1266 | tmp &= ~DMAC_CRCCHKSUM_CRCCHKSUM_Msk; |
| 1267 | tmp |= DMAC_CRCCHKSUM_CRCCHKSUM(data); |
| 1268 | ((Dmac *)hw)->CRCCHKSUM.reg = tmp; |
| 1269 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1270 | } |
| 1271 | |
| 1272 | static inline void hri_dmac_clear_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) |
| 1273 | { |
| 1274 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1275 | ((Dmac *)hw)->CRCCHKSUM.reg &= ~DMAC_CRCCHKSUM_CRCCHKSUM(mask); |
| 1276 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1277 | } |
| 1278 | |
| 1279 | static inline void hri_dmac_toggle_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) |
| 1280 | { |
| 1281 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1282 | ((Dmac *)hw)->CRCCHKSUM.reg ^= DMAC_CRCCHKSUM_CRCCHKSUM(mask); |
| 1283 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1284 | } |
| 1285 | |
| 1286 | static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw) |
| 1287 | { |
| 1288 | uint32_t tmp; |
| 1289 | tmp = ((Dmac *)hw)->CRCCHKSUM.reg; |
| 1290 | tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM_Msk) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; |
| 1291 | return tmp; |
| 1292 | } |
| 1293 | |
| 1294 | static inline void hri_dmac_set_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) |
| 1295 | { |
| 1296 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1297 | ((Dmac *)hw)->CRCCHKSUM.reg |= mask; |
| 1298 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1299 | } |
| 1300 | |
| 1301 | static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) |
| 1302 | { |
| 1303 | uint32_t tmp; |
| 1304 | tmp = ((Dmac *)hw)->CRCCHKSUM.reg; |
| 1305 | tmp &= mask; |
| 1306 | return tmp; |
| 1307 | } |
| 1308 | |
| 1309 | static inline void hri_dmac_write_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t data) |
| 1310 | { |
| 1311 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1312 | ((Dmac *)hw)->CRCCHKSUM.reg = data; |
| 1313 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1314 | } |
| 1315 | |
| 1316 | static inline void hri_dmac_clear_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) |
| 1317 | { |
| 1318 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1319 | ((Dmac *)hw)->CRCCHKSUM.reg &= ~mask; |
| 1320 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1321 | } |
| 1322 | |
| 1323 | static inline void hri_dmac_toggle_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) |
| 1324 | { |
| 1325 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1326 | ((Dmac *)hw)->CRCCHKSUM.reg ^= mask; |
| 1327 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1328 | } |
| 1329 | |
| 1330 | static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_reg(const void *const hw) |
| 1331 | { |
| 1332 | return ((Dmac *)hw)->CRCCHKSUM.reg; |
| 1333 | } |
| 1334 | |
| 1335 | static inline void hri_dmac_set_DBGCTRL_DBGRUN_bit(const void *const hw) |
| 1336 | { |
| 1337 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1338 | ((Dmac *)hw)->DBGCTRL.reg |= DMAC_DBGCTRL_DBGRUN; |
| 1339 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1340 | } |
| 1341 | |
| 1342 | static inline bool hri_dmac_get_DBGCTRL_DBGRUN_bit(const void *const hw) |
| 1343 | { |
| 1344 | uint8_t tmp; |
| 1345 | tmp = ((Dmac *)hw)->DBGCTRL.reg; |
| 1346 | tmp = (tmp & DMAC_DBGCTRL_DBGRUN) >> DMAC_DBGCTRL_DBGRUN_Pos; |
| 1347 | return (bool)tmp; |
| 1348 | } |
| 1349 | |
| 1350 | static inline void hri_dmac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) |
| 1351 | { |
| 1352 | uint8_t tmp; |
| 1353 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1354 | tmp = ((Dmac *)hw)->DBGCTRL.reg; |
| 1355 | tmp &= ~DMAC_DBGCTRL_DBGRUN; |
| 1356 | tmp |= value << DMAC_DBGCTRL_DBGRUN_Pos; |
| 1357 | ((Dmac *)hw)->DBGCTRL.reg = tmp; |
| 1358 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1359 | } |
| 1360 | |
| 1361 | static inline void hri_dmac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) |
| 1362 | { |
| 1363 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1364 | ((Dmac *)hw)->DBGCTRL.reg &= ~DMAC_DBGCTRL_DBGRUN; |
| 1365 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1366 | } |
| 1367 | |
| 1368 | static inline void hri_dmac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) |
| 1369 | { |
| 1370 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1371 | ((Dmac *)hw)->DBGCTRL.reg ^= DMAC_DBGCTRL_DBGRUN; |
| 1372 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1373 | } |
| 1374 | |
| 1375 | static inline void hri_dmac_set_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) |
| 1376 | { |
| 1377 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1378 | ((Dmac *)hw)->DBGCTRL.reg |= mask; |
| 1379 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1380 | } |
| 1381 | |
| 1382 | static inline hri_dmac_dbgctrl_reg_t hri_dmac_get_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) |
| 1383 | { |
| 1384 | uint8_t tmp; |
| 1385 | tmp = ((Dmac *)hw)->DBGCTRL.reg; |
| 1386 | tmp &= mask; |
| 1387 | return tmp; |
| 1388 | } |
| 1389 | |
| 1390 | static inline void hri_dmac_write_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t data) |
| 1391 | { |
| 1392 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1393 | ((Dmac *)hw)->DBGCTRL.reg = data; |
| 1394 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1395 | } |
| 1396 | |
| 1397 | static inline void hri_dmac_clear_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) |
| 1398 | { |
| 1399 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1400 | ((Dmac *)hw)->DBGCTRL.reg &= ~mask; |
| 1401 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1402 | } |
| 1403 | |
| 1404 | static inline void hri_dmac_toggle_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) |
| 1405 | { |
| 1406 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1407 | ((Dmac *)hw)->DBGCTRL.reg ^= mask; |
| 1408 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1409 | } |
| 1410 | |
| 1411 | static inline hri_dmac_dbgctrl_reg_t hri_dmac_read_DBGCTRL_reg(const void *const hw) |
| 1412 | { |
| 1413 | return ((Dmac *)hw)->DBGCTRL.reg; |
| 1414 | } |
| 1415 | |
| 1416 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) |
| 1417 | { |
| 1418 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1419 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG0; |
| 1420 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1421 | } |
| 1422 | |
| 1423 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) |
| 1424 | { |
| 1425 | uint32_t tmp; |
| 1426 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1427 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG0) >> DMAC_SWTRIGCTRL_SWTRIG0_Pos; |
| 1428 | return (bool)tmp; |
| 1429 | } |
| 1430 | |
| 1431 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG0_bit(const void *const hw, bool value) |
| 1432 | { |
| 1433 | uint32_t tmp; |
| 1434 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1435 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1436 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG0; |
| 1437 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG0_Pos; |
| 1438 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 1439 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1440 | } |
| 1441 | |
| 1442 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) |
| 1443 | { |
| 1444 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1445 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG0; |
| 1446 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1447 | } |
| 1448 | |
| 1449 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) |
| 1450 | { |
| 1451 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1452 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG0; |
| 1453 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1454 | } |
| 1455 | |
| 1456 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) |
| 1457 | { |
| 1458 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1459 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG1; |
| 1460 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1461 | } |
| 1462 | |
| 1463 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) |
| 1464 | { |
| 1465 | uint32_t tmp; |
| 1466 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1467 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG1) >> DMAC_SWTRIGCTRL_SWTRIG1_Pos; |
| 1468 | return (bool)tmp; |
| 1469 | } |
| 1470 | |
| 1471 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG1_bit(const void *const hw, bool value) |
| 1472 | { |
| 1473 | uint32_t tmp; |
| 1474 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1475 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1476 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG1; |
| 1477 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG1_Pos; |
| 1478 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 1479 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1480 | } |
| 1481 | |
| 1482 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) |
| 1483 | { |
| 1484 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1485 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG1; |
| 1486 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1487 | } |
| 1488 | |
| 1489 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) |
| 1490 | { |
| 1491 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1492 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG1; |
| 1493 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1494 | } |
| 1495 | |
| 1496 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) |
| 1497 | { |
| 1498 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1499 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG2; |
| 1500 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1501 | } |
| 1502 | |
| 1503 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) |
| 1504 | { |
| 1505 | uint32_t tmp; |
| 1506 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1507 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG2) >> DMAC_SWTRIGCTRL_SWTRIG2_Pos; |
| 1508 | return (bool)tmp; |
| 1509 | } |
| 1510 | |
| 1511 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG2_bit(const void *const hw, bool value) |
| 1512 | { |
| 1513 | uint32_t tmp; |
| 1514 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1515 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1516 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG2; |
| 1517 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG2_Pos; |
| 1518 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 1519 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1520 | } |
| 1521 | |
| 1522 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) |
| 1523 | { |
| 1524 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1525 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG2; |
| 1526 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1527 | } |
| 1528 | |
| 1529 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) |
| 1530 | { |
| 1531 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1532 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG2; |
| 1533 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1534 | } |
| 1535 | |
| 1536 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) |
| 1537 | { |
| 1538 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1539 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG3; |
| 1540 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1541 | } |
| 1542 | |
| 1543 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) |
| 1544 | { |
| 1545 | uint32_t tmp; |
| 1546 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1547 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG3) >> DMAC_SWTRIGCTRL_SWTRIG3_Pos; |
| 1548 | return (bool)tmp; |
| 1549 | } |
| 1550 | |
| 1551 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG3_bit(const void *const hw, bool value) |
| 1552 | { |
| 1553 | uint32_t tmp; |
| 1554 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1555 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1556 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG3; |
| 1557 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG3_Pos; |
| 1558 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 1559 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1560 | } |
| 1561 | |
| 1562 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) |
| 1563 | { |
| 1564 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1565 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG3; |
| 1566 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1567 | } |
| 1568 | |
| 1569 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) |
| 1570 | { |
| 1571 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1572 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG3; |
| 1573 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1574 | } |
| 1575 | |
| 1576 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) |
| 1577 | { |
| 1578 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1579 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG4; |
| 1580 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1581 | } |
| 1582 | |
| 1583 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) |
| 1584 | { |
| 1585 | uint32_t tmp; |
| 1586 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1587 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG4) >> DMAC_SWTRIGCTRL_SWTRIG4_Pos; |
| 1588 | return (bool)tmp; |
| 1589 | } |
| 1590 | |
| 1591 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG4_bit(const void *const hw, bool value) |
| 1592 | { |
| 1593 | uint32_t tmp; |
| 1594 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1595 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1596 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG4; |
| 1597 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG4_Pos; |
| 1598 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 1599 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1600 | } |
| 1601 | |
| 1602 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) |
| 1603 | { |
| 1604 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1605 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG4; |
| 1606 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1607 | } |
| 1608 | |
| 1609 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) |
| 1610 | { |
| 1611 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1612 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG4; |
| 1613 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1614 | } |
| 1615 | |
| 1616 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) |
| 1617 | { |
| 1618 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1619 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG5; |
| 1620 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1621 | } |
| 1622 | |
| 1623 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) |
| 1624 | { |
| 1625 | uint32_t tmp; |
| 1626 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1627 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG5) >> DMAC_SWTRIGCTRL_SWTRIG5_Pos; |
| 1628 | return (bool)tmp; |
| 1629 | } |
| 1630 | |
| 1631 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG5_bit(const void *const hw, bool value) |
| 1632 | { |
| 1633 | uint32_t tmp; |
| 1634 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1635 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1636 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG5; |
| 1637 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG5_Pos; |
| 1638 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 1639 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1640 | } |
| 1641 | |
| 1642 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) |
| 1643 | { |
| 1644 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1645 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG5; |
| 1646 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1647 | } |
| 1648 | |
| 1649 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) |
| 1650 | { |
| 1651 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1652 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG5; |
| 1653 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1654 | } |
| 1655 | |
| 1656 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) |
| 1657 | { |
| 1658 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1659 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG6; |
| 1660 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1661 | } |
| 1662 | |
| 1663 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) |
| 1664 | { |
| 1665 | uint32_t tmp; |
| 1666 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1667 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG6) >> DMAC_SWTRIGCTRL_SWTRIG6_Pos; |
| 1668 | return (bool)tmp; |
| 1669 | } |
| 1670 | |
| 1671 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG6_bit(const void *const hw, bool value) |
| 1672 | { |
| 1673 | uint32_t tmp; |
| 1674 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1675 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1676 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG6; |
| 1677 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG6_Pos; |
| 1678 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 1679 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1680 | } |
| 1681 | |
| 1682 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) |
| 1683 | { |
| 1684 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1685 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG6; |
| 1686 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1687 | } |
| 1688 | |
| 1689 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) |
| 1690 | { |
| 1691 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1692 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG6; |
| 1693 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1694 | } |
| 1695 | |
| 1696 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) |
| 1697 | { |
| 1698 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1699 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG7; |
| 1700 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1701 | } |
| 1702 | |
| 1703 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) |
| 1704 | { |
| 1705 | uint32_t tmp; |
| 1706 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1707 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG7) >> DMAC_SWTRIGCTRL_SWTRIG7_Pos; |
| 1708 | return (bool)tmp; |
| 1709 | } |
| 1710 | |
| 1711 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG7_bit(const void *const hw, bool value) |
| 1712 | { |
| 1713 | uint32_t tmp; |
| 1714 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1715 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1716 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG7; |
| 1717 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG7_Pos; |
| 1718 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 1719 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1720 | } |
| 1721 | |
| 1722 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) |
| 1723 | { |
| 1724 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1725 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG7; |
| 1726 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1727 | } |
| 1728 | |
| 1729 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) |
| 1730 | { |
| 1731 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1732 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG7; |
| 1733 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1734 | } |
| 1735 | |
| 1736 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) |
| 1737 | { |
| 1738 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1739 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG8; |
| 1740 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1741 | } |
| 1742 | |
| 1743 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) |
| 1744 | { |
| 1745 | uint32_t tmp; |
| 1746 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1747 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG8) >> DMAC_SWTRIGCTRL_SWTRIG8_Pos; |
| 1748 | return (bool)tmp; |
| 1749 | } |
| 1750 | |
| 1751 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG8_bit(const void *const hw, bool value) |
| 1752 | { |
| 1753 | uint32_t tmp; |
| 1754 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1755 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1756 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG8; |
| 1757 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG8_Pos; |
| 1758 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 1759 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1760 | } |
| 1761 | |
| 1762 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) |
| 1763 | { |
| 1764 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1765 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG8; |
| 1766 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1767 | } |
| 1768 | |
| 1769 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) |
| 1770 | { |
| 1771 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1772 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG8; |
| 1773 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1774 | } |
| 1775 | |
| 1776 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) |
| 1777 | { |
| 1778 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1779 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG9; |
| 1780 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1781 | } |
| 1782 | |
| 1783 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) |
| 1784 | { |
| 1785 | uint32_t tmp; |
| 1786 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1787 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG9) >> DMAC_SWTRIGCTRL_SWTRIG9_Pos; |
| 1788 | return (bool)tmp; |
| 1789 | } |
| 1790 | |
| 1791 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG9_bit(const void *const hw, bool value) |
| 1792 | { |
| 1793 | uint32_t tmp; |
| 1794 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1795 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1796 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG9; |
| 1797 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG9_Pos; |
| 1798 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 1799 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1800 | } |
| 1801 | |
| 1802 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) |
| 1803 | { |
| 1804 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1805 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG9; |
| 1806 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1807 | } |
| 1808 | |
| 1809 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) |
| 1810 | { |
| 1811 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1812 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG9; |
| 1813 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1814 | } |
| 1815 | |
| 1816 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) |
| 1817 | { |
| 1818 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1819 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG10; |
| 1820 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1821 | } |
| 1822 | |
| 1823 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) |
| 1824 | { |
| 1825 | uint32_t tmp; |
| 1826 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1827 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG10) >> DMAC_SWTRIGCTRL_SWTRIG10_Pos; |
| 1828 | return (bool)tmp; |
| 1829 | } |
| 1830 | |
| 1831 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG10_bit(const void *const hw, bool value) |
| 1832 | { |
| 1833 | uint32_t tmp; |
| 1834 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1835 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1836 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG10; |
| 1837 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG10_Pos; |
| 1838 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 1839 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1840 | } |
| 1841 | |
| 1842 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) |
| 1843 | { |
| 1844 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1845 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG10; |
| 1846 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1847 | } |
| 1848 | |
| 1849 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) |
| 1850 | { |
| 1851 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1852 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG10; |
| 1853 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1854 | } |
| 1855 | |
| 1856 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) |
| 1857 | { |
| 1858 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1859 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG11; |
| 1860 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1861 | } |
| 1862 | |
| 1863 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) |
| 1864 | { |
| 1865 | uint32_t tmp; |
| 1866 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1867 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG11) >> DMAC_SWTRIGCTRL_SWTRIG11_Pos; |
| 1868 | return (bool)tmp; |
| 1869 | } |
| 1870 | |
| 1871 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG11_bit(const void *const hw, bool value) |
| 1872 | { |
| 1873 | uint32_t tmp; |
| 1874 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1875 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1876 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG11; |
| 1877 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG11_Pos; |
| 1878 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 1879 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1880 | } |
| 1881 | |
| 1882 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) |
| 1883 | { |
| 1884 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1885 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG11; |
| 1886 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1887 | } |
| 1888 | |
| 1889 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) |
| 1890 | { |
| 1891 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1892 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG11; |
| 1893 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1894 | } |
| 1895 | |
| 1896 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) |
| 1897 | { |
| 1898 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1899 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG12; |
| 1900 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1901 | } |
| 1902 | |
| 1903 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) |
| 1904 | { |
| 1905 | uint32_t tmp; |
| 1906 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1907 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG12) >> DMAC_SWTRIGCTRL_SWTRIG12_Pos; |
| 1908 | return (bool)tmp; |
| 1909 | } |
| 1910 | |
| 1911 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG12_bit(const void *const hw, bool value) |
| 1912 | { |
| 1913 | uint32_t tmp; |
| 1914 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1915 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1916 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG12; |
| 1917 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG12_Pos; |
| 1918 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 1919 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1920 | } |
| 1921 | |
| 1922 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) |
| 1923 | { |
| 1924 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1925 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG12; |
| 1926 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1927 | } |
| 1928 | |
| 1929 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) |
| 1930 | { |
| 1931 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1932 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG12; |
| 1933 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1934 | } |
| 1935 | |
| 1936 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) |
| 1937 | { |
| 1938 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1939 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG13; |
| 1940 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1941 | } |
| 1942 | |
| 1943 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) |
| 1944 | { |
| 1945 | uint32_t tmp; |
| 1946 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1947 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG13) >> DMAC_SWTRIGCTRL_SWTRIG13_Pos; |
| 1948 | return (bool)tmp; |
| 1949 | } |
| 1950 | |
| 1951 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG13_bit(const void *const hw, bool value) |
| 1952 | { |
| 1953 | uint32_t tmp; |
| 1954 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1955 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1956 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG13; |
| 1957 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG13_Pos; |
| 1958 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 1959 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1960 | } |
| 1961 | |
| 1962 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) |
| 1963 | { |
| 1964 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1965 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG13; |
| 1966 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1967 | } |
| 1968 | |
| 1969 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) |
| 1970 | { |
| 1971 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1972 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG13; |
| 1973 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1974 | } |
| 1975 | |
| 1976 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) |
| 1977 | { |
| 1978 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1979 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG14; |
| 1980 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 1981 | } |
| 1982 | |
| 1983 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) |
| 1984 | { |
| 1985 | uint32_t tmp; |
| 1986 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1987 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG14) >> DMAC_SWTRIGCTRL_SWTRIG14_Pos; |
| 1988 | return (bool)tmp; |
| 1989 | } |
| 1990 | |
| 1991 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG14_bit(const void *const hw, bool value) |
| 1992 | { |
| 1993 | uint32_t tmp; |
| 1994 | DMAC_CRITICAL_SECTION_ENTER(); |
| 1995 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 1996 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG14; |
| 1997 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG14_Pos; |
| 1998 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 1999 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2000 | } |
| 2001 | |
| 2002 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) |
| 2003 | { |
| 2004 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2005 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG14; |
| 2006 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2007 | } |
| 2008 | |
| 2009 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) |
| 2010 | { |
| 2011 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2012 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG14; |
| 2013 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2014 | } |
| 2015 | |
| 2016 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) |
| 2017 | { |
| 2018 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2019 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG15; |
| 2020 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2021 | } |
| 2022 | |
| 2023 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) |
| 2024 | { |
| 2025 | uint32_t tmp; |
| 2026 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2027 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG15) >> DMAC_SWTRIGCTRL_SWTRIG15_Pos; |
| 2028 | return (bool)tmp; |
| 2029 | } |
| 2030 | |
| 2031 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG15_bit(const void *const hw, bool value) |
| 2032 | { |
| 2033 | uint32_t tmp; |
| 2034 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2035 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2036 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG15; |
| 2037 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG15_Pos; |
| 2038 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 2039 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2040 | } |
| 2041 | |
| 2042 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) |
| 2043 | { |
| 2044 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2045 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG15; |
| 2046 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2047 | } |
| 2048 | |
| 2049 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) |
| 2050 | { |
| 2051 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2052 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG15; |
| 2053 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2054 | } |
| 2055 | |
| 2056 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) |
| 2057 | { |
| 2058 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2059 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG16; |
| 2060 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2061 | } |
| 2062 | |
| 2063 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) |
| 2064 | { |
| 2065 | uint32_t tmp; |
| 2066 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2067 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG16) >> DMAC_SWTRIGCTRL_SWTRIG16_Pos; |
| 2068 | return (bool)tmp; |
| 2069 | } |
| 2070 | |
| 2071 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG16_bit(const void *const hw, bool value) |
| 2072 | { |
| 2073 | uint32_t tmp; |
| 2074 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2075 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2076 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG16; |
| 2077 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG16_Pos; |
| 2078 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 2079 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2080 | } |
| 2081 | |
| 2082 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) |
| 2083 | { |
| 2084 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2085 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG16; |
| 2086 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2087 | } |
| 2088 | |
| 2089 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) |
| 2090 | { |
| 2091 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2092 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG16; |
| 2093 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2094 | } |
| 2095 | |
| 2096 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) |
| 2097 | { |
| 2098 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2099 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG17; |
| 2100 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2101 | } |
| 2102 | |
| 2103 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) |
| 2104 | { |
| 2105 | uint32_t tmp; |
| 2106 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2107 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG17) >> DMAC_SWTRIGCTRL_SWTRIG17_Pos; |
| 2108 | return (bool)tmp; |
| 2109 | } |
| 2110 | |
| 2111 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG17_bit(const void *const hw, bool value) |
| 2112 | { |
| 2113 | uint32_t tmp; |
| 2114 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2115 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2116 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG17; |
| 2117 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG17_Pos; |
| 2118 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 2119 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2120 | } |
| 2121 | |
| 2122 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) |
| 2123 | { |
| 2124 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2125 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG17; |
| 2126 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2127 | } |
| 2128 | |
| 2129 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) |
| 2130 | { |
| 2131 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2132 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG17; |
| 2133 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2134 | } |
| 2135 | |
| 2136 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) |
| 2137 | { |
| 2138 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2139 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG18; |
| 2140 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2141 | } |
| 2142 | |
| 2143 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) |
| 2144 | { |
| 2145 | uint32_t tmp; |
| 2146 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2147 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG18) >> DMAC_SWTRIGCTRL_SWTRIG18_Pos; |
| 2148 | return (bool)tmp; |
| 2149 | } |
| 2150 | |
| 2151 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG18_bit(const void *const hw, bool value) |
| 2152 | { |
| 2153 | uint32_t tmp; |
| 2154 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2155 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2156 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG18; |
| 2157 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG18_Pos; |
| 2158 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 2159 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2160 | } |
| 2161 | |
| 2162 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) |
| 2163 | { |
| 2164 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2165 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG18; |
| 2166 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2167 | } |
| 2168 | |
| 2169 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) |
| 2170 | { |
| 2171 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2172 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG18; |
| 2173 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2174 | } |
| 2175 | |
| 2176 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) |
| 2177 | { |
| 2178 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2179 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG19; |
| 2180 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2181 | } |
| 2182 | |
| 2183 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) |
| 2184 | { |
| 2185 | uint32_t tmp; |
| 2186 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2187 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG19) >> DMAC_SWTRIGCTRL_SWTRIG19_Pos; |
| 2188 | return (bool)tmp; |
| 2189 | } |
| 2190 | |
| 2191 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG19_bit(const void *const hw, bool value) |
| 2192 | { |
| 2193 | uint32_t tmp; |
| 2194 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2195 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2196 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG19; |
| 2197 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG19_Pos; |
| 2198 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 2199 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2200 | } |
| 2201 | |
| 2202 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) |
| 2203 | { |
| 2204 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2205 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG19; |
| 2206 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2207 | } |
| 2208 | |
| 2209 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) |
| 2210 | { |
| 2211 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2212 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG19; |
| 2213 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2214 | } |
| 2215 | |
| 2216 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) |
| 2217 | { |
| 2218 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2219 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG20; |
| 2220 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2221 | } |
| 2222 | |
| 2223 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) |
| 2224 | { |
| 2225 | uint32_t tmp; |
| 2226 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2227 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG20) >> DMAC_SWTRIGCTRL_SWTRIG20_Pos; |
| 2228 | return (bool)tmp; |
| 2229 | } |
| 2230 | |
| 2231 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG20_bit(const void *const hw, bool value) |
| 2232 | { |
| 2233 | uint32_t tmp; |
| 2234 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2235 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2236 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG20; |
| 2237 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG20_Pos; |
| 2238 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 2239 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2240 | } |
| 2241 | |
| 2242 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) |
| 2243 | { |
| 2244 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2245 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG20; |
| 2246 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2247 | } |
| 2248 | |
| 2249 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) |
| 2250 | { |
| 2251 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2252 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG20; |
| 2253 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2254 | } |
| 2255 | |
| 2256 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) |
| 2257 | { |
| 2258 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2259 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG21; |
| 2260 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2261 | } |
| 2262 | |
| 2263 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) |
| 2264 | { |
| 2265 | uint32_t tmp; |
| 2266 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2267 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG21) >> DMAC_SWTRIGCTRL_SWTRIG21_Pos; |
| 2268 | return (bool)tmp; |
| 2269 | } |
| 2270 | |
| 2271 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG21_bit(const void *const hw, bool value) |
| 2272 | { |
| 2273 | uint32_t tmp; |
| 2274 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2275 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2276 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG21; |
| 2277 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG21_Pos; |
| 2278 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 2279 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2280 | } |
| 2281 | |
| 2282 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) |
| 2283 | { |
| 2284 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2285 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG21; |
| 2286 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2287 | } |
| 2288 | |
| 2289 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) |
| 2290 | { |
| 2291 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2292 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG21; |
| 2293 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2294 | } |
| 2295 | |
| 2296 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) |
| 2297 | { |
| 2298 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2299 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG22; |
| 2300 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2301 | } |
| 2302 | |
| 2303 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) |
| 2304 | { |
| 2305 | uint32_t tmp; |
| 2306 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2307 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG22) >> DMAC_SWTRIGCTRL_SWTRIG22_Pos; |
| 2308 | return (bool)tmp; |
| 2309 | } |
| 2310 | |
| 2311 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG22_bit(const void *const hw, bool value) |
| 2312 | { |
| 2313 | uint32_t tmp; |
| 2314 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2315 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2316 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG22; |
| 2317 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG22_Pos; |
| 2318 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 2319 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2320 | } |
| 2321 | |
| 2322 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) |
| 2323 | { |
| 2324 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2325 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG22; |
| 2326 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2327 | } |
| 2328 | |
| 2329 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) |
| 2330 | { |
| 2331 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2332 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG22; |
| 2333 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2334 | } |
| 2335 | |
| 2336 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) |
| 2337 | { |
| 2338 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2339 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG23; |
| 2340 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2341 | } |
| 2342 | |
| 2343 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) |
| 2344 | { |
| 2345 | uint32_t tmp; |
| 2346 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2347 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG23) >> DMAC_SWTRIGCTRL_SWTRIG23_Pos; |
| 2348 | return (bool)tmp; |
| 2349 | } |
| 2350 | |
| 2351 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG23_bit(const void *const hw, bool value) |
| 2352 | { |
| 2353 | uint32_t tmp; |
| 2354 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2355 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2356 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG23; |
| 2357 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG23_Pos; |
| 2358 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 2359 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2360 | } |
| 2361 | |
| 2362 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) |
| 2363 | { |
| 2364 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2365 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG23; |
| 2366 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2367 | } |
| 2368 | |
| 2369 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) |
| 2370 | { |
| 2371 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2372 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG23; |
| 2373 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2374 | } |
| 2375 | |
| 2376 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) |
| 2377 | { |
| 2378 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2379 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG24; |
| 2380 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2381 | } |
| 2382 | |
| 2383 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) |
| 2384 | { |
| 2385 | uint32_t tmp; |
| 2386 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2387 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG24) >> DMAC_SWTRIGCTRL_SWTRIG24_Pos; |
| 2388 | return (bool)tmp; |
| 2389 | } |
| 2390 | |
| 2391 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG24_bit(const void *const hw, bool value) |
| 2392 | { |
| 2393 | uint32_t tmp; |
| 2394 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2395 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2396 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG24; |
| 2397 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG24_Pos; |
| 2398 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 2399 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2400 | } |
| 2401 | |
| 2402 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) |
| 2403 | { |
| 2404 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2405 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG24; |
| 2406 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2407 | } |
| 2408 | |
| 2409 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) |
| 2410 | { |
| 2411 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2412 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG24; |
| 2413 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2414 | } |
| 2415 | |
| 2416 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) |
| 2417 | { |
| 2418 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2419 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG25; |
| 2420 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2421 | } |
| 2422 | |
| 2423 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) |
| 2424 | { |
| 2425 | uint32_t tmp; |
| 2426 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2427 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG25) >> DMAC_SWTRIGCTRL_SWTRIG25_Pos; |
| 2428 | return (bool)tmp; |
| 2429 | } |
| 2430 | |
| 2431 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG25_bit(const void *const hw, bool value) |
| 2432 | { |
| 2433 | uint32_t tmp; |
| 2434 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2435 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2436 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG25; |
| 2437 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG25_Pos; |
| 2438 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 2439 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2440 | } |
| 2441 | |
| 2442 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) |
| 2443 | { |
| 2444 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2445 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG25; |
| 2446 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2447 | } |
| 2448 | |
| 2449 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) |
| 2450 | { |
| 2451 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2452 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG25; |
| 2453 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2454 | } |
| 2455 | |
| 2456 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) |
| 2457 | { |
| 2458 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2459 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG26; |
| 2460 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2461 | } |
| 2462 | |
| 2463 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) |
| 2464 | { |
| 2465 | uint32_t tmp; |
| 2466 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2467 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG26) >> DMAC_SWTRIGCTRL_SWTRIG26_Pos; |
| 2468 | return (bool)tmp; |
| 2469 | } |
| 2470 | |
| 2471 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG26_bit(const void *const hw, bool value) |
| 2472 | { |
| 2473 | uint32_t tmp; |
| 2474 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2475 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2476 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG26; |
| 2477 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG26_Pos; |
| 2478 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 2479 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2480 | } |
| 2481 | |
| 2482 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) |
| 2483 | { |
| 2484 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2485 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG26; |
| 2486 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2487 | } |
| 2488 | |
| 2489 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) |
| 2490 | { |
| 2491 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2492 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG26; |
| 2493 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2494 | } |
| 2495 | |
| 2496 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) |
| 2497 | { |
| 2498 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2499 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG27; |
| 2500 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2501 | } |
| 2502 | |
| 2503 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) |
| 2504 | { |
| 2505 | uint32_t tmp; |
| 2506 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2507 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG27) >> DMAC_SWTRIGCTRL_SWTRIG27_Pos; |
| 2508 | return (bool)tmp; |
| 2509 | } |
| 2510 | |
| 2511 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG27_bit(const void *const hw, bool value) |
| 2512 | { |
| 2513 | uint32_t tmp; |
| 2514 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2515 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2516 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG27; |
| 2517 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG27_Pos; |
| 2518 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 2519 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2520 | } |
| 2521 | |
| 2522 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) |
| 2523 | { |
| 2524 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2525 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG27; |
| 2526 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2527 | } |
| 2528 | |
| 2529 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) |
| 2530 | { |
| 2531 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2532 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG27; |
| 2533 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2534 | } |
| 2535 | |
| 2536 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) |
| 2537 | { |
| 2538 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2539 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG28; |
| 2540 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2541 | } |
| 2542 | |
| 2543 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) |
| 2544 | { |
| 2545 | uint32_t tmp; |
| 2546 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2547 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG28) >> DMAC_SWTRIGCTRL_SWTRIG28_Pos; |
| 2548 | return (bool)tmp; |
| 2549 | } |
| 2550 | |
| 2551 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG28_bit(const void *const hw, bool value) |
| 2552 | { |
| 2553 | uint32_t tmp; |
| 2554 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2555 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2556 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG28; |
| 2557 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG28_Pos; |
| 2558 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 2559 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2560 | } |
| 2561 | |
| 2562 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) |
| 2563 | { |
| 2564 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2565 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG28; |
| 2566 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2567 | } |
| 2568 | |
| 2569 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) |
| 2570 | { |
| 2571 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2572 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG28; |
| 2573 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2574 | } |
| 2575 | |
| 2576 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) |
| 2577 | { |
| 2578 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2579 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG29; |
| 2580 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2581 | } |
| 2582 | |
| 2583 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) |
| 2584 | { |
| 2585 | uint32_t tmp; |
| 2586 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2587 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG29) >> DMAC_SWTRIGCTRL_SWTRIG29_Pos; |
| 2588 | return (bool)tmp; |
| 2589 | } |
| 2590 | |
| 2591 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG29_bit(const void *const hw, bool value) |
| 2592 | { |
| 2593 | uint32_t tmp; |
| 2594 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2595 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2596 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG29; |
| 2597 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG29_Pos; |
| 2598 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 2599 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2600 | } |
| 2601 | |
| 2602 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) |
| 2603 | { |
| 2604 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2605 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG29; |
| 2606 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2607 | } |
| 2608 | |
| 2609 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) |
| 2610 | { |
| 2611 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2612 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG29; |
| 2613 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2614 | } |
| 2615 | |
| 2616 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) |
| 2617 | { |
| 2618 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2619 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG30; |
| 2620 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2621 | } |
| 2622 | |
| 2623 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) |
| 2624 | { |
| 2625 | uint32_t tmp; |
| 2626 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2627 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG30) >> DMAC_SWTRIGCTRL_SWTRIG30_Pos; |
| 2628 | return (bool)tmp; |
| 2629 | } |
| 2630 | |
| 2631 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG30_bit(const void *const hw, bool value) |
| 2632 | { |
| 2633 | uint32_t tmp; |
| 2634 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2635 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2636 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG30; |
| 2637 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG30_Pos; |
| 2638 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 2639 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2640 | } |
| 2641 | |
| 2642 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) |
| 2643 | { |
| 2644 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2645 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG30; |
| 2646 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2647 | } |
| 2648 | |
| 2649 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) |
| 2650 | { |
| 2651 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2652 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG30; |
| 2653 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2654 | } |
| 2655 | |
| 2656 | static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) |
| 2657 | { |
| 2658 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2659 | ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG31; |
| 2660 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2661 | } |
| 2662 | |
| 2663 | static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) |
| 2664 | { |
| 2665 | uint32_t tmp; |
| 2666 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2667 | tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG31) >> DMAC_SWTRIGCTRL_SWTRIG31_Pos; |
| 2668 | return (bool)tmp; |
| 2669 | } |
| 2670 | |
| 2671 | static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG31_bit(const void *const hw, bool value) |
| 2672 | { |
| 2673 | uint32_t tmp; |
| 2674 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2675 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2676 | tmp &= ~DMAC_SWTRIGCTRL_SWTRIG31; |
| 2677 | tmp |= value << DMAC_SWTRIGCTRL_SWTRIG31_Pos; |
| 2678 | ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; |
| 2679 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2680 | } |
| 2681 | |
| 2682 | static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) |
| 2683 | { |
| 2684 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2685 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG31; |
| 2686 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2687 | } |
| 2688 | |
| 2689 | static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) |
| 2690 | { |
| 2691 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2692 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG31; |
| 2693 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2694 | } |
| 2695 | |
| 2696 | static inline void hri_dmac_set_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) |
| 2697 | { |
| 2698 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2699 | ((Dmac *)hw)->SWTRIGCTRL.reg |= mask; |
| 2700 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2701 | } |
| 2702 | |
| 2703 | static inline hri_dmac_swtrigctrl_reg_t hri_dmac_get_SWTRIGCTRL_reg(const void *const hw, |
| 2704 | hri_dmac_swtrigctrl_reg_t mask) |
| 2705 | { |
| 2706 | uint32_t tmp; |
| 2707 | tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2708 | tmp &= mask; |
| 2709 | return tmp; |
| 2710 | } |
| 2711 | |
| 2712 | static inline void hri_dmac_write_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t data) |
| 2713 | { |
| 2714 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2715 | ((Dmac *)hw)->SWTRIGCTRL.reg = data; |
| 2716 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2717 | } |
| 2718 | |
| 2719 | static inline void hri_dmac_clear_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) |
| 2720 | { |
| 2721 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2722 | ((Dmac *)hw)->SWTRIGCTRL.reg &= ~mask; |
| 2723 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2724 | } |
| 2725 | |
| 2726 | static inline void hri_dmac_toggle_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) |
| 2727 | { |
| 2728 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2729 | ((Dmac *)hw)->SWTRIGCTRL.reg ^= mask; |
| 2730 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2731 | } |
| 2732 | |
| 2733 | static inline hri_dmac_swtrigctrl_reg_t hri_dmac_read_SWTRIGCTRL_reg(const void *const hw) |
| 2734 | { |
| 2735 | return ((Dmac *)hw)->SWTRIGCTRL.reg; |
| 2736 | } |
| 2737 | |
| 2738 | static inline void hri_dmac_set_PRICTRL0_RRLVLEN0_bit(const void *const hw) |
| 2739 | { |
| 2740 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2741 | ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN0; |
| 2742 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2743 | } |
| 2744 | |
| 2745 | static inline bool hri_dmac_get_PRICTRL0_RRLVLEN0_bit(const void *const hw) |
| 2746 | { |
| 2747 | uint32_t tmp; |
| 2748 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 2749 | tmp = (tmp & DMAC_PRICTRL0_RRLVLEN0) >> DMAC_PRICTRL0_RRLVLEN0_Pos; |
| 2750 | return (bool)tmp; |
| 2751 | } |
| 2752 | |
| 2753 | static inline void hri_dmac_write_PRICTRL0_RRLVLEN0_bit(const void *const hw, bool value) |
| 2754 | { |
| 2755 | uint32_t tmp; |
| 2756 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2757 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 2758 | tmp &= ~DMAC_PRICTRL0_RRLVLEN0; |
| 2759 | tmp |= value << DMAC_PRICTRL0_RRLVLEN0_Pos; |
| 2760 | ((Dmac *)hw)->PRICTRL0.reg = tmp; |
| 2761 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2762 | } |
| 2763 | |
| 2764 | static inline void hri_dmac_clear_PRICTRL0_RRLVLEN0_bit(const void *const hw) |
| 2765 | { |
| 2766 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2767 | ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN0; |
| 2768 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2769 | } |
| 2770 | |
| 2771 | static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN0_bit(const void *const hw) |
| 2772 | { |
| 2773 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2774 | ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN0; |
| 2775 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2776 | } |
| 2777 | |
| 2778 | static inline void hri_dmac_set_PRICTRL0_RRLVLEN1_bit(const void *const hw) |
| 2779 | { |
| 2780 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2781 | ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN1; |
| 2782 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2783 | } |
| 2784 | |
| 2785 | static inline bool hri_dmac_get_PRICTRL0_RRLVLEN1_bit(const void *const hw) |
| 2786 | { |
| 2787 | uint32_t tmp; |
| 2788 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 2789 | tmp = (tmp & DMAC_PRICTRL0_RRLVLEN1) >> DMAC_PRICTRL0_RRLVLEN1_Pos; |
| 2790 | return (bool)tmp; |
| 2791 | } |
| 2792 | |
| 2793 | static inline void hri_dmac_write_PRICTRL0_RRLVLEN1_bit(const void *const hw, bool value) |
| 2794 | { |
| 2795 | uint32_t tmp; |
| 2796 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2797 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 2798 | tmp &= ~DMAC_PRICTRL0_RRLVLEN1; |
| 2799 | tmp |= value << DMAC_PRICTRL0_RRLVLEN1_Pos; |
| 2800 | ((Dmac *)hw)->PRICTRL0.reg = tmp; |
| 2801 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2802 | } |
| 2803 | |
| 2804 | static inline void hri_dmac_clear_PRICTRL0_RRLVLEN1_bit(const void *const hw) |
| 2805 | { |
| 2806 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2807 | ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN1; |
| 2808 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2809 | } |
| 2810 | |
| 2811 | static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN1_bit(const void *const hw) |
| 2812 | { |
| 2813 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2814 | ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN1; |
| 2815 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2816 | } |
| 2817 | |
| 2818 | static inline void hri_dmac_set_PRICTRL0_RRLVLEN2_bit(const void *const hw) |
| 2819 | { |
| 2820 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2821 | ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN2; |
| 2822 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2823 | } |
| 2824 | |
| 2825 | static inline bool hri_dmac_get_PRICTRL0_RRLVLEN2_bit(const void *const hw) |
| 2826 | { |
| 2827 | uint32_t tmp; |
| 2828 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 2829 | tmp = (tmp & DMAC_PRICTRL0_RRLVLEN2) >> DMAC_PRICTRL0_RRLVLEN2_Pos; |
| 2830 | return (bool)tmp; |
| 2831 | } |
| 2832 | |
| 2833 | static inline void hri_dmac_write_PRICTRL0_RRLVLEN2_bit(const void *const hw, bool value) |
| 2834 | { |
| 2835 | uint32_t tmp; |
| 2836 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2837 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 2838 | tmp &= ~DMAC_PRICTRL0_RRLVLEN2; |
| 2839 | tmp |= value << DMAC_PRICTRL0_RRLVLEN2_Pos; |
| 2840 | ((Dmac *)hw)->PRICTRL0.reg = tmp; |
| 2841 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2842 | } |
| 2843 | |
| 2844 | static inline void hri_dmac_clear_PRICTRL0_RRLVLEN2_bit(const void *const hw) |
| 2845 | { |
| 2846 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2847 | ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN2; |
| 2848 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2849 | } |
| 2850 | |
| 2851 | static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN2_bit(const void *const hw) |
| 2852 | { |
| 2853 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2854 | ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN2; |
| 2855 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2856 | } |
| 2857 | |
| 2858 | static inline void hri_dmac_set_PRICTRL0_RRLVLEN3_bit(const void *const hw) |
| 2859 | { |
| 2860 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2861 | ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN3; |
| 2862 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2863 | } |
| 2864 | |
| 2865 | static inline bool hri_dmac_get_PRICTRL0_RRLVLEN3_bit(const void *const hw) |
| 2866 | { |
| 2867 | uint32_t tmp; |
| 2868 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 2869 | tmp = (tmp & DMAC_PRICTRL0_RRLVLEN3) >> DMAC_PRICTRL0_RRLVLEN3_Pos; |
| 2870 | return (bool)tmp; |
| 2871 | } |
| 2872 | |
| 2873 | static inline void hri_dmac_write_PRICTRL0_RRLVLEN3_bit(const void *const hw, bool value) |
| 2874 | { |
| 2875 | uint32_t tmp; |
| 2876 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2877 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 2878 | tmp &= ~DMAC_PRICTRL0_RRLVLEN3; |
| 2879 | tmp |= value << DMAC_PRICTRL0_RRLVLEN3_Pos; |
| 2880 | ((Dmac *)hw)->PRICTRL0.reg = tmp; |
| 2881 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2882 | } |
| 2883 | |
| 2884 | static inline void hri_dmac_clear_PRICTRL0_RRLVLEN3_bit(const void *const hw) |
| 2885 | { |
| 2886 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2887 | ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN3; |
| 2888 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2889 | } |
| 2890 | |
| 2891 | static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN3_bit(const void *const hw) |
| 2892 | { |
| 2893 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2894 | ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN3; |
| 2895 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2896 | } |
| 2897 | |
| 2898 | static inline void hri_dmac_set_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 2899 | { |
| 2900 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2901 | ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI0(mask); |
| 2902 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2903 | } |
| 2904 | |
| 2905 | static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI0_bf(const void *const hw, |
| 2906 | hri_dmac_prictrl0_reg_t mask) |
| 2907 | { |
| 2908 | uint32_t tmp; |
| 2909 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 2910 | tmp = (tmp & DMAC_PRICTRL0_LVLPRI0(mask)) >> DMAC_PRICTRL0_LVLPRI0_Pos; |
| 2911 | return tmp; |
| 2912 | } |
| 2913 | |
| 2914 | static inline void hri_dmac_write_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) |
| 2915 | { |
| 2916 | uint32_t tmp; |
| 2917 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2918 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 2919 | tmp &= ~DMAC_PRICTRL0_LVLPRI0_Msk; |
| 2920 | tmp |= DMAC_PRICTRL0_LVLPRI0(data); |
| 2921 | ((Dmac *)hw)->PRICTRL0.reg = tmp; |
| 2922 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2923 | } |
| 2924 | |
| 2925 | static inline void hri_dmac_clear_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 2926 | { |
| 2927 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2928 | ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI0(mask); |
| 2929 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2930 | } |
| 2931 | |
| 2932 | static inline void hri_dmac_toggle_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 2933 | { |
| 2934 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2935 | ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI0(mask); |
| 2936 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2937 | } |
| 2938 | |
| 2939 | static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI0_bf(const void *const hw) |
| 2940 | { |
| 2941 | uint32_t tmp; |
| 2942 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 2943 | tmp = (tmp & DMAC_PRICTRL0_LVLPRI0_Msk) >> DMAC_PRICTRL0_LVLPRI0_Pos; |
| 2944 | return tmp; |
| 2945 | } |
| 2946 | |
| 2947 | static inline void hri_dmac_set_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 2948 | { |
| 2949 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2950 | ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS0(mask); |
| 2951 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2952 | } |
| 2953 | |
| 2954 | static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 2955 | { |
| 2956 | uint32_t tmp; |
| 2957 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 2958 | tmp = (tmp & DMAC_PRICTRL0_QOS0(mask)) >> DMAC_PRICTRL0_QOS0_Pos; |
| 2959 | return tmp; |
| 2960 | } |
| 2961 | |
| 2962 | static inline void hri_dmac_write_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) |
| 2963 | { |
| 2964 | uint32_t tmp; |
| 2965 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2966 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 2967 | tmp &= ~DMAC_PRICTRL0_QOS0_Msk; |
| 2968 | tmp |= DMAC_PRICTRL0_QOS0(data); |
| 2969 | ((Dmac *)hw)->PRICTRL0.reg = tmp; |
| 2970 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2971 | } |
| 2972 | |
| 2973 | static inline void hri_dmac_clear_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 2974 | { |
| 2975 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2976 | ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS0(mask); |
| 2977 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2978 | } |
| 2979 | |
| 2980 | static inline void hri_dmac_toggle_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 2981 | { |
| 2982 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2983 | ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS0(mask); |
| 2984 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 2985 | } |
| 2986 | |
| 2987 | static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS0_bf(const void *const hw) |
| 2988 | { |
| 2989 | uint32_t tmp; |
| 2990 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 2991 | tmp = (tmp & DMAC_PRICTRL0_QOS0_Msk) >> DMAC_PRICTRL0_QOS0_Pos; |
| 2992 | return tmp; |
| 2993 | } |
| 2994 | |
| 2995 | static inline void hri_dmac_set_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 2996 | { |
| 2997 | DMAC_CRITICAL_SECTION_ENTER(); |
| 2998 | ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI1(mask); |
| 2999 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3000 | } |
| 3001 | |
| 3002 | static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI1_bf(const void *const hw, |
| 3003 | hri_dmac_prictrl0_reg_t mask) |
| 3004 | { |
| 3005 | uint32_t tmp; |
| 3006 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 3007 | tmp = (tmp & DMAC_PRICTRL0_LVLPRI1(mask)) >> DMAC_PRICTRL0_LVLPRI1_Pos; |
| 3008 | return tmp; |
| 3009 | } |
| 3010 | |
| 3011 | static inline void hri_dmac_write_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) |
| 3012 | { |
| 3013 | uint32_t tmp; |
| 3014 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3015 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 3016 | tmp &= ~DMAC_PRICTRL0_LVLPRI1_Msk; |
| 3017 | tmp |= DMAC_PRICTRL0_LVLPRI1(data); |
| 3018 | ((Dmac *)hw)->PRICTRL0.reg = tmp; |
| 3019 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3020 | } |
| 3021 | |
| 3022 | static inline void hri_dmac_clear_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 3023 | { |
| 3024 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3025 | ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI1(mask); |
| 3026 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3027 | } |
| 3028 | |
| 3029 | static inline void hri_dmac_toggle_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 3030 | { |
| 3031 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3032 | ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI1(mask); |
| 3033 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3034 | } |
| 3035 | |
| 3036 | static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI1_bf(const void *const hw) |
| 3037 | { |
| 3038 | uint32_t tmp; |
| 3039 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 3040 | tmp = (tmp & DMAC_PRICTRL0_LVLPRI1_Msk) >> DMAC_PRICTRL0_LVLPRI1_Pos; |
| 3041 | return tmp; |
| 3042 | } |
| 3043 | |
| 3044 | static inline void hri_dmac_set_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 3045 | { |
| 3046 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3047 | ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS1(mask); |
| 3048 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3049 | } |
| 3050 | |
| 3051 | static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 3052 | { |
| 3053 | uint32_t tmp; |
| 3054 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 3055 | tmp = (tmp & DMAC_PRICTRL0_QOS1(mask)) >> DMAC_PRICTRL0_QOS1_Pos; |
| 3056 | return tmp; |
| 3057 | } |
| 3058 | |
| 3059 | static inline void hri_dmac_write_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) |
| 3060 | { |
| 3061 | uint32_t tmp; |
| 3062 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3063 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 3064 | tmp &= ~DMAC_PRICTRL0_QOS1_Msk; |
| 3065 | tmp |= DMAC_PRICTRL0_QOS1(data); |
| 3066 | ((Dmac *)hw)->PRICTRL0.reg = tmp; |
| 3067 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3068 | } |
| 3069 | |
| 3070 | static inline void hri_dmac_clear_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 3071 | { |
| 3072 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3073 | ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS1(mask); |
| 3074 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3075 | } |
| 3076 | |
| 3077 | static inline void hri_dmac_toggle_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 3078 | { |
| 3079 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3080 | ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS1(mask); |
| 3081 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3082 | } |
| 3083 | |
| 3084 | static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS1_bf(const void *const hw) |
| 3085 | { |
| 3086 | uint32_t tmp; |
| 3087 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 3088 | tmp = (tmp & DMAC_PRICTRL0_QOS1_Msk) >> DMAC_PRICTRL0_QOS1_Pos; |
| 3089 | return tmp; |
| 3090 | } |
| 3091 | |
| 3092 | static inline void hri_dmac_set_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 3093 | { |
| 3094 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3095 | ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI2(mask); |
| 3096 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3097 | } |
| 3098 | |
| 3099 | static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI2_bf(const void *const hw, |
| 3100 | hri_dmac_prictrl0_reg_t mask) |
| 3101 | { |
| 3102 | uint32_t tmp; |
| 3103 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 3104 | tmp = (tmp & DMAC_PRICTRL0_LVLPRI2(mask)) >> DMAC_PRICTRL0_LVLPRI2_Pos; |
| 3105 | return tmp; |
| 3106 | } |
| 3107 | |
| 3108 | static inline void hri_dmac_write_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) |
| 3109 | { |
| 3110 | uint32_t tmp; |
| 3111 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3112 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 3113 | tmp &= ~DMAC_PRICTRL0_LVLPRI2_Msk; |
| 3114 | tmp |= DMAC_PRICTRL0_LVLPRI2(data); |
| 3115 | ((Dmac *)hw)->PRICTRL0.reg = tmp; |
| 3116 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3117 | } |
| 3118 | |
| 3119 | static inline void hri_dmac_clear_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 3120 | { |
| 3121 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3122 | ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI2(mask); |
| 3123 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3124 | } |
| 3125 | |
| 3126 | static inline void hri_dmac_toggle_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 3127 | { |
| 3128 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3129 | ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI2(mask); |
| 3130 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3131 | } |
| 3132 | |
| 3133 | static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI2_bf(const void *const hw) |
| 3134 | { |
| 3135 | uint32_t tmp; |
| 3136 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 3137 | tmp = (tmp & DMAC_PRICTRL0_LVLPRI2_Msk) >> DMAC_PRICTRL0_LVLPRI2_Pos; |
| 3138 | return tmp; |
| 3139 | } |
| 3140 | |
| 3141 | static inline void hri_dmac_set_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 3142 | { |
| 3143 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3144 | ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS2(mask); |
| 3145 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3146 | } |
| 3147 | |
| 3148 | static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 3149 | { |
| 3150 | uint32_t tmp; |
| 3151 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 3152 | tmp = (tmp & DMAC_PRICTRL0_QOS2(mask)) >> DMAC_PRICTRL0_QOS2_Pos; |
| 3153 | return tmp; |
| 3154 | } |
| 3155 | |
| 3156 | static inline void hri_dmac_write_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) |
| 3157 | { |
| 3158 | uint32_t tmp; |
| 3159 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3160 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 3161 | tmp &= ~DMAC_PRICTRL0_QOS2_Msk; |
| 3162 | tmp |= DMAC_PRICTRL0_QOS2(data); |
| 3163 | ((Dmac *)hw)->PRICTRL0.reg = tmp; |
| 3164 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3165 | } |
| 3166 | |
| 3167 | static inline void hri_dmac_clear_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 3168 | { |
| 3169 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3170 | ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS2(mask); |
| 3171 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3172 | } |
| 3173 | |
| 3174 | static inline void hri_dmac_toggle_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 3175 | { |
| 3176 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3177 | ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS2(mask); |
| 3178 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3179 | } |
| 3180 | |
| 3181 | static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS2_bf(const void *const hw) |
| 3182 | { |
| 3183 | uint32_t tmp; |
| 3184 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 3185 | tmp = (tmp & DMAC_PRICTRL0_QOS2_Msk) >> DMAC_PRICTRL0_QOS2_Pos; |
| 3186 | return tmp; |
| 3187 | } |
| 3188 | |
| 3189 | static inline void hri_dmac_set_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 3190 | { |
| 3191 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3192 | ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI3(mask); |
| 3193 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3194 | } |
| 3195 | |
| 3196 | static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI3_bf(const void *const hw, |
| 3197 | hri_dmac_prictrl0_reg_t mask) |
| 3198 | { |
| 3199 | uint32_t tmp; |
| 3200 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 3201 | tmp = (tmp & DMAC_PRICTRL0_LVLPRI3(mask)) >> DMAC_PRICTRL0_LVLPRI3_Pos; |
| 3202 | return tmp; |
| 3203 | } |
| 3204 | |
| 3205 | static inline void hri_dmac_write_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) |
| 3206 | { |
| 3207 | uint32_t tmp; |
| 3208 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3209 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 3210 | tmp &= ~DMAC_PRICTRL0_LVLPRI3_Msk; |
| 3211 | tmp |= DMAC_PRICTRL0_LVLPRI3(data); |
| 3212 | ((Dmac *)hw)->PRICTRL0.reg = tmp; |
| 3213 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3214 | } |
| 3215 | |
| 3216 | static inline void hri_dmac_clear_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 3217 | { |
| 3218 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3219 | ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI3(mask); |
| 3220 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3221 | } |
| 3222 | |
| 3223 | static inline void hri_dmac_toggle_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 3224 | { |
| 3225 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3226 | ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI3(mask); |
| 3227 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3228 | } |
| 3229 | |
| 3230 | static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI3_bf(const void *const hw) |
| 3231 | { |
| 3232 | uint32_t tmp; |
| 3233 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 3234 | tmp = (tmp & DMAC_PRICTRL0_LVLPRI3_Msk) >> DMAC_PRICTRL0_LVLPRI3_Pos; |
| 3235 | return tmp; |
| 3236 | } |
| 3237 | |
| 3238 | static inline void hri_dmac_set_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 3239 | { |
| 3240 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3241 | ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS3(mask); |
| 3242 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3243 | } |
| 3244 | |
| 3245 | static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 3246 | { |
| 3247 | uint32_t tmp; |
| 3248 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 3249 | tmp = (tmp & DMAC_PRICTRL0_QOS3(mask)) >> DMAC_PRICTRL0_QOS3_Pos; |
| 3250 | return tmp; |
| 3251 | } |
| 3252 | |
| 3253 | static inline void hri_dmac_write_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) |
| 3254 | { |
| 3255 | uint32_t tmp; |
| 3256 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3257 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 3258 | tmp &= ~DMAC_PRICTRL0_QOS3_Msk; |
| 3259 | tmp |= DMAC_PRICTRL0_QOS3(data); |
| 3260 | ((Dmac *)hw)->PRICTRL0.reg = tmp; |
| 3261 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3262 | } |
| 3263 | |
| 3264 | static inline void hri_dmac_clear_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 3265 | { |
| 3266 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3267 | ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS3(mask); |
| 3268 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3269 | } |
| 3270 | |
| 3271 | static inline void hri_dmac_toggle_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 3272 | { |
| 3273 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3274 | ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS3(mask); |
| 3275 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3276 | } |
| 3277 | |
| 3278 | static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS3_bf(const void *const hw) |
| 3279 | { |
| 3280 | uint32_t tmp; |
| 3281 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 3282 | tmp = (tmp & DMAC_PRICTRL0_QOS3_Msk) >> DMAC_PRICTRL0_QOS3_Pos; |
| 3283 | return tmp; |
| 3284 | } |
| 3285 | |
| 3286 | static inline void hri_dmac_set_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 3287 | { |
| 3288 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3289 | ((Dmac *)hw)->PRICTRL0.reg |= mask; |
| 3290 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3291 | } |
| 3292 | |
| 3293 | static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 3294 | { |
| 3295 | uint32_t tmp; |
| 3296 | tmp = ((Dmac *)hw)->PRICTRL0.reg; |
| 3297 | tmp &= mask; |
| 3298 | return tmp; |
| 3299 | } |
| 3300 | |
| 3301 | static inline void hri_dmac_write_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t data) |
| 3302 | { |
| 3303 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3304 | ((Dmac *)hw)->PRICTRL0.reg = data; |
| 3305 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3306 | } |
| 3307 | |
| 3308 | static inline void hri_dmac_clear_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 3309 | { |
| 3310 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3311 | ((Dmac *)hw)->PRICTRL0.reg &= ~mask; |
| 3312 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3313 | } |
| 3314 | |
| 3315 | static inline void hri_dmac_toggle_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) |
| 3316 | { |
| 3317 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3318 | ((Dmac *)hw)->PRICTRL0.reg ^= mask; |
| 3319 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3320 | } |
| 3321 | |
| 3322 | static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_reg(const void *const hw) |
| 3323 | { |
| 3324 | return ((Dmac *)hw)->PRICTRL0.reg; |
| 3325 | } |
| 3326 | |
| 3327 | static inline void hri_dmac_set_INTPEND_TERR_bit(const void *const hw) |
| 3328 | { |
| 3329 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3330 | ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TERR; |
| 3331 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3332 | } |
| 3333 | |
| 3334 | static inline bool hri_dmac_get_INTPEND_TERR_bit(const void *const hw) |
| 3335 | { |
| 3336 | uint16_t tmp; |
| 3337 | tmp = ((Dmac *)hw)->INTPEND.reg; |
| 3338 | tmp = (tmp & DMAC_INTPEND_TERR) >> DMAC_INTPEND_TERR_Pos; |
| 3339 | return (bool)tmp; |
| 3340 | } |
| 3341 | |
| 3342 | static inline void hri_dmac_write_INTPEND_TERR_bit(const void *const hw, bool value) |
| 3343 | { |
| 3344 | uint16_t tmp; |
| 3345 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3346 | tmp = ((Dmac *)hw)->INTPEND.reg; |
| 3347 | tmp &= ~DMAC_INTPEND_TERR; |
| 3348 | tmp |= value << DMAC_INTPEND_TERR_Pos; |
| 3349 | ((Dmac *)hw)->INTPEND.reg = tmp; |
| 3350 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3351 | } |
| 3352 | |
| 3353 | static inline void hri_dmac_clear_INTPEND_TERR_bit(const void *const hw) |
| 3354 | { |
| 3355 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3356 | ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TERR; |
| 3357 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3358 | } |
| 3359 | |
| 3360 | static inline void hri_dmac_toggle_INTPEND_TERR_bit(const void *const hw) |
| 3361 | { |
| 3362 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3363 | ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TERR; |
| 3364 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3365 | } |
| 3366 | |
| 3367 | static inline void hri_dmac_set_INTPEND_TCMPL_bit(const void *const hw) |
| 3368 | { |
| 3369 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3370 | ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TCMPL; |
| 3371 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3372 | } |
| 3373 | |
| 3374 | static inline bool hri_dmac_get_INTPEND_TCMPL_bit(const void *const hw) |
| 3375 | { |
| 3376 | uint16_t tmp; |
| 3377 | tmp = ((Dmac *)hw)->INTPEND.reg; |
| 3378 | tmp = (tmp & DMAC_INTPEND_TCMPL) >> DMAC_INTPEND_TCMPL_Pos; |
| 3379 | return (bool)tmp; |
| 3380 | } |
| 3381 | |
| 3382 | static inline void hri_dmac_write_INTPEND_TCMPL_bit(const void *const hw, bool value) |
| 3383 | { |
| 3384 | uint16_t tmp; |
| 3385 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3386 | tmp = ((Dmac *)hw)->INTPEND.reg; |
| 3387 | tmp &= ~DMAC_INTPEND_TCMPL; |
| 3388 | tmp |= value << DMAC_INTPEND_TCMPL_Pos; |
| 3389 | ((Dmac *)hw)->INTPEND.reg = tmp; |
| 3390 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3391 | } |
| 3392 | |
| 3393 | static inline void hri_dmac_clear_INTPEND_TCMPL_bit(const void *const hw) |
| 3394 | { |
| 3395 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3396 | ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TCMPL; |
| 3397 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3398 | } |
| 3399 | |
| 3400 | static inline void hri_dmac_toggle_INTPEND_TCMPL_bit(const void *const hw) |
| 3401 | { |
| 3402 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3403 | ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TCMPL; |
| 3404 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3405 | } |
| 3406 | |
| 3407 | static inline void hri_dmac_set_INTPEND_SUSP_bit(const void *const hw) |
| 3408 | { |
| 3409 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3410 | ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_SUSP; |
| 3411 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3412 | } |
| 3413 | |
| 3414 | static inline bool hri_dmac_get_INTPEND_SUSP_bit(const void *const hw) |
| 3415 | { |
| 3416 | uint16_t tmp; |
| 3417 | tmp = ((Dmac *)hw)->INTPEND.reg; |
| 3418 | tmp = (tmp & DMAC_INTPEND_SUSP) >> DMAC_INTPEND_SUSP_Pos; |
| 3419 | return (bool)tmp; |
| 3420 | } |
| 3421 | |
| 3422 | static inline void hri_dmac_write_INTPEND_SUSP_bit(const void *const hw, bool value) |
| 3423 | { |
| 3424 | uint16_t tmp; |
| 3425 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3426 | tmp = ((Dmac *)hw)->INTPEND.reg; |
| 3427 | tmp &= ~DMAC_INTPEND_SUSP; |
| 3428 | tmp |= value << DMAC_INTPEND_SUSP_Pos; |
| 3429 | ((Dmac *)hw)->INTPEND.reg = tmp; |
| 3430 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3431 | } |
| 3432 | |
| 3433 | static inline void hri_dmac_clear_INTPEND_SUSP_bit(const void *const hw) |
| 3434 | { |
| 3435 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3436 | ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_SUSP; |
| 3437 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3438 | } |
| 3439 | |
| 3440 | static inline void hri_dmac_toggle_INTPEND_SUSP_bit(const void *const hw) |
| 3441 | { |
| 3442 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3443 | ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_SUSP; |
| 3444 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3445 | } |
| 3446 | |
| 3447 | static inline void hri_dmac_set_INTPEND_CRCERR_bit(const void *const hw) |
| 3448 | { |
| 3449 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3450 | ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_CRCERR; |
| 3451 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3452 | } |
| 3453 | |
| 3454 | static inline bool hri_dmac_get_INTPEND_CRCERR_bit(const void *const hw) |
| 3455 | { |
| 3456 | uint16_t tmp; |
| 3457 | tmp = ((Dmac *)hw)->INTPEND.reg; |
| 3458 | tmp = (tmp & DMAC_INTPEND_CRCERR) >> DMAC_INTPEND_CRCERR_Pos; |
| 3459 | return (bool)tmp; |
| 3460 | } |
| 3461 | |
| 3462 | static inline void hri_dmac_write_INTPEND_CRCERR_bit(const void *const hw, bool value) |
| 3463 | { |
| 3464 | uint16_t tmp; |
| 3465 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3466 | tmp = ((Dmac *)hw)->INTPEND.reg; |
| 3467 | tmp &= ~DMAC_INTPEND_CRCERR; |
| 3468 | tmp |= value << DMAC_INTPEND_CRCERR_Pos; |
| 3469 | ((Dmac *)hw)->INTPEND.reg = tmp; |
| 3470 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3471 | } |
| 3472 | |
| 3473 | static inline void hri_dmac_clear_INTPEND_CRCERR_bit(const void *const hw) |
| 3474 | { |
| 3475 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3476 | ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_CRCERR; |
| 3477 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3478 | } |
| 3479 | |
| 3480 | static inline void hri_dmac_toggle_INTPEND_CRCERR_bit(const void *const hw) |
| 3481 | { |
| 3482 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3483 | ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_CRCERR; |
| 3484 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3485 | } |
| 3486 | |
| 3487 | static inline void hri_dmac_set_INTPEND_FERR_bit(const void *const hw) |
| 3488 | { |
| 3489 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3490 | ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_FERR; |
| 3491 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3492 | } |
| 3493 | |
| 3494 | static inline bool hri_dmac_get_INTPEND_FERR_bit(const void *const hw) |
| 3495 | { |
| 3496 | uint16_t tmp; |
| 3497 | tmp = ((Dmac *)hw)->INTPEND.reg; |
| 3498 | tmp = (tmp & DMAC_INTPEND_FERR) >> DMAC_INTPEND_FERR_Pos; |
| 3499 | return (bool)tmp; |
| 3500 | } |
| 3501 | |
| 3502 | static inline void hri_dmac_write_INTPEND_FERR_bit(const void *const hw, bool value) |
| 3503 | { |
| 3504 | uint16_t tmp; |
| 3505 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3506 | tmp = ((Dmac *)hw)->INTPEND.reg; |
| 3507 | tmp &= ~DMAC_INTPEND_FERR; |
| 3508 | tmp |= value << DMAC_INTPEND_FERR_Pos; |
| 3509 | ((Dmac *)hw)->INTPEND.reg = tmp; |
| 3510 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3511 | } |
| 3512 | |
| 3513 | static inline void hri_dmac_clear_INTPEND_FERR_bit(const void *const hw) |
| 3514 | { |
| 3515 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3516 | ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_FERR; |
| 3517 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3518 | } |
| 3519 | |
| 3520 | static inline void hri_dmac_toggle_INTPEND_FERR_bit(const void *const hw) |
| 3521 | { |
| 3522 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3523 | ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_FERR; |
| 3524 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3525 | } |
| 3526 | |
| 3527 | static inline void hri_dmac_set_INTPEND_BUSY_bit(const void *const hw) |
| 3528 | { |
| 3529 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3530 | ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_BUSY; |
| 3531 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3532 | } |
| 3533 | |
| 3534 | static inline bool hri_dmac_get_INTPEND_BUSY_bit(const void *const hw) |
| 3535 | { |
| 3536 | uint16_t tmp; |
| 3537 | tmp = ((Dmac *)hw)->INTPEND.reg; |
| 3538 | tmp = (tmp & DMAC_INTPEND_BUSY) >> DMAC_INTPEND_BUSY_Pos; |
| 3539 | return (bool)tmp; |
| 3540 | } |
| 3541 | |
| 3542 | static inline void hri_dmac_write_INTPEND_BUSY_bit(const void *const hw, bool value) |
| 3543 | { |
| 3544 | uint16_t tmp; |
| 3545 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3546 | tmp = ((Dmac *)hw)->INTPEND.reg; |
| 3547 | tmp &= ~DMAC_INTPEND_BUSY; |
| 3548 | tmp |= value << DMAC_INTPEND_BUSY_Pos; |
| 3549 | ((Dmac *)hw)->INTPEND.reg = tmp; |
| 3550 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3551 | } |
| 3552 | |
| 3553 | static inline void hri_dmac_clear_INTPEND_BUSY_bit(const void *const hw) |
| 3554 | { |
| 3555 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3556 | ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_BUSY; |
| 3557 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3558 | } |
| 3559 | |
| 3560 | static inline void hri_dmac_toggle_INTPEND_BUSY_bit(const void *const hw) |
| 3561 | { |
| 3562 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3563 | ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_BUSY; |
| 3564 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3565 | } |
| 3566 | |
| 3567 | static inline void hri_dmac_set_INTPEND_PEND_bit(const void *const hw) |
| 3568 | { |
| 3569 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3570 | ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_PEND; |
| 3571 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3572 | } |
| 3573 | |
| 3574 | static inline bool hri_dmac_get_INTPEND_PEND_bit(const void *const hw) |
| 3575 | { |
| 3576 | uint16_t tmp; |
| 3577 | tmp = ((Dmac *)hw)->INTPEND.reg; |
| 3578 | tmp = (tmp & DMAC_INTPEND_PEND) >> DMAC_INTPEND_PEND_Pos; |
| 3579 | return (bool)tmp; |
| 3580 | } |
| 3581 | |
| 3582 | static inline void hri_dmac_write_INTPEND_PEND_bit(const void *const hw, bool value) |
| 3583 | { |
| 3584 | uint16_t tmp; |
| 3585 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3586 | tmp = ((Dmac *)hw)->INTPEND.reg; |
| 3587 | tmp &= ~DMAC_INTPEND_PEND; |
| 3588 | tmp |= value << DMAC_INTPEND_PEND_Pos; |
| 3589 | ((Dmac *)hw)->INTPEND.reg = tmp; |
| 3590 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3591 | } |
| 3592 | |
| 3593 | static inline void hri_dmac_clear_INTPEND_PEND_bit(const void *const hw) |
| 3594 | { |
| 3595 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3596 | ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_PEND; |
| 3597 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3598 | } |
| 3599 | |
| 3600 | static inline void hri_dmac_toggle_INTPEND_PEND_bit(const void *const hw) |
| 3601 | { |
| 3602 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3603 | ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_PEND; |
| 3604 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3605 | } |
| 3606 | |
| 3607 | static inline void hri_dmac_set_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) |
| 3608 | { |
| 3609 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3610 | ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_ID(mask); |
| 3611 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3612 | } |
| 3613 | |
| 3614 | static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) |
| 3615 | { |
| 3616 | uint16_t tmp; |
| 3617 | tmp = ((Dmac *)hw)->INTPEND.reg; |
| 3618 | tmp = (tmp & DMAC_INTPEND_ID(mask)) >> DMAC_INTPEND_ID_Pos; |
| 3619 | return tmp; |
| 3620 | } |
| 3621 | |
| 3622 | static inline void hri_dmac_write_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t data) |
| 3623 | { |
| 3624 | uint16_t tmp; |
| 3625 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3626 | tmp = ((Dmac *)hw)->INTPEND.reg; |
| 3627 | tmp &= ~DMAC_INTPEND_ID_Msk; |
| 3628 | tmp |= DMAC_INTPEND_ID(data); |
| 3629 | ((Dmac *)hw)->INTPEND.reg = tmp; |
| 3630 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3631 | } |
| 3632 | |
| 3633 | static inline void hri_dmac_clear_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) |
| 3634 | { |
| 3635 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3636 | ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_ID(mask); |
| 3637 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3638 | } |
| 3639 | |
| 3640 | static inline void hri_dmac_toggle_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) |
| 3641 | { |
| 3642 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3643 | ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_ID(mask); |
| 3644 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3645 | } |
| 3646 | |
| 3647 | static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_ID_bf(const void *const hw) |
| 3648 | { |
| 3649 | uint16_t tmp; |
| 3650 | tmp = ((Dmac *)hw)->INTPEND.reg; |
| 3651 | tmp = (tmp & DMAC_INTPEND_ID_Msk) >> DMAC_INTPEND_ID_Pos; |
| 3652 | return tmp; |
| 3653 | } |
| 3654 | |
| 3655 | static inline void hri_dmac_set_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) |
| 3656 | { |
| 3657 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3658 | ((Dmac *)hw)->INTPEND.reg |= mask; |
| 3659 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3660 | } |
| 3661 | |
| 3662 | static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) |
| 3663 | { |
| 3664 | uint16_t tmp; |
| 3665 | tmp = ((Dmac *)hw)->INTPEND.reg; |
| 3666 | tmp &= mask; |
| 3667 | return tmp; |
| 3668 | } |
| 3669 | |
| 3670 | static inline void hri_dmac_write_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t data) |
| 3671 | { |
| 3672 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3673 | ((Dmac *)hw)->INTPEND.reg = data; |
| 3674 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3675 | } |
| 3676 | |
| 3677 | static inline void hri_dmac_clear_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) |
| 3678 | { |
| 3679 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3680 | ((Dmac *)hw)->INTPEND.reg &= ~mask; |
| 3681 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3682 | } |
| 3683 | |
| 3684 | static inline void hri_dmac_toggle_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) |
| 3685 | { |
| 3686 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3687 | ((Dmac *)hw)->INTPEND.reg ^= mask; |
| 3688 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3689 | } |
| 3690 | |
| 3691 | static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_reg(const void *const hw) |
| 3692 | { |
| 3693 | return ((Dmac *)hw)->INTPEND.reg; |
| 3694 | } |
| 3695 | |
| 3696 | static inline void hri_dmac_set_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) |
| 3697 | { |
| 3698 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3699 | ((Dmac *)hw)->BASEADDR.reg |= DMAC_BASEADDR_BASEADDR(mask); |
| 3700 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3701 | } |
| 3702 | |
| 3703 | static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_BASEADDR_bf(const void *const hw, |
| 3704 | hri_dmac_baseaddr_reg_t mask) |
| 3705 | { |
| 3706 | uint32_t tmp; |
| 3707 | tmp = ((Dmac *)hw)->BASEADDR.reg; |
| 3708 | tmp = (tmp & DMAC_BASEADDR_BASEADDR(mask)) >> DMAC_BASEADDR_BASEADDR_Pos; |
| 3709 | return tmp; |
| 3710 | } |
| 3711 | |
| 3712 | static inline void hri_dmac_write_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t data) |
| 3713 | { |
| 3714 | uint32_t tmp; |
| 3715 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3716 | tmp = ((Dmac *)hw)->BASEADDR.reg; |
| 3717 | tmp &= ~DMAC_BASEADDR_BASEADDR_Msk; |
| 3718 | tmp |= DMAC_BASEADDR_BASEADDR(data); |
| 3719 | ((Dmac *)hw)->BASEADDR.reg = tmp; |
| 3720 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3721 | } |
| 3722 | |
| 3723 | static inline void hri_dmac_clear_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) |
| 3724 | { |
| 3725 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3726 | ((Dmac *)hw)->BASEADDR.reg &= ~DMAC_BASEADDR_BASEADDR(mask); |
| 3727 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3728 | } |
| 3729 | |
| 3730 | static inline void hri_dmac_toggle_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) |
| 3731 | { |
| 3732 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3733 | ((Dmac *)hw)->BASEADDR.reg ^= DMAC_BASEADDR_BASEADDR(mask); |
| 3734 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3735 | } |
| 3736 | |
| 3737 | static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_BASEADDR_bf(const void *const hw) |
| 3738 | { |
| 3739 | uint32_t tmp; |
| 3740 | tmp = ((Dmac *)hw)->BASEADDR.reg; |
| 3741 | tmp = (tmp & DMAC_BASEADDR_BASEADDR_Msk) >> DMAC_BASEADDR_BASEADDR_Pos; |
| 3742 | return tmp; |
| 3743 | } |
| 3744 | |
| 3745 | static inline void hri_dmac_set_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) |
| 3746 | { |
| 3747 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3748 | ((Dmac *)hw)->BASEADDR.reg |= mask; |
| 3749 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3750 | } |
| 3751 | |
| 3752 | static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) |
| 3753 | { |
| 3754 | uint32_t tmp; |
| 3755 | tmp = ((Dmac *)hw)->BASEADDR.reg; |
| 3756 | tmp &= mask; |
| 3757 | return tmp; |
| 3758 | } |
| 3759 | |
| 3760 | static inline void hri_dmac_write_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t data) |
| 3761 | { |
| 3762 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3763 | ((Dmac *)hw)->BASEADDR.reg = data; |
| 3764 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3765 | } |
| 3766 | |
| 3767 | static inline void hri_dmac_clear_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) |
| 3768 | { |
| 3769 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3770 | ((Dmac *)hw)->BASEADDR.reg &= ~mask; |
| 3771 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3772 | } |
| 3773 | |
| 3774 | static inline void hri_dmac_toggle_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) |
| 3775 | { |
| 3776 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3777 | ((Dmac *)hw)->BASEADDR.reg ^= mask; |
| 3778 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3779 | } |
| 3780 | |
| 3781 | static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_reg(const void *const hw) |
| 3782 | { |
| 3783 | return ((Dmac *)hw)->BASEADDR.reg; |
| 3784 | } |
| 3785 | |
| 3786 | static inline void hri_dmac_set_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) |
| 3787 | { |
| 3788 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3789 | ((Dmac *)hw)->WRBADDR.reg |= DMAC_WRBADDR_WRBADDR(mask); |
| 3790 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3791 | } |
| 3792 | |
| 3793 | static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) |
| 3794 | { |
| 3795 | uint32_t tmp; |
| 3796 | tmp = ((Dmac *)hw)->WRBADDR.reg; |
| 3797 | tmp = (tmp & DMAC_WRBADDR_WRBADDR(mask)) >> DMAC_WRBADDR_WRBADDR_Pos; |
| 3798 | return tmp; |
| 3799 | } |
| 3800 | |
| 3801 | static inline void hri_dmac_write_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t data) |
| 3802 | { |
| 3803 | uint32_t tmp; |
| 3804 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3805 | tmp = ((Dmac *)hw)->WRBADDR.reg; |
| 3806 | tmp &= ~DMAC_WRBADDR_WRBADDR_Msk; |
| 3807 | tmp |= DMAC_WRBADDR_WRBADDR(data); |
| 3808 | ((Dmac *)hw)->WRBADDR.reg = tmp; |
| 3809 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3810 | } |
| 3811 | |
| 3812 | static inline void hri_dmac_clear_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) |
| 3813 | { |
| 3814 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3815 | ((Dmac *)hw)->WRBADDR.reg &= ~DMAC_WRBADDR_WRBADDR(mask); |
| 3816 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3817 | } |
| 3818 | |
| 3819 | static inline void hri_dmac_toggle_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) |
| 3820 | { |
| 3821 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3822 | ((Dmac *)hw)->WRBADDR.reg ^= DMAC_WRBADDR_WRBADDR(mask); |
| 3823 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3824 | } |
| 3825 | |
| 3826 | static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_WRBADDR_bf(const void *const hw) |
| 3827 | { |
| 3828 | uint32_t tmp; |
| 3829 | tmp = ((Dmac *)hw)->WRBADDR.reg; |
| 3830 | tmp = (tmp & DMAC_WRBADDR_WRBADDR_Msk) >> DMAC_WRBADDR_WRBADDR_Pos; |
| 3831 | return tmp; |
| 3832 | } |
| 3833 | |
| 3834 | static inline void hri_dmac_set_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) |
| 3835 | { |
| 3836 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3837 | ((Dmac *)hw)->WRBADDR.reg |= mask; |
| 3838 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3839 | } |
| 3840 | |
| 3841 | static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) |
| 3842 | { |
| 3843 | uint32_t tmp; |
| 3844 | tmp = ((Dmac *)hw)->WRBADDR.reg; |
| 3845 | tmp &= mask; |
| 3846 | return tmp; |
| 3847 | } |
| 3848 | |
| 3849 | static inline void hri_dmac_write_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t data) |
| 3850 | { |
| 3851 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3852 | ((Dmac *)hw)->WRBADDR.reg = data; |
| 3853 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3854 | } |
| 3855 | |
| 3856 | static inline void hri_dmac_clear_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) |
| 3857 | { |
| 3858 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3859 | ((Dmac *)hw)->WRBADDR.reg &= ~mask; |
| 3860 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3861 | } |
| 3862 | |
| 3863 | static inline void hri_dmac_toggle_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) |
| 3864 | { |
| 3865 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3866 | ((Dmac *)hw)->WRBADDR.reg ^= mask; |
| 3867 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3868 | } |
| 3869 | |
| 3870 | static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_reg(const void *const hw) |
| 3871 | { |
| 3872 | return ((Dmac *)hw)->WRBADDR.reg; |
| 3873 | } |
| 3874 | |
| 3875 | static inline bool hri_dmac_get_CRCSTATUS_CRCBUSY_bit(const void *const hw) |
| 3876 | { |
| 3877 | return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) >> DMAC_CRCSTATUS_CRCBUSY_Pos; |
| 3878 | } |
| 3879 | |
| 3880 | static inline void hri_dmac_clear_CRCSTATUS_CRCBUSY_bit(const void *const hw) |
| 3881 | { |
| 3882 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3883 | ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY; |
| 3884 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3885 | } |
| 3886 | |
| 3887 | static inline bool hri_dmac_get_CRCSTATUS_CRCZERO_bit(const void *const hw) |
| 3888 | { |
| 3889 | return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCZERO) >> DMAC_CRCSTATUS_CRCZERO_Pos; |
| 3890 | } |
| 3891 | |
| 3892 | static inline void hri_dmac_clear_CRCSTATUS_CRCZERO_bit(const void *const hw) |
| 3893 | { |
| 3894 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3895 | ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCZERO; |
| 3896 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3897 | } |
| 3898 | |
| 3899 | static inline bool hri_dmac_get_CRCSTATUS_CRCERR_bit(const void *const hw) |
| 3900 | { |
| 3901 | return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCERR) >> DMAC_CRCSTATUS_CRCERR_Pos; |
| 3902 | } |
| 3903 | |
| 3904 | static inline void hri_dmac_clear_CRCSTATUS_CRCERR_bit(const void *const hw) |
| 3905 | { |
| 3906 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3907 | ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCERR; |
| 3908 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3909 | } |
| 3910 | |
| 3911 | static inline hri_dmac_crcstatus_reg_t hri_dmac_get_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) |
| 3912 | { |
| 3913 | uint8_t tmp; |
| 3914 | tmp = ((Dmac *)hw)->CRCSTATUS.reg; |
| 3915 | tmp &= mask; |
| 3916 | return tmp; |
| 3917 | } |
| 3918 | |
| 3919 | static inline void hri_dmac_clear_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) |
| 3920 | { |
| 3921 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3922 | ((Dmac *)hw)->CRCSTATUS.reg = mask; |
| 3923 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3924 | } |
| 3925 | |
| 3926 | static inline hri_dmac_crcstatus_reg_t hri_dmac_read_CRCSTATUS_reg(const void *const hw) |
| 3927 | { |
| 3928 | return ((Dmac *)hw)->CRCSTATUS.reg; |
| 3929 | } |
| 3930 | |
| 3931 | static inline void hri_dmacdescriptor_set_BTCTRL_VALID_bit(const void *const hw) |
| 3932 | { |
| 3933 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3934 | ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_VALID; |
| 3935 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3936 | } |
| 3937 | |
| 3938 | static inline bool hri_dmacdescriptor_get_BTCTRL_VALID_bit(const void *const hw) |
| 3939 | { |
| 3940 | uint16_t tmp; |
| 3941 | tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; |
| 3942 | tmp = (tmp & DMAC_BTCTRL_VALID) >> DMAC_BTCTRL_VALID_Pos; |
| 3943 | return (bool)tmp; |
| 3944 | } |
| 3945 | |
| 3946 | static inline void hri_dmacdescriptor_write_BTCTRL_VALID_bit(const void *const hw, bool value) |
| 3947 | { |
| 3948 | uint16_t tmp; |
| 3949 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3950 | tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; |
| 3951 | tmp &= ~DMAC_BTCTRL_VALID; |
| 3952 | tmp |= value << DMAC_BTCTRL_VALID_Pos; |
| 3953 | ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; |
| 3954 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3955 | } |
| 3956 | |
| 3957 | static inline void hri_dmacdescriptor_clear_BTCTRL_VALID_bit(const void *const hw) |
| 3958 | { |
| 3959 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3960 | ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_VALID; |
| 3961 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3962 | } |
| 3963 | |
| 3964 | static inline void hri_dmacdescriptor_toggle_BTCTRL_VALID_bit(const void *const hw) |
| 3965 | { |
| 3966 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3967 | ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_VALID; |
| 3968 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3969 | } |
| 3970 | |
| 3971 | static inline void hri_dmacdescriptor_set_BTCTRL_SRCINC_bit(const void *const hw) |
| 3972 | { |
| 3973 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3974 | ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_SRCINC; |
| 3975 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3976 | } |
| 3977 | |
| 3978 | static inline bool hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(const void *const hw) |
| 3979 | { |
| 3980 | uint16_t tmp; |
| 3981 | tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; |
| 3982 | tmp = (tmp & DMAC_BTCTRL_SRCINC) >> DMAC_BTCTRL_SRCINC_Pos; |
| 3983 | return (bool)tmp; |
| 3984 | } |
| 3985 | |
| 3986 | static inline void hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(const void *const hw, bool value) |
| 3987 | { |
| 3988 | uint16_t tmp; |
| 3989 | DMAC_CRITICAL_SECTION_ENTER(); |
| 3990 | tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; |
| 3991 | tmp &= ~DMAC_BTCTRL_SRCINC; |
| 3992 | tmp |= value << DMAC_BTCTRL_SRCINC_Pos; |
| 3993 | ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; |
| 3994 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 3995 | } |
| 3996 | |
| 3997 | static inline void hri_dmacdescriptor_clear_BTCTRL_SRCINC_bit(const void *const hw) |
| 3998 | { |
| 3999 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4000 | ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_SRCINC; |
| 4001 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4002 | } |
| 4003 | |
| 4004 | static inline void hri_dmacdescriptor_toggle_BTCTRL_SRCINC_bit(const void *const hw) |
| 4005 | { |
| 4006 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4007 | ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_SRCINC; |
| 4008 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4009 | } |
| 4010 | |
| 4011 | static inline void hri_dmacdescriptor_set_BTCTRL_DSTINC_bit(const void *const hw) |
| 4012 | { |
| 4013 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4014 | ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_DSTINC; |
| 4015 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4016 | } |
| 4017 | |
| 4018 | static inline bool hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(const void *const hw) |
| 4019 | { |
| 4020 | uint16_t tmp; |
| 4021 | tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; |
| 4022 | tmp = (tmp & DMAC_BTCTRL_DSTINC) >> DMAC_BTCTRL_DSTINC_Pos; |
| 4023 | return (bool)tmp; |
| 4024 | } |
| 4025 | |
| 4026 | static inline void hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(const void *const hw, bool value) |
| 4027 | { |
| 4028 | uint16_t tmp; |
| 4029 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4030 | tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; |
| 4031 | tmp &= ~DMAC_BTCTRL_DSTINC; |
| 4032 | tmp |= value << DMAC_BTCTRL_DSTINC_Pos; |
| 4033 | ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; |
| 4034 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4035 | } |
| 4036 | |
| 4037 | static inline void hri_dmacdescriptor_clear_BTCTRL_DSTINC_bit(const void *const hw) |
| 4038 | { |
| 4039 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4040 | ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_DSTINC; |
| 4041 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4042 | } |
| 4043 | |
| 4044 | static inline void hri_dmacdescriptor_toggle_BTCTRL_DSTINC_bit(const void *const hw) |
| 4045 | { |
| 4046 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4047 | ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_DSTINC; |
| 4048 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4049 | } |
| 4050 | |
| 4051 | static inline void hri_dmacdescriptor_set_BTCTRL_STEPSEL_bit(const void *const hw) |
| 4052 | { |
| 4053 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4054 | ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSEL; |
| 4055 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4056 | } |
| 4057 | |
| 4058 | static inline bool hri_dmacdescriptor_get_BTCTRL_STEPSEL_bit(const void *const hw) |
| 4059 | { |
| 4060 | uint16_t tmp; |
| 4061 | tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; |
| 4062 | tmp = (tmp & DMAC_BTCTRL_STEPSEL) >> DMAC_BTCTRL_STEPSEL_Pos; |
| 4063 | return (bool)tmp; |
| 4064 | } |
| 4065 | |
| 4066 | static inline void hri_dmacdescriptor_write_BTCTRL_STEPSEL_bit(const void *const hw, bool value) |
| 4067 | { |
| 4068 | uint16_t tmp; |
| 4069 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4070 | tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; |
| 4071 | tmp &= ~DMAC_BTCTRL_STEPSEL; |
| 4072 | tmp |= value << DMAC_BTCTRL_STEPSEL_Pos; |
| 4073 | ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; |
| 4074 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4075 | } |
| 4076 | |
| 4077 | static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSEL_bit(const void *const hw) |
| 4078 | { |
| 4079 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4080 | ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSEL; |
| 4081 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4082 | } |
| 4083 | |
| 4084 | static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSEL_bit(const void *const hw) |
| 4085 | { |
| 4086 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4087 | ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSEL; |
| 4088 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4089 | } |
| 4090 | |
| 4091 | static inline void hri_dmacdescriptor_set_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) |
| 4092 | { |
| 4093 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4094 | ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_EVOSEL(mask); |
| 4095 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4096 | } |
| 4097 | |
| 4098 | static inline hri_dmacdescriptor_btctrl_reg_t |
| 4099 | hri_dmacdescriptor_get_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) |
| 4100 | { |
| 4101 | uint16_t tmp; |
| 4102 | tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; |
| 4103 | tmp = (tmp & DMAC_BTCTRL_EVOSEL(mask)) >> DMAC_BTCTRL_EVOSEL_Pos; |
| 4104 | return tmp; |
| 4105 | } |
| 4106 | |
| 4107 | static inline void hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) |
| 4108 | { |
| 4109 | uint16_t tmp; |
| 4110 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4111 | tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; |
| 4112 | tmp &= ~DMAC_BTCTRL_EVOSEL_Msk; |
| 4113 | tmp |= DMAC_BTCTRL_EVOSEL(data); |
| 4114 | ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; |
| 4115 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4116 | } |
| 4117 | |
| 4118 | static inline void hri_dmacdescriptor_clear_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) |
| 4119 | { |
| 4120 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4121 | ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_EVOSEL(mask); |
| 4122 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4123 | } |
| 4124 | |
| 4125 | static inline void hri_dmacdescriptor_toggle_BTCTRL_EVOSEL_bf(const void *const hw, |
| 4126 | hri_dmacdescriptor_btctrl_reg_t mask) |
| 4127 | { |
| 4128 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4129 | ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_EVOSEL(mask); |
| 4130 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4131 | } |
| 4132 | |
| 4133 | static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_EVOSEL_bf(const void *const hw) |
| 4134 | { |
| 4135 | uint16_t tmp; |
| 4136 | tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; |
| 4137 | tmp = (tmp & DMAC_BTCTRL_EVOSEL_Msk) >> DMAC_BTCTRL_EVOSEL_Pos; |
| 4138 | return tmp; |
| 4139 | } |
| 4140 | |
| 4141 | static inline void hri_dmacdescriptor_set_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) |
| 4142 | { |
| 4143 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4144 | ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BLOCKACT(mask); |
| 4145 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4146 | } |
| 4147 | |
| 4148 | static inline hri_dmacdescriptor_btctrl_reg_t |
| 4149 | hri_dmacdescriptor_get_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) |
| 4150 | { |
| 4151 | uint16_t tmp; |
| 4152 | tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; |
| 4153 | tmp = (tmp & DMAC_BTCTRL_BLOCKACT(mask)) >> DMAC_BTCTRL_BLOCKACT_Pos; |
| 4154 | return tmp; |
| 4155 | } |
| 4156 | |
| 4157 | static inline void hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(const void *const hw, |
| 4158 | hri_dmacdescriptor_btctrl_reg_t data) |
| 4159 | { |
| 4160 | uint16_t tmp; |
| 4161 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4162 | tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; |
| 4163 | tmp &= ~DMAC_BTCTRL_BLOCKACT_Msk; |
| 4164 | tmp |= DMAC_BTCTRL_BLOCKACT(data); |
| 4165 | ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; |
| 4166 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4167 | } |
| 4168 | |
| 4169 | static inline void hri_dmacdescriptor_clear_BTCTRL_BLOCKACT_bf(const void *const hw, |
| 4170 | hri_dmacdescriptor_btctrl_reg_t mask) |
| 4171 | { |
| 4172 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4173 | ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BLOCKACT(mask); |
| 4174 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4175 | } |
| 4176 | |
| 4177 | static inline void hri_dmacdescriptor_toggle_BTCTRL_BLOCKACT_bf(const void *const hw, |
| 4178 | hri_dmacdescriptor_btctrl_reg_t mask) |
| 4179 | { |
| 4180 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4181 | ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BLOCKACT(mask); |
| 4182 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4183 | } |
| 4184 | |
| 4185 | static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BLOCKACT_bf(const void *const hw) |
| 4186 | { |
| 4187 | uint16_t tmp; |
| 4188 | tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; |
| 4189 | tmp = (tmp & DMAC_BTCTRL_BLOCKACT_Msk) >> DMAC_BTCTRL_BLOCKACT_Pos; |
| 4190 | return tmp; |
| 4191 | } |
| 4192 | |
| 4193 | static inline void hri_dmacdescriptor_set_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) |
| 4194 | { |
| 4195 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4196 | ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BEATSIZE(mask); |
| 4197 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4198 | } |
| 4199 | |
| 4200 | static inline hri_dmacdescriptor_btctrl_reg_t |
| 4201 | hri_dmacdescriptor_get_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) |
| 4202 | { |
| 4203 | uint16_t tmp; |
| 4204 | tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; |
| 4205 | tmp = (tmp & DMAC_BTCTRL_BEATSIZE(mask)) >> DMAC_BTCTRL_BEATSIZE_Pos; |
| 4206 | return tmp; |
| 4207 | } |
| 4208 | |
| 4209 | static inline void hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(const void *const hw, |
| 4210 | hri_dmacdescriptor_btctrl_reg_t data) |
| 4211 | { |
| 4212 | uint16_t tmp; |
| 4213 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4214 | tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; |
| 4215 | tmp &= ~DMAC_BTCTRL_BEATSIZE_Msk; |
| 4216 | tmp |= DMAC_BTCTRL_BEATSIZE(data); |
| 4217 | ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; |
| 4218 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4219 | } |
| 4220 | |
| 4221 | static inline void hri_dmacdescriptor_clear_BTCTRL_BEATSIZE_bf(const void *const hw, |
| 4222 | hri_dmacdescriptor_btctrl_reg_t mask) |
| 4223 | { |
| 4224 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4225 | ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BEATSIZE(mask); |
| 4226 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4227 | } |
| 4228 | |
| 4229 | static inline void hri_dmacdescriptor_toggle_BTCTRL_BEATSIZE_bf(const void *const hw, |
| 4230 | hri_dmacdescriptor_btctrl_reg_t mask) |
| 4231 | { |
| 4232 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4233 | ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BEATSIZE(mask); |
| 4234 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4235 | } |
| 4236 | |
| 4237 | static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(const void *const hw) |
| 4238 | { |
| 4239 | uint16_t tmp; |
| 4240 | tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; |
| 4241 | tmp = (tmp & DMAC_BTCTRL_BEATSIZE_Msk) >> DMAC_BTCTRL_BEATSIZE_Pos; |
| 4242 | return tmp; |
| 4243 | } |
| 4244 | |
| 4245 | static inline void hri_dmacdescriptor_set_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) |
| 4246 | { |
| 4247 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4248 | ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSIZE(mask); |
| 4249 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4250 | } |
| 4251 | |
| 4252 | static inline hri_dmacdescriptor_btctrl_reg_t |
| 4253 | hri_dmacdescriptor_get_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) |
| 4254 | { |
| 4255 | uint16_t tmp; |
| 4256 | tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; |
| 4257 | tmp = (tmp & DMAC_BTCTRL_STEPSIZE(mask)) >> DMAC_BTCTRL_STEPSIZE_Pos; |
| 4258 | return tmp; |
| 4259 | } |
| 4260 | |
| 4261 | static inline void hri_dmacdescriptor_write_BTCTRL_STEPSIZE_bf(const void *const hw, |
| 4262 | hri_dmacdescriptor_btctrl_reg_t data) |
| 4263 | { |
| 4264 | uint16_t tmp; |
| 4265 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4266 | tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; |
| 4267 | tmp &= ~DMAC_BTCTRL_STEPSIZE_Msk; |
| 4268 | tmp |= DMAC_BTCTRL_STEPSIZE(data); |
| 4269 | ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; |
| 4270 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4271 | } |
| 4272 | |
| 4273 | static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSIZE_bf(const void *const hw, |
| 4274 | hri_dmacdescriptor_btctrl_reg_t mask) |
| 4275 | { |
| 4276 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4277 | ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSIZE(mask); |
| 4278 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4279 | } |
| 4280 | |
| 4281 | static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSIZE_bf(const void *const hw, |
| 4282 | hri_dmacdescriptor_btctrl_reg_t mask) |
| 4283 | { |
| 4284 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4285 | ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSIZE(mask); |
| 4286 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4287 | } |
| 4288 | |
| 4289 | static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_STEPSIZE_bf(const void *const hw) |
| 4290 | { |
| 4291 | uint16_t tmp; |
| 4292 | tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; |
| 4293 | tmp = (tmp & DMAC_BTCTRL_STEPSIZE_Msk) >> DMAC_BTCTRL_STEPSIZE_Pos; |
| 4294 | return tmp; |
| 4295 | } |
| 4296 | |
| 4297 | static inline void hri_dmacdescriptor_set_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) |
| 4298 | { |
| 4299 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4300 | ((DmacDescriptor *)hw)->BTCTRL.reg |= mask; |
| 4301 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4302 | } |
| 4303 | |
| 4304 | static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_get_BTCTRL_reg(const void *const hw, |
| 4305 | hri_dmacdescriptor_btctrl_reg_t mask) |
| 4306 | { |
| 4307 | uint16_t tmp; |
| 4308 | tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; |
| 4309 | tmp &= mask; |
| 4310 | return tmp; |
| 4311 | } |
| 4312 | |
| 4313 | static inline void hri_dmacdescriptor_write_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) |
| 4314 | { |
| 4315 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4316 | ((DmacDescriptor *)hw)->BTCTRL.reg = data; |
| 4317 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4318 | } |
| 4319 | |
| 4320 | static inline void hri_dmacdescriptor_clear_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) |
| 4321 | { |
| 4322 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4323 | ((DmacDescriptor *)hw)->BTCTRL.reg &= ~mask; |
| 4324 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4325 | } |
| 4326 | |
| 4327 | static inline void hri_dmacdescriptor_toggle_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) |
| 4328 | { |
| 4329 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4330 | ((DmacDescriptor *)hw)->BTCTRL.reg ^= mask; |
| 4331 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4332 | } |
| 4333 | |
| 4334 | static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_reg(const void *const hw) |
| 4335 | { |
| 4336 | return ((DmacDescriptor *)hw)->BTCTRL.reg; |
| 4337 | } |
| 4338 | |
| 4339 | static inline void hri_dmacdescriptor_set_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) |
| 4340 | { |
| 4341 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4342 | ((DmacDescriptor *)hw)->BTCNT.reg |= DMAC_BTCNT_BTCNT(mask); |
| 4343 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4344 | } |
| 4345 | |
| 4346 | static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_BTCNT_bf(const void *const hw, |
| 4347 | hri_dmacdescriptor_btcnt_reg_t mask) |
| 4348 | { |
| 4349 | uint16_t tmp; |
| 4350 | tmp = ((DmacDescriptor *)hw)->BTCNT.reg; |
| 4351 | tmp = (tmp & DMAC_BTCNT_BTCNT(mask)) >> DMAC_BTCNT_BTCNT_Pos; |
| 4352 | return tmp; |
| 4353 | } |
| 4354 | |
| 4355 | static inline void hri_dmacdescriptor_write_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) |
| 4356 | { |
| 4357 | uint16_t tmp; |
| 4358 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4359 | tmp = ((DmacDescriptor *)hw)->BTCNT.reg; |
| 4360 | tmp &= ~DMAC_BTCNT_BTCNT_Msk; |
| 4361 | tmp |= DMAC_BTCNT_BTCNT(data); |
| 4362 | ((DmacDescriptor *)hw)->BTCNT.reg = tmp; |
| 4363 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4364 | } |
| 4365 | |
| 4366 | static inline void hri_dmacdescriptor_clear_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) |
| 4367 | { |
| 4368 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4369 | ((DmacDescriptor *)hw)->BTCNT.reg &= ~DMAC_BTCNT_BTCNT(mask); |
| 4370 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4371 | } |
| 4372 | |
| 4373 | static inline void hri_dmacdescriptor_toggle_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) |
| 4374 | { |
| 4375 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4376 | ((DmacDescriptor *)hw)->BTCNT.reg ^= DMAC_BTCNT_BTCNT(mask); |
| 4377 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4378 | } |
| 4379 | |
| 4380 | static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_BTCNT_bf(const void *const hw) |
| 4381 | { |
| 4382 | uint16_t tmp; |
| 4383 | tmp = ((DmacDescriptor *)hw)->BTCNT.reg; |
| 4384 | tmp = (tmp & DMAC_BTCNT_BTCNT_Msk) >> DMAC_BTCNT_BTCNT_Pos; |
| 4385 | return tmp; |
| 4386 | } |
| 4387 | |
| 4388 | static inline void hri_dmacdescriptor_set_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) |
| 4389 | { |
| 4390 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4391 | ((DmacDescriptor *)hw)->BTCNT.reg |= mask; |
| 4392 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4393 | } |
| 4394 | |
| 4395 | static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_reg(const void *const hw, |
| 4396 | hri_dmacdescriptor_btcnt_reg_t mask) |
| 4397 | { |
| 4398 | uint16_t tmp; |
| 4399 | tmp = ((DmacDescriptor *)hw)->BTCNT.reg; |
| 4400 | tmp &= mask; |
| 4401 | return tmp; |
| 4402 | } |
| 4403 | |
| 4404 | static inline void hri_dmacdescriptor_write_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) |
| 4405 | { |
| 4406 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4407 | ((DmacDescriptor *)hw)->BTCNT.reg = data; |
| 4408 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4409 | } |
| 4410 | |
| 4411 | static inline void hri_dmacdescriptor_clear_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) |
| 4412 | { |
| 4413 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4414 | ((DmacDescriptor *)hw)->BTCNT.reg &= ~mask; |
| 4415 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4416 | } |
| 4417 | |
| 4418 | static inline void hri_dmacdescriptor_toggle_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) |
| 4419 | { |
| 4420 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4421 | ((DmacDescriptor *)hw)->BTCNT.reg ^= mask; |
| 4422 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4423 | } |
| 4424 | |
| 4425 | static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_reg(const void *const hw) |
| 4426 | { |
| 4427 | return ((DmacDescriptor *)hw)->BTCNT.reg; |
| 4428 | } |
| 4429 | |
| 4430 | static inline void hri_dmacdescriptor_set_SRCADDR_SRCADDR_bf(const void *const hw, |
| 4431 | hri_dmacdescriptor_srcaddr_reg_t mask) |
| 4432 | { |
| 4433 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4434 | ((DmacDescriptor *)hw)->SRCADDR.reg |= DMAC_SRCADDR_SRCADDR(mask); |
| 4435 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4436 | } |
| 4437 | |
| 4438 | static inline hri_dmacdescriptor_srcaddr_reg_t |
| 4439 | hri_dmacdescriptor_get_SRCADDR_SRCADDR_bf(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) |
| 4440 | { |
| 4441 | uint32_t tmp; |
| 4442 | tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; |
| 4443 | tmp = (tmp & DMAC_SRCADDR_SRCADDR(mask)) >> DMAC_SRCADDR_SRCADDR_Pos; |
| 4444 | return tmp; |
| 4445 | } |
| 4446 | |
| 4447 | static inline void hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(const void *const hw, |
| 4448 | hri_dmacdescriptor_srcaddr_reg_t data) |
| 4449 | { |
| 4450 | uint32_t tmp; |
| 4451 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4452 | tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; |
| 4453 | tmp &= ~DMAC_SRCADDR_SRCADDR_Msk; |
| 4454 | tmp |= DMAC_SRCADDR_SRCADDR(data); |
| 4455 | ((DmacDescriptor *)hw)->SRCADDR.reg = tmp; |
| 4456 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4457 | } |
| 4458 | |
| 4459 | static inline void hri_dmacdescriptor_clear_SRCADDR_SRCADDR_bf(const void *const hw, |
| 4460 | hri_dmacdescriptor_srcaddr_reg_t mask) |
| 4461 | { |
| 4462 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4463 | ((DmacDescriptor *)hw)->SRCADDR.reg &= ~DMAC_SRCADDR_SRCADDR(mask); |
| 4464 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4465 | } |
| 4466 | |
| 4467 | static inline void hri_dmacdescriptor_toggle_SRCADDR_SRCADDR_bf(const void *const hw, |
| 4468 | hri_dmacdescriptor_srcaddr_reg_t mask) |
| 4469 | { |
| 4470 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4471 | ((DmacDescriptor *)hw)->SRCADDR.reg ^= DMAC_SRCADDR_SRCADDR(mask); |
| 4472 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4473 | } |
| 4474 | |
| 4475 | static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_SRCADDR_bf(const void *const hw) |
| 4476 | { |
| 4477 | uint32_t tmp; |
| 4478 | tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; |
| 4479 | tmp = (tmp & DMAC_SRCADDR_SRCADDR_Msk) >> DMAC_SRCADDR_SRCADDR_Pos; |
| 4480 | return tmp; |
| 4481 | } |
| 4482 | |
| 4483 | static inline void hri_dmacdescriptor_set_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) |
| 4484 | { |
| 4485 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4486 | ((DmacDescriptor *)hw)->SRCADDR.reg |= mask; |
| 4487 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4488 | } |
| 4489 | |
| 4490 | static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_get_SRCADDR_reg(const void *const hw, |
| 4491 | hri_dmacdescriptor_srcaddr_reg_t mask) |
| 4492 | { |
| 4493 | uint32_t tmp; |
| 4494 | tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; |
| 4495 | tmp &= mask; |
| 4496 | return tmp; |
| 4497 | } |
| 4498 | |
| 4499 | static inline void hri_dmacdescriptor_write_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t data) |
| 4500 | { |
| 4501 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4502 | ((DmacDescriptor *)hw)->SRCADDR.reg = data; |
| 4503 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4504 | } |
| 4505 | |
| 4506 | static inline void hri_dmacdescriptor_clear_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) |
| 4507 | { |
| 4508 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4509 | ((DmacDescriptor *)hw)->SRCADDR.reg &= ~mask; |
| 4510 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4511 | } |
| 4512 | |
| 4513 | static inline void hri_dmacdescriptor_toggle_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) |
| 4514 | { |
| 4515 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4516 | ((DmacDescriptor *)hw)->SRCADDR.reg ^= mask; |
| 4517 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4518 | } |
| 4519 | |
| 4520 | static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_reg(const void *const hw) |
| 4521 | { |
| 4522 | return ((DmacDescriptor *)hw)->SRCADDR.reg; |
| 4523 | } |
| 4524 | |
| 4525 | static inline void hri_dmacdescriptor_set_DSTADDR_CRC_CHKINIT_bf(const void *const hw, |
| 4526 | hri_dmacdescriptor_dstaddr_reg_t mask) |
| 4527 | { |
| 4528 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4529 | ((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_CRC_CHKINIT(mask); |
| 4530 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4531 | } |
| 4532 | |
| 4533 | static inline hri_dmacdescriptor_dstaddr_reg_t |
| 4534 | hri_dmacdescriptor_get_DSTADDR_CRC_CHKINIT_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) |
| 4535 | { |
| 4536 | uint32_t tmp; |
| 4537 | tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; |
| 4538 | tmp = (tmp & DMAC_DSTADDR_CRC_CHKINIT(mask)) >> DMAC_DSTADDR_CRC_CHKINIT_Pos; |
| 4539 | return tmp; |
| 4540 | } |
| 4541 | |
| 4542 | static inline void hri_dmacdescriptor_write_DSTADDR_CRC_CHKINIT_bf(const void *const hw, |
| 4543 | hri_dmacdescriptor_dstaddr_reg_t data) |
| 4544 | { |
| 4545 | uint32_t tmp; |
| 4546 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4547 | tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; |
| 4548 | tmp &= ~DMAC_DSTADDR_CRC_CHKINIT_Msk; |
| 4549 | tmp |= DMAC_DSTADDR_CRC_CHKINIT(data); |
| 4550 | ((DmacDescriptor *)hw)->DSTADDR.reg = tmp; |
| 4551 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4552 | } |
| 4553 | |
| 4554 | static inline void hri_dmacdescriptor_clear_DSTADDR_CRC_CHKINIT_bf(const void *const hw, |
| 4555 | hri_dmacdescriptor_dstaddr_reg_t mask) |
| 4556 | { |
| 4557 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4558 | ((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_CRC_CHKINIT(mask); |
| 4559 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4560 | } |
| 4561 | |
| 4562 | static inline void hri_dmacdescriptor_toggle_DSTADDR_CRC_CHKINIT_bf(const void *const hw, |
| 4563 | hri_dmacdescriptor_dstaddr_reg_t mask) |
| 4564 | { |
| 4565 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4566 | ((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_CRC_CHKINIT(mask); |
| 4567 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4568 | } |
| 4569 | |
| 4570 | static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_CRC_CHKINIT_bf(const void *const hw) |
| 4571 | { |
| 4572 | uint32_t tmp; |
| 4573 | tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; |
| 4574 | tmp = (tmp & DMAC_DSTADDR_CRC_CHKINIT_Msk) >> DMAC_DSTADDR_CRC_CHKINIT_Pos; |
| 4575 | return tmp; |
| 4576 | } |
| 4577 | |
| 4578 | static inline void hri_dmacdescriptor_set_DSTADDR_DSTADDR_bf(const void *const hw, |
| 4579 | hri_dmacdescriptor_dstaddr_reg_t mask) |
| 4580 | { |
| 4581 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4582 | ((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_DSTADDR(mask); |
| 4583 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4584 | } |
| 4585 | |
| 4586 | static inline hri_dmacdescriptor_dstaddr_reg_t |
| 4587 | hri_dmacdescriptor_get_DSTADDR_DSTADDR_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) |
| 4588 | { |
| 4589 | uint32_t tmp; |
| 4590 | tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; |
| 4591 | tmp = (tmp & DMAC_DSTADDR_DSTADDR(mask)) >> DMAC_DSTADDR_DSTADDR_Pos; |
| 4592 | return tmp; |
| 4593 | } |
| 4594 | |
| 4595 | static inline void hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(const void *const hw, |
| 4596 | hri_dmacdescriptor_dstaddr_reg_t data) |
| 4597 | { |
| 4598 | uint32_t tmp; |
| 4599 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4600 | tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; |
| 4601 | tmp &= ~DMAC_DSTADDR_DSTADDR_Msk; |
| 4602 | tmp |= DMAC_DSTADDR_DSTADDR(data); |
| 4603 | ((DmacDescriptor *)hw)->DSTADDR.reg = tmp; |
| 4604 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4605 | } |
| 4606 | |
| 4607 | static inline void hri_dmacdescriptor_clear_DSTADDR_DSTADDR_bf(const void *const hw, |
| 4608 | hri_dmacdescriptor_dstaddr_reg_t mask) |
| 4609 | { |
| 4610 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4611 | ((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_DSTADDR(mask); |
| 4612 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4613 | } |
| 4614 | |
| 4615 | static inline void hri_dmacdescriptor_toggle_DSTADDR_DSTADDR_bf(const void *const hw, |
| 4616 | hri_dmacdescriptor_dstaddr_reg_t mask) |
| 4617 | { |
| 4618 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4619 | ((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_DSTADDR(mask); |
| 4620 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4621 | } |
| 4622 | |
| 4623 | static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_DSTADDR_bf(const void *const hw) |
| 4624 | { |
| 4625 | uint32_t tmp; |
| 4626 | tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; |
| 4627 | tmp = (tmp & DMAC_DSTADDR_DSTADDR_Msk) >> DMAC_DSTADDR_DSTADDR_Pos; |
| 4628 | return tmp; |
| 4629 | } |
| 4630 | |
| 4631 | static inline void hri_dmacdescriptor_set_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) |
| 4632 | { |
| 4633 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4634 | ((DmacDescriptor *)hw)->DSTADDR.reg |= mask; |
| 4635 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4636 | } |
| 4637 | |
| 4638 | static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_get_DSTADDR_reg(const void *const hw, |
| 4639 | hri_dmacdescriptor_dstaddr_reg_t mask) |
| 4640 | { |
| 4641 | uint32_t tmp; |
| 4642 | tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; |
| 4643 | tmp &= mask; |
| 4644 | return tmp; |
| 4645 | } |
| 4646 | |
| 4647 | static inline void hri_dmacdescriptor_write_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t data) |
| 4648 | { |
| 4649 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4650 | ((DmacDescriptor *)hw)->DSTADDR.reg = data; |
| 4651 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4652 | } |
| 4653 | |
| 4654 | static inline void hri_dmacdescriptor_clear_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) |
| 4655 | { |
| 4656 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4657 | ((DmacDescriptor *)hw)->DSTADDR.reg &= ~mask; |
| 4658 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4659 | } |
| 4660 | |
| 4661 | static inline void hri_dmacdescriptor_toggle_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) |
| 4662 | { |
| 4663 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4664 | ((DmacDescriptor *)hw)->DSTADDR.reg ^= mask; |
| 4665 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4666 | } |
| 4667 | |
| 4668 | static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_reg(const void *const hw) |
| 4669 | { |
| 4670 | return ((DmacDescriptor *)hw)->DSTADDR.reg; |
| 4671 | } |
| 4672 | |
| 4673 | static inline void hri_dmacdescriptor_set_DESCADDR_DESCADDR_bf(const void *const hw, |
| 4674 | hri_dmacdescriptor_descaddr_reg_t mask) |
| 4675 | { |
| 4676 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4677 | ((DmacDescriptor *)hw)->DESCADDR.reg |= DMAC_DESCADDR_DESCADDR(mask); |
| 4678 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4679 | } |
| 4680 | |
| 4681 | static inline hri_dmacdescriptor_descaddr_reg_t |
| 4682 | hri_dmacdescriptor_get_DESCADDR_DESCADDR_bf(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) |
| 4683 | { |
| 4684 | uint32_t tmp; |
| 4685 | tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; |
| 4686 | tmp = (tmp & DMAC_DESCADDR_DESCADDR(mask)) >> DMAC_DESCADDR_DESCADDR_Pos; |
| 4687 | return tmp; |
| 4688 | } |
| 4689 | |
| 4690 | static inline void hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(const void *const hw, |
| 4691 | hri_dmacdescriptor_descaddr_reg_t data) |
| 4692 | { |
| 4693 | uint32_t tmp; |
| 4694 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4695 | tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; |
| 4696 | tmp &= ~DMAC_DESCADDR_DESCADDR_Msk; |
| 4697 | tmp |= DMAC_DESCADDR_DESCADDR(data); |
| 4698 | ((DmacDescriptor *)hw)->DESCADDR.reg = tmp; |
| 4699 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4700 | } |
| 4701 | |
| 4702 | static inline void hri_dmacdescriptor_clear_DESCADDR_DESCADDR_bf(const void *const hw, |
| 4703 | hri_dmacdescriptor_descaddr_reg_t mask) |
| 4704 | { |
| 4705 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4706 | ((DmacDescriptor *)hw)->DESCADDR.reg &= ~DMAC_DESCADDR_DESCADDR(mask); |
| 4707 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4708 | } |
| 4709 | |
| 4710 | static inline void hri_dmacdescriptor_toggle_DESCADDR_DESCADDR_bf(const void *const hw, |
| 4711 | hri_dmacdescriptor_descaddr_reg_t mask) |
| 4712 | { |
| 4713 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4714 | ((DmacDescriptor *)hw)->DESCADDR.reg ^= DMAC_DESCADDR_DESCADDR(mask); |
| 4715 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4716 | } |
| 4717 | |
| 4718 | static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_DESCADDR_bf(const void *const hw) |
| 4719 | { |
| 4720 | uint32_t tmp; |
| 4721 | tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; |
| 4722 | tmp = (tmp & DMAC_DESCADDR_DESCADDR_Msk) >> DMAC_DESCADDR_DESCADDR_Pos; |
| 4723 | return tmp; |
| 4724 | } |
| 4725 | |
| 4726 | static inline void hri_dmacdescriptor_set_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) |
| 4727 | { |
| 4728 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4729 | ((DmacDescriptor *)hw)->DESCADDR.reg |= mask; |
| 4730 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4731 | } |
| 4732 | |
| 4733 | static inline hri_dmacdescriptor_descaddr_reg_t |
| 4734 | hri_dmacdescriptor_get_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) |
| 4735 | { |
| 4736 | uint32_t tmp; |
| 4737 | tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; |
| 4738 | tmp &= mask; |
| 4739 | return tmp; |
| 4740 | } |
| 4741 | |
| 4742 | static inline void hri_dmacdescriptor_write_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t data) |
| 4743 | { |
| 4744 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4745 | ((DmacDescriptor *)hw)->DESCADDR.reg = data; |
| 4746 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4747 | } |
| 4748 | |
| 4749 | static inline void hri_dmacdescriptor_clear_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) |
| 4750 | { |
| 4751 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4752 | ((DmacDescriptor *)hw)->DESCADDR.reg &= ~mask; |
| 4753 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4754 | } |
| 4755 | |
| 4756 | static inline void hri_dmacdescriptor_toggle_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) |
| 4757 | { |
| 4758 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4759 | ((DmacDescriptor *)hw)->DESCADDR.reg ^= mask; |
| 4760 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4761 | } |
| 4762 | |
| 4763 | static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_reg(const void *const hw) |
| 4764 | { |
| 4765 | return ((DmacDescriptor *)hw)->DESCADDR.reg; |
| 4766 | } |
| 4767 | |
| 4768 | static inline bool hri_dmacchannel_get_CHINTFLAG_TERR_bit(const void *const hw) |
| 4769 | { |
| 4770 | return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; |
| 4771 | } |
| 4772 | |
| 4773 | static inline void hri_dmacchannel_clear_CHINTFLAG_TERR_bit(const void *const hw) |
| 4774 | { |
| 4775 | ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; |
| 4776 | } |
| 4777 | |
| 4778 | static inline bool hri_dmacchannel_get_CHINTFLAG_TCMPL_bit(const void *const hw) |
| 4779 | { |
| 4780 | return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; |
| 4781 | } |
| 4782 | |
| 4783 | static inline void hri_dmacchannel_clear_CHINTFLAG_TCMPL_bit(const void *const hw) |
| 4784 | { |
| 4785 | ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; |
| 4786 | } |
| 4787 | |
| 4788 | static inline bool hri_dmacchannel_get_CHINTFLAG_SUSP_bit(const void *const hw) |
| 4789 | { |
| 4790 | return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; |
| 4791 | } |
| 4792 | |
| 4793 | static inline void hri_dmacchannel_clear_CHINTFLAG_SUSP_bit(const void *const hw) |
| 4794 | { |
| 4795 | ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; |
| 4796 | } |
| 4797 | |
| 4798 | static inline bool hri_dmacchannel_get_interrupt_TERR_bit(const void *const hw) |
| 4799 | { |
| 4800 | return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; |
| 4801 | } |
| 4802 | |
| 4803 | static inline void hri_dmacchannel_clear_interrupt_TERR_bit(const void *const hw) |
| 4804 | { |
| 4805 | ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; |
| 4806 | } |
| 4807 | |
| 4808 | static inline bool hri_dmacchannel_get_interrupt_TCMPL_bit(const void *const hw) |
| 4809 | { |
| 4810 | return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; |
| 4811 | } |
| 4812 | |
| 4813 | static inline void hri_dmacchannel_clear_interrupt_TCMPL_bit(const void *const hw) |
| 4814 | { |
| 4815 | ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; |
| 4816 | } |
| 4817 | |
| 4818 | static inline bool hri_dmacchannel_get_interrupt_SUSP_bit(const void *const hw) |
| 4819 | { |
| 4820 | return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; |
| 4821 | } |
| 4822 | |
| 4823 | static inline void hri_dmacchannel_clear_interrupt_SUSP_bit(const void *const hw) |
| 4824 | { |
| 4825 | ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; |
| 4826 | } |
| 4827 | |
| 4828 | static inline hri_dmac_chintflag_reg_t hri_dmacchannel_get_CHINTFLAG_reg(const void *const hw, |
| 4829 | hri_dmac_chintflag_reg_t mask) |
| 4830 | { |
| 4831 | uint8_t tmp; |
| 4832 | tmp = ((DmacChannel *)hw)->CHINTFLAG.reg; |
| 4833 | tmp &= mask; |
| 4834 | return tmp; |
| 4835 | } |
| 4836 | |
| 4837 | static inline hri_dmac_chintflag_reg_t hri_dmacchannel_read_CHINTFLAG_reg(const void *const hw) |
| 4838 | { |
| 4839 | return ((DmacChannel *)hw)->CHINTFLAG.reg; |
| 4840 | } |
| 4841 | |
| 4842 | static inline void hri_dmacchannel_clear_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask) |
| 4843 | { |
| 4844 | ((DmacChannel *)hw)->CHINTFLAG.reg = mask; |
| 4845 | } |
| 4846 | |
| 4847 | static inline void hri_dmacchannel_set_CHINTEN_TERR_bit(const void *const hw) |
| 4848 | { |
| 4849 | ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; |
| 4850 | } |
| 4851 | |
| 4852 | static inline bool hri_dmacchannel_get_CHINTEN_TERR_bit(const void *const hw) |
| 4853 | { |
| 4854 | return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; |
| 4855 | } |
| 4856 | |
| 4857 | static inline void hri_dmacchannel_write_CHINTEN_TERR_bit(const void *const hw, bool value) |
| 4858 | { |
| 4859 | if (value == 0x0) { |
| 4860 | ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; |
| 4861 | } else { |
| 4862 | ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; |
| 4863 | } |
| 4864 | } |
| 4865 | |
| 4866 | static inline void hri_dmacchannel_clear_CHINTEN_TERR_bit(const void *const hw) |
| 4867 | { |
| 4868 | ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; |
| 4869 | } |
| 4870 | |
| 4871 | static inline void hri_dmacchannel_set_CHINTEN_TCMPL_bit(const void *const hw) |
| 4872 | { |
| 4873 | ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; |
| 4874 | } |
| 4875 | |
| 4876 | static inline bool hri_dmacchannel_get_CHINTEN_TCMPL_bit(const void *const hw) |
| 4877 | { |
| 4878 | return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos; |
| 4879 | } |
| 4880 | |
| 4881 | static inline void hri_dmacchannel_write_CHINTEN_TCMPL_bit(const void *const hw, bool value) |
| 4882 | { |
| 4883 | if (value == 0x0) { |
| 4884 | ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; |
| 4885 | } else { |
| 4886 | ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; |
| 4887 | } |
| 4888 | } |
| 4889 | |
| 4890 | static inline void hri_dmacchannel_clear_CHINTEN_TCMPL_bit(const void *const hw) |
| 4891 | { |
| 4892 | ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; |
| 4893 | } |
| 4894 | |
| 4895 | static inline void hri_dmacchannel_set_CHINTEN_SUSP_bit(const void *const hw) |
| 4896 | { |
| 4897 | ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; |
| 4898 | } |
| 4899 | |
| 4900 | static inline bool hri_dmacchannel_get_CHINTEN_SUSP_bit(const void *const hw) |
| 4901 | { |
| 4902 | return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos; |
| 4903 | } |
| 4904 | |
| 4905 | static inline void hri_dmacchannel_write_CHINTEN_SUSP_bit(const void *const hw, bool value) |
| 4906 | { |
| 4907 | if (value == 0x0) { |
| 4908 | ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; |
| 4909 | } else { |
| 4910 | ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; |
| 4911 | } |
| 4912 | } |
| 4913 | |
| 4914 | static inline void hri_dmacchannel_clear_CHINTEN_SUSP_bit(const void *const hw) |
| 4915 | { |
| 4916 | ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; |
| 4917 | } |
| 4918 | |
| 4919 | static inline void hri_dmacchannel_set_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) |
| 4920 | { |
| 4921 | ((DmacChannel *)hw)->CHINTENSET.reg = mask; |
| 4922 | } |
| 4923 | |
| 4924 | static inline hri_dmac_chintenset_reg_t hri_dmacchannel_get_CHINTEN_reg(const void *const hw, |
| 4925 | hri_dmac_chintenset_reg_t mask) |
| 4926 | { |
| 4927 | uint8_t tmp; |
| 4928 | tmp = ((DmacChannel *)hw)->CHINTENSET.reg; |
| 4929 | tmp &= mask; |
| 4930 | return tmp; |
| 4931 | } |
| 4932 | |
| 4933 | static inline hri_dmac_chintenset_reg_t hri_dmacchannel_read_CHINTEN_reg(const void *const hw) |
| 4934 | { |
| 4935 | return ((DmacChannel *)hw)->CHINTENSET.reg; |
| 4936 | } |
| 4937 | |
| 4938 | static inline void hri_dmacchannel_write_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t data) |
| 4939 | { |
| 4940 | ((DmacChannel *)hw)->CHINTENSET.reg = data; |
| 4941 | ((DmacChannel *)hw)->CHINTENCLR.reg = ~data; |
| 4942 | } |
| 4943 | |
| 4944 | static inline void hri_dmacchannel_clear_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) |
| 4945 | { |
| 4946 | ((DmacChannel *)hw)->CHINTENCLR.reg = mask; |
| 4947 | } |
| 4948 | |
| 4949 | static inline void hri_dmacchannel_set_CHCTRLA_SWRST_bit(const void *const hw) |
| 4950 | { |
| 4951 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4952 | ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_SWRST; |
| 4953 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4954 | } |
| 4955 | |
| 4956 | static inline bool hri_dmacchannel_get_CHCTRLA_SWRST_bit(const void *const hw) |
| 4957 | { |
| 4958 | uint32_t tmp; |
| 4959 | tmp = ((DmacChannel *)hw)->CHCTRLA.reg; |
| 4960 | tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos; |
| 4961 | return (bool)tmp; |
| 4962 | } |
| 4963 | |
| 4964 | static inline void hri_dmacchannel_set_CHCTRLA_ENABLE_bit(const void *const hw) |
| 4965 | { |
| 4966 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4967 | ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; |
| 4968 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4969 | } |
| 4970 | |
| 4971 | static inline bool hri_dmacchannel_get_CHCTRLA_ENABLE_bit(const void *const hw) |
| 4972 | { |
| 4973 | uint32_t tmp; |
| 4974 | tmp = ((DmacChannel *)hw)->CHCTRLA.reg; |
| 4975 | tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos; |
| 4976 | return (bool)tmp; |
| 4977 | } |
| 4978 | |
| 4979 | static inline void hri_dmacchannel_write_CHCTRLA_ENABLE_bit(const void *const hw, bool value) |
| 4980 | { |
| 4981 | uint32_t tmp; |
| 4982 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4983 | tmp = ((DmacChannel *)hw)->CHCTRLA.reg; |
| 4984 | tmp &= ~DMAC_CHCTRLA_ENABLE; |
| 4985 | tmp |= value << DMAC_CHCTRLA_ENABLE_Pos; |
| 4986 | ((DmacChannel *)hw)->CHCTRLA.reg = tmp; |
| 4987 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4988 | } |
| 4989 | |
| 4990 | static inline void hri_dmacchannel_clear_CHCTRLA_ENABLE_bit(const void *const hw) |
| 4991 | { |
| 4992 | DMAC_CRITICAL_SECTION_ENTER(); |
| 4993 | ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; |
| 4994 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 4995 | } |
| 4996 | |
| 4997 | static inline void hri_dmacchannel_toggle_CHCTRLA_ENABLE_bit(const void *const hw) |
| 4998 | { |
| 4999 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5000 | ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE; |
| 5001 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5002 | } |
| 5003 | |
| 5004 | static inline void hri_dmacchannel_set_CHCTRLA_RUNSTDBY_bit(const void *const hw) |
| 5005 | { |
| 5006 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5007 | ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; |
| 5008 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5009 | } |
| 5010 | |
| 5011 | static inline bool hri_dmacchannel_get_CHCTRLA_RUNSTDBY_bit(const void *const hw) |
| 5012 | { |
| 5013 | uint32_t tmp; |
| 5014 | tmp = ((DmacChannel *)hw)->CHCTRLA.reg; |
| 5015 | tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos; |
| 5016 | return (bool)tmp; |
| 5017 | } |
| 5018 | |
| 5019 | static inline void hri_dmacchannel_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, bool value) |
| 5020 | { |
| 5021 | uint32_t tmp; |
| 5022 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5023 | tmp = ((DmacChannel *)hw)->CHCTRLA.reg; |
| 5024 | tmp &= ~DMAC_CHCTRLA_RUNSTDBY; |
| 5025 | tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos; |
| 5026 | ((DmacChannel *)hw)->CHCTRLA.reg = tmp; |
| 5027 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5028 | } |
| 5029 | |
| 5030 | static inline void hri_dmacchannel_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw) |
| 5031 | { |
| 5032 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5033 | ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY; |
| 5034 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5035 | } |
| 5036 | |
| 5037 | static inline void hri_dmacchannel_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw) |
| 5038 | { |
| 5039 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5040 | ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY; |
| 5041 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5042 | } |
| 5043 | |
| 5044 | static inline void hri_dmacchannel_set_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) |
| 5045 | { |
| 5046 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5047 | ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_TRIGSRC(mask); |
| 5048 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5049 | } |
| 5050 | |
| 5051 | static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_TRIGSRC_bf(const void *const hw, |
| 5052 | hri_dmac_chctrla_reg_t mask) |
| 5053 | { |
| 5054 | uint32_t tmp; |
| 5055 | tmp = ((DmacChannel *)hw)->CHCTRLA.reg; |
| 5056 | tmp = (tmp & DMAC_CHCTRLA_TRIGSRC(mask)) >> DMAC_CHCTRLA_TRIGSRC_Pos; |
| 5057 | return tmp; |
| 5058 | } |
| 5059 | |
| 5060 | static inline void hri_dmacchannel_write_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t data) |
| 5061 | { |
| 5062 | uint32_t tmp; |
| 5063 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5064 | tmp = ((DmacChannel *)hw)->CHCTRLA.reg; |
| 5065 | tmp &= ~DMAC_CHCTRLA_TRIGSRC_Msk; |
| 5066 | tmp |= DMAC_CHCTRLA_TRIGSRC(data); |
| 5067 | ((DmacChannel *)hw)->CHCTRLA.reg = tmp; |
| 5068 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5069 | } |
| 5070 | |
| 5071 | static inline void hri_dmacchannel_clear_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) |
| 5072 | { |
| 5073 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5074 | ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGSRC(mask); |
| 5075 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5076 | } |
| 5077 | |
| 5078 | static inline void hri_dmacchannel_toggle_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) |
| 5079 | { |
| 5080 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5081 | ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGSRC(mask); |
| 5082 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5083 | } |
| 5084 | |
| 5085 | static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_TRIGSRC_bf(const void *const hw) |
| 5086 | { |
| 5087 | uint32_t tmp; |
| 5088 | tmp = ((DmacChannel *)hw)->CHCTRLA.reg; |
| 5089 | tmp = (tmp & DMAC_CHCTRLA_TRIGSRC_Msk) >> DMAC_CHCTRLA_TRIGSRC_Pos; |
| 5090 | return tmp; |
| 5091 | } |
| 5092 | |
| 5093 | static inline void hri_dmacchannel_set_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) |
| 5094 | { |
| 5095 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5096 | ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_TRIGACT(mask); |
| 5097 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5098 | } |
| 5099 | |
| 5100 | static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_TRIGACT_bf(const void *const hw, |
| 5101 | hri_dmac_chctrla_reg_t mask) |
| 5102 | { |
| 5103 | uint32_t tmp; |
| 5104 | tmp = ((DmacChannel *)hw)->CHCTRLA.reg; |
| 5105 | tmp = (tmp & DMAC_CHCTRLA_TRIGACT(mask)) >> DMAC_CHCTRLA_TRIGACT_Pos; |
| 5106 | return tmp; |
| 5107 | } |
| 5108 | |
| 5109 | static inline void hri_dmacchannel_write_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t data) |
| 5110 | { |
| 5111 | uint32_t tmp; |
| 5112 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5113 | tmp = ((DmacChannel *)hw)->CHCTRLA.reg; |
| 5114 | tmp &= ~DMAC_CHCTRLA_TRIGACT_Msk; |
| 5115 | tmp |= DMAC_CHCTRLA_TRIGACT(data); |
| 5116 | ((DmacChannel *)hw)->CHCTRLA.reg = tmp; |
| 5117 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5118 | } |
| 5119 | |
| 5120 | static inline void hri_dmacchannel_clear_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) |
| 5121 | { |
| 5122 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5123 | ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGACT(mask); |
| 5124 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5125 | } |
| 5126 | |
| 5127 | static inline void hri_dmacchannel_toggle_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) |
| 5128 | { |
| 5129 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5130 | ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGACT(mask); |
| 5131 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5132 | } |
| 5133 | |
| 5134 | static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_TRIGACT_bf(const void *const hw) |
| 5135 | { |
| 5136 | uint32_t tmp; |
| 5137 | tmp = ((DmacChannel *)hw)->CHCTRLA.reg; |
| 5138 | tmp = (tmp & DMAC_CHCTRLA_TRIGACT_Msk) >> DMAC_CHCTRLA_TRIGACT_Pos; |
| 5139 | return tmp; |
| 5140 | } |
| 5141 | |
| 5142 | static inline void hri_dmacchannel_set_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) |
| 5143 | { |
| 5144 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5145 | ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_BURSTLEN(mask); |
| 5146 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5147 | } |
| 5148 | |
| 5149 | static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_BURSTLEN_bf(const void *const hw, |
| 5150 | hri_dmac_chctrla_reg_t mask) |
| 5151 | { |
| 5152 | uint32_t tmp; |
| 5153 | tmp = ((DmacChannel *)hw)->CHCTRLA.reg; |
| 5154 | tmp = (tmp & DMAC_CHCTRLA_BURSTLEN(mask)) >> DMAC_CHCTRLA_BURSTLEN_Pos; |
| 5155 | return tmp; |
| 5156 | } |
| 5157 | |
| 5158 | static inline void hri_dmacchannel_write_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t data) |
| 5159 | { |
| 5160 | uint32_t tmp; |
| 5161 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5162 | tmp = ((DmacChannel *)hw)->CHCTRLA.reg; |
| 5163 | tmp &= ~DMAC_CHCTRLA_BURSTLEN_Msk; |
| 5164 | tmp |= DMAC_CHCTRLA_BURSTLEN(data); |
| 5165 | ((DmacChannel *)hw)->CHCTRLA.reg = tmp; |
| 5166 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5167 | } |
| 5168 | |
| 5169 | static inline void hri_dmacchannel_clear_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) |
| 5170 | { |
| 5171 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5172 | ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_BURSTLEN(mask); |
| 5173 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5174 | } |
| 5175 | |
| 5176 | static inline void hri_dmacchannel_toggle_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) |
| 5177 | { |
| 5178 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5179 | ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_BURSTLEN(mask); |
| 5180 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5181 | } |
| 5182 | |
| 5183 | static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_BURSTLEN_bf(const void *const hw) |
| 5184 | { |
| 5185 | uint32_t tmp; |
| 5186 | tmp = ((DmacChannel *)hw)->CHCTRLA.reg; |
| 5187 | tmp = (tmp & DMAC_CHCTRLA_BURSTLEN_Msk) >> DMAC_CHCTRLA_BURSTLEN_Pos; |
| 5188 | return tmp; |
| 5189 | } |
| 5190 | |
| 5191 | static inline void hri_dmacchannel_set_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) |
| 5192 | { |
| 5193 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5194 | ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_THRESHOLD(mask); |
| 5195 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5196 | } |
| 5197 | |
| 5198 | static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_THRESHOLD_bf(const void *const hw, |
| 5199 | hri_dmac_chctrla_reg_t mask) |
| 5200 | { |
| 5201 | uint32_t tmp; |
| 5202 | tmp = ((DmacChannel *)hw)->CHCTRLA.reg; |
| 5203 | tmp = (tmp & DMAC_CHCTRLA_THRESHOLD(mask)) >> DMAC_CHCTRLA_THRESHOLD_Pos; |
| 5204 | return tmp; |
| 5205 | } |
| 5206 | |
| 5207 | static inline void hri_dmacchannel_write_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t data) |
| 5208 | { |
| 5209 | uint32_t tmp; |
| 5210 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5211 | tmp = ((DmacChannel *)hw)->CHCTRLA.reg; |
| 5212 | tmp &= ~DMAC_CHCTRLA_THRESHOLD_Msk; |
| 5213 | tmp |= DMAC_CHCTRLA_THRESHOLD(data); |
| 5214 | ((DmacChannel *)hw)->CHCTRLA.reg = tmp; |
| 5215 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5216 | } |
| 5217 | |
| 5218 | static inline void hri_dmacchannel_clear_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) |
| 5219 | { |
| 5220 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5221 | ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_THRESHOLD(mask); |
| 5222 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5223 | } |
| 5224 | |
| 5225 | static inline void hri_dmacchannel_toggle_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) |
| 5226 | { |
| 5227 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5228 | ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_THRESHOLD(mask); |
| 5229 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5230 | } |
| 5231 | |
| 5232 | static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_THRESHOLD_bf(const void *const hw) |
| 5233 | { |
| 5234 | uint32_t tmp; |
| 5235 | tmp = ((DmacChannel *)hw)->CHCTRLA.reg; |
| 5236 | tmp = (tmp & DMAC_CHCTRLA_THRESHOLD_Msk) >> DMAC_CHCTRLA_THRESHOLD_Pos; |
| 5237 | return tmp; |
| 5238 | } |
| 5239 | |
| 5240 | static inline void hri_dmacchannel_set_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) |
| 5241 | { |
| 5242 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5243 | ((DmacChannel *)hw)->CHCTRLA.reg |= mask; |
| 5244 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5245 | } |
| 5246 | |
| 5247 | static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) |
| 5248 | { |
| 5249 | uint32_t tmp; |
| 5250 | tmp = ((DmacChannel *)hw)->CHCTRLA.reg; |
| 5251 | tmp &= mask; |
| 5252 | return tmp; |
| 5253 | } |
| 5254 | |
| 5255 | static inline void hri_dmacchannel_write_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t data) |
| 5256 | { |
| 5257 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5258 | ((DmacChannel *)hw)->CHCTRLA.reg = data; |
| 5259 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5260 | } |
| 5261 | |
| 5262 | static inline void hri_dmacchannel_clear_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) |
| 5263 | { |
| 5264 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5265 | ((DmacChannel *)hw)->CHCTRLA.reg &= ~mask; |
| 5266 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5267 | } |
| 5268 | |
| 5269 | static inline void hri_dmacchannel_toggle_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) |
| 5270 | { |
| 5271 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5272 | ((DmacChannel *)hw)->CHCTRLA.reg ^= mask; |
| 5273 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5274 | } |
| 5275 | |
| 5276 | static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_reg(const void *const hw) |
| 5277 | { |
| 5278 | return ((DmacChannel *)hw)->CHCTRLA.reg; |
| 5279 | } |
| 5280 | |
| 5281 | static inline void hri_dmacchannel_set_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) |
| 5282 | { |
| 5283 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5284 | ((DmacChannel *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask); |
| 5285 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5286 | } |
| 5287 | |
| 5288 | static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_get_CHCTRLB_CMD_bf(const void *const hw, |
| 5289 | hri_dmac_chctrlb_reg_t mask) |
| 5290 | { |
| 5291 | uint8_t tmp; |
| 5292 | tmp = ((DmacChannel *)hw)->CHCTRLB.reg; |
| 5293 | tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos; |
| 5294 | return tmp; |
| 5295 | } |
| 5296 | |
| 5297 | static inline void hri_dmacchannel_write_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) |
| 5298 | { |
| 5299 | uint8_t tmp; |
| 5300 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5301 | tmp = ((DmacChannel *)hw)->CHCTRLB.reg; |
| 5302 | tmp &= ~DMAC_CHCTRLB_CMD_Msk; |
| 5303 | tmp |= DMAC_CHCTRLB_CMD(data); |
| 5304 | ((DmacChannel *)hw)->CHCTRLB.reg = tmp; |
| 5305 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5306 | } |
| 5307 | |
| 5308 | static inline void hri_dmacchannel_clear_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) |
| 5309 | { |
| 5310 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5311 | ((DmacChannel *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask); |
| 5312 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5313 | } |
| 5314 | |
| 5315 | static inline void hri_dmacchannel_toggle_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) |
| 5316 | { |
| 5317 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5318 | ((DmacChannel *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask); |
| 5319 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5320 | } |
| 5321 | |
| 5322 | static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_read_CHCTRLB_CMD_bf(const void *const hw) |
| 5323 | { |
| 5324 | uint8_t tmp; |
| 5325 | tmp = ((DmacChannel *)hw)->CHCTRLB.reg; |
| 5326 | tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos; |
| 5327 | return tmp; |
| 5328 | } |
| 5329 | |
| 5330 | static inline void hri_dmacchannel_set_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) |
| 5331 | { |
| 5332 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5333 | ((DmacChannel *)hw)->CHCTRLB.reg |= mask; |
| 5334 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5335 | } |
| 5336 | |
| 5337 | static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_get_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) |
| 5338 | { |
| 5339 | uint8_t tmp; |
| 5340 | tmp = ((DmacChannel *)hw)->CHCTRLB.reg; |
| 5341 | tmp &= mask; |
| 5342 | return tmp; |
| 5343 | } |
| 5344 | |
| 5345 | static inline void hri_dmacchannel_write_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t data) |
| 5346 | { |
| 5347 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5348 | ((DmacChannel *)hw)->CHCTRLB.reg = data; |
| 5349 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5350 | } |
| 5351 | |
| 5352 | static inline void hri_dmacchannel_clear_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) |
| 5353 | { |
| 5354 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5355 | ((DmacChannel *)hw)->CHCTRLB.reg &= ~mask; |
| 5356 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5357 | } |
| 5358 | |
| 5359 | static inline void hri_dmacchannel_toggle_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) |
| 5360 | { |
| 5361 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5362 | ((DmacChannel *)hw)->CHCTRLB.reg ^= mask; |
| 5363 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5364 | } |
| 5365 | |
| 5366 | static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_read_CHCTRLB_reg(const void *const hw) |
| 5367 | { |
| 5368 | return ((DmacChannel *)hw)->CHCTRLB.reg; |
| 5369 | } |
| 5370 | |
| 5371 | static inline void hri_dmacchannel_set_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask) |
| 5372 | { |
| 5373 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5374 | ((DmacChannel *)hw)->CHPRILVL.reg |= DMAC_CHPRILVL_PRILVL(mask); |
| 5375 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5376 | } |
| 5377 | |
| 5378 | static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_get_CHPRILVL_PRILVL_bf(const void *const hw, |
| 5379 | hri_dmac_chprilvl_reg_t mask) |
| 5380 | { |
| 5381 | uint8_t tmp; |
| 5382 | tmp = ((DmacChannel *)hw)->CHPRILVL.reg; |
| 5383 | tmp = (tmp & DMAC_CHPRILVL_PRILVL(mask)) >> DMAC_CHPRILVL_PRILVL_Pos; |
| 5384 | return tmp; |
| 5385 | } |
| 5386 | |
| 5387 | static inline void hri_dmacchannel_write_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t data) |
| 5388 | { |
| 5389 | uint8_t tmp; |
| 5390 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5391 | tmp = ((DmacChannel *)hw)->CHPRILVL.reg; |
| 5392 | tmp &= ~DMAC_CHPRILVL_PRILVL_Msk; |
| 5393 | tmp |= DMAC_CHPRILVL_PRILVL(data); |
| 5394 | ((DmacChannel *)hw)->CHPRILVL.reg = tmp; |
| 5395 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5396 | } |
| 5397 | |
| 5398 | static inline void hri_dmacchannel_clear_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask) |
| 5399 | { |
| 5400 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5401 | ((DmacChannel *)hw)->CHPRILVL.reg &= ~DMAC_CHPRILVL_PRILVL(mask); |
| 5402 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5403 | } |
| 5404 | |
| 5405 | static inline void hri_dmacchannel_toggle_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask) |
| 5406 | { |
| 5407 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5408 | ((DmacChannel *)hw)->CHPRILVL.reg ^= DMAC_CHPRILVL_PRILVL(mask); |
| 5409 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5410 | } |
| 5411 | |
| 5412 | static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_read_CHPRILVL_PRILVL_bf(const void *const hw) |
| 5413 | { |
| 5414 | uint8_t tmp; |
| 5415 | tmp = ((DmacChannel *)hw)->CHPRILVL.reg; |
| 5416 | tmp = (tmp & DMAC_CHPRILVL_PRILVL_Msk) >> DMAC_CHPRILVL_PRILVL_Pos; |
| 5417 | return tmp; |
| 5418 | } |
| 5419 | |
| 5420 | static inline void hri_dmacchannel_set_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask) |
| 5421 | { |
| 5422 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5423 | ((DmacChannel *)hw)->CHPRILVL.reg |= mask; |
| 5424 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5425 | } |
| 5426 | |
| 5427 | static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_get_CHPRILVL_reg(const void *const hw, |
| 5428 | hri_dmac_chprilvl_reg_t mask) |
| 5429 | { |
| 5430 | uint8_t tmp; |
| 5431 | tmp = ((DmacChannel *)hw)->CHPRILVL.reg; |
| 5432 | tmp &= mask; |
| 5433 | return tmp; |
| 5434 | } |
| 5435 | |
| 5436 | static inline void hri_dmacchannel_write_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t data) |
| 5437 | { |
| 5438 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5439 | ((DmacChannel *)hw)->CHPRILVL.reg = data; |
| 5440 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5441 | } |
| 5442 | |
| 5443 | static inline void hri_dmacchannel_clear_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask) |
| 5444 | { |
| 5445 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5446 | ((DmacChannel *)hw)->CHPRILVL.reg &= ~mask; |
| 5447 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5448 | } |
| 5449 | |
| 5450 | static inline void hri_dmacchannel_toggle_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask) |
| 5451 | { |
| 5452 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5453 | ((DmacChannel *)hw)->CHPRILVL.reg ^= mask; |
| 5454 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5455 | } |
| 5456 | |
| 5457 | static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_read_CHPRILVL_reg(const void *const hw) |
| 5458 | { |
| 5459 | return ((DmacChannel *)hw)->CHPRILVL.reg; |
| 5460 | } |
| 5461 | |
| 5462 | static inline void hri_dmacchannel_set_CHEVCTRL_EVIE_bit(const void *const hw) |
| 5463 | { |
| 5464 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5465 | ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVIE; |
| 5466 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5467 | } |
| 5468 | |
| 5469 | static inline bool hri_dmacchannel_get_CHEVCTRL_EVIE_bit(const void *const hw) |
| 5470 | { |
| 5471 | uint8_t tmp; |
| 5472 | tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; |
| 5473 | tmp = (tmp & DMAC_CHEVCTRL_EVIE) >> DMAC_CHEVCTRL_EVIE_Pos; |
| 5474 | return (bool)tmp; |
| 5475 | } |
| 5476 | |
| 5477 | static inline void hri_dmacchannel_write_CHEVCTRL_EVIE_bit(const void *const hw, bool value) |
| 5478 | { |
| 5479 | uint8_t tmp; |
| 5480 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5481 | tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; |
| 5482 | tmp &= ~DMAC_CHEVCTRL_EVIE; |
| 5483 | tmp |= value << DMAC_CHEVCTRL_EVIE_Pos; |
| 5484 | ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; |
| 5485 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5486 | } |
| 5487 | |
| 5488 | static inline void hri_dmacchannel_clear_CHEVCTRL_EVIE_bit(const void *const hw) |
| 5489 | { |
| 5490 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5491 | ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVIE; |
| 5492 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5493 | } |
| 5494 | |
| 5495 | static inline void hri_dmacchannel_toggle_CHEVCTRL_EVIE_bit(const void *const hw) |
| 5496 | { |
| 5497 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5498 | ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVIE; |
| 5499 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5500 | } |
| 5501 | |
| 5502 | static inline void hri_dmacchannel_set_CHEVCTRL_EVOE_bit(const void *const hw) |
| 5503 | { |
| 5504 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5505 | ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOE; |
| 5506 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5507 | } |
| 5508 | |
| 5509 | static inline bool hri_dmacchannel_get_CHEVCTRL_EVOE_bit(const void *const hw) |
| 5510 | { |
| 5511 | uint8_t tmp; |
| 5512 | tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; |
| 5513 | tmp = (tmp & DMAC_CHEVCTRL_EVOE) >> DMAC_CHEVCTRL_EVOE_Pos; |
| 5514 | return (bool)tmp; |
| 5515 | } |
| 5516 | |
| 5517 | static inline void hri_dmacchannel_write_CHEVCTRL_EVOE_bit(const void *const hw, bool value) |
| 5518 | { |
| 5519 | uint8_t tmp; |
| 5520 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5521 | tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; |
| 5522 | tmp &= ~DMAC_CHEVCTRL_EVOE; |
| 5523 | tmp |= value << DMAC_CHEVCTRL_EVOE_Pos; |
| 5524 | ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; |
| 5525 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5526 | } |
| 5527 | |
| 5528 | static inline void hri_dmacchannel_clear_CHEVCTRL_EVOE_bit(const void *const hw) |
| 5529 | { |
| 5530 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5531 | ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOE; |
| 5532 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5533 | } |
| 5534 | |
| 5535 | static inline void hri_dmacchannel_toggle_CHEVCTRL_EVOE_bit(const void *const hw) |
| 5536 | { |
| 5537 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5538 | ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOE; |
| 5539 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5540 | } |
| 5541 | |
| 5542 | static inline void hri_dmacchannel_set_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) |
| 5543 | { |
| 5544 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5545 | ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVACT(mask); |
| 5546 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5547 | } |
| 5548 | |
| 5549 | static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_EVACT_bf(const void *const hw, |
| 5550 | hri_dmac_chevctrl_reg_t mask) |
| 5551 | { |
| 5552 | uint8_t tmp; |
| 5553 | tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; |
| 5554 | tmp = (tmp & DMAC_CHEVCTRL_EVACT(mask)) >> DMAC_CHEVCTRL_EVACT_Pos; |
| 5555 | return tmp; |
| 5556 | } |
| 5557 | |
| 5558 | static inline void hri_dmacchannel_write_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t data) |
| 5559 | { |
| 5560 | uint8_t tmp; |
| 5561 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5562 | tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; |
| 5563 | tmp &= ~DMAC_CHEVCTRL_EVACT_Msk; |
| 5564 | tmp |= DMAC_CHEVCTRL_EVACT(data); |
| 5565 | ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; |
| 5566 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5567 | } |
| 5568 | |
| 5569 | static inline void hri_dmacchannel_clear_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) |
| 5570 | { |
| 5571 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5572 | ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVACT(mask); |
| 5573 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5574 | } |
| 5575 | |
| 5576 | static inline void hri_dmacchannel_toggle_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) |
| 5577 | { |
| 5578 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5579 | ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVACT(mask); |
| 5580 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5581 | } |
| 5582 | |
| 5583 | static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_EVACT_bf(const void *const hw) |
| 5584 | { |
| 5585 | uint8_t tmp; |
| 5586 | tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; |
| 5587 | tmp = (tmp & DMAC_CHEVCTRL_EVACT_Msk) >> DMAC_CHEVCTRL_EVACT_Pos; |
| 5588 | return tmp; |
| 5589 | } |
| 5590 | |
| 5591 | static inline void hri_dmacchannel_set_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) |
| 5592 | { |
| 5593 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5594 | ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOMODE(mask); |
| 5595 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5596 | } |
| 5597 | |
| 5598 | static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_EVOMODE_bf(const void *const hw, |
| 5599 | hri_dmac_chevctrl_reg_t mask) |
| 5600 | { |
| 5601 | uint8_t tmp; |
| 5602 | tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; |
| 5603 | tmp = (tmp & DMAC_CHEVCTRL_EVOMODE(mask)) >> DMAC_CHEVCTRL_EVOMODE_Pos; |
| 5604 | return tmp; |
| 5605 | } |
| 5606 | |
| 5607 | static inline void hri_dmacchannel_write_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t data) |
| 5608 | { |
| 5609 | uint8_t tmp; |
| 5610 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5611 | tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; |
| 5612 | tmp &= ~DMAC_CHEVCTRL_EVOMODE_Msk; |
| 5613 | tmp |= DMAC_CHEVCTRL_EVOMODE(data); |
| 5614 | ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; |
| 5615 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5616 | } |
| 5617 | |
| 5618 | static inline void hri_dmacchannel_clear_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) |
| 5619 | { |
| 5620 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5621 | ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOMODE(mask); |
| 5622 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5623 | } |
| 5624 | |
| 5625 | static inline void hri_dmacchannel_toggle_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) |
| 5626 | { |
| 5627 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5628 | ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOMODE(mask); |
| 5629 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5630 | } |
| 5631 | |
| 5632 | static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_EVOMODE_bf(const void *const hw) |
| 5633 | { |
| 5634 | uint8_t tmp; |
| 5635 | tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; |
| 5636 | tmp = (tmp & DMAC_CHEVCTRL_EVOMODE_Msk) >> DMAC_CHEVCTRL_EVOMODE_Pos; |
| 5637 | return tmp; |
| 5638 | } |
| 5639 | |
| 5640 | static inline void hri_dmacchannel_set_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask) |
| 5641 | { |
| 5642 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5643 | ((DmacChannel *)hw)->CHEVCTRL.reg |= mask; |
| 5644 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5645 | } |
| 5646 | |
| 5647 | static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_reg(const void *const hw, |
| 5648 | hri_dmac_chevctrl_reg_t mask) |
| 5649 | { |
| 5650 | uint8_t tmp; |
| 5651 | tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; |
| 5652 | tmp &= mask; |
| 5653 | return tmp; |
| 5654 | } |
| 5655 | |
| 5656 | static inline void hri_dmacchannel_write_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t data) |
| 5657 | { |
| 5658 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5659 | ((DmacChannel *)hw)->CHEVCTRL.reg = data; |
| 5660 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5661 | } |
| 5662 | |
| 5663 | static inline void hri_dmacchannel_clear_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask) |
| 5664 | { |
| 5665 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5666 | ((DmacChannel *)hw)->CHEVCTRL.reg &= ~mask; |
| 5667 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5668 | } |
| 5669 | |
| 5670 | static inline void hri_dmacchannel_toggle_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask) |
| 5671 | { |
| 5672 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5673 | ((DmacChannel *)hw)->CHEVCTRL.reg ^= mask; |
| 5674 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5675 | } |
| 5676 | |
| 5677 | static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_reg(const void *const hw) |
| 5678 | { |
| 5679 | return ((DmacChannel *)hw)->CHEVCTRL.reg; |
| 5680 | } |
| 5681 | |
| 5682 | static inline bool hri_dmacchannel_get_CHSTATUS_PEND_bit(const void *const hw) |
| 5683 | { |
| 5684 | return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos; |
| 5685 | } |
| 5686 | |
| 5687 | static inline void hri_dmacchannel_clear_CHSTATUS_PEND_bit(const void *const hw) |
| 5688 | { |
| 5689 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5690 | ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_PEND; |
| 5691 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5692 | } |
| 5693 | |
| 5694 | static inline bool hri_dmacchannel_get_CHSTATUS_BUSY_bit(const void *const hw) |
| 5695 | { |
| 5696 | return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos; |
| 5697 | } |
| 5698 | |
| 5699 | static inline void hri_dmacchannel_clear_CHSTATUS_BUSY_bit(const void *const hw) |
| 5700 | { |
| 5701 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5702 | ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_BUSY; |
| 5703 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5704 | } |
| 5705 | |
| 5706 | static inline bool hri_dmacchannel_get_CHSTATUS_FERR_bit(const void *const hw) |
| 5707 | { |
| 5708 | return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos; |
| 5709 | } |
| 5710 | |
| 5711 | static inline void hri_dmacchannel_clear_CHSTATUS_FERR_bit(const void *const hw) |
| 5712 | { |
| 5713 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5714 | ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_FERR; |
| 5715 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5716 | } |
| 5717 | |
| 5718 | static inline bool hri_dmacchannel_get_CHSTATUS_CRCERR_bit(const void *const hw) |
| 5719 | { |
| 5720 | return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_CRCERR) >> DMAC_CHSTATUS_CRCERR_Pos; |
| 5721 | } |
| 5722 | |
| 5723 | static inline void hri_dmacchannel_clear_CHSTATUS_CRCERR_bit(const void *const hw) |
| 5724 | { |
| 5725 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5726 | ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_CRCERR; |
| 5727 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5728 | } |
| 5729 | |
| 5730 | static inline hri_dmac_chstatus_reg_t hri_dmacchannel_get_CHSTATUS_reg(const void *const hw, |
| 5731 | hri_dmac_chstatus_reg_t mask) |
| 5732 | { |
| 5733 | uint8_t tmp; |
| 5734 | tmp = ((DmacChannel *)hw)->CHSTATUS.reg; |
| 5735 | tmp &= mask; |
| 5736 | return tmp; |
| 5737 | } |
| 5738 | |
| 5739 | static inline void hri_dmacchannel_clear_CHSTATUS_reg(const void *const hw, hri_dmac_chstatus_reg_t mask) |
| 5740 | { |
| 5741 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5742 | ((DmacChannel *)hw)->CHSTATUS.reg = mask; |
| 5743 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5744 | } |
| 5745 | |
| 5746 | static inline hri_dmac_chstatus_reg_t hri_dmacchannel_read_CHSTATUS_reg(const void *const hw) |
| 5747 | { |
| 5748 | return ((DmacChannel *)hw)->CHSTATUS.reg; |
| 5749 | } |
| 5750 | |
| 5751 | static inline bool hri_dmac_get_CHINTFLAG_TERR_bit(const void *const hw, uint8_t submodule_index) |
| 5752 | { |
| 5753 | return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; |
| 5754 | } |
| 5755 | |
| 5756 | static inline void hri_dmac_clear_CHINTFLAG_TERR_bit(const void *const hw, uint8_t submodule_index) |
| 5757 | { |
| 5758 | ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; |
| 5759 | } |
| 5760 | |
| 5761 | static inline bool hri_dmac_get_CHINTFLAG_TCMPL_bit(const void *const hw, uint8_t submodule_index) |
| 5762 | { |
| 5763 | return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; |
| 5764 | } |
| 5765 | |
| 5766 | static inline void hri_dmac_clear_CHINTFLAG_TCMPL_bit(const void *const hw, uint8_t submodule_index) |
| 5767 | { |
| 5768 | ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; |
| 5769 | } |
| 5770 | |
| 5771 | static inline bool hri_dmac_get_CHINTFLAG_SUSP_bit(const void *const hw, uint8_t submodule_index) |
| 5772 | { |
| 5773 | return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; |
| 5774 | } |
| 5775 | |
| 5776 | static inline void hri_dmac_clear_CHINTFLAG_SUSP_bit(const void *const hw, uint8_t submodule_index) |
| 5777 | { |
| 5778 | ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; |
| 5779 | } |
| 5780 | |
| 5781 | static inline bool hri_dmac_get_interrupt_TERR_bit(const void *const hw, uint8_t submodule_index) |
| 5782 | { |
| 5783 | return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; |
| 5784 | } |
| 5785 | |
| 5786 | static inline void hri_dmac_clear_interrupt_TERR_bit(const void *const hw, uint8_t submodule_index) |
| 5787 | { |
| 5788 | ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; |
| 5789 | } |
| 5790 | |
| 5791 | static inline bool hri_dmac_get_interrupt_TCMPL_bit(const void *const hw, uint8_t submodule_index) |
| 5792 | { |
| 5793 | return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; |
| 5794 | } |
| 5795 | |
| 5796 | static inline void hri_dmac_clear_interrupt_TCMPL_bit(const void *const hw, uint8_t submodule_index) |
| 5797 | { |
| 5798 | ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; |
| 5799 | } |
| 5800 | |
| 5801 | static inline bool hri_dmac_get_interrupt_SUSP_bit(const void *const hw, uint8_t submodule_index) |
| 5802 | { |
| 5803 | return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; |
| 5804 | } |
| 5805 | |
| 5806 | static inline void hri_dmac_clear_interrupt_SUSP_bit(const void *const hw, uint8_t submodule_index) |
| 5807 | { |
| 5808 | ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; |
| 5809 | } |
| 5810 | |
| 5811 | static inline hri_dmac_chintflag_reg_t hri_dmac_get_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, |
| 5812 | hri_dmac_chintflag_reg_t mask) |
| 5813 | { |
| 5814 | uint8_t tmp; |
| 5815 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg; |
| 5816 | tmp &= mask; |
| 5817 | return tmp; |
| 5818 | } |
| 5819 | |
| 5820 | static inline hri_dmac_chintflag_reg_t hri_dmac_read_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index) |
| 5821 | { |
| 5822 | return ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg; |
| 5823 | } |
| 5824 | |
| 5825 | static inline void hri_dmac_clear_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, |
| 5826 | hri_dmac_chintflag_reg_t mask) |
| 5827 | { |
| 5828 | ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = mask; |
| 5829 | } |
| 5830 | |
| 5831 | static inline void hri_dmac_set_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index) |
| 5832 | { |
| 5833 | ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TERR; |
| 5834 | } |
| 5835 | |
| 5836 | static inline bool hri_dmac_get_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index) |
| 5837 | { |
| 5838 | return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; |
| 5839 | } |
| 5840 | |
| 5841 | static inline void hri_dmac_write_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index, bool value) |
| 5842 | { |
| 5843 | if (value == 0x0) { |
| 5844 | ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TERR; |
| 5845 | } else { |
| 5846 | ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TERR; |
| 5847 | } |
| 5848 | } |
| 5849 | |
| 5850 | static inline void hri_dmac_clear_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index) |
| 5851 | { |
| 5852 | ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TERR; |
| 5853 | } |
| 5854 | |
| 5855 | static inline void hri_dmac_set_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index) |
| 5856 | { |
| 5857 | ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; |
| 5858 | } |
| 5859 | |
| 5860 | static inline bool hri_dmac_get_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index) |
| 5861 | { |
| 5862 | return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos; |
| 5863 | } |
| 5864 | |
| 5865 | static inline void hri_dmac_write_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index, bool value) |
| 5866 | { |
| 5867 | if (value == 0x0) { |
| 5868 | ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; |
| 5869 | } else { |
| 5870 | ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; |
| 5871 | } |
| 5872 | } |
| 5873 | |
| 5874 | static inline void hri_dmac_clear_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index) |
| 5875 | { |
| 5876 | ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; |
| 5877 | } |
| 5878 | |
| 5879 | static inline void hri_dmac_set_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index) |
| 5880 | { |
| 5881 | ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_SUSP; |
| 5882 | } |
| 5883 | |
| 5884 | static inline bool hri_dmac_get_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index) |
| 5885 | { |
| 5886 | return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos; |
| 5887 | } |
| 5888 | |
| 5889 | static inline void hri_dmac_write_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index, bool value) |
| 5890 | { |
| 5891 | if (value == 0x0) { |
| 5892 | ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; |
| 5893 | } else { |
| 5894 | ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_SUSP; |
| 5895 | } |
| 5896 | } |
| 5897 | |
| 5898 | static inline void hri_dmac_clear_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index) |
| 5899 | { |
| 5900 | ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; |
| 5901 | } |
| 5902 | |
| 5903 | static inline void hri_dmac_set_CHINTEN_reg(const void *const hw, uint8_t submodule_index, |
| 5904 | hri_dmac_chintenset_reg_t mask) |
| 5905 | { |
| 5906 | ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = mask; |
| 5907 | } |
| 5908 | |
| 5909 | static inline hri_dmac_chintenset_reg_t hri_dmac_get_CHINTEN_reg(const void *const hw, uint8_t submodule_index, |
| 5910 | hri_dmac_chintenset_reg_t mask) |
| 5911 | { |
| 5912 | uint8_t tmp; |
| 5913 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg; |
| 5914 | tmp &= mask; |
| 5915 | return tmp; |
| 5916 | } |
| 5917 | |
| 5918 | static inline hri_dmac_chintenset_reg_t hri_dmac_read_CHINTEN_reg(const void *const hw, uint8_t submodule_index) |
| 5919 | { |
| 5920 | return ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg; |
| 5921 | } |
| 5922 | |
| 5923 | static inline void hri_dmac_write_CHINTEN_reg(const void *const hw, uint8_t submodule_index, |
| 5924 | hri_dmac_chintenset_reg_t data) |
| 5925 | { |
| 5926 | ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = data; |
| 5927 | ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = ~data; |
| 5928 | } |
| 5929 | |
| 5930 | static inline void hri_dmac_clear_CHINTEN_reg(const void *const hw, uint8_t submodule_index, |
| 5931 | hri_dmac_chintenset_reg_t mask) |
| 5932 | { |
| 5933 | ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = mask; |
| 5934 | } |
| 5935 | |
| 5936 | static inline void hri_dmac_set_CHCTRLA_SWRST_bit(const void *const hw, uint8_t submodule_index) |
| 5937 | { |
| 5938 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5939 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_SWRST; |
| 5940 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5941 | } |
| 5942 | |
| 5943 | static inline bool hri_dmac_get_CHCTRLA_SWRST_bit(const void *const hw, uint8_t submodule_index) |
| 5944 | { |
| 5945 | uint32_t tmp; |
| 5946 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; |
| 5947 | tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos; |
| 5948 | return (bool)tmp; |
| 5949 | } |
| 5950 | |
| 5951 | static inline void hri_dmac_set_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) |
| 5952 | { |
| 5953 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5954 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; |
| 5955 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5956 | } |
| 5957 | |
| 5958 | static inline bool hri_dmac_get_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) |
| 5959 | { |
| 5960 | uint32_t tmp; |
| 5961 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; |
| 5962 | tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos; |
| 5963 | return (bool)tmp; |
| 5964 | } |
| 5965 | |
| 5966 | static inline void hri_dmac_write_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index, bool value) |
| 5967 | { |
| 5968 | uint32_t tmp; |
| 5969 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5970 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; |
| 5971 | tmp &= ~DMAC_CHCTRLA_ENABLE; |
| 5972 | tmp |= value << DMAC_CHCTRLA_ENABLE_Pos; |
| 5973 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; |
| 5974 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5975 | } |
| 5976 | |
| 5977 | static inline void hri_dmac_clear_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) |
| 5978 | { |
| 5979 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5980 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; |
| 5981 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5982 | } |
| 5983 | |
| 5984 | static inline void hri_dmac_toggle_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) |
| 5985 | { |
| 5986 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5987 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE; |
| 5988 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5989 | } |
| 5990 | |
| 5991 | static inline void hri_dmac_set_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) |
| 5992 | { |
| 5993 | DMAC_CRITICAL_SECTION_ENTER(); |
| 5994 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; |
| 5995 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 5996 | } |
| 5997 | |
| 5998 | static inline bool hri_dmac_get_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) |
| 5999 | { |
| 6000 | uint32_t tmp; |
| 6001 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; |
| 6002 | tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos; |
| 6003 | return (bool)tmp; |
| 6004 | } |
| 6005 | |
| 6006 | static inline void hri_dmac_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value) |
| 6007 | { |
| 6008 | uint32_t tmp; |
| 6009 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6010 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; |
| 6011 | tmp &= ~DMAC_CHCTRLA_RUNSTDBY; |
| 6012 | tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos; |
| 6013 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; |
| 6014 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6015 | } |
| 6016 | |
| 6017 | static inline void hri_dmac_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) |
| 6018 | { |
| 6019 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6020 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY; |
| 6021 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6022 | } |
| 6023 | |
| 6024 | static inline void hri_dmac_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) |
| 6025 | { |
| 6026 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6027 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY; |
| 6028 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6029 | } |
| 6030 | |
| 6031 | static inline void hri_dmac_set_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, |
| 6032 | hri_dmac_chctrla_reg_t mask) |
| 6033 | { |
| 6034 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6035 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_TRIGSRC(mask); |
| 6036 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6037 | } |
| 6038 | |
| 6039 | static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, |
| 6040 | hri_dmac_chctrla_reg_t mask) |
| 6041 | { |
| 6042 | uint32_t tmp; |
| 6043 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; |
| 6044 | tmp = (tmp & DMAC_CHCTRLA_TRIGSRC(mask)) >> DMAC_CHCTRLA_TRIGSRC_Pos; |
| 6045 | return tmp; |
| 6046 | } |
| 6047 | |
| 6048 | static inline void hri_dmac_write_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, |
| 6049 | hri_dmac_chctrla_reg_t data) |
| 6050 | { |
| 6051 | uint32_t tmp; |
| 6052 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6053 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; |
| 6054 | tmp &= ~DMAC_CHCTRLA_TRIGSRC_Msk; |
| 6055 | tmp |= DMAC_CHCTRLA_TRIGSRC(data); |
| 6056 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; |
| 6057 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6058 | } |
| 6059 | |
| 6060 | static inline void hri_dmac_clear_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, |
| 6061 | hri_dmac_chctrla_reg_t mask) |
| 6062 | { |
| 6063 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6064 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGSRC(mask); |
| 6065 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6066 | } |
| 6067 | |
| 6068 | static inline void hri_dmac_toggle_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, |
| 6069 | hri_dmac_chctrla_reg_t mask) |
| 6070 | { |
| 6071 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6072 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGSRC(mask); |
| 6073 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6074 | } |
| 6075 | |
| 6076 | static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index) |
| 6077 | { |
| 6078 | uint32_t tmp; |
| 6079 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; |
| 6080 | tmp = (tmp & DMAC_CHCTRLA_TRIGSRC_Msk) >> DMAC_CHCTRLA_TRIGSRC_Pos; |
| 6081 | return tmp; |
| 6082 | } |
| 6083 | |
| 6084 | static inline void hri_dmac_set_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, |
| 6085 | hri_dmac_chctrla_reg_t mask) |
| 6086 | { |
| 6087 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6088 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_TRIGACT(mask); |
| 6089 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6090 | } |
| 6091 | |
| 6092 | static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, |
| 6093 | hri_dmac_chctrla_reg_t mask) |
| 6094 | { |
| 6095 | uint32_t tmp; |
| 6096 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; |
| 6097 | tmp = (tmp & DMAC_CHCTRLA_TRIGACT(mask)) >> DMAC_CHCTRLA_TRIGACT_Pos; |
| 6098 | return tmp; |
| 6099 | } |
| 6100 | |
| 6101 | static inline void hri_dmac_write_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, |
| 6102 | hri_dmac_chctrla_reg_t data) |
| 6103 | { |
| 6104 | uint32_t tmp; |
| 6105 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6106 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; |
| 6107 | tmp &= ~DMAC_CHCTRLA_TRIGACT_Msk; |
| 6108 | tmp |= DMAC_CHCTRLA_TRIGACT(data); |
| 6109 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; |
| 6110 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6111 | } |
| 6112 | |
| 6113 | static inline void hri_dmac_clear_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, |
| 6114 | hri_dmac_chctrla_reg_t mask) |
| 6115 | { |
| 6116 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6117 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGACT(mask); |
| 6118 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6119 | } |
| 6120 | |
| 6121 | static inline void hri_dmac_toggle_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, |
| 6122 | hri_dmac_chctrla_reg_t mask) |
| 6123 | { |
| 6124 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6125 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGACT(mask); |
| 6126 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6127 | } |
| 6128 | |
| 6129 | static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index) |
| 6130 | { |
| 6131 | uint32_t tmp; |
| 6132 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; |
| 6133 | tmp = (tmp & DMAC_CHCTRLA_TRIGACT_Msk) >> DMAC_CHCTRLA_TRIGACT_Pos; |
| 6134 | return tmp; |
| 6135 | } |
| 6136 | |
| 6137 | static inline void hri_dmac_set_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, |
| 6138 | hri_dmac_chctrla_reg_t mask) |
| 6139 | { |
| 6140 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6141 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_BURSTLEN(mask); |
| 6142 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6143 | } |
| 6144 | |
| 6145 | static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, |
| 6146 | hri_dmac_chctrla_reg_t mask) |
| 6147 | { |
| 6148 | uint32_t tmp; |
| 6149 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; |
| 6150 | tmp = (tmp & DMAC_CHCTRLA_BURSTLEN(mask)) >> DMAC_CHCTRLA_BURSTLEN_Pos; |
| 6151 | return tmp; |
| 6152 | } |
| 6153 | |
| 6154 | static inline void hri_dmac_write_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, |
| 6155 | hri_dmac_chctrla_reg_t data) |
| 6156 | { |
| 6157 | uint32_t tmp; |
| 6158 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6159 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; |
| 6160 | tmp &= ~DMAC_CHCTRLA_BURSTLEN_Msk; |
| 6161 | tmp |= DMAC_CHCTRLA_BURSTLEN(data); |
| 6162 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; |
| 6163 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6164 | } |
| 6165 | |
| 6166 | static inline void hri_dmac_clear_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, |
| 6167 | hri_dmac_chctrla_reg_t mask) |
| 6168 | { |
| 6169 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6170 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_BURSTLEN(mask); |
| 6171 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6172 | } |
| 6173 | |
| 6174 | static inline void hri_dmac_toggle_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, |
| 6175 | hri_dmac_chctrla_reg_t mask) |
| 6176 | { |
| 6177 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6178 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_BURSTLEN(mask); |
| 6179 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6180 | } |
| 6181 | |
| 6182 | static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index) |
| 6183 | { |
| 6184 | uint32_t tmp; |
| 6185 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; |
| 6186 | tmp = (tmp & DMAC_CHCTRLA_BURSTLEN_Msk) >> DMAC_CHCTRLA_BURSTLEN_Pos; |
| 6187 | return tmp; |
| 6188 | } |
| 6189 | |
| 6190 | static inline void hri_dmac_set_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, |
| 6191 | hri_dmac_chctrla_reg_t mask) |
| 6192 | { |
| 6193 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6194 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_THRESHOLD(mask); |
| 6195 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6196 | } |
| 6197 | |
| 6198 | static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, |
| 6199 | hri_dmac_chctrla_reg_t mask) |
| 6200 | { |
| 6201 | uint32_t tmp; |
| 6202 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; |
| 6203 | tmp = (tmp & DMAC_CHCTRLA_THRESHOLD(mask)) >> DMAC_CHCTRLA_THRESHOLD_Pos; |
| 6204 | return tmp; |
| 6205 | } |
| 6206 | |
| 6207 | static inline void hri_dmac_write_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, |
| 6208 | hri_dmac_chctrla_reg_t data) |
| 6209 | { |
| 6210 | uint32_t tmp; |
| 6211 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6212 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; |
| 6213 | tmp &= ~DMAC_CHCTRLA_THRESHOLD_Msk; |
| 6214 | tmp |= DMAC_CHCTRLA_THRESHOLD(data); |
| 6215 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; |
| 6216 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6217 | } |
| 6218 | |
| 6219 | static inline void hri_dmac_clear_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, |
| 6220 | hri_dmac_chctrla_reg_t mask) |
| 6221 | { |
| 6222 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6223 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_THRESHOLD(mask); |
| 6224 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6225 | } |
| 6226 | |
| 6227 | static inline void hri_dmac_toggle_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, |
| 6228 | hri_dmac_chctrla_reg_t mask) |
| 6229 | { |
| 6230 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6231 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_THRESHOLD(mask); |
| 6232 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6233 | } |
| 6234 | |
| 6235 | static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index) |
| 6236 | { |
| 6237 | uint32_t tmp; |
| 6238 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; |
| 6239 | tmp = (tmp & DMAC_CHCTRLA_THRESHOLD_Msk) >> DMAC_CHCTRLA_THRESHOLD_Pos; |
| 6240 | return tmp; |
| 6241 | } |
| 6242 | |
| 6243 | static inline void hri_dmac_set_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, hri_dmac_chctrla_reg_t mask) |
| 6244 | { |
| 6245 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6246 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= mask; |
| 6247 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6248 | } |
| 6249 | |
| 6250 | static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, |
| 6251 | hri_dmac_chctrla_reg_t mask) |
| 6252 | { |
| 6253 | uint32_t tmp; |
| 6254 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; |
| 6255 | tmp &= mask; |
| 6256 | return tmp; |
| 6257 | } |
| 6258 | |
| 6259 | static inline void hri_dmac_write_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, |
| 6260 | hri_dmac_chctrla_reg_t data) |
| 6261 | { |
| 6262 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6263 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = data; |
| 6264 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6265 | } |
| 6266 | |
| 6267 | static inline void hri_dmac_clear_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, |
| 6268 | hri_dmac_chctrla_reg_t mask) |
| 6269 | { |
| 6270 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6271 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~mask; |
| 6272 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6273 | } |
| 6274 | |
| 6275 | static inline void hri_dmac_toggle_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, |
| 6276 | hri_dmac_chctrla_reg_t mask) |
| 6277 | { |
| 6278 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6279 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= mask; |
| 6280 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6281 | } |
| 6282 | |
| 6283 | static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_reg(const void *const hw, uint8_t submodule_index) |
| 6284 | { |
| 6285 | return ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; |
| 6286 | } |
| 6287 | |
| 6288 | static inline void hri_dmac_set_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, |
| 6289 | hri_dmac_chctrlb_reg_t mask) |
| 6290 | { |
| 6291 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6292 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask); |
| 6293 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6294 | } |
| 6295 | |
| 6296 | static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, |
| 6297 | hri_dmac_chctrlb_reg_t mask) |
| 6298 | { |
| 6299 | uint8_t tmp; |
| 6300 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; |
| 6301 | tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos; |
| 6302 | return tmp; |
| 6303 | } |
| 6304 | |
| 6305 | static inline void hri_dmac_write_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, |
| 6306 | hri_dmac_chctrlb_reg_t data) |
| 6307 | { |
| 6308 | uint8_t tmp; |
| 6309 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6310 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; |
| 6311 | tmp &= ~DMAC_CHCTRLB_CMD_Msk; |
| 6312 | tmp |= DMAC_CHCTRLB_CMD(data); |
| 6313 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg = tmp; |
| 6314 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6315 | } |
| 6316 | |
| 6317 | static inline void hri_dmac_clear_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, |
| 6318 | hri_dmac_chctrlb_reg_t mask) |
| 6319 | { |
| 6320 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6321 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask); |
| 6322 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6323 | } |
| 6324 | |
| 6325 | static inline void hri_dmac_toggle_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, |
| 6326 | hri_dmac_chctrlb_reg_t mask) |
| 6327 | { |
| 6328 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6329 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask); |
| 6330 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6331 | } |
| 6332 | |
| 6333 | static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index) |
| 6334 | { |
| 6335 | uint8_t tmp; |
| 6336 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; |
| 6337 | tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos; |
| 6338 | return tmp; |
| 6339 | } |
| 6340 | |
| 6341 | static inline void hri_dmac_set_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, hri_dmac_chctrlb_reg_t mask) |
| 6342 | { |
| 6343 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6344 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg |= mask; |
| 6345 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6346 | } |
| 6347 | |
| 6348 | static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, |
| 6349 | hri_dmac_chctrlb_reg_t mask) |
| 6350 | { |
| 6351 | uint8_t tmp; |
| 6352 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; |
| 6353 | tmp &= mask; |
| 6354 | return tmp; |
| 6355 | } |
| 6356 | |
| 6357 | static inline void hri_dmac_write_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, |
| 6358 | hri_dmac_chctrlb_reg_t data) |
| 6359 | { |
| 6360 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6361 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg = data; |
| 6362 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6363 | } |
| 6364 | |
| 6365 | static inline void hri_dmac_clear_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, |
| 6366 | hri_dmac_chctrlb_reg_t mask) |
| 6367 | { |
| 6368 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6369 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg &= ~mask; |
| 6370 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6371 | } |
| 6372 | |
| 6373 | static inline void hri_dmac_toggle_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, |
| 6374 | hri_dmac_chctrlb_reg_t mask) |
| 6375 | { |
| 6376 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6377 | ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg ^= mask; |
| 6378 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6379 | } |
| 6380 | |
| 6381 | static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_reg(const void *const hw, uint8_t submodule_index) |
| 6382 | { |
| 6383 | return ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; |
| 6384 | } |
| 6385 | |
| 6386 | static inline void hri_dmac_set_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, |
| 6387 | hri_dmac_chprilvl_reg_t mask) |
| 6388 | { |
| 6389 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6390 | ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg |= DMAC_CHPRILVL_PRILVL(mask); |
| 6391 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6392 | } |
| 6393 | |
| 6394 | static inline hri_dmac_chprilvl_reg_t hri_dmac_get_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, |
| 6395 | hri_dmac_chprilvl_reg_t mask) |
| 6396 | { |
| 6397 | uint8_t tmp; |
| 6398 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; |
| 6399 | tmp = (tmp & DMAC_CHPRILVL_PRILVL(mask)) >> DMAC_CHPRILVL_PRILVL_Pos; |
| 6400 | return tmp; |
| 6401 | } |
| 6402 | |
| 6403 | static inline void hri_dmac_write_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, |
| 6404 | hri_dmac_chprilvl_reg_t data) |
| 6405 | { |
| 6406 | uint8_t tmp; |
| 6407 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6408 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; |
| 6409 | tmp &= ~DMAC_CHPRILVL_PRILVL_Msk; |
| 6410 | tmp |= DMAC_CHPRILVL_PRILVL(data); |
| 6411 | ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg = tmp; |
| 6412 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6413 | } |
| 6414 | |
| 6415 | static inline void hri_dmac_clear_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, |
| 6416 | hri_dmac_chprilvl_reg_t mask) |
| 6417 | { |
| 6418 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6419 | ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg &= ~DMAC_CHPRILVL_PRILVL(mask); |
| 6420 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6421 | } |
| 6422 | |
| 6423 | static inline void hri_dmac_toggle_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, |
| 6424 | hri_dmac_chprilvl_reg_t mask) |
| 6425 | { |
| 6426 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6427 | ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg ^= DMAC_CHPRILVL_PRILVL(mask); |
| 6428 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6429 | } |
| 6430 | |
| 6431 | static inline hri_dmac_chprilvl_reg_t hri_dmac_read_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index) |
| 6432 | { |
| 6433 | uint8_t tmp; |
| 6434 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; |
| 6435 | tmp = (tmp & DMAC_CHPRILVL_PRILVL_Msk) >> DMAC_CHPRILVL_PRILVL_Pos; |
| 6436 | return tmp; |
| 6437 | } |
| 6438 | |
| 6439 | static inline void hri_dmac_set_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, |
| 6440 | hri_dmac_chprilvl_reg_t mask) |
| 6441 | { |
| 6442 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6443 | ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg |= mask; |
| 6444 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6445 | } |
| 6446 | |
| 6447 | static inline hri_dmac_chprilvl_reg_t hri_dmac_get_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, |
| 6448 | hri_dmac_chprilvl_reg_t mask) |
| 6449 | { |
| 6450 | uint8_t tmp; |
| 6451 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; |
| 6452 | tmp &= mask; |
| 6453 | return tmp; |
| 6454 | } |
| 6455 | |
| 6456 | static inline void hri_dmac_write_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, |
| 6457 | hri_dmac_chprilvl_reg_t data) |
| 6458 | { |
| 6459 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6460 | ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg = data; |
| 6461 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6462 | } |
| 6463 | |
| 6464 | static inline void hri_dmac_clear_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, |
| 6465 | hri_dmac_chprilvl_reg_t mask) |
| 6466 | { |
| 6467 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6468 | ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg &= ~mask; |
| 6469 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6470 | } |
| 6471 | |
| 6472 | static inline void hri_dmac_toggle_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, |
| 6473 | hri_dmac_chprilvl_reg_t mask) |
| 6474 | { |
| 6475 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6476 | ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg ^= mask; |
| 6477 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6478 | } |
| 6479 | |
| 6480 | static inline hri_dmac_chprilvl_reg_t hri_dmac_read_CHPRILVL_reg(const void *const hw, uint8_t submodule_index) |
| 6481 | { |
| 6482 | return ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; |
| 6483 | } |
| 6484 | |
| 6485 | static inline void hri_dmac_set_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) |
| 6486 | { |
| 6487 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6488 | ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVIE; |
| 6489 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6490 | } |
| 6491 | |
| 6492 | static inline bool hri_dmac_get_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) |
| 6493 | { |
| 6494 | uint8_t tmp; |
| 6495 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; |
| 6496 | tmp = (tmp & DMAC_CHEVCTRL_EVIE) >> DMAC_CHEVCTRL_EVIE_Pos; |
| 6497 | return (bool)tmp; |
| 6498 | } |
| 6499 | |
| 6500 | static inline void hri_dmac_write_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index, bool value) |
| 6501 | { |
| 6502 | uint8_t tmp; |
| 6503 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6504 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; |
| 6505 | tmp &= ~DMAC_CHEVCTRL_EVIE; |
| 6506 | tmp |= value << DMAC_CHEVCTRL_EVIE_Pos; |
| 6507 | ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; |
| 6508 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6509 | } |
| 6510 | |
| 6511 | static inline void hri_dmac_clear_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) |
| 6512 | { |
| 6513 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6514 | ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVIE; |
| 6515 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6516 | } |
| 6517 | |
| 6518 | static inline void hri_dmac_toggle_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) |
| 6519 | { |
| 6520 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6521 | ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVIE; |
| 6522 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6523 | } |
| 6524 | |
| 6525 | static inline void hri_dmac_set_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) |
| 6526 | { |
| 6527 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6528 | ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOE; |
| 6529 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6530 | } |
| 6531 | |
| 6532 | static inline bool hri_dmac_get_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) |
| 6533 | { |
| 6534 | uint8_t tmp; |
| 6535 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; |
| 6536 | tmp = (tmp & DMAC_CHEVCTRL_EVOE) >> DMAC_CHEVCTRL_EVOE_Pos; |
| 6537 | return (bool)tmp; |
| 6538 | } |
| 6539 | |
| 6540 | static inline void hri_dmac_write_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index, bool value) |
| 6541 | { |
| 6542 | uint8_t tmp; |
| 6543 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6544 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; |
| 6545 | tmp &= ~DMAC_CHEVCTRL_EVOE; |
| 6546 | tmp |= value << DMAC_CHEVCTRL_EVOE_Pos; |
| 6547 | ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; |
| 6548 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6549 | } |
| 6550 | |
| 6551 | static inline void hri_dmac_clear_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) |
| 6552 | { |
| 6553 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6554 | ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOE; |
| 6555 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6556 | } |
| 6557 | |
| 6558 | static inline void hri_dmac_toggle_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) |
| 6559 | { |
| 6560 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6561 | ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOE; |
| 6562 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6563 | } |
| 6564 | |
| 6565 | static inline void hri_dmac_set_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, |
| 6566 | hri_dmac_chevctrl_reg_t mask) |
| 6567 | { |
| 6568 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6569 | ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVACT(mask); |
| 6570 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6571 | } |
| 6572 | |
| 6573 | static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, |
| 6574 | hri_dmac_chevctrl_reg_t mask) |
| 6575 | { |
| 6576 | uint8_t tmp; |
| 6577 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; |
| 6578 | tmp = (tmp & DMAC_CHEVCTRL_EVACT(mask)) >> DMAC_CHEVCTRL_EVACT_Pos; |
| 6579 | return tmp; |
| 6580 | } |
| 6581 | |
| 6582 | static inline void hri_dmac_write_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, |
| 6583 | hri_dmac_chevctrl_reg_t data) |
| 6584 | { |
| 6585 | uint8_t tmp; |
| 6586 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6587 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; |
| 6588 | tmp &= ~DMAC_CHEVCTRL_EVACT_Msk; |
| 6589 | tmp |= DMAC_CHEVCTRL_EVACT(data); |
| 6590 | ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; |
| 6591 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6592 | } |
| 6593 | |
| 6594 | static inline void hri_dmac_clear_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, |
| 6595 | hri_dmac_chevctrl_reg_t mask) |
| 6596 | { |
| 6597 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6598 | ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVACT(mask); |
| 6599 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6600 | } |
| 6601 | |
| 6602 | static inline void hri_dmac_toggle_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, |
| 6603 | hri_dmac_chevctrl_reg_t mask) |
| 6604 | { |
| 6605 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6606 | ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVACT(mask); |
| 6607 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6608 | } |
| 6609 | |
| 6610 | static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index) |
| 6611 | { |
| 6612 | uint8_t tmp; |
| 6613 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; |
| 6614 | tmp = (tmp & DMAC_CHEVCTRL_EVACT_Msk) >> DMAC_CHEVCTRL_EVACT_Pos; |
| 6615 | return tmp; |
| 6616 | } |
| 6617 | |
| 6618 | static inline void hri_dmac_set_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, |
| 6619 | hri_dmac_chevctrl_reg_t mask) |
| 6620 | { |
| 6621 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6622 | ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOMODE(mask); |
| 6623 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6624 | } |
| 6625 | |
| 6626 | static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, |
| 6627 | hri_dmac_chevctrl_reg_t mask) |
| 6628 | { |
| 6629 | uint8_t tmp; |
| 6630 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; |
| 6631 | tmp = (tmp & DMAC_CHEVCTRL_EVOMODE(mask)) >> DMAC_CHEVCTRL_EVOMODE_Pos; |
| 6632 | return tmp; |
| 6633 | } |
| 6634 | |
| 6635 | static inline void hri_dmac_write_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, |
| 6636 | hri_dmac_chevctrl_reg_t data) |
| 6637 | { |
| 6638 | uint8_t tmp; |
| 6639 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6640 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; |
| 6641 | tmp &= ~DMAC_CHEVCTRL_EVOMODE_Msk; |
| 6642 | tmp |= DMAC_CHEVCTRL_EVOMODE(data); |
| 6643 | ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; |
| 6644 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6645 | } |
| 6646 | |
| 6647 | static inline void hri_dmac_clear_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, |
| 6648 | hri_dmac_chevctrl_reg_t mask) |
| 6649 | { |
| 6650 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6651 | ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOMODE(mask); |
| 6652 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6653 | } |
| 6654 | |
| 6655 | static inline void hri_dmac_toggle_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, |
| 6656 | hri_dmac_chevctrl_reg_t mask) |
| 6657 | { |
| 6658 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6659 | ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOMODE(mask); |
| 6660 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6661 | } |
| 6662 | |
| 6663 | static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index) |
| 6664 | { |
| 6665 | uint8_t tmp; |
| 6666 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; |
| 6667 | tmp = (tmp & DMAC_CHEVCTRL_EVOMODE_Msk) >> DMAC_CHEVCTRL_EVOMODE_Pos; |
| 6668 | return tmp; |
| 6669 | } |
| 6670 | |
| 6671 | static inline void hri_dmac_set_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, |
| 6672 | hri_dmac_chevctrl_reg_t mask) |
| 6673 | { |
| 6674 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6675 | ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= mask; |
| 6676 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6677 | } |
| 6678 | |
| 6679 | static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, |
| 6680 | hri_dmac_chevctrl_reg_t mask) |
| 6681 | { |
| 6682 | uint8_t tmp; |
| 6683 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; |
| 6684 | tmp &= mask; |
| 6685 | return tmp; |
| 6686 | } |
| 6687 | |
| 6688 | static inline void hri_dmac_write_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, |
| 6689 | hri_dmac_chevctrl_reg_t data) |
| 6690 | { |
| 6691 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6692 | ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = data; |
| 6693 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6694 | } |
| 6695 | |
| 6696 | static inline void hri_dmac_clear_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, |
| 6697 | hri_dmac_chevctrl_reg_t mask) |
| 6698 | { |
| 6699 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6700 | ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~mask; |
| 6701 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6702 | } |
| 6703 | |
| 6704 | static inline void hri_dmac_toggle_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, |
| 6705 | hri_dmac_chevctrl_reg_t mask) |
| 6706 | { |
| 6707 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6708 | ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= mask; |
| 6709 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6710 | } |
| 6711 | |
| 6712 | static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index) |
| 6713 | { |
| 6714 | return ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; |
| 6715 | } |
| 6716 | |
| 6717 | static inline bool hri_dmac_get_CHSTATUS_PEND_bit(const void *const hw, uint8_t submodule_index) |
| 6718 | { |
| 6719 | return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos; |
| 6720 | } |
| 6721 | |
| 6722 | static inline void hri_dmac_clear_CHSTATUS_PEND_bit(const void *const hw, uint8_t submodule_index) |
| 6723 | { |
| 6724 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6725 | ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_PEND; |
| 6726 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6727 | } |
| 6728 | |
| 6729 | static inline bool hri_dmac_get_CHSTATUS_BUSY_bit(const void *const hw, uint8_t submodule_index) |
| 6730 | { |
| 6731 | return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos; |
| 6732 | } |
| 6733 | |
| 6734 | static inline void hri_dmac_clear_CHSTATUS_BUSY_bit(const void *const hw, uint8_t submodule_index) |
| 6735 | { |
| 6736 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6737 | ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_BUSY; |
| 6738 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6739 | } |
| 6740 | |
| 6741 | static inline bool hri_dmac_get_CHSTATUS_FERR_bit(const void *const hw, uint8_t submodule_index) |
| 6742 | { |
| 6743 | return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos; |
| 6744 | } |
| 6745 | |
| 6746 | static inline void hri_dmac_clear_CHSTATUS_FERR_bit(const void *const hw, uint8_t submodule_index) |
| 6747 | { |
| 6748 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6749 | ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_FERR; |
| 6750 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6751 | } |
| 6752 | |
| 6753 | static inline bool hri_dmac_get_CHSTATUS_CRCERR_bit(const void *const hw, uint8_t submodule_index) |
| 6754 | { |
| 6755 | return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_CRCERR) >> DMAC_CHSTATUS_CRCERR_Pos; |
| 6756 | } |
| 6757 | |
| 6758 | static inline void hri_dmac_clear_CHSTATUS_CRCERR_bit(const void *const hw, uint8_t submodule_index) |
| 6759 | { |
| 6760 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6761 | ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_CRCERR; |
| 6762 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6763 | } |
| 6764 | |
| 6765 | static inline hri_dmac_chstatus_reg_t hri_dmac_get_CHSTATUS_reg(const void *const hw, uint8_t submodule_index, |
| 6766 | hri_dmac_chstatus_reg_t mask) |
| 6767 | { |
| 6768 | uint8_t tmp; |
| 6769 | tmp = ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg; |
| 6770 | tmp &= mask; |
| 6771 | return tmp; |
| 6772 | } |
| 6773 | |
| 6774 | static inline void hri_dmac_clear_CHSTATUS_reg(const void *const hw, uint8_t submodule_index, |
| 6775 | hri_dmac_chstatus_reg_t mask) |
| 6776 | { |
| 6777 | DMAC_CRITICAL_SECTION_ENTER(); |
| 6778 | ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = mask; |
| 6779 | DMAC_CRITICAL_SECTION_LEAVE(); |
| 6780 | } |
| 6781 | |
| 6782 | static inline hri_dmac_chstatus_reg_t hri_dmac_read_CHSTATUS_reg(const void *const hw, uint8_t submodule_index) |
| 6783 | { |
| 6784 | return ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg; |
| 6785 | } |
| 6786 | |
| 6787 | /* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ |
| 6788 | #define hri_dmacdescriptor_set_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_set_DSTADDR_reg(a, b) |
| 6789 | #define hri_dmacdescriptor_get_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_get_DSTADDR_reg(a, b) |
| 6790 | #define hri_dmacdescriptor_write_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_write_DSTADDR_reg(a, b) |
| 6791 | #define hri_dmacdescriptor_clear_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_clear_DSTADDR_reg(a, b) |
| 6792 | #define hri_dmacdescriptor_toggle_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_toggle_DSTADDR_reg(a, b) |
| 6793 | #define hri_dmacdescriptor_read_DSTADDR_CRC_reg(a) hri_dmacdescriptor_read_DSTADDR_reg(a) |
| 6794 | |
| 6795 | #ifdef __cplusplus |
| 6796 | } |
| 6797 | #endif |
| 6798 | |
| 6799 | #endif /* _HRI_DMAC_E54_H_INCLUDED */ |
| 6800 | #endif /* _SAME54_DMAC_COMPONENT_ */ |