Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM CAN |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_CAN_COMPONENT_ |
| 35 | #ifndef _HRI_CAN_E54_H_INCLUDED_ |
| 36 | #define _HRI_CAN_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_CAN_CRITICAL_SECTIONS) |
| 46 | #define CAN_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define CAN_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define CAN_CRITICAL_SECTION_ENTER() |
| 50 | #define CAN_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint32_t hri_can_cccr_reg_t; |
| 54 | typedef uint32_t hri_can_crel_reg_t; |
| 55 | typedef uint32_t hri_can_dbtp_reg_t; |
| 56 | typedef uint32_t hri_can_ecr_reg_t; |
| 57 | typedef uint32_t hri_can_endn_reg_t; |
| 58 | typedef uint32_t hri_can_gfc_reg_t; |
| 59 | typedef uint32_t hri_can_hpms_reg_t; |
| 60 | typedef uint32_t hri_can_ie_reg_t; |
| 61 | typedef uint32_t hri_can_ile_reg_t; |
| 62 | typedef uint32_t hri_can_ils_reg_t; |
| 63 | typedef uint32_t hri_can_ir_reg_t; |
| 64 | typedef uint32_t hri_can_mrcfg_reg_t; |
| 65 | typedef uint32_t hri_can_nbtp_reg_t; |
| 66 | typedef uint32_t hri_can_ndat1_reg_t; |
| 67 | typedef uint32_t hri_can_ndat2_reg_t; |
| 68 | typedef uint32_t hri_can_psr_reg_t; |
| 69 | typedef uint32_t hri_can_rwd_reg_t; |
| 70 | typedef uint32_t hri_can_rxbc_reg_t; |
| 71 | typedef uint32_t hri_can_rxesc_reg_t; |
| 72 | typedef uint32_t hri_can_rxf0a_reg_t; |
| 73 | typedef uint32_t hri_can_rxf0c_reg_t; |
| 74 | typedef uint32_t hri_can_rxf0s_reg_t; |
| 75 | typedef uint32_t hri_can_rxf1a_reg_t; |
| 76 | typedef uint32_t hri_can_rxf1c_reg_t; |
| 77 | typedef uint32_t hri_can_rxf1s_reg_t; |
| 78 | typedef uint32_t hri_can_sidfc_reg_t; |
| 79 | typedef uint32_t hri_can_tdcr_reg_t; |
| 80 | typedef uint32_t hri_can_test_reg_t; |
| 81 | typedef uint32_t hri_can_tocc_reg_t; |
| 82 | typedef uint32_t hri_can_tocv_reg_t; |
| 83 | typedef uint32_t hri_can_tscc_reg_t; |
| 84 | typedef uint32_t hri_can_tscv_reg_t; |
| 85 | typedef uint32_t hri_can_txbar_reg_t; |
| 86 | typedef uint32_t hri_can_txbc_reg_t; |
| 87 | typedef uint32_t hri_can_txbcf_reg_t; |
| 88 | typedef uint32_t hri_can_txbcie_reg_t; |
| 89 | typedef uint32_t hri_can_txbcr_reg_t; |
| 90 | typedef uint32_t hri_can_txbrp_reg_t; |
| 91 | typedef uint32_t hri_can_txbtie_reg_t; |
| 92 | typedef uint32_t hri_can_txbto_reg_t; |
| 93 | typedef uint32_t hri_can_txefa_reg_t; |
| 94 | typedef uint32_t hri_can_txefc_reg_t; |
| 95 | typedef uint32_t hri_can_txefs_reg_t; |
| 96 | typedef uint32_t hri_can_txesc_reg_t; |
| 97 | typedef uint32_t hri_can_txfqs_reg_t; |
| 98 | typedef uint32_t hri_can_xidam_reg_t; |
| 99 | typedef uint32_t hri_can_xidfc_reg_t; |
| 100 | |
| 101 | static inline hri_can_crel_reg_t hri_can_get_CREL_SUBSTEP_bf(const void *const hw, hri_can_crel_reg_t mask) |
| 102 | { |
| 103 | return (((Can *)hw)->CREL.reg & CAN_CREL_SUBSTEP(mask)) >> CAN_CREL_SUBSTEP_Pos; |
| 104 | } |
| 105 | |
| 106 | static inline hri_can_crel_reg_t hri_can_read_CREL_SUBSTEP_bf(const void *const hw) |
| 107 | { |
| 108 | return (((Can *)hw)->CREL.reg & CAN_CREL_SUBSTEP_Msk) >> CAN_CREL_SUBSTEP_Pos; |
| 109 | } |
| 110 | |
| 111 | static inline hri_can_crel_reg_t hri_can_get_CREL_STEP_bf(const void *const hw, hri_can_crel_reg_t mask) |
| 112 | { |
| 113 | return (((Can *)hw)->CREL.reg & CAN_CREL_STEP(mask)) >> CAN_CREL_STEP_Pos; |
| 114 | } |
| 115 | |
| 116 | static inline hri_can_crel_reg_t hri_can_read_CREL_STEP_bf(const void *const hw) |
| 117 | { |
| 118 | return (((Can *)hw)->CREL.reg & CAN_CREL_STEP_Msk) >> CAN_CREL_STEP_Pos; |
| 119 | } |
| 120 | |
| 121 | static inline hri_can_crel_reg_t hri_can_get_CREL_REL_bf(const void *const hw, hri_can_crel_reg_t mask) |
| 122 | { |
| 123 | return (((Can *)hw)->CREL.reg & CAN_CREL_REL(mask)) >> CAN_CREL_REL_Pos; |
| 124 | } |
| 125 | |
| 126 | static inline hri_can_crel_reg_t hri_can_read_CREL_REL_bf(const void *const hw) |
| 127 | { |
| 128 | return (((Can *)hw)->CREL.reg & CAN_CREL_REL_Msk) >> CAN_CREL_REL_Pos; |
| 129 | } |
| 130 | |
| 131 | static inline hri_can_crel_reg_t hri_can_get_CREL_reg(const void *const hw, hri_can_crel_reg_t mask) |
| 132 | { |
| 133 | uint32_t tmp; |
| 134 | tmp = ((Can *)hw)->CREL.reg; |
| 135 | tmp &= mask; |
| 136 | return tmp; |
| 137 | } |
| 138 | |
| 139 | static inline hri_can_crel_reg_t hri_can_read_CREL_reg(const void *const hw) |
| 140 | { |
| 141 | return ((Can *)hw)->CREL.reg; |
| 142 | } |
| 143 | |
| 144 | static inline hri_can_endn_reg_t hri_can_get_ENDN_ETV_bf(const void *const hw, hri_can_endn_reg_t mask) |
| 145 | { |
| 146 | return (((Can *)hw)->ENDN.reg & CAN_ENDN_ETV(mask)) >> CAN_ENDN_ETV_Pos; |
| 147 | } |
| 148 | |
| 149 | static inline hri_can_endn_reg_t hri_can_read_ENDN_ETV_bf(const void *const hw) |
| 150 | { |
| 151 | return (((Can *)hw)->ENDN.reg & CAN_ENDN_ETV_Msk) >> CAN_ENDN_ETV_Pos; |
| 152 | } |
| 153 | |
| 154 | static inline hri_can_endn_reg_t hri_can_get_ENDN_reg(const void *const hw, hri_can_endn_reg_t mask) |
| 155 | { |
| 156 | uint32_t tmp; |
| 157 | tmp = ((Can *)hw)->ENDN.reg; |
| 158 | tmp &= mask; |
| 159 | return tmp; |
| 160 | } |
| 161 | |
| 162 | static inline hri_can_endn_reg_t hri_can_read_ENDN_reg(const void *const hw) |
| 163 | { |
| 164 | return ((Can *)hw)->ENDN.reg; |
| 165 | } |
| 166 | |
| 167 | static inline hri_can_tscv_reg_t hri_can_get_TSCV_TSC_bf(const void *const hw, hri_can_tscv_reg_t mask) |
| 168 | { |
| 169 | return (((Can *)hw)->TSCV.reg & CAN_TSCV_TSC(mask)) >> CAN_TSCV_TSC_Pos; |
| 170 | } |
| 171 | |
| 172 | static inline hri_can_tscv_reg_t hri_can_read_TSCV_TSC_bf(const void *const hw) |
| 173 | { |
| 174 | return (((Can *)hw)->TSCV.reg & CAN_TSCV_TSC_Msk) >> CAN_TSCV_TSC_Pos; |
| 175 | } |
| 176 | |
| 177 | static inline hri_can_tscv_reg_t hri_can_get_TSCV_reg(const void *const hw, hri_can_tscv_reg_t mask) |
| 178 | { |
| 179 | uint32_t tmp; |
| 180 | tmp = ((Can *)hw)->TSCV.reg; |
| 181 | tmp &= mask; |
| 182 | return tmp; |
| 183 | } |
| 184 | |
| 185 | static inline hri_can_tscv_reg_t hri_can_read_TSCV_reg(const void *const hw) |
| 186 | { |
| 187 | return ((Can *)hw)->TSCV.reg; |
| 188 | } |
| 189 | |
| 190 | static inline bool hri_can_get_ECR_RP_bit(const void *const hw) |
| 191 | { |
| 192 | return (((Can *)hw)->ECR.reg & CAN_ECR_RP) >> CAN_ECR_RP_Pos; |
| 193 | } |
| 194 | |
| 195 | static inline hri_can_ecr_reg_t hri_can_get_ECR_TEC_bf(const void *const hw, hri_can_ecr_reg_t mask) |
| 196 | { |
| 197 | return (((Can *)hw)->ECR.reg & CAN_ECR_TEC(mask)) >> CAN_ECR_TEC_Pos; |
| 198 | } |
| 199 | |
| 200 | static inline hri_can_ecr_reg_t hri_can_read_ECR_TEC_bf(const void *const hw) |
| 201 | { |
| 202 | return (((Can *)hw)->ECR.reg & CAN_ECR_TEC_Msk) >> CAN_ECR_TEC_Pos; |
| 203 | } |
| 204 | |
| 205 | static inline hri_can_ecr_reg_t hri_can_get_ECR_REC_bf(const void *const hw, hri_can_ecr_reg_t mask) |
| 206 | { |
| 207 | return (((Can *)hw)->ECR.reg & CAN_ECR_REC(mask)) >> CAN_ECR_REC_Pos; |
| 208 | } |
| 209 | |
| 210 | static inline hri_can_ecr_reg_t hri_can_read_ECR_REC_bf(const void *const hw) |
| 211 | { |
| 212 | return (((Can *)hw)->ECR.reg & CAN_ECR_REC_Msk) >> CAN_ECR_REC_Pos; |
| 213 | } |
| 214 | |
| 215 | static inline hri_can_ecr_reg_t hri_can_get_ECR_CEL_bf(const void *const hw, hri_can_ecr_reg_t mask) |
| 216 | { |
| 217 | return (((Can *)hw)->ECR.reg & CAN_ECR_CEL(mask)) >> CAN_ECR_CEL_Pos; |
| 218 | } |
| 219 | |
| 220 | static inline hri_can_ecr_reg_t hri_can_read_ECR_CEL_bf(const void *const hw) |
| 221 | { |
| 222 | return (((Can *)hw)->ECR.reg & CAN_ECR_CEL_Msk) >> CAN_ECR_CEL_Pos; |
| 223 | } |
| 224 | |
| 225 | static inline hri_can_ecr_reg_t hri_can_get_ECR_reg(const void *const hw, hri_can_ecr_reg_t mask) |
| 226 | { |
| 227 | uint32_t tmp; |
| 228 | tmp = ((Can *)hw)->ECR.reg; |
| 229 | tmp &= mask; |
| 230 | return tmp; |
| 231 | } |
| 232 | |
| 233 | static inline hri_can_ecr_reg_t hri_can_read_ECR_reg(const void *const hw) |
| 234 | { |
| 235 | return ((Can *)hw)->ECR.reg; |
| 236 | } |
| 237 | |
| 238 | static inline bool hri_can_get_PSR_EP_bit(const void *const hw) |
| 239 | { |
| 240 | return (((Can *)hw)->PSR.reg & CAN_PSR_EP) >> CAN_PSR_EP_Pos; |
| 241 | } |
| 242 | |
| 243 | static inline bool hri_can_get_PSR_EW_bit(const void *const hw) |
| 244 | { |
| 245 | return (((Can *)hw)->PSR.reg & CAN_PSR_EW) >> CAN_PSR_EW_Pos; |
| 246 | } |
| 247 | |
| 248 | static inline bool hri_can_get_PSR_BO_bit(const void *const hw) |
| 249 | { |
| 250 | return (((Can *)hw)->PSR.reg & CAN_PSR_BO) >> CAN_PSR_BO_Pos; |
| 251 | } |
| 252 | |
| 253 | static inline bool hri_can_get_PSR_RESI_bit(const void *const hw) |
| 254 | { |
| 255 | return (((Can *)hw)->PSR.reg & CAN_PSR_RESI) >> CAN_PSR_RESI_Pos; |
| 256 | } |
| 257 | |
| 258 | static inline bool hri_can_get_PSR_RBRS_bit(const void *const hw) |
| 259 | { |
| 260 | return (((Can *)hw)->PSR.reg & CAN_PSR_RBRS) >> CAN_PSR_RBRS_Pos; |
| 261 | } |
| 262 | |
| 263 | static inline bool hri_can_get_PSR_RFDF_bit(const void *const hw) |
| 264 | { |
| 265 | return (((Can *)hw)->PSR.reg & CAN_PSR_RFDF) >> CAN_PSR_RFDF_Pos; |
| 266 | } |
| 267 | |
| 268 | static inline bool hri_can_get_PSR_PXE_bit(const void *const hw) |
| 269 | { |
| 270 | return (((Can *)hw)->PSR.reg & CAN_PSR_PXE) >> CAN_PSR_PXE_Pos; |
| 271 | } |
| 272 | |
| 273 | static inline hri_can_psr_reg_t hri_can_get_PSR_LEC_bf(const void *const hw, hri_can_psr_reg_t mask) |
| 274 | { |
| 275 | return (((Can *)hw)->PSR.reg & CAN_PSR_LEC(mask)) >> CAN_PSR_LEC_Pos; |
| 276 | } |
| 277 | |
| 278 | static inline hri_can_psr_reg_t hri_can_read_PSR_LEC_bf(const void *const hw) |
| 279 | { |
| 280 | return (((Can *)hw)->PSR.reg & CAN_PSR_LEC_Msk) >> CAN_PSR_LEC_Pos; |
| 281 | } |
| 282 | |
| 283 | static inline hri_can_psr_reg_t hri_can_get_PSR_ACT_bf(const void *const hw, hri_can_psr_reg_t mask) |
| 284 | { |
| 285 | return (((Can *)hw)->PSR.reg & CAN_PSR_ACT(mask)) >> CAN_PSR_ACT_Pos; |
| 286 | } |
| 287 | |
| 288 | static inline hri_can_psr_reg_t hri_can_read_PSR_ACT_bf(const void *const hw) |
| 289 | { |
| 290 | return (((Can *)hw)->PSR.reg & CAN_PSR_ACT_Msk) >> CAN_PSR_ACT_Pos; |
| 291 | } |
| 292 | |
| 293 | static inline hri_can_psr_reg_t hri_can_get_PSR_DLEC_bf(const void *const hw, hri_can_psr_reg_t mask) |
| 294 | { |
| 295 | return (((Can *)hw)->PSR.reg & CAN_PSR_DLEC(mask)) >> CAN_PSR_DLEC_Pos; |
| 296 | } |
| 297 | |
| 298 | static inline hri_can_psr_reg_t hri_can_read_PSR_DLEC_bf(const void *const hw) |
| 299 | { |
| 300 | return (((Can *)hw)->PSR.reg & CAN_PSR_DLEC_Msk) >> CAN_PSR_DLEC_Pos; |
| 301 | } |
| 302 | |
| 303 | static inline hri_can_psr_reg_t hri_can_get_PSR_TDCV_bf(const void *const hw, hri_can_psr_reg_t mask) |
| 304 | { |
| 305 | return (((Can *)hw)->PSR.reg & CAN_PSR_TDCV(mask)) >> CAN_PSR_TDCV_Pos; |
| 306 | } |
| 307 | |
| 308 | static inline hri_can_psr_reg_t hri_can_read_PSR_TDCV_bf(const void *const hw) |
| 309 | { |
| 310 | return (((Can *)hw)->PSR.reg & CAN_PSR_TDCV_Msk) >> CAN_PSR_TDCV_Pos; |
| 311 | } |
| 312 | |
| 313 | static inline hri_can_psr_reg_t hri_can_get_PSR_reg(const void *const hw, hri_can_psr_reg_t mask) |
| 314 | { |
| 315 | uint32_t tmp; |
| 316 | tmp = ((Can *)hw)->PSR.reg; |
| 317 | tmp &= mask; |
| 318 | return tmp; |
| 319 | } |
| 320 | |
| 321 | static inline hri_can_psr_reg_t hri_can_read_PSR_reg(const void *const hw) |
| 322 | { |
| 323 | return ((Can *)hw)->PSR.reg; |
| 324 | } |
| 325 | |
| 326 | static inline bool hri_can_get_HPMS_FLST_bit(const void *const hw) |
| 327 | { |
| 328 | return (((Can *)hw)->HPMS.reg & CAN_HPMS_FLST) >> CAN_HPMS_FLST_Pos; |
| 329 | } |
| 330 | |
| 331 | static inline hri_can_hpms_reg_t hri_can_get_HPMS_BIDX_bf(const void *const hw, hri_can_hpms_reg_t mask) |
| 332 | { |
| 333 | return (((Can *)hw)->HPMS.reg & CAN_HPMS_BIDX(mask)) >> CAN_HPMS_BIDX_Pos; |
| 334 | } |
| 335 | |
| 336 | static inline hri_can_hpms_reg_t hri_can_read_HPMS_BIDX_bf(const void *const hw) |
| 337 | { |
| 338 | return (((Can *)hw)->HPMS.reg & CAN_HPMS_BIDX_Msk) >> CAN_HPMS_BIDX_Pos; |
| 339 | } |
| 340 | |
| 341 | static inline hri_can_hpms_reg_t hri_can_get_HPMS_MSI_bf(const void *const hw, hri_can_hpms_reg_t mask) |
| 342 | { |
| 343 | return (((Can *)hw)->HPMS.reg & CAN_HPMS_MSI(mask)) >> CAN_HPMS_MSI_Pos; |
| 344 | } |
| 345 | |
| 346 | static inline hri_can_hpms_reg_t hri_can_read_HPMS_MSI_bf(const void *const hw) |
| 347 | { |
| 348 | return (((Can *)hw)->HPMS.reg & CAN_HPMS_MSI_Msk) >> CAN_HPMS_MSI_Pos; |
| 349 | } |
| 350 | |
| 351 | static inline hri_can_hpms_reg_t hri_can_get_HPMS_FIDX_bf(const void *const hw, hri_can_hpms_reg_t mask) |
| 352 | { |
| 353 | return (((Can *)hw)->HPMS.reg & CAN_HPMS_FIDX(mask)) >> CAN_HPMS_FIDX_Pos; |
| 354 | } |
| 355 | |
| 356 | static inline hri_can_hpms_reg_t hri_can_read_HPMS_FIDX_bf(const void *const hw) |
| 357 | { |
| 358 | return (((Can *)hw)->HPMS.reg & CAN_HPMS_FIDX_Msk) >> CAN_HPMS_FIDX_Pos; |
| 359 | } |
| 360 | |
| 361 | static inline hri_can_hpms_reg_t hri_can_get_HPMS_reg(const void *const hw, hri_can_hpms_reg_t mask) |
| 362 | { |
| 363 | uint32_t tmp; |
| 364 | tmp = ((Can *)hw)->HPMS.reg; |
| 365 | tmp &= mask; |
| 366 | return tmp; |
| 367 | } |
| 368 | |
| 369 | static inline hri_can_hpms_reg_t hri_can_read_HPMS_reg(const void *const hw) |
| 370 | { |
| 371 | return ((Can *)hw)->HPMS.reg; |
| 372 | } |
| 373 | |
| 374 | static inline bool hri_can_get_RXF0S_F0F_bit(const void *const hw) |
| 375 | { |
| 376 | return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0F) >> CAN_RXF0S_F0F_Pos; |
| 377 | } |
| 378 | |
| 379 | static inline bool hri_can_get_RXF0S_RF0L_bit(const void *const hw) |
| 380 | { |
| 381 | return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_RF0L) >> CAN_RXF0S_RF0L_Pos; |
| 382 | } |
| 383 | |
| 384 | static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0FL_bf(const void *const hw, hri_can_rxf0s_reg_t mask) |
| 385 | { |
| 386 | return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0FL(mask)) >> CAN_RXF0S_F0FL_Pos; |
| 387 | } |
| 388 | |
| 389 | static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0FL_bf(const void *const hw) |
| 390 | { |
| 391 | return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0FL_Msk) >> CAN_RXF0S_F0FL_Pos; |
| 392 | } |
| 393 | |
| 394 | static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0GI_bf(const void *const hw, hri_can_rxf0s_reg_t mask) |
| 395 | { |
| 396 | return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0GI(mask)) >> CAN_RXF0S_F0GI_Pos; |
| 397 | } |
| 398 | |
| 399 | static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0GI_bf(const void *const hw) |
| 400 | { |
| 401 | return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0GI_Msk) >> CAN_RXF0S_F0GI_Pos; |
| 402 | } |
| 403 | |
| 404 | static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0PI_bf(const void *const hw, hri_can_rxf0s_reg_t mask) |
| 405 | { |
| 406 | return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0PI(mask)) >> CAN_RXF0S_F0PI_Pos; |
| 407 | } |
| 408 | |
| 409 | static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0PI_bf(const void *const hw) |
| 410 | { |
| 411 | return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0PI_Msk) >> CAN_RXF0S_F0PI_Pos; |
| 412 | } |
| 413 | |
| 414 | static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_reg(const void *const hw, hri_can_rxf0s_reg_t mask) |
| 415 | { |
| 416 | uint32_t tmp; |
| 417 | tmp = ((Can *)hw)->RXF0S.reg; |
| 418 | tmp &= mask; |
| 419 | return tmp; |
| 420 | } |
| 421 | |
| 422 | static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_reg(const void *const hw) |
| 423 | { |
| 424 | return ((Can *)hw)->RXF0S.reg; |
| 425 | } |
| 426 | |
| 427 | static inline bool hri_can_get_RXF1S_F1F_bit(const void *const hw) |
| 428 | { |
| 429 | return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1F) >> CAN_RXF1S_F1F_Pos; |
| 430 | } |
| 431 | |
| 432 | static inline bool hri_can_get_RXF1S_RF1L_bit(const void *const hw) |
| 433 | { |
| 434 | return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_RF1L) >> CAN_RXF1S_RF1L_Pos; |
| 435 | } |
| 436 | |
| 437 | static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1FL_bf(const void *const hw, hri_can_rxf1s_reg_t mask) |
| 438 | { |
| 439 | return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1FL(mask)) >> CAN_RXF1S_F1FL_Pos; |
| 440 | } |
| 441 | |
| 442 | static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1FL_bf(const void *const hw) |
| 443 | { |
| 444 | return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1FL_Msk) >> CAN_RXF1S_F1FL_Pos; |
| 445 | } |
| 446 | |
| 447 | static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1GI_bf(const void *const hw, hri_can_rxf1s_reg_t mask) |
| 448 | { |
| 449 | return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1GI(mask)) >> CAN_RXF1S_F1GI_Pos; |
| 450 | } |
| 451 | |
| 452 | static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1GI_bf(const void *const hw) |
| 453 | { |
| 454 | return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1GI_Msk) >> CAN_RXF1S_F1GI_Pos; |
| 455 | } |
| 456 | |
| 457 | static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1PI_bf(const void *const hw, hri_can_rxf1s_reg_t mask) |
| 458 | { |
| 459 | return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1PI(mask)) >> CAN_RXF1S_F1PI_Pos; |
| 460 | } |
| 461 | |
| 462 | static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1PI_bf(const void *const hw) |
| 463 | { |
| 464 | return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1PI_Msk) >> CAN_RXF1S_F1PI_Pos; |
| 465 | } |
| 466 | |
| 467 | static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_DMS_bf(const void *const hw, hri_can_rxf1s_reg_t mask) |
| 468 | { |
| 469 | return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_DMS(mask)) >> CAN_RXF1S_DMS_Pos; |
| 470 | } |
| 471 | |
| 472 | static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_DMS_bf(const void *const hw) |
| 473 | { |
| 474 | return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_DMS_Msk) >> CAN_RXF1S_DMS_Pos; |
| 475 | } |
| 476 | |
| 477 | static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_reg(const void *const hw, hri_can_rxf1s_reg_t mask) |
| 478 | { |
| 479 | uint32_t tmp; |
| 480 | tmp = ((Can *)hw)->RXF1S.reg; |
| 481 | tmp &= mask; |
| 482 | return tmp; |
| 483 | } |
| 484 | |
| 485 | static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_reg(const void *const hw) |
| 486 | { |
| 487 | return ((Can *)hw)->RXF1S.reg; |
| 488 | } |
| 489 | |
| 490 | static inline bool hri_can_get_TXFQS_TFQF_bit(const void *const hw) |
| 491 | { |
| 492 | return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQF) >> CAN_TXFQS_TFQF_Pos; |
| 493 | } |
| 494 | |
| 495 | static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFFL_bf(const void *const hw, hri_can_txfqs_reg_t mask) |
| 496 | { |
| 497 | return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFFL(mask)) >> CAN_TXFQS_TFFL_Pos; |
| 498 | } |
| 499 | |
| 500 | static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFFL_bf(const void *const hw) |
| 501 | { |
| 502 | return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFFL_Msk) >> CAN_TXFQS_TFFL_Pos; |
| 503 | } |
| 504 | |
| 505 | static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFGI_bf(const void *const hw, hri_can_txfqs_reg_t mask) |
| 506 | { |
| 507 | return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFGI(mask)) >> CAN_TXFQS_TFGI_Pos; |
| 508 | } |
| 509 | |
| 510 | static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFGI_bf(const void *const hw) |
| 511 | { |
| 512 | return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFGI_Msk) >> CAN_TXFQS_TFGI_Pos; |
| 513 | } |
| 514 | |
| 515 | static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFQPI_bf(const void *const hw, hri_can_txfqs_reg_t mask) |
| 516 | { |
| 517 | return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQPI(mask)) >> CAN_TXFQS_TFQPI_Pos; |
| 518 | } |
| 519 | |
| 520 | static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFQPI_bf(const void *const hw) |
| 521 | { |
| 522 | return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQPI_Msk) >> CAN_TXFQS_TFQPI_Pos; |
| 523 | } |
| 524 | |
| 525 | static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_reg(const void *const hw, hri_can_txfqs_reg_t mask) |
| 526 | { |
| 527 | uint32_t tmp; |
| 528 | tmp = ((Can *)hw)->TXFQS.reg; |
| 529 | tmp &= mask; |
| 530 | return tmp; |
| 531 | } |
| 532 | |
| 533 | static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_reg(const void *const hw) |
| 534 | { |
| 535 | return ((Can *)hw)->TXFQS.reg; |
| 536 | } |
| 537 | |
| 538 | static inline bool hri_can_get_TXBRP_TRP0_bit(const void *const hw) |
| 539 | { |
| 540 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP0) >> CAN_TXBRP_TRP0_Pos; |
| 541 | } |
| 542 | |
| 543 | static inline bool hri_can_get_TXBRP_TRP1_bit(const void *const hw) |
| 544 | { |
| 545 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP1) >> CAN_TXBRP_TRP1_Pos; |
| 546 | } |
| 547 | |
| 548 | static inline bool hri_can_get_TXBRP_TRP2_bit(const void *const hw) |
| 549 | { |
| 550 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP2) >> CAN_TXBRP_TRP2_Pos; |
| 551 | } |
| 552 | |
| 553 | static inline bool hri_can_get_TXBRP_TRP3_bit(const void *const hw) |
| 554 | { |
| 555 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP3) >> CAN_TXBRP_TRP3_Pos; |
| 556 | } |
| 557 | |
| 558 | static inline bool hri_can_get_TXBRP_TRP4_bit(const void *const hw) |
| 559 | { |
| 560 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP4) >> CAN_TXBRP_TRP4_Pos; |
| 561 | } |
| 562 | |
| 563 | static inline bool hri_can_get_TXBRP_TRP5_bit(const void *const hw) |
| 564 | { |
| 565 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP5) >> CAN_TXBRP_TRP5_Pos; |
| 566 | } |
| 567 | |
| 568 | static inline bool hri_can_get_TXBRP_TRP6_bit(const void *const hw) |
| 569 | { |
| 570 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP6) >> CAN_TXBRP_TRP6_Pos; |
| 571 | } |
| 572 | |
| 573 | static inline bool hri_can_get_TXBRP_TRP7_bit(const void *const hw) |
| 574 | { |
| 575 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP7) >> CAN_TXBRP_TRP7_Pos; |
| 576 | } |
| 577 | |
| 578 | static inline bool hri_can_get_TXBRP_TRP8_bit(const void *const hw) |
| 579 | { |
| 580 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP8) >> CAN_TXBRP_TRP8_Pos; |
| 581 | } |
| 582 | |
| 583 | static inline bool hri_can_get_TXBRP_TRP9_bit(const void *const hw) |
| 584 | { |
| 585 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP9) >> CAN_TXBRP_TRP9_Pos; |
| 586 | } |
| 587 | |
| 588 | static inline bool hri_can_get_TXBRP_TRP10_bit(const void *const hw) |
| 589 | { |
| 590 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP10) >> CAN_TXBRP_TRP10_Pos; |
| 591 | } |
| 592 | |
| 593 | static inline bool hri_can_get_TXBRP_TRP11_bit(const void *const hw) |
| 594 | { |
| 595 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP11) >> CAN_TXBRP_TRP11_Pos; |
| 596 | } |
| 597 | |
| 598 | static inline bool hri_can_get_TXBRP_TRP12_bit(const void *const hw) |
| 599 | { |
| 600 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP12) >> CAN_TXBRP_TRP12_Pos; |
| 601 | } |
| 602 | |
| 603 | static inline bool hri_can_get_TXBRP_TRP13_bit(const void *const hw) |
| 604 | { |
| 605 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP13) >> CAN_TXBRP_TRP13_Pos; |
| 606 | } |
| 607 | |
| 608 | static inline bool hri_can_get_TXBRP_TRP14_bit(const void *const hw) |
| 609 | { |
| 610 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP14) >> CAN_TXBRP_TRP14_Pos; |
| 611 | } |
| 612 | |
| 613 | static inline bool hri_can_get_TXBRP_TRP15_bit(const void *const hw) |
| 614 | { |
| 615 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP15) >> CAN_TXBRP_TRP15_Pos; |
| 616 | } |
| 617 | |
| 618 | static inline bool hri_can_get_TXBRP_TRP16_bit(const void *const hw) |
| 619 | { |
| 620 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP16) >> CAN_TXBRP_TRP16_Pos; |
| 621 | } |
| 622 | |
| 623 | static inline bool hri_can_get_TXBRP_TRP17_bit(const void *const hw) |
| 624 | { |
| 625 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP17) >> CAN_TXBRP_TRP17_Pos; |
| 626 | } |
| 627 | |
| 628 | static inline bool hri_can_get_TXBRP_TRP18_bit(const void *const hw) |
| 629 | { |
| 630 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP18) >> CAN_TXBRP_TRP18_Pos; |
| 631 | } |
| 632 | |
| 633 | static inline bool hri_can_get_TXBRP_TRP19_bit(const void *const hw) |
| 634 | { |
| 635 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP19) >> CAN_TXBRP_TRP19_Pos; |
| 636 | } |
| 637 | |
| 638 | static inline bool hri_can_get_TXBRP_TRP20_bit(const void *const hw) |
| 639 | { |
| 640 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP20) >> CAN_TXBRP_TRP20_Pos; |
| 641 | } |
| 642 | |
| 643 | static inline bool hri_can_get_TXBRP_TRP21_bit(const void *const hw) |
| 644 | { |
| 645 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP21) >> CAN_TXBRP_TRP21_Pos; |
| 646 | } |
| 647 | |
| 648 | static inline bool hri_can_get_TXBRP_TRP22_bit(const void *const hw) |
| 649 | { |
| 650 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP22) >> CAN_TXBRP_TRP22_Pos; |
| 651 | } |
| 652 | |
| 653 | static inline bool hri_can_get_TXBRP_TRP23_bit(const void *const hw) |
| 654 | { |
| 655 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP23) >> CAN_TXBRP_TRP23_Pos; |
| 656 | } |
| 657 | |
| 658 | static inline bool hri_can_get_TXBRP_TRP24_bit(const void *const hw) |
| 659 | { |
| 660 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP24) >> CAN_TXBRP_TRP24_Pos; |
| 661 | } |
| 662 | |
| 663 | static inline bool hri_can_get_TXBRP_TRP25_bit(const void *const hw) |
| 664 | { |
| 665 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP25) >> CAN_TXBRP_TRP25_Pos; |
| 666 | } |
| 667 | |
| 668 | static inline bool hri_can_get_TXBRP_TRP26_bit(const void *const hw) |
| 669 | { |
| 670 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP26) >> CAN_TXBRP_TRP26_Pos; |
| 671 | } |
| 672 | |
| 673 | static inline bool hri_can_get_TXBRP_TRP27_bit(const void *const hw) |
| 674 | { |
| 675 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP27) >> CAN_TXBRP_TRP27_Pos; |
| 676 | } |
| 677 | |
| 678 | static inline bool hri_can_get_TXBRP_TRP28_bit(const void *const hw) |
| 679 | { |
| 680 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP28) >> CAN_TXBRP_TRP28_Pos; |
| 681 | } |
| 682 | |
| 683 | static inline bool hri_can_get_TXBRP_TRP29_bit(const void *const hw) |
| 684 | { |
| 685 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP29) >> CAN_TXBRP_TRP29_Pos; |
| 686 | } |
| 687 | |
| 688 | static inline bool hri_can_get_TXBRP_TRP30_bit(const void *const hw) |
| 689 | { |
| 690 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP30) >> CAN_TXBRP_TRP30_Pos; |
| 691 | } |
| 692 | |
| 693 | static inline bool hri_can_get_TXBRP_TRP31_bit(const void *const hw) |
| 694 | { |
| 695 | return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP31) >> CAN_TXBRP_TRP31_Pos; |
| 696 | } |
| 697 | |
| 698 | static inline hri_can_txbrp_reg_t hri_can_get_TXBRP_reg(const void *const hw, hri_can_txbrp_reg_t mask) |
| 699 | { |
| 700 | uint32_t tmp; |
| 701 | tmp = ((Can *)hw)->TXBRP.reg; |
| 702 | tmp &= mask; |
| 703 | return tmp; |
| 704 | } |
| 705 | |
| 706 | static inline hri_can_txbrp_reg_t hri_can_read_TXBRP_reg(const void *const hw) |
| 707 | { |
| 708 | return ((Can *)hw)->TXBRP.reg; |
| 709 | } |
| 710 | |
| 711 | static inline bool hri_can_get_TXBTO_TO0_bit(const void *const hw) |
| 712 | { |
| 713 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO0) >> CAN_TXBTO_TO0_Pos; |
| 714 | } |
| 715 | |
| 716 | static inline bool hri_can_get_TXBTO_TO1_bit(const void *const hw) |
| 717 | { |
| 718 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO1) >> CAN_TXBTO_TO1_Pos; |
| 719 | } |
| 720 | |
| 721 | static inline bool hri_can_get_TXBTO_TO2_bit(const void *const hw) |
| 722 | { |
| 723 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO2) >> CAN_TXBTO_TO2_Pos; |
| 724 | } |
| 725 | |
| 726 | static inline bool hri_can_get_TXBTO_TO3_bit(const void *const hw) |
| 727 | { |
| 728 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO3) >> CAN_TXBTO_TO3_Pos; |
| 729 | } |
| 730 | |
| 731 | static inline bool hri_can_get_TXBTO_TO4_bit(const void *const hw) |
| 732 | { |
| 733 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO4) >> CAN_TXBTO_TO4_Pos; |
| 734 | } |
| 735 | |
| 736 | static inline bool hri_can_get_TXBTO_TO5_bit(const void *const hw) |
| 737 | { |
| 738 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO5) >> CAN_TXBTO_TO5_Pos; |
| 739 | } |
| 740 | |
| 741 | static inline bool hri_can_get_TXBTO_TO6_bit(const void *const hw) |
| 742 | { |
| 743 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO6) >> CAN_TXBTO_TO6_Pos; |
| 744 | } |
| 745 | |
| 746 | static inline bool hri_can_get_TXBTO_TO7_bit(const void *const hw) |
| 747 | { |
| 748 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO7) >> CAN_TXBTO_TO7_Pos; |
| 749 | } |
| 750 | |
| 751 | static inline bool hri_can_get_TXBTO_TO8_bit(const void *const hw) |
| 752 | { |
| 753 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO8) >> CAN_TXBTO_TO8_Pos; |
| 754 | } |
| 755 | |
| 756 | static inline bool hri_can_get_TXBTO_TO9_bit(const void *const hw) |
| 757 | { |
| 758 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO9) >> CAN_TXBTO_TO9_Pos; |
| 759 | } |
| 760 | |
| 761 | static inline bool hri_can_get_TXBTO_TO10_bit(const void *const hw) |
| 762 | { |
| 763 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO10) >> CAN_TXBTO_TO10_Pos; |
| 764 | } |
| 765 | |
| 766 | static inline bool hri_can_get_TXBTO_TO11_bit(const void *const hw) |
| 767 | { |
| 768 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO11) >> CAN_TXBTO_TO11_Pos; |
| 769 | } |
| 770 | |
| 771 | static inline bool hri_can_get_TXBTO_TO12_bit(const void *const hw) |
| 772 | { |
| 773 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO12) >> CAN_TXBTO_TO12_Pos; |
| 774 | } |
| 775 | |
| 776 | static inline bool hri_can_get_TXBTO_TO13_bit(const void *const hw) |
| 777 | { |
| 778 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO13) >> CAN_TXBTO_TO13_Pos; |
| 779 | } |
| 780 | |
| 781 | static inline bool hri_can_get_TXBTO_TO14_bit(const void *const hw) |
| 782 | { |
| 783 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO14) >> CAN_TXBTO_TO14_Pos; |
| 784 | } |
| 785 | |
| 786 | static inline bool hri_can_get_TXBTO_TO15_bit(const void *const hw) |
| 787 | { |
| 788 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO15) >> CAN_TXBTO_TO15_Pos; |
| 789 | } |
| 790 | |
| 791 | static inline bool hri_can_get_TXBTO_TO16_bit(const void *const hw) |
| 792 | { |
| 793 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO16) >> CAN_TXBTO_TO16_Pos; |
| 794 | } |
| 795 | |
| 796 | static inline bool hri_can_get_TXBTO_TO17_bit(const void *const hw) |
| 797 | { |
| 798 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO17) >> CAN_TXBTO_TO17_Pos; |
| 799 | } |
| 800 | |
| 801 | static inline bool hri_can_get_TXBTO_TO18_bit(const void *const hw) |
| 802 | { |
| 803 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO18) >> CAN_TXBTO_TO18_Pos; |
| 804 | } |
| 805 | |
| 806 | static inline bool hri_can_get_TXBTO_TO19_bit(const void *const hw) |
| 807 | { |
| 808 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO19) >> CAN_TXBTO_TO19_Pos; |
| 809 | } |
| 810 | |
| 811 | static inline bool hri_can_get_TXBTO_TO20_bit(const void *const hw) |
| 812 | { |
| 813 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO20) >> CAN_TXBTO_TO20_Pos; |
| 814 | } |
| 815 | |
| 816 | static inline bool hri_can_get_TXBTO_TO21_bit(const void *const hw) |
| 817 | { |
| 818 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO21) >> CAN_TXBTO_TO21_Pos; |
| 819 | } |
| 820 | |
| 821 | static inline bool hri_can_get_TXBTO_TO22_bit(const void *const hw) |
| 822 | { |
| 823 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO22) >> CAN_TXBTO_TO22_Pos; |
| 824 | } |
| 825 | |
| 826 | static inline bool hri_can_get_TXBTO_TO23_bit(const void *const hw) |
| 827 | { |
| 828 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO23) >> CAN_TXBTO_TO23_Pos; |
| 829 | } |
| 830 | |
| 831 | static inline bool hri_can_get_TXBTO_TO24_bit(const void *const hw) |
| 832 | { |
| 833 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO24) >> CAN_TXBTO_TO24_Pos; |
| 834 | } |
| 835 | |
| 836 | static inline bool hri_can_get_TXBTO_TO25_bit(const void *const hw) |
| 837 | { |
| 838 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO25) >> CAN_TXBTO_TO25_Pos; |
| 839 | } |
| 840 | |
| 841 | static inline bool hri_can_get_TXBTO_TO26_bit(const void *const hw) |
| 842 | { |
| 843 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO26) >> CAN_TXBTO_TO26_Pos; |
| 844 | } |
| 845 | |
| 846 | static inline bool hri_can_get_TXBTO_TO27_bit(const void *const hw) |
| 847 | { |
| 848 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO27) >> CAN_TXBTO_TO27_Pos; |
| 849 | } |
| 850 | |
| 851 | static inline bool hri_can_get_TXBTO_TO28_bit(const void *const hw) |
| 852 | { |
| 853 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO28) >> CAN_TXBTO_TO28_Pos; |
| 854 | } |
| 855 | |
| 856 | static inline bool hri_can_get_TXBTO_TO29_bit(const void *const hw) |
| 857 | { |
| 858 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO29) >> CAN_TXBTO_TO29_Pos; |
| 859 | } |
| 860 | |
| 861 | static inline bool hri_can_get_TXBTO_TO30_bit(const void *const hw) |
| 862 | { |
| 863 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO30) >> CAN_TXBTO_TO30_Pos; |
| 864 | } |
| 865 | |
| 866 | static inline bool hri_can_get_TXBTO_TO31_bit(const void *const hw) |
| 867 | { |
| 868 | return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO31) >> CAN_TXBTO_TO31_Pos; |
| 869 | } |
| 870 | |
| 871 | static inline hri_can_txbto_reg_t hri_can_get_TXBTO_reg(const void *const hw, hri_can_txbto_reg_t mask) |
| 872 | { |
| 873 | uint32_t tmp; |
| 874 | tmp = ((Can *)hw)->TXBTO.reg; |
| 875 | tmp &= mask; |
| 876 | return tmp; |
| 877 | } |
| 878 | |
| 879 | static inline hri_can_txbto_reg_t hri_can_read_TXBTO_reg(const void *const hw) |
| 880 | { |
| 881 | return ((Can *)hw)->TXBTO.reg; |
| 882 | } |
| 883 | |
| 884 | static inline bool hri_can_get_TXBCF_CF0_bit(const void *const hw) |
| 885 | { |
| 886 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF0) >> CAN_TXBCF_CF0_Pos; |
| 887 | } |
| 888 | |
| 889 | static inline bool hri_can_get_TXBCF_CF1_bit(const void *const hw) |
| 890 | { |
| 891 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF1) >> CAN_TXBCF_CF1_Pos; |
| 892 | } |
| 893 | |
| 894 | static inline bool hri_can_get_TXBCF_CF2_bit(const void *const hw) |
| 895 | { |
| 896 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF2) >> CAN_TXBCF_CF2_Pos; |
| 897 | } |
| 898 | |
| 899 | static inline bool hri_can_get_TXBCF_CF3_bit(const void *const hw) |
| 900 | { |
| 901 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF3) >> CAN_TXBCF_CF3_Pos; |
| 902 | } |
| 903 | |
| 904 | static inline bool hri_can_get_TXBCF_CF4_bit(const void *const hw) |
| 905 | { |
| 906 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF4) >> CAN_TXBCF_CF4_Pos; |
| 907 | } |
| 908 | |
| 909 | static inline bool hri_can_get_TXBCF_CF5_bit(const void *const hw) |
| 910 | { |
| 911 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF5) >> CAN_TXBCF_CF5_Pos; |
| 912 | } |
| 913 | |
| 914 | static inline bool hri_can_get_TXBCF_CF6_bit(const void *const hw) |
| 915 | { |
| 916 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF6) >> CAN_TXBCF_CF6_Pos; |
| 917 | } |
| 918 | |
| 919 | static inline bool hri_can_get_TXBCF_CF7_bit(const void *const hw) |
| 920 | { |
| 921 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF7) >> CAN_TXBCF_CF7_Pos; |
| 922 | } |
| 923 | |
| 924 | static inline bool hri_can_get_TXBCF_CF8_bit(const void *const hw) |
| 925 | { |
| 926 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF8) >> CAN_TXBCF_CF8_Pos; |
| 927 | } |
| 928 | |
| 929 | static inline bool hri_can_get_TXBCF_CF9_bit(const void *const hw) |
| 930 | { |
| 931 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF9) >> CAN_TXBCF_CF9_Pos; |
| 932 | } |
| 933 | |
| 934 | static inline bool hri_can_get_TXBCF_CF10_bit(const void *const hw) |
| 935 | { |
| 936 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF10) >> CAN_TXBCF_CF10_Pos; |
| 937 | } |
| 938 | |
| 939 | static inline bool hri_can_get_TXBCF_CF11_bit(const void *const hw) |
| 940 | { |
| 941 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF11) >> CAN_TXBCF_CF11_Pos; |
| 942 | } |
| 943 | |
| 944 | static inline bool hri_can_get_TXBCF_CF12_bit(const void *const hw) |
| 945 | { |
| 946 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF12) >> CAN_TXBCF_CF12_Pos; |
| 947 | } |
| 948 | |
| 949 | static inline bool hri_can_get_TXBCF_CF13_bit(const void *const hw) |
| 950 | { |
| 951 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF13) >> CAN_TXBCF_CF13_Pos; |
| 952 | } |
| 953 | |
| 954 | static inline bool hri_can_get_TXBCF_CF14_bit(const void *const hw) |
| 955 | { |
| 956 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF14) >> CAN_TXBCF_CF14_Pos; |
| 957 | } |
| 958 | |
| 959 | static inline bool hri_can_get_TXBCF_CF15_bit(const void *const hw) |
| 960 | { |
| 961 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF15) >> CAN_TXBCF_CF15_Pos; |
| 962 | } |
| 963 | |
| 964 | static inline bool hri_can_get_TXBCF_CF16_bit(const void *const hw) |
| 965 | { |
| 966 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF16) >> CAN_TXBCF_CF16_Pos; |
| 967 | } |
| 968 | |
| 969 | static inline bool hri_can_get_TXBCF_CF17_bit(const void *const hw) |
| 970 | { |
| 971 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF17) >> CAN_TXBCF_CF17_Pos; |
| 972 | } |
| 973 | |
| 974 | static inline bool hri_can_get_TXBCF_CF18_bit(const void *const hw) |
| 975 | { |
| 976 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF18) >> CAN_TXBCF_CF18_Pos; |
| 977 | } |
| 978 | |
| 979 | static inline bool hri_can_get_TXBCF_CF19_bit(const void *const hw) |
| 980 | { |
| 981 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF19) >> CAN_TXBCF_CF19_Pos; |
| 982 | } |
| 983 | |
| 984 | static inline bool hri_can_get_TXBCF_CF20_bit(const void *const hw) |
| 985 | { |
| 986 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF20) >> CAN_TXBCF_CF20_Pos; |
| 987 | } |
| 988 | |
| 989 | static inline bool hri_can_get_TXBCF_CF21_bit(const void *const hw) |
| 990 | { |
| 991 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF21) >> CAN_TXBCF_CF21_Pos; |
| 992 | } |
| 993 | |
| 994 | static inline bool hri_can_get_TXBCF_CF22_bit(const void *const hw) |
| 995 | { |
| 996 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF22) >> CAN_TXBCF_CF22_Pos; |
| 997 | } |
| 998 | |
| 999 | static inline bool hri_can_get_TXBCF_CF23_bit(const void *const hw) |
| 1000 | { |
| 1001 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF23) >> CAN_TXBCF_CF23_Pos; |
| 1002 | } |
| 1003 | |
| 1004 | static inline bool hri_can_get_TXBCF_CF24_bit(const void *const hw) |
| 1005 | { |
| 1006 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF24) >> CAN_TXBCF_CF24_Pos; |
| 1007 | } |
| 1008 | |
| 1009 | static inline bool hri_can_get_TXBCF_CF25_bit(const void *const hw) |
| 1010 | { |
| 1011 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF25) >> CAN_TXBCF_CF25_Pos; |
| 1012 | } |
| 1013 | |
| 1014 | static inline bool hri_can_get_TXBCF_CF26_bit(const void *const hw) |
| 1015 | { |
| 1016 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF26) >> CAN_TXBCF_CF26_Pos; |
| 1017 | } |
| 1018 | |
| 1019 | static inline bool hri_can_get_TXBCF_CF27_bit(const void *const hw) |
| 1020 | { |
| 1021 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF27) >> CAN_TXBCF_CF27_Pos; |
| 1022 | } |
| 1023 | |
| 1024 | static inline bool hri_can_get_TXBCF_CF28_bit(const void *const hw) |
| 1025 | { |
| 1026 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF28) >> CAN_TXBCF_CF28_Pos; |
| 1027 | } |
| 1028 | |
| 1029 | static inline bool hri_can_get_TXBCF_CF29_bit(const void *const hw) |
| 1030 | { |
| 1031 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF29) >> CAN_TXBCF_CF29_Pos; |
| 1032 | } |
| 1033 | |
| 1034 | static inline bool hri_can_get_TXBCF_CF30_bit(const void *const hw) |
| 1035 | { |
| 1036 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF30) >> CAN_TXBCF_CF30_Pos; |
| 1037 | } |
| 1038 | |
| 1039 | static inline bool hri_can_get_TXBCF_CF31_bit(const void *const hw) |
| 1040 | { |
| 1041 | return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF31) >> CAN_TXBCF_CF31_Pos; |
| 1042 | } |
| 1043 | |
| 1044 | static inline hri_can_txbcf_reg_t hri_can_get_TXBCF_reg(const void *const hw, hri_can_txbcf_reg_t mask) |
| 1045 | { |
| 1046 | uint32_t tmp; |
| 1047 | tmp = ((Can *)hw)->TXBCF.reg; |
| 1048 | tmp &= mask; |
| 1049 | return tmp; |
| 1050 | } |
| 1051 | |
| 1052 | static inline hri_can_txbcf_reg_t hri_can_read_TXBCF_reg(const void *const hw) |
| 1053 | { |
| 1054 | return ((Can *)hw)->TXBCF.reg; |
| 1055 | } |
| 1056 | |
| 1057 | static inline bool hri_can_get_TXEFS_EFF_bit(const void *const hw) |
| 1058 | { |
| 1059 | return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFF) >> CAN_TXEFS_EFF_Pos; |
| 1060 | } |
| 1061 | |
| 1062 | static inline bool hri_can_get_TXEFS_TEFL_bit(const void *const hw) |
| 1063 | { |
| 1064 | return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_TEFL) >> CAN_TXEFS_TEFL_Pos; |
| 1065 | } |
| 1066 | |
| 1067 | static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFFL_bf(const void *const hw, hri_can_txefs_reg_t mask) |
| 1068 | { |
| 1069 | return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFFL(mask)) >> CAN_TXEFS_EFFL_Pos; |
| 1070 | } |
| 1071 | |
| 1072 | static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFFL_bf(const void *const hw) |
| 1073 | { |
| 1074 | return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFFL_Msk) >> CAN_TXEFS_EFFL_Pos; |
| 1075 | } |
| 1076 | |
| 1077 | static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFGI_bf(const void *const hw, hri_can_txefs_reg_t mask) |
| 1078 | { |
| 1079 | return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFGI(mask)) >> CAN_TXEFS_EFGI_Pos; |
| 1080 | } |
| 1081 | |
| 1082 | static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFGI_bf(const void *const hw) |
| 1083 | { |
| 1084 | return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFGI_Msk) >> CAN_TXEFS_EFGI_Pos; |
| 1085 | } |
| 1086 | |
| 1087 | static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFPI_bf(const void *const hw, hri_can_txefs_reg_t mask) |
| 1088 | { |
| 1089 | return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFPI(mask)) >> CAN_TXEFS_EFPI_Pos; |
| 1090 | } |
| 1091 | |
| 1092 | static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFPI_bf(const void *const hw) |
| 1093 | { |
| 1094 | return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFPI_Msk) >> CAN_TXEFS_EFPI_Pos; |
| 1095 | } |
| 1096 | |
| 1097 | static inline hri_can_txefs_reg_t hri_can_get_TXEFS_reg(const void *const hw, hri_can_txefs_reg_t mask) |
| 1098 | { |
| 1099 | uint32_t tmp; |
| 1100 | tmp = ((Can *)hw)->TXEFS.reg; |
| 1101 | tmp &= mask; |
| 1102 | return tmp; |
| 1103 | } |
| 1104 | |
| 1105 | static inline hri_can_txefs_reg_t hri_can_read_TXEFS_reg(const void *const hw) |
| 1106 | { |
| 1107 | return ((Can *)hw)->TXEFS.reg; |
| 1108 | } |
| 1109 | |
| 1110 | static inline void hri_can_set_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) |
| 1111 | { |
| 1112 | CAN_CRITICAL_SECTION_ENTER(); |
| 1113 | ((Can *)hw)->MRCFG.reg |= CAN_MRCFG_QOS(mask); |
| 1114 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1115 | } |
| 1116 | |
| 1117 | static inline hri_can_mrcfg_reg_t hri_can_get_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) |
| 1118 | { |
| 1119 | uint32_t tmp; |
| 1120 | tmp = ((Can *)hw)->MRCFG.reg; |
| 1121 | tmp = (tmp & CAN_MRCFG_QOS(mask)) >> CAN_MRCFG_QOS_Pos; |
| 1122 | return tmp; |
| 1123 | } |
| 1124 | |
| 1125 | static inline void hri_can_write_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t data) |
| 1126 | { |
| 1127 | uint32_t tmp; |
| 1128 | CAN_CRITICAL_SECTION_ENTER(); |
| 1129 | tmp = ((Can *)hw)->MRCFG.reg; |
| 1130 | tmp &= ~CAN_MRCFG_QOS_Msk; |
| 1131 | tmp |= CAN_MRCFG_QOS(data); |
| 1132 | ((Can *)hw)->MRCFG.reg = tmp; |
| 1133 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1134 | } |
| 1135 | |
| 1136 | static inline void hri_can_clear_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) |
| 1137 | { |
| 1138 | CAN_CRITICAL_SECTION_ENTER(); |
| 1139 | ((Can *)hw)->MRCFG.reg &= ~CAN_MRCFG_QOS(mask); |
| 1140 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1141 | } |
| 1142 | |
| 1143 | static inline void hri_can_toggle_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) |
| 1144 | { |
| 1145 | CAN_CRITICAL_SECTION_ENTER(); |
| 1146 | ((Can *)hw)->MRCFG.reg ^= CAN_MRCFG_QOS(mask); |
| 1147 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1148 | } |
| 1149 | |
| 1150 | static inline hri_can_mrcfg_reg_t hri_can_read_MRCFG_QOS_bf(const void *const hw) |
| 1151 | { |
| 1152 | uint32_t tmp; |
| 1153 | tmp = ((Can *)hw)->MRCFG.reg; |
| 1154 | tmp = (tmp & CAN_MRCFG_QOS_Msk) >> CAN_MRCFG_QOS_Pos; |
| 1155 | return tmp; |
| 1156 | } |
| 1157 | |
| 1158 | static inline void hri_can_set_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) |
| 1159 | { |
| 1160 | CAN_CRITICAL_SECTION_ENTER(); |
| 1161 | ((Can *)hw)->MRCFG.reg |= mask; |
| 1162 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1163 | } |
| 1164 | |
| 1165 | static inline hri_can_mrcfg_reg_t hri_can_get_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) |
| 1166 | { |
| 1167 | uint32_t tmp; |
| 1168 | tmp = ((Can *)hw)->MRCFG.reg; |
| 1169 | tmp &= mask; |
| 1170 | return tmp; |
| 1171 | } |
| 1172 | |
| 1173 | static inline void hri_can_write_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t data) |
| 1174 | { |
| 1175 | CAN_CRITICAL_SECTION_ENTER(); |
| 1176 | ((Can *)hw)->MRCFG.reg = data; |
| 1177 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1178 | } |
| 1179 | |
| 1180 | static inline void hri_can_clear_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) |
| 1181 | { |
| 1182 | CAN_CRITICAL_SECTION_ENTER(); |
| 1183 | ((Can *)hw)->MRCFG.reg &= ~mask; |
| 1184 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1185 | } |
| 1186 | |
| 1187 | static inline void hri_can_toggle_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) |
| 1188 | { |
| 1189 | CAN_CRITICAL_SECTION_ENTER(); |
| 1190 | ((Can *)hw)->MRCFG.reg ^= mask; |
| 1191 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1192 | } |
| 1193 | |
| 1194 | static inline hri_can_mrcfg_reg_t hri_can_read_MRCFG_reg(const void *const hw) |
| 1195 | { |
| 1196 | return ((Can *)hw)->MRCFG.reg; |
| 1197 | } |
| 1198 | |
| 1199 | static inline void hri_can_set_DBTP_TDC_bit(const void *const hw) |
| 1200 | { |
| 1201 | CAN_CRITICAL_SECTION_ENTER(); |
| 1202 | ((Can *)hw)->DBTP.reg |= CAN_DBTP_TDC; |
| 1203 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1204 | } |
| 1205 | |
| 1206 | static inline bool hri_can_get_DBTP_TDC_bit(const void *const hw) |
| 1207 | { |
| 1208 | uint32_t tmp; |
| 1209 | tmp = ((Can *)hw)->DBTP.reg; |
| 1210 | tmp = (tmp & CAN_DBTP_TDC) >> CAN_DBTP_TDC_Pos; |
| 1211 | return (bool)tmp; |
| 1212 | } |
| 1213 | |
| 1214 | static inline void hri_can_write_DBTP_TDC_bit(const void *const hw, bool value) |
| 1215 | { |
| 1216 | uint32_t tmp; |
| 1217 | CAN_CRITICAL_SECTION_ENTER(); |
| 1218 | tmp = ((Can *)hw)->DBTP.reg; |
| 1219 | tmp &= ~CAN_DBTP_TDC; |
| 1220 | tmp |= value << CAN_DBTP_TDC_Pos; |
| 1221 | ((Can *)hw)->DBTP.reg = tmp; |
| 1222 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1223 | } |
| 1224 | |
| 1225 | static inline void hri_can_clear_DBTP_TDC_bit(const void *const hw) |
| 1226 | { |
| 1227 | CAN_CRITICAL_SECTION_ENTER(); |
| 1228 | ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_TDC; |
| 1229 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1230 | } |
| 1231 | |
| 1232 | static inline void hri_can_toggle_DBTP_TDC_bit(const void *const hw) |
| 1233 | { |
| 1234 | CAN_CRITICAL_SECTION_ENTER(); |
| 1235 | ((Can *)hw)->DBTP.reg ^= CAN_DBTP_TDC; |
| 1236 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1237 | } |
| 1238 | |
| 1239 | static inline void hri_can_set_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) |
| 1240 | { |
| 1241 | CAN_CRITICAL_SECTION_ENTER(); |
| 1242 | ((Can *)hw)->DBTP.reg |= CAN_DBTP_DSJW(mask); |
| 1243 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1244 | } |
| 1245 | |
| 1246 | static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) |
| 1247 | { |
| 1248 | uint32_t tmp; |
| 1249 | tmp = ((Can *)hw)->DBTP.reg; |
| 1250 | tmp = (tmp & CAN_DBTP_DSJW(mask)) >> CAN_DBTP_DSJW_Pos; |
| 1251 | return tmp; |
| 1252 | } |
| 1253 | |
| 1254 | static inline void hri_can_write_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t data) |
| 1255 | { |
| 1256 | uint32_t tmp; |
| 1257 | CAN_CRITICAL_SECTION_ENTER(); |
| 1258 | tmp = ((Can *)hw)->DBTP.reg; |
| 1259 | tmp &= ~CAN_DBTP_DSJW_Msk; |
| 1260 | tmp |= CAN_DBTP_DSJW(data); |
| 1261 | ((Can *)hw)->DBTP.reg = tmp; |
| 1262 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1263 | } |
| 1264 | |
| 1265 | static inline void hri_can_clear_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) |
| 1266 | { |
| 1267 | CAN_CRITICAL_SECTION_ENTER(); |
| 1268 | ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DSJW(mask); |
| 1269 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1270 | } |
| 1271 | |
| 1272 | static inline void hri_can_toggle_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) |
| 1273 | { |
| 1274 | CAN_CRITICAL_SECTION_ENTER(); |
| 1275 | ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DSJW(mask); |
| 1276 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1277 | } |
| 1278 | |
| 1279 | static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DSJW_bf(const void *const hw) |
| 1280 | { |
| 1281 | uint32_t tmp; |
| 1282 | tmp = ((Can *)hw)->DBTP.reg; |
| 1283 | tmp = (tmp & CAN_DBTP_DSJW_Msk) >> CAN_DBTP_DSJW_Pos; |
| 1284 | return tmp; |
| 1285 | } |
| 1286 | |
| 1287 | static inline void hri_can_set_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) |
| 1288 | { |
| 1289 | CAN_CRITICAL_SECTION_ENTER(); |
| 1290 | ((Can *)hw)->DBTP.reg |= CAN_DBTP_DTSEG2(mask); |
| 1291 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1292 | } |
| 1293 | |
| 1294 | static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) |
| 1295 | { |
| 1296 | uint32_t tmp; |
| 1297 | tmp = ((Can *)hw)->DBTP.reg; |
| 1298 | tmp = (tmp & CAN_DBTP_DTSEG2(mask)) >> CAN_DBTP_DTSEG2_Pos; |
| 1299 | return tmp; |
| 1300 | } |
| 1301 | |
| 1302 | static inline void hri_can_write_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t data) |
| 1303 | { |
| 1304 | uint32_t tmp; |
| 1305 | CAN_CRITICAL_SECTION_ENTER(); |
| 1306 | tmp = ((Can *)hw)->DBTP.reg; |
| 1307 | tmp &= ~CAN_DBTP_DTSEG2_Msk; |
| 1308 | tmp |= CAN_DBTP_DTSEG2(data); |
| 1309 | ((Can *)hw)->DBTP.reg = tmp; |
| 1310 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1311 | } |
| 1312 | |
| 1313 | static inline void hri_can_clear_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) |
| 1314 | { |
| 1315 | CAN_CRITICAL_SECTION_ENTER(); |
| 1316 | ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DTSEG2(mask); |
| 1317 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1318 | } |
| 1319 | |
| 1320 | static inline void hri_can_toggle_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) |
| 1321 | { |
| 1322 | CAN_CRITICAL_SECTION_ENTER(); |
| 1323 | ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DTSEG2(mask); |
| 1324 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1325 | } |
| 1326 | |
| 1327 | static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DTSEG2_bf(const void *const hw) |
| 1328 | { |
| 1329 | uint32_t tmp; |
| 1330 | tmp = ((Can *)hw)->DBTP.reg; |
| 1331 | tmp = (tmp & CAN_DBTP_DTSEG2_Msk) >> CAN_DBTP_DTSEG2_Pos; |
| 1332 | return tmp; |
| 1333 | } |
| 1334 | |
| 1335 | static inline void hri_can_set_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) |
| 1336 | { |
| 1337 | CAN_CRITICAL_SECTION_ENTER(); |
| 1338 | ((Can *)hw)->DBTP.reg |= CAN_DBTP_DTSEG1(mask); |
| 1339 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1340 | } |
| 1341 | |
| 1342 | static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) |
| 1343 | { |
| 1344 | uint32_t tmp; |
| 1345 | tmp = ((Can *)hw)->DBTP.reg; |
| 1346 | tmp = (tmp & CAN_DBTP_DTSEG1(mask)) >> CAN_DBTP_DTSEG1_Pos; |
| 1347 | return tmp; |
| 1348 | } |
| 1349 | |
| 1350 | static inline void hri_can_write_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t data) |
| 1351 | { |
| 1352 | uint32_t tmp; |
| 1353 | CAN_CRITICAL_SECTION_ENTER(); |
| 1354 | tmp = ((Can *)hw)->DBTP.reg; |
| 1355 | tmp &= ~CAN_DBTP_DTSEG1_Msk; |
| 1356 | tmp |= CAN_DBTP_DTSEG1(data); |
| 1357 | ((Can *)hw)->DBTP.reg = tmp; |
| 1358 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1359 | } |
| 1360 | |
| 1361 | static inline void hri_can_clear_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) |
| 1362 | { |
| 1363 | CAN_CRITICAL_SECTION_ENTER(); |
| 1364 | ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DTSEG1(mask); |
| 1365 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1366 | } |
| 1367 | |
| 1368 | static inline void hri_can_toggle_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) |
| 1369 | { |
| 1370 | CAN_CRITICAL_SECTION_ENTER(); |
| 1371 | ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DTSEG1(mask); |
| 1372 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1373 | } |
| 1374 | |
| 1375 | static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DTSEG1_bf(const void *const hw) |
| 1376 | { |
| 1377 | uint32_t tmp; |
| 1378 | tmp = ((Can *)hw)->DBTP.reg; |
| 1379 | tmp = (tmp & CAN_DBTP_DTSEG1_Msk) >> CAN_DBTP_DTSEG1_Pos; |
| 1380 | return tmp; |
| 1381 | } |
| 1382 | |
| 1383 | static inline void hri_can_set_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) |
| 1384 | { |
| 1385 | CAN_CRITICAL_SECTION_ENTER(); |
| 1386 | ((Can *)hw)->DBTP.reg |= CAN_DBTP_DBRP(mask); |
| 1387 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1388 | } |
| 1389 | |
| 1390 | static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) |
| 1391 | { |
| 1392 | uint32_t tmp; |
| 1393 | tmp = ((Can *)hw)->DBTP.reg; |
| 1394 | tmp = (tmp & CAN_DBTP_DBRP(mask)) >> CAN_DBTP_DBRP_Pos; |
| 1395 | return tmp; |
| 1396 | } |
| 1397 | |
| 1398 | static inline void hri_can_write_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t data) |
| 1399 | { |
| 1400 | uint32_t tmp; |
| 1401 | CAN_CRITICAL_SECTION_ENTER(); |
| 1402 | tmp = ((Can *)hw)->DBTP.reg; |
| 1403 | tmp &= ~CAN_DBTP_DBRP_Msk; |
| 1404 | tmp |= CAN_DBTP_DBRP(data); |
| 1405 | ((Can *)hw)->DBTP.reg = tmp; |
| 1406 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1407 | } |
| 1408 | |
| 1409 | static inline void hri_can_clear_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) |
| 1410 | { |
| 1411 | CAN_CRITICAL_SECTION_ENTER(); |
| 1412 | ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DBRP(mask); |
| 1413 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1414 | } |
| 1415 | |
| 1416 | static inline void hri_can_toggle_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) |
| 1417 | { |
| 1418 | CAN_CRITICAL_SECTION_ENTER(); |
| 1419 | ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DBRP(mask); |
| 1420 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1421 | } |
| 1422 | |
| 1423 | static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DBRP_bf(const void *const hw) |
| 1424 | { |
| 1425 | uint32_t tmp; |
| 1426 | tmp = ((Can *)hw)->DBTP.reg; |
| 1427 | tmp = (tmp & CAN_DBTP_DBRP_Msk) >> CAN_DBTP_DBRP_Pos; |
| 1428 | return tmp; |
| 1429 | } |
| 1430 | |
| 1431 | static inline void hri_can_set_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) |
| 1432 | { |
| 1433 | CAN_CRITICAL_SECTION_ENTER(); |
| 1434 | ((Can *)hw)->DBTP.reg |= mask; |
| 1435 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1436 | } |
| 1437 | |
| 1438 | static inline hri_can_dbtp_reg_t hri_can_get_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) |
| 1439 | { |
| 1440 | uint32_t tmp; |
| 1441 | tmp = ((Can *)hw)->DBTP.reg; |
| 1442 | tmp &= mask; |
| 1443 | return tmp; |
| 1444 | } |
| 1445 | |
| 1446 | static inline void hri_can_write_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t data) |
| 1447 | { |
| 1448 | CAN_CRITICAL_SECTION_ENTER(); |
| 1449 | ((Can *)hw)->DBTP.reg = data; |
| 1450 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1451 | } |
| 1452 | |
| 1453 | static inline void hri_can_clear_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) |
| 1454 | { |
| 1455 | CAN_CRITICAL_SECTION_ENTER(); |
| 1456 | ((Can *)hw)->DBTP.reg &= ~mask; |
| 1457 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1458 | } |
| 1459 | |
| 1460 | static inline void hri_can_toggle_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) |
| 1461 | { |
| 1462 | CAN_CRITICAL_SECTION_ENTER(); |
| 1463 | ((Can *)hw)->DBTP.reg ^= mask; |
| 1464 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1465 | } |
| 1466 | |
| 1467 | static inline hri_can_dbtp_reg_t hri_can_read_DBTP_reg(const void *const hw) |
| 1468 | { |
| 1469 | return ((Can *)hw)->DBTP.reg; |
| 1470 | } |
| 1471 | |
| 1472 | static inline void hri_can_set_TEST_LBCK_bit(const void *const hw) |
| 1473 | { |
| 1474 | CAN_CRITICAL_SECTION_ENTER(); |
| 1475 | ((Can *)hw)->TEST.reg |= CAN_TEST_LBCK; |
| 1476 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1477 | } |
| 1478 | |
| 1479 | static inline bool hri_can_get_TEST_LBCK_bit(const void *const hw) |
| 1480 | { |
| 1481 | uint32_t tmp; |
| 1482 | tmp = ((Can *)hw)->TEST.reg; |
| 1483 | tmp = (tmp & CAN_TEST_LBCK) >> CAN_TEST_LBCK_Pos; |
| 1484 | return (bool)tmp; |
| 1485 | } |
| 1486 | |
| 1487 | static inline void hri_can_write_TEST_LBCK_bit(const void *const hw, bool value) |
| 1488 | { |
| 1489 | uint32_t tmp; |
| 1490 | CAN_CRITICAL_SECTION_ENTER(); |
| 1491 | tmp = ((Can *)hw)->TEST.reg; |
| 1492 | tmp &= ~CAN_TEST_LBCK; |
| 1493 | tmp |= value << CAN_TEST_LBCK_Pos; |
| 1494 | ((Can *)hw)->TEST.reg = tmp; |
| 1495 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1496 | } |
| 1497 | |
| 1498 | static inline void hri_can_clear_TEST_LBCK_bit(const void *const hw) |
| 1499 | { |
| 1500 | CAN_CRITICAL_SECTION_ENTER(); |
| 1501 | ((Can *)hw)->TEST.reg &= ~CAN_TEST_LBCK; |
| 1502 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1503 | } |
| 1504 | |
| 1505 | static inline void hri_can_toggle_TEST_LBCK_bit(const void *const hw) |
| 1506 | { |
| 1507 | CAN_CRITICAL_SECTION_ENTER(); |
| 1508 | ((Can *)hw)->TEST.reg ^= CAN_TEST_LBCK; |
| 1509 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1510 | } |
| 1511 | |
| 1512 | static inline void hri_can_set_TEST_RX_bit(const void *const hw) |
| 1513 | { |
| 1514 | CAN_CRITICAL_SECTION_ENTER(); |
| 1515 | ((Can *)hw)->TEST.reg |= CAN_TEST_RX; |
| 1516 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1517 | } |
| 1518 | |
| 1519 | static inline bool hri_can_get_TEST_RX_bit(const void *const hw) |
| 1520 | { |
| 1521 | uint32_t tmp; |
| 1522 | tmp = ((Can *)hw)->TEST.reg; |
| 1523 | tmp = (tmp & CAN_TEST_RX) >> CAN_TEST_RX_Pos; |
| 1524 | return (bool)tmp; |
| 1525 | } |
| 1526 | |
| 1527 | static inline void hri_can_write_TEST_RX_bit(const void *const hw, bool value) |
| 1528 | { |
| 1529 | uint32_t tmp; |
| 1530 | CAN_CRITICAL_SECTION_ENTER(); |
| 1531 | tmp = ((Can *)hw)->TEST.reg; |
| 1532 | tmp &= ~CAN_TEST_RX; |
| 1533 | tmp |= value << CAN_TEST_RX_Pos; |
| 1534 | ((Can *)hw)->TEST.reg = tmp; |
| 1535 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1536 | } |
| 1537 | |
| 1538 | static inline void hri_can_clear_TEST_RX_bit(const void *const hw) |
| 1539 | { |
| 1540 | CAN_CRITICAL_SECTION_ENTER(); |
| 1541 | ((Can *)hw)->TEST.reg &= ~CAN_TEST_RX; |
| 1542 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1543 | } |
| 1544 | |
| 1545 | static inline void hri_can_toggle_TEST_RX_bit(const void *const hw) |
| 1546 | { |
| 1547 | CAN_CRITICAL_SECTION_ENTER(); |
| 1548 | ((Can *)hw)->TEST.reg ^= CAN_TEST_RX; |
| 1549 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1550 | } |
| 1551 | |
| 1552 | static inline void hri_can_set_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) |
| 1553 | { |
| 1554 | CAN_CRITICAL_SECTION_ENTER(); |
| 1555 | ((Can *)hw)->TEST.reg |= CAN_TEST_TX(mask); |
| 1556 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1557 | } |
| 1558 | |
| 1559 | static inline hri_can_test_reg_t hri_can_get_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) |
| 1560 | { |
| 1561 | uint32_t tmp; |
| 1562 | tmp = ((Can *)hw)->TEST.reg; |
| 1563 | tmp = (tmp & CAN_TEST_TX(mask)) >> CAN_TEST_TX_Pos; |
| 1564 | return tmp; |
| 1565 | } |
| 1566 | |
| 1567 | static inline void hri_can_write_TEST_TX_bf(const void *const hw, hri_can_test_reg_t data) |
| 1568 | { |
| 1569 | uint32_t tmp; |
| 1570 | CAN_CRITICAL_SECTION_ENTER(); |
| 1571 | tmp = ((Can *)hw)->TEST.reg; |
| 1572 | tmp &= ~CAN_TEST_TX_Msk; |
| 1573 | tmp |= CAN_TEST_TX(data); |
| 1574 | ((Can *)hw)->TEST.reg = tmp; |
| 1575 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1576 | } |
| 1577 | |
| 1578 | static inline void hri_can_clear_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) |
| 1579 | { |
| 1580 | CAN_CRITICAL_SECTION_ENTER(); |
| 1581 | ((Can *)hw)->TEST.reg &= ~CAN_TEST_TX(mask); |
| 1582 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1583 | } |
| 1584 | |
| 1585 | static inline void hri_can_toggle_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) |
| 1586 | { |
| 1587 | CAN_CRITICAL_SECTION_ENTER(); |
| 1588 | ((Can *)hw)->TEST.reg ^= CAN_TEST_TX(mask); |
| 1589 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1590 | } |
| 1591 | |
| 1592 | static inline hri_can_test_reg_t hri_can_read_TEST_TX_bf(const void *const hw) |
| 1593 | { |
| 1594 | uint32_t tmp; |
| 1595 | tmp = ((Can *)hw)->TEST.reg; |
| 1596 | tmp = (tmp & CAN_TEST_TX_Msk) >> CAN_TEST_TX_Pos; |
| 1597 | return tmp; |
| 1598 | } |
| 1599 | |
| 1600 | static inline void hri_can_set_TEST_reg(const void *const hw, hri_can_test_reg_t mask) |
| 1601 | { |
| 1602 | CAN_CRITICAL_SECTION_ENTER(); |
| 1603 | ((Can *)hw)->TEST.reg |= mask; |
| 1604 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1605 | } |
| 1606 | |
| 1607 | static inline hri_can_test_reg_t hri_can_get_TEST_reg(const void *const hw, hri_can_test_reg_t mask) |
| 1608 | { |
| 1609 | uint32_t tmp; |
| 1610 | tmp = ((Can *)hw)->TEST.reg; |
| 1611 | tmp &= mask; |
| 1612 | return tmp; |
| 1613 | } |
| 1614 | |
| 1615 | static inline void hri_can_write_TEST_reg(const void *const hw, hri_can_test_reg_t data) |
| 1616 | { |
| 1617 | CAN_CRITICAL_SECTION_ENTER(); |
| 1618 | ((Can *)hw)->TEST.reg = data; |
| 1619 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1620 | } |
| 1621 | |
| 1622 | static inline void hri_can_clear_TEST_reg(const void *const hw, hri_can_test_reg_t mask) |
| 1623 | { |
| 1624 | CAN_CRITICAL_SECTION_ENTER(); |
| 1625 | ((Can *)hw)->TEST.reg &= ~mask; |
| 1626 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1627 | } |
| 1628 | |
| 1629 | static inline void hri_can_toggle_TEST_reg(const void *const hw, hri_can_test_reg_t mask) |
| 1630 | { |
| 1631 | CAN_CRITICAL_SECTION_ENTER(); |
| 1632 | ((Can *)hw)->TEST.reg ^= mask; |
| 1633 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1634 | } |
| 1635 | |
| 1636 | static inline hri_can_test_reg_t hri_can_read_TEST_reg(const void *const hw) |
| 1637 | { |
| 1638 | return ((Can *)hw)->TEST.reg; |
| 1639 | } |
| 1640 | |
| 1641 | static inline void hri_can_set_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) |
| 1642 | { |
| 1643 | CAN_CRITICAL_SECTION_ENTER(); |
| 1644 | ((Can *)hw)->RWD.reg |= CAN_RWD_WDC(mask); |
| 1645 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1646 | } |
| 1647 | |
| 1648 | static inline hri_can_rwd_reg_t hri_can_get_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) |
| 1649 | { |
| 1650 | uint32_t tmp; |
| 1651 | tmp = ((Can *)hw)->RWD.reg; |
| 1652 | tmp = (tmp & CAN_RWD_WDC(mask)) >> CAN_RWD_WDC_Pos; |
| 1653 | return tmp; |
| 1654 | } |
| 1655 | |
| 1656 | static inline void hri_can_write_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t data) |
| 1657 | { |
| 1658 | uint32_t tmp; |
| 1659 | CAN_CRITICAL_SECTION_ENTER(); |
| 1660 | tmp = ((Can *)hw)->RWD.reg; |
| 1661 | tmp &= ~CAN_RWD_WDC_Msk; |
| 1662 | tmp |= CAN_RWD_WDC(data); |
| 1663 | ((Can *)hw)->RWD.reg = tmp; |
| 1664 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1665 | } |
| 1666 | |
| 1667 | static inline void hri_can_clear_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) |
| 1668 | { |
| 1669 | CAN_CRITICAL_SECTION_ENTER(); |
| 1670 | ((Can *)hw)->RWD.reg &= ~CAN_RWD_WDC(mask); |
| 1671 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1672 | } |
| 1673 | |
| 1674 | static inline void hri_can_toggle_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) |
| 1675 | { |
| 1676 | CAN_CRITICAL_SECTION_ENTER(); |
| 1677 | ((Can *)hw)->RWD.reg ^= CAN_RWD_WDC(mask); |
| 1678 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1679 | } |
| 1680 | |
| 1681 | static inline hri_can_rwd_reg_t hri_can_read_RWD_WDC_bf(const void *const hw) |
| 1682 | { |
| 1683 | uint32_t tmp; |
| 1684 | tmp = ((Can *)hw)->RWD.reg; |
| 1685 | tmp = (tmp & CAN_RWD_WDC_Msk) >> CAN_RWD_WDC_Pos; |
| 1686 | return tmp; |
| 1687 | } |
| 1688 | |
| 1689 | static inline void hri_can_set_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) |
| 1690 | { |
| 1691 | CAN_CRITICAL_SECTION_ENTER(); |
| 1692 | ((Can *)hw)->RWD.reg |= CAN_RWD_WDV(mask); |
| 1693 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1694 | } |
| 1695 | |
| 1696 | static inline hri_can_rwd_reg_t hri_can_get_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) |
| 1697 | { |
| 1698 | uint32_t tmp; |
| 1699 | tmp = ((Can *)hw)->RWD.reg; |
| 1700 | tmp = (tmp & CAN_RWD_WDV(mask)) >> CAN_RWD_WDV_Pos; |
| 1701 | return tmp; |
| 1702 | } |
| 1703 | |
| 1704 | static inline void hri_can_write_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t data) |
| 1705 | { |
| 1706 | uint32_t tmp; |
| 1707 | CAN_CRITICAL_SECTION_ENTER(); |
| 1708 | tmp = ((Can *)hw)->RWD.reg; |
| 1709 | tmp &= ~CAN_RWD_WDV_Msk; |
| 1710 | tmp |= CAN_RWD_WDV(data); |
| 1711 | ((Can *)hw)->RWD.reg = tmp; |
| 1712 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1713 | } |
| 1714 | |
| 1715 | static inline void hri_can_clear_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) |
| 1716 | { |
| 1717 | CAN_CRITICAL_SECTION_ENTER(); |
| 1718 | ((Can *)hw)->RWD.reg &= ~CAN_RWD_WDV(mask); |
| 1719 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1720 | } |
| 1721 | |
| 1722 | static inline void hri_can_toggle_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) |
| 1723 | { |
| 1724 | CAN_CRITICAL_SECTION_ENTER(); |
| 1725 | ((Can *)hw)->RWD.reg ^= CAN_RWD_WDV(mask); |
| 1726 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1727 | } |
| 1728 | |
| 1729 | static inline hri_can_rwd_reg_t hri_can_read_RWD_WDV_bf(const void *const hw) |
| 1730 | { |
| 1731 | uint32_t tmp; |
| 1732 | tmp = ((Can *)hw)->RWD.reg; |
| 1733 | tmp = (tmp & CAN_RWD_WDV_Msk) >> CAN_RWD_WDV_Pos; |
| 1734 | return tmp; |
| 1735 | } |
| 1736 | |
| 1737 | static inline void hri_can_set_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) |
| 1738 | { |
| 1739 | CAN_CRITICAL_SECTION_ENTER(); |
| 1740 | ((Can *)hw)->RWD.reg |= mask; |
| 1741 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1742 | } |
| 1743 | |
| 1744 | static inline hri_can_rwd_reg_t hri_can_get_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) |
| 1745 | { |
| 1746 | uint32_t tmp; |
| 1747 | tmp = ((Can *)hw)->RWD.reg; |
| 1748 | tmp &= mask; |
| 1749 | return tmp; |
| 1750 | } |
| 1751 | |
| 1752 | static inline void hri_can_write_RWD_reg(const void *const hw, hri_can_rwd_reg_t data) |
| 1753 | { |
| 1754 | CAN_CRITICAL_SECTION_ENTER(); |
| 1755 | ((Can *)hw)->RWD.reg = data; |
| 1756 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1757 | } |
| 1758 | |
| 1759 | static inline void hri_can_clear_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) |
| 1760 | { |
| 1761 | CAN_CRITICAL_SECTION_ENTER(); |
| 1762 | ((Can *)hw)->RWD.reg &= ~mask; |
| 1763 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1764 | } |
| 1765 | |
| 1766 | static inline void hri_can_toggle_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) |
| 1767 | { |
| 1768 | CAN_CRITICAL_SECTION_ENTER(); |
| 1769 | ((Can *)hw)->RWD.reg ^= mask; |
| 1770 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1771 | } |
| 1772 | |
| 1773 | static inline hri_can_rwd_reg_t hri_can_read_RWD_reg(const void *const hw) |
| 1774 | { |
| 1775 | return ((Can *)hw)->RWD.reg; |
| 1776 | } |
| 1777 | |
| 1778 | static inline void hri_can_set_CCCR_INIT_bit(const void *const hw) |
| 1779 | { |
| 1780 | CAN_CRITICAL_SECTION_ENTER(); |
| 1781 | ((Can *)hw)->CCCR.reg |= CAN_CCCR_INIT; |
| 1782 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1783 | } |
| 1784 | |
| 1785 | static inline bool hri_can_get_CCCR_INIT_bit(const void *const hw) |
| 1786 | { |
| 1787 | uint32_t tmp; |
| 1788 | tmp = ((Can *)hw)->CCCR.reg; |
| 1789 | tmp = (tmp & CAN_CCCR_INIT) >> CAN_CCCR_INIT_Pos; |
| 1790 | return (bool)tmp; |
| 1791 | } |
| 1792 | |
| 1793 | static inline void hri_can_write_CCCR_INIT_bit(const void *const hw, bool value) |
| 1794 | { |
| 1795 | uint32_t tmp; |
| 1796 | CAN_CRITICAL_SECTION_ENTER(); |
| 1797 | tmp = ((Can *)hw)->CCCR.reg; |
| 1798 | tmp &= ~CAN_CCCR_INIT; |
| 1799 | tmp |= value << CAN_CCCR_INIT_Pos; |
| 1800 | ((Can *)hw)->CCCR.reg = tmp; |
| 1801 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1802 | } |
| 1803 | |
| 1804 | static inline void hri_can_clear_CCCR_INIT_bit(const void *const hw) |
| 1805 | { |
| 1806 | CAN_CRITICAL_SECTION_ENTER(); |
| 1807 | ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_INIT; |
| 1808 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1809 | } |
| 1810 | |
| 1811 | static inline void hri_can_toggle_CCCR_INIT_bit(const void *const hw) |
| 1812 | { |
| 1813 | CAN_CRITICAL_SECTION_ENTER(); |
| 1814 | ((Can *)hw)->CCCR.reg ^= CAN_CCCR_INIT; |
| 1815 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1816 | } |
| 1817 | |
| 1818 | static inline void hri_can_set_CCCR_CCE_bit(const void *const hw) |
| 1819 | { |
| 1820 | CAN_CRITICAL_SECTION_ENTER(); |
| 1821 | ((Can *)hw)->CCCR.reg |= CAN_CCCR_CCE; |
| 1822 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1823 | } |
| 1824 | |
| 1825 | static inline bool hri_can_get_CCCR_CCE_bit(const void *const hw) |
| 1826 | { |
| 1827 | uint32_t tmp; |
| 1828 | tmp = ((Can *)hw)->CCCR.reg; |
| 1829 | tmp = (tmp & CAN_CCCR_CCE) >> CAN_CCCR_CCE_Pos; |
| 1830 | return (bool)tmp; |
| 1831 | } |
| 1832 | |
| 1833 | static inline void hri_can_write_CCCR_CCE_bit(const void *const hw, bool value) |
| 1834 | { |
| 1835 | uint32_t tmp; |
| 1836 | CAN_CRITICAL_SECTION_ENTER(); |
| 1837 | tmp = ((Can *)hw)->CCCR.reg; |
| 1838 | tmp &= ~CAN_CCCR_CCE; |
| 1839 | tmp |= value << CAN_CCCR_CCE_Pos; |
| 1840 | ((Can *)hw)->CCCR.reg = tmp; |
| 1841 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1842 | } |
| 1843 | |
| 1844 | static inline void hri_can_clear_CCCR_CCE_bit(const void *const hw) |
| 1845 | { |
| 1846 | CAN_CRITICAL_SECTION_ENTER(); |
| 1847 | ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CCE; |
| 1848 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1849 | } |
| 1850 | |
| 1851 | static inline void hri_can_toggle_CCCR_CCE_bit(const void *const hw) |
| 1852 | { |
| 1853 | CAN_CRITICAL_SECTION_ENTER(); |
| 1854 | ((Can *)hw)->CCCR.reg ^= CAN_CCCR_CCE; |
| 1855 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1856 | } |
| 1857 | |
| 1858 | static inline void hri_can_set_CCCR_ASM_bit(const void *const hw) |
| 1859 | { |
| 1860 | CAN_CRITICAL_SECTION_ENTER(); |
| 1861 | ((Can *)hw)->CCCR.reg |= CAN_CCCR_ASM; |
| 1862 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1863 | } |
| 1864 | |
| 1865 | static inline bool hri_can_get_CCCR_ASM_bit(const void *const hw) |
| 1866 | { |
| 1867 | uint32_t tmp; |
| 1868 | tmp = ((Can *)hw)->CCCR.reg; |
| 1869 | tmp = (tmp & CAN_CCCR_ASM) >> CAN_CCCR_ASM_Pos; |
| 1870 | return (bool)tmp; |
| 1871 | } |
| 1872 | |
| 1873 | static inline void hri_can_write_CCCR_ASM_bit(const void *const hw, bool value) |
| 1874 | { |
| 1875 | uint32_t tmp; |
| 1876 | CAN_CRITICAL_SECTION_ENTER(); |
| 1877 | tmp = ((Can *)hw)->CCCR.reg; |
| 1878 | tmp &= ~CAN_CCCR_ASM; |
| 1879 | tmp |= value << CAN_CCCR_ASM_Pos; |
| 1880 | ((Can *)hw)->CCCR.reg = tmp; |
| 1881 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1882 | } |
| 1883 | |
| 1884 | static inline void hri_can_clear_CCCR_ASM_bit(const void *const hw) |
| 1885 | { |
| 1886 | CAN_CRITICAL_SECTION_ENTER(); |
| 1887 | ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_ASM; |
| 1888 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1889 | } |
| 1890 | |
| 1891 | static inline void hri_can_toggle_CCCR_ASM_bit(const void *const hw) |
| 1892 | { |
| 1893 | CAN_CRITICAL_SECTION_ENTER(); |
| 1894 | ((Can *)hw)->CCCR.reg ^= CAN_CCCR_ASM; |
| 1895 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1896 | } |
| 1897 | |
| 1898 | static inline void hri_can_set_CCCR_CSA_bit(const void *const hw) |
| 1899 | { |
| 1900 | CAN_CRITICAL_SECTION_ENTER(); |
| 1901 | ((Can *)hw)->CCCR.reg |= CAN_CCCR_CSA; |
| 1902 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1903 | } |
| 1904 | |
| 1905 | static inline bool hri_can_get_CCCR_CSA_bit(const void *const hw) |
| 1906 | { |
| 1907 | uint32_t tmp; |
| 1908 | tmp = ((Can *)hw)->CCCR.reg; |
| 1909 | tmp = (tmp & CAN_CCCR_CSA) >> CAN_CCCR_CSA_Pos; |
| 1910 | return (bool)tmp; |
| 1911 | } |
| 1912 | |
| 1913 | static inline void hri_can_write_CCCR_CSA_bit(const void *const hw, bool value) |
| 1914 | { |
| 1915 | uint32_t tmp; |
| 1916 | CAN_CRITICAL_SECTION_ENTER(); |
| 1917 | tmp = ((Can *)hw)->CCCR.reg; |
| 1918 | tmp &= ~CAN_CCCR_CSA; |
| 1919 | tmp |= value << CAN_CCCR_CSA_Pos; |
| 1920 | ((Can *)hw)->CCCR.reg = tmp; |
| 1921 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1922 | } |
| 1923 | |
| 1924 | static inline void hri_can_clear_CCCR_CSA_bit(const void *const hw) |
| 1925 | { |
| 1926 | CAN_CRITICAL_SECTION_ENTER(); |
| 1927 | ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CSA; |
| 1928 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1929 | } |
| 1930 | |
| 1931 | static inline void hri_can_toggle_CCCR_CSA_bit(const void *const hw) |
| 1932 | { |
| 1933 | CAN_CRITICAL_SECTION_ENTER(); |
| 1934 | ((Can *)hw)->CCCR.reg ^= CAN_CCCR_CSA; |
| 1935 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1936 | } |
| 1937 | |
| 1938 | static inline void hri_can_set_CCCR_CSR_bit(const void *const hw) |
| 1939 | { |
| 1940 | CAN_CRITICAL_SECTION_ENTER(); |
| 1941 | ((Can *)hw)->CCCR.reg |= CAN_CCCR_CSR; |
| 1942 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1943 | } |
| 1944 | |
| 1945 | static inline bool hri_can_get_CCCR_CSR_bit(const void *const hw) |
| 1946 | { |
| 1947 | uint32_t tmp; |
| 1948 | tmp = ((Can *)hw)->CCCR.reg; |
| 1949 | tmp = (tmp & CAN_CCCR_CSR) >> CAN_CCCR_CSR_Pos; |
| 1950 | return (bool)tmp; |
| 1951 | } |
| 1952 | |
| 1953 | static inline void hri_can_write_CCCR_CSR_bit(const void *const hw, bool value) |
| 1954 | { |
| 1955 | uint32_t tmp; |
| 1956 | CAN_CRITICAL_SECTION_ENTER(); |
| 1957 | tmp = ((Can *)hw)->CCCR.reg; |
| 1958 | tmp &= ~CAN_CCCR_CSR; |
| 1959 | tmp |= value << CAN_CCCR_CSR_Pos; |
| 1960 | ((Can *)hw)->CCCR.reg = tmp; |
| 1961 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1962 | } |
| 1963 | |
| 1964 | static inline void hri_can_clear_CCCR_CSR_bit(const void *const hw) |
| 1965 | { |
| 1966 | CAN_CRITICAL_SECTION_ENTER(); |
| 1967 | ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CSR; |
| 1968 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1969 | } |
| 1970 | |
| 1971 | static inline void hri_can_toggle_CCCR_CSR_bit(const void *const hw) |
| 1972 | { |
| 1973 | CAN_CRITICAL_SECTION_ENTER(); |
| 1974 | ((Can *)hw)->CCCR.reg ^= CAN_CCCR_CSR; |
| 1975 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1976 | } |
| 1977 | |
| 1978 | static inline void hri_can_set_CCCR_MON_bit(const void *const hw) |
| 1979 | { |
| 1980 | CAN_CRITICAL_SECTION_ENTER(); |
| 1981 | ((Can *)hw)->CCCR.reg |= CAN_CCCR_MON; |
| 1982 | CAN_CRITICAL_SECTION_LEAVE(); |
| 1983 | } |
| 1984 | |
| 1985 | static inline bool hri_can_get_CCCR_MON_bit(const void *const hw) |
| 1986 | { |
| 1987 | uint32_t tmp; |
| 1988 | tmp = ((Can *)hw)->CCCR.reg; |
| 1989 | tmp = (tmp & CAN_CCCR_MON) >> CAN_CCCR_MON_Pos; |
| 1990 | return (bool)tmp; |
| 1991 | } |
| 1992 | |
| 1993 | static inline void hri_can_write_CCCR_MON_bit(const void *const hw, bool value) |
| 1994 | { |
| 1995 | uint32_t tmp; |
| 1996 | CAN_CRITICAL_SECTION_ENTER(); |
| 1997 | tmp = ((Can *)hw)->CCCR.reg; |
| 1998 | tmp &= ~CAN_CCCR_MON; |
| 1999 | tmp |= value << CAN_CCCR_MON_Pos; |
| 2000 | ((Can *)hw)->CCCR.reg = tmp; |
| 2001 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2002 | } |
| 2003 | |
| 2004 | static inline void hri_can_clear_CCCR_MON_bit(const void *const hw) |
| 2005 | { |
| 2006 | CAN_CRITICAL_SECTION_ENTER(); |
| 2007 | ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_MON; |
| 2008 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2009 | } |
| 2010 | |
| 2011 | static inline void hri_can_toggle_CCCR_MON_bit(const void *const hw) |
| 2012 | { |
| 2013 | CAN_CRITICAL_SECTION_ENTER(); |
| 2014 | ((Can *)hw)->CCCR.reg ^= CAN_CCCR_MON; |
| 2015 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2016 | } |
| 2017 | |
| 2018 | static inline void hri_can_set_CCCR_DAR_bit(const void *const hw) |
| 2019 | { |
| 2020 | CAN_CRITICAL_SECTION_ENTER(); |
| 2021 | ((Can *)hw)->CCCR.reg |= CAN_CCCR_DAR; |
| 2022 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2023 | } |
| 2024 | |
| 2025 | static inline bool hri_can_get_CCCR_DAR_bit(const void *const hw) |
| 2026 | { |
| 2027 | uint32_t tmp; |
| 2028 | tmp = ((Can *)hw)->CCCR.reg; |
| 2029 | tmp = (tmp & CAN_CCCR_DAR) >> CAN_CCCR_DAR_Pos; |
| 2030 | return (bool)tmp; |
| 2031 | } |
| 2032 | |
| 2033 | static inline void hri_can_write_CCCR_DAR_bit(const void *const hw, bool value) |
| 2034 | { |
| 2035 | uint32_t tmp; |
| 2036 | CAN_CRITICAL_SECTION_ENTER(); |
| 2037 | tmp = ((Can *)hw)->CCCR.reg; |
| 2038 | tmp &= ~CAN_CCCR_DAR; |
| 2039 | tmp |= value << CAN_CCCR_DAR_Pos; |
| 2040 | ((Can *)hw)->CCCR.reg = tmp; |
| 2041 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2042 | } |
| 2043 | |
| 2044 | static inline void hri_can_clear_CCCR_DAR_bit(const void *const hw) |
| 2045 | { |
| 2046 | CAN_CRITICAL_SECTION_ENTER(); |
| 2047 | ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_DAR; |
| 2048 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2049 | } |
| 2050 | |
| 2051 | static inline void hri_can_toggle_CCCR_DAR_bit(const void *const hw) |
| 2052 | { |
| 2053 | CAN_CRITICAL_SECTION_ENTER(); |
| 2054 | ((Can *)hw)->CCCR.reg ^= CAN_CCCR_DAR; |
| 2055 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2056 | } |
| 2057 | |
| 2058 | static inline void hri_can_set_CCCR_TEST_bit(const void *const hw) |
| 2059 | { |
| 2060 | CAN_CRITICAL_SECTION_ENTER(); |
| 2061 | ((Can *)hw)->CCCR.reg |= CAN_CCCR_TEST; |
| 2062 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2063 | } |
| 2064 | |
| 2065 | static inline bool hri_can_get_CCCR_TEST_bit(const void *const hw) |
| 2066 | { |
| 2067 | uint32_t tmp; |
| 2068 | tmp = ((Can *)hw)->CCCR.reg; |
| 2069 | tmp = (tmp & CAN_CCCR_TEST) >> CAN_CCCR_TEST_Pos; |
| 2070 | return (bool)tmp; |
| 2071 | } |
| 2072 | |
| 2073 | static inline void hri_can_write_CCCR_TEST_bit(const void *const hw, bool value) |
| 2074 | { |
| 2075 | uint32_t tmp; |
| 2076 | CAN_CRITICAL_SECTION_ENTER(); |
| 2077 | tmp = ((Can *)hw)->CCCR.reg; |
| 2078 | tmp &= ~CAN_CCCR_TEST; |
| 2079 | tmp |= value << CAN_CCCR_TEST_Pos; |
| 2080 | ((Can *)hw)->CCCR.reg = tmp; |
| 2081 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2082 | } |
| 2083 | |
| 2084 | static inline void hri_can_clear_CCCR_TEST_bit(const void *const hw) |
| 2085 | { |
| 2086 | CAN_CRITICAL_SECTION_ENTER(); |
| 2087 | ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_TEST; |
| 2088 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2089 | } |
| 2090 | |
| 2091 | static inline void hri_can_toggle_CCCR_TEST_bit(const void *const hw) |
| 2092 | { |
| 2093 | CAN_CRITICAL_SECTION_ENTER(); |
| 2094 | ((Can *)hw)->CCCR.reg ^= CAN_CCCR_TEST; |
| 2095 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2096 | } |
| 2097 | |
| 2098 | static inline void hri_can_set_CCCR_FDOE_bit(const void *const hw) |
| 2099 | { |
| 2100 | CAN_CRITICAL_SECTION_ENTER(); |
| 2101 | ((Can *)hw)->CCCR.reg |= CAN_CCCR_FDOE; |
| 2102 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2103 | } |
| 2104 | |
| 2105 | static inline bool hri_can_get_CCCR_FDOE_bit(const void *const hw) |
| 2106 | { |
| 2107 | uint32_t tmp; |
| 2108 | tmp = ((Can *)hw)->CCCR.reg; |
| 2109 | tmp = (tmp & CAN_CCCR_FDOE) >> CAN_CCCR_FDOE_Pos; |
| 2110 | return (bool)tmp; |
| 2111 | } |
| 2112 | |
| 2113 | static inline void hri_can_write_CCCR_FDOE_bit(const void *const hw, bool value) |
| 2114 | { |
| 2115 | uint32_t tmp; |
| 2116 | CAN_CRITICAL_SECTION_ENTER(); |
| 2117 | tmp = ((Can *)hw)->CCCR.reg; |
| 2118 | tmp &= ~CAN_CCCR_FDOE; |
| 2119 | tmp |= value << CAN_CCCR_FDOE_Pos; |
| 2120 | ((Can *)hw)->CCCR.reg = tmp; |
| 2121 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2122 | } |
| 2123 | |
| 2124 | static inline void hri_can_clear_CCCR_FDOE_bit(const void *const hw) |
| 2125 | { |
| 2126 | CAN_CRITICAL_SECTION_ENTER(); |
| 2127 | ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_FDOE; |
| 2128 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2129 | } |
| 2130 | |
| 2131 | static inline void hri_can_toggle_CCCR_FDOE_bit(const void *const hw) |
| 2132 | { |
| 2133 | CAN_CRITICAL_SECTION_ENTER(); |
| 2134 | ((Can *)hw)->CCCR.reg ^= CAN_CCCR_FDOE; |
| 2135 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2136 | } |
| 2137 | |
| 2138 | static inline void hri_can_set_CCCR_BRSE_bit(const void *const hw) |
| 2139 | { |
| 2140 | CAN_CRITICAL_SECTION_ENTER(); |
| 2141 | ((Can *)hw)->CCCR.reg |= CAN_CCCR_BRSE; |
| 2142 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2143 | } |
| 2144 | |
| 2145 | static inline bool hri_can_get_CCCR_BRSE_bit(const void *const hw) |
| 2146 | { |
| 2147 | uint32_t tmp; |
| 2148 | tmp = ((Can *)hw)->CCCR.reg; |
| 2149 | tmp = (tmp & CAN_CCCR_BRSE) >> CAN_CCCR_BRSE_Pos; |
| 2150 | return (bool)tmp; |
| 2151 | } |
| 2152 | |
| 2153 | static inline void hri_can_write_CCCR_BRSE_bit(const void *const hw, bool value) |
| 2154 | { |
| 2155 | uint32_t tmp; |
| 2156 | CAN_CRITICAL_SECTION_ENTER(); |
| 2157 | tmp = ((Can *)hw)->CCCR.reg; |
| 2158 | tmp &= ~CAN_CCCR_BRSE; |
| 2159 | tmp |= value << CAN_CCCR_BRSE_Pos; |
| 2160 | ((Can *)hw)->CCCR.reg = tmp; |
| 2161 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2162 | } |
| 2163 | |
| 2164 | static inline void hri_can_clear_CCCR_BRSE_bit(const void *const hw) |
| 2165 | { |
| 2166 | CAN_CRITICAL_SECTION_ENTER(); |
| 2167 | ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_BRSE; |
| 2168 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2169 | } |
| 2170 | |
| 2171 | static inline void hri_can_toggle_CCCR_BRSE_bit(const void *const hw) |
| 2172 | { |
| 2173 | CAN_CRITICAL_SECTION_ENTER(); |
| 2174 | ((Can *)hw)->CCCR.reg ^= CAN_CCCR_BRSE; |
| 2175 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2176 | } |
| 2177 | |
| 2178 | static inline void hri_can_set_CCCR_PXHD_bit(const void *const hw) |
| 2179 | { |
| 2180 | CAN_CRITICAL_SECTION_ENTER(); |
| 2181 | ((Can *)hw)->CCCR.reg |= CAN_CCCR_PXHD; |
| 2182 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2183 | } |
| 2184 | |
| 2185 | static inline bool hri_can_get_CCCR_PXHD_bit(const void *const hw) |
| 2186 | { |
| 2187 | uint32_t tmp; |
| 2188 | tmp = ((Can *)hw)->CCCR.reg; |
| 2189 | tmp = (tmp & CAN_CCCR_PXHD) >> CAN_CCCR_PXHD_Pos; |
| 2190 | return (bool)tmp; |
| 2191 | } |
| 2192 | |
| 2193 | static inline void hri_can_write_CCCR_PXHD_bit(const void *const hw, bool value) |
| 2194 | { |
| 2195 | uint32_t tmp; |
| 2196 | CAN_CRITICAL_SECTION_ENTER(); |
| 2197 | tmp = ((Can *)hw)->CCCR.reg; |
| 2198 | tmp &= ~CAN_CCCR_PXHD; |
| 2199 | tmp |= value << CAN_CCCR_PXHD_Pos; |
| 2200 | ((Can *)hw)->CCCR.reg = tmp; |
| 2201 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2202 | } |
| 2203 | |
| 2204 | static inline void hri_can_clear_CCCR_PXHD_bit(const void *const hw) |
| 2205 | { |
| 2206 | CAN_CRITICAL_SECTION_ENTER(); |
| 2207 | ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_PXHD; |
| 2208 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2209 | } |
| 2210 | |
| 2211 | static inline void hri_can_toggle_CCCR_PXHD_bit(const void *const hw) |
| 2212 | { |
| 2213 | CAN_CRITICAL_SECTION_ENTER(); |
| 2214 | ((Can *)hw)->CCCR.reg ^= CAN_CCCR_PXHD; |
| 2215 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2216 | } |
| 2217 | |
| 2218 | static inline void hri_can_set_CCCR_EFBI_bit(const void *const hw) |
| 2219 | { |
| 2220 | CAN_CRITICAL_SECTION_ENTER(); |
| 2221 | ((Can *)hw)->CCCR.reg |= CAN_CCCR_EFBI; |
| 2222 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2223 | } |
| 2224 | |
| 2225 | static inline bool hri_can_get_CCCR_EFBI_bit(const void *const hw) |
| 2226 | { |
| 2227 | uint32_t tmp; |
| 2228 | tmp = ((Can *)hw)->CCCR.reg; |
| 2229 | tmp = (tmp & CAN_CCCR_EFBI) >> CAN_CCCR_EFBI_Pos; |
| 2230 | return (bool)tmp; |
| 2231 | } |
| 2232 | |
| 2233 | static inline void hri_can_write_CCCR_EFBI_bit(const void *const hw, bool value) |
| 2234 | { |
| 2235 | uint32_t tmp; |
| 2236 | CAN_CRITICAL_SECTION_ENTER(); |
| 2237 | tmp = ((Can *)hw)->CCCR.reg; |
| 2238 | tmp &= ~CAN_CCCR_EFBI; |
| 2239 | tmp |= value << CAN_CCCR_EFBI_Pos; |
| 2240 | ((Can *)hw)->CCCR.reg = tmp; |
| 2241 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2242 | } |
| 2243 | |
| 2244 | static inline void hri_can_clear_CCCR_EFBI_bit(const void *const hw) |
| 2245 | { |
| 2246 | CAN_CRITICAL_SECTION_ENTER(); |
| 2247 | ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_EFBI; |
| 2248 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2249 | } |
| 2250 | |
| 2251 | static inline void hri_can_toggle_CCCR_EFBI_bit(const void *const hw) |
| 2252 | { |
| 2253 | CAN_CRITICAL_SECTION_ENTER(); |
| 2254 | ((Can *)hw)->CCCR.reg ^= CAN_CCCR_EFBI; |
| 2255 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2256 | } |
| 2257 | |
| 2258 | static inline void hri_can_set_CCCR_TXP_bit(const void *const hw) |
| 2259 | { |
| 2260 | CAN_CRITICAL_SECTION_ENTER(); |
| 2261 | ((Can *)hw)->CCCR.reg |= CAN_CCCR_TXP; |
| 2262 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2263 | } |
| 2264 | |
| 2265 | static inline bool hri_can_get_CCCR_TXP_bit(const void *const hw) |
| 2266 | { |
| 2267 | uint32_t tmp; |
| 2268 | tmp = ((Can *)hw)->CCCR.reg; |
| 2269 | tmp = (tmp & CAN_CCCR_TXP) >> CAN_CCCR_TXP_Pos; |
| 2270 | return (bool)tmp; |
| 2271 | } |
| 2272 | |
| 2273 | static inline void hri_can_write_CCCR_TXP_bit(const void *const hw, bool value) |
| 2274 | { |
| 2275 | uint32_t tmp; |
| 2276 | CAN_CRITICAL_SECTION_ENTER(); |
| 2277 | tmp = ((Can *)hw)->CCCR.reg; |
| 2278 | tmp &= ~CAN_CCCR_TXP; |
| 2279 | tmp |= value << CAN_CCCR_TXP_Pos; |
| 2280 | ((Can *)hw)->CCCR.reg = tmp; |
| 2281 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2282 | } |
| 2283 | |
| 2284 | static inline void hri_can_clear_CCCR_TXP_bit(const void *const hw) |
| 2285 | { |
| 2286 | CAN_CRITICAL_SECTION_ENTER(); |
| 2287 | ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_TXP; |
| 2288 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2289 | } |
| 2290 | |
| 2291 | static inline void hri_can_toggle_CCCR_TXP_bit(const void *const hw) |
| 2292 | { |
| 2293 | CAN_CRITICAL_SECTION_ENTER(); |
| 2294 | ((Can *)hw)->CCCR.reg ^= CAN_CCCR_TXP; |
| 2295 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2296 | } |
| 2297 | |
| 2298 | static inline void hri_can_set_CCCR_NISO_bit(const void *const hw) |
| 2299 | { |
| 2300 | CAN_CRITICAL_SECTION_ENTER(); |
| 2301 | ((Can *)hw)->CCCR.reg |= CAN_CCCR_NISO; |
| 2302 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2303 | } |
| 2304 | |
| 2305 | static inline bool hri_can_get_CCCR_NISO_bit(const void *const hw) |
| 2306 | { |
| 2307 | uint32_t tmp; |
| 2308 | tmp = ((Can *)hw)->CCCR.reg; |
| 2309 | tmp = (tmp & CAN_CCCR_NISO) >> CAN_CCCR_NISO_Pos; |
| 2310 | return (bool)tmp; |
| 2311 | } |
| 2312 | |
| 2313 | static inline void hri_can_write_CCCR_NISO_bit(const void *const hw, bool value) |
| 2314 | { |
| 2315 | uint32_t tmp; |
| 2316 | CAN_CRITICAL_SECTION_ENTER(); |
| 2317 | tmp = ((Can *)hw)->CCCR.reg; |
| 2318 | tmp &= ~CAN_CCCR_NISO; |
| 2319 | tmp |= value << CAN_CCCR_NISO_Pos; |
| 2320 | ((Can *)hw)->CCCR.reg = tmp; |
| 2321 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2322 | } |
| 2323 | |
| 2324 | static inline void hri_can_clear_CCCR_NISO_bit(const void *const hw) |
| 2325 | { |
| 2326 | CAN_CRITICAL_SECTION_ENTER(); |
| 2327 | ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_NISO; |
| 2328 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2329 | } |
| 2330 | |
| 2331 | static inline void hri_can_toggle_CCCR_NISO_bit(const void *const hw) |
| 2332 | { |
| 2333 | CAN_CRITICAL_SECTION_ENTER(); |
| 2334 | ((Can *)hw)->CCCR.reg ^= CAN_CCCR_NISO; |
| 2335 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2336 | } |
| 2337 | |
| 2338 | static inline void hri_can_set_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) |
| 2339 | { |
| 2340 | CAN_CRITICAL_SECTION_ENTER(); |
| 2341 | ((Can *)hw)->CCCR.reg |= mask; |
| 2342 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2343 | } |
| 2344 | |
| 2345 | static inline hri_can_cccr_reg_t hri_can_get_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) |
| 2346 | { |
| 2347 | uint32_t tmp; |
| 2348 | tmp = ((Can *)hw)->CCCR.reg; |
| 2349 | tmp &= mask; |
| 2350 | return tmp; |
| 2351 | } |
| 2352 | |
| 2353 | static inline void hri_can_write_CCCR_reg(const void *const hw, hri_can_cccr_reg_t data) |
| 2354 | { |
| 2355 | CAN_CRITICAL_SECTION_ENTER(); |
| 2356 | ((Can *)hw)->CCCR.reg = data; |
| 2357 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2358 | } |
| 2359 | |
| 2360 | static inline void hri_can_clear_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) |
| 2361 | { |
| 2362 | CAN_CRITICAL_SECTION_ENTER(); |
| 2363 | ((Can *)hw)->CCCR.reg &= ~mask; |
| 2364 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2365 | } |
| 2366 | |
| 2367 | static inline void hri_can_toggle_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) |
| 2368 | { |
| 2369 | CAN_CRITICAL_SECTION_ENTER(); |
| 2370 | ((Can *)hw)->CCCR.reg ^= mask; |
| 2371 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2372 | } |
| 2373 | |
| 2374 | static inline hri_can_cccr_reg_t hri_can_read_CCCR_reg(const void *const hw) |
| 2375 | { |
| 2376 | return ((Can *)hw)->CCCR.reg; |
| 2377 | } |
| 2378 | |
| 2379 | static inline void hri_can_set_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) |
| 2380 | { |
| 2381 | CAN_CRITICAL_SECTION_ENTER(); |
| 2382 | ((Can *)hw)->NBTP.reg |= CAN_NBTP_NTSEG2(mask); |
| 2383 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2384 | } |
| 2385 | |
| 2386 | static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) |
| 2387 | { |
| 2388 | uint32_t tmp; |
| 2389 | tmp = ((Can *)hw)->NBTP.reg; |
| 2390 | tmp = (tmp & CAN_NBTP_NTSEG2(mask)) >> CAN_NBTP_NTSEG2_Pos; |
| 2391 | return tmp; |
| 2392 | } |
| 2393 | |
| 2394 | static inline void hri_can_write_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t data) |
| 2395 | { |
| 2396 | uint32_t tmp; |
| 2397 | CAN_CRITICAL_SECTION_ENTER(); |
| 2398 | tmp = ((Can *)hw)->NBTP.reg; |
| 2399 | tmp &= ~CAN_NBTP_NTSEG2_Msk; |
| 2400 | tmp |= CAN_NBTP_NTSEG2(data); |
| 2401 | ((Can *)hw)->NBTP.reg = tmp; |
| 2402 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2403 | } |
| 2404 | |
| 2405 | static inline void hri_can_clear_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) |
| 2406 | { |
| 2407 | CAN_CRITICAL_SECTION_ENTER(); |
| 2408 | ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NTSEG2(mask); |
| 2409 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2410 | } |
| 2411 | |
| 2412 | static inline void hri_can_toggle_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) |
| 2413 | { |
| 2414 | CAN_CRITICAL_SECTION_ENTER(); |
| 2415 | ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NTSEG2(mask); |
| 2416 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2417 | } |
| 2418 | |
| 2419 | static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NTSEG2_bf(const void *const hw) |
| 2420 | { |
| 2421 | uint32_t tmp; |
| 2422 | tmp = ((Can *)hw)->NBTP.reg; |
| 2423 | tmp = (tmp & CAN_NBTP_NTSEG2_Msk) >> CAN_NBTP_NTSEG2_Pos; |
| 2424 | return tmp; |
| 2425 | } |
| 2426 | |
| 2427 | static inline void hri_can_set_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) |
| 2428 | { |
| 2429 | CAN_CRITICAL_SECTION_ENTER(); |
| 2430 | ((Can *)hw)->NBTP.reg |= CAN_NBTP_NTSEG1(mask); |
| 2431 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2432 | } |
| 2433 | |
| 2434 | static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) |
| 2435 | { |
| 2436 | uint32_t tmp; |
| 2437 | tmp = ((Can *)hw)->NBTP.reg; |
| 2438 | tmp = (tmp & CAN_NBTP_NTSEG1(mask)) >> CAN_NBTP_NTSEG1_Pos; |
| 2439 | return tmp; |
| 2440 | } |
| 2441 | |
| 2442 | static inline void hri_can_write_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t data) |
| 2443 | { |
| 2444 | uint32_t tmp; |
| 2445 | CAN_CRITICAL_SECTION_ENTER(); |
| 2446 | tmp = ((Can *)hw)->NBTP.reg; |
| 2447 | tmp &= ~CAN_NBTP_NTSEG1_Msk; |
| 2448 | tmp |= CAN_NBTP_NTSEG1(data); |
| 2449 | ((Can *)hw)->NBTP.reg = tmp; |
| 2450 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2451 | } |
| 2452 | |
| 2453 | static inline void hri_can_clear_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) |
| 2454 | { |
| 2455 | CAN_CRITICAL_SECTION_ENTER(); |
| 2456 | ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NTSEG1(mask); |
| 2457 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2458 | } |
| 2459 | |
| 2460 | static inline void hri_can_toggle_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) |
| 2461 | { |
| 2462 | CAN_CRITICAL_SECTION_ENTER(); |
| 2463 | ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NTSEG1(mask); |
| 2464 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2465 | } |
| 2466 | |
| 2467 | static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NTSEG1_bf(const void *const hw) |
| 2468 | { |
| 2469 | uint32_t tmp; |
| 2470 | tmp = ((Can *)hw)->NBTP.reg; |
| 2471 | tmp = (tmp & CAN_NBTP_NTSEG1_Msk) >> CAN_NBTP_NTSEG1_Pos; |
| 2472 | return tmp; |
| 2473 | } |
| 2474 | |
| 2475 | static inline void hri_can_set_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) |
| 2476 | { |
| 2477 | CAN_CRITICAL_SECTION_ENTER(); |
| 2478 | ((Can *)hw)->NBTP.reg |= CAN_NBTP_NBRP(mask); |
| 2479 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2480 | } |
| 2481 | |
| 2482 | static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) |
| 2483 | { |
| 2484 | uint32_t tmp; |
| 2485 | tmp = ((Can *)hw)->NBTP.reg; |
| 2486 | tmp = (tmp & CAN_NBTP_NBRP(mask)) >> CAN_NBTP_NBRP_Pos; |
| 2487 | return tmp; |
| 2488 | } |
| 2489 | |
| 2490 | static inline void hri_can_write_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t data) |
| 2491 | { |
| 2492 | uint32_t tmp; |
| 2493 | CAN_CRITICAL_SECTION_ENTER(); |
| 2494 | tmp = ((Can *)hw)->NBTP.reg; |
| 2495 | tmp &= ~CAN_NBTP_NBRP_Msk; |
| 2496 | tmp |= CAN_NBTP_NBRP(data); |
| 2497 | ((Can *)hw)->NBTP.reg = tmp; |
| 2498 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2499 | } |
| 2500 | |
| 2501 | static inline void hri_can_clear_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) |
| 2502 | { |
| 2503 | CAN_CRITICAL_SECTION_ENTER(); |
| 2504 | ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NBRP(mask); |
| 2505 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2506 | } |
| 2507 | |
| 2508 | static inline void hri_can_toggle_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) |
| 2509 | { |
| 2510 | CAN_CRITICAL_SECTION_ENTER(); |
| 2511 | ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NBRP(mask); |
| 2512 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2513 | } |
| 2514 | |
| 2515 | static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NBRP_bf(const void *const hw) |
| 2516 | { |
| 2517 | uint32_t tmp; |
| 2518 | tmp = ((Can *)hw)->NBTP.reg; |
| 2519 | tmp = (tmp & CAN_NBTP_NBRP_Msk) >> CAN_NBTP_NBRP_Pos; |
| 2520 | return tmp; |
| 2521 | } |
| 2522 | |
| 2523 | static inline void hri_can_set_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) |
| 2524 | { |
| 2525 | CAN_CRITICAL_SECTION_ENTER(); |
| 2526 | ((Can *)hw)->NBTP.reg |= CAN_NBTP_NSJW(mask); |
| 2527 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2528 | } |
| 2529 | |
| 2530 | static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) |
| 2531 | { |
| 2532 | uint32_t tmp; |
| 2533 | tmp = ((Can *)hw)->NBTP.reg; |
| 2534 | tmp = (tmp & CAN_NBTP_NSJW(mask)) >> CAN_NBTP_NSJW_Pos; |
| 2535 | return tmp; |
| 2536 | } |
| 2537 | |
| 2538 | static inline void hri_can_write_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t data) |
| 2539 | { |
| 2540 | uint32_t tmp; |
| 2541 | CAN_CRITICAL_SECTION_ENTER(); |
| 2542 | tmp = ((Can *)hw)->NBTP.reg; |
| 2543 | tmp &= ~CAN_NBTP_NSJW_Msk; |
| 2544 | tmp |= CAN_NBTP_NSJW(data); |
| 2545 | ((Can *)hw)->NBTP.reg = tmp; |
| 2546 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2547 | } |
| 2548 | |
| 2549 | static inline void hri_can_clear_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) |
| 2550 | { |
| 2551 | CAN_CRITICAL_SECTION_ENTER(); |
| 2552 | ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NSJW(mask); |
| 2553 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2554 | } |
| 2555 | |
| 2556 | static inline void hri_can_toggle_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) |
| 2557 | { |
| 2558 | CAN_CRITICAL_SECTION_ENTER(); |
| 2559 | ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NSJW(mask); |
| 2560 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2561 | } |
| 2562 | |
| 2563 | static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NSJW_bf(const void *const hw) |
| 2564 | { |
| 2565 | uint32_t tmp; |
| 2566 | tmp = ((Can *)hw)->NBTP.reg; |
| 2567 | tmp = (tmp & CAN_NBTP_NSJW_Msk) >> CAN_NBTP_NSJW_Pos; |
| 2568 | return tmp; |
| 2569 | } |
| 2570 | |
| 2571 | static inline void hri_can_set_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) |
| 2572 | { |
| 2573 | CAN_CRITICAL_SECTION_ENTER(); |
| 2574 | ((Can *)hw)->NBTP.reg |= mask; |
| 2575 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2576 | } |
| 2577 | |
| 2578 | static inline hri_can_nbtp_reg_t hri_can_get_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) |
| 2579 | { |
| 2580 | uint32_t tmp; |
| 2581 | tmp = ((Can *)hw)->NBTP.reg; |
| 2582 | tmp &= mask; |
| 2583 | return tmp; |
| 2584 | } |
| 2585 | |
| 2586 | static inline void hri_can_write_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t data) |
| 2587 | { |
| 2588 | CAN_CRITICAL_SECTION_ENTER(); |
| 2589 | ((Can *)hw)->NBTP.reg = data; |
| 2590 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2591 | } |
| 2592 | |
| 2593 | static inline void hri_can_clear_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) |
| 2594 | { |
| 2595 | CAN_CRITICAL_SECTION_ENTER(); |
| 2596 | ((Can *)hw)->NBTP.reg &= ~mask; |
| 2597 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2598 | } |
| 2599 | |
| 2600 | static inline void hri_can_toggle_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) |
| 2601 | { |
| 2602 | CAN_CRITICAL_SECTION_ENTER(); |
| 2603 | ((Can *)hw)->NBTP.reg ^= mask; |
| 2604 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2605 | } |
| 2606 | |
| 2607 | static inline hri_can_nbtp_reg_t hri_can_read_NBTP_reg(const void *const hw) |
| 2608 | { |
| 2609 | return ((Can *)hw)->NBTP.reg; |
| 2610 | } |
| 2611 | |
| 2612 | static inline void hri_can_set_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) |
| 2613 | { |
| 2614 | CAN_CRITICAL_SECTION_ENTER(); |
| 2615 | ((Can *)hw)->TSCC.reg |= CAN_TSCC_TSS(mask); |
| 2616 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2617 | } |
| 2618 | |
| 2619 | static inline hri_can_tscc_reg_t hri_can_get_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) |
| 2620 | { |
| 2621 | uint32_t tmp; |
| 2622 | tmp = ((Can *)hw)->TSCC.reg; |
| 2623 | tmp = (tmp & CAN_TSCC_TSS(mask)) >> CAN_TSCC_TSS_Pos; |
| 2624 | return tmp; |
| 2625 | } |
| 2626 | |
| 2627 | static inline void hri_can_write_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t data) |
| 2628 | { |
| 2629 | uint32_t tmp; |
| 2630 | CAN_CRITICAL_SECTION_ENTER(); |
| 2631 | tmp = ((Can *)hw)->TSCC.reg; |
| 2632 | tmp &= ~CAN_TSCC_TSS_Msk; |
| 2633 | tmp |= CAN_TSCC_TSS(data); |
| 2634 | ((Can *)hw)->TSCC.reg = tmp; |
| 2635 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2636 | } |
| 2637 | |
| 2638 | static inline void hri_can_clear_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) |
| 2639 | { |
| 2640 | CAN_CRITICAL_SECTION_ENTER(); |
| 2641 | ((Can *)hw)->TSCC.reg &= ~CAN_TSCC_TSS(mask); |
| 2642 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2643 | } |
| 2644 | |
| 2645 | static inline void hri_can_toggle_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) |
| 2646 | { |
| 2647 | CAN_CRITICAL_SECTION_ENTER(); |
| 2648 | ((Can *)hw)->TSCC.reg ^= CAN_TSCC_TSS(mask); |
| 2649 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2650 | } |
| 2651 | |
| 2652 | static inline hri_can_tscc_reg_t hri_can_read_TSCC_TSS_bf(const void *const hw) |
| 2653 | { |
| 2654 | uint32_t tmp; |
| 2655 | tmp = ((Can *)hw)->TSCC.reg; |
| 2656 | tmp = (tmp & CAN_TSCC_TSS_Msk) >> CAN_TSCC_TSS_Pos; |
| 2657 | return tmp; |
| 2658 | } |
| 2659 | |
| 2660 | static inline void hri_can_set_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) |
| 2661 | { |
| 2662 | CAN_CRITICAL_SECTION_ENTER(); |
| 2663 | ((Can *)hw)->TSCC.reg |= CAN_TSCC_TCP(mask); |
| 2664 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2665 | } |
| 2666 | |
| 2667 | static inline hri_can_tscc_reg_t hri_can_get_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) |
| 2668 | { |
| 2669 | uint32_t tmp; |
| 2670 | tmp = ((Can *)hw)->TSCC.reg; |
| 2671 | tmp = (tmp & CAN_TSCC_TCP(mask)) >> CAN_TSCC_TCP_Pos; |
| 2672 | return tmp; |
| 2673 | } |
| 2674 | |
| 2675 | static inline void hri_can_write_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t data) |
| 2676 | { |
| 2677 | uint32_t tmp; |
| 2678 | CAN_CRITICAL_SECTION_ENTER(); |
| 2679 | tmp = ((Can *)hw)->TSCC.reg; |
| 2680 | tmp &= ~CAN_TSCC_TCP_Msk; |
| 2681 | tmp |= CAN_TSCC_TCP(data); |
| 2682 | ((Can *)hw)->TSCC.reg = tmp; |
| 2683 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2684 | } |
| 2685 | |
| 2686 | static inline void hri_can_clear_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) |
| 2687 | { |
| 2688 | CAN_CRITICAL_SECTION_ENTER(); |
| 2689 | ((Can *)hw)->TSCC.reg &= ~CAN_TSCC_TCP(mask); |
| 2690 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2691 | } |
| 2692 | |
| 2693 | static inline void hri_can_toggle_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) |
| 2694 | { |
| 2695 | CAN_CRITICAL_SECTION_ENTER(); |
| 2696 | ((Can *)hw)->TSCC.reg ^= CAN_TSCC_TCP(mask); |
| 2697 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2698 | } |
| 2699 | |
| 2700 | static inline hri_can_tscc_reg_t hri_can_read_TSCC_TCP_bf(const void *const hw) |
| 2701 | { |
| 2702 | uint32_t tmp; |
| 2703 | tmp = ((Can *)hw)->TSCC.reg; |
| 2704 | tmp = (tmp & CAN_TSCC_TCP_Msk) >> CAN_TSCC_TCP_Pos; |
| 2705 | return tmp; |
| 2706 | } |
| 2707 | |
| 2708 | static inline void hri_can_set_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) |
| 2709 | { |
| 2710 | CAN_CRITICAL_SECTION_ENTER(); |
| 2711 | ((Can *)hw)->TSCC.reg |= mask; |
| 2712 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2713 | } |
| 2714 | |
| 2715 | static inline hri_can_tscc_reg_t hri_can_get_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) |
| 2716 | { |
| 2717 | uint32_t tmp; |
| 2718 | tmp = ((Can *)hw)->TSCC.reg; |
| 2719 | tmp &= mask; |
| 2720 | return tmp; |
| 2721 | } |
| 2722 | |
| 2723 | static inline void hri_can_write_TSCC_reg(const void *const hw, hri_can_tscc_reg_t data) |
| 2724 | { |
| 2725 | CAN_CRITICAL_SECTION_ENTER(); |
| 2726 | ((Can *)hw)->TSCC.reg = data; |
| 2727 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2728 | } |
| 2729 | |
| 2730 | static inline void hri_can_clear_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) |
| 2731 | { |
| 2732 | CAN_CRITICAL_SECTION_ENTER(); |
| 2733 | ((Can *)hw)->TSCC.reg &= ~mask; |
| 2734 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2735 | } |
| 2736 | |
| 2737 | static inline void hri_can_toggle_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) |
| 2738 | { |
| 2739 | CAN_CRITICAL_SECTION_ENTER(); |
| 2740 | ((Can *)hw)->TSCC.reg ^= mask; |
| 2741 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2742 | } |
| 2743 | |
| 2744 | static inline hri_can_tscc_reg_t hri_can_read_TSCC_reg(const void *const hw) |
| 2745 | { |
| 2746 | return ((Can *)hw)->TSCC.reg; |
| 2747 | } |
| 2748 | |
| 2749 | static inline void hri_can_set_TOCC_ETOC_bit(const void *const hw) |
| 2750 | { |
| 2751 | CAN_CRITICAL_SECTION_ENTER(); |
| 2752 | ((Can *)hw)->TOCC.reg |= CAN_TOCC_ETOC; |
| 2753 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2754 | } |
| 2755 | |
| 2756 | static inline bool hri_can_get_TOCC_ETOC_bit(const void *const hw) |
| 2757 | { |
| 2758 | uint32_t tmp; |
| 2759 | tmp = ((Can *)hw)->TOCC.reg; |
| 2760 | tmp = (tmp & CAN_TOCC_ETOC) >> CAN_TOCC_ETOC_Pos; |
| 2761 | return (bool)tmp; |
| 2762 | } |
| 2763 | |
| 2764 | static inline void hri_can_write_TOCC_ETOC_bit(const void *const hw, bool value) |
| 2765 | { |
| 2766 | uint32_t tmp; |
| 2767 | CAN_CRITICAL_SECTION_ENTER(); |
| 2768 | tmp = ((Can *)hw)->TOCC.reg; |
| 2769 | tmp &= ~CAN_TOCC_ETOC; |
| 2770 | tmp |= value << CAN_TOCC_ETOC_Pos; |
| 2771 | ((Can *)hw)->TOCC.reg = tmp; |
| 2772 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2773 | } |
| 2774 | |
| 2775 | static inline void hri_can_clear_TOCC_ETOC_bit(const void *const hw) |
| 2776 | { |
| 2777 | CAN_CRITICAL_SECTION_ENTER(); |
| 2778 | ((Can *)hw)->TOCC.reg &= ~CAN_TOCC_ETOC; |
| 2779 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2780 | } |
| 2781 | |
| 2782 | static inline void hri_can_toggle_TOCC_ETOC_bit(const void *const hw) |
| 2783 | { |
| 2784 | CAN_CRITICAL_SECTION_ENTER(); |
| 2785 | ((Can *)hw)->TOCC.reg ^= CAN_TOCC_ETOC; |
| 2786 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2787 | } |
| 2788 | |
| 2789 | static inline void hri_can_set_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) |
| 2790 | { |
| 2791 | CAN_CRITICAL_SECTION_ENTER(); |
| 2792 | ((Can *)hw)->TOCC.reg |= CAN_TOCC_TOS(mask); |
| 2793 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2794 | } |
| 2795 | |
| 2796 | static inline hri_can_tocc_reg_t hri_can_get_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) |
| 2797 | { |
| 2798 | uint32_t tmp; |
| 2799 | tmp = ((Can *)hw)->TOCC.reg; |
| 2800 | tmp = (tmp & CAN_TOCC_TOS(mask)) >> CAN_TOCC_TOS_Pos; |
| 2801 | return tmp; |
| 2802 | } |
| 2803 | |
| 2804 | static inline void hri_can_write_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t data) |
| 2805 | { |
| 2806 | uint32_t tmp; |
| 2807 | CAN_CRITICAL_SECTION_ENTER(); |
| 2808 | tmp = ((Can *)hw)->TOCC.reg; |
| 2809 | tmp &= ~CAN_TOCC_TOS_Msk; |
| 2810 | tmp |= CAN_TOCC_TOS(data); |
| 2811 | ((Can *)hw)->TOCC.reg = tmp; |
| 2812 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2813 | } |
| 2814 | |
| 2815 | static inline void hri_can_clear_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) |
| 2816 | { |
| 2817 | CAN_CRITICAL_SECTION_ENTER(); |
| 2818 | ((Can *)hw)->TOCC.reg &= ~CAN_TOCC_TOS(mask); |
| 2819 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2820 | } |
| 2821 | |
| 2822 | static inline void hri_can_toggle_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) |
| 2823 | { |
| 2824 | CAN_CRITICAL_SECTION_ENTER(); |
| 2825 | ((Can *)hw)->TOCC.reg ^= CAN_TOCC_TOS(mask); |
| 2826 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2827 | } |
| 2828 | |
| 2829 | static inline hri_can_tocc_reg_t hri_can_read_TOCC_TOS_bf(const void *const hw) |
| 2830 | { |
| 2831 | uint32_t tmp; |
| 2832 | tmp = ((Can *)hw)->TOCC.reg; |
| 2833 | tmp = (tmp & CAN_TOCC_TOS_Msk) >> CAN_TOCC_TOS_Pos; |
| 2834 | return tmp; |
| 2835 | } |
| 2836 | |
| 2837 | static inline void hri_can_set_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) |
| 2838 | { |
| 2839 | CAN_CRITICAL_SECTION_ENTER(); |
| 2840 | ((Can *)hw)->TOCC.reg |= CAN_TOCC_TOP(mask); |
| 2841 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2842 | } |
| 2843 | |
| 2844 | static inline hri_can_tocc_reg_t hri_can_get_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) |
| 2845 | { |
| 2846 | uint32_t tmp; |
| 2847 | tmp = ((Can *)hw)->TOCC.reg; |
| 2848 | tmp = (tmp & CAN_TOCC_TOP(mask)) >> CAN_TOCC_TOP_Pos; |
| 2849 | return tmp; |
| 2850 | } |
| 2851 | |
| 2852 | static inline void hri_can_write_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t data) |
| 2853 | { |
| 2854 | uint32_t tmp; |
| 2855 | CAN_CRITICAL_SECTION_ENTER(); |
| 2856 | tmp = ((Can *)hw)->TOCC.reg; |
| 2857 | tmp &= ~CAN_TOCC_TOP_Msk; |
| 2858 | tmp |= CAN_TOCC_TOP(data); |
| 2859 | ((Can *)hw)->TOCC.reg = tmp; |
| 2860 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2861 | } |
| 2862 | |
| 2863 | static inline void hri_can_clear_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) |
| 2864 | { |
| 2865 | CAN_CRITICAL_SECTION_ENTER(); |
| 2866 | ((Can *)hw)->TOCC.reg &= ~CAN_TOCC_TOP(mask); |
| 2867 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2868 | } |
| 2869 | |
| 2870 | static inline void hri_can_toggle_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) |
| 2871 | { |
| 2872 | CAN_CRITICAL_SECTION_ENTER(); |
| 2873 | ((Can *)hw)->TOCC.reg ^= CAN_TOCC_TOP(mask); |
| 2874 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2875 | } |
| 2876 | |
| 2877 | static inline hri_can_tocc_reg_t hri_can_read_TOCC_TOP_bf(const void *const hw) |
| 2878 | { |
| 2879 | uint32_t tmp; |
| 2880 | tmp = ((Can *)hw)->TOCC.reg; |
| 2881 | tmp = (tmp & CAN_TOCC_TOP_Msk) >> CAN_TOCC_TOP_Pos; |
| 2882 | return tmp; |
| 2883 | } |
| 2884 | |
| 2885 | static inline void hri_can_set_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) |
| 2886 | { |
| 2887 | CAN_CRITICAL_SECTION_ENTER(); |
| 2888 | ((Can *)hw)->TOCC.reg |= mask; |
| 2889 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2890 | } |
| 2891 | |
| 2892 | static inline hri_can_tocc_reg_t hri_can_get_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) |
| 2893 | { |
| 2894 | uint32_t tmp; |
| 2895 | tmp = ((Can *)hw)->TOCC.reg; |
| 2896 | tmp &= mask; |
| 2897 | return tmp; |
| 2898 | } |
| 2899 | |
| 2900 | static inline void hri_can_write_TOCC_reg(const void *const hw, hri_can_tocc_reg_t data) |
| 2901 | { |
| 2902 | CAN_CRITICAL_SECTION_ENTER(); |
| 2903 | ((Can *)hw)->TOCC.reg = data; |
| 2904 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2905 | } |
| 2906 | |
| 2907 | static inline void hri_can_clear_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) |
| 2908 | { |
| 2909 | CAN_CRITICAL_SECTION_ENTER(); |
| 2910 | ((Can *)hw)->TOCC.reg &= ~mask; |
| 2911 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2912 | } |
| 2913 | |
| 2914 | static inline void hri_can_toggle_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) |
| 2915 | { |
| 2916 | CAN_CRITICAL_SECTION_ENTER(); |
| 2917 | ((Can *)hw)->TOCC.reg ^= mask; |
| 2918 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2919 | } |
| 2920 | |
| 2921 | static inline hri_can_tocc_reg_t hri_can_read_TOCC_reg(const void *const hw) |
| 2922 | { |
| 2923 | return ((Can *)hw)->TOCC.reg; |
| 2924 | } |
| 2925 | |
| 2926 | static inline void hri_can_set_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) |
| 2927 | { |
| 2928 | CAN_CRITICAL_SECTION_ENTER(); |
| 2929 | ((Can *)hw)->TOCV.reg |= CAN_TOCV_TOC(mask); |
| 2930 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2931 | } |
| 2932 | |
| 2933 | static inline hri_can_tocv_reg_t hri_can_get_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) |
| 2934 | { |
| 2935 | uint32_t tmp; |
| 2936 | tmp = ((Can *)hw)->TOCV.reg; |
| 2937 | tmp = (tmp & CAN_TOCV_TOC(mask)) >> CAN_TOCV_TOC_Pos; |
| 2938 | return tmp; |
| 2939 | } |
| 2940 | |
| 2941 | static inline void hri_can_write_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t data) |
| 2942 | { |
| 2943 | uint32_t tmp; |
| 2944 | CAN_CRITICAL_SECTION_ENTER(); |
| 2945 | tmp = ((Can *)hw)->TOCV.reg; |
| 2946 | tmp &= ~CAN_TOCV_TOC_Msk; |
| 2947 | tmp |= CAN_TOCV_TOC(data); |
| 2948 | ((Can *)hw)->TOCV.reg = tmp; |
| 2949 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2950 | } |
| 2951 | |
| 2952 | static inline void hri_can_clear_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) |
| 2953 | { |
| 2954 | CAN_CRITICAL_SECTION_ENTER(); |
| 2955 | ((Can *)hw)->TOCV.reg &= ~CAN_TOCV_TOC(mask); |
| 2956 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2957 | } |
| 2958 | |
| 2959 | static inline void hri_can_toggle_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) |
| 2960 | { |
| 2961 | CAN_CRITICAL_SECTION_ENTER(); |
| 2962 | ((Can *)hw)->TOCV.reg ^= CAN_TOCV_TOC(mask); |
| 2963 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2964 | } |
| 2965 | |
| 2966 | static inline hri_can_tocv_reg_t hri_can_read_TOCV_TOC_bf(const void *const hw) |
| 2967 | { |
| 2968 | uint32_t tmp; |
| 2969 | tmp = ((Can *)hw)->TOCV.reg; |
| 2970 | tmp = (tmp & CAN_TOCV_TOC_Msk) >> CAN_TOCV_TOC_Pos; |
| 2971 | return tmp; |
| 2972 | } |
| 2973 | |
| 2974 | static inline void hri_can_set_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) |
| 2975 | { |
| 2976 | CAN_CRITICAL_SECTION_ENTER(); |
| 2977 | ((Can *)hw)->TOCV.reg |= mask; |
| 2978 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2979 | } |
| 2980 | |
| 2981 | static inline hri_can_tocv_reg_t hri_can_get_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) |
| 2982 | { |
| 2983 | uint32_t tmp; |
| 2984 | tmp = ((Can *)hw)->TOCV.reg; |
| 2985 | tmp &= mask; |
| 2986 | return tmp; |
| 2987 | } |
| 2988 | |
| 2989 | static inline void hri_can_write_TOCV_reg(const void *const hw, hri_can_tocv_reg_t data) |
| 2990 | { |
| 2991 | CAN_CRITICAL_SECTION_ENTER(); |
| 2992 | ((Can *)hw)->TOCV.reg = data; |
| 2993 | CAN_CRITICAL_SECTION_LEAVE(); |
| 2994 | } |
| 2995 | |
| 2996 | static inline void hri_can_clear_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) |
| 2997 | { |
| 2998 | CAN_CRITICAL_SECTION_ENTER(); |
| 2999 | ((Can *)hw)->TOCV.reg &= ~mask; |
| 3000 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3001 | } |
| 3002 | |
| 3003 | static inline void hri_can_toggle_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) |
| 3004 | { |
| 3005 | CAN_CRITICAL_SECTION_ENTER(); |
| 3006 | ((Can *)hw)->TOCV.reg ^= mask; |
| 3007 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3008 | } |
| 3009 | |
| 3010 | static inline hri_can_tocv_reg_t hri_can_read_TOCV_reg(const void *const hw) |
| 3011 | { |
| 3012 | return ((Can *)hw)->TOCV.reg; |
| 3013 | } |
| 3014 | |
| 3015 | static inline void hri_can_set_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) |
| 3016 | { |
| 3017 | CAN_CRITICAL_SECTION_ENTER(); |
| 3018 | ((Can *)hw)->TDCR.reg |= CAN_TDCR_TDCF(mask); |
| 3019 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3020 | } |
| 3021 | |
| 3022 | static inline hri_can_tdcr_reg_t hri_can_get_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) |
| 3023 | { |
| 3024 | uint32_t tmp; |
| 3025 | tmp = ((Can *)hw)->TDCR.reg; |
| 3026 | tmp = (tmp & CAN_TDCR_TDCF(mask)) >> CAN_TDCR_TDCF_Pos; |
| 3027 | return tmp; |
| 3028 | } |
| 3029 | |
| 3030 | static inline void hri_can_write_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t data) |
| 3031 | { |
| 3032 | uint32_t tmp; |
| 3033 | CAN_CRITICAL_SECTION_ENTER(); |
| 3034 | tmp = ((Can *)hw)->TDCR.reg; |
| 3035 | tmp &= ~CAN_TDCR_TDCF_Msk; |
| 3036 | tmp |= CAN_TDCR_TDCF(data); |
| 3037 | ((Can *)hw)->TDCR.reg = tmp; |
| 3038 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3039 | } |
| 3040 | |
| 3041 | static inline void hri_can_clear_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) |
| 3042 | { |
| 3043 | CAN_CRITICAL_SECTION_ENTER(); |
| 3044 | ((Can *)hw)->TDCR.reg &= ~CAN_TDCR_TDCF(mask); |
| 3045 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3046 | } |
| 3047 | |
| 3048 | static inline void hri_can_toggle_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) |
| 3049 | { |
| 3050 | CAN_CRITICAL_SECTION_ENTER(); |
| 3051 | ((Can *)hw)->TDCR.reg ^= CAN_TDCR_TDCF(mask); |
| 3052 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3053 | } |
| 3054 | |
| 3055 | static inline hri_can_tdcr_reg_t hri_can_read_TDCR_TDCF_bf(const void *const hw) |
| 3056 | { |
| 3057 | uint32_t tmp; |
| 3058 | tmp = ((Can *)hw)->TDCR.reg; |
| 3059 | tmp = (tmp & CAN_TDCR_TDCF_Msk) >> CAN_TDCR_TDCF_Pos; |
| 3060 | return tmp; |
| 3061 | } |
| 3062 | |
| 3063 | static inline void hri_can_set_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) |
| 3064 | { |
| 3065 | CAN_CRITICAL_SECTION_ENTER(); |
| 3066 | ((Can *)hw)->TDCR.reg |= CAN_TDCR_TDCO(mask); |
| 3067 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3068 | } |
| 3069 | |
| 3070 | static inline hri_can_tdcr_reg_t hri_can_get_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) |
| 3071 | { |
| 3072 | uint32_t tmp; |
| 3073 | tmp = ((Can *)hw)->TDCR.reg; |
| 3074 | tmp = (tmp & CAN_TDCR_TDCO(mask)) >> CAN_TDCR_TDCO_Pos; |
| 3075 | return tmp; |
| 3076 | } |
| 3077 | |
| 3078 | static inline void hri_can_write_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t data) |
| 3079 | { |
| 3080 | uint32_t tmp; |
| 3081 | CAN_CRITICAL_SECTION_ENTER(); |
| 3082 | tmp = ((Can *)hw)->TDCR.reg; |
| 3083 | tmp &= ~CAN_TDCR_TDCO_Msk; |
| 3084 | tmp |= CAN_TDCR_TDCO(data); |
| 3085 | ((Can *)hw)->TDCR.reg = tmp; |
| 3086 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3087 | } |
| 3088 | |
| 3089 | static inline void hri_can_clear_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) |
| 3090 | { |
| 3091 | CAN_CRITICAL_SECTION_ENTER(); |
| 3092 | ((Can *)hw)->TDCR.reg &= ~CAN_TDCR_TDCO(mask); |
| 3093 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3094 | } |
| 3095 | |
| 3096 | static inline void hri_can_toggle_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) |
| 3097 | { |
| 3098 | CAN_CRITICAL_SECTION_ENTER(); |
| 3099 | ((Can *)hw)->TDCR.reg ^= CAN_TDCR_TDCO(mask); |
| 3100 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3101 | } |
| 3102 | |
| 3103 | static inline hri_can_tdcr_reg_t hri_can_read_TDCR_TDCO_bf(const void *const hw) |
| 3104 | { |
| 3105 | uint32_t tmp; |
| 3106 | tmp = ((Can *)hw)->TDCR.reg; |
| 3107 | tmp = (tmp & CAN_TDCR_TDCO_Msk) >> CAN_TDCR_TDCO_Pos; |
| 3108 | return tmp; |
| 3109 | } |
| 3110 | |
| 3111 | static inline void hri_can_set_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) |
| 3112 | { |
| 3113 | CAN_CRITICAL_SECTION_ENTER(); |
| 3114 | ((Can *)hw)->TDCR.reg |= mask; |
| 3115 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3116 | } |
| 3117 | |
| 3118 | static inline hri_can_tdcr_reg_t hri_can_get_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) |
| 3119 | { |
| 3120 | uint32_t tmp; |
| 3121 | tmp = ((Can *)hw)->TDCR.reg; |
| 3122 | tmp &= mask; |
| 3123 | return tmp; |
| 3124 | } |
| 3125 | |
| 3126 | static inline void hri_can_write_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t data) |
| 3127 | { |
| 3128 | CAN_CRITICAL_SECTION_ENTER(); |
| 3129 | ((Can *)hw)->TDCR.reg = data; |
| 3130 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3131 | } |
| 3132 | |
| 3133 | static inline void hri_can_clear_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) |
| 3134 | { |
| 3135 | CAN_CRITICAL_SECTION_ENTER(); |
| 3136 | ((Can *)hw)->TDCR.reg &= ~mask; |
| 3137 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3138 | } |
| 3139 | |
| 3140 | static inline void hri_can_toggle_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) |
| 3141 | { |
| 3142 | CAN_CRITICAL_SECTION_ENTER(); |
| 3143 | ((Can *)hw)->TDCR.reg ^= mask; |
| 3144 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3145 | } |
| 3146 | |
| 3147 | static inline hri_can_tdcr_reg_t hri_can_read_TDCR_reg(const void *const hw) |
| 3148 | { |
| 3149 | return ((Can *)hw)->TDCR.reg; |
| 3150 | } |
| 3151 | |
| 3152 | static inline void hri_can_set_IR_RF0N_bit(const void *const hw) |
| 3153 | { |
| 3154 | CAN_CRITICAL_SECTION_ENTER(); |
| 3155 | ((Can *)hw)->IR.reg |= CAN_IR_RF0N; |
| 3156 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3157 | } |
| 3158 | |
| 3159 | static inline bool hri_can_get_IR_RF0N_bit(const void *const hw) |
| 3160 | { |
| 3161 | uint32_t tmp; |
| 3162 | tmp = ((Can *)hw)->IR.reg; |
| 3163 | tmp = (tmp & CAN_IR_RF0N) >> CAN_IR_RF0N_Pos; |
| 3164 | return (bool)tmp; |
| 3165 | } |
| 3166 | |
| 3167 | static inline void hri_can_write_IR_RF0N_bit(const void *const hw, bool value) |
| 3168 | { |
| 3169 | uint32_t tmp; |
| 3170 | CAN_CRITICAL_SECTION_ENTER(); |
| 3171 | tmp = ((Can *)hw)->IR.reg; |
| 3172 | tmp &= ~CAN_IR_RF0N; |
| 3173 | tmp |= value << CAN_IR_RF0N_Pos; |
| 3174 | ((Can *)hw)->IR.reg = tmp; |
| 3175 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3176 | } |
| 3177 | |
| 3178 | static inline void hri_can_clear_IR_RF0N_bit(const void *const hw) |
| 3179 | { |
| 3180 | CAN_CRITICAL_SECTION_ENTER(); |
| 3181 | ((Can *)hw)->IR.reg &= ~CAN_IR_RF0N; |
| 3182 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3183 | } |
| 3184 | |
| 3185 | static inline void hri_can_toggle_IR_RF0N_bit(const void *const hw) |
| 3186 | { |
| 3187 | CAN_CRITICAL_SECTION_ENTER(); |
| 3188 | ((Can *)hw)->IR.reg ^= CAN_IR_RF0N; |
| 3189 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3190 | } |
| 3191 | |
| 3192 | static inline void hri_can_set_IR_RF0W_bit(const void *const hw) |
| 3193 | { |
| 3194 | CAN_CRITICAL_SECTION_ENTER(); |
| 3195 | ((Can *)hw)->IR.reg |= CAN_IR_RF0W; |
| 3196 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3197 | } |
| 3198 | |
| 3199 | static inline bool hri_can_get_IR_RF0W_bit(const void *const hw) |
| 3200 | { |
| 3201 | uint32_t tmp; |
| 3202 | tmp = ((Can *)hw)->IR.reg; |
| 3203 | tmp = (tmp & CAN_IR_RF0W) >> CAN_IR_RF0W_Pos; |
| 3204 | return (bool)tmp; |
| 3205 | } |
| 3206 | |
| 3207 | static inline void hri_can_write_IR_RF0W_bit(const void *const hw, bool value) |
| 3208 | { |
| 3209 | uint32_t tmp; |
| 3210 | CAN_CRITICAL_SECTION_ENTER(); |
| 3211 | tmp = ((Can *)hw)->IR.reg; |
| 3212 | tmp &= ~CAN_IR_RF0W; |
| 3213 | tmp |= value << CAN_IR_RF0W_Pos; |
| 3214 | ((Can *)hw)->IR.reg = tmp; |
| 3215 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3216 | } |
| 3217 | |
| 3218 | static inline void hri_can_clear_IR_RF0W_bit(const void *const hw) |
| 3219 | { |
| 3220 | CAN_CRITICAL_SECTION_ENTER(); |
| 3221 | ((Can *)hw)->IR.reg &= ~CAN_IR_RF0W; |
| 3222 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3223 | } |
| 3224 | |
| 3225 | static inline void hri_can_toggle_IR_RF0W_bit(const void *const hw) |
| 3226 | { |
| 3227 | CAN_CRITICAL_SECTION_ENTER(); |
| 3228 | ((Can *)hw)->IR.reg ^= CAN_IR_RF0W; |
| 3229 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3230 | } |
| 3231 | |
| 3232 | static inline void hri_can_set_IR_RF0F_bit(const void *const hw) |
| 3233 | { |
| 3234 | CAN_CRITICAL_SECTION_ENTER(); |
| 3235 | ((Can *)hw)->IR.reg |= CAN_IR_RF0F; |
| 3236 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3237 | } |
| 3238 | |
| 3239 | static inline bool hri_can_get_IR_RF0F_bit(const void *const hw) |
| 3240 | { |
| 3241 | uint32_t tmp; |
| 3242 | tmp = ((Can *)hw)->IR.reg; |
| 3243 | tmp = (tmp & CAN_IR_RF0F) >> CAN_IR_RF0F_Pos; |
| 3244 | return (bool)tmp; |
| 3245 | } |
| 3246 | |
| 3247 | static inline void hri_can_write_IR_RF0F_bit(const void *const hw, bool value) |
| 3248 | { |
| 3249 | uint32_t tmp; |
| 3250 | CAN_CRITICAL_SECTION_ENTER(); |
| 3251 | tmp = ((Can *)hw)->IR.reg; |
| 3252 | tmp &= ~CAN_IR_RF0F; |
| 3253 | tmp |= value << CAN_IR_RF0F_Pos; |
| 3254 | ((Can *)hw)->IR.reg = tmp; |
| 3255 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3256 | } |
| 3257 | |
| 3258 | static inline void hri_can_clear_IR_RF0F_bit(const void *const hw) |
| 3259 | { |
| 3260 | CAN_CRITICAL_SECTION_ENTER(); |
| 3261 | ((Can *)hw)->IR.reg &= ~CAN_IR_RF0F; |
| 3262 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3263 | } |
| 3264 | |
| 3265 | static inline void hri_can_toggle_IR_RF0F_bit(const void *const hw) |
| 3266 | { |
| 3267 | CAN_CRITICAL_SECTION_ENTER(); |
| 3268 | ((Can *)hw)->IR.reg ^= CAN_IR_RF0F; |
| 3269 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3270 | } |
| 3271 | |
| 3272 | static inline void hri_can_set_IR_RF0L_bit(const void *const hw) |
| 3273 | { |
| 3274 | CAN_CRITICAL_SECTION_ENTER(); |
| 3275 | ((Can *)hw)->IR.reg |= CAN_IR_RF0L; |
| 3276 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3277 | } |
| 3278 | |
| 3279 | static inline bool hri_can_get_IR_RF0L_bit(const void *const hw) |
| 3280 | { |
| 3281 | uint32_t tmp; |
| 3282 | tmp = ((Can *)hw)->IR.reg; |
| 3283 | tmp = (tmp & CAN_IR_RF0L) >> CAN_IR_RF0L_Pos; |
| 3284 | return (bool)tmp; |
| 3285 | } |
| 3286 | |
| 3287 | static inline void hri_can_write_IR_RF0L_bit(const void *const hw, bool value) |
| 3288 | { |
| 3289 | uint32_t tmp; |
| 3290 | CAN_CRITICAL_SECTION_ENTER(); |
| 3291 | tmp = ((Can *)hw)->IR.reg; |
| 3292 | tmp &= ~CAN_IR_RF0L; |
| 3293 | tmp |= value << CAN_IR_RF0L_Pos; |
| 3294 | ((Can *)hw)->IR.reg = tmp; |
| 3295 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3296 | } |
| 3297 | |
| 3298 | static inline void hri_can_clear_IR_RF0L_bit(const void *const hw) |
| 3299 | { |
| 3300 | CAN_CRITICAL_SECTION_ENTER(); |
| 3301 | ((Can *)hw)->IR.reg &= ~CAN_IR_RF0L; |
| 3302 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3303 | } |
| 3304 | |
| 3305 | static inline void hri_can_toggle_IR_RF0L_bit(const void *const hw) |
| 3306 | { |
| 3307 | CAN_CRITICAL_SECTION_ENTER(); |
| 3308 | ((Can *)hw)->IR.reg ^= CAN_IR_RF0L; |
| 3309 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3310 | } |
| 3311 | |
| 3312 | static inline void hri_can_set_IR_RF1N_bit(const void *const hw) |
| 3313 | { |
| 3314 | CAN_CRITICAL_SECTION_ENTER(); |
| 3315 | ((Can *)hw)->IR.reg |= CAN_IR_RF1N; |
| 3316 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3317 | } |
| 3318 | |
| 3319 | static inline bool hri_can_get_IR_RF1N_bit(const void *const hw) |
| 3320 | { |
| 3321 | uint32_t tmp; |
| 3322 | tmp = ((Can *)hw)->IR.reg; |
| 3323 | tmp = (tmp & CAN_IR_RF1N) >> CAN_IR_RF1N_Pos; |
| 3324 | return (bool)tmp; |
| 3325 | } |
| 3326 | |
| 3327 | static inline void hri_can_write_IR_RF1N_bit(const void *const hw, bool value) |
| 3328 | { |
| 3329 | uint32_t tmp; |
| 3330 | CAN_CRITICAL_SECTION_ENTER(); |
| 3331 | tmp = ((Can *)hw)->IR.reg; |
| 3332 | tmp &= ~CAN_IR_RF1N; |
| 3333 | tmp |= value << CAN_IR_RF1N_Pos; |
| 3334 | ((Can *)hw)->IR.reg = tmp; |
| 3335 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3336 | } |
| 3337 | |
| 3338 | static inline void hri_can_clear_IR_RF1N_bit(const void *const hw) |
| 3339 | { |
| 3340 | CAN_CRITICAL_SECTION_ENTER(); |
| 3341 | ((Can *)hw)->IR.reg &= ~CAN_IR_RF1N; |
| 3342 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3343 | } |
| 3344 | |
| 3345 | static inline void hri_can_toggle_IR_RF1N_bit(const void *const hw) |
| 3346 | { |
| 3347 | CAN_CRITICAL_SECTION_ENTER(); |
| 3348 | ((Can *)hw)->IR.reg ^= CAN_IR_RF1N; |
| 3349 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3350 | } |
| 3351 | |
| 3352 | static inline void hri_can_set_IR_RF1W_bit(const void *const hw) |
| 3353 | { |
| 3354 | CAN_CRITICAL_SECTION_ENTER(); |
| 3355 | ((Can *)hw)->IR.reg |= CAN_IR_RF1W; |
| 3356 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3357 | } |
| 3358 | |
| 3359 | static inline bool hri_can_get_IR_RF1W_bit(const void *const hw) |
| 3360 | { |
| 3361 | uint32_t tmp; |
| 3362 | tmp = ((Can *)hw)->IR.reg; |
| 3363 | tmp = (tmp & CAN_IR_RF1W) >> CAN_IR_RF1W_Pos; |
| 3364 | return (bool)tmp; |
| 3365 | } |
| 3366 | |
| 3367 | static inline void hri_can_write_IR_RF1W_bit(const void *const hw, bool value) |
| 3368 | { |
| 3369 | uint32_t tmp; |
| 3370 | CAN_CRITICAL_SECTION_ENTER(); |
| 3371 | tmp = ((Can *)hw)->IR.reg; |
| 3372 | tmp &= ~CAN_IR_RF1W; |
| 3373 | tmp |= value << CAN_IR_RF1W_Pos; |
| 3374 | ((Can *)hw)->IR.reg = tmp; |
| 3375 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3376 | } |
| 3377 | |
| 3378 | static inline void hri_can_clear_IR_RF1W_bit(const void *const hw) |
| 3379 | { |
| 3380 | CAN_CRITICAL_SECTION_ENTER(); |
| 3381 | ((Can *)hw)->IR.reg &= ~CAN_IR_RF1W; |
| 3382 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3383 | } |
| 3384 | |
| 3385 | static inline void hri_can_toggle_IR_RF1W_bit(const void *const hw) |
| 3386 | { |
| 3387 | CAN_CRITICAL_SECTION_ENTER(); |
| 3388 | ((Can *)hw)->IR.reg ^= CAN_IR_RF1W; |
| 3389 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3390 | } |
| 3391 | |
| 3392 | static inline void hri_can_set_IR_RF1F_bit(const void *const hw) |
| 3393 | { |
| 3394 | CAN_CRITICAL_SECTION_ENTER(); |
| 3395 | ((Can *)hw)->IR.reg |= CAN_IR_RF1F; |
| 3396 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3397 | } |
| 3398 | |
| 3399 | static inline bool hri_can_get_IR_RF1F_bit(const void *const hw) |
| 3400 | { |
| 3401 | uint32_t tmp; |
| 3402 | tmp = ((Can *)hw)->IR.reg; |
| 3403 | tmp = (tmp & CAN_IR_RF1F) >> CAN_IR_RF1F_Pos; |
| 3404 | return (bool)tmp; |
| 3405 | } |
| 3406 | |
| 3407 | static inline void hri_can_write_IR_RF1F_bit(const void *const hw, bool value) |
| 3408 | { |
| 3409 | uint32_t tmp; |
| 3410 | CAN_CRITICAL_SECTION_ENTER(); |
| 3411 | tmp = ((Can *)hw)->IR.reg; |
| 3412 | tmp &= ~CAN_IR_RF1F; |
| 3413 | tmp |= value << CAN_IR_RF1F_Pos; |
| 3414 | ((Can *)hw)->IR.reg = tmp; |
| 3415 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3416 | } |
| 3417 | |
| 3418 | static inline void hri_can_clear_IR_RF1F_bit(const void *const hw) |
| 3419 | { |
| 3420 | CAN_CRITICAL_SECTION_ENTER(); |
| 3421 | ((Can *)hw)->IR.reg &= ~CAN_IR_RF1F; |
| 3422 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3423 | } |
| 3424 | |
| 3425 | static inline void hri_can_toggle_IR_RF1F_bit(const void *const hw) |
| 3426 | { |
| 3427 | CAN_CRITICAL_SECTION_ENTER(); |
| 3428 | ((Can *)hw)->IR.reg ^= CAN_IR_RF1F; |
| 3429 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3430 | } |
| 3431 | |
| 3432 | static inline void hri_can_set_IR_RF1L_bit(const void *const hw) |
| 3433 | { |
| 3434 | CAN_CRITICAL_SECTION_ENTER(); |
| 3435 | ((Can *)hw)->IR.reg |= CAN_IR_RF1L; |
| 3436 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3437 | } |
| 3438 | |
| 3439 | static inline bool hri_can_get_IR_RF1L_bit(const void *const hw) |
| 3440 | { |
| 3441 | uint32_t tmp; |
| 3442 | tmp = ((Can *)hw)->IR.reg; |
| 3443 | tmp = (tmp & CAN_IR_RF1L) >> CAN_IR_RF1L_Pos; |
| 3444 | return (bool)tmp; |
| 3445 | } |
| 3446 | |
| 3447 | static inline void hri_can_write_IR_RF1L_bit(const void *const hw, bool value) |
| 3448 | { |
| 3449 | uint32_t tmp; |
| 3450 | CAN_CRITICAL_SECTION_ENTER(); |
| 3451 | tmp = ((Can *)hw)->IR.reg; |
| 3452 | tmp &= ~CAN_IR_RF1L; |
| 3453 | tmp |= value << CAN_IR_RF1L_Pos; |
| 3454 | ((Can *)hw)->IR.reg = tmp; |
| 3455 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3456 | } |
| 3457 | |
| 3458 | static inline void hri_can_clear_IR_RF1L_bit(const void *const hw) |
| 3459 | { |
| 3460 | CAN_CRITICAL_SECTION_ENTER(); |
| 3461 | ((Can *)hw)->IR.reg &= ~CAN_IR_RF1L; |
| 3462 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3463 | } |
| 3464 | |
| 3465 | static inline void hri_can_toggle_IR_RF1L_bit(const void *const hw) |
| 3466 | { |
| 3467 | CAN_CRITICAL_SECTION_ENTER(); |
| 3468 | ((Can *)hw)->IR.reg ^= CAN_IR_RF1L; |
| 3469 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3470 | } |
| 3471 | |
| 3472 | static inline void hri_can_set_IR_HPM_bit(const void *const hw) |
| 3473 | { |
| 3474 | CAN_CRITICAL_SECTION_ENTER(); |
| 3475 | ((Can *)hw)->IR.reg |= CAN_IR_HPM; |
| 3476 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3477 | } |
| 3478 | |
| 3479 | static inline bool hri_can_get_IR_HPM_bit(const void *const hw) |
| 3480 | { |
| 3481 | uint32_t tmp; |
| 3482 | tmp = ((Can *)hw)->IR.reg; |
| 3483 | tmp = (tmp & CAN_IR_HPM) >> CAN_IR_HPM_Pos; |
| 3484 | return (bool)tmp; |
| 3485 | } |
| 3486 | |
| 3487 | static inline void hri_can_write_IR_HPM_bit(const void *const hw, bool value) |
| 3488 | { |
| 3489 | uint32_t tmp; |
| 3490 | CAN_CRITICAL_SECTION_ENTER(); |
| 3491 | tmp = ((Can *)hw)->IR.reg; |
| 3492 | tmp &= ~CAN_IR_HPM; |
| 3493 | tmp |= value << CAN_IR_HPM_Pos; |
| 3494 | ((Can *)hw)->IR.reg = tmp; |
| 3495 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3496 | } |
| 3497 | |
| 3498 | static inline void hri_can_clear_IR_HPM_bit(const void *const hw) |
| 3499 | { |
| 3500 | CAN_CRITICAL_SECTION_ENTER(); |
| 3501 | ((Can *)hw)->IR.reg &= ~CAN_IR_HPM; |
| 3502 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3503 | } |
| 3504 | |
| 3505 | static inline void hri_can_toggle_IR_HPM_bit(const void *const hw) |
| 3506 | { |
| 3507 | CAN_CRITICAL_SECTION_ENTER(); |
| 3508 | ((Can *)hw)->IR.reg ^= CAN_IR_HPM; |
| 3509 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3510 | } |
| 3511 | |
| 3512 | static inline void hri_can_set_IR_TC_bit(const void *const hw) |
| 3513 | { |
| 3514 | CAN_CRITICAL_SECTION_ENTER(); |
| 3515 | ((Can *)hw)->IR.reg |= CAN_IR_TC; |
| 3516 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3517 | } |
| 3518 | |
| 3519 | static inline bool hri_can_get_IR_TC_bit(const void *const hw) |
| 3520 | { |
| 3521 | uint32_t tmp; |
| 3522 | tmp = ((Can *)hw)->IR.reg; |
| 3523 | tmp = (tmp & CAN_IR_TC) >> CAN_IR_TC_Pos; |
| 3524 | return (bool)tmp; |
| 3525 | } |
| 3526 | |
| 3527 | static inline void hri_can_write_IR_TC_bit(const void *const hw, bool value) |
| 3528 | { |
| 3529 | uint32_t tmp; |
| 3530 | CAN_CRITICAL_SECTION_ENTER(); |
| 3531 | tmp = ((Can *)hw)->IR.reg; |
| 3532 | tmp &= ~CAN_IR_TC; |
| 3533 | tmp |= value << CAN_IR_TC_Pos; |
| 3534 | ((Can *)hw)->IR.reg = tmp; |
| 3535 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3536 | } |
| 3537 | |
| 3538 | static inline void hri_can_clear_IR_TC_bit(const void *const hw) |
| 3539 | { |
| 3540 | CAN_CRITICAL_SECTION_ENTER(); |
| 3541 | ((Can *)hw)->IR.reg &= ~CAN_IR_TC; |
| 3542 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3543 | } |
| 3544 | |
| 3545 | static inline void hri_can_toggle_IR_TC_bit(const void *const hw) |
| 3546 | { |
| 3547 | CAN_CRITICAL_SECTION_ENTER(); |
| 3548 | ((Can *)hw)->IR.reg ^= CAN_IR_TC; |
| 3549 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3550 | } |
| 3551 | |
| 3552 | static inline void hri_can_set_IR_TCF_bit(const void *const hw) |
| 3553 | { |
| 3554 | CAN_CRITICAL_SECTION_ENTER(); |
| 3555 | ((Can *)hw)->IR.reg |= CAN_IR_TCF; |
| 3556 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3557 | } |
| 3558 | |
| 3559 | static inline bool hri_can_get_IR_TCF_bit(const void *const hw) |
| 3560 | { |
| 3561 | uint32_t tmp; |
| 3562 | tmp = ((Can *)hw)->IR.reg; |
| 3563 | tmp = (tmp & CAN_IR_TCF) >> CAN_IR_TCF_Pos; |
| 3564 | return (bool)tmp; |
| 3565 | } |
| 3566 | |
| 3567 | static inline void hri_can_write_IR_TCF_bit(const void *const hw, bool value) |
| 3568 | { |
| 3569 | uint32_t tmp; |
| 3570 | CAN_CRITICAL_SECTION_ENTER(); |
| 3571 | tmp = ((Can *)hw)->IR.reg; |
| 3572 | tmp &= ~CAN_IR_TCF; |
| 3573 | tmp |= value << CAN_IR_TCF_Pos; |
| 3574 | ((Can *)hw)->IR.reg = tmp; |
| 3575 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3576 | } |
| 3577 | |
| 3578 | static inline void hri_can_clear_IR_TCF_bit(const void *const hw) |
| 3579 | { |
| 3580 | CAN_CRITICAL_SECTION_ENTER(); |
| 3581 | ((Can *)hw)->IR.reg &= ~CAN_IR_TCF; |
| 3582 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3583 | } |
| 3584 | |
| 3585 | static inline void hri_can_toggle_IR_TCF_bit(const void *const hw) |
| 3586 | { |
| 3587 | CAN_CRITICAL_SECTION_ENTER(); |
| 3588 | ((Can *)hw)->IR.reg ^= CAN_IR_TCF; |
| 3589 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3590 | } |
| 3591 | |
| 3592 | static inline void hri_can_set_IR_TFE_bit(const void *const hw) |
| 3593 | { |
| 3594 | CAN_CRITICAL_SECTION_ENTER(); |
| 3595 | ((Can *)hw)->IR.reg |= CAN_IR_TFE; |
| 3596 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3597 | } |
| 3598 | |
| 3599 | static inline bool hri_can_get_IR_TFE_bit(const void *const hw) |
| 3600 | { |
| 3601 | uint32_t tmp; |
| 3602 | tmp = ((Can *)hw)->IR.reg; |
| 3603 | tmp = (tmp & CAN_IR_TFE) >> CAN_IR_TFE_Pos; |
| 3604 | return (bool)tmp; |
| 3605 | } |
| 3606 | |
| 3607 | static inline void hri_can_write_IR_TFE_bit(const void *const hw, bool value) |
| 3608 | { |
| 3609 | uint32_t tmp; |
| 3610 | CAN_CRITICAL_SECTION_ENTER(); |
| 3611 | tmp = ((Can *)hw)->IR.reg; |
| 3612 | tmp &= ~CAN_IR_TFE; |
| 3613 | tmp |= value << CAN_IR_TFE_Pos; |
| 3614 | ((Can *)hw)->IR.reg = tmp; |
| 3615 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3616 | } |
| 3617 | |
| 3618 | static inline void hri_can_clear_IR_TFE_bit(const void *const hw) |
| 3619 | { |
| 3620 | CAN_CRITICAL_SECTION_ENTER(); |
| 3621 | ((Can *)hw)->IR.reg &= ~CAN_IR_TFE; |
| 3622 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3623 | } |
| 3624 | |
| 3625 | static inline void hri_can_toggle_IR_TFE_bit(const void *const hw) |
| 3626 | { |
| 3627 | CAN_CRITICAL_SECTION_ENTER(); |
| 3628 | ((Can *)hw)->IR.reg ^= CAN_IR_TFE; |
| 3629 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3630 | } |
| 3631 | |
| 3632 | static inline void hri_can_set_IR_TEFN_bit(const void *const hw) |
| 3633 | { |
| 3634 | CAN_CRITICAL_SECTION_ENTER(); |
| 3635 | ((Can *)hw)->IR.reg |= CAN_IR_TEFN; |
| 3636 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3637 | } |
| 3638 | |
| 3639 | static inline bool hri_can_get_IR_TEFN_bit(const void *const hw) |
| 3640 | { |
| 3641 | uint32_t tmp; |
| 3642 | tmp = ((Can *)hw)->IR.reg; |
| 3643 | tmp = (tmp & CAN_IR_TEFN) >> CAN_IR_TEFN_Pos; |
| 3644 | return (bool)tmp; |
| 3645 | } |
| 3646 | |
| 3647 | static inline void hri_can_write_IR_TEFN_bit(const void *const hw, bool value) |
| 3648 | { |
| 3649 | uint32_t tmp; |
| 3650 | CAN_CRITICAL_SECTION_ENTER(); |
| 3651 | tmp = ((Can *)hw)->IR.reg; |
| 3652 | tmp &= ~CAN_IR_TEFN; |
| 3653 | tmp |= value << CAN_IR_TEFN_Pos; |
| 3654 | ((Can *)hw)->IR.reg = tmp; |
| 3655 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3656 | } |
| 3657 | |
| 3658 | static inline void hri_can_clear_IR_TEFN_bit(const void *const hw) |
| 3659 | { |
| 3660 | CAN_CRITICAL_SECTION_ENTER(); |
| 3661 | ((Can *)hw)->IR.reg &= ~CAN_IR_TEFN; |
| 3662 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3663 | } |
| 3664 | |
| 3665 | static inline void hri_can_toggle_IR_TEFN_bit(const void *const hw) |
| 3666 | { |
| 3667 | CAN_CRITICAL_SECTION_ENTER(); |
| 3668 | ((Can *)hw)->IR.reg ^= CAN_IR_TEFN; |
| 3669 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3670 | } |
| 3671 | |
| 3672 | static inline void hri_can_set_IR_TEFW_bit(const void *const hw) |
| 3673 | { |
| 3674 | CAN_CRITICAL_SECTION_ENTER(); |
| 3675 | ((Can *)hw)->IR.reg |= CAN_IR_TEFW; |
| 3676 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3677 | } |
| 3678 | |
| 3679 | static inline bool hri_can_get_IR_TEFW_bit(const void *const hw) |
| 3680 | { |
| 3681 | uint32_t tmp; |
| 3682 | tmp = ((Can *)hw)->IR.reg; |
| 3683 | tmp = (tmp & CAN_IR_TEFW) >> CAN_IR_TEFW_Pos; |
| 3684 | return (bool)tmp; |
| 3685 | } |
| 3686 | |
| 3687 | static inline void hri_can_write_IR_TEFW_bit(const void *const hw, bool value) |
| 3688 | { |
| 3689 | uint32_t tmp; |
| 3690 | CAN_CRITICAL_SECTION_ENTER(); |
| 3691 | tmp = ((Can *)hw)->IR.reg; |
| 3692 | tmp &= ~CAN_IR_TEFW; |
| 3693 | tmp |= value << CAN_IR_TEFW_Pos; |
| 3694 | ((Can *)hw)->IR.reg = tmp; |
| 3695 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3696 | } |
| 3697 | |
| 3698 | static inline void hri_can_clear_IR_TEFW_bit(const void *const hw) |
| 3699 | { |
| 3700 | CAN_CRITICAL_SECTION_ENTER(); |
| 3701 | ((Can *)hw)->IR.reg &= ~CAN_IR_TEFW; |
| 3702 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3703 | } |
| 3704 | |
| 3705 | static inline void hri_can_toggle_IR_TEFW_bit(const void *const hw) |
| 3706 | { |
| 3707 | CAN_CRITICAL_SECTION_ENTER(); |
| 3708 | ((Can *)hw)->IR.reg ^= CAN_IR_TEFW; |
| 3709 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3710 | } |
| 3711 | |
| 3712 | static inline void hri_can_set_IR_TEFF_bit(const void *const hw) |
| 3713 | { |
| 3714 | CAN_CRITICAL_SECTION_ENTER(); |
| 3715 | ((Can *)hw)->IR.reg |= CAN_IR_TEFF; |
| 3716 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3717 | } |
| 3718 | |
| 3719 | static inline bool hri_can_get_IR_TEFF_bit(const void *const hw) |
| 3720 | { |
| 3721 | uint32_t tmp; |
| 3722 | tmp = ((Can *)hw)->IR.reg; |
| 3723 | tmp = (tmp & CAN_IR_TEFF) >> CAN_IR_TEFF_Pos; |
| 3724 | return (bool)tmp; |
| 3725 | } |
| 3726 | |
| 3727 | static inline void hri_can_write_IR_TEFF_bit(const void *const hw, bool value) |
| 3728 | { |
| 3729 | uint32_t tmp; |
| 3730 | CAN_CRITICAL_SECTION_ENTER(); |
| 3731 | tmp = ((Can *)hw)->IR.reg; |
| 3732 | tmp &= ~CAN_IR_TEFF; |
| 3733 | tmp |= value << CAN_IR_TEFF_Pos; |
| 3734 | ((Can *)hw)->IR.reg = tmp; |
| 3735 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3736 | } |
| 3737 | |
| 3738 | static inline void hri_can_clear_IR_TEFF_bit(const void *const hw) |
| 3739 | { |
| 3740 | CAN_CRITICAL_SECTION_ENTER(); |
| 3741 | ((Can *)hw)->IR.reg &= ~CAN_IR_TEFF; |
| 3742 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3743 | } |
| 3744 | |
| 3745 | static inline void hri_can_toggle_IR_TEFF_bit(const void *const hw) |
| 3746 | { |
| 3747 | CAN_CRITICAL_SECTION_ENTER(); |
| 3748 | ((Can *)hw)->IR.reg ^= CAN_IR_TEFF; |
| 3749 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3750 | } |
| 3751 | |
| 3752 | static inline void hri_can_set_IR_TEFL_bit(const void *const hw) |
| 3753 | { |
| 3754 | CAN_CRITICAL_SECTION_ENTER(); |
| 3755 | ((Can *)hw)->IR.reg |= CAN_IR_TEFL; |
| 3756 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3757 | } |
| 3758 | |
| 3759 | static inline bool hri_can_get_IR_TEFL_bit(const void *const hw) |
| 3760 | { |
| 3761 | uint32_t tmp; |
| 3762 | tmp = ((Can *)hw)->IR.reg; |
| 3763 | tmp = (tmp & CAN_IR_TEFL) >> CAN_IR_TEFL_Pos; |
| 3764 | return (bool)tmp; |
| 3765 | } |
| 3766 | |
| 3767 | static inline void hri_can_write_IR_TEFL_bit(const void *const hw, bool value) |
| 3768 | { |
| 3769 | uint32_t tmp; |
| 3770 | CAN_CRITICAL_SECTION_ENTER(); |
| 3771 | tmp = ((Can *)hw)->IR.reg; |
| 3772 | tmp &= ~CAN_IR_TEFL; |
| 3773 | tmp |= value << CAN_IR_TEFL_Pos; |
| 3774 | ((Can *)hw)->IR.reg = tmp; |
| 3775 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3776 | } |
| 3777 | |
| 3778 | static inline void hri_can_clear_IR_TEFL_bit(const void *const hw) |
| 3779 | { |
| 3780 | CAN_CRITICAL_SECTION_ENTER(); |
| 3781 | ((Can *)hw)->IR.reg &= ~CAN_IR_TEFL; |
| 3782 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3783 | } |
| 3784 | |
| 3785 | static inline void hri_can_toggle_IR_TEFL_bit(const void *const hw) |
| 3786 | { |
| 3787 | CAN_CRITICAL_SECTION_ENTER(); |
| 3788 | ((Can *)hw)->IR.reg ^= CAN_IR_TEFL; |
| 3789 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3790 | } |
| 3791 | |
| 3792 | static inline void hri_can_set_IR_TSW_bit(const void *const hw) |
| 3793 | { |
| 3794 | CAN_CRITICAL_SECTION_ENTER(); |
| 3795 | ((Can *)hw)->IR.reg |= CAN_IR_TSW; |
| 3796 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3797 | } |
| 3798 | |
| 3799 | static inline bool hri_can_get_IR_TSW_bit(const void *const hw) |
| 3800 | { |
| 3801 | uint32_t tmp; |
| 3802 | tmp = ((Can *)hw)->IR.reg; |
| 3803 | tmp = (tmp & CAN_IR_TSW) >> CAN_IR_TSW_Pos; |
| 3804 | return (bool)tmp; |
| 3805 | } |
| 3806 | |
| 3807 | static inline void hri_can_write_IR_TSW_bit(const void *const hw, bool value) |
| 3808 | { |
| 3809 | uint32_t tmp; |
| 3810 | CAN_CRITICAL_SECTION_ENTER(); |
| 3811 | tmp = ((Can *)hw)->IR.reg; |
| 3812 | tmp &= ~CAN_IR_TSW; |
| 3813 | tmp |= value << CAN_IR_TSW_Pos; |
| 3814 | ((Can *)hw)->IR.reg = tmp; |
| 3815 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3816 | } |
| 3817 | |
| 3818 | static inline void hri_can_clear_IR_TSW_bit(const void *const hw) |
| 3819 | { |
| 3820 | CAN_CRITICAL_SECTION_ENTER(); |
| 3821 | ((Can *)hw)->IR.reg &= ~CAN_IR_TSW; |
| 3822 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3823 | } |
| 3824 | |
| 3825 | static inline void hri_can_toggle_IR_TSW_bit(const void *const hw) |
| 3826 | { |
| 3827 | CAN_CRITICAL_SECTION_ENTER(); |
| 3828 | ((Can *)hw)->IR.reg ^= CAN_IR_TSW; |
| 3829 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3830 | } |
| 3831 | |
| 3832 | static inline void hri_can_set_IR_MRAF_bit(const void *const hw) |
| 3833 | { |
| 3834 | CAN_CRITICAL_SECTION_ENTER(); |
| 3835 | ((Can *)hw)->IR.reg |= CAN_IR_MRAF; |
| 3836 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3837 | } |
| 3838 | |
| 3839 | static inline bool hri_can_get_IR_MRAF_bit(const void *const hw) |
| 3840 | { |
| 3841 | uint32_t tmp; |
| 3842 | tmp = ((Can *)hw)->IR.reg; |
| 3843 | tmp = (tmp & CAN_IR_MRAF) >> CAN_IR_MRAF_Pos; |
| 3844 | return (bool)tmp; |
| 3845 | } |
| 3846 | |
| 3847 | static inline void hri_can_write_IR_MRAF_bit(const void *const hw, bool value) |
| 3848 | { |
| 3849 | uint32_t tmp; |
| 3850 | CAN_CRITICAL_SECTION_ENTER(); |
| 3851 | tmp = ((Can *)hw)->IR.reg; |
| 3852 | tmp &= ~CAN_IR_MRAF; |
| 3853 | tmp |= value << CAN_IR_MRAF_Pos; |
| 3854 | ((Can *)hw)->IR.reg = tmp; |
| 3855 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3856 | } |
| 3857 | |
| 3858 | static inline void hri_can_clear_IR_MRAF_bit(const void *const hw) |
| 3859 | { |
| 3860 | CAN_CRITICAL_SECTION_ENTER(); |
| 3861 | ((Can *)hw)->IR.reg &= ~CAN_IR_MRAF; |
| 3862 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3863 | } |
| 3864 | |
| 3865 | static inline void hri_can_toggle_IR_MRAF_bit(const void *const hw) |
| 3866 | { |
| 3867 | CAN_CRITICAL_SECTION_ENTER(); |
| 3868 | ((Can *)hw)->IR.reg ^= CAN_IR_MRAF; |
| 3869 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3870 | } |
| 3871 | |
| 3872 | static inline void hri_can_set_IR_TOO_bit(const void *const hw) |
| 3873 | { |
| 3874 | CAN_CRITICAL_SECTION_ENTER(); |
| 3875 | ((Can *)hw)->IR.reg |= CAN_IR_TOO; |
| 3876 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3877 | } |
| 3878 | |
| 3879 | static inline bool hri_can_get_IR_TOO_bit(const void *const hw) |
| 3880 | { |
| 3881 | uint32_t tmp; |
| 3882 | tmp = ((Can *)hw)->IR.reg; |
| 3883 | tmp = (tmp & CAN_IR_TOO) >> CAN_IR_TOO_Pos; |
| 3884 | return (bool)tmp; |
| 3885 | } |
| 3886 | |
| 3887 | static inline void hri_can_write_IR_TOO_bit(const void *const hw, bool value) |
| 3888 | { |
| 3889 | uint32_t tmp; |
| 3890 | CAN_CRITICAL_SECTION_ENTER(); |
| 3891 | tmp = ((Can *)hw)->IR.reg; |
| 3892 | tmp &= ~CAN_IR_TOO; |
| 3893 | tmp |= value << CAN_IR_TOO_Pos; |
| 3894 | ((Can *)hw)->IR.reg = tmp; |
| 3895 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3896 | } |
| 3897 | |
| 3898 | static inline void hri_can_clear_IR_TOO_bit(const void *const hw) |
| 3899 | { |
| 3900 | CAN_CRITICAL_SECTION_ENTER(); |
| 3901 | ((Can *)hw)->IR.reg &= ~CAN_IR_TOO; |
| 3902 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3903 | } |
| 3904 | |
| 3905 | static inline void hri_can_toggle_IR_TOO_bit(const void *const hw) |
| 3906 | { |
| 3907 | CAN_CRITICAL_SECTION_ENTER(); |
| 3908 | ((Can *)hw)->IR.reg ^= CAN_IR_TOO; |
| 3909 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3910 | } |
| 3911 | |
| 3912 | static inline void hri_can_set_IR_DRX_bit(const void *const hw) |
| 3913 | { |
| 3914 | CAN_CRITICAL_SECTION_ENTER(); |
| 3915 | ((Can *)hw)->IR.reg |= CAN_IR_DRX; |
| 3916 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3917 | } |
| 3918 | |
| 3919 | static inline bool hri_can_get_IR_DRX_bit(const void *const hw) |
| 3920 | { |
| 3921 | uint32_t tmp; |
| 3922 | tmp = ((Can *)hw)->IR.reg; |
| 3923 | tmp = (tmp & CAN_IR_DRX) >> CAN_IR_DRX_Pos; |
| 3924 | return (bool)tmp; |
| 3925 | } |
| 3926 | |
| 3927 | static inline void hri_can_write_IR_DRX_bit(const void *const hw, bool value) |
| 3928 | { |
| 3929 | uint32_t tmp; |
| 3930 | CAN_CRITICAL_SECTION_ENTER(); |
| 3931 | tmp = ((Can *)hw)->IR.reg; |
| 3932 | tmp &= ~CAN_IR_DRX; |
| 3933 | tmp |= value << CAN_IR_DRX_Pos; |
| 3934 | ((Can *)hw)->IR.reg = tmp; |
| 3935 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3936 | } |
| 3937 | |
| 3938 | static inline void hri_can_clear_IR_DRX_bit(const void *const hw) |
| 3939 | { |
| 3940 | CAN_CRITICAL_SECTION_ENTER(); |
| 3941 | ((Can *)hw)->IR.reg &= ~CAN_IR_DRX; |
| 3942 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3943 | } |
| 3944 | |
| 3945 | static inline void hri_can_toggle_IR_DRX_bit(const void *const hw) |
| 3946 | { |
| 3947 | CAN_CRITICAL_SECTION_ENTER(); |
| 3948 | ((Can *)hw)->IR.reg ^= CAN_IR_DRX; |
| 3949 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3950 | } |
| 3951 | |
| 3952 | static inline void hri_can_set_IR_BEC_bit(const void *const hw) |
| 3953 | { |
| 3954 | CAN_CRITICAL_SECTION_ENTER(); |
| 3955 | ((Can *)hw)->IR.reg |= CAN_IR_BEC; |
| 3956 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3957 | } |
| 3958 | |
| 3959 | static inline bool hri_can_get_IR_BEC_bit(const void *const hw) |
| 3960 | { |
| 3961 | uint32_t tmp; |
| 3962 | tmp = ((Can *)hw)->IR.reg; |
| 3963 | tmp = (tmp & CAN_IR_BEC) >> CAN_IR_BEC_Pos; |
| 3964 | return (bool)tmp; |
| 3965 | } |
| 3966 | |
| 3967 | static inline void hri_can_write_IR_BEC_bit(const void *const hw, bool value) |
| 3968 | { |
| 3969 | uint32_t tmp; |
| 3970 | CAN_CRITICAL_SECTION_ENTER(); |
| 3971 | tmp = ((Can *)hw)->IR.reg; |
| 3972 | tmp &= ~CAN_IR_BEC; |
| 3973 | tmp |= value << CAN_IR_BEC_Pos; |
| 3974 | ((Can *)hw)->IR.reg = tmp; |
| 3975 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3976 | } |
| 3977 | |
| 3978 | static inline void hri_can_clear_IR_BEC_bit(const void *const hw) |
| 3979 | { |
| 3980 | CAN_CRITICAL_SECTION_ENTER(); |
| 3981 | ((Can *)hw)->IR.reg &= ~CAN_IR_BEC; |
| 3982 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3983 | } |
| 3984 | |
| 3985 | static inline void hri_can_toggle_IR_BEC_bit(const void *const hw) |
| 3986 | { |
| 3987 | CAN_CRITICAL_SECTION_ENTER(); |
| 3988 | ((Can *)hw)->IR.reg ^= CAN_IR_BEC; |
| 3989 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3990 | } |
| 3991 | |
| 3992 | static inline void hri_can_set_IR_BEU_bit(const void *const hw) |
| 3993 | { |
| 3994 | CAN_CRITICAL_SECTION_ENTER(); |
| 3995 | ((Can *)hw)->IR.reg |= CAN_IR_BEU; |
| 3996 | CAN_CRITICAL_SECTION_LEAVE(); |
| 3997 | } |
| 3998 | |
| 3999 | static inline bool hri_can_get_IR_BEU_bit(const void *const hw) |
| 4000 | { |
| 4001 | uint32_t tmp; |
| 4002 | tmp = ((Can *)hw)->IR.reg; |
| 4003 | tmp = (tmp & CAN_IR_BEU) >> CAN_IR_BEU_Pos; |
| 4004 | return (bool)tmp; |
| 4005 | } |
| 4006 | |
| 4007 | static inline void hri_can_write_IR_BEU_bit(const void *const hw, bool value) |
| 4008 | { |
| 4009 | uint32_t tmp; |
| 4010 | CAN_CRITICAL_SECTION_ENTER(); |
| 4011 | tmp = ((Can *)hw)->IR.reg; |
| 4012 | tmp &= ~CAN_IR_BEU; |
| 4013 | tmp |= value << CAN_IR_BEU_Pos; |
| 4014 | ((Can *)hw)->IR.reg = tmp; |
| 4015 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4016 | } |
| 4017 | |
| 4018 | static inline void hri_can_clear_IR_BEU_bit(const void *const hw) |
| 4019 | { |
| 4020 | CAN_CRITICAL_SECTION_ENTER(); |
| 4021 | ((Can *)hw)->IR.reg &= ~CAN_IR_BEU; |
| 4022 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4023 | } |
| 4024 | |
| 4025 | static inline void hri_can_toggle_IR_BEU_bit(const void *const hw) |
| 4026 | { |
| 4027 | CAN_CRITICAL_SECTION_ENTER(); |
| 4028 | ((Can *)hw)->IR.reg ^= CAN_IR_BEU; |
| 4029 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4030 | } |
| 4031 | |
| 4032 | static inline void hri_can_set_IR_ELO_bit(const void *const hw) |
| 4033 | { |
| 4034 | CAN_CRITICAL_SECTION_ENTER(); |
| 4035 | ((Can *)hw)->IR.reg |= CAN_IR_ELO; |
| 4036 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4037 | } |
| 4038 | |
| 4039 | static inline bool hri_can_get_IR_ELO_bit(const void *const hw) |
| 4040 | { |
| 4041 | uint32_t tmp; |
| 4042 | tmp = ((Can *)hw)->IR.reg; |
| 4043 | tmp = (tmp & CAN_IR_ELO) >> CAN_IR_ELO_Pos; |
| 4044 | return (bool)tmp; |
| 4045 | } |
| 4046 | |
| 4047 | static inline void hri_can_write_IR_ELO_bit(const void *const hw, bool value) |
| 4048 | { |
| 4049 | uint32_t tmp; |
| 4050 | CAN_CRITICAL_SECTION_ENTER(); |
| 4051 | tmp = ((Can *)hw)->IR.reg; |
| 4052 | tmp &= ~CAN_IR_ELO; |
| 4053 | tmp |= value << CAN_IR_ELO_Pos; |
| 4054 | ((Can *)hw)->IR.reg = tmp; |
| 4055 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4056 | } |
| 4057 | |
| 4058 | static inline void hri_can_clear_IR_ELO_bit(const void *const hw) |
| 4059 | { |
| 4060 | CAN_CRITICAL_SECTION_ENTER(); |
| 4061 | ((Can *)hw)->IR.reg &= ~CAN_IR_ELO; |
| 4062 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4063 | } |
| 4064 | |
| 4065 | static inline void hri_can_toggle_IR_ELO_bit(const void *const hw) |
| 4066 | { |
| 4067 | CAN_CRITICAL_SECTION_ENTER(); |
| 4068 | ((Can *)hw)->IR.reg ^= CAN_IR_ELO; |
| 4069 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4070 | } |
| 4071 | |
| 4072 | static inline void hri_can_set_IR_EP_bit(const void *const hw) |
| 4073 | { |
| 4074 | CAN_CRITICAL_SECTION_ENTER(); |
| 4075 | ((Can *)hw)->IR.reg |= CAN_IR_EP; |
| 4076 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4077 | } |
| 4078 | |
| 4079 | static inline bool hri_can_get_IR_EP_bit(const void *const hw) |
| 4080 | { |
| 4081 | uint32_t tmp; |
| 4082 | tmp = ((Can *)hw)->IR.reg; |
| 4083 | tmp = (tmp & CAN_IR_EP) >> CAN_IR_EP_Pos; |
| 4084 | return (bool)tmp; |
| 4085 | } |
| 4086 | |
| 4087 | static inline void hri_can_write_IR_EP_bit(const void *const hw, bool value) |
| 4088 | { |
| 4089 | uint32_t tmp; |
| 4090 | CAN_CRITICAL_SECTION_ENTER(); |
| 4091 | tmp = ((Can *)hw)->IR.reg; |
| 4092 | tmp &= ~CAN_IR_EP; |
| 4093 | tmp |= value << CAN_IR_EP_Pos; |
| 4094 | ((Can *)hw)->IR.reg = tmp; |
| 4095 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4096 | } |
| 4097 | |
| 4098 | static inline void hri_can_clear_IR_EP_bit(const void *const hw) |
| 4099 | { |
| 4100 | CAN_CRITICAL_SECTION_ENTER(); |
| 4101 | ((Can *)hw)->IR.reg &= ~CAN_IR_EP; |
| 4102 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4103 | } |
| 4104 | |
| 4105 | static inline void hri_can_toggle_IR_EP_bit(const void *const hw) |
| 4106 | { |
| 4107 | CAN_CRITICAL_SECTION_ENTER(); |
| 4108 | ((Can *)hw)->IR.reg ^= CAN_IR_EP; |
| 4109 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4110 | } |
| 4111 | |
| 4112 | static inline void hri_can_set_IR_EW_bit(const void *const hw) |
| 4113 | { |
| 4114 | CAN_CRITICAL_SECTION_ENTER(); |
| 4115 | ((Can *)hw)->IR.reg |= CAN_IR_EW; |
| 4116 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4117 | } |
| 4118 | |
| 4119 | static inline bool hri_can_get_IR_EW_bit(const void *const hw) |
| 4120 | { |
| 4121 | uint32_t tmp; |
| 4122 | tmp = ((Can *)hw)->IR.reg; |
| 4123 | tmp = (tmp & CAN_IR_EW) >> CAN_IR_EW_Pos; |
| 4124 | return (bool)tmp; |
| 4125 | } |
| 4126 | |
| 4127 | static inline void hri_can_write_IR_EW_bit(const void *const hw, bool value) |
| 4128 | { |
| 4129 | uint32_t tmp; |
| 4130 | CAN_CRITICAL_SECTION_ENTER(); |
| 4131 | tmp = ((Can *)hw)->IR.reg; |
| 4132 | tmp &= ~CAN_IR_EW; |
| 4133 | tmp |= value << CAN_IR_EW_Pos; |
| 4134 | ((Can *)hw)->IR.reg = tmp; |
| 4135 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4136 | } |
| 4137 | |
| 4138 | static inline void hri_can_clear_IR_EW_bit(const void *const hw) |
| 4139 | { |
| 4140 | CAN_CRITICAL_SECTION_ENTER(); |
| 4141 | ((Can *)hw)->IR.reg &= ~CAN_IR_EW; |
| 4142 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4143 | } |
| 4144 | |
| 4145 | static inline void hri_can_toggle_IR_EW_bit(const void *const hw) |
| 4146 | { |
| 4147 | CAN_CRITICAL_SECTION_ENTER(); |
| 4148 | ((Can *)hw)->IR.reg ^= CAN_IR_EW; |
| 4149 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4150 | } |
| 4151 | |
| 4152 | static inline void hri_can_set_IR_BO_bit(const void *const hw) |
| 4153 | { |
| 4154 | CAN_CRITICAL_SECTION_ENTER(); |
| 4155 | ((Can *)hw)->IR.reg |= CAN_IR_BO; |
| 4156 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4157 | } |
| 4158 | |
| 4159 | static inline bool hri_can_get_IR_BO_bit(const void *const hw) |
| 4160 | { |
| 4161 | uint32_t tmp; |
| 4162 | tmp = ((Can *)hw)->IR.reg; |
| 4163 | tmp = (tmp & CAN_IR_BO) >> CAN_IR_BO_Pos; |
| 4164 | return (bool)tmp; |
| 4165 | } |
| 4166 | |
| 4167 | static inline void hri_can_write_IR_BO_bit(const void *const hw, bool value) |
| 4168 | { |
| 4169 | uint32_t tmp; |
| 4170 | CAN_CRITICAL_SECTION_ENTER(); |
| 4171 | tmp = ((Can *)hw)->IR.reg; |
| 4172 | tmp &= ~CAN_IR_BO; |
| 4173 | tmp |= value << CAN_IR_BO_Pos; |
| 4174 | ((Can *)hw)->IR.reg = tmp; |
| 4175 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4176 | } |
| 4177 | |
| 4178 | static inline void hri_can_clear_IR_BO_bit(const void *const hw) |
| 4179 | { |
| 4180 | CAN_CRITICAL_SECTION_ENTER(); |
| 4181 | ((Can *)hw)->IR.reg &= ~CAN_IR_BO; |
| 4182 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4183 | } |
| 4184 | |
| 4185 | static inline void hri_can_toggle_IR_BO_bit(const void *const hw) |
| 4186 | { |
| 4187 | CAN_CRITICAL_SECTION_ENTER(); |
| 4188 | ((Can *)hw)->IR.reg ^= CAN_IR_BO; |
| 4189 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4190 | } |
| 4191 | |
| 4192 | static inline void hri_can_set_IR_WDI_bit(const void *const hw) |
| 4193 | { |
| 4194 | CAN_CRITICAL_SECTION_ENTER(); |
| 4195 | ((Can *)hw)->IR.reg |= CAN_IR_WDI; |
| 4196 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4197 | } |
| 4198 | |
| 4199 | static inline bool hri_can_get_IR_WDI_bit(const void *const hw) |
| 4200 | { |
| 4201 | uint32_t tmp; |
| 4202 | tmp = ((Can *)hw)->IR.reg; |
| 4203 | tmp = (tmp & CAN_IR_WDI) >> CAN_IR_WDI_Pos; |
| 4204 | return (bool)tmp; |
| 4205 | } |
| 4206 | |
| 4207 | static inline void hri_can_write_IR_WDI_bit(const void *const hw, bool value) |
| 4208 | { |
| 4209 | uint32_t tmp; |
| 4210 | CAN_CRITICAL_SECTION_ENTER(); |
| 4211 | tmp = ((Can *)hw)->IR.reg; |
| 4212 | tmp &= ~CAN_IR_WDI; |
| 4213 | tmp |= value << CAN_IR_WDI_Pos; |
| 4214 | ((Can *)hw)->IR.reg = tmp; |
| 4215 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4216 | } |
| 4217 | |
| 4218 | static inline void hri_can_clear_IR_WDI_bit(const void *const hw) |
| 4219 | { |
| 4220 | CAN_CRITICAL_SECTION_ENTER(); |
| 4221 | ((Can *)hw)->IR.reg &= ~CAN_IR_WDI; |
| 4222 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4223 | } |
| 4224 | |
| 4225 | static inline void hri_can_toggle_IR_WDI_bit(const void *const hw) |
| 4226 | { |
| 4227 | CAN_CRITICAL_SECTION_ENTER(); |
| 4228 | ((Can *)hw)->IR.reg ^= CAN_IR_WDI; |
| 4229 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4230 | } |
| 4231 | |
| 4232 | static inline void hri_can_set_IR_PEA_bit(const void *const hw) |
| 4233 | { |
| 4234 | CAN_CRITICAL_SECTION_ENTER(); |
| 4235 | ((Can *)hw)->IR.reg |= CAN_IR_PEA; |
| 4236 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4237 | } |
| 4238 | |
| 4239 | static inline bool hri_can_get_IR_PEA_bit(const void *const hw) |
| 4240 | { |
| 4241 | uint32_t tmp; |
| 4242 | tmp = ((Can *)hw)->IR.reg; |
| 4243 | tmp = (tmp & CAN_IR_PEA) >> CAN_IR_PEA_Pos; |
| 4244 | return (bool)tmp; |
| 4245 | } |
| 4246 | |
| 4247 | static inline void hri_can_write_IR_PEA_bit(const void *const hw, bool value) |
| 4248 | { |
| 4249 | uint32_t tmp; |
| 4250 | CAN_CRITICAL_SECTION_ENTER(); |
| 4251 | tmp = ((Can *)hw)->IR.reg; |
| 4252 | tmp &= ~CAN_IR_PEA; |
| 4253 | tmp |= value << CAN_IR_PEA_Pos; |
| 4254 | ((Can *)hw)->IR.reg = tmp; |
| 4255 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4256 | } |
| 4257 | |
| 4258 | static inline void hri_can_clear_IR_PEA_bit(const void *const hw) |
| 4259 | { |
| 4260 | CAN_CRITICAL_SECTION_ENTER(); |
| 4261 | ((Can *)hw)->IR.reg &= ~CAN_IR_PEA; |
| 4262 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4263 | } |
| 4264 | |
| 4265 | static inline void hri_can_toggle_IR_PEA_bit(const void *const hw) |
| 4266 | { |
| 4267 | CAN_CRITICAL_SECTION_ENTER(); |
| 4268 | ((Can *)hw)->IR.reg ^= CAN_IR_PEA; |
| 4269 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4270 | } |
| 4271 | |
| 4272 | static inline void hri_can_set_IR_PED_bit(const void *const hw) |
| 4273 | { |
| 4274 | CAN_CRITICAL_SECTION_ENTER(); |
| 4275 | ((Can *)hw)->IR.reg |= CAN_IR_PED; |
| 4276 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4277 | } |
| 4278 | |
| 4279 | static inline bool hri_can_get_IR_PED_bit(const void *const hw) |
| 4280 | { |
| 4281 | uint32_t tmp; |
| 4282 | tmp = ((Can *)hw)->IR.reg; |
| 4283 | tmp = (tmp & CAN_IR_PED) >> CAN_IR_PED_Pos; |
| 4284 | return (bool)tmp; |
| 4285 | } |
| 4286 | |
| 4287 | static inline void hri_can_write_IR_PED_bit(const void *const hw, bool value) |
| 4288 | { |
| 4289 | uint32_t tmp; |
| 4290 | CAN_CRITICAL_SECTION_ENTER(); |
| 4291 | tmp = ((Can *)hw)->IR.reg; |
| 4292 | tmp &= ~CAN_IR_PED; |
| 4293 | tmp |= value << CAN_IR_PED_Pos; |
| 4294 | ((Can *)hw)->IR.reg = tmp; |
| 4295 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4296 | } |
| 4297 | |
| 4298 | static inline void hri_can_clear_IR_PED_bit(const void *const hw) |
| 4299 | { |
| 4300 | CAN_CRITICAL_SECTION_ENTER(); |
| 4301 | ((Can *)hw)->IR.reg &= ~CAN_IR_PED; |
| 4302 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4303 | } |
| 4304 | |
| 4305 | static inline void hri_can_toggle_IR_PED_bit(const void *const hw) |
| 4306 | { |
| 4307 | CAN_CRITICAL_SECTION_ENTER(); |
| 4308 | ((Can *)hw)->IR.reg ^= CAN_IR_PED; |
| 4309 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4310 | } |
| 4311 | |
| 4312 | static inline void hri_can_set_IR_ARA_bit(const void *const hw) |
| 4313 | { |
| 4314 | CAN_CRITICAL_SECTION_ENTER(); |
| 4315 | ((Can *)hw)->IR.reg |= CAN_IR_ARA; |
| 4316 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4317 | } |
| 4318 | |
| 4319 | static inline bool hri_can_get_IR_ARA_bit(const void *const hw) |
| 4320 | { |
| 4321 | uint32_t tmp; |
| 4322 | tmp = ((Can *)hw)->IR.reg; |
| 4323 | tmp = (tmp & CAN_IR_ARA) >> CAN_IR_ARA_Pos; |
| 4324 | return (bool)tmp; |
| 4325 | } |
| 4326 | |
| 4327 | static inline void hri_can_write_IR_ARA_bit(const void *const hw, bool value) |
| 4328 | { |
| 4329 | uint32_t tmp; |
| 4330 | CAN_CRITICAL_SECTION_ENTER(); |
| 4331 | tmp = ((Can *)hw)->IR.reg; |
| 4332 | tmp &= ~CAN_IR_ARA; |
| 4333 | tmp |= value << CAN_IR_ARA_Pos; |
| 4334 | ((Can *)hw)->IR.reg = tmp; |
| 4335 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4336 | } |
| 4337 | |
| 4338 | static inline void hri_can_clear_IR_ARA_bit(const void *const hw) |
| 4339 | { |
| 4340 | CAN_CRITICAL_SECTION_ENTER(); |
| 4341 | ((Can *)hw)->IR.reg &= ~CAN_IR_ARA; |
| 4342 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4343 | } |
| 4344 | |
| 4345 | static inline void hri_can_toggle_IR_ARA_bit(const void *const hw) |
| 4346 | { |
| 4347 | CAN_CRITICAL_SECTION_ENTER(); |
| 4348 | ((Can *)hw)->IR.reg ^= CAN_IR_ARA; |
| 4349 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4350 | } |
| 4351 | |
| 4352 | static inline void hri_can_set_IR_reg(const void *const hw, hri_can_ir_reg_t mask) |
| 4353 | { |
| 4354 | CAN_CRITICAL_SECTION_ENTER(); |
| 4355 | ((Can *)hw)->IR.reg |= mask; |
| 4356 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4357 | } |
| 4358 | |
| 4359 | static inline hri_can_ir_reg_t hri_can_get_IR_reg(const void *const hw, hri_can_ir_reg_t mask) |
| 4360 | { |
| 4361 | uint32_t tmp; |
| 4362 | tmp = ((Can *)hw)->IR.reg; |
| 4363 | tmp &= mask; |
| 4364 | return tmp; |
| 4365 | } |
| 4366 | |
| 4367 | static inline void hri_can_write_IR_reg(const void *const hw, hri_can_ir_reg_t data) |
| 4368 | { |
| 4369 | CAN_CRITICAL_SECTION_ENTER(); |
| 4370 | ((Can *)hw)->IR.reg = data; |
| 4371 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4372 | } |
| 4373 | |
| 4374 | static inline void hri_can_clear_IR_reg(const void *const hw, hri_can_ir_reg_t mask) |
| 4375 | { |
| 4376 | CAN_CRITICAL_SECTION_ENTER(); |
| 4377 | ((Can *)hw)->IR.reg &= ~mask; |
| 4378 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4379 | } |
| 4380 | |
| 4381 | static inline void hri_can_toggle_IR_reg(const void *const hw, hri_can_ir_reg_t mask) |
| 4382 | { |
| 4383 | CAN_CRITICAL_SECTION_ENTER(); |
| 4384 | ((Can *)hw)->IR.reg ^= mask; |
| 4385 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4386 | } |
| 4387 | |
| 4388 | static inline hri_can_ir_reg_t hri_can_read_IR_reg(const void *const hw) |
| 4389 | { |
| 4390 | return ((Can *)hw)->IR.reg; |
| 4391 | } |
| 4392 | |
| 4393 | static inline void hri_can_set_IE_RF0NE_bit(const void *const hw) |
| 4394 | { |
| 4395 | CAN_CRITICAL_SECTION_ENTER(); |
| 4396 | ((Can *)hw)->IE.reg |= CAN_IE_RF0NE; |
| 4397 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4398 | } |
| 4399 | |
| 4400 | static inline bool hri_can_get_IE_RF0NE_bit(const void *const hw) |
| 4401 | { |
| 4402 | uint32_t tmp; |
| 4403 | tmp = ((Can *)hw)->IE.reg; |
| 4404 | tmp = (tmp & CAN_IE_RF0NE) >> CAN_IE_RF0NE_Pos; |
| 4405 | return (bool)tmp; |
| 4406 | } |
| 4407 | |
| 4408 | static inline void hri_can_write_IE_RF0NE_bit(const void *const hw, bool value) |
| 4409 | { |
| 4410 | uint32_t tmp; |
| 4411 | CAN_CRITICAL_SECTION_ENTER(); |
| 4412 | tmp = ((Can *)hw)->IE.reg; |
| 4413 | tmp &= ~CAN_IE_RF0NE; |
| 4414 | tmp |= value << CAN_IE_RF0NE_Pos; |
| 4415 | ((Can *)hw)->IE.reg = tmp; |
| 4416 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4417 | } |
| 4418 | |
| 4419 | static inline void hri_can_clear_IE_RF0NE_bit(const void *const hw) |
| 4420 | { |
| 4421 | CAN_CRITICAL_SECTION_ENTER(); |
| 4422 | ((Can *)hw)->IE.reg &= ~CAN_IE_RF0NE; |
| 4423 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4424 | } |
| 4425 | |
| 4426 | static inline void hri_can_toggle_IE_RF0NE_bit(const void *const hw) |
| 4427 | { |
| 4428 | CAN_CRITICAL_SECTION_ENTER(); |
| 4429 | ((Can *)hw)->IE.reg ^= CAN_IE_RF0NE; |
| 4430 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4431 | } |
| 4432 | |
| 4433 | static inline void hri_can_set_IE_RF0WE_bit(const void *const hw) |
| 4434 | { |
| 4435 | CAN_CRITICAL_SECTION_ENTER(); |
| 4436 | ((Can *)hw)->IE.reg |= CAN_IE_RF0WE; |
| 4437 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4438 | } |
| 4439 | |
| 4440 | static inline bool hri_can_get_IE_RF0WE_bit(const void *const hw) |
| 4441 | { |
| 4442 | uint32_t tmp; |
| 4443 | tmp = ((Can *)hw)->IE.reg; |
| 4444 | tmp = (tmp & CAN_IE_RF0WE) >> CAN_IE_RF0WE_Pos; |
| 4445 | return (bool)tmp; |
| 4446 | } |
| 4447 | |
| 4448 | static inline void hri_can_write_IE_RF0WE_bit(const void *const hw, bool value) |
| 4449 | { |
| 4450 | uint32_t tmp; |
| 4451 | CAN_CRITICAL_SECTION_ENTER(); |
| 4452 | tmp = ((Can *)hw)->IE.reg; |
| 4453 | tmp &= ~CAN_IE_RF0WE; |
| 4454 | tmp |= value << CAN_IE_RF0WE_Pos; |
| 4455 | ((Can *)hw)->IE.reg = tmp; |
| 4456 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4457 | } |
| 4458 | |
| 4459 | static inline void hri_can_clear_IE_RF0WE_bit(const void *const hw) |
| 4460 | { |
| 4461 | CAN_CRITICAL_SECTION_ENTER(); |
| 4462 | ((Can *)hw)->IE.reg &= ~CAN_IE_RF0WE; |
| 4463 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4464 | } |
| 4465 | |
| 4466 | static inline void hri_can_toggle_IE_RF0WE_bit(const void *const hw) |
| 4467 | { |
| 4468 | CAN_CRITICAL_SECTION_ENTER(); |
| 4469 | ((Can *)hw)->IE.reg ^= CAN_IE_RF0WE; |
| 4470 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4471 | } |
| 4472 | |
| 4473 | static inline void hri_can_set_IE_RF0FE_bit(const void *const hw) |
| 4474 | { |
| 4475 | CAN_CRITICAL_SECTION_ENTER(); |
| 4476 | ((Can *)hw)->IE.reg |= CAN_IE_RF0FE; |
| 4477 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4478 | } |
| 4479 | |
| 4480 | static inline bool hri_can_get_IE_RF0FE_bit(const void *const hw) |
| 4481 | { |
| 4482 | uint32_t tmp; |
| 4483 | tmp = ((Can *)hw)->IE.reg; |
| 4484 | tmp = (tmp & CAN_IE_RF0FE) >> CAN_IE_RF0FE_Pos; |
| 4485 | return (bool)tmp; |
| 4486 | } |
| 4487 | |
| 4488 | static inline void hri_can_write_IE_RF0FE_bit(const void *const hw, bool value) |
| 4489 | { |
| 4490 | uint32_t tmp; |
| 4491 | CAN_CRITICAL_SECTION_ENTER(); |
| 4492 | tmp = ((Can *)hw)->IE.reg; |
| 4493 | tmp &= ~CAN_IE_RF0FE; |
| 4494 | tmp |= value << CAN_IE_RF0FE_Pos; |
| 4495 | ((Can *)hw)->IE.reg = tmp; |
| 4496 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4497 | } |
| 4498 | |
| 4499 | static inline void hri_can_clear_IE_RF0FE_bit(const void *const hw) |
| 4500 | { |
| 4501 | CAN_CRITICAL_SECTION_ENTER(); |
| 4502 | ((Can *)hw)->IE.reg &= ~CAN_IE_RF0FE; |
| 4503 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4504 | } |
| 4505 | |
| 4506 | static inline void hri_can_toggle_IE_RF0FE_bit(const void *const hw) |
| 4507 | { |
| 4508 | CAN_CRITICAL_SECTION_ENTER(); |
| 4509 | ((Can *)hw)->IE.reg ^= CAN_IE_RF0FE; |
| 4510 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4511 | } |
| 4512 | |
| 4513 | static inline void hri_can_set_IE_RF0LE_bit(const void *const hw) |
| 4514 | { |
| 4515 | CAN_CRITICAL_SECTION_ENTER(); |
| 4516 | ((Can *)hw)->IE.reg |= CAN_IE_RF0LE; |
| 4517 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4518 | } |
| 4519 | |
| 4520 | static inline bool hri_can_get_IE_RF0LE_bit(const void *const hw) |
| 4521 | { |
| 4522 | uint32_t tmp; |
| 4523 | tmp = ((Can *)hw)->IE.reg; |
| 4524 | tmp = (tmp & CAN_IE_RF0LE) >> CAN_IE_RF0LE_Pos; |
| 4525 | return (bool)tmp; |
| 4526 | } |
| 4527 | |
| 4528 | static inline void hri_can_write_IE_RF0LE_bit(const void *const hw, bool value) |
| 4529 | { |
| 4530 | uint32_t tmp; |
| 4531 | CAN_CRITICAL_SECTION_ENTER(); |
| 4532 | tmp = ((Can *)hw)->IE.reg; |
| 4533 | tmp &= ~CAN_IE_RF0LE; |
| 4534 | tmp |= value << CAN_IE_RF0LE_Pos; |
| 4535 | ((Can *)hw)->IE.reg = tmp; |
| 4536 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4537 | } |
| 4538 | |
| 4539 | static inline void hri_can_clear_IE_RF0LE_bit(const void *const hw) |
| 4540 | { |
| 4541 | CAN_CRITICAL_SECTION_ENTER(); |
| 4542 | ((Can *)hw)->IE.reg &= ~CAN_IE_RF0LE; |
| 4543 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4544 | } |
| 4545 | |
| 4546 | static inline void hri_can_toggle_IE_RF0LE_bit(const void *const hw) |
| 4547 | { |
| 4548 | CAN_CRITICAL_SECTION_ENTER(); |
| 4549 | ((Can *)hw)->IE.reg ^= CAN_IE_RF0LE; |
| 4550 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4551 | } |
| 4552 | |
| 4553 | static inline void hri_can_set_IE_RF1NE_bit(const void *const hw) |
| 4554 | { |
| 4555 | CAN_CRITICAL_SECTION_ENTER(); |
| 4556 | ((Can *)hw)->IE.reg |= CAN_IE_RF1NE; |
| 4557 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4558 | } |
| 4559 | |
| 4560 | static inline bool hri_can_get_IE_RF1NE_bit(const void *const hw) |
| 4561 | { |
| 4562 | uint32_t tmp; |
| 4563 | tmp = ((Can *)hw)->IE.reg; |
| 4564 | tmp = (tmp & CAN_IE_RF1NE) >> CAN_IE_RF1NE_Pos; |
| 4565 | return (bool)tmp; |
| 4566 | } |
| 4567 | |
| 4568 | static inline void hri_can_write_IE_RF1NE_bit(const void *const hw, bool value) |
| 4569 | { |
| 4570 | uint32_t tmp; |
| 4571 | CAN_CRITICAL_SECTION_ENTER(); |
| 4572 | tmp = ((Can *)hw)->IE.reg; |
| 4573 | tmp &= ~CAN_IE_RF1NE; |
| 4574 | tmp |= value << CAN_IE_RF1NE_Pos; |
| 4575 | ((Can *)hw)->IE.reg = tmp; |
| 4576 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4577 | } |
| 4578 | |
| 4579 | static inline void hri_can_clear_IE_RF1NE_bit(const void *const hw) |
| 4580 | { |
| 4581 | CAN_CRITICAL_SECTION_ENTER(); |
| 4582 | ((Can *)hw)->IE.reg &= ~CAN_IE_RF1NE; |
| 4583 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4584 | } |
| 4585 | |
| 4586 | static inline void hri_can_toggle_IE_RF1NE_bit(const void *const hw) |
| 4587 | { |
| 4588 | CAN_CRITICAL_SECTION_ENTER(); |
| 4589 | ((Can *)hw)->IE.reg ^= CAN_IE_RF1NE; |
| 4590 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4591 | } |
| 4592 | |
| 4593 | static inline void hri_can_set_IE_RF1WE_bit(const void *const hw) |
| 4594 | { |
| 4595 | CAN_CRITICAL_SECTION_ENTER(); |
| 4596 | ((Can *)hw)->IE.reg |= CAN_IE_RF1WE; |
| 4597 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4598 | } |
| 4599 | |
| 4600 | static inline bool hri_can_get_IE_RF1WE_bit(const void *const hw) |
| 4601 | { |
| 4602 | uint32_t tmp; |
| 4603 | tmp = ((Can *)hw)->IE.reg; |
| 4604 | tmp = (tmp & CAN_IE_RF1WE) >> CAN_IE_RF1WE_Pos; |
| 4605 | return (bool)tmp; |
| 4606 | } |
| 4607 | |
| 4608 | static inline void hri_can_write_IE_RF1WE_bit(const void *const hw, bool value) |
| 4609 | { |
| 4610 | uint32_t tmp; |
| 4611 | CAN_CRITICAL_SECTION_ENTER(); |
| 4612 | tmp = ((Can *)hw)->IE.reg; |
| 4613 | tmp &= ~CAN_IE_RF1WE; |
| 4614 | tmp |= value << CAN_IE_RF1WE_Pos; |
| 4615 | ((Can *)hw)->IE.reg = tmp; |
| 4616 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4617 | } |
| 4618 | |
| 4619 | static inline void hri_can_clear_IE_RF1WE_bit(const void *const hw) |
| 4620 | { |
| 4621 | CAN_CRITICAL_SECTION_ENTER(); |
| 4622 | ((Can *)hw)->IE.reg &= ~CAN_IE_RF1WE; |
| 4623 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4624 | } |
| 4625 | |
| 4626 | static inline void hri_can_toggle_IE_RF1WE_bit(const void *const hw) |
| 4627 | { |
| 4628 | CAN_CRITICAL_SECTION_ENTER(); |
| 4629 | ((Can *)hw)->IE.reg ^= CAN_IE_RF1WE; |
| 4630 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4631 | } |
| 4632 | |
| 4633 | static inline void hri_can_set_IE_RF1FE_bit(const void *const hw) |
| 4634 | { |
| 4635 | CAN_CRITICAL_SECTION_ENTER(); |
| 4636 | ((Can *)hw)->IE.reg |= CAN_IE_RF1FE; |
| 4637 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4638 | } |
| 4639 | |
| 4640 | static inline bool hri_can_get_IE_RF1FE_bit(const void *const hw) |
| 4641 | { |
| 4642 | uint32_t tmp; |
| 4643 | tmp = ((Can *)hw)->IE.reg; |
| 4644 | tmp = (tmp & CAN_IE_RF1FE) >> CAN_IE_RF1FE_Pos; |
| 4645 | return (bool)tmp; |
| 4646 | } |
| 4647 | |
| 4648 | static inline void hri_can_write_IE_RF1FE_bit(const void *const hw, bool value) |
| 4649 | { |
| 4650 | uint32_t tmp; |
| 4651 | CAN_CRITICAL_SECTION_ENTER(); |
| 4652 | tmp = ((Can *)hw)->IE.reg; |
| 4653 | tmp &= ~CAN_IE_RF1FE; |
| 4654 | tmp |= value << CAN_IE_RF1FE_Pos; |
| 4655 | ((Can *)hw)->IE.reg = tmp; |
| 4656 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4657 | } |
| 4658 | |
| 4659 | static inline void hri_can_clear_IE_RF1FE_bit(const void *const hw) |
| 4660 | { |
| 4661 | CAN_CRITICAL_SECTION_ENTER(); |
| 4662 | ((Can *)hw)->IE.reg &= ~CAN_IE_RF1FE; |
| 4663 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4664 | } |
| 4665 | |
| 4666 | static inline void hri_can_toggle_IE_RF1FE_bit(const void *const hw) |
| 4667 | { |
| 4668 | CAN_CRITICAL_SECTION_ENTER(); |
| 4669 | ((Can *)hw)->IE.reg ^= CAN_IE_RF1FE; |
| 4670 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4671 | } |
| 4672 | |
| 4673 | static inline void hri_can_set_IE_RF1LE_bit(const void *const hw) |
| 4674 | { |
| 4675 | CAN_CRITICAL_SECTION_ENTER(); |
| 4676 | ((Can *)hw)->IE.reg |= CAN_IE_RF1LE; |
| 4677 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4678 | } |
| 4679 | |
| 4680 | static inline bool hri_can_get_IE_RF1LE_bit(const void *const hw) |
| 4681 | { |
| 4682 | uint32_t tmp; |
| 4683 | tmp = ((Can *)hw)->IE.reg; |
| 4684 | tmp = (tmp & CAN_IE_RF1LE) >> CAN_IE_RF1LE_Pos; |
| 4685 | return (bool)tmp; |
| 4686 | } |
| 4687 | |
| 4688 | static inline void hri_can_write_IE_RF1LE_bit(const void *const hw, bool value) |
| 4689 | { |
| 4690 | uint32_t tmp; |
| 4691 | CAN_CRITICAL_SECTION_ENTER(); |
| 4692 | tmp = ((Can *)hw)->IE.reg; |
| 4693 | tmp &= ~CAN_IE_RF1LE; |
| 4694 | tmp |= value << CAN_IE_RF1LE_Pos; |
| 4695 | ((Can *)hw)->IE.reg = tmp; |
| 4696 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4697 | } |
| 4698 | |
| 4699 | static inline void hri_can_clear_IE_RF1LE_bit(const void *const hw) |
| 4700 | { |
| 4701 | CAN_CRITICAL_SECTION_ENTER(); |
| 4702 | ((Can *)hw)->IE.reg &= ~CAN_IE_RF1LE; |
| 4703 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4704 | } |
| 4705 | |
| 4706 | static inline void hri_can_toggle_IE_RF1LE_bit(const void *const hw) |
| 4707 | { |
| 4708 | CAN_CRITICAL_SECTION_ENTER(); |
| 4709 | ((Can *)hw)->IE.reg ^= CAN_IE_RF1LE; |
| 4710 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4711 | } |
| 4712 | |
| 4713 | static inline void hri_can_set_IE_HPME_bit(const void *const hw) |
| 4714 | { |
| 4715 | CAN_CRITICAL_SECTION_ENTER(); |
| 4716 | ((Can *)hw)->IE.reg |= CAN_IE_HPME; |
| 4717 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4718 | } |
| 4719 | |
| 4720 | static inline bool hri_can_get_IE_HPME_bit(const void *const hw) |
| 4721 | { |
| 4722 | uint32_t tmp; |
| 4723 | tmp = ((Can *)hw)->IE.reg; |
| 4724 | tmp = (tmp & CAN_IE_HPME) >> CAN_IE_HPME_Pos; |
| 4725 | return (bool)tmp; |
| 4726 | } |
| 4727 | |
| 4728 | static inline void hri_can_write_IE_HPME_bit(const void *const hw, bool value) |
| 4729 | { |
| 4730 | uint32_t tmp; |
| 4731 | CAN_CRITICAL_SECTION_ENTER(); |
| 4732 | tmp = ((Can *)hw)->IE.reg; |
| 4733 | tmp &= ~CAN_IE_HPME; |
| 4734 | tmp |= value << CAN_IE_HPME_Pos; |
| 4735 | ((Can *)hw)->IE.reg = tmp; |
| 4736 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4737 | } |
| 4738 | |
| 4739 | static inline void hri_can_clear_IE_HPME_bit(const void *const hw) |
| 4740 | { |
| 4741 | CAN_CRITICAL_SECTION_ENTER(); |
| 4742 | ((Can *)hw)->IE.reg &= ~CAN_IE_HPME; |
| 4743 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4744 | } |
| 4745 | |
| 4746 | static inline void hri_can_toggle_IE_HPME_bit(const void *const hw) |
| 4747 | { |
| 4748 | CAN_CRITICAL_SECTION_ENTER(); |
| 4749 | ((Can *)hw)->IE.reg ^= CAN_IE_HPME; |
| 4750 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4751 | } |
| 4752 | |
| 4753 | static inline void hri_can_set_IE_TCE_bit(const void *const hw) |
| 4754 | { |
| 4755 | CAN_CRITICAL_SECTION_ENTER(); |
| 4756 | ((Can *)hw)->IE.reg |= CAN_IE_TCE; |
| 4757 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4758 | } |
| 4759 | |
| 4760 | static inline bool hri_can_get_IE_TCE_bit(const void *const hw) |
| 4761 | { |
| 4762 | uint32_t tmp; |
| 4763 | tmp = ((Can *)hw)->IE.reg; |
| 4764 | tmp = (tmp & CAN_IE_TCE) >> CAN_IE_TCE_Pos; |
| 4765 | return (bool)tmp; |
| 4766 | } |
| 4767 | |
| 4768 | static inline void hri_can_write_IE_TCE_bit(const void *const hw, bool value) |
| 4769 | { |
| 4770 | uint32_t tmp; |
| 4771 | CAN_CRITICAL_SECTION_ENTER(); |
| 4772 | tmp = ((Can *)hw)->IE.reg; |
| 4773 | tmp &= ~CAN_IE_TCE; |
| 4774 | tmp |= value << CAN_IE_TCE_Pos; |
| 4775 | ((Can *)hw)->IE.reg = tmp; |
| 4776 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4777 | } |
| 4778 | |
| 4779 | static inline void hri_can_clear_IE_TCE_bit(const void *const hw) |
| 4780 | { |
| 4781 | CAN_CRITICAL_SECTION_ENTER(); |
| 4782 | ((Can *)hw)->IE.reg &= ~CAN_IE_TCE; |
| 4783 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4784 | } |
| 4785 | |
| 4786 | static inline void hri_can_toggle_IE_TCE_bit(const void *const hw) |
| 4787 | { |
| 4788 | CAN_CRITICAL_SECTION_ENTER(); |
| 4789 | ((Can *)hw)->IE.reg ^= CAN_IE_TCE; |
| 4790 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4791 | } |
| 4792 | |
| 4793 | static inline void hri_can_set_IE_TCFE_bit(const void *const hw) |
| 4794 | { |
| 4795 | CAN_CRITICAL_SECTION_ENTER(); |
| 4796 | ((Can *)hw)->IE.reg |= CAN_IE_TCFE; |
| 4797 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4798 | } |
| 4799 | |
| 4800 | static inline bool hri_can_get_IE_TCFE_bit(const void *const hw) |
| 4801 | { |
| 4802 | uint32_t tmp; |
| 4803 | tmp = ((Can *)hw)->IE.reg; |
| 4804 | tmp = (tmp & CAN_IE_TCFE) >> CAN_IE_TCFE_Pos; |
| 4805 | return (bool)tmp; |
| 4806 | } |
| 4807 | |
| 4808 | static inline void hri_can_write_IE_TCFE_bit(const void *const hw, bool value) |
| 4809 | { |
| 4810 | uint32_t tmp; |
| 4811 | CAN_CRITICAL_SECTION_ENTER(); |
| 4812 | tmp = ((Can *)hw)->IE.reg; |
| 4813 | tmp &= ~CAN_IE_TCFE; |
| 4814 | tmp |= value << CAN_IE_TCFE_Pos; |
| 4815 | ((Can *)hw)->IE.reg = tmp; |
| 4816 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4817 | } |
| 4818 | |
| 4819 | static inline void hri_can_clear_IE_TCFE_bit(const void *const hw) |
| 4820 | { |
| 4821 | CAN_CRITICAL_SECTION_ENTER(); |
| 4822 | ((Can *)hw)->IE.reg &= ~CAN_IE_TCFE; |
| 4823 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4824 | } |
| 4825 | |
| 4826 | static inline void hri_can_toggle_IE_TCFE_bit(const void *const hw) |
| 4827 | { |
| 4828 | CAN_CRITICAL_SECTION_ENTER(); |
| 4829 | ((Can *)hw)->IE.reg ^= CAN_IE_TCFE; |
| 4830 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4831 | } |
| 4832 | |
| 4833 | static inline void hri_can_set_IE_TFEE_bit(const void *const hw) |
| 4834 | { |
| 4835 | CAN_CRITICAL_SECTION_ENTER(); |
| 4836 | ((Can *)hw)->IE.reg |= CAN_IE_TFEE; |
| 4837 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4838 | } |
| 4839 | |
| 4840 | static inline bool hri_can_get_IE_TFEE_bit(const void *const hw) |
| 4841 | { |
| 4842 | uint32_t tmp; |
| 4843 | tmp = ((Can *)hw)->IE.reg; |
| 4844 | tmp = (tmp & CAN_IE_TFEE) >> CAN_IE_TFEE_Pos; |
| 4845 | return (bool)tmp; |
| 4846 | } |
| 4847 | |
| 4848 | static inline void hri_can_write_IE_TFEE_bit(const void *const hw, bool value) |
| 4849 | { |
| 4850 | uint32_t tmp; |
| 4851 | CAN_CRITICAL_SECTION_ENTER(); |
| 4852 | tmp = ((Can *)hw)->IE.reg; |
| 4853 | tmp &= ~CAN_IE_TFEE; |
| 4854 | tmp |= value << CAN_IE_TFEE_Pos; |
| 4855 | ((Can *)hw)->IE.reg = tmp; |
| 4856 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4857 | } |
| 4858 | |
| 4859 | static inline void hri_can_clear_IE_TFEE_bit(const void *const hw) |
| 4860 | { |
| 4861 | CAN_CRITICAL_SECTION_ENTER(); |
| 4862 | ((Can *)hw)->IE.reg &= ~CAN_IE_TFEE; |
| 4863 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4864 | } |
| 4865 | |
| 4866 | static inline void hri_can_toggle_IE_TFEE_bit(const void *const hw) |
| 4867 | { |
| 4868 | CAN_CRITICAL_SECTION_ENTER(); |
| 4869 | ((Can *)hw)->IE.reg ^= CAN_IE_TFEE; |
| 4870 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4871 | } |
| 4872 | |
| 4873 | static inline void hri_can_set_IE_TEFNE_bit(const void *const hw) |
| 4874 | { |
| 4875 | CAN_CRITICAL_SECTION_ENTER(); |
| 4876 | ((Can *)hw)->IE.reg |= CAN_IE_TEFNE; |
| 4877 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4878 | } |
| 4879 | |
| 4880 | static inline bool hri_can_get_IE_TEFNE_bit(const void *const hw) |
| 4881 | { |
| 4882 | uint32_t tmp; |
| 4883 | tmp = ((Can *)hw)->IE.reg; |
| 4884 | tmp = (tmp & CAN_IE_TEFNE) >> CAN_IE_TEFNE_Pos; |
| 4885 | return (bool)tmp; |
| 4886 | } |
| 4887 | |
| 4888 | static inline void hri_can_write_IE_TEFNE_bit(const void *const hw, bool value) |
| 4889 | { |
| 4890 | uint32_t tmp; |
| 4891 | CAN_CRITICAL_SECTION_ENTER(); |
| 4892 | tmp = ((Can *)hw)->IE.reg; |
| 4893 | tmp &= ~CAN_IE_TEFNE; |
| 4894 | tmp |= value << CAN_IE_TEFNE_Pos; |
| 4895 | ((Can *)hw)->IE.reg = tmp; |
| 4896 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4897 | } |
| 4898 | |
| 4899 | static inline void hri_can_clear_IE_TEFNE_bit(const void *const hw) |
| 4900 | { |
| 4901 | CAN_CRITICAL_SECTION_ENTER(); |
| 4902 | ((Can *)hw)->IE.reg &= ~CAN_IE_TEFNE; |
| 4903 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4904 | } |
| 4905 | |
| 4906 | static inline void hri_can_toggle_IE_TEFNE_bit(const void *const hw) |
| 4907 | { |
| 4908 | CAN_CRITICAL_SECTION_ENTER(); |
| 4909 | ((Can *)hw)->IE.reg ^= CAN_IE_TEFNE; |
| 4910 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4911 | } |
| 4912 | |
| 4913 | static inline void hri_can_set_IE_TEFWE_bit(const void *const hw) |
| 4914 | { |
| 4915 | CAN_CRITICAL_SECTION_ENTER(); |
| 4916 | ((Can *)hw)->IE.reg |= CAN_IE_TEFWE; |
| 4917 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4918 | } |
| 4919 | |
| 4920 | static inline bool hri_can_get_IE_TEFWE_bit(const void *const hw) |
| 4921 | { |
| 4922 | uint32_t tmp; |
| 4923 | tmp = ((Can *)hw)->IE.reg; |
| 4924 | tmp = (tmp & CAN_IE_TEFWE) >> CAN_IE_TEFWE_Pos; |
| 4925 | return (bool)tmp; |
| 4926 | } |
| 4927 | |
| 4928 | static inline void hri_can_write_IE_TEFWE_bit(const void *const hw, bool value) |
| 4929 | { |
| 4930 | uint32_t tmp; |
| 4931 | CAN_CRITICAL_SECTION_ENTER(); |
| 4932 | tmp = ((Can *)hw)->IE.reg; |
| 4933 | tmp &= ~CAN_IE_TEFWE; |
| 4934 | tmp |= value << CAN_IE_TEFWE_Pos; |
| 4935 | ((Can *)hw)->IE.reg = tmp; |
| 4936 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4937 | } |
| 4938 | |
| 4939 | static inline void hri_can_clear_IE_TEFWE_bit(const void *const hw) |
| 4940 | { |
| 4941 | CAN_CRITICAL_SECTION_ENTER(); |
| 4942 | ((Can *)hw)->IE.reg &= ~CAN_IE_TEFWE; |
| 4943 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4944 | } |
| 4945 | |
| 4946 | static inline void hri_can_toggle_IE_TEFWE_bit(const void *const hw) |
| 4947 | { |
| 4948 | CAN_CRITICAL_SECTION_ENTER(); |
| 4949 | ((Can *)hw)->IE.reg ^= CAN_IE_TEFWE; |
| 4950 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4951 | } |
| 4952 | |
| 4953 | static inline void hri_can_set_IE_TEFFE_bit(const void *const hw) |
| 4954 | { |
| 4955 | CAN_CRITICAL_SECTION_ENTER(); |
| 4956 | ((Can *)hw)->IE.reg |= CAN_IE_TEFFE; |
| 4957 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4958 | } |
| 4959 | |
| 4960 | static inline bool hri_can_get_IE_TEFFE_bit(const void *const hw) |
| 4961 | { |
| 4962 | uint32_t tmp; |
| 4963 | tmp = ((Can *)hw)->IE.reg; |
| 4964 | tmp = (tmp & CAN_IE_TEFFE) >> CAN_IE_TEFFE_Pos; |
| 4965 | return (bool)tmp; |
| 4966 | } |
| 4967 | |
| 4968 | static inline void hri_can_write_IE_TEFFE_bit(const void *const hw, bool value) |
| 4969 | { |
| 4970 | uint32_t tmp; |
| 4971 | CAN_CRITICAL_SECTION_ENTER(); |
| 4972 | tmp = ((Can *)hw)->IE.reg; |
| 4973 | tmp &= ~CAN_IE_TEFFE; |
| 4974 | tmp |= value << CAN_IE_TEFFE_Pos; |
| 4975 | ((Can *)hw)->IE.reg = tmp; |
| 4976 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4977 | } |
| 4978 | |
| 4979 | static inline void hri_can_clear_IE_TEFFE_bit(const void *const hw) |
| 4980 | { |
| 4981 | CAN_CRITICAL_SECTION_ENTER(); |
| 4982 | ((Can *)hw)->IE.reg &= ~CAN_IE_TEFFE; |
| 4983 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4984 | } |
| 4985 | |
| 4986 | static inline void hri_can_toggle_IE_TEFFE_bit(const void *const hw) |
| 4987 | { |
| 4988 | CAN_CRITICAL_SECTION_ENTER(); |
| 4989 | ((Can *)hw)->IE.reg ^= CAN_IE_TEFFE; |
| 4990 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4991 | } |
| 4992 | |
| 4993 | static inline void hri_can_set_IE_TEFLE_bit(const void *const hw) |
| 4994 | { |
| 4995 | CAN_CRITICAL_SECTION_ENTER(); |
| 4996 | ((Can *)hw)->IE.reg |= CAN_IE_TEFLE; |
| 4997 | CAN_CRITICAL_SECTION_LEAVE(); |
| 4998 | } |
| 4999 | |
| 5000 | static inline bool hri_can_get_IE_TEFLE_bit(const void *const hw) |
| 5001 | { |
| 5002 | uint32_t tmp; |
| 5003 | tmp = ((Can *)hw)->IE.reg; |
| 5004 | tmp = (tmp & CAN_IE_TEFLE) >> CAN_IE_TEFLE_Pos; |
| 5005 | return (bool)tmp; |
| 5006 | } |
| 5007 | |
| 5008 | static inline void hri_can_write_IE_TEFLE_bit(const void *const hw, bool value) |
| 5009 | { |
| 5010 | uint32_t tmp; |
| 5011 | CAN_CRITICAL_SECTION_ENTER(); |
| 5012 | tmp = ((Can *)hw)->IE.reg; |
| 5013 | tmp &= ~CAN_IE_TEFLE; |
| 5014 | tmp |= value << CAN_IE_TEFLE_Pos; |
| 5015 | ((Can *)hw)->IE.reg = tmp; |
| 5016 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5017 | } |
| 5018 | |
| 5019 | static inline void hri_can_clear_IE_TEFLE_bit(const void *const hw) |
| 5020 | { |
| 5021 | CAN_CRITICAL_SECTION_ENTER(); |
| 5022 | ((Can *)hw)->IE.reg &= ~CAN_IE_TEFLE; |
| 5023 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5024 | } |
| 5025 | |
| 5026 | static inline void hri_can_toggle_IE_TEFLE_bit(const void *const hw) |
| 5027 | { |
| 5028 | CAN_CRITICAL_SECTION_ENTER(); |
| 5029 | ((Can *)hw)->IE.reg ^= CAN_IE_TEFLE; |
| 5030 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5031 | } |
| 5032 | |
| 5033 | static inline void hri_can_set_IE_TSWE_bit(const void *const hw) |
| 5034 | { |
| 5035 | CAN_CRITICAL_SECTION_ENTER(); |
| 5036 | ((Can *)hw)->IE.reg |= CAN_IE_TSWE; |
| 5037 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5038 | } |
| 5039 | |
| 5040 | static inline bool hri_can_get_IE_TSWE_bit(const void *const hw) |
| 5041 | { |
| 5042 | uint32_t tmp; |
| 5043 | tmp = ((Can *)hw)->IE.reg; |
| 5044 | tmp = (tmp & CAN_IE_TSWE) >> CAN_IE_TSWE_Pos; |
| 5045 | return (bool)tmp; |
| 5046 | } |
| 5047 | |
| 5048 | static inline void hri_can_write_IE_TSWE_bit(const void *const hw, bool value) |
| 5049 | { |
| 5050 | uint32_t tmp; |
| 5051 | CAN_CRITICAL_SECTION_ENTER(); |
| 5052 | tmp = ((Can *)hw)->IE.reg; |
| 5053 | tmp &= ~CAN_IE_TSWE; |
| 5054 | tmp |= value << CAN_IE_TSWE_Pos; |
| 5055 | ((Can *)hw)->IE.reg = tmp; |
| 5056 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5057 | } |
| 5058 | |
| 5059 | static inline void hri_can_clear_IE_TSWE_bit(const void *const hw) |
| 5060 | { |
| 5061 | CAN_CRITICAL_SECTION_ENTER(); |
| 5062 | ((Can *)hw)->IE.reg &= ~CAN_IE_TSWE; |
| 5063 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5064 | } |
| 5065 | |
| 5066 | static inline void hri_can_toggle_IE_TSWE_bit(const void *const hw) |
| 5067 | { |
| 5068 | CAN_CRITICAL_SECTION_ENTER(); |
| 5069 | ((Can *)hw)->IE.reg ^= CAN_IE_TSWE; |
| 5070 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5071 | } |
| 5072 | |
| 5073 | static inline void hri_can_set_IE_MRAFE_bit(const void *const hw) |
| 5074 | { |
| 5075 | CAN_CRITICAL_SECTION_ENTER(); |
| 5076 | ((Can *)hw)->IE.reg |= CAN_IE_MRAFE; |
| 5077 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5078 | } |
| 5079 | |
| 5080 | static inline bool hri_can_get_IE_MRAFE_bit(const void *const hw) |
| 5081 | { |
| 5082 | uint32_t tmp; |
| 5083 | tmp = ((Can *)hw)->IE.reg; |
| 5084 | tmp = (tmp & CAN_IE_MRAFE) >> CAN_IE_MRAFE_Pos; |
| 5085 | return (bool)tmp; |
| 5086 | } |
| 5087 | |
| 5088 | static inline void hri_can_write_IE_MRAFE_bit(const void *const hw, bool value) |
| 5089 | { |
| 5090 | uint32_t tmp; |
| 5091 | CAN_CRITICAL_SECTION_ENTER(); |
| 5092 | tmp = ((Can *)hw)->IE.reg; |
| 5093 | tmp &= ~CAN_IE_MRAFE; |
| 5094 | tmp |= value << CAN_IE_MRAFE_Pos; |
| 5095 | ((Can *)hw)->IE.reg = tmp; |
| 5096 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5097 | } |
| 5098 | |
| 5099 | static inline void hri_can_clear_IE_MRAFE_bit(const void *const hw) |
| 5100 | { |
| 5101 | CAN_CRITICAL_SECTION_ENTER(); |
| 5102 | ((Can *)hw)->IE.reg &= ~CAN_IE_MRAFE; |
| 5103 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5104 | } |
| 5105 | |
| 5106 | static inline void hri_can_toggle_IE_MRAFE_bit(const void *const hw) |
| 5107 | { |
| 5108 | CAN_CRITICAL_SECTION_ENTER(); |
| 5109 | ((Can *)hw)->IE.reg ^= CAN_IE_MRAFE; |
| 5110 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5111 | } |
| 5112 | |
| 5113 | static inline void hri_can_set_IE_TOOE_bit(const void *const hw) |
| 5114 | { |
| 5115 | CAN_CRITICAL_SECTION_ENTER(); |
| 5116 | ((Can *)hw)->IE.reg |= CAN_IE_TOOE; |
| 5117 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5118 | } |
| 5119 | |
| 5120 | static inline bool hri_can_get_IE_TOOE_bit(const void *const hw) |
| 5121 | { |
| 5122 | uint32_t tmp; |
| 5123 | tmp = ((Can *)hw)->IE.reg; |
| 5124 | tmp = (tmp & CAN_IE_TOOE) >> CAN_IE_TOOE_Pos; |
| 5125 | return (bool)tmp; |
| 5126 | } |
| 5127 | |
| 5128 | static inline void hri_can_write_IE_TOOE_bit(const void *const hw, bool value) |
| 5129 | { |
| 5130 | uint32_t tmp; |
| 5131 | CAN_CRITICAL_SECTION_ENTER(); |
| 5132 | tmp = ((Can *)hw)->IE.reg; |
| 5133 | tmp &= ~CAN_IE_TOOE; |
| 5134 | tmp |= value << CAN_IE_TOOE_Pos; |
| 5135 | ((Can *)hw)->IE.reg = tmp; |
| 5136 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5137 | } |
| 5138 | |
| 5139 | static inline void hri_can_clear_IE_TOOE_bit(const void *const hw) |
| 5140 | { |
| 5141 | CAN_CRITICAL_SECTION_ENTER(); |
| 5142 | ((Can *)hw)->IE.reg &= ~CAN_IE_TOOE; |
| 5143 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5144 | } |
| 5145 | |
| 5146 | static inline void hri_can_toggle_IE_TOOE_bit(const void *const hw) |
| 5147 | { |
| 5148 | CAN_CRITICAL_SECTION_ENTER(); |
| 5149 | ((Can *)hw)->IE.reg ^= CAN_IE_TOOE; |
| 5150 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5151 | } |
| 5152 | |
| 5153 | static inline void hri_can_set_IE_DRXE_bit(const void *const hw) |
| 5154 | { |
| 5155 | CAN_CRITICAL_SECTION_ENTER(); |
| 5156 | ((Can *)hw)->IE.reg |= CAN_IE_DRXE; |
| 5157 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5158 | } |
| 5159 | |
| 5160 | static inline bool hri_can_get_IE_DRXE_bit(const void *const hw) |
| 5161 | { |
| 5162 | uint32_t tmp; |
| 5163 | tmp = ((Can *)hw)->IE.reg; |
| 5164 | tmp = (tmp & CAN_IE_DRXE) >> CAN_IE_DRXE_Pos; |
| 5165 | return (bool)tmp; |
| 5166 | } |
| 5167 | |
| 5168 | static inline void hri_can_write_IE_DRXE_bit(const void *const hw, bool value) |
| 5169 | { |
| 5170 | uint32_t tmp; |
| 5171 | CAN_CRITICAL_SECTION_ENTER(); |
| 5172 | tmp = ((Can *)hw)->IE.reg; |
| 5173 | tmp &= ~CAN_IE_DRXE; |
| 5174 | tmp |= value << CAN_IE_DRXE_Pos; |
| 5175 | ((Can *)hw)->IE.reg = tmp; |
| 5176 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5177 | } |
| 5178 | |
| 5179 | static inline void hri_can_clear_IE_DRXE_bit(const void *const hw) |
| 5180 | { |
| 5181 | CAN_CRITICAL_SECTION_ENTER(); |
| 5182 | ((Can *)hw)->IE.reg &= ~CAN_IE_DRXE; |
| 5183 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5184 | } |
| 5185 | |
| 5186 | static inline void hri_can_toggle_IE_DRXE_bit(const void *const hw) |
| 5187 | { |
| 5188 | CAN_CRITICAL_SECTION_ENTER(); |
| 5189 | ((Can *)hw)->IE.reg ^= CAN_IE_DRXE; |
| 5190 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5191 | } |
| 5192 | |
| 5193 | static inline void hri_can_set_IE_BECE_bit(const void *const hw) |
| 5194 | { |
| 5195 | CAN_CRITICAL_SECTION_ENTER(); |
| 5196 | ((Can *)hw)->IE.reg |= CAN_IE_BECE; |
| 5197 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5198 | } |
| 5199 | |
| 5200 | static inline bool hri_can_get_IE_BECE_bit(const void *const hw) |
| 5201 | { |
| 5202 | uint32_t tmp; |
| 5203 | tmp = ((Can *)hw)->IE.reg; |
| 5204 | tmp = (tmp & CAN_IE_BECE) >> CAN_IE_BECE_Pos; |
| 5205 | return (bool)tmp; |
| 5206 | } |
| 5207 | |
| 5208 | static inline void hri_can_write_IE_BECE_bit(const void *const hw, bool value) |
| 5209 | { |
| 5210 | uint32_t tmp; |
| 5211 | CAN_CRITICAL_SECTION_ENTER(); |
| 5212 | tmp = ((Can *)hw)->IE.reg; |
| 5213 | tmp &= ~CAN_IE_BECE; |
| 5214 | tmp |= value << CAN_IE_BECE_Pos; |
| 5215 | ((Can *)hw)->IE.reg = tmp; |
| 5216 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5217 | } |
| 5218 | |
| 5219 | static inline void hri_can_clear_IE_BECE_bit(const void *const hw) |
| 5220 | { |
| 5221 | CAN_CRITICAL_SECTION_ENTER(); |
| 5222 | ((Can *)hw)->IE.reg &= ~CAN_IE_BECE; |
| 5223 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5224 | } |
| 5225 | |
| 5226 | static inline void hri_can_toggle_IE_BECE_bit(const void *const hw) |
| 5227 | { |
| 5228 | CAN_CRITICAL_SECTION_ENTER(); |
| 5229 | ((Can *)hw)->IE.reg ^= CAN_IE_BECE; |
| 5230 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5231 | } |
| 5232 | |
| 5233 | static inline void hri_can_set_IE_BEUE_bit(const void *const hw) |
| 5234 | { |
| 5235 | CAN_CRITICAL_SECTION_ENTER(); |
| 5236 | ((Can *)hw)->IE.reg |= CAN_IE_BEUE; |
| 5237 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5238 | } |
| 5239 | |
| 5240 | static inline bool hri_can_get_IE_BEUE_bit(const void *const hw) |
| 5241 | { |
| 5242 | uint32_t tmp; |
| 5243 | tmp = ((Can *)hw)->IE.reg; |
| 5244 | tmp = (tmp & CAN_IE_BEUE) >> CAN_IE_BEUE_Pos; |
| 5245 | return (bool)tmp; |
| 5246 | } |
| 5247 | |
| 5248 | static inline void hri_can_write_IE_BEUE_bit(const void *const hw, bool value) |
| 5249 | { |
| 5250 | uint32_t tmp; |
| 5251 | CAN_CRITICAL_SECTION_ENTER(); |
| 5252 | tmp = ((Can *)hw)->IE.reg; |
| 5253 | tmp &= ~CAN_IE_BEUE; |
| 5254 | tmp |= value << CAN_IE_BEUE_Pos; |
| 5255 | ((Can *)hw)->IE.reg = tmp; |
| 5256 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5257 | } |
| 5258 | |
| 5259 | static inline void hri_can_clear_IE_BEUE_bit(const void *const hw) |
| 5260 | { |
| 5261 | CAN_CRITICAL_SECTION_ENTER(); |
| 5262 | ((Can *)hw)->IE.reg &= ~CAN_IE_BEUE; |
| 5263 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5264 | } |
| 5265 | |
| 5266 | static inline void hri_can_toggle_IE_BEUE_bit(const void *const hw) |
| 5267 | { |
| 5268 | CAN_CRITICAL_SECTION_ENTER(); |
| 5269 | ((Can *)hw)->IE.reg ^= CAN_IE_BEUE; |
| 5270 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5271 | } |
| 5272 | |
| 5273 | static inline void hri_can_set_IE_ELOE_bit(const void *const hw) |
| 5274 | { |
| 5275 | CAN_CRITICAL_SECTION_ENTER(); |
| 5276 | ((Can *)hw)->IE.reg |= CAN_IE_ELOE; |
| 5277 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5278 | } |
| 5279 | |
| 5280 | static inline bool hri_can_get_IE_ELOE_bit(const void *const hw) |
| 5281 | { |
| 5282 | uint32_t tmp; |
| 5283 | tmp = ((Can *)hw)->IE.reg; |
| 5284 | tmp = (tmp & CAN_IE_ELOE) >> CAN_IE_ELOE_Pos; |
| 5285 | return (bool)tmp; |
| 5286 | } |
| 5287 | |
| 5288 | static inline void hri_can_write_IE_ELOE_bit(const void *const hw, bool value) |
| 5289 | { |
| 5290 | uint32_t tmp; |
| 5291 | CAN_CRITICAL_SECTION_ENTER(); |
| 5292 | tmp = ((Can *)hw)->IE.reg; |
| 5293 | tmp &= ~CAN_IE_ELOE; |
| 5294 | tmp |= value << CAN_IE_ELOE_Pos; |
| 5295 | ((Can *)hw)->IE.reg = tmp; |
| 5296 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5297 | } |
| 5298 | |
| 5299 | static inline void hri_can_clear_IE_ELOE_bit(const void *const hw) |
| 5300 | { |
| 5301 | CAN_CRITICAL_SECTION_ENTER(); |
| 5302 | ((Can *)hw)->IE.reg &= ~CAN_IE_ELOE; |
| 5303 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5304 | } |
| 5305 | |
| 5306 | static inline void hri_can_toggle_IE_ELOE_bit(const void *const hw) |
| 5307 | { |
| 5308 | CAN_CRITICAL_SECTION_ENTER(); |
| 5309 | ((Can *)hw)->IE.reg ^= CAN_IE_ELOE; |
| 5310 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5311 | } |
| 5312 | |
| 5313 | static inline void hri_can_set_IE_EPE_bit(const void *const hw) |
| 5314 | { |
| 5315 | CAN_CRITICAL_SECTION_ENTER(); |
| 5316 | ((Can *)hw)->IE.reg |= CAN_IE_EPE; |
| 5317 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5318 | } |
| 5319 | |
| 5320 | static inline bool hri_can_get_IE_EPE_bit(const void *const hw) |
| 5321 | { |
| 5322 | uint32_t tmp; |
| 5323 | tmp = ((Can *)hw)->IE.reg; |
| 5324 | tmp = (tmp & CAN_IE_EPE) >> CAN_IE_EPE_Pos; |
| 5325 | return (bool)tmp; |
| 5326 | } |
| 5327 | |
| 5328 | static inline void hri_can_write_IE_EPE_bit(const void *const hw, bool value) |
| 5329 | { |
| 5330 | uint32_t tmp; |
| 5331 | CAN_CRITICAL_SECTION_ENTER(); |
| 5332 | tmp = ((Can *)hw)->IE.reg; |
| 5333 | tmp &= ~CAN_IE_EPE; |
| 5334 | tmp |= value << CAN_IE_EPE_Pos; |
| 5335 | ((Can *)hw)->IE.reg = tmp; |
| 5336 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5337 | } |
| 5338 | |
| 5339 | static inline void hri_can_clear_IE_EPE_bit(const void *const hw) |
| 5340 | { |
| 5341 | CAN_CRITICAL_SECTION_ENTER(); |
| 5342 | ((Can *)hw)->IE.reg &= ~CAN_IE_EPE; |
| 5343 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5344 | } |
| 5345 | |
| 5346 | static inline void hri_can_toggle_IE_EPE_bit(const void *const hw) |
| 5347 | { |
| 5348 | CAN_CRITICAL_SECTION_ENTER(); |
| 5349 | ((Can *)hw)->IE.reg ^= CAN_IE_EPE; |
| 5350 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5351 | } |
| 5352 | |
| 5353 | static inline void hri_can_set_IE_EWE_bit(const void *const hw) |
| 5354 | { |
| 5355 | CAN_CRITICAL_SECTION_ENTER(); |
| 5356 | ((Can *)hw)->IE.reg |= CAN_IE_EWE; |
| 5357 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5358 | } |
| 5359 | |
| 5360 | static inline bool hri_can_get_IE_EWE_bit(const void *const hw) |
| 5361 | { |
| 5362 | uint32_t tmp; |
| 5363 | tmp = ((Can *)hw)->IE.reg; |
| 5364 | tmp = (tmp & CAN_IE_EWE) >> CAN_IE_EWE_Pos; |
| 5365 | return (bool)tmp; |
| 5366 | } |
| 5367 | |
| 5368 | static inline void hri_can_write_IE_EWE_bit(const void *const hw, bool value) |
| 5369 | { |
| 5370 | uint32_t tmp; |
| 5371 | CAN_CRITICAL_SECTION_ENTER(); |
| 5372 | tmp = ((Can *)hw)->IE.reg; |
| 5373 | tmp &= ~CAN_IE_EWE; |
| 5374 | tmp |= value << CAN_IE_EWE_Pos; |
| 5375 | ((Can *)hw)->IE.reg = tmp; |
| 5376 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5377 | } |
| 5378 | |
| 5379 | static inline void hri_can_clear_IE_EWE_bit(const void *const hw) |
| 5380 | { |
| 5381 | CAN_CRITICAL_SECTION_ENTER(); |
| 5382 | ((Can *)hw)->IE.reg &= ~CAN_IE_EWE; |
| 5383 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5384 | } |
| 5385 | |
| 5386 | static inline void hri_can_toggle_IE_EWE_bit(const void *const hw) |
| 5387 | { |
| 5388 | CAN_CRITICAL_SECTION_ENTER(); |
| 5389 | ((Can *)hw)->IE.reg ^= CAN_IE_EWE; |
| 5390 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5391 | } |
| 5392 | |
| 5393 | static inline void hri_can_set_IE_BOE_bit(const void *const hw) |
| 5394 | { |
| 5395 | CAN_CRITICAL_SECTION_ENTER(); |
| 5396 | ((Can *)hw)->IE.reg |= CAN_IE_BOE; |
| 5397 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5398 | } |
| 5399 | |
| 5400 | static inline bool hri_can_get_IE_BOE_bit(const void *const hw) |
| 5401 | { |
| 5402 | uint32_t tmp; |
| 5403 | tmp = ((Can *)hw)->IE.reg; |
| 5404 | tmp = (tmp & CAN_IE_BOE) >> CAN_IE_BOE_Pos; |
| 5405 | return (bool)tmp; |
| 5406 | } |
| 5407 | |
| 5408 | static inline void hri_can_write_IE_BOE_bit(const void *const hw, bool value) |
| 5409 | { |
| 5410 | uint32_t tmp; |
| 5411 | CAN_CRITICAL_SECTION_ENTER(); |
| 5412 | tmp = ((Can *)hw)->IE.reg; |
| 5413 | tmp &= ~CAN_IE_BOE; |
| 5414 | tmp |= value << CAN_IE_BOE_Pos; |
| 5415 | ((Can *)hw)->IE.reg = tmp; |
| 5416 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5417 | } |
| 5418 | |
| 5419 | static inline void hri_can_clear_IE_BOE_bit(const void *const hw) |
| 5420 | { |
| 5421 | CAN_CRITICAL_SECTION_ENTER(); |
| 5422 | ((Can *)hw)->IE.reg &= ~CAN_IE_BOE; |
| 5423 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5424 | } |
| 5425 | |
| 5426 | static inline void hri_can_toggle_IE_BOE_bit(const void *const hw) |
| 5427 | { |
| 5428 | CAN_CRITICAL_SECTION_ENTER(); |
| 5429 | ((Can *)hw)->IE.reg ^= CAN_IE_BOE; |
| 5430 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5431 | } |
| 5432 | |
| 5433 | static inline void hri_can_set_IE_WDIE_bit(const void *const hw) |
| 5434 | { |
| 5435 | CAN_CRITICAL_SECTION_ENTER(); |
| 5436 | ((Can *)hw)->IE.reg |= CAN_IE_WDIE; |
| 5437 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5438 | } |
| 5439 | |
| 5440 | static inline bool hri_can_get_IE_WDIE_bit(const void *const hw) |
| 5441 | { |
| 5442 | uint32_t tmp; |
| 5443 | tmp = ((Can *)hw)->IE.reg; |
| 5444 | tmp = (tmp & CAN_IE_WDIE) >> CAN_IE_WDIE_Pos; |
| 5445 | return (bool)tmp; |
| 5446 | } |
| 5447 | |
| 5448 | static inline void hri_can_write_IE_WDIE_bit(const void *const hw, bool value) |
| 5449 | { |
| 5450 | uint32_t tmp; |
| 5451 | CAN_CRITICAL_SECTION_ENTER(); |
| 5452 | tmp = ((Can *)hw)->IE.reg; |
| 5453 | tmp &= ~CAN_IE_WDIE; |
| 5454 | tmp |= value << CAN_IE_WDIE_Pos; |
| 5455 | ((Can *)hw)->IE.reg = tmp; |
| 5456 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5457 | } |
| 5458 | |
| 5459 | static inline void hri_can_clear_IE_WDIE_bit(const void *const hw) |
| 5460 | { |
| 5461 | CAN_CRITICAL_SECTION_ENTER(); |
| 5462 | ((Can *)hw)->IE.reg &= ~CAN_IE_WDIE; |
| 5463 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5464 | } |
| 5465 | |
| 5466 | static inline void hri_can_toggle_IE_WDIE_bit(const void *const hw) |
| 5467 | { |
| 5468 | CAN_CRITICAL_SECTION_ENTER(); |
| 5469 | ((Can *)hw)->IE.reg ^= CAN_IE_WDIE; |
| 5470 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5471 | } |
| 5472 | |
| 5473 | static inline void hri_can_set_IE_PEAE_bit(const void *const hw) |
| 5474 | { |
| 5475 | CAN_CRITICAL_SECTION_ENTER(); |
| 5476 | ((Can *)hw)->IE.reg |= CAN_IE_PEAE; |
| 5477 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5478 | } |
| 5479 | |
| 5480 | static inline bool hri_can_get_IE_PEAE_bit(const void *const hw) |
| 5481 | { |
| 5482 | uint32_t tmp; |
| 5483 | tmp = ((Can *)hw)->IE.reg; |
| 5484 | tmp = (tmp & CAN_IE_PEAE) >> CAN_IE_PEAE_Pos; |
| 5485 | return (bool)tmp; |
| 5486 | } |
| 5487 | |
| 5488 | static inline void hri_can_write_IE_PEAE_bit(const void *const hw, bool value) |
| 5489 | { |
| 5490 | uint32_t tmp; |
| 5491 | CAN_CRITICAL_SECTION_ENTER(); |
| 5492 | tmp = ((Can *)hw)->IE.reg; |
| 5493 | tmp &= ~CAN_IE_PEAE; |
| 5494 | tmp |= value << CAN_IE_PEAE_Pos; |
| 5495 | ((Can *)hw)->IE.reg = tmp; |
| 5496 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5497 | } |
| 5498 | |
| 5499 | static inline void hri_can_clear_IE_PEAE_bit(const void *const hw) |
| 5500 | { |
| 5501 | CAN_CRITICAL_SECTION_ENTER(); |
| 5502 | ((Can *)hw)->IE.reg &= ~CAN_IE_PEAE; |
| 5503 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5504 | } |
| 5505 | |
| 5506 | static inline void hri_can_toggle_IE_PEAE_bit(const void *const hw) |
| 5507 | { |
| 5508 | CAN_CRITICAL_SECTION_ENTER(); |
| 5509 | ((Can *)hw)->IE.reg ^= CAN_IE_PEAE; |
| 5510 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5511 | } |
| 5512 | |
| 5513 | static inline void hri_can_set_IE_PEDE_bit(const void *const hw) |
| 5514 | { |
| 5515 | CAN_CRITICAL_SECTION_ENTER(); |
| 5516 | ((Can *)hw)->IE.reg |= CAN_IE_PEDE; |
| 5517 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5518 | } |
| 5519 | |
| 5520 | static inline bool hri_can_get_IE_PEDE_bit(const void *const hw) |
| 5521 | { |
| 5522 | uint32_t tmp; |
| 5523 | tmp = ((Can *)hw)->IE.reg; |
| 5524 | tmp = (tmp & CAN_IE_PEDE) >> CAN_IE_PEDE_Pos; |
| 5525 | return (bool)tmp; |
| 5526 | } |
| 5527 | |
| 5528 | static inline void hri_can_write_IE_PEDE_bit(const void *const hw, bool value) |
| 5529 | { |
| 5530 | uint32_t tmp; |
| 5531 | CAN_CRITICAL_SECTION_ENTER(); |
| 5532 | tmp = ((Can *)hw)->IE.reg; |
| 5533 | tmp &= ~CAN_IE_PEDE; |
| 5534 | tmp |= value << CAN_IE_PEDE_Pos; |
| 5535 | ((Can *)hw)->IE.reg = tmp; |
| 5536 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5537 | } |
| 5538 | |
| 5539 | static inline void hri_can_clear_IE_PEDE_bit(const void *const hw) |
| 5540 | { |
| 5541 | CAN_CRITICAL_SECTION_ENTER(); |
| 5542 | ((Can *)hw)->IE.reg &= ~CAN_IE_PEDE; |
| 5543 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5544 | } |
| 5545 | |
| 5546 | static inline void hri_can_toggle_IE_PEDE_bit(const void *const hw) |
| 5547 | { |
| 5548 | CAN_CRITICAL_SECTION_ENTER(); |
| 5549 | ((Can *)hw)->IE.reg ^= CAN_IE_PEDE; |
| 5550 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5551 | } |
| 5552 | |
| 5553 | static inline void hri_can_set_IE_ARAE_bit(const void *const hw) |
| 5554 | { |
| 5555 | CAN_CRITICAL_SECTION_ENTER(); |
| 5556 | ((Can *)hw)->IE.reg |= CAN_IE_ARAE; |
| 5557 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5558 | } |
| 5559 | |
| 5560 | static inline bool hri_can_get_IE_ARAE_bit(const void *const hw) |
| 5561 | { |
| 5562 | uint32_t tmp; |
| 5563 | tmp = ((Can *)hw)->IE.reg; |
| 5564 | tmp = (tmp & CAN_IE_ARAE) >> CAN_IE_ARAE_Pos; |
| 5565 | return (bool)tmp; |
| 5566 | } |
| 5567 | |
| 5568 | static inline void hri_can_write_IE_ARAE_bit(const void *const hw, bool value) |
| 5569 | { |
| 5570 | uint32_t tmp; |
| 5571 | CAN_CRITICAL_SECTION_ENTER(); |
| 5572 | tmp = ((Can *)hw)->IE.reg; |
| 5573 | tmp &= ~CAN_IE_ARAE; |
| 5574 | tmp |= value << CAN_IE_ARAE_Pos; |
| 5575 | ((Can *)hw)->IE.reg = tmp; |
| 5576 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5577 | } |
| 5578 | |
| 5579 | static inline void hri_can_clear_IE_ARAE_bit(const void *const hw) |
| 5580 | { |
| 5581 | CAN_CRITICAL_SECTION_ENTER(); |
| 5582 | ((Can *)hw)->IE.reg &= ~CAN_IE_ARAE; |
| 5583 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5584 | } |
| 5585 | |
| 5586 | static inline void hri_can_toggle_IE_ARAE_bit(const void *const hw) |
| 5587 | { |
| 5588 | CAN_CRITICAL_SECTION_ENTER(); |
| 5589 | ((Can *)hw)->IE.reg ^= CAN_IE_ARAE; |
| 5590 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5591 | } |
| 5592 | |
| 5593 | static inline void hri_can_set_IE_reg(const void *const hw, hri_can_ie_reg_t mask) |
| 5594 | { |
| 5595 | CAN_CRITICAL_SECTION_ENTER(); |
| 5596 | ((Can *)hw)->IE.reg |= mask; |
| 5597 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5598 | } |
| 5599 | |
| 5600 | static inline hri_can_ie_reg_t hri_can_get_IE_reg(const void *const hw, hri_can_ie_reg_t mask) |
| 5601 | { |
| 5602 | uint32_t tmp; |
| 5603 | tmp = ((Can *)hw)->IE.reg; |
| 5604 | tmp &= mask; |
| 5605 | return tmp; |
| 5606 | } |
| 5607 | |
| 5608 | static inline void hri_can_write_IE_reg(const void *const hw, hri_can_ie_reg_t data) |
| 5609 | { |
| 5610 | CAN_CRITICAL_SECTION_ENTER(); |
| 5611 | ((Can *)hw)->IE.reg = data; |
| 5612 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5613 | } |
| 5614 | |
| 5615 | static inline void hri_can_clear_IE_reg(const void *const hw, hri_can_ie_reg_t mask) |
| 5616 | { |
| 5617 | CAN_CRITICAL_SECTION_ENTER(); |
| 5618 | ((Can *)hw)->IE.reg &= ~mask; |
| 5619 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5620 | } |
| 5621 | |
| 5622 | static inline void hri_can_toggle_IE_reg(const void *const hw, hri_can_ie_reg_t mask) |
| 5623 | { |
| 5624 | CAN_CRITICAL_SECTION_ENTER(); |
| 5625 | ((Can *)hw)->IE.reg ^= mask; |
| 5626 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5627 | } |
| 5628 | |
| 5629 | static inline hri_can_ie_reg_t hri_can_read_IE_reg(const void *const hw) |
| 5630 | { |
| 5631 | return ((Can *)hw)->IE.reg; |
| 5632 | } |
| 5633 | |
| 5634 | static inline void hri_can_set_ILS_RF0NL_bit(const void *const hw) |
| 5635 | { |
| 5636 | CAN_CRITICAL_SECTION_ENTER(); |
| 5637 | ((Can *)hw)->ILS.reg |= CAN_ILS_RF0NL; |
| 5638 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5639 | } |
| 5640 | |
| 5641 | static inline bool hri_can_get_ILS_RF0NL_bit(const void *const hw) |
| 5642 | { |
| 5643 | uint32_t tmp; |
| 5644 | tmp = ((Can *)hw)->ILS.reg; |
| 5645 | tmp = (tmp & CAN_ILS_RF0NL) >> CAN_ILS_RF0NL_Pos; |
| 5646 | return (bool)tmp; |
| 5647 | } |
| 5648 | |
| 5649 | static inline void hri_can_write_ILS_RF0NL_bit(const void *const hw, bool value) |
| 5650 | { |
| 5651 | uint32_t tmp; |
| 5652 | CAN_CRITICAL_SECTION_ENTER(); |
| 5653 | tmp = ((Can *)hw)->ILS.reg; |
| 5654 | tmp &= ~CAN_ILS_RF0NL; |
| 5655 | tmp |= value << CAN_ILS_RF0NL_Pos; |
| 5656 | ((Can *)hw)->ILS.reg = tmp; |
| 5657 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5658 | } |
| 5659 | |
| 5660 | static inline void hri_can_clear_ILS_RF0NL_bit(const void *const hw) |
| 5661 | { |
| 5662 | CAN_CRITICAL_SECTION_ENTER(); |
| 5663 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0NL; |
| 5664 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5665 | } |
| 5666 | |
| 5667 | static inline void hri_can_toggle_ILS_RF0NL_bit(const void *const hw) |
| 5668 | { |
| 5669 | CAN_CRITICAL_SECTION_ENTER(); |
| 5670 | ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0NL; |
| 5671 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5672 | } |
| 5673 | |
| 5674 | static inline void hri_can_set_ILS_RF0WL_bit(const void *const hw) |
| 5675 | { |
| 5676 | CAN_CRITICAL_SECTION_ENTER(); |
| 5677 | ((Can *)hw)->ILS.reg |= CAN_ILS_RF0WL; |
| 5678 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5679 | } |
| 5680 | |
| 5681 | static inline bool hri_can_get_ILS_RF0WL_bit(const void *const hw) |
| 5682 | { |
| 5683 | uint32_t tmp; |
| 5684 | tmp = ((Can *)hw)->ILS.reg; |
| 5685 | tmp = (tmp & CAN_ILS_RF0WL) >> CAN_ILS_RF0WL_Pos; |
| 5686 | return (bool)tmp; |
| 5687 | } |
| 5688 | |
| 5689 | static inline void hri_can_write_ILS_RF0WL_bit(const void *const hw, bool value) |
| 5690 | { |
| 5691 | uint32_t tmp; |
| 5692 | CAN_CRITICAL_SECTION_ENTER(); |
| 5693 | tmp = ((Can *)hw)->ILS.reg; |
| 5694 | tmp &= ~CAN_ILS_RF0WL; |
| 5695 | tmp |= value << CAN_ILS_RF0WL_Pos; |
| 5696 | ((Can *)hw)->ILS.reg = tmp; |
| 5697 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5698 | } |
| 5699 | |
| 5700 | static inline void hri_can_clear_ILS_RF0WL_bit(const void *const hw) |
| 5701 | { |
| 5702 | CAN_CRITICAL_SECTION_ENTER(); |
| 5703 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0WL; |
| 5704 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5705 | } |
| 5706 | |
| 5707 | static inline void hri_can_toggle_ILS_RF0WL_bit(const void *const hw) |
| 5708 | { |
| 5709 | CAN_CRITICAL_SECTION_ENTER(); |
| 5710 | ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0WL; |
| 5711 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5712 | } |
| 5713 | |
| 5714 | static inline void hri_can_set_ILS_RF0FL_bit(const void *const hw) |
| 5715 | { |
| 5716 | CAN_CRITICAL_SECTION_ENTER(); |
| 5717 | ((Can *)hw)->ILS.reg |= CAN_ILS_RF0FL; |
| 5718 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5719 | } |
| 5720 | |
| 5721 | static inline bool hri_can_get_ILS_RF0FL_bit(const void *const hw) |
| 5722 | { |
| 5723 | uint32_t tmp; |
| 5724 | tmp = ((Can *)hw)->ILS.reg; |
| 5725 | tmp = (tmp & CAN_ILS_RF0FL) >> CAN_ILS_RF0FL_Pos; |
| 5726 | return (bool)tmp; |
| 5727 | } |
| 5728 | |
| 5729 | static inline void hri_can_write_ILS_RF0FL_bit(const void *const hw, bool value) |
| 5730 | { |
| 5731 | uint32_t tmp; |
| 5732 | CAN_CRITICAL_SECTION_ENTER(); |
| 5733 | tmp = ((Can *)hw)->ILS.reg; |
| 5734 | tmp &= ~CAN_ILS_RF0FL; |
| 5735 | tmp |= value << CAN_ILS_RF0FL_Pos; |
| 5736 | ((Can *)hw)->ILS.reg = tmp; |
| 5737 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5738 | } |
| 5739 | |
| 5740 | static inline void hri_can_clear_ILS_RF0FL_bit(const void *const hw) |
| 5741 | { |
| 5742 | CAN_CRITICAL_SECTION_ENTER(); |
| 5743 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0FL; |
| 5744 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5745 | } |
| 5746 | |
| 5747 | static inline void hri_can_toggle_ILS_RF0FL_bit(const void *const hw) |
| 5748 | { |
| 5749 | CAN_CRITICAL_SECTION_ENTER(); |
| 5750 | ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0FL; |
| 5751 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5752 | } |
| 5753 | |
| 5754 | static inline void hri_can_set_ILS_RF0LL_bit(const void *const hw) |
| 5755 | { |
| 5756 | CAN_CRITICAL_SECTION_ENTER(); |
| 5757 | ((Can *)hw)->ILS.reg |= CAN_ILS_RF0LL; |
| 5758 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5759 | } |
| 5760 | |
| 5761 | static inline bool hri_can_get_ILS_RF0LL_bit(const void *const hw) |
| 5762 | { |
| 5763 | uint32_t tmp; |
| 5764 | tmp = ((Can *)hw)->ILS.reg; |
| 5765 | tmp = (tmp & CAN_ILS_RF0LL) >> CAN_ILS_RF0LL_Pos; |
| 5766 | return (bool)tmp; |
| 5767 | } |
| 5768 | |
| 5769 | static inline void hri_can_write_ILS_RF0LL_bit(const void *const hw, bool value) |
| 5770 | { |
| 5771 | uint32_t tmp; |
| 5772 | CAN_CRITICAL_SECTION_ENTER(); |
| 5773 | tmp = ((Can *)hw)->ILS.reg; |
| 5774 | tmp &= ~CAN_ILS_RF0LL; |
| 5775 | tmp |= value << CAN_ILS_RF0LL_Pos; |
| 5776 | ((Can *)hw)->ILS.reg = tmp; |
| 5777 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5778 | } |
| 5779 | |
| 5780 | static inline void hri_can_clear_ILS_RF0LL_bit(const void *const hw) |
| 5781 | { |
| 5782 | CAN_CRITICAL_SECTION_ENTER(); |
| 5783 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0LL; |
| 5784 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5785 | } |
| 5786 | |
| 5787 | static inline void hri_can_toggle_ILS_RF0LL_bit(const void *const hw) |
| 5788 | { |
| 5789 | CAN_CRITICAL_SECTION_ENTER(); |
| 5790 | ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0LL; |
| 5791 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5792 | } |
| 5793 | |
| 5794 | static inline void hri_can_set_ILS_RF1NL_bit(const void *const hw) |
| 5795 | { |
| 5796 | CAN_CRITICAL_SECTION_ENTER(); |
| 5797 | ((Can *)hw)->ILS.reg |= CAN_ILS_RF1NL; |
| 5798 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5799 | } |
| 5800 | |
| 5801 | static inline bool hri_can_get_ILS_RF1NL_bit(const void *const hw) |
| 5802 | { |
| 5803 | uint32_t tmp; |
| 5804 | tmp = ((Can *)hw)->ILS.reg; |
| 5805 | tmp = (tmp & CAN_ILS_RF1NL) >> CAN_ILS_RF1NL_Pos; |
| 5806 | return (bool)tmp; |
| 5807 | } |
| 5808 | |
| 5809 | static inline void hri_can_write_ILS_RF1NL_bit(const void *const hw, bool value) |
| 5810 | { |
| 5811 | uint32_t tmp; |
| 5812 | CAN_CRITICAL_SECTION_ENTER(); |
| 5813 | tmp = ((Can *)hw)->ILS.reg; |
| 5814 | tmp &= ~CAN_ILS_RF1NL; |
| 5815 | tmp |= value << CAN_ILS_RF1NL_Pos; |
| 5816 | ((Can *)hw)->ILS.reg = tmp; |
| 5817 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5818 | } |
| 5819 | |
| 5820 | static inline void hri_can_clear_ILS_RF1NL_bit(const void *const hw) |
| 5821 | { |
| 5822 | CAN_CRITICAL_SECTION_ENTER(); |
| 5823 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1NL; |
| 5824 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5825 | } |
| 5826 | |
| 5827 | static inline void hri_can_toggle_ILS_RF1NL_bit(const void *const hw) |
| 5828 | { |
| 5829 | CAN_CRITICAL_SECTION_ENTER(); |
| 5830 | ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1NL; |
| 5831 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5832 | } |
| 5833 | |
| 5834 | static inline void hri_can_set_ILS_RF1WL_bit(const void *const hw) |
| 5835 | { |
| 5836 | CAN_CRITICAL_SECTION_ENTER(); |
| 5837 | ((Can *)hw)->ILS.reg |= CAN_ILS_RF1WL; |
| 5838 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5839 | } |
| 5840 | |
| 5841 | static inline bool hri_can_get_ILS_RF1WL_bit(const void *const hw) |
| 5842 | { |
| 5843 | uint32_t tmp; |
| 5844 | tmp = ((Can *)hw)->ILS.reg; |
| 5845 | tmp = (tmp & CAN_ILS_RF1WL) >> CAN_ILS_RF1WL_Pos; |
| 5846 | return (bool)tmp; |
| 5847 | } |
| 5848 | |
| 5849 | static inline void hri_can_write_ILS_RF1WL_bit(const void *const hw, bool value) |
| 5850 | { |
| 5851 | uint32_t tmp; |
| 5852 | CAN_CRITICAL_SECTION_ENTER(); |
| 5853 | tmp = ((Can *)hw)->ILS.reg; |
| 5854 | tmp &= ~CAN_ILS_RF1WL; |
| 5855 | tmp |= value << CAN_ILS_RF1WL_Pos; |
| 5856 | ((Can *)hw)->ILS.reg = tmp; |
| 5857 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5858 | } |
| 5859 | |
| 5860 | static inline void hri_can_clear_ILS_RF1WL_bit(const void *const hw) |
| 5861 | { |
| 5862 | CAN_CRITICAL_SECTION_ENTER(); |
| 5863 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1WL; |
| 5864 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5865 | } |
| 5866 | |
| 5867 | static inline void hri_can_toggle_ILS_RF1WL_bit(const void *const hw) |
| 5868 | { |
| 5869 | CAN_CRITICAL_SECTION_ENTER(); |
| 5870 | ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1WL; |
| 5871 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5872 | } |
| 5873 | |
| 5874 | static inline void hri_can_set_ILS_RF1FL_bit(const void *const hw) |
| 5875 | { |
| 5876 | CAN_CRITICAL_SECTION_ENTER(); |
| 5877 | ((Can *)hw)->ILS.reg |= CAN_ILS_RF1FL; |
| 5878 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5879 | } |
| 5880 | |
| 5881 | static inline bool hri_can_get_ILS_RF1FL_bit(const void *const hw) |
| 5882 | { |
| 5883 | uint32_t tmp; |
| 5884 | tmp = ((Can *)hw)->ILS.reg; |
| 5885 | tmp = (tmp & CAN_ILS_RF1FL) >> CAN_ILS_RF1FL_Pos; |
| 5886 | return (bool)tmp; |
| 5887 | } |
| 5888 | |
| 5889 | static inline void hri_can_write_ILS_RF1FL_bit(const void *const hw, bool value) |
| 5890 | { |
| 5891 | uint32_t tmp; |
| 5892 | CAN_CRITICAL_SECTION_ENTER(); |
| 5893 | tmp = ((Can *)hw)->ILS.reg; |
| 5894 | tmp &= ~CAN_ILS_RF1FL; |
| 5895 | tmp |= value << CAN_ILS_RF1FL_Pos; |
| 5896 | ((Can *)hw)->ILS.reg = tmp; |
| 5897 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5898 | } |
| 5899 | |
| 5900 | static inline void hri_can_clear_ILS_RF1FL_bit(const void *const hw) |
| 5901 | { |
| 5902 | CAN_CRITICAL_SECTION_ENTER(); |
| 5903 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1FL; |
| 5904 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5905 | } |
| 5906 | |
| 5907 | static inline void hri_can_toggle_ILS_RF1FL_bit(const void *const hw) |
| 5908 | { |
| 5909 | CAN_CRITICAL_SECTION_ENTER(); |
| 5910 | ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1FL; |
| 5911 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5912 | } |
| 5913 | |
| 5914 | static inline void hri_can_set_ILS_RF1LL_bit(const void *const hw) |
| 5915 | { |
| 5916 | CAN_CRITICAL_SECTION_ENTER(); |
| 5917 | ((Can *)hw)->ILS.reg |= CAN_ILS_RF1LL; |
| 5918 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5919 | } |
| 5920 | |
| 5921 | static inline bool hri_can_get_ILS_RF1LL_bit(const void *const hw) |
| 5922 | { |
| 5923 | uint32_t tmp; |
| 5924 | tmp = ((Can *)hw)->ILS.reg; |
| 5925 | tmp = (tmp & CAN_ILS_RF1LL) >> CAN_ILS_RF1LL_Pos; |
| 5926 | return (bool)tmp; |
| 5927 | } |
| 5928 | |
| 5929 | static inline void hri_can_write_ILS_RF1LL_bit(const void *const hw, bool value) |
| 5930 | { |
| 5931 | uint32_t tmp; |
| 5932 | CAN_CRITICAL_SECTION_ENTER(); |
| 5933 | tmp = ((Can *)hw)->ILS.reg; |
| 5934 | tmp &= ~CAN_ILS_RF1LL; |
| 5935 | tmp |= value << CAN_ILS_RF1LL_Pos; |
| 5936 | ((Can *)hw)->ILS.reg = tmp; |
| 5937 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5938 | } |
| 5939 | |
| 5940 | static inline void hri_can_clear_ILS_RF1LL_bit(const void *const hw) |
| 5941 | { |
| 5942 | CAN_CRITICAL_SECTION_ENTER(); |
| 5943 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1LL; |
| 5944 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5945 | } |
| 5946 | |
| 5947 | static inline void hri_can_toggle_ILS_RF1LL_bit(const void *const hw) |
| 5948 | { |
| 5949 | CAN_CRITICAL_SECTION_ENTER(); |
| 5950 | ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1LL; |
| 5951 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5952 | } |
| 5953 | |
| 5954 | static inline void hri_can_set_ILS_HPML_bit(const void *const hw) |
| 5955 | { |
| 5956 | CAN_CRITICAL_SECTION_ENTER(); |
| 5957 | ((Can *)hw)->ILS.reg |= CAN_ILS_HPML; |
| 5958 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5959 | } |
| 5960 | |
| 5961 | static inline bool hri_can_get_ILS_HPML_bit(const void *const hw) |
| 5962 | { |
| 5963 | uint32_t tmp; |
| 5964 | tmp = ((Can *)hw)->ILS.reg; |
| 5965 | tmp = (tmp & CAN_ILS_HPML) >> CAN_ILS_HPML_Pos; |
| 5966 | return (bool)tmp; |
| 5967 | } |
| 5968 | |
| 5969 | static inline void hri_can_write_ILS_HPML_bit(const void *const hw, bool value) |
| 5970 | { |
| 5971 | uint32_t tmp; |
| 5972 | CAN_CRITICAL_SECTION_ENTER(); |
| 5973 | tmp = ((Can *)hw)->ILS.reg; |
| 5974 | tmp &= ~CAN_ILS_HPML; |
| 5975 | tmp |= value << CAN_ILS_HPML_Pos; |
| 5976 | ((Can *)hw)->ILS.reg = tmp; |
| 5977 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5978 | } |
| 5979 | |
| 5980 | static inline void hri_can_clear_ILS_HPML_bit(const void *const hw) |
| 5981 | { |
| 5982 | CAN_CRITICAL_SECTION_ENTER(); |
| 5983 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_HPML; |
| 5984 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5985 | } |
| 5986 | |
| 5987 | static inline void hri_can_toggle_ILS_HPML_bit(const void *const hw) |
| 5988 | { |
| 5989 | CAN_CRITICAL_SECTION_ENTER(); |
| 5990 | ((Can *)hw)->ILS.reg ^= CAN_ILS_HPML; |
| 5991 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5992 | } |
| 5993 | |
| 5994 | static inline void hri_can_set_ILS_TCL_bit(const void *const hw) |
| 5995 | { |
| 5996 | CAN_CRITICAL_SECTION_ENTER(); |
| 5997 | ((Can *)hw)->ILS.reg |= CAN_ILS_TCL; |
| 5998 | CAN_CRITICAL_SECTION_LEAVE(); |
| 5999 | } |
| 6000 | |
| 6001 | static inline bool hri_can_get_ILS_TCL_bit(const void *const hw) |
| 6002 | { |
| 6003 | uint32_t tmp; |
| 6004 | tmp = ((Can *)hw)->ILS.reg; |
| 6005 | tmp = (tmp & CAN_ILS_TCL) >> CAN_ILS_TCL_Pos; |
| 6006 | return (bool)tmp; |
| 6007 | } |
| 6008 | |
| 6009 | static inline void hri_can_write_ILS_TCL_bit(const void *const hw, bool value) |
| 6010 | { |
| 6011 | uint32_t tmp; |
| 6012 | CAN_CRITICAL_SECTION_ENTER(); |
| 6013 | tmp = ((Can *)hw)->ILS.reg; |
| 6014 | tmp &= ~CAN_ILS_TCL; |
| 6015 | tmp |= value << CAN_ILS_TCL_Pos; |
| 6016 | ((Can *)hw)->ILS.reg = tmp; |
| 6017 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6018 | } |
| 6019 | |
| 6020 | static inline void hri_can_clear_ILS_TCL_bit(const void *const hw) |
| 6021 | { |
| 6022 | CAN_CRITICAL_SECTION_ENTER(); |
| 6023 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_TCL; |
| 6024 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6025 | } |
| 6026 | |
| 6027 | static inline void hri_can_toggle_ILS_TCL_bit(const void *const hw) |
| 6028 | { |
| 6029 | CAN_CRITICAL_SECTION_ENTER(); |
| 6030 | ((Can *)hw)->ILS.reg ^= CAN_ILS_TCL; |
| 6031 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6032 | } |
| 6033 | |
| 6034 | static inline void hri_can_set_ILS_TCFL_bit(const void *const hw) |
| 6035 | { |
| 6036 | CAN_CRITICAL_SECTION_ENTER(); |
| 6037 | ((Can *)hw)->ILS.reg |= CAN_ILS_TCFL; |
| 6038 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6039 | } |
| 6040 | |
| 6041 | static inline bool hri_can_get_ILS_TCFL_bit(const void *const hw) |
| 6042 | { |
| 6043 | uint32_t tmp; |
| 6044 | tmp = ((Can *)hw)->ILS.reg; |
| 6045 | tmp = (tmp & CAN_ILS_TCFL) >> CAN_ILS_TCFL_Pos; |
| 6046 | return (bool)tmp; |
| 6047 | } |
| 6048 | |
| 6049 | static inline void hri_can_write_ILS_TCFL_bit(const void *const hw, bool value) |
| 6050 | { |
| 6051 | uint32_t tmp; |
| 6052 | CAN_CRITICAL_SECTION_ENTER(); |
| 6053 | tmp = ((Can *)hw)->ILS.reg; |
| 6054 | tmp &= ~CAN_ILS_TCFL; |
| 6055 | tmp |= value << CAN_ILS_TCFL_Pos; |
| 6056 | ((Can *)hw)->ILS.reg = tmp; |
| 6057 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6058 | } |
| 6059 | |
| 6060 | static inline void hri_can_clear_ILS_TCFL_bit(const void *const hw) |
| 6061 | { |
| 6062 | CAN_CRITICAL_SECTION_ENTER(); |
| 6063 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_TCFL; |
| 6064 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6065 | } |
| 6066 | |
| 6067 | static inline void hri_can_toggle_ILS_TCFL_bit(const void *const hw) |
| 6068 | { |
| 6069 | CAN_CRITICAL_SECTION_ENTER(); |
| 6070 | ((Can *)hw)->ILS.reg ^= CAN_ILS_TCFL; |
| 6071 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6072 | } |
| 6073 | |
| 6074 | static inline void hri_can_set_ILS_TFEL_bit(const void *const hw) |
| 6075 | { |
| 6076 | CAN_CRITICAL_SECTION_ENTER(); |
| 6077 | ((Can *)hw)->ILS.reg |= CAN_ILS_TFEL; |
| 6078 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6079 | } |
| 6080 | |
| 6081 | static inline bool hri_can_get_ILS_TFEL_bit(const void *const hw) |
| 6082 | { |
| 6083 | uint32_t tmp; |
| 6084 | tmp = ((Can *)hw)->ILS.reg; |
| 6085 | tmp = (tmp & CAN_ILS_TFEL) >> CAN_ILS_TFEL_Pos; |
| 6086 | return (bool)tmp; |
| 6087 | } |
| 6088 | |
| 6089 | static inline void hri_can_write_ILS_TFEL_bit(const void *const hw, bool value) |
| 6090 | { |
| 6091 | uint32_t tmp; |
| 6092 | CAN_CRITICAL_SECTION_ENTER(); |
| 6093 | tmp = ((Can *)hw)->ILS.reg; |
| 6094 | tmp &= ~CAN_ILS_TFEL; |
| 6095 | tmp |= value << CAN_ILS_TFEL_Pos; |
| 6096 | ((Can *)hw)->ILS.reg = tmp; |
| 6097 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6098 | } |
| 6099 | |
| 6100 | static inline void hri_can_clear_ILS_TFEL_bit(const void *const hw) |
| 6101 | { |
| 6102 | CAN_CRITICAL_SECTION_ENTER(); |
| 6103 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_TFEL; |
| 6104 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6105 | } |
| 6106 | |
| 6107 | static inline void hri_can_toggle_ILS_TFEL_bit(const void *const hw) |
| 6108 | { |
| 6109 | CAN_CRITICAL_SECTION_ENTER(); |
| 6110 | ((Can *)hw)->ILS.reg ^= CAN_ILS_TFEL; |
| 6111 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6112 | } |
| 6113 | |
| 6114 | static inline void hri_can_set_ILS_TEFNL_bit(const void *const hw) |
| 6115 | { |
| 6116 | CAN_CRITICAL_SECTION_ENTER(); |
| 6117 | ((Can *)hw)->ILS.reg |= CAN_ILS_TEFNL; |
| 6118 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6119 | } |
| 6120 | |
| 6121 | static inline bool hri_can_get_ILS_TEFNL_bit(const void *const hw) |
| 6122 | { |
| 6123 | uint32_t tmp; |
| 6124 | tmp = ((Can *)hw)->ILS.reg; |
| 6125 | tmp = (tmp & CAN_ILS_TEFNL) >> CAN_ILS_TEFNL_Pos; |
| 6126 | return (bool)tmp; |
| 6127 | } |
| 6128 | |
| 6129 | static inline void hri_can_write_ILS_TEFNL_bit(const void *const hw, bool value) |
| 6130 | { |
| 6131 | uint32_t tmp; |
| 6132 | CAN_CRITICAL_SECTION_ENTER(); |
| 6133 | tmp = ((Can *)hw)->ILS.reg; |
| 6134 | tmp &= ~CAN_ILS_TEFNL; |
| 6135 | tmp |= value << CAN_ILS_TEFNL_Pos; |
| 6136 | ((Can *)hw)->ILS.reg = tmp; |
| 6137 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6138 | } |
| 6139 | |
| 6140 | static inline void hri_can_clear_ILS_TEFNL_bit(const void *const hw) |
| 6141 | { |
| 6142 | CAN_CRITICAL_SECTION_ENTER(); |
| 6143 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFNL; |
| 6144 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6145 | } |
| 6146 | |
| 6147 | static inline void hri_can_toggle_ILS_TEFNL_bit(const void *const hw) |
| 6148 | { |
| 6149 | CAN_CRITICAL_SECTION_ENTER(); |
| 6150 | ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFNL; |
| 6151 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6152 | } |
| 6153 | |
| 6154 | static inline void hri_can_set_ILS_TEFWL_bit(const void *const hw) |
| 6155 | { |
| 6156 | CAN_CRITICAL_SECTION_ENTER(); |
| 6157 | ((Can *)hw)->ILS.reg |= CAN_ILS_TEFWL; |
| 6158 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6159 | } |
| 6160 | |
| 6161 | static inline bool hri_can_get_ILS_TEFWL_bit(const void *const hw) |
| 6162 | { |
| 6163 | uint32_t tmp; |
| 6164 | tmp = ((Can *)hw)->ILS.reg; |
| 6165 | tmp = (tmp & CAN_ILS_TEFWL) >> CAN_ILS_TEFWL_Pos; |
| 6166 | return (bool)tmp; |
| 6167 | } |
| 6168 | |
| 6169 | static inline void hri_can_write_ILS_TEFWL_bit(const void *const hw, bool value) |
| 6170 | { |
| 6171 | uint32_t tmp; |
| 6172 | CAN_CRITICAL_SECTION_ENTER(); |
| 6173 | tmp = ((Can *)hw)->ILS.reg; |
| 6174 | tmp &= ~CAN_ILS_TEFWL; |
| 6175 | tmp |= value << CAN_ILS_TEFWL_Pos; |
| 6176 | ((Can *)hw)->ILS.reg = tmp; |
| 6177 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6178 | } |
| 6179 | |
| 6180 | static inline void hri_can_clear_ILS_TEFWL_bit(const void *const hw) |
| 6181 | { |
| 6182 | CAN_CRITICAL_SECTION_ENTER(); |
| 6183 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFWL; |
| 6184 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6185 | } |
| 6186 | |
| 6187 | static inline void hri_can_toggle_ILS_TEFWL_bit(const void *const hw) |
| 6188 | { |
| 6189 | CAN_CRITICAL_SECTION_ENTER(); |
| 6190 | ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFWL; |
| 6191 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6192 | } |
| 6193 | |
| 6194 | static inline void hri_can_set_ILS_TEFFL_bit(const void *const hw) |
| 6195 | { |
| 6196 | CAN_CRITICAL_SECTION_ENTER(); |
| 6197 | ((Can *)hw)->ILS.reg |= CAN_ILS_TEFFL; |
| 6198 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6199 | } |
| 6200 | |
| 6201 | static inline bool hri_can_get_ILS_TEFFL_bit(const void *const hw) |
| 6202 | { |
| 6203 | uint32_t tmp; |
| 6204 | tmp = ((Can *)hw)->ILS.reg; |
| 6205 | tmp = (tmp & CAN_ILS_TEFFL) >> CAN_ILS_TEFFL_Pos; |
| 6206 | return (bool)tmp; |
| 6207 | } |
| 6208 | |
| 6209 | static inline void hri_can_write_ILS_TEFFL_bit(const void *const hw, bool value) |
| 6210 | { |
| 6211 | uint32_t tmp; |
| 6212 | CAN_CRITICAL_SECTION_ENTER(); |
| 6213 | tmp = ((Can *)hw)->ILS.reg; |
| 6214 | tmp &= ~CAN_ILS_TEFFL; |
| 6215 | tmp |= value << CAN_ILS_TEFFL_Pos; |
| 6216 | ((Can *)hw)->ILS.reg = tmp; |
| 6217 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6218 | } |
| 6219 | |
| 6220 | static inline void hri_can_clear_ILS_TEFFL_bit(const void *const hw) |
| 6221 | { |
| 6222 | CAN_CRITICAL_SECTION_ENTER(); |
| 6223 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFFL; |
| 6224 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6225 | } |
| 6226 | |
| 6227 | static inline void hri_can_toggle_ILS_TEFFL_bit(const void *const hw) |
| 6228 | { |
| 6229 | CAN_CRITICAL_SECTION_ENTER(); |
| 6230 | ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFFL; |
| 6231 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6232 | } |
| 6233 | |
| 6234 | static inline void hri_can_set_ILS_TEFLL_bit(const void *const hw) |
| 6235 | { |
| 6236 | CAN_CRITICAL_SECTION_ENTER(); |
| 6237 | ((Can *)hw)->ILS.reg |= CAN_ILS_TEFLL; |
| 6238 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6239 | } |
| 6240 | |
| 6241 | static inline bool hri_can_get_ILS_TEFLL_bit(const void *const hw) |
| 6242 | { |
| 6243 | uint32_t tmp; |
| 6244 | tmp = ((Can *)hw)->ILS.reg; |
| 6245 | tmp = (tmp & CAN_ILS_TEFLL) >> CAN_ILS_TEFLL_Pos; |
| 6246 | return (bool)tmp; |
| 6247 | } |
| 6248 | |
| 6249 | static inline void hri_can_write_ILS_TEFLL_bit(const void *const hw, bool value) |
| 6250 | { |
| 6251 | uint32_t tmp; |
| 6252 | CAN_CRITICAL_SECTION_ENTER(); |
| 6253 | tmp = ((Can *)hw)->ILS.reg; |
| 6254 | tmp &= ~CAN_ILS_TEFLL; |
| 6255 | tmp |= value << CAN_ILS_TEFLL_Pos; |
| 6256 | ((Can *)hw)->ILS.reg = tmp; |
| 6257 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6258 | } |
| 6259 | |
| 6260 | static inline void hri_can_clear_ILS_TEFLL_bit(const void *const hw) |
| 6261 | { |
| 6262 | CAN_CRITICAL_SECTION_ENTER(); |
| 6263 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFLL; |
| 6264 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6265 | } |
| 6266 | |
| 6267 | static inline void hri_can_toggle_ILS_TEFLL_bit(const void *const hw) |
| 6268 | { |
| 6269 | CAN_CRITICAL_SECTION_ENTER(); |
| 6270 | ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFLL; |
| 6271 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6272 | } |
| 6273 | |
| 6274 | static inline void hri_can_set_ILS_TSWL_bit(const void *const hw) |
| 6275 | { |
| 6276 | CAN_CRITICAL_SECTION_ENTER(); |
| 6277 | ((Can *)hw)->ILS.reg |= CAN_ILS_TSWL; |
| 6278 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6279 | } |
| 6280 | |
| 6281 | static inline bool hri_can_get_ILS_TSWL_bit(const void *const hw) |
| 6282 | { |
| 6283 | uint32_t tmp; |
| 6284 | tmp = ((Can *)hw)->ILS.reg; |
| 6285 | tmp = (tmp & CAN_ILS_TSWL) >> CAN_ILS_TSWL_Pos; |
| 6286 | return (bool)tmp; |
| 6287 | } |
| 6288 | |
| 6289 | static inline void hri_can_write_ILS_TSWL_bit(const void *const hw, bool value) |
| 6290 | { |
| 6291 | uint32_t tmp; |
| 6292 | CAN_CRITICAL_SECTION_ENTER(); |
| 6293 | tmp = ((Can *)hw)->ILS.reg; |
| 6294 | tmp &= ~CAN_ILS_TSWL; |
| 6295 | tmp |= value << CAN_ILS_TSWL_Pos; |
| 6296 | ((Can *)hw)->ILS.reg = tmp; |
| 6297 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6298 | } |
| 6299 | |
| 6300 | static inline void hri_can_clear_ILS_TSWL_bit(const void *const hw) |
| 6301 | { |
| 6302 | CAN_CRITICAL_SECTION_ENTER(); |
| 6303 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_TSWL; |
| 6304 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6305 | } |
| 6306 | |
| 6307 | static inline void hri_can_toggle_ILS_TSWL_bit(const void *const hw) |
| 6308 | { |
| 6309 | CAN_CRITICAL_SECTION_ENTER(); |
| 6310 | ((Can *)hw)->ILS.reg ^= CAN_ILS_TSWL; |
| 6311 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6312 | } |
| 6313 | |
| 6314 | static inline void hri_can_set_ILS_MRAFL_bit(const void *const hw) |
| 6315 | { |
| 6316 | CAN_CRITICAL_SECTION_ENTER(); |
| 6317 | ((Can *)hw)->ILS.reg |= CAN_ILS_MRAFL; |
| 6318 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6319 | } |
| 6320 | |
| 6321 | static inline bool hri_can_get_ILS_MRAFL_bit(const void *const hw) |
| 6322 | { |
| 6323 | uint32_t tmp; |
| 6324 | tmp = ((Can *)hw)->ILS.reg; |
| 6325 | tmp = (tmp & CAN_ILS_MRAFL) >> CAN_ILS_MRAFL_Pos; |
| 6326 | return (bool)tmp; |
| 6327 | } |
| 6328 | |
| 6329 | static inline void hri_can_write_ILS_MRAFL_bit(const void *const hw, bool value) |
| 6330 | { |
| 6331 | uint32_t tmp; |
| 6332 | CAN_CRITICAL_SECTION_ENTER(); |
| 6333 | tmp = ((Can *)hw)->ILS.reg; |
| 6334 | tmp &= ~CAN_ILS_MRAFL; |
| 6335 | tmp |= value << CAN_ILS_MRAFL_Pos; |
| 6336 | ((Can *)hw)->ILS.reg = tmp; |
| 6337 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6338 | } |
| 6339 | |
| 6340 | static inline void hri_can_clear_ILS_MRAFL_bit(const void *const hw) |
| 6341 | { |
| 6342 | CAN_CRITICAL_SECTION_ENTER(); |
| 6343 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_MRAFL; |
| 6344 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6345 | } |
| 6346 | |
| 6347 | static inline void hri_can_toggle_ILS_MRAFL_bit(const void *const hw) |
| 6348 | { |
| 6349 | CAN_CRITICAL_SECTION_ENTER(); |
| 6350 | ((Can *)hw)->ILS.reg ^= CAN_ILS_MRAFL; |
| 6351 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6352 | } |
| 6353 | |
| 6354 | static inline void hri_can_set_ILS_TOOL_bit(const void *const hw) |
| 6355 | { |
| 6356 | CAN_CRITICAL_SECTION_ENTER(); |
| 6357 | ((Can *)hw)->ILS.reg |= CAN_ILS_TOOL; |
| 6358 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6359 | } |
| 6360 | |
| 6361 | static inline bool hri_can_get_ILS_TOOL_bit(const void *const hw) |
| 6362 | { |
| 6363 | uint32_t tmp; |
| 6364 | tmp = ((Can *)hw)->ILS.reg; |
| 6365 | tmp = (tmp & CAN_ILS_TOOL) >> CAN_ILS_TOOL_Pos; |
| 6366 | return (bool)tmp; |
| 6367 | } |
| 6368 | |
| 6369 | static inline void hri_can_write_ILS_TOOL_bit(const void *const hw, bool value) |
| 6370 | { |
| 6371 | uint32_t tmp; |
| 6372 | CAN_CRITICAL_SECTION_ENTER(); |
| 6373 | tmp = ((Can *)hw)->ILS.reg; |
| 6374 | tmp &= ~CAN_ILS_TOOL; |
| 6375 | tmp |= value << CAN_ILS_TOOL_Pos; |
| 6376 | ((Can *)hw)->ILS.reg = tmp; |
| 6377 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6378 | } |
| 6379 | |
| 6380 | static inline void hri_can_clear_ILS_TOOL_bit(const void *const hw) |
| 6381 | { |
| 6382 | CAN_CRITICAL_SECTION_ENTER(); |
| 6383 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_TOOL; |
| 6384 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6385 | } |
| 6386 | |
| 6387 | static inline void hri_can_toggle_ILS_TOOL_bit(const void *const hw) |
| 6388 | { |
| 6389 | CAN_CRITICAL_SECTION_ENTER(); |
| 6390 | ((Can *)hw)->ILS.reg ^= CAN_ILS_TOOL; |
| 6391 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6392 | } |
| 6393 | |
| 6394 | static inline void hri_can_set_ILS_DRXL_bit(const void *const hw) |
| 6395 | { |
| 6396 | CAN_CRITICAL_SECTION_ENTER(); |
| 6397 | ((Can *)hw)->ILS.reg |= CAN_ILS_DRXL; |
| 6398 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6399 | } |
| 6400 | |
| 6401 | static inline bool hri_can_get_ILS_DRXL_bit(const void *const hw) |
| 6402 | { |
| 6403 | uint32_t tmp; |
| 6404 | tmp = ((Can *)hw)->ILS.reg; |
| 6405 | tmp = (tmp & CAN_ILS_DRXL) >> CAN_ILS_DRXL_Pos; |
| 6406 | return (bool)tmp; |
| 6407 | } |
| 6408 | |
| 6409 | static inline void hri_can_write_ILS_DRXL_bit(const void *const hw, bool value) |
| 6410 | { |
| 6411 | uint32_t tmp; |
| 6412 | CAN_CRITICAL_SECTION_ENTER(); |
| 6413 | tmp = ((Can *)hw)->ILS.reg; |
| 6414 | tmp &= ~CAN_ILS_DRXL; |
| 6415 | tmp |= value << CAN_ILS_DRXL_Pos; |
| 6416 | ((Can *)hw)->ILS.reg = tmp; |
| 6417 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6418 | } |
| 6419 | |
| 6420 | static inline void hri_can_clear_ILS_DRXL_bit(const void *const hw) |
| 6421 | { |
| 6422 | CAN_CRITICAL_SECTION_ENTER(); |
| 6423 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_DRXL; |
| 6424 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6425 | } |
| 6426 | |
| 6427 | static inline void hri_can_toggle_ILS_DRXL_bit(const void *const hw) |
| 6428 | { |
| 6429 | CAN_CRITICAL_SECTION_ENTER(); |
| 6430 | ((Can *)hw)->ILS.reg ^= CAN_ILS_DRXL; |
| 6431 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6432 | } |
| 6433 | |
| 6434 | static inline void hri_can_set_ILS_BECL_bit(const void *const hw) |
| 6435 | { |
| 6436 | CAN_CRITICAL_SECTION_ENTER(); |
| 6437 | ((Can *)hw)->ILS.reg |= CAN_ILS_BECL; |
| 6438 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6439 | } |
| 6440 | |
| 6441 | static inline bool hri_can_get_ILS_BECL_bit(const void *const hw) |
| 6442 | { |
| 6443 | uint32_t tmp; |
| 6444 | tmp = ((Can *)hw)->ILS.reg; |
| 6445 | tmp = (tmp & CAN_ILS_BECL) >> CAN_ILS_BECL_Pos; |
| 6446 | return (bool)tmp; |
| 6447 | } |
| 6448 | |
| 6449 | static inline void hri_can_write_ILS_BECL_bit(const void *const hw, bool value) |
| 6450 | { |
| 6451 | uint32_t tmp; |
| 6452 | CAN_CRITICAL_SECTION_ENTER(); |
| 6453 | tmp = ((Can *)hw)->ILS.reg; |
| 6454 | tmp &= ~CAN_ILS_BECL; |
| 6455 | tmp |= value << CAN_ILS_BECL_Pos; |
| 6456 | ((Can *)hw)->ILS.reg = tmp; |
| 6457 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6458 | } |
| 6459 | |
| 6460 | static inline void hri_can_clear_ILS_BECL_bit(const void *const hw) |
| 6461 | { |
| 6462 | CAN_CRITICAL_SECTION_ENTER(); |
| 6463 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_BECL; |
| 6464 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6465 | } |
| 6466 | |
| 6467 | static inline void hri_can_toggle_ILS_BECL_bit(const void *const hw) |
| 6468 | { |
| 6469 | CAN_CRITICAL_SECTION_ENTER(); |
| 6470 | ((Can *)hw)->ILS.reg ^= CAN_ILS_BECL; |
| 6471 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6472 | } |
| 6473 | |
| 6474 | static inline void hri_can_set_ILS_BEUL_bit(const void *const hw) |
| 6475 | { |
| 6476 | CAN_CRITICAL_SECTION_ENTER(); |
| 6477 | ((Can *)hw)->ILS.reg |= CAN_ILS_BEUL; |
| 6478 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6479 | } |
| 6480 | |
| 6481 | static inline bool hri_can_get_ILS_BEUL_bit(const void *const hw) |
| 6482 | { |
| 6483 | uint32_t tmp; |
| 6484 | tmp = ((Can *)hw)->ILS.reg; |
| 6485 | tmp = (tmp & CAN_ILS_BEUL) >> CAN_ILS_BEUL_Pos; |
| 6486 | return (bool)tmp; |
| 6487 | } |
| 6488 | |
| 6489 | static inline void hri_can_write_ILS_BEUL_bit(const void *const hw, bool value) |
| 6490 | { |
| 6491 | uint32_t tmp; |
| 6492 | CAN_CRITICAL_SECTION_ENTER(); |
| 6493 | tmp = ((Can *)hw)->ILS.reg; |
| 6494 | tmp &= ~CAN_ILS_BEUL; |
| 6495 | tmp |= value << CAN_ILS_BEUL_Pos; |
| 6496 | ((Can *)hw)->ILS.reg = tmp; |
| 6497 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6498 | } |
| 6499 | |
| 6500 | static inline void hri_can_clear_ILS_BEUL_bit(const void *const hw) |
| 6501 | { |
| 6502 | CAN_CRITICAL_SECTION_ENTER(); |
| 6503 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_BEUL; |
| 6504 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6505 | } |
| 6506 | |
| 6507 | static inline void hri_can_toggle_ILS_BEUL_bit(const void *const hw) |
| 6508 | { |
| 6509 | CAN_CRITICAL_SECTION_ENTER(); |
| 6510 | ((Can *)hw)->ILS.reg ^= CAN_ILS_BEUL; |
| 6511 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6512 | } |
| 6513 | |
| 6514 | static inline void hri_can_set_ILS_ELOL_bit(const void *const hw) |
| 6515 | { |
| 6516 | CAN_CRITICAL_SECTION_ENTER(); |
| 6517 | ((Can *)hw)->ILS.reg |= CAN_ILS_ELOL; |
| 6518 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6519 | } |
| 6520 | |
| 6521 | static inline bool hri_can_get_ILS_ELOL_bit(const void *const hw) |
| 6522 | { |
| 6523 | uint32_t tmp; |
| 6524 | tmp = ((Can *)hw)->ILS.reg; |
| 6525 | tmp = (tmp & CAN_ILS_ELOL) >> CAN_ILS_ELOL_Pos; |
| 6526 | return (bool)tmp; |
| 6527 | } |
| 6528 | |
| 6529 | static inline void hri_can_write_ILS_ELOL_bit(const void *const hw, bool value) |
| 6530 | { |
| 6531 | uint32_t tmp; |
| 6532 | CAN_CRITICAL_SECTION_ENTER(); |
| 6533 | tmp = ((Can *)hw)->ILS.reg; |
| 6534 | tmp &= ~CAN_ILS_ELOL; |
| 6535 | tmp |= value << CAN_ILS_ELOL_Pos; |
| 6536 | ((Can *)hw)->ILS.reg = tmp; |
| 6537 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6538 | } |
| 6539 | |
| 6540 | static inline void hri_can_clear_ILS_ELOL_bit(const void *const hw) |
| 6541 | { |
| 6542 | CAN_CRITICAL_SECTION_ENTER(); |
| 6543 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_ELOL; |
| 6544 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6545 | } |
| 6546 | |
| 6547 | static inline void hri_can_toggle_ILS_ELOL_bit(const void *const hw) |
| 6548 | { |
| 6549 | CAN_CRITICAL_SECTION_ENTER(); |
| 6550 | ((Can *)hw)->ILS.reg ^= CAN_ILS_ELOL; |
| 6551 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6552 | } |
| 6553 | |
| 6554 | static inline void hri_can_set_ILS_EPL_bit(const void *const hw) |
| 6555 | { |
| 6556 | CAN_CRITICAL_SECTION_ENTER(); |
| 6557 | ((Can *)hw)->ILS.reg |= CAN_ILS_EPL; |
| 6558 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6559 | } |
| 6560 | |
| 6561 | static inline bool hri_can_get_ILS_EPL_bit(const void *const hw) |
| 6562 | { |
| 6563 | uint32_t tmp; |
| 6564 | tmp = ((Can *)hw)->ILS.reg; |
| 6565 | tmp = (tmp & CAN_ILS_EPL) >> CAN_ILS_EPL_Pos; |
| 6566 | return (bool)tmp; |
| 6567 | } |
| 6568 | |
| 6569 | static inline void hri_can_write_ILS_EPL_bit(const void *const hw, bool value) |
| 6570 | { |
| 6571 | uint32_t tmp; |
| 6572 | CAN_CRITICAL_SECTION_ENTER(); |
| 6573 | tmp = ((Can *)hw)->ILS.reg; |
| 6574 | tmp &= ~CAN_ILS_EPL; |
| 6575 | tmp |= value << CAN_ILS_EPL_Pos; |
| 6576 | ((Can *)hw)->ILS.reg = tmp; |
| 6577 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6578 | } |
| 6579 | |
| 6580 | static inline void hri_can_clear_ILS_EPL_bit(const void *const hw) |
| 6581 | { |
| 6582 | CAN_CRITICAL_SECTION_ENTER(); |
| 6583 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_EPL; |
| 6584 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6585 | } |
| 6586 | |
| 6587 | static inline void hri_can_toggle_ILS_EPL_bit(const void *const hw) |
| 6588 | { |
| 6589 | CAN_CRITICAL_SECTION_ENTER(); |
| 6590 | ((Can *)hw)->ILS.reg ^= CAN_ILS_EPL; |
| 6591 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6592 | } |
| 6593 | |
| 6594 | static inline void hri_can_set_ILS_EWL_bit(const void *const hw) |
| 6595 | { |
| 6596 | CAN_CRITICAL_SECTION_ENTER(); |
| 6597 | ((Can *)hw)->ILS.reg |= CAN_ILS_EWL; |
| 6598 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6599 | } |
| 6600 | |
| 6601 | static inline bool hri_can_get_ILS_EWL_bit(const void *const hw) |
| 6602 | { |
| 6603 | uint32_t tmp; |
| 6604 | tmp = ((Can *)hw)->ILS.reg; |
| 6605 | tmp = (tmp & CAN_ILS_EWL) >> CAN_ILS_EWL_Pos; |
| 6606 | return (bool)tmp; |
| 6607 | } |
| 6608 | |
| 6609 | static inline void hri_can_write_ILS_EWL_bit(const void *const hw, bool value) |
| 6610 | { |
| 6611 | uint32_t tmp; |
| 6612 | CAN_CRITICAL_SECTION_ENTER(); |
| 6613 | tmp = ((Can *)hw)->ILS.reg; |
| 6614 | tmp &= ~CAN_ILS_EWL; |
| 6615 | tmp |= value << CAN_ILS_EWL_Pos; |
| 6616 | ((Can *)hw)->ILS.reg = tmp; |
| 6617 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6618 | } |
| 6619 | |
| 6620 | static inline void hri_can_clear_ILS_EWL_bit(const void *const hw) |
| 6621 | { |
| 6622 | CAN_CRITICAL_SECTION_ENTER(); |
| 6623 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_EWL; |
| 6624 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6625 | } |
| 6626 | |
| 6627 | static inline void hri_can_toggle_ILS_EWL_bit(const void *const hw) |
| 6628 | { |
| 6629 | CAN_CRITICAL_SECTION_ENTER(); |
| 6630 | ((Can *)hw)->ILS.reg ^= CAN_ILS_EWL; |
| 6631 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6632 | } |
| 6633 | |
| 6634 | static inline void hri_can_set_ILS_BOL_bit(const void *const hw) |
| 6635 | { |
| 6636 | CAN_CRITICAL_SECTION_ENTER(); |
| 6637 | ((Can *)hw)->ILS.reg |= CAN_ILS_BOL; |
| 6638 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6639 | } |
| 6640 | |
| 6641 | static inline bool hri_can_get_ILS_BOL_bit(const void *const hw) |
| 6642 | { |
| 6643 | uint32_t tmp; |
| 6644 | tmp = ((Can *)hw)->ILS.reg; |
| 6645 | tmp = (tmp & CAN_ILS_BOL) >> CAN_ILS_BOL_Pos; |
| 6646 | return (bool)tmp; |
| 6647 | } |
| 6648 | |
| 6649 | static inline void hri_can_write_ILS_BOL_bit(const void *const hw, bool value) |
| 6650 | { |
| 6651 | uint32_t tmp; |
| 6652 | CAN_CRITICAL_SECTION_ENTER(); |
| 6653 | tmp = ((Can *)hw)->ILS.reg; |
| 6654 | tmp &= ~CAN_ILS_BOL; |
| 6655 | tmp |= value << CAN_ILS_BOL_Pos; |
| 6656 | ((Can *)hw)->ILS.reg = tmp; |
| 6657 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6658 | } |
| 6659 | |
| 6660 | static inline void hri_can_clear_ILS_BOL_bit(const void *const hw) |
| 6661 | { |
| 6662 | CAN_CRITICAL_SECTION_ENTER(); |
| 6663 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_BOL; |
| 6664 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6665 | } |
| 6666 | |
| 6667 | static inline void hri_can_toggle_ILS_BOL_bit(const void *const hw) |
| 6668 | { |
| 6669 | CAN_CRITICAL_SECTION_ENTER(); |
| 6670 | ((Can *)hw)->ILS.reg ^= CAN_ILS_BOL; |
| 6671 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6672 | } |
| 6673 | |
| 6674 | static inline void hri_can_set_ILS_WDIL_bit(const void *const hw) |
| 6675 | { |
| 6676 | CAN_CRITICAL_SECTION_ENTER(); |
| 6677 | ((Can *)hw)->ILS.reg |= CAN_ILS_WDIL; |
| 6678 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6679 | } |
| 6680 | |
| 6681 | static inline bool hri_can_get_ILS_WDIL_bit(const void *const hw) |
| 6682 | { |
| 6683 | uint32_t tmp; |
| 6684 | tmp = ((Can *)hw)->ILS.reg; |
| 6685 | tmp = (tmp & CAN_ILS_WDIL) >> CAN_ILS_WDIL_Pos; |
| 6686 | return (bool)tmp; |
| 6687 | } |
| 6688 | |
| 6689 | static inline void hri_can_write_ILS_WDIL_bit(const void *const hw, bool value) |
| 6690 | { |
| 6691 | uint32_t tmp; |
| 6692 | CAN_CRITICAL_SECTION_ENTER(); |
| 6693 | tmp = ((Can *)hw)->ILS.reg; |
| 6694 | tmp &= ~CAN_ILS_WDIL; |
| 6695 | tmp |= value << CAN_ILS_WDIL_Pos; |
| 6696 | ((Can *)hw)->ILS.reg = tmp; |
| 6697 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6698 | } |
| 6699 | |
| 6700 | static inline void hri_can_clear_ILS_WDIL_bit(const void *const hw) |
| 6701 | { |
| 6702 | CAN_CRITICAL_SECTION_ENTER(); |
| 6703 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_WDIL; |
| 6704 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6705 | } |
| 6706 | |
| 6707 | static inline void hri_can_toggle_ILS_WDIL_bit(const void *const hw) |
| 6708 | { |
| 6709 | CAN_CRITICAL_SECTION_ENTER(); |
| 6710 | ((Can *)hw)->ILS.reg ^= CAN_ILS_WDIL; |
| 6711 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6712 | } |
| 6713 | |
| 6714 | static inline void hri_can_set_ILS_PEAL_bit(const void *const hw) |
| 6715 | { |
| 6716 | CAN_CRITICAL_SECTION_ENTER(); |
| 6717 | ((Can *)hw)->ILS.reg |= CAN_ILS_PEAL; |
| 6718 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6719 | } |
| 6720 | |
| 6721 | static inline bool hri_can_get_ILS_PEAL_bit(const void *const hw) |
| 6722 | { |
| 6723 | uint32_t tmp; |
| 6724 | tmp = ((Can *)hw)->ILS.reg; |
| 6725 | tmp = (tmp & CAN_ILS_PEAL) >> CAN_ILS_PEAL_Pos; |
| 6726 | return (bool)tmp; |
| 6727 | } |
| 6728 | |
| 6729 | static inline void hri_can_write_ILS_PEAL_bit(const void *const hw, bool value) |
| 6730 | { |
| 6731 | uint32_t tmp; |
| 6732 | CAN_CRITICAL_SECTION_ENTER(); |
| 6733 | tmp = ((Can *)hw)->ILS.reg; |
| 6734 | tmp &= ~CAN_ILS_PEAL; |
| 6735 | tmp |= value << CAN_ILS_PEAL_Pos; |
| 6736 | ((Can *)hw)->ILS.reg = tmp; |
| 6737 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6738 | } |
| 6739 | |
| 6740 | static inline void hri_can_clear_ILS_PEAL_bit(const void *const hw) |
| 6741 | { |
| 6742 | CAN_CRITICAL_SECTION_ENTER(); |
| 6743 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_PEAL; |
| 6744 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6745 | } |
| 6746 | |
| 6747 | static inline void hri_can_toggle_ILS_PEAL_bit(const void *const hw) |
| 6748 | { |
| 6749 | CAN_CRITICAL_SECTION_ENTER(); |
| 6750 | ((Can *)hw)->ILS.reg ^= CAN_ILS_PEAL; |
| 6751 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6752 | } |
| 6753 | |
| 6754 | static inline void hri_can_set_ILS_PEDL_bit(const void *const hw) |
| 6755 | { |
| 6756 | CAN_CRITICAL_SECTION_ENTER(); |
| 6757 | ((Can *)hw)->ILS.reg |= CAN_ILS_PEDL; |
| 6758 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6759 | } |
| 6760 | |
| 6761 | static inline bool hri_can_get_ILS_PEDL_bit(const void *const hw) |
| 6762 | { |
| 6763 | uint32_t tmp; |
| 6764 | tmp = ((Can *)hw)->ILS.reg; |
| 6765 | tmp = (tmp & CAN_ILS_PEDL) >> CAN_ILS_PEDL_Pos; |
| 6766 | return (bool)tmp; |
| 6767 | } |
| 6768 | |
| 6769 | static inline void hri_can_write_ILS_PEDL_bit(const void *const hw, bool value) |
| 6770 | { |
| 6771 | uint32_t tmp; |
| 6772 | CAN_CRITICAL_SECTION_ENTER(); |
| 6773 | tmp = ((Can *)hw)->ILS.reg; |
| 6774 | tmp &= ~CAN_ILS_PEDL; |
| 6775 | tmp |= value << CAN_ILS_PEDL_Pos; |
| 6776 | ((Can *)hw)->ILS.reg = tmp; |
| 6777 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6778 | } |
| 6779 | |
| 6780 | static inline void hri_can_clear_ILS_PEDL_bit(const void *const hw) |
| 6781 | { |
| 6782 | CAN_CRITICAL_SECTION_ENTER(); |
| 6783 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_PEDL; |
| 6784 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6785 | } |
| 6786 | |
| 6787 | static inline void hri_can_toggle_ILS_PEDL_bit(const void *const hw) |
| 6788 | { |
| 6789 | CAN_CRITICAL_SECTION_ENTER(); |
| 6790 | ((Can *)hw)->ILS.reg ^= CAN_ILS_PEDL; |
| 6791 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6792 | } |
| 6793 | |
| 6794 | static inline void hri_can_set_ILS_ARAL_bit(const void *const hw) |
| 6795 | { |
| 6796 | CAN_CRITICAL_SECTION_ENTER(); |
| 6797 | ((Can *)hw)->ILS.reg |= CAN_ILS_ARAL; |
| 6798 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6799 | } |
| 6800 | |
| 6801 | static inline bool hri_can_get_ILS_ARAL_bit(const void *const hw) |
| 6802 | { |
| 6803 | uint32_t tmp; |
| 6804 | tmp = ((Can *)hw)->ILS.reg; |
| 6805 | tmp = (tmp & CAN_ILS_ARAL) >> CAN_ILS_ARAL_Pos; |
| 6806 | return (bool)tmp; |
| 6807 | } |
| 6808 | |
| 6809 | static inline void hri_can_write_ILS_ARAL_bit(const void *const hw, bool value) |
| 6810 | { |
| 6811 | uint32_t tmp; |
| 6812 | CAN_CRITICAL_SECTION_ENTER(); |
| 6813 | tmp = ((Can *)hw)->ILS.reg; |
| 6814 | tmp &= ~CAN_ILS_ARAL; |
| 6815 | tmp |= value << CAN_ILS_ARAL_Pos; |
| 6816 | ((Can *)hw)->ILS.reg = tmp; |
| 6817 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6818 | } |
| 6819 | |
| 6820 | static inline void hri_can_clear_ILS_ARAL_bit(const void *const hw) |
| 6821 | { |
| 6822 | CAN_CRITICAL_SECTION_ENTER(); |
| 6823 | ((Can *)hw)->ILS.reg &= ~CAN_ILS_ARAL; |
| 6824 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6825 | } |
| 6826 | |
| 6827 | static inline void hri_can_toggle_ILS_ARAL_bit(const void *const hw) |
| 6828 | { |
| 6829 | CAN_CRITICAL_SECTION_ENTER(); |
| 6830 | ((Can *)hw)->ILS.reg ^= CAN_ILS_ARAL; |
| 6831 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6832 | } |
| 6833 | |
| 6834 | static inline void hri_can_set_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) |
| 6835 | { |
| 6836 | CAN_CRITICAL_SECTION_ENTER(); |
| 6837 | ((Can *)hw)->ILS.reg |= mask; |
| 6838 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6839 | } |
| 6840 | |
| 6841 | static inline hri_can_ils_reg_t hri_can_get_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) |
| 6842 | { |
| 6843 | uint32_t tmp; |
| 6844 | tmp = ((Can *)hw)->ILS.reg; |
| 6845 | tmp &= mask; |
| 6846 | return tmp; |
| 6847 | } |
| 6848 | |
| 6849 | static inline void hri_can_write_ILS_reg(const void *const hw, hri_can_ils_reg_t data) |
| 6850 | { |
| 6851 | CAN_CRITICAL_SECTION_ENTER(); |
| 6852 | ((Can *)hw)->ILS.reg = data; |
| 6853 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6854 | } |
| 6855 | |
| 6856 | static inline void hri_can_clear_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) |
| 6857 | { |
| 6858 | CAN_CRITICAL_SECTION_ENTER(); |
| 6859 | ((Can *)hw)->ILS.reg &= ~mask; |
| 6860 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6861 | } |
| 6862 | |
| 6863 | static inline void hri_can_toggle_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) |
| 6864 | { |
| 6865 | CAN_CRITICAL_SECTION_ENTER(); |
| 6866 | ((Can *)hw)->ILS.reg ^= mask; |
| 6867 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6868 | } |
| 6869 | |
| 6870 | static inline hri_can_ils_reg_t hri_can_read_ILS_reg(const void *const hw) |
| 6871 | { |
| 6872 | return ((Can *)hw)->ILS.reg; |
| 6873 | } |
| 6874 | |
| 6875 | static inline void hri_can_set_ILE_EINT0_bit(const void *const hw) |
| 6876 | { |
| 6877 | CAN_CRITICAL_SECTION_ENTER(); |
| 6878 | ((Can *)hw)->ILE.reg |= CAN_ILE_EINT0; |
| 6879 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6880 | } |
| 6881 | |
| 6882 | static inline bool hri_can_get_ILE_EINT0_bit(const void *const hw) |
| 6883 | { |
| 6884 | uint32_t tmp; |
| 6885 | tmp = ((Can *)hw)->ILE.reg; |
| 6886 | tmp = (tmp & CAN_ILE_EINT0) >> CAN_ILE_EINT0_Pos; |
| 6887 | return (bool)tmp; |
| 6888 | } |
| 6889 | |
| 6890 | static inline void hri_can_write_ILE_EINT0_bit(const void *const hw, bool value) |
| 6891 | { |
| 6892 | uint32_t tmp; |
| 6893 | CAN_CRITICAL_SECTION_ENTER(); |
| 6894 | tmp = ((Can *)hw)->ILE.reg; |
| 6895 | tmp &= ~CAN_ILE_EINT0; |
| 6896 | tmp |= value << CAN_ILE_EINT0_Pos; |
| 6897 | ((Can *)hw)->ILE.reg = tmp; |
| 6898 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6899 | } |
| 6900 | |
| 6901 | static inline void hri_can_clear_ILE_EINT0_bit(const void *const hw) |
| 6902 | { |
| 6903 | CAN_CRITICAL_SECTION_ENTER(); |
| 6904 | ((Can *)hw)->ILE.reg &= ~CAN_ILE_EINT0; |
| 6905 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6906 | } |
| 6907 | |
| 6908 | static inline void hri_can_toggle_ILE_EINT0_bit(const void *const hw) |
| 6909 | { |
| 6910 | CAN_CRITICAL_SECTION_ENTER(); |
| 6911 | ((Can *)hw)->ILE.reg ^= CAN_ILE_EINT0; |
| 6912 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6913 | } |
| 6914 | |
| 6915 | static inline void hri_can_set_ILE_EINT1_bit(const void *const hw) |
| 6916 | { |
| 6917 | CAN_CRITICAL_SECTION_ENTER(); |
| 6918 | ((Can *)hw)->ILE.reg |= CAN_ILE_EINT1; |
| 6919 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6920 | } |
| 6921 | |
| 6922 | static inline bool hri_can_get_ILE_EINT1_bit(const void *const hw) |
| 6923 | { |
| 6924 | uint32_t tmp; |
| 6925 | tmp = ((Can *)hw)->ILE.reg; |
| 6926 | tmp = (tmp & CAN_ILE_EINT1) >> CAN_ILE_EINT1_Pos; |
| 6927 | return (bool)tmp; |
| 6928 | } |
| 6929 | |
| 6930 | static inline void hri_can_write_ILE_EINT1_bit(const void *const hw, bool value) |
| 6931 | { |
| 6932 | uint32_t tmp; |
| 6933 | CAN_CRITICAL_SECTION_ENTER(); |
| 6934 | tmp = ((Can *)hw)->ILE.reg; |
| 6935 | tmp &= ~CAN_ILE_EINT1; |
| 6936 | tmp |= value << CAN_ILE_EINT1_Pos; |
| 6937 | ((Can *)hw)->ILE.reg = tmp; |
| 6938 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6939 | } |
| 6940 | |
| 6941 | static inline void hri_can_clear_ILE_EINT1_bit(const void *const hw) |
| 6942 | { |
| 6943 | CAN_CRITICAL_SECTION_ENTER(); |
| 6944 | ((Can *)hw)->ILE.reg &= ~CAN_ILE_EINT1; |
| 6945 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6946 | } |
| 6947 | |
| 6948 | static inline void hri_can_toggle_ILE_EINT1_bit(const void *const hw) |
| 6949 | { |
| 6950 | CAN_CRITICAL_SECTION_ENTER(); |
| 6951 | ((Can *)hw)->ILE.reg ^= CAN_ILE_EINT1; |
| 6952 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6953 | } |
| 6954 | |
| 6955 | static inline void hri_can_set_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) |
| 6956 | { |
| 6957 | CAN_CRITICAL_SECTION_ENTER(); |
| 6958 | ((Can *)hw)->ILE.reg |= mask; |
| 6959 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6960 | } |
| 6961 | |
| 6962 | static inline hri_can_ile_reg_t hri_can_get_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) |
| 6963 | { |
| 6964 | uint32_t tmp; |
| 6965 | tmp = ((Can *)hw)->ILE.reg; |
| 6966 | tmp &= mask; |
| 6967 | return tmp; |
| 6968 | } |
| 6969 | |
| 6970 | static inline void hri_can_write_ILE_reg(const void *const hw, hri_can_ile_reg_t data) |
| 6971 | { |
| 6972 | CAN_CRITICAL_SECTION_ENTER(); |
| 6973 | ((Can *)hw)->ILE.reg = data; |
| 6974 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6975 | } |
| 6976 | |
| 6977 | static inline void hri_can_clear_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) |
| 6978 | { |
| 6979 | CAN_CRITICAL_SECTION_ENTER(); |
| 6980 | ((Can *)hw)->ILE.reg &= ~mask; |
| 6981 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6982 | } |
| 6983 | |
| 6984 | static inline void hri_can_toggle_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) |
| 6985 | { |
| 6986 | CAN_CRITICAL_SECTION_ENTER(); |
| 6987 | ((Can *)hw)->ILE.reg ^= mask; |
| 6988 | CAN_CRITICAL_SECTION_LEAVE(); |
| 6989 | } |
| 6990 | |
| 6991 | static inline hri_can_ile_reg_t hri_can_read_ILE_reg(const void *const hw) |
| 6992 | { |
| 6993 | return ((Can *)hw)->ILE.reg; |
| 6994 | } |
| 6995 | |
| 6996 | static inline void hri_can_set_GFC_RRFE_bit(const void *const hw) |
| 6997 | { |
| 6998 | CAN_CRITICAL_SECTION_ENTER(); |
| 6999 | ((Can *)hw)->GFC.reg |= CAN_GFC_RRFE; |
| 7000 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7001 | } |
| 7002 | |
| 7003 | static inline bool hri_can_get_GFC_RRFE_bit(const void *const hw) |
| 7004 | { |
| 7005 | uint32_t tmp; |
| 7006 | tmp = ((Can *)hw)->GFC.reg; |
| 7007 | tmp = (tmp & CAN_GFC_RRFE) >> CAN_GFC_RRFE_Pos; |
| 7008 | return (bool)tmp; |
| 7009 | } |
| 7010 | |
| 7011 | static inline void hri_can_write_GFC_RRFE_bit(const void *const hw, bool value) |
| 7012 | { |
| 7013 | uint32_t tmp; |
| 7014 | CAN_CRITICAL_SECTION_ENTER(); |
| 7015 | tmp = ((Can *)hw)->GFC.reg; |
| 7016 | tmp &= ~CAN_GFC_RRFE; |
| 7017 | tmp |= value << CAN_GFC_RRFE_Pos; |
| 7018 | ((Can *)hw)->GFC.reg = tmp; |
| 7019 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7020 | } |
| 7021 | |
| 7022 | static inline void hri_can_clear_GFC_RRFE_bit(const void *const hw) |
| 7023 | { |
| 7024 | CAN_CRITICAL_SECTION_ENTER(); |
| 7025 | ((Can *)hw)->GFC.reg &= ~CAN_GFC_RRFE; |
| 7026 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7027 | } |
| 7028 | |
| 7029 | static inline void hri_can_toggle_GFC_RRFE_bit(const void *const hw) |
| 7030 | { |
| 7031 | CAN_CRITICAL_SECTION_ENTER(); |
| 7032 | ((Can *)hw)->GFC.reg ^= CAN_GFC_RRFE; |
| 7033 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7034 | } |
| 7035 | |
| 7036 | static inline void hri_can_set_GFC_RRFS_bit(const void *const hw) |
| 7037 | { |
| 7038 | CAN_CRITICAL_SECTION_ENTER(); |
| 7039 | ((Can *)hw)->GFC.reg |= CAN_GFC_RRFS; |
| 7040 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7041 | } |
| 7042 | |
| 7043 | static inline bool hri_can_get_GFC_RRFS_bit(const void *const hw) |
| 7044 | { |
| 7045 | uint32_t tmp; |
| 7046 | tmp = ((Can *)hw)->GFC.reg; |
| 7047 | tmp = (tmp & CAN_GFC_RRFS) >> CAN_GFC_RRFS_Pos; |
| 7048 | return (bool)tmp; |
| 7049 | } |
| 7050 | |
| 7051 | static inline void hri_can_write_GFC_RRFS_bit(const void *const hw, bool value) |
| 7052 | { |
| 7053 | uint32_t tmp; |
| 7054 | CAN_CRITICAL_SECTION_ENTER(); |
| 7055 | tmp = ((Can *)hw)->GFC.reg; |
| 7056 | tmp &= ~CAN_GFC_RRFS; |
| 7057 | tmp |= value << CAN_GFC_RRFS_Pos; |
| 7058 | ((Can *)hw)->GFC.reg = tmp; |
| 7059 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7060 | } |
| 7061 | |
| 7062 | static inline void hri_can_clear_GFC_RRFS_bit(const void *const hw) |
| 7063 | { |
| 7064 | CAN_CRITICAL_SECTION_ENTER(); |
| 7065 | ((Can *)hw)->GFC.reg &= ~CAN_GFC_RRFS; |
| 7066 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7067 | } |
| 7068 | |
| 7069 | static inline void hri_can_toggle_GFC_RRFS_bit(const void *const hw) |
| 7070 | { |
| 7071 | CAN_CRITICAL_SECTION_ENTER(); |
| 7072 | ((Can *)hw)->GFC.reg ^= CAN_GFC_RRFS; |
| 7073 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7074 | } |
| 7075 | |
| 7076 | static inline void hri_can_set_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) |
| 7077 | { |
| 7078 | CAN_CRITICAL_SECTION_ENTER(); |
| 7079 | ((Can *)hw)->GFC.reg |= CAN_GFC_ANFE(mask); |
| 7080 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7081 | } |
| 7082 | |
| 7083 | static inline hri_can_gfc_reg_t hri_can_get_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) |
| 7084 | { |
| 7085 | uint32_t tmp; |
| 7086 | tmp = ((Can *)hw)->GFC.reg; |
| 7087 | tmp = (tmp & CAN_GFC_ANFE(mask)) >> CAN_GFC_ANFE_Pos; |
| 7088 | return tmp; |
| 7089 | } |
| 7090 | |
| 7091 | static inline void hri_can_write_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t data) |
| 7092 | { |
| 7093 | uint32_t tmp; |
| 7094 | CAN_CRITICAL_SECTION_ENTER(); |
| 7095 | tmp = ((Can *)hw)->GFC.reg; |
| 7096 | tmp &= ~CAN_GFC_ANFE_Msk; |
| 7097 | tmp |= CAN_GFC_ANFE(data); |
| 7098 | ((Can *)hw)->GFC.reg = tmp; |
| 7099 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7100 | } |
| 7101 | |
| 7102 | static inline void hri_can_clear_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) |
| 7103 | { |
| 7104 | CAN_CRITICAL_SECTION_ENTER(); |
| 7105 | ((Can *)hw)->GFC.reg &= ~CAN_GFC_ANFE(mask); |
| 7106 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7107 | } |
| 7108 | |
| 7109 | static inline void hri_can_toggle_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) |
| 7110 | { |
| 7111 | CAN_CRITICAL_SECTION_ENTER(); |
| 7112 | ((Can *)hw)->GFC.reg ^= CAN_GFC_ANFE(mask); |
| 7113 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7114 | } |
| 7115 | |
| 7116 | static inline hri_can_gfc_reg_t hri_can_read_GFC_ANFE_bf(const void *const hw) |
| 7117 | { |
| 7118 | uint32_t tmp; |
| 7119 | tmp = ((Can *)hw)->GFC.reg; |
| 7120 | tmp = (tmp & CAN_GFC_ANFE_Msk) >> CAN_GFC_ANFE_Pos; |
| 7121 | return tmp; |
| 7122 | } |
| 7123 | |
| 7124 | static inline void hri_can_set_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) |
| 7125 | { |
| 7126 | CAN_CRITICAL_SECTION_ENTER(); |
| 7127 | ((Can *)hw)->GFC.reg |= CAN_GFC_ANFS(mask); |
| 7128 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7129 | } |
| 7130 | |
| 7131 | static inline hri_can_gfc_reg_t hri_can_get_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) |
| 7132 | { |
| 7133 | uint32_t tmp; |
| 7134 | tmp = ((Can *)hw)->GFC.reg; |
| 7135 | tmp = (tmp & CAN_GFC_ANFS(mask)) >> CAN_GFC_ANFS_Pos; |
| 7136 | return tmp; |
| 7137 | } |
| 7138 | |
| 7139 | static inline void hri_can_write_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t data) |
| 7140 | { |
| 7141 | uint32_t tmp; |
| 7142 | CAN_CRITICAL_SECTION_ENTER(); |
| 7143 | tmp = ((Can *)hw)->GFC.reg; |
| 7144 | tmp &= ~CAN_GFC_ANFS_Msk; |
| 7145 | tmp |= CAN_GFC_ANFS(data); |
| 7146 | ((Can *)hw)->GFC.reg = tmp; |
| 7147 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7148 | } |
| 7149 | |
| 7150 | static inline void hri_can_clear_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) |
| 7151 | { |
| 7152 | CAN_CRITICAL_SECTION_ENTER(); |
| 7153 | ((Can *)hw)->GFC.reg &= ~CAN_GFC_ANFS(mask); |
| 7154 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7155 | } |
| 7156 | |
| 7157 | static inline void hri_can_toggle_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) |
| 7158 | { |
| 7159 | CAN_CRITICAL_SECTION_ENTER(); |
| 7160 | ((Can *)hw)->GFC.reg ^= CAN_GFC_ANFS(mask); |
| 7161 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7162 | } |
| 7163 | |
| 7164 | static inline hri_can_gfc_reg_t hri_can_read_GFC_ANFS_bf(const void *const hw) |
| 7165 | { |
| 7166 | uint32_t tmp; |
| 7167 | tmp = ((Can *)hw)->GFC.reg; |
| 7168 | tmp = (tmp & CAN_GFC_ANFS_Msk) >> CAN_GFC_ANFS_Pos; |
| 7169 | return tmp; |
| 7170 | } |
| 7171 | |
| 7172 | static inline void hri_can_set_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) |
| 7173 | { |
| 7174 | CAN_CRITICAL_SECTION_ENTER(); |
| 7175 | ((Can *)hw)->GFC.reg |= mask; |
| 7176 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7177 | } |
| 7178 | |
| 7179 | static inline hri_can_gfc_reg_t hri_can_get_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) |
| 7180 | { |
| 7181 | uint32_t tmp; |
| 7182 | tmp = ((Can *)hw)->GFC.reg; |
| 7183 | tmp &= mask; |
| 7184 | return tmp; |
| 7185 | } |
| 7186 | |
| 7187 | static inline void hri_can_write_GFC_reg(const void *const hw, hri_can_gfc_reg_t data) |
| 7188 | { |
| 7189 | CAN_CRITICAL_SECTION_ENTER(); |
| 7190 | ((Can *)hw)->GFC.reg = data; |
| 7191 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7192 | } |
| 7193 | |
| 7194 | static inline void hri_can_clear_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) |
| 7195 | { |
| 7196 | CAN_CRITICAL_SECTION_ENTER(); |
| 7197 | ((Can *)hw)->GFC.reg &= ~mask; |
| 7198 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7199 | } |
| 7200 | |
| 7201 | static inline void hri_can_toggle_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) |
| 7202 | { |
| 7203 | CAN_CRITICAL_SECTION_ENTER(); |
| 7204 | ((Can *)hw)->GFC.reg ^= mask; |
| 7205 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7206 | } |
| 7207 | |
| 7208 | static inline hri_can_gfc_reg_t hri_can_read_GFC_reg(const void *const hw) |
| 7209 | { |
| 7210 | return ((Can *)hw)->GFC.reg; |
| 7211 | } |
| 7212 | |
| 7213 | static inline void hri_can_set_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) |
| 7214 | { |
| 7215 | CAN_CRITICAL_SECTION_ENTER(); |
| 7216 | ((Can *)hw)->SIDFC.reg |= CAN_SIDFC_FLSSA(mask); |
| 7217 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7218 | } |
| 7219 | |
| 7220 | static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) |
| 7221 | { |
| 7222 | uint32_t tmp; |
| 7223 | tmp = ((Can *)hw)->SIDFC.reg; |
| 7224 | tmp = (tmp & CAN_SIDFC_FLSSA(mask)) >> CAN_SIDFC_FLSSA_Pos; |
| 7225 | return tmp; |
| 7226 | } |
| 7227 | |
| 7228 | static inline void hri_can_write_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t data) |
| 7229 | { |
| 7230 | uint32_t tmp; |
| 7231 | CAN_CRITICAL_SECTION_ENTER(); |
| 7232 | tmp = ((Can *)hw)->SIDFC.reg; |
| 7233 | tmp &= ~CAN_SIDFC_FLSSA_Msk; |
| 7234 | tmp |= CAN_SIDFC_FLSSA(data); |
| 7235 | ((Can *)hw)->SIDFC.reg = tmp; |
| 7236 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7237 | } |
| 7238 | |
| 7239 | static inline void hri_can_clear_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) |
| 7240 | { |
| 7241 | CAN_CRITICAL_SECTION_ENTER(); |
| 7242 | ((Can *)hw)->SIDFC.reg &= ~CAN_SIDFC_FLSSA(mask); |
| 7243 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7244 | } |
| 7245 | |
| 7246 | static inline void hri_can_toggle_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) |
| 7247 | { |
| 7248 | CAN_CRITICAL_SECTION_ENTER(); |
| 7249 | ((Can *)hw)->SIDFC.reg ^= CAN_SIDFC_FLSSA(mask); |
| 7250 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7251 | } |
| 7252 | |
| 7253 | static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_FLSSA_bf(const void *const hw) |
| 7254 | { |
| 7255 | uint32_t tmp; |
| 7256 | tmp = ((Can *)hw)->SIDFC.reg; |
| 7257 | tmp = (tmp & CAN_SIDFC_FLSSA_Msk) >> CAN_SIDFC_FLSSA_Pos; |
| 7258 | return tmp; |
| 7259 | } |
| 7260 | |
| 7261 | static inline void hri_can_set_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) |
| 7262 | { |
| 7263 | CAN_CRITICAL_SECTION_ENTER(); |
| 7264 | ((Can *)hw)->SIDFC.reg |= CAN_SIDFC_LSS(mask); |
| 7265 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7266 | } |
| 7267 | |
| 7268 | static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) |
| 7269 | { |
| 7270 | uint32_t tmp; |
| 7271 | tmp = ((Can *)hw)->SIDFC.reg; |
| 7272 | tmp = (tmp & CAN_SIDFC_LSS(mask)) >> CAN_SIDFC_LSS_Pos; |
| 7273 | return tmp; |
| 7274 | } |
| 7275 | |
| 7276 | static inline void hri_can_write_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t data) |
| 7277 | { |
| 7278 | uint32_t tmp; |
| 7279 | CAN_CRITICAL_SECTION_ENTER(); |
| 7280 | tmp = ((Can *)hw)->SIDFC.reg; |
| 7281 | tmp &= ~CAN_SIDFC_LSS_Msk; |
| 7282 | tmp |= CAN_SIDFC_LSS(data); |
| 7283 | ((Can *)hw)->SIDFC.reg = tmp; |
| 7284 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7285 | } |
| 7286 | |
| 7287 | static inline void hri_can_clear_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) |
| 7288 | { |
| 7289 | CAN_CRITICAL_SECTION_ENTER(); |
| 7290 | ((Can *)hw)->SIDFC.reg &= ~CAN_SIDFC_LSS(mask); |
| 7291 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7292 | } |
| 7293 | |
| 7294 | static inline void hri_can_toggle_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) |
| 7295 | { |
| 7296 | CAN_CRITICAL_SECTION_ENTER(); |
| 7297 | ((Can *)hw)->SIDFC.reg ^= CAN_SIDFC_LSS(mask); |
| 7298 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7299 | } |
| 7300 | |
| 7301 | static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_LSS_bf(const void *const hw) |
| 7302 | { |
| 7303 | uint32_t tmp; |
| 7304 | tmp = ((Can *)hw)->SIDFC.reg; |
| 7305 | tmp = (tmp & CAN_SIDFC_LSS_Msk) >> CAN_SIDFC_LSS_Pos; |
| 7306 | return tmp; |
| 7307 | } |
| 7308 | |
| 7309 | static inline void hri_can_set_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) |
| 7310 | { |
| 7311 | CAN_CRITICAL_SECTION_ENTER(); |
| 7312 | ((Can *)hw)->SIDFC.reg |= mask; |
| 7313 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7314 | } |
| 7315 | |
| 7316 | static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) |
| 7317 | { |
| 7318 | uint32_t tmp; |
| 7319 | tmp = ((Can *)hw)->SIDFC.reg; |
| 7320 | tmp &= mask; |
| 7321 | return tmp; |
| 7322 | } |
| 7323 | |
| 7324 | static inline void hri_can_write_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t data) |
| 7325 | { |
| 7326 | CAN_CRITICAL_SECTION_ENTER(); |
| 7327 | ((Can *)hw)->SIDFC.reg = data; |
| 7328 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7329 | } |
| 7330 | |
| 7331 | static inline void hri_can_clear_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) |
| 7332 | { |
| 7333 | CAN_CRITICAL_SECTION_ENTER(); |
| 7334 | ((Can *)hw)->SIDFC.reg &= ~mask; |
| 7335 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7336 | } |
| 7337 | |
| 7338 | static inline void hri_can_toggle_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) |
| 7339 | { |
| 7340 | CAN_CRITICAL_SECTION_ENTER(); |
| 7341 | ((Can *)hw)->SIDFC.reg ^= mask; |
| 7342 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7343 | } |
| 7344 | |
| 7345 | static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_reg(const void *const hw) |
| 7346 | { |
| 7347 | return ((Can *)hw)->SIDFC.reg; |
| 7348 | } |
| 7349 | |
| 7350 | static inline void hri_can_set_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) |
| 7351 | { |
| 7352 | CAN_CRITICAL_SECTION_ENTER(); |
| 7353 | ((Can *)hw)->XIDFC.reg |= CAN_XIDFC_FLESA(mask); |
| 7354 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7355 | } |
| 7356 | |
| 7357 | static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) |
| 7358 | { |
| 7359 | uint32_t tmp; |
| 7360 | tmp = ((Can *)hw)->XIDFC.reg; |
| 7361 | tmp = (tmp & CAN_XIDFC_FLESA(mask)) >> CAN_XIDFC_FLESA_Pos; |
| 7362 | return tmp; |
| 7363 | } |
| 7364 | |
| 7365 | static inline void hri_can_write_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t data) |
| 7366 | { |
| 7367 | uint32_t tmp; |
| 7368 | CAN_CRITICAL_SECTION_ENTER(); |
| 7369 | tmp = ((Can *)hw)->XIDFC.reg; |
| 7370 | tmp &= ~CAN_XIDFC_FLESA_Msk; |
| 7371 | tmp |= CAN_XIDFC_FLESA(data); |
| 7372 | ((Can *)hw)->XIDFC.reg = tmp; |
| 7373 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7374 | } |
| 7375 | |
| 7376 | static inline void hri_can_clear_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) |
| 7377 | { |
| 7378 | CAN_CRITICAL_SECTION_ENTER(); |
| 7379 | ((Can *)hw)->XIDFC.reg &= ~CAN_XIDFC_FLESA(mask); |
| 7380 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7381 | } |
| 7382 | |
| 7383 | static inline void hri_can_toggle_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) |
| 7384 | { |
| 7385 | CAN_CRITICAL_SECTION_ENTER(); |
| 7386 | ((Can *)hw)->XIDFC.reg ^= CAN_XIDFC_FLESA(mask); |
| 7387 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7388 | } |
| 7389 | |
| 7390 | static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_FLESA_bf(const void *const hw) |
| 7391 | { |
| 7392 | uint32_t tmp; |
| 7393 | tmp = ((Can *)hw)->XIDFC.reg; |
| 7394 | tmp = (tmp & CAN_XIDFC_FLESA_Msk) >> CAN_XIDFC_FLESA_Pos; |
| 7395 | return tmp; |
| 7396 | } |
| 7397 | |
| 7398 | static inline void hri_can_set_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) |
| 7399 | { |
| 7400 | CAN_CRITICAL_SECTION_ENTER(); |
| 7401 | ((Can *)hw)->XIDFC.reg |= CAN_XIDFC_LSE(mask); |
| 7402 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7403 | } |
| 7404 | |
| 7405 | static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) |
| 7406 | { |
| 7407 | uint32_t tmp; |
| 7408 | tmp = ((Can *)hw)->XIDFC.reg; |
| 7409 | tmp = (tmp & CAN_XIDFC_LSE(mask)) >> CAN_XIDFC_LSE_Pos; |
| 7410 | return tmp; |
| 7411 | } |
| 7412 | |
| 7413 | static inline void hri_can_write_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t data) |
| 7414 | { |
| 7415 | uint32_t tmp; |
| 7416 | CAN_CRITICAL_SECTION_ENTER(); |
| 7417 | tmp = ((Can *)hw)->XIDFC.reg; |
| 7418 | tmp &= ~CAN_XIDFC_LSE_Msk; |
| 7419 | tmp |= CAN_XIDFC_LSE(data); |
| 7420 | ((Can *)hw)->XIDFC.reg = tmp; |
| 7421 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7422 | } |
| 7423 | |
| 7424 | static inline void hri_can_clear_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) |
| 7425 | { |
| 7426 | CAN_CRITICAL_SECTION_ENTER(); |
| 7427 | ((Can *)hw)->XIDFC.reg &= ~CAN_XIDFC_LSE(mask); |
| 7428 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7429 | } |
| 7430 | |
| 7431 | static inline void hri_can_toggle_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) |
| 7432 | { |
| 7433 | CAN_CRITICAL_SECTION_ENTER(); |
| 7434 | ((Can *)hw)->XIDFC.reg ^= CAN_XIDFC_LSE(mask); |
| 7435 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7436 | } |
| 7437 | |
| 7438 | static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_LSE_bf(const void *const hw) |
| 7439 | { |
| 7440 | uint32_t tmp; |
| 7441 | tmp = ((Can *)hw)->XIDFC.reg; |
| 7442 | tmp = (tmp & CAN_XIDFC_LSE_Msk) >> CAN_XIDFC_LSE_Pos; |
| 7443 | return tmp; |
| 7444 | } |
| 7445 | |
| 7446 | static inline void hri_can_set_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) |
| 7447 | { |
| 7448 | CAN_CRITICAL_SECTION_ENTER(); |
| 7449 | ((Can *)hw)->XIDFC.reg |= mask; |
| 7450 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7451 | } |
| 7452 | |
| 7453 | static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) |
| 7454 | { |
| 7455 | uint32_t tmp; |
| 7456 | tmp = ((Can *)hw)->XIDFC.reg; |
| 7457 | tmp &= mask; |
| 7458 | return tmp; |
| 7459 | } |
| 7460 | |
| 7461 | static inline void hri_can_write_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t data) |
| 7462 | { |
| 7463 | CAN_CRITICAL_SECTION_ENTER(); |
| 7464 | ((Can *)hw)->XIDFC.reg = data; |
| 7465 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7466 | } |
| 7467 | |
| 7468 | static inline void hri_can_clear_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) |
| 7469 | { |
| 7470 | CAN_CRITICAL_SECTION_ENTER(); |
| 7471 | ((Can *)hw)->XIDFC.reg &= ~mask; |
| 7472 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7473 | } |
| 7474 | |
| 7475 | static inline void hri_can_toggle_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) |
| 7476 | { |
| 7477 | CAN_CRITICAL_SECTION_ENTER(); |
| 7478 | ((Can *)hw)->XIDFC.reg ^= mask; |
| 7479 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7480 | } |
| 7481 | |
| 7482 | static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_reg(const void *const hw) |
| 7483 | { |
| 7484 | return ((Can *)hw)->XIDFC.reg; |
| 7485 | } |
| 7486 | |
| 7487 | static inline void hri_can_set_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) |
| 7488 | { |
| 7489 | CAN_CRITICAL_SECTION_ENTER(); |
| 7490 | ((Can *)hw)->XIDAM.reg |= CAN_XIDAM_EIDM(mask); |
| 7491 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7492 | } |
| 7493 | |
| 7494 | static inline hri_can_xidam_reg_t hri_can_get_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) |
| 7495 | { |
| 7496 | uint32_t tmp; |
| 7497 | tmp = ((Can *)hw)->XIDAM.reg; |
| 7498 | tmp = (tmp & CAN_XIDAM_EIDM(mask)) >> CAN_XIDAM_EIDM_Pos; |
| 7499 | return tmp; |
| 7500 | } |
| 7501 | |
| 7502 | static inline void hri_can_write_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t data) |
| 7503 | { |
| 7504 | uint32_t tmp; |
| 7505 | CAN_CRITICAL_SECTION_ENTER(); |
| 7506 | tmp = ((Can *)hw)->XIDAM.reg; |
| 7507 | tmp &= ~CAN_XIDAM_EIDM_Msk; |
| 7508 | tmp |= CAN_XIDAM_EIDM(data); |
| 7509 | ((Can *)hw)->XIDAM.reg = tmp; |
| 7510 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7511 | } |
| 7512 | |
| 7513 | static inline void hri_can_clear_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) |
| 7514 | { |
| 7515 | CAN_CRITICAL_SECTION_ENTER(); |
| 7516 | ((Can *)hw)->XIDAM.reg &= ~CAN_XIDAM_EIDM(mask); |
| 7517 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7518 | } |
| 7519 | |
| 7520 | static inline void hri_can_toggle_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) |
| 7521 | { |
| 7522 | CAN_CRITICAL_SECTION_ENTER(); |
| 7523 | ((Can *)hw)->XIDAM.reg ^= CAN_XIDAM_EIDM(mask); |
| 7524 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7525 | } |
| 7526 | |
| 7527 | static inline hri_can_xidam_reg_t hri_can_read_XIDAM_EIDM_bf(const void *const hw) |
| 7528 | { |
| 7529 | uint32_t tmp; |
| 7530 | tmp = ((Can *)hw)->XIDAM.reg; |
| 7531 | tmp = (tmp & CAN_XIDAM_EIDM_Msk) >> CAN_XIDAM_EIDM_Pos; |
| 7532 | return tmp; |
| 7533 | } |
| 7534 | |
| 7535 | static inline void hri_can_set_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) |
| 7536 | { |
| 7537 | CAN_CRITICAL_SECTION_ENTER(); |
| 7538 | ((Can *)hw)->XIDAM.reg |= mask; |
| 7539 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7540 | } |
| 7541 | |
| 7542 | static inline hri_can_xidam_reg_t hri_can_get_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) |
| 7543 | { |
| 7544 | uint32_t tmp; |
| 7545 | tmp = ((Can *)hw)->XIDAM.reg; |
| 7546 | tmp &= mask; |
| 7547 | return tmp; |
| 7548 | } |
| 7549 | |
| 7550 | static inline void hri_can_write_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t data) |
| 7551 | { |
| 7552 | CAN_CRITICAL_SECTION_ENTER(); |
| 7553 | ((Can *)hw)->XIDAM.reg = data; |
| 7554 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7555 | } |
| 7556 | |
| 7557 | static inline void hri_can_clear_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) |
| 7558 | { |
| 7559 | CAN_CRITICAL_SECTION_ENTER(); |
| 7560 | ((Can *)hw)->XIDAM.reg &= ~mask; |
| 7561 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7562 | } |
| 7563 | |
| 7564 | static inline void hri_can_toggle_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) |
| 7565 | { |
| 7566 | CAN_CRITICAL_SECTION_ENTER(); |
| 7567 | ((Can *)hw)->XIDAM.reg ^= mask; |
| 7568 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7569 | } |
| 7570 | |
| 7571 | static inline hri_can_xidam_reg_t hri_can_read_XIDAM_reg(const void *const hw) |
| 7572 | { |
| 7573 | return ((Can *)hw)->XIDAM.reg; |
| 7574 | } |
| 7575 | |
| 7576 | static inline void hri_can_set_NDAT1_ND0_bit(const void *const hw) |
| 7577 | { |
| 7578 | CAN_CRITICAL_SECTION_ENTER(); |
| 7579 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND0; |
| 7580 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7581 | } |
| 7582 | |
| 7583 | static inline bool hri_can_get_NDAT1_ND0_bit(const void *const hw) |
| 7584 | { |
| 7585 | uint32_t tmp; |
| 7586 | tmp = ((Can *)hw)->NDAT1.reg; |
| 7587 | tmp = (tmp & CAN_NDAT1_ND0) >> CAN_NDAT1_ND0_Pos; |
| 7588 | return (bool)tmp; |
| 7589 | } |
| 7590 | |
| 7591 | static inline void hri_can_write_NDAT1_ND0_bit(const void *const hw, bool value) |
| 7592 | { |
| 7593 | uint32_t tmp; |
| 7594 | CAN_CRITICAL_SECTION_ENTER(); |
| 7595 | tmp = ((Can *)hw)->NDAT1.reg; |
| 7596 | tmp &= ~CAN_NDAT1_ND0; |
| 7597 | tmp |= value << CAN_NDAT1_ND0_Pos; |
| 7598 | ((Can *)hw)->NDAT1.reg = tmp; |
| 7599 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7600 | } |
| 7601 | |
| 7602 | static inline void hri_can_clear_NDAT1_ND0_bit(const void *const hw) |
| 7603 | { |
| 7604 | CAN_CRITICAL_SECTION_ENTER(); |
| 7605 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND0; |
| 7606 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7607 | } |
| 7608 | |
| 7609 | static inline void hri_can_toggle_NDAT1_ND0_bit(const void *const hw) |
| 7610 | { |
| 7611 | CAN_CRITICAL_SECTION_ENTER(); |
| 7612 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND0; |
| 7613 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7614 | } |
| 7615 | |
| 7616 | static inline void hri_can_set_NDAT1_ND1_bit(const void *const hw) |
| 7617 | { |
| 7618 | CAN_CRITICAL_SECTION_ENTER(); |
| 7619 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND1; |
| 7620 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7621 | } |
| 7622 | |
| 7623 | static inline bool hri_can_get_NDAT1_ND1_bit(const void *const hw) |
| 7624 | { |
| 7625 | uint32_t tmp; |
| 7626 | tmp = ((Can *)hw)->NDAT1.reg; |
| 7627 | tmp = (tmp & CAN_NDAT1_ND1) >> CAN_NDAT1_ND1_Pos; |
| 7628 | return (bool)tmp; |
| 7629 | } |
| 7630 | |
| 7631 | static inline void hri_can_write_NDAT1_ND1_bit(const void *const hw, bool value) |
| 7632 | { |
| 7633 | uint32_t tmp; |
| 7634 | CAN_CRITICAL_SECTION_ENTER(); |
| 7635 | tmp = ((Can *)hw)->NDAT1.reg; |
| 7636 | tmp &= ~CAN_NDAT1_ND1; |
| 7637 | tmp |= value << CAN_NDAT1_ND1_Pos; |
| 7638 | ((Can *)hw)->NDAT1.reg = tmp; |
| 7639 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7640 | } |
| 7641 | |
| 7642 | static inline void hri_can_clear_NDAT1_ND1_bit(const void *const hw) |
| 7643 | { |
| 7644 | CAN_CRITICAL_SECTION_ENTER(); |
| 7645 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND1; |
| 7646 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7647 | } |
| 7648 | |
| 7649 | static inline void hri_can_toggle_NDAT1_ND1_bit(const void *const hw) |
| 7650 | { |
| 7651 | CAN_CRITICAL_SECTION_ENTER(); |
| 7652 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND1; |
| 7653 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7654 | } |
| 7655 | |
| 7656 | static inline void hri_can_set_NDAT1_ND2_bit(const void *const hw) |
| 7657 | { |
| 7658 | CAN_CRITICAL_SECTION_ENTER(); |
| 7659 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND2; |
| 7660 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7661 | } |
| 7662 | |
| 7663 | static inline bool hri_can_get_NDAT1_ND2_bit(const void *const hw) |
| 7664 | { |
| 7665 | uint32_t tmp; |
| 7666 | tmp = ((Can *)hw)->NDAT1.reg; |
| 7667 | tmp = (tmp & CAN_NDAT1_ND2) >> CAN_NDAT1_ND2_Pos; |
| 7668 | return (bool)tmp; |
| 7669 | } |
| 7670 | |
| 7671 | static inline void hri_can_write_NDAT1_ND2_bit(const void *const hw, bool value) |
| 7672 | { |
| 7673 | uint32_t tmp; |
| 7674 | CAN_CRITICAL_SECTION_ENTER(); |
| 7675 | tmp = ((Can *)hw)->NDAT1.reg; |
| 7676 | tmp &= ~CAN_NDAT1_ND2; |
| 7677 | tmp |= value << CAN_NDAT1_ND2_Pos; |
| 7678 | ((Can *)hw)->NDAT1.reg = tmp; |
| 7679 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7680 | } |
| 7681 | |
| 7682 | static inline void hri_can_clear_NDAT1_ND2_bit(const void *const hw) |
| 7683 | { |
| 7684 | CAN_CRITICAL_SECTION_ENTER(); |
| 7685 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND2; |
| 7686 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7687 | } |
| 7688 | |
| 7689 | static inline void hri_can_toggle_NDAT1_ND2_bit(const void *const hw) |
| 7690 | { |
| 7691 | CAN_CRITICAL_SECTION_ENTER(); |
| 7692 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND2; |
| 7693 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7694 | } |
| 7695 | |
| 7696 | static inline void hri_can_set_NDAT1_ND3_bit(const void *const hw) |
| 7697 | { |
| 7698 | CAN_CRITICAL_SECTION_ENTER(); |
| 7699 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND3; |
| 7700 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7701 | } |
| 7702 | |
| 7703 | static inline bool hri_can_get_NDAT1_ND3_bit(const void *const hw) |
| 7704 | { |
| 7705 | uint32_t tmp; |
| 7706 | tmp = ((Can *)hw)->NDAT1.reg; |
| 7707 | tmp = (tmp & CAN_NDAT1_ND3) >> CAN_NDAT1_ND3_Pos; |
| 7708 | return (bool)tmp; |
| 7709 | } |
| 7710 | |
| 7711 | static inline void hri_can_write_NDAT1_ND3_bit(const void *const hw, bool value) |
| 7712 | { |
| 7713 | uint32_t tmp; |
| 7714 | CAN_CRITICAL_SECTION_ENTER(); |
| 7715 | tmp = ((Can *)hw)->NDAT1.reg; |
| 7716 | tmp &= ~CAN_NDAT1_ND3; |
| 7717 | tmp |= value << CAN_NDAT1_ND3_Pos; |
| 7718 | ((Can *)hw)->NDAT1.reg = tmp; |
| 7719 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7720 | } |
| 7721 | |
| 7722 | static inline void hri_can_clear_NDAT1_ND3_bit(const void *const hw) |
| 7723 | { |
| 7724 | CAN_CRITICAL_SECTION_ENTER(); |
| 7725 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND3; |
| 7726 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7727 | } |
| 7728 | |
| 7729 | static inline void hri_can_toggle_NDAT1_ND3_bit(const void *const hw) |
| 7730 | { |
| 7731 | CAN_CRITICAL_SECTION_ENTER(); |
| 7732 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND3; |
| 7733 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7734 | } |
| 7735 | |
| 7736 | static inline void hri_can_set_NDAT1_ND4_bit(const void *const hw) |
| 7737 | { |
| 7738 | CAN_CRITICAL_SECTION_ENTER(); |
| 7739 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND4; |
| 7740 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7741 | } |
| 7742 | |
| 7743 | static inline bool hri_can_get_NDAT1_ND4_bit(const void *const hw) |
| 7744 | { |
| 7745 | uint32_t tmp; |
| 7746 | tmp = ((Can *)hw)->NDAT1.reg; |
| 7747 | tmp = (tmp & CAN_NDAT1_ND4) >> CAN_NDAT1_ND4_Pos; |
| 7748 | return (bool)tmp; |
| 7749 | } |
| 7750 | |
| 7751 | static inline void hri_can_write_NDAT1_ND4_bit(const void *const hw, bool value) |
| 7752 | { |
| 7753 | uint32_t tmp; |
| 7754 | CAN_CRITICAL_SECTION_ENTER(); |
| 7755 | tmp = ((Can *)hw)->NDAT1.reg; |
| 7756 | tmp &= ~CAN_NDAT1_ND4; |
| 7757 | tmp |= value << CAN_NDAT1_ND4_Pos; |
| 7758 | ((Can *)hw)->NDAT1.reg = tmp; |
| 7759 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7760 | } |
| 7761 | |
| 7762 | static inline void hri_can_clear_NDAT1_ND4_bit(const void *const hw) |
| 7763 | { |
| 7764 | CAN_CRITICAL_SECTION_ENTER(); |
| 7765 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND4; |
| 7766 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7767 | } |
| 7768 | |
| 7769 | static inline void hri_can_toggle_NDAT1_ND4_bit(const void *const hw) |
| 7770 | { |
| 7771 | CAN_CRITICAL_SECTION_ENTER(); |
| 7772 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND4; |
| 7773 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7774 | } |
| 7775 | |
| 7776 | static inline void hri_can_set_NDAT1_ND5_bit(const void *const hw) |
| 7777 | { |
| 7778 | CAN_CRITICAL_SECTION_ENTER(); |
| 7779 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND5; |
| 7780 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7781 | } |
| 7782 | |
| 7783 | static inline bool hri_can_get_NDAT1_ND5_bit(const void *const hw) |
| 7784 | { |
| 7785 | uint32_t tmp; |
| 7786 | tmp = ((Can *)hw)->NDAT1.reg; |
| 7787 | tmp = (tmp & CAN_NDAT1_ND5) >> CAN_NDAT1_ND5_Pos; |
| 7788 | return (bool)tmp; |
| 7789 | } |
| 7790 | |
| 7791 | static inline void hri_can_write_NDAT1_ND5_bit(const void *const hw, bool value) |
| 7792 | { |
| 7793 | uint32_t tmp; |
| 7794 | CAN_CRITICAL_SECTION_ENTER(); |
| 7795 | tmp = ((Can *)hw)->NDAT1.reg; |
| 7796 | tmp &= ~CAN_NDAT1_ND5; |
| 7797 | tmp |= value << CAN_NDAT1_ND5_Pos; |
| 7798 | ((Can *)hw)->NDAT1.reg = tmp; |
| 7799 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7800 | } |
| 7801 | |
| 7802 | static inline void hri_can_clear_NDAT1_ND5_bit(const void *const hw) |
| 7803 | { |
| 7804 | CAN_CRITICAL_SECTION_ENTER(); |
| 7805 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND5; |
| 7806 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7807 | } |
| 7808 | |
| 7809 | static inline void hri_can_toggle_NDAT1_ND5_bit(const void *const hw) |
| 7810 | { |
| 7811 | CAN_CRITICAL_SECTION_ENTER(); |
| 7812 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND5; |
| 7813 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7814 | } |
| 7815 | |
| 7816 | static inline void hri_can_set_NDAT1_ND6_bit(const void *const hw) |
| 7817 | { |
| 7818 | CAN_CRITICAL_SECTION_ENTER(); |
| 7819 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND6; |
| 7820 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7821 | } |
| 7822 | |
| 7823 | static inline bool hri_can_get_NDAT1_ND6_bit(const void *const hw) |
| 7824 | { |
| 7825 | uint32_t tmp; |
| 7826 | tmp = ((Can *)hw)->NDAT1.reg; |
| 7827 | tmp = (tmp & CAN_NDAT1_ND6) >> CAN_NDAT1_ND6_Pos; |
| 7828 | return (bool)tmp; |
| 7829 | } |
| 7830 | |
| 7831 | static inline void hri_can_write_NDAT1_ND6_bit(const void *const hw, bool value) |
| 7832 | { |
| 7833 | uint32_t tmp; |
| 7834 | CAN_CRITICAL_SECTION_ENTER(); |
| 7835 | tmp = ((Can *)hw)->NDAT1.reg; |
| 7836 | tmp &= ~CAN_NDAT1_ND6; |
| 7837 | tmp |= value << CAN_NDAT1_ND6_Pos; |
| 7838 | ((Can *)hw)->NDAT1.reg = tmp; |
| 7839 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7840 | } |
| 7841 | |
| 7842 | static inline void hri_can_clear_NDAT1_ND6_bit(const void *const hw) |
| 7843 | { |
| 7844 | CAN_CRITICAL_SECTION_ENTER(); |
| 7845 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND6; |
| 7846 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7847 | } |
| 7848 | |
| 7849 | static inline void hri_can_toggle_NDAT1_ND6_bit(const void *const hw) |
| 7850 | { |
| 7851 | CAN_CRITICAL_SECTION_ENTER(); |
| 7852 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND6; |
| 7853 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7854 | } |
| 7855 | |
| 7856 | static inline void hri_can_set_NDAT1_ND7_bit(const void *const hw) |
| 7857 | { |
| 7858 | CAN_CRITICAL_SECTION_ENTER(); |
| 7859 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND7; |
| 7860 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7861 | } |
| 7862 | |
| 7863 | static inline bool hri_can_get_NDAT1_ND7_bit(const void *const hw) |
| 7864 | { |
| 7865 | uint32_t tmp; |
| 7866 | tmp = ((Can *)hw)->NDAT1.reg; |
| 7867 | tmp = (tmp & CAN_NDAT1_ND7) >> CAN_NDAT1_ND7_Pos; |
| 7868 | return (bool)tmp; |
| 7869 | } |
| 7870 | |
| 7871 | static inline void hri_can_write_NDAT1_ND7_bit(const void *const hw, bool value) |
| 7872 | { |
| 7873 | uint32_t tmp; |
| 7874 | CAN_CRITICAL_SECTION_ENTER(); |
| 7875 | tmp = ((Can *)hw)->NDAT1.reg; |
| 7876 | tmp &= ~CAN_NDAT1_ND7; |
| 7877 | tmp |= value << CAN_NDAT1_ND7_Pos; |
| 7878 | ((Can *)hw)->NDAT1.reg = tmp; |
| 7879 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7880 | } |
| 7881 | |
| 7882 | static inline void hri_can_clear_NDAT1_ND7_bit(const void *const hw) |
| 7883 | { |
| 7884 | CAN_CRITICAL_SECTION_ENTER(); |
| 7885 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND7; |
| 7886 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7887 | } |
| 7888 | |
| 7889 | static inline void hri_can_toggle_NDAT1_ND7_bit(const void *const hw) |
| 7890 | { |
| 7891 | CAN_CRITICAL_SECTION_ENTER(); |
| 7892 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND7; |
| 7893 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7894 | } |
| 7895 | |
| 7896 | static inline void hri_can_set_NDAT1_ND8_bit(const void *const hw) |
| 7897 | { |
| 7898 | CAN_CRITICAL_SECTION_ENTER(); |
| 7899 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND8; |
| 7900 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7901 | } |
| 7902 | |
| 7903 | static inline bool hri_can_get_NDAT1_ND8_bit(const void *const hw) |
| 7904 | { |
| 7905 | uint32_t tmp; |
| 7906 | tmp = ((Can *)hw)->NDAT1.reg; |
| 7907 | tmp = (tmp & CAN_NDAT1_ND8) >> CAN_NDAT1_ND8_Pos; |
| 7908 | return (bool)tmp; |
| 7909 | } |
| 7910 | |
| 7911 | static inline void hri_can_write_NDAT1_ND8_bit(const void *const hw, bool value) |
| 7912 | { |
| 7913 | uint32_t tmp; |
| 7914 | CAN_CRITICAL_SECTION_ENTER(); |
| 7915 | tmp = ((Can *)hw)->NDAT1.reg; |
| 7916 | tmp &= ~CAN_NDAT1_ND8; |
| 7917 | tmp |= value << CAN_NDAT1_ND8_Pos; |
| 7918 | ((Can *)hw)->NDAT1.reg = tmp; |
| 7919 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7920 | } |
| 7921 | |
| 7922 | static inline void hri_can_clear_NDAT1_ND8_bit(const void *const hw) |
| 7923 | { |
| 7924 | CAN_CRITICAL_SECTION_ENTER(); |
| 7925 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND8; |
| 7926 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7927 | } |
| 7928 | |
| 7929 | static inline void hri_can_toggle_NDAT1_ND8_bit(const void *const hw) |
| 7930 | { |
| 7931 | CAN_CRITICAL_SECTION_ENTER(); |
| 7932 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND8; |
| 7933 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7934 | } |
| 7935 | |
| 7936 | static inline void hri_can_set_NDAT1_ND9_bit(const void *const hw) |
| 7937 | { |
| 7938 | CAN_CRITICAL_SECTION_ENTER(); |
| 7939 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND9; |
| 7940 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7941 | } |
| 7942 | |
| 7943 | static inline bool hri_can_get_NDAT1_ND9_bit(const void *const hw) |
| 7944 | { |
| 7945 | uint32_t tmp; |
| 7946 | tmp = ((Can *)hw)->NDAT1.reg; |
| 7947 | tmp = (tmp & CAN_NDAT1_ND9) >> CAN_NDAT1_ND9_Pos; |
| 7948 | return (bool)tmp; |
| 7949 | } |
| 7950 | |
| 7951 | static inline void hri_can_write_NDAT1_ND9_bit(const void *const hw, bool value) |
| 7952 | { |
| 7953 | uint32_t tmp; |
| 7954 | CAN_CRITICAL_SECTION_ENTER(); |
| 7955 | tmp = ((Can *)hw)->NDAT1.reg; |
| 7956 | tmp &= ~CAN_NDAT1_ND9; |
| 7957 | tmp |= value << CAN_NDAT1_ND9_Pos; |
| 7958 | ((Can *)hw)->NDAT1.reg = tmp; |
| 7959 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7960 | } |
| 7961 | |
| 7962 | static inline void hri_can_clear_NDAT1_ND9_bit(const void *const hw) |
| 7963 | { |
| 7964 | CAN_CRITICAL_SECTION_ENTER(); |
| 7965 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND9; |
| 7966 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7967 | } |
| 7968 | |
| 7969 | static inline void hri_can_toggle_NDAT1_ND9_bit(const void *const hw) |
| 7970 | { |
| 7971 | CAN_CRITICAL_SECTION_ENTER(); |
| 7972 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND9; |
| 7973 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7974 | } |
| 7975 | |
| 7976 | static inline void hri_can_set_NDAT1_ND10_bit(const void *const hw) |
| 7977 | { |
| 7978 | CAN_CRITICAL_SECTION_ENTER(); |
| 7979 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND10; |
| 7980 | CAN_CRITICAL_SECTION_LEAVE(); |
| 7981 | } |
| 7982 | |
| 7983 | static inline bool hri_can_get_NDAT1_ND10_bit(const void *const hw) |
| 7984 | { |
| 7985 | uint32_t tmp; |
| 7986 | tmp = ((Can *)hw)->NDAT1.reg; |
| 7987 | tmp = (tmp & CAN_NDAT1_ND10) >> CAN_NDAT1_ND10_Pos; |
| 7988 | return (bool)tmp; |
| 7989 | } |
| 7990 | |
| 7991 | static inline void hri_can_write_NDAT1_ND10_bit(const void *const hw, bool value) |
| 7992 | { |
| 7993 | uint32_t tmp; |
| 7994 | CAN_CRITICAL_SECTION_ENTER(); |
| 7995 | tmp = ((Can *)hw)->NDAT1.reg; |
| 7996 | tmp &= ~CAN_NDAT1_ND10; |
| 7997 | tmp |= value << CAN_NDAT1_ND10_Pos; |
| 7998 | ((Can *)hw)->NDAT1.reg = tmp; |
| 7999 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8000 | } |
| 8001 | |
| 8002 | static inline void hri_can_clear_NDAT1_ND10_bit(const void *const hw) |
| 8003 | { |
| 8004 | CAN_CRITICAL_SECTION_ENTER(); |
| 8005 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND10; |
| 8006 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8007 | } |
| 8008 | |
| 8009 | static inline void hri_can_toggle_NDAT1_ND10_bit(const void *const hw) |
| 8010 | { |
| 8011 | CAN_CRITICAL_SECTION_ENTER(); |
| 8012 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND10; |
| 8013 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8014 | } |
| 8015 | |
| 8016 | static inline void hri_can_set_NDAT1_ND11_bit(const void *const hw) |
| 8017 | { |
| 8018 | CAN_CRITICAL_SECTION_ENTER(); |
| 8019 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND11; |
| 8020 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8021 | } |
| 8022 | |
| 8023 | static inline bool hri_can_get_NDAT1_ND11_bit(const void *const hw) |
| 8024 | { |
| 8025 | uint32_t tmp; |
| 8026 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8027 | tmp = (tmp & CAN_NDAT1_ND11) >> CAN_NDAT1_ND11_Pos; |
| 8028 | return (bool)tmp; |
| 8029 | } |
| 8030 | |
| 8031 | static inline void hri_can_write_NDAT1_ND11_bit(const void *const hw, bool value) |
| 8032 | { |
| 8033 | uint32_t tmp; |
| 8034 | CAN_CRITICAL_SECTION_ENTER(); |
| 8035 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8036 | tmp &= ~CAN_NDAT1_ND11; |
| 8037 | tmp |= value << CAN_NDAT1_ND11_Pos; |
| 8038 | ((Can *)hw)->NDAT1.reg = tmp; |
| 8039 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8040 | } |
| 8041 | |
| 8042 | static inline void hri_can_clear_NDAT1_ND11_bit(const void *const hw) |
| 8043 | { |
| 8044 | CAN_CRITICAL_SECTION_ENTER(); |
| 8045 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND11; |
| 8046 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8047 | } |
| 8048 | |
| 8049 | static inline void hri_can_toggle_NDAT1_ND11_bit(const void *const hw) |
| 8050 | { |
| 8051 | CAN_CRITICAL_SECTION_ENTER(); |
| 8052 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND11; |
| 8053 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8054 | } |
| 8055 | |
| 8056 | static inline void hri_can_set_NDAT1_ND12_bit(const void *const hw) |
| 8057 | { |
| 8058 | CAN_CRITICAL_SECTION_ENTER(); |
| 8059 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND12; |
| 8060 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8061 | } |
| 8062 | |
| 8063 | static inline bool hri_can_get_NDAT1_ND12_bit(const void *const hw) |
| 8064 | { |
| 8065 | uint32_t tmp; |
| 8066 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8067 | tmp = (tmp & CAN_NDAT1_ND12) >> CAN_NDAT1_ND12_Pos; |
| 8068 | return (bool)tmp; |
| 8069 | } |
| 8070 | |
| 8071 | static inline void hri_can_write_NDAT1_ND12_bit(const void *const hw, bool value) |
| 8072 | { |
| 8073 | uint32_t tmp; |
| 8074 | CAN_CRITICAL_SECTION_ENTER(); |
| 8075 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8076 | tmp &= ~CAN_NDAT1_ND12; |
| 8077 | tmp |= value << CAN_NDAT1_ND12_Pos; |
| 8078 | ((Can *)hw)->NDAT1.reg = tmp; |
| 8079 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8080 | } |
| 8081 | |
| 8082 | static inline void hri_can_clear_NDAT1_ND12_bit(const void *const hw) |
| 8083 | { |
| 8084 | CAN_CRITICAL_SECTION_ENTER(); |
| 8085 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND12; |
| 8086 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8087 | } |
| 8088 | |
| 8089 | static inline void hri_can_toggle_NDAT1_ND12_bit(const void *const hw) |
| 8090 | { |
| 8091 | CAN_CRITICAL_SECTION_ENTER(); |
| 8092 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND12; |
| 8093 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8094 | } |
| 8095 | |
| 8096 | static inline void hri_can_set_NDAT1_ND13_bit(const void *const hw) |
| 8097 | { |
| 8098 | CAN_CRITICAL_SECTION_ENTER(); |
| 8099 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND13; |
| 8100 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8101 | } |
| 8102 | |
| 8103 | static inline bool hri_can_get_NDAT1_ND13_bit(const void *const hw) |
| 8104 | { |
| 8105 | uint32_t tmp; |
| 8106 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8107 | tmp = (tmp & CAN_NDAT1_ND13) >> CAN_NDAT1_ND13_Pos; |
| 8108 | return (bool)tmp; |
| 8109 | } |
| 8110 | |
| 8111 | static inline void hri_can_write_NDAT1_ND13_bit(const void *const hw, bool value) |
| 8112 | { |
| 8113 | uint32_t tmp; |
| 8114 | CAN_CRITICAL_SECTION_ENTER(); |
| 8115 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8116 | tmp &= ~CAN_NDAT1_ND13; |
| 8117 | tmp |= value << CAN_NDAT1_ND13_Pos; |
| 8118 | ((Can *)hw)->NDAT1.reg = tmp; |
| 8119 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8120 | } |
| 8121 | |
| 8122 | static inline void hri_can_clear_NDAT1_ND13_bit(const void *const hw) |
| 8123 | { |
| 8124 | CAN_CRITICAL_SECTION_ENTER(); |
| 8125 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND13; |
| 8126 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8127 | } |
| 8128 | |
| 8129 | static inline void hri_can_toggle_NDAT1_ND13_bit(const void *const hw) |
| 8130 | { |
| 8131 | CAN_CRITICAL_SECTION_ENTER(); |
| 8132 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND13; |
| 8133 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8134 | } |
| 8135 | |
| 8136 | static inline void hri_can_set_NDAT1_ND14_bit(const void *const hw) |
| 8137 | { |
| 8138 | CAN_CRITICAL_SECTION_ENTER(); |
| 8139 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND14; |
| 8140 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8141 | } |
| 8142 | |
| 8143 | static inline bool hri_can_get_NDAT1_ND14_bit(const void *const hw) |
| 8144 | { |
| 8145 | uint32_t tmp; |
| 8146 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8147 | tmp = (tmp & CAN_NDAT1_ND14) >> CAN_NDAT1_ND14_Pos; |
| 8148 | return (bool)tmp; |
| 8149 | } |
| 8150 | |
| 8151 | static inline void hri_can_write_NDAT1_ND14_bit(const void *const hw, bool value) |
| 8152 | { |
| 8153 | uint32_t tmp; |
| 8154 | CAN_CRITICAL_SECTION_ENTER(); |
| 8155 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8156 | tmp &= ~CAN_NDAT1_ND14; |
| 8157 | tmp |= value << CAN_NDAT1_ND14_Pos; |
| 8158 | ((Can *)hw)->NDAT1.reg = tmp; |
| 8159 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8160 | } |
| 8161 | |
| 8162 | static inline void hri_can_clear_NDAT1_ND14_bit(const void *const hw) |
| 8163 | { |
| 8164 | CAN_CRITICAL_SECTION_ENTER(); |
| 8165 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND14; |
| 8166 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8167 | } |
| 8168 | |
| 8169 | static inline void hri_can_toggle_NDAT1_ND14_bit(const void *const hw) |
| 8170 | { |
| 8171 | CAN_CRITICAL_SECTION_ENTER(); |
| 8172 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND14; |
| 8173 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8174 | } |
| 8175 | |
| 8176 | static inline void hri_can_set_NDAT1_ND15_bit(const void *const hw) |
| 8177 | { |
| 8178 | CAN_CRITICAL_SECTION_ENTER(); |
| 8179 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND15; |
| 8180 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8181 | } |
| 8182 | |
| 8183 | static inline bool hri_can_get_NDAT1_ND15_bit(const void *const hw) |
| 8184 | { |
| 8185 | uint32_t tmp; |
| 8186 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8187 | tmp = (tmp & CAN_NDAT1_ND15) >> CAN_NDAT1_ND15_Pos; |
| 8188 | return (bool)tmp; |
| 8189 | } |
| 8190 | |
| 8191 | static inline void hri_can_write_NDAT1_ND15_bit(const void *const hw, bool value) |
| 8192 | { |
| 8193 | uint32_t tmp; |
| 8194 | CAN_CRITICAL_SECTION_ENTER(); |
| 8195 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8196 | tmp &= ~CAN_NDAT1_ND15; |
| 8197 | tmp |= value << CAN_NDAT1_ND15_Pos; |
| 8198 | ((Can *)hw)->NDAT1.reg = tmp; |
| 8199 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8200 | } |
| 8201 | |
| 8202 | static inline void hri_can_clear_NDAT1_ND15_bit(const void *const hw) |
| 8203 | { |
| 8204 | CAN_CRITICAL_SECTION_ENTER(); |
| 8205 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND15; |
| 8206 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8207 | } |
| 8208 | |
| 8209 | static inline void hri_can_toggle_NDAT1_ND15_bit(const void *const hw) |
| 8210 | { |
| 8211 | CAN_CRITICAL_SECTION_ENTER(); |
| 8212 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND15; |
| 8213 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8214 | } |
| 8215 | |
| 8216 | static inline void hri_can_set_NDAT1_ND16_bit(const void *const hw) |
| 8217 | { |
| 8218 | CAN_CRITICAL_SECTION_ENTER(); |
| 8219 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND16; |
| 8220 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8221 | } |
| 8222 | |
| 8223 | static inline bool hri_can_get_NDAT1_ND16_bit(const void *const hw) |
| 8224 | { |
| 8225 | uint32_t tmp; |
| 8226 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8227 | tmp = (tmp & CAN_NDAT1_ND16) >> CAN_NDAT1_ND16_Pos; |
| 8228 | return (bool)tmp; |
| 8229 | } |
| 8230 | |
| 8231 | static inline void hri_can_write_NDAT1_ND16_bit(const void *const hw, bool value) |
| 8232 | { |
| 8233 | uint32_t tmp; |
| 8234 | CAN_CRITICAL_SECTION_ENTER(); |
| 8235 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8236 | tmp &= ~CAN_NDAT1_ND16; |
| 8237 | tmp |= value << CAN_NDAT1_ND16_Pos; |
| 8238 | ((Can *)hw)->NDAT1.reg = tmp; |
| 8239 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8240 | } |
| 8241 | |
| 8242 | static inline void hri_can_clear_NDAT1_ND16_bit(const void *const hw) |
| 8243 | { |
| 8244 | CAN_CRITICAL_SECTION_ENTER(); |
| 8245 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND16; |
| 8246 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8247 | } |
| 8248 | |
| 8249 | static inline void hri_can_toggle_NDAT1_ND16_bit(const void *const hw) |
| 8250 | { |
| 8251 | CAN_CRITICAL_SECTION_ENTER(); |
| 8252 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND16; |
| 8253 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8254 | } |
| 8255 | |
| 8256 | static inline void hri_can_set_NDAT1_ND17_bit(const void *const hw) |
| 8257 | { |
| 8258 | CAN_CRITICAL_SECTION_ENTER(); |
| 8259 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND17; |
| 8260 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8261 | } |
| 8262 | |
| 8263 | static inline bool hri_can_get_NDAT1_ND17_bit(const void *const hw) |
| 8264 | { |
| 8265 | uint32_t tmp; |
| 8266 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8267 | tmp = (tmp & CAN_NDAT1_ND17) >> CAN_NDAT1_ND17_Pos; |
| 8268 | return (bool)tmp; |
| 8269 | } |
| 8270 | |
| 8271 | static inline void hri_can_write_NDAT1_ND17_bit(const void *const hw, bool value) |
| 8272 | { |
| 8273 | uint32_t tmp; |
| 8274 | CAN_CRITICAL_SECTION_ENTER(); |
| 8275 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8276 | tmp &= ~CAN_NDAT1_ND17; |
| 8277 | tmp |= value << CAN_NDAT1_ND17_Pos; |
| 8278 | ((Can *)hw)->NDAT1.reg = tmp; |
| 8279 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8280 | } |
| 8281 | |
| 8282 | static inline void hri_can_clear_NDAT1_ND17_bit(const void *const hw) |
| 8283 | { |
| 8284 | CAN_CRITICAL_SECTION_ENTER(); |
| 8285 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND17; |
| 8286 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8287 | } |
| 8288 | |
| 8289 | static inline void hri_can_toggle_NDAT1_ND17_bit(const void *const hw) |
| 8290 | { |
| 8291 | CAN_CRITICAL_SECTION_ENTER(); |
| 8292 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND17; |
| 8293 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8294 | } |
| 8295 | |
| 8296 | static inline void hri_can_set_NDAT1_ND18_bit(const void *const hw) |
| 8297 | { |
| 8298 | CAN_CRITICAL_SECTION_ENTER(); |
| 8299 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND18; |
| 8300 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8301 | } |
| 8302 | |
| 8303 | static inline bool hri_can_get_NDAT1_ND18_bit(const void *const hw) |
| 8304 | { |
| 8305 | uint32_t tmp; |
| 8306 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8307 | tmp = (tmp & CAN_NDAT1_ND18) >> CAN_NDAT1_ND18_Pos; |
| 8308 | return (bool)tmp; |
| 8309 | } |
| 8310 | |
| 8311 | static inline void hri_can_write_NDAT1_ND18_bit(const void *const hw, bool value) |
| 8312 | { |
| 8313 | uint32_t tmp; |
| 8314 | CAN_CRITICAL_SECTION_ENTER(); |
| 8315 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8316 | tmp &= ~CAN_NDAT1_ND18; |
| 8317 | tmp |= value << CAN_NDAT1_ND18_Pos; |
| 8318 | ((Can *)hw)->NDAT1.reg = tmp; |
| 8319 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8320 | } |
| 8321 | |
| 8322 | static inline void hri_can_clear_NDAT1_ND18_bit(const void *const hw) |
| 8323 | { |
| 8324 | CAN_CRITICAL_SECTION_ENTER(); |
| 8325 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND18; |
| 8326 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8327 | } |
| 8328 | |
| 8329 | static inline void hri_can_toggle_NDAT1_ND18_bit(const void *const hw) |
| 8330 | { |
| 8331 | CAN_CRITICAL_SECTION_ENTER(); |
| 8332 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND18; |
| 8333 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8334 | } |
| 8335 | |
| 8336 | static inline void hri_can_set_NDAT1_ND19_bit(const void *const hw) |
| 8337 | { |
| 8338 | CAN_CRITICAL_SECTION_ENTER(); |
| 8339 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND19; |
| 8340 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8341 | } |
| 8342 | |
| 8343 | static inline bool hri_can_get_NDAT1_ND19_bit(const void *const hw) |
| 8344 | { |
| 8345 | uint32_t tmp; |
| 8346 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8347 | tmp = (tmp & CAN_NDAT1_ND19) >> CAN_NDAT1_ND19_Pos; |
| 8348 | return (bool)tmp; |
| 8349 | } |
| 8350 | |
| 8351 | static inline void hri_can_write_NDAT1_ND19_bit(const void *const hw, bool value) |
| 8352 | { |
| 8353 | uint32_t tmp; |
| 8354 | CAN_CRITICAL_SECTION_ENTER(); |
| 8355 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8356 | tmp &= ~CAN_NDAT1_ND19; |
| 8357 | tmp |= value << CAN_NDAT1_ND19_Pos; |
| 8358 | ((Can *)hw)->NDAT1.reg = tmp; |
| 8359 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8360 | } |
| 8361 | |
| 8362 | static inline void hri_can_clear_NDAT1_ND19_bit(const void *const hw) |
| 8363 | { |
| 8364 | CAN_CRITICAL_SECTION_ENTER(); |
| 8365 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND19; |
| 8366 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8367 | } |
| 8368 | |
| 8369 | static inline void hri_can_toggle_NDAT1_ND19_bit(const void *const hw) |
| 8370 | { |
| 8371 | CAN_CRITICAL_SECTION_ENTER(); |
| 8372 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND19; |
| 8373 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8374 | } |
| 8375 | |
| 8376 | static inline void hri_can_set_NDAT1_ND20_bit(const void *const hw) |
| 8377 | { |
| 8378 | CAN_CRITICAL_SECTION_ENTER(); |
| 8379 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND20; |
| 8380 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8381 | } |
| 8382 | |
| 8383 | static inline bool hri_can_get_NDAT1_ND20_bit(const void *const hw) |
| 8384 | { |
| 8385 | uint32_t tmp; |
| 8386 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8387 | tmp = (tmp & CAN_NDAT1_ND20) >> CAN_NDAT1_ND20_Pos; |
| 8388 | return (bool)tmp; |
| 8389 | } |
| 8390 | |
| 8391 | static inline void hri_can_write_NDAT1_ND20_bit(const void *const hw, bool value) |
| 8392 | { |
| 8393 | uint32_t tmp; |
| 8394 | CAN_CRITICAL_SECTION_ENTER(); |
| 8395 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8396 | tmp &= ~CAN_NDAT1_ND20; |
| 8397 | tmp |= value << CAN_NDAT1_ND20_Pos; |
| 8398 | ((Can *)hw)->NDAT1.reg = tmp; |
| 8399 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8400 | } |
| 8401 | |
| 8402 | static inline void hri_can_clear_NDAT1_ND20_bit(const void *const hw) |
| 8403 | { |
| 8404 | CAN_CRITICAL_SECTION_ENTER(); |
| 8405 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND20; |
| 8406 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8407 | } |
| 8408 | |
| 8409 | static inline void hri_can_toggle_NDAT1_ND20_bit(const void *const hw) |
| 8410 | { |
| 8411 | CAN_CRITICAL_SECTION_ENTER(); |
| 8412 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND20; |
| 8413 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8414 | } |
| 8415 | |
| 8416 | static inline void hri_can_set_NDAT1_ND21_bit(const void *const hw) |
| 8417 | { |
| 8418 | CAN_CRITICAL_SECTION_ENTER(); |
| 8419 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND21; |
| 8420 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8421 | } |
| 8422 | |
| 8423 | static inline bool hri_can_get_NDAT1_ND21_bit(const void *const hw) |
| 8424 | { |
| 8425 | uint32_t tmp; |
| 8426 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8427 | tmp = (tmp & CAN_NDAT1_ND21) >> CAN_NDAT1_ND21_Pos; |
| 8428 | return (bool)tmp; |
| 8429 | } |
| 8430 | |
| 8431 | static inline void hri_can_write_NDAT1_ND21_bit(const void *const hw, bool value) |
| 8432 | { |
| 8433 | uint32_t tmp; |
| 8434 | CAN_CRITICAL_SECTION_ENTER(); |
| 8435 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8436 | tmp &= ~CAN_NDAT1_ND21; |
| 8437 | tmp |= value << CAN_NDAT1_ND21_Pos; |
| 8438 | ((Can *)hw)->NDAT1.reg = tmp; |
| 8439 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8440 | } |
| 8441 | |
| 8442 | static inline void hri_can_clear_NDAT1_ND21_bit(const void *const hw) |
| 8443 | { |
| 8444 | CAN_CRITICAL_SECTION_ENTER(); |
| 8445 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND21; |
| 8446 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8447 | } |
| 8448 | |
| 8449 | static inline void hri_can_toggle_NDAT1_ND21_bit(const void *const hw) |
| 8450 | { |
| 8451 | CAN_CRITICAL_SECTION_ENTER(); |
| 8452 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND21; |
| 8453 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8454 | } |
| 8455 | |
| 8456 | static inline void hri_can_set_NDAT1_ND22_bit(const void *const hw) |
| 8457 | { |
| 8458 | CAN_CRITICAL_SECTION_ENTER(); |
| 8459 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND22; |
| 8460 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8461 | } |
| 8462 | |
| 8463 | static inline bool hri_can_get_NDAT1_ND22_bit(const void *const hw) |
| 8464 | { |
| 8465 | uint32_t tmp; |
| 8466 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8467 | tmp = (tmp & CAN_NDAT1_ND22) >> CAN_NDAT1_ND22_Pos; |
| 8468 | return (bool)tmp; |
| 8469 | } |
| 8470 | |
| 8471 | static inline void hri_can_write_NDAT1_ND22_bit(const void *const hw, bool value) |
| 8472 | { |
| 8473 | uint32_t tmp; |
| 8474 | CAN_CRITICAL_SECTION_ENTER(); |
| 8475 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8476 | tmp &= ~CAN_NDAT1_ND22; |
| 8477 | tmp |= value << CAN_NDAT1_ND22_Pos; |
| 8478 | ((Can *)hw)->NDAT1.reg = tmp; |
| 8479 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8480 | } |
| 8481 | |
| 8482 | static inline void hri_can_clear_NDAT1_ND22_bit(const void *const hw) |
| 8483 | { |
| 8484 | CAN_CRITICAL_SECTION_ENTER(); |
| 8485 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND22; |
| 8486 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8487 | } |
| 8488 | |
| 8489 | static inline void hri_can_toggle_NDAT1_ND22_bit(const void *const hw) |
| 8490 | { |
| 8491 | CAN_CRITICAL_SECTION_ENTER(); |
| 8492 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND22; |
| 8493 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8494 | } |
| 8495 | |
| 8496 | static inline void hri_can_set_NDAT1_ND23_bit(const void *const hw) |
| 8497 | { |
| 8498 | CAN_CRITICAL_SECTION_ENTER(); |
| 8499 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND23; |
| 8500 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8501 | } |
| 8502 | |
| 8503 | static inline bool hri_can_get_NDAT1_ND23_bit(const void *const hw) |
| 8504 | { |
| 8505 | uint32_t tmp; |
| 8506 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8507 | tmp = (tmp & CAN_NDAT1_ND23) >> CAN_NDAT1_ND23_Pos; |
| 8508 | return (bool)tmp; |
| 8509 | } |
| 8510 | |
| 8511 | static inline void hri_can_write_NDAT1_ND23_bit(const void *const hw, bool value) |
| 8512 | { |
| 8513 | uint32_t tmp; |
| 8514 | CAN_CRITICAL_SECTION_ENTER(); |
| 8515 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8516 | tmp &= ~CAN_NDAT1_ND23; |
| 8517 | tmp |= value << CAN_NDAT1_ND23_Pos; |
| 8518 | ((Can *)hw)->NDAT1.reg = tmp; |
| 8519 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8520 | } |
| 8521 | |
| 8522 | static inline void hri_can_clear_NDAT1_ND23_bit(const void *const hw) |
| 8523 | { |
| 8524 | CAN_CRITICAL_SECTION_ENTER(); |
| 8525 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND23; |
| 8526 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8527 | } |
| 8528 | |
| 8529 | static inline void hri_can_toggle_NDAT1_ND23_bit(const void *const hw) |
| 8530 | { |
| 8531 | CAN_CRITICAL_SECTION_ENTER(); |
| 8532 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND23; |
| 8533 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8534 | } |
| 8535 | |
| 8536 | static inline void hri_can_set_NDAT1_ND24_bit(const void *const hw) |
| 8537 | { |
| 8538 | CAN_CRITICAL_SECTION_ENTER(); |
| 8539 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND24; |
| 8540 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8541 | } |
| 8542 | |
| 8543 | static inline bool hri_can_get_NDAT1_ND24_bit(const void *const hw) |
| 8544 | { |
| 8545 | uint32_t tmp; |
| 8546 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8547 | tmp = (tmp & CAN_NDAT1_ND24) >> CAN_NDAT1_ND24_Pos; |
| 8548 | return (bool)tmp; |
| 8549 | } |
| 8550 | |
| 8551 | static inline void hri_can_write_NDAT1_ND24_bit(const void *const hw, bool value) |
| 8552 | { |
| 8553 | uint32_t tmp; |
| 8554 | CAN_CRITICAL_SECTION_ENTER(); |
| 8555 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8556 | tmp &= ~CAN_NDAT1_ND24; |
| 8557 | tmp |= value << CAN_NDAT1_ND24_Pos; |
| 8558 | ((Can *)hw)->NDAT1.reg = tmp; |
| 8559 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8560 | } |
| 8561 | |
| 8562 | static inline void hri_can_clear_NDAT1_ND24_bit(const void *const hw) |
| 8563 | { |
| 8564 | CAN_CRITICAL_SECTION_ENTER(); |
| 8565 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND24; |
| 8566 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8567 | } |
| 8568 | |
| 8569 | static inline void hri_can_toggle_NDAT1_ND24_bit(const void *const hw) |
| 8570 | { |
| 8571 | CAN_CRITICAL_SECTION_ENTER(); |
| 8572 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND24; |
| 8573 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8574 | } |
| 8575 | |
| 8576 | static inline void hri_can_set_NDAT1_ND25_bit(const void *const hw) |
| 8577 | { |
| 8578 | CAN_CRITICAL_SECTION_ENTER(); |
| 8579 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND25; |
| 8580 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8581 | } |
| 8582 | |
| 8583 | static inline bool hri_can_get_NDAT1_ND25_bit(const void *const hw) |
| 8584 | { |
| 8585 | uint32_t tmp; |
| 8586 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8587 | tmp = (tmp & CAN_NDAT1_ND25) >> CAN_NDAT1_ND25_Pos; |
| 8588 | return (bool)tmp; |
| 8589 | } |
| 8590 | |
| 8591 | static inline void hri_can_write_NDAT1_ND25_bit(const void *const hw, bool value) |
| 8592 | { |
| 8593 | uint32_t tmp; |
| 8594 | CAN_CRITICAL_SECTION_ENTER(); |
| 8595 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8596 | tmp &= ~CAN_NDAT1_ND25; |
| 8597 | tmp |= value << CAN_NDAT1_ND25_Pos; |
| 8598 | ((Can *)hw)->NDAT1.reg = tmp; |
| 8599 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8600 | } |
| 8601 | |
| 8602 | static inline void hri_can_clear_NDAT1_ND25_bit(const void *const hw) |
| 8603 | { |
| 8604 | CAN_CRITICAL_SECTION_ENTER(); |
| 8605 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND25; |
| 8606 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8607 | } |
| 8608 | |
| 8609 | static inline void hri_can_toggle_NDAT1_ND25_bit(const void *const hw) |
| 8610 | { |
| 8611 | CAN_CRITICAL_SECTION_ENTER(); |
| 8612 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND25; |
| 8613 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8614 | } |
| 8615 | |
| 8616 | static inline void hri_can_set_NDAT1_ND26_bit(const void *const hw) |
| 8617 | { |
| 8618 | CAN_CRITICAL_SECTION_ENTER(); |
| 8619 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND26; |
| 8620 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8621 | } |
| 8622 | |
| 8623 | static inline bool hri_can_get_NDAT1_ND26_bit(const void *const hw) |
| 8624 | { |
| 8625 | uint32_t tmp; |
| 8626 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8627 | tmp = (tmp & CAN_NDAT1_ND26) >> CAN_NDAT1_ND26_Pos; |
| 8628 | return (bool)tmp; |
| 8629 | } |
| 8630 | |
| 8631 | static inline void hri_can_write_NDAT1_ND26_bit(const void *const hw, bool value) |
| 8632 | { |
| 8633 | uint32_t tmp; |
| 8634 | CAN_CRITICAL_SECTION_ENTER(); |
| 8635 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8636 | tmp &= ~CAN_NDAT1_ND26; |
| 8637 | tmp |= value << CAN_NDAT1_ND26_Pos; |
| 8638 | ((Can *)hw)->NDAT1.reg = tmp; |
| 8639 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8640 | } |
| 8641 | |
| 8642 | static inline void hri_can_clear_NDAT1_ND26_bit(const void *const hw) |
| 8643 | { |
| 8644 | CAN_CRITICAL_SECTION_ENTER(); |
| 8645 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND26; |
| 8646 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8647 | } |
| 8648 | |
| 8649 | static inline void hri_can_toggle_NDAT1_ND26_bit(const void *const hw) |
| 8650 | { |
| 8651 | CAN_CRITICAL_SECTION_ENTER(); |
| 8652 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND26; |
| 8653 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8654 | } |
| 8655 | |
| 8656 | static inline void hri_can_set_NDAT1_ND27_bit(const void *const hw) |
| 8657 | { |
| 8658 | CAN_CRITICAL_SECTION_ENTER(); |
| 8659 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND27; |
| 8660 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8661 | } |
| 8662 | |
| 8663 | static inline bool hri_can_get_NDAT1_ND27_bit(const void *const hw) |
| 8664 | { |
| 8665 | uint32_t tmp; |
| 8666 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8667 | tmp = (tmp & CAN_NDAT1_ND27) >> CAN_NDAT1_ND27_Pos; |
| 8668 | return (bool)tmp; |
| 8669 | } |
| 8670 | |
| 8671 | static inline void hri_can_write_NDAT1_ND27_bit(const void *const hw, bool value) |
| 8672 | { |
| 8673 | uint32_t tmp; |
| 8674 | CAN_CRITICAL_SECTION_ENTER(); |
| 8675 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8676 | tmp &= ~CAN_NDAT1_ND27; |
| 8677 | tmp |= value << CAN_NDAT1_ND27_Pos; |
| 8678 | ((Can *)hw)->NDAT1.reg = tmp; |
| 8679 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8680 | } |
| 8681 | |
| 8682 | static inline void hri_can_clear_NDAT1_ND27_bit(const void *const hw) |
| 8683 | { |
| 8684 | CAN_CRITICAL_SECTION_ENTER(); |
| 8685 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND27; |
| 8686 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8687 | } |
| 8688 | |
| 8689 | static inline void hri_can_toggle_NDAT1_ND27_bit(const void *const hw) |
| 8690 | { |
| 8691 | CAN_CRITICAL_SECTION_ENTER(); |
| 8692 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND27; |
| 8693 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8694 | } |
| 8695 | |
| 8696 | static inline void hri_can_set_NDAT1_ND28_bit(const void *const hw) |
| 8697 | { |
| 8698 | CAN_CRITICAL_SECTION_ENTER(); |
| 8699 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND28; |
| 8700 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8701 | } |
| 8702 | |
| 8703 | static inline bool hri_can_get_NDAT1_ND28_bit(const void *const hw) |
| 8704 | { |
| 8705 | uint32_t tmp; |
| 8706 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8707 | tmp = (tmp & CAN_NDAT1_ND28) >> CAN_NDAT1_ND28_Pos; |
| 8708 | return (bool)tmp; |
| 8709 | } |
| 8710 | |
| 8711 | static inline void hri_can_write_NDAT1_ND28_bit(const void *const hw, bool value) |
| 8712 | { |
| 8713 | uint32_t tmp; |
| 8714 | CAN_CRITICAL_SECTION_ENTER(); |
| 8715 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8716 | tmp &= ~CAN_NDAT1_ND28; |
| 8717 | tmp |= value << CAN_NDAT1_ND28_Pos; |
| 8718 | ((Can *)hw)->NDAT1.reg = tmp; |
| 8719 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8720 | } |
| 8721 | |
| 8722 | static inline void hri_can_clear_NDAT1_ND28_bit(const void *const hw) |
| 8723 | { |
| 8724 | CAN_CRITICAL_SECTION_ENTER(); |
| 8725 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND28; |
| 8726 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8727 | } |
| 8728 | |
| 8729 | static inline void hri_can_toggle_NDAT1_ND28_bit(const void *const hw) |
| 8730 | { |
| 8731 | CAN_CRITICAL_SECTION_ENTER(); |
| 8732 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND28; |
| 8733 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8734 | } |
| 8735 | |
| 8736 | static inline void hri_can_set_NDAT1_ND29_bit(const void *const hw) |
| 8737 | { |
| 8738 | CAN_CRITICAL_SECTION_ENTER(); |
| 8739 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND29; |
| 8740 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8741 | } |
| 8742 | |
| 8743 | static inline bool hri_can_get_NDAT1_ND29_bit(const void *const hw) |
| 8744 | { |
| 8745 | uint32_t tmp; |
| 8746 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8747 | tmp = (tmp & CAN_NDAT1_ND29) >> CAN_NDAT1_ND29_Pos; |
| 8748 | return (bool)tmp; |
| 8749 | } |
| 8750 | |
| 8751 | static inline void hri_can_write_NDAT1_ND29_bit(const void *const hw, bool value) |
| 8752 | { |
| 8753 | uint32_t tmp; |
| 8754 | CAN_CRITICAL_SECTION_ENTER(); |
| 8755 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8756 | tmp &= ~CAN_NDAT1_ND29; |
| 8757 | tmp |= value << CAN_NDAT1_ND29_Pos; |
| 8758 | ((Can *)hw)->NDAT1.reg = tmp; |
| 8759 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8760 | } |
| 8761 | |
| 8762 | static inline void hri_can_clear_NDAT1_ND29_bit(const void *const hw) |
| 8763 | { |
| 8764 | CAN_CRITICAL_SECTION_ENTER(); |
| 8765 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND29; |
| 8766 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8767 | } |
| 8768 | |
| 8769 | static inline void hri_can_toggle_NDAT1_ND29_bit(const void *const hw) |
| 8770 | { |
| 8771 | CAN_CRITICAL_SECTION_ENTER(); |
| 8772 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND29; |
| 8773 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8774 | } |
| 8775 | |
| 8776 | static inline void hri_can_set_NDAT1_ND30_bit(const void *const hw) |
| 8777 | { |
| 8778 | CAN_CRITICAL_SECTION_ENTER(); |
| 8779 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND30; |
| 8780 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8781 | } |
| 8782 | |
| 8783 | static inline bool hri_can_get_NDAT1_ND30_bit(const void *const hw) |
| 8784 | { |
| 8785 | uint32_t tmp; |
| 8786 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8787 | tmp = (tmp & CAN_NDAT1_ND30) >> CAN_NDAT1_ND30_Pos; |
| 8788 | return (bool)tmp; |
| 8789 | } |
| 8790 | |
| 8791 | static inline void hri_can_write_NDAT1_ND30_bit(const void *const hw, bool value) |
| 8792 | { |
| 8793 | uint32_t tmp; |
| 8794 | CAN_CRITICAL_SECTION_ENTER(); |
| 8795 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8796 | tmp &= ~CAN_NDAT1_ND30; |
| 8797 | tmp |= value << CAN_NDAT1_ND30_Pos; |
| 8798 | ((Can *)hw)->NDAT1.reg = tmp; |
| 8799 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8800 | } |
| 8801 | |
| 8802 | static inline void hri_can_clear_NDAT1_ND30_bit(const void *const hw) |
| 8803 | { |
| 8804 | CAN_CRITICAL_SECTION_ENTER(); |
| 8805 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND30; |
| 8806 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8807 | } |
| 8808 | |
| 8809 | static inline void hri_can_toggle_NDAT1_ND30_bit(const void *const hw) |
| 8810 | { |
| 8811 | CAN_CRITICAL_SECTION_ENTER(); |
| 8812 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND30; |
| 8813 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8814 | } |
| 8815 | |
| 8816 | static inline void hri_can_set_NDAT1_ND31_bit(const void *const hw) |
| 8817 | { |
| 8818 | CAN_CRITICAL_SECTION_ENTER(); |
| 8819 | ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND31; |
| 8820 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8821 | } |
| 8822 | |
| 8823 | static inline bool hri_can_get_NDAT1_ND31_bit(const void *const hw) |
| 8824 | { |
| 8825 | uint32_t tmp; |
| 8826 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8827 | tmp = (tmp & CAN_NDAT1_ND31) >> CAN_NDAT1_ND31_Pos; |
| 8828 | return (bool)tmp; |
| 8829 | } |
| 8830 | |
| 8831 | static inline void hri_can_write_NDAT1_ND31_bit(const void *const hw, bool value) |
| 8832 | { |
| 8833 | uint32_t tmp; |
| 8834 | CAN_CRITICAL_SECTION_ENTER(); |
| 8835 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8836 | tmp &= ~CAN_NDAT1_ND31; |
| 8837 | tmp |= value << CAN_NDAT1_ND31_Pos; |
| 8838 | ((Can *)hw)->NDAT1.reg = tmp; |
| 8839 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8840 | } |
| 8841 | |
| 8842 | static inline void hri_can_clear_NDAT1_ND31_bit(const void *const hw) |
| 8843 | { |
| 8844 | CAN_CRITICAL_SECTION_ENTER(); |
| 8845 | ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND31; |
| 8846 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8847 | } |
| 8848 | |
| 8849 | static inline void hri_can_toggle_NDAT1_ND31_bit(const void *const hw) |
| 8850 | { |
| 8851 | CAN_CRITICAL_SECTION_ENTER(); |
| 8852 | ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND31; |
| 8853 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8854 | } |
| 8855 | |
| 8856 | static inline void hri_can_set_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) |
| 8857 | { |
| 8858 | CAN_CRITICAL_SECTION_ENTER(); |
| 8859 | ((Can *)hw)->NDAT1.reg |= mask; |
| 8860 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8861 | } |
| 8862 | |
| 8863 | static inline hri_can_ndat1_reg_t hri_can_get_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) |
| 8864 | { |
| 8865 | uint32_t tmp; |
| 8866 | tmp = ((Can *)hw)->NDAT1.reg; |
| 8867 | tmp &= mask; |
| 8868 | return tmp; |
| 8869 | } |
| 8870 | |
| 8871 | static inline void hri_can_write_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t data) |
| 8872 | { |
| 8873 | CAN_CRITICAL_SECTION_ENTER(); |
| 8874 | ((Can *)hw)->NDAT1.reg = data; |
| 8875 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8876 | } |
| 8877 | |
| 8878 | static inline void hri_can_clear_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) |
| 8879 | { |
| 8880 | CAN_CRITICAL_SECTION_ENTER(); |
| 8881 | ((Can *)hw)->NDAT1.reg &= ~mask; |
| 8882 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8883 | } |
| 8884 | |
| 8885 | static inline void hri_can_toggle_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) |
| 8886 | { |
| 8887 | CAN_CRITICAL_SECTION_ENTER(); |
| 8888 | ((Can *)hw)->NDAT1.reg ^= mask; |
| 8889 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8890 | } |
| 8891 | |
| 8892 | static inline hri_can_ndat1_reg_t hri_can_read_NDAT1_reg(const void *const hw) |
| 8893 | { |
| 8894 | return ((Can *)hw)->NDAT1.reg; |
| 8895 | } |
| 8896 | |
| 8897 | static inline void hri_can_set_NDAT2_ND32_bit(const void *const hw) |
| 8898 | { |
| 8899 | CAN_CRITICAL_SECTION_ENTER(); |
| 8900 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND32; |
| 8901 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8902 | } |
| 8903 | |
| 8904 | static inline bool hri_can_get_NDAT2_ND32_bit(const void *const hw) |
| 8905 | { |
| 8906 | uint32_t tmp; |
| 8907 | tmp = ((Can *)hw)->NDAT2.reg; |
| 8908 | tmp = (tmp & CAN_NDAT2_ND32) >> CAN_NDAT2_ND32_Pos; |
| 8909 | return (bool)tmp; |
| 8910 | } |
| 8911 | |
| 8912 | static inline void hri_can_write_NDAT2_ND32_bit(const void *const hw, bool value) |
| 8913 | { |
| 8914 | uint32_t tmp; |
| 8915 | CAN_CRITICAL_SECTION_ENTER(); |
| 8916 | tmp = ((Can *)hw)->NDAT2.reg; |
| 8917 | tmp &= ~CAN_NDAT2_ND32; |
| 8918 | tmp |= value << CAN_NDAT2_ND32_Pos; |
| 8919 | ((Can *)hw)->NDAT2.reg = tmp; |
| 8920 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8921 | } |
| 8922 | |
| 8923 | static inline void hri_can_clear_NDAT2_ND32_bit(const void *const hw) |
| 8924 | { |
| 8925 | CAN_CRITICAL_SECTION_ENTER(); |
| 8926 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND32; |
| 8927 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8928 | } |
| 8929 | |
| 8930 | static inline void hri_can_toggle_NDAT2_ND32_bit(const void *const hw) |
| 8931 | { |
| 8932 | CAN_CRITICAL_SECTION_ENTER(); |
| 8933 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND32; |
| 8934 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8935 | } |
| 8936 | |
| 8937 | static inline void hri_can_set_NDAT2_ND33_bit(const void *const hw) |
| 8938 | { |
| 8939 | CAN_CRITICAL_SECTION_ENTER(); |
| 8940 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND33; |
| 8941 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8942 | } |
| 8943 | |
| 8944 | static inline bool hri_can_get_NDAT2_ND33_bit(const void *const hw) |
| 8945 | { |
| 8946 | uint32_t tmp; |
| 8947 | tmp = ((Can *)hw)->NDAT2.reg; |
| 8948 | tmp = (tmp & CAN_NDAT2_ND33) >> CAN_NDAT2_ND33_Pos; |
| 8949 | return (bool)tmp; |
| 8950 | } |
| 8951 | |
| 8952 | static inline void hri_can_write_NDAT2_ND33_bit(const void *const hw, bool value) |
| 8953 | { |
| 8954 | uint32_t tmp; |
| 8955 | CAN_CRITICAL_SECTION_ENTER(); |
| 8956 | tmp = ((Can *)hw)->NDAT2.reg; |
| 8957 | tmp &= ~CAN_NDAT2_ND33; |
| 8958 | tmp |= value << CAN_NDAT2_ND33_Pos; |
| 8959 | ((Can *)hw)->NDAT2.reg = tmp; |
| 8960 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8961 | } |
| 8962 | |
| 8963 | static inline void hri_can_clear_NDAT2_ND33_bit(const void *const hw) |
| 8964 | { |
| 8965 | CAN_CRITICAL_SECTION_ENTER(); |
| 8966 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND33; |
| 8967 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8968 | } |
| 8969 | |
| 8970 | static inline void hri_can_toggle_NDAT2_ND33_bit(const void *const hw) |
| 8971 | { |
| 8972 | CAN_CRITICAL_SECTION_ENTER(); |
| 8973 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND33; |
| 8974 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8975 | } |
| 8976 | |
| 8977 | static inline void hri_can_set_NDAT2_ND34_bit(const void *const hw) |
| 8978 | { |
| 8979 | CAN_CRITICAL_SECTION_ENTER(); |
| 8980 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND34; |
| 8981 | CAN_CRITICAL_SECTION_LEAVE(); |
| 8982 | } |
| 8983 | |
| 8984 | static inline bool hri_can_get_NDAT2_ND34_bit(const void *const hw) |
| 8985 | { |
| 8986 | uint32_t tmp; |
| 8987 | tmp = ((Can *)hw)->NDAT2.reg; |
| 8988 | tmp = (tmp & CAN_NDAT2_ND34) >> CAN_NDAT2_ND34_Pos; |
| 8989 | return (bool)tmp; |
| 8990 | } |
| 8991 | |
| 8992 | static inline void hri_can_write_NDAT2_ND34_bit(const void *const hw, bool value) |
| 8993 | { |
| 8994 | uint32_t tmp; |
| 8995 | CAN_CRITICAL_SECTION_ENTER(); |
| 8996 | tmp = ((Can *)hw)->NDAT2.reg; |
| 8997 | tmp &= ~CAN_NDAT2_ND34; |
| 8998 | tmp |= value << CAN_NDAT2_ND34_Pos; |
| 8999 | ((Can *)hw)->NDAT2.reg = tmp; |
| 9000 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9001 | } |
| 9002 | |
| 9003 | static inline void hri_can_clear_NDAT2_ND34_bit(const void *const hw) |
| 9004 | { |
| 9005 | CAN_CRITICAL_SECTION_ENTER(); |
| 9006 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND34; |
| 9007 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9008 | } |
| 9009 | |
| 9010 | static inline void hri_can_toggle_NDAT2_ND34_bit(const void *const hw) |
| 9011 | { |
| 9012 | CAN_CRITICAL_SECTION_ENTER(); |
| 9013 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND34; |
| 9014 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9015 | } |
| 9016 | |
| 9017 | static inline void hri_can_set_NDAT2_ND35_bit(const void *const hw) |
| 9018 | { |
| 9019 | CAN_CRITICAL_SECTION_ENTER(); |
| 9020 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND35; |
| 9021 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9022 | } |
| 9023 | |
| 9024 | static inline bool hri_can_get_NDAT2_ND35_bit(const void *const hw) |
| 9025 | { |
| 9026 | uint32_t tmp; |
| 9027 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9028 | tmp = (tmp & CAN_NDAT2_ND35) >> CAN_NDAT2_ND35_Pos; |
| 9029 | return (bool)tmp; |
| 9030 | } |
| 9031 | |
| 9032 | static inline void hri_can_write_NDAT2_ND35_bit(const void *const hw, bool value) |
| 9033 | { |
| 9034 | uint32_t tmp; |
| 9035 | CAN_CRITICAL_SECTION_ENTER(); |
| 9036 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9037 | tmp &= ~CAN_NDAT2_ND35; |
| 9038 | tmp |= value << CAN_NDAT2_ND35_Pos; |
| 9039 | ((Can *)hw)->NDAT2.reg = tmp; |
| 9040 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9041 | } |
| 9042 | |
| 9043 | static inline void hri_can_clear_NDAT2_ND35_bit(const void *const hw) |
| 9044 | { |
| 9045 | CAN_CRITICAL_SECTION_ENTER(); |
| 9046 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND35; |
| 9047 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9048 | } |
| 9049 | |
| 9050 | static inline void hri_can_toggle_NDAT2_ND35_bit(const void *const hw) |
| 9051 | { |
| 9052 | CAN_CRITICAL_SECTION_ENTER(); |
| 9053 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND35; |
| 9054 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9055 | } |
| 9056 | |
| 9057 | static inline void hri_can_set_NDAT2_ND36_bit(const void *const hw) |
| 9058 | { |
| 9059 | CAN_CRITICAL_SECTION_ENTER(); |
| 9060 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND36; |
| 9061 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9062 | } |
| 9063 | |
| 9064 | static inline bool hri_can_get_NDAT2_ND36_bit(const void *const hw) |
| 9065 | { |
| 9066 | uint32_t tmp; |
| 9067 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9068 | tmp = (tmp & CAN_NDAT2_ND36) >> CAN_NDAT2_ND36_Pos; |
| 9069 | return (bool)tmp; |
| 9070 | } |
| 9071 | |
| 9072 | static inline void hri_can_write_NDAT2_ND36_bit(const void *const hw, bool value) |
| 9073 | { |
| 9074 | uint32_t tmp; |
| 9075 | CAN_CRITICAL_SECTION_ENTER(); |
| 9076 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9077 | tmp &= ~CAN_NDAT2_ND36; |
| 9078 | tmp |= value << CAN_NDAT2_ND36_Pos; |
| 9079 | ((Can *)hw)->NDAT2.reg = tmp; |
| 9080 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9081 | } |
| 9082 | |
| 9083 | static inline void hri_can_clear_NDAT2_ND36_bit(const void *const hw) |
| 9084 | { |
| 9085 | CAN_CRITICAL_SECTION_ENTER(); |
| 9086 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND36; |
| 9087 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9088 | } |
| 9089 | |
| 9090 | static inline void hri_can_toggle_NDAT2_ND36_bit(const void *const hw) |
| 9091 | { |
| 9092 | CAN_CRITICAL_SECTION_ENTER(); |
| 9093 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND36; |
| 9094 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9095 | } |
| 9096 | |
| 9097 | static inline void hri_can_set_NDAT2_ND37_bit(const void *const hw) |
| 9098 | { |
| 9099 | CAN_CRITICAL_SECTION_ENTER(); |
| 9100 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND37; |
| 9101 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9102 | } |
| 9103 | |
| 9104 | static inline bool hri_can_get_NDAT2_ND37_bit(const void *const hw) |
| 9105 | { |
| 9106 | uint32_t tmp; |
| 9107 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9108 | tmp = (tmp & CAN_NDAT2_ND37) >> CAN_NDAT2_ND37_Pos; |
| 9109 | return (bool)tmp; |
| 9110 | } |
| 9111 | |
| 9112 | static inline void hri_can_write_NDAT2_ND37_bit(const void *const hw, bool value) |
| 9113 | { |
| 9114 | uint32_t tmp; |
| 9115 | CAN_CRITICAL_SECTION_ENTER(); |
| 9116 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9117 | tmp &= ~CAN_NDAT2_ND37; |
| 9118 | tmp |= value << CAN_NDAT2_ND37_Pos; |
| 9119 | ((Can *)hw)->NDAT2.reg = tmp; |
| 9120 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9121 | } |
| 9122 | |
| 9123 | static inline void hri_can_clear_NDAT2_ND37_bit(const void *const hw) |
| 9124 | { |
| 9125 | CAN_CRITICAL_SECTION_ENTER(); |
| 9126 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND37; |
| 9127 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9128 | } |
| 9129 | |
| 9130 | static inline void hri_can_toggle_NDAT2_ND37_bit(const void *const hw) |
| 9131 | { |
| 9132 | CAN_CRITICAL_SECTION_ENTER(); |
| 9133 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND37; |
| 9134 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9135 | } |
| 9136 | |
| 9137 | static inline void hri_can_set_NDAT2_ND38_bit(const void *const hw) |
| 9138 | { |
| 9139 | CAN_CRITICAL_SECTION_ENTER(); |
| 9140 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND38; |
| 9141 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9142 | } |
| 9143 | |
| 9144 | static inline bool hri_can_get_NDAT2_ND38_bit(const void *const hw) |
| 9145 | { |
| 9146 | uint32_t tmp; |
| 9147 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9148 | tmp = (tmp & CAN_NDAT2_ND38) >> CAN_NDAT2_ND38_Pos; |
| 9149 | return (bool)tmp; |
| 9150 | } |
| 9151 | |
| 9152 | static inline void hri_can_write_NDAT2_ND38_bit(const void *const hw, bool value) |
| 9153 | { |
| 9154 | uint32_t tmp; |
| 9155 | CAN_CRITICAL_SECTION_ENTER(); |
| 9156 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9157 | tmp &= ~CAN_NDAT2_ND38; |
| 9158 | tmp |= value << CAN_NDAT2_ND38_Pos; |
| 9159 | ((Can *)hw)->NDAT2.reg = tmp; |
| 9160 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9161 | } |
| 9162 | |
| 9163 | static inline void hri_can_clear_NDAT2_ND38_bit(const void *const hw) |
| 9164 | { |
| 9165 | CAN_CRITICAL_SECTION_ENTER(); |
| 9166 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND38; |
| 9167 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9168 | } |
| 9169 | |
| 9170 | static inline void hri_can_toggle_NDAT2_ND38_bit(const void *const hw) |
| 9171 | { |
| 9172 | CAN_CRITICAL_SECTION_ENTER(); |
| 9173 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND38; |
| 9174 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9175 | } |
| 9176 | |
| 9177 | static inline void hri_can_set_NDAT2_ND39_bit(const void *const hw) |
| 9178 | { |
| 9179 | CAN_CRITICAL_SECTION_ENTER(); |
| 9180 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND39; |
| 9181 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9182 | } |
| 9183 | |
| 9184 | static inline bool hri_can_get_NDAT2_ND39_bit(const void *const hw) |
| 9185 | { |
| 9186 | uint32_t tmp; |
| 9187 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9188 | tmp = (tmp & CAN_NDAT2_ND39) >> CAN_NDAT2_ND39_Pos; |
| 9189 | return (bool)tmp; |
| 9190 | } |
| 9191 | |
| 9192 | static inline void hri_can_write_NDAT2_ND39_bit(const void *const hw, bool value) |
| 9193 | { |
| 9194 | uint32_t tmp; |
| 9195 | CAN_CRITICAL_SECTION_ENTER(); |
| 9196 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9197 | tmp &= ~CAN_NDAT2_ND39; |
| 9198 | tmp |= value << CAN_NDAT2_ND39_Pos; |
| 9199 | ((Can *)hw)->NDAT2.reg = tmp; |
| 9200 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9201 | } |
| 9202 | |
| 9203 | static inline void hri_can_clear_NDAT2_ND39_bit(const void *const hw) |
| 9204 | { |
| 9205 | CAN_CRITICAL_SECTION_ENTER(); |
| 9206 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND39; |
| 9207 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9208 | } |
| 9209 | |
| 9210 | static inline void hri_can_toggle_NDAT2_ND39_bit(const void *const hw) |
| 9211 | { |
| 9212 | CAN_CRITICAL_SECTION_ENTER(); |
| 9213 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND39; |
| 9214 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9215 | } |
| 9216 | |
| 9217 | static inline void hri_can_set_NDAT2_ND40_bit(const void *const hw) |
| 9218 | { |
| 9219 | CAN_CRITICAL_SECTION_ENTER(); |
| 9220 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND40; |
| 9221 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9222 | } |
| 9223 | |
| 9224 | static inline bool hri_can_get_NDAT2_ND40_bit(const void *const hw) |
| 9225 | { |
| 9226 | uint32_t tmp; |
| 9227 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9228 | tmp = (tmp & CAN_NDAT2_ND40) >> CAN_NDAT2_ND40_Pos; |
| 9229 | return (bool)tmp; |
| 9230 | } |
| 9231 | |
| 9232 | static inline void hri_can_write_NDAT2_ND40_bit(const void *const hw, bool value) |
| 9233 | { |
| 9234 | uint32_t tmp; |
| 9235 | CAN_CRITICAL_SECTION_ENTER(); |
| 9236 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9237 | tmp &= ~CAN_NDAT2_ND40; |
| 9238 | tmp |= value << CAN_NDAT2_ND40_Pos; |
| 9239 | ((Can *)hw)->NDAT2.reg = tmp; |
| 9240 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9241 | } |
| 9242 | |
| 9243 | static inline void hri_can_clear_NDAT2_ND40_bit(const void *const hw) |
| 9244 | { |
| 9245 | CAN_CRITICAL_SECTION_ENTER(); |
| 9246 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND40; |
| 9247 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9248 | } |
| 9249 | |
| 9250 | static inline void hri_can_toggle_NDAT2_ND40_bit(const void *const hw) |
| 9251 | { |
| 9252 | CAN_CRITICAL_SECTION_ENTER(); |
| 9253 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND40; |
| 9254 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9255 | } |
| 9256 | |
| 9257 | static inline void hri_can_set_NDAT2_ND41_bit(const void *const hw) |
| 9258 | { |
| 9259 | CAN_CRITICAL_SECTION_ENTER(); |
| 9260 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND41; |
| 9261 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9262 | } |
| 9263 | |
| 9264 | static inline bool hri_can_get_NDAT2_ND41_bit(const void *const hw) |
| 9265 | { |
| 9266 | uint32_t tmp; |
| 9267 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9268 | tmp = (tmp & CAN_NDAT2_ND41) >> CAN_NDAT2_ND41_Pos; |
| 9269 | return (bool)tmp; |
| 9270 | } |
| 9271 | |
| 9272 | static inline void hri_can_write_NDAT2_ND41_bit(const void *const hw, bool value) |
| 9273 | { |
| 9274 | uint32_t tmp; |
| 9275 | CAN_CRITICAL_SECTION_ENTER(); |
| 9276 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9277 | tmp &= ~CAN_NDAT2_ND41; |
| 9278 | tmp |= value << CAN_NDAT2_ND41_Pos; |
| 9279 | ((Can *)hw)->NDAT2.reg = tmp; |
| 9280 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9281 | } |
| 9282 | |
| 9283 | static inline void hri_can_clear_NDAT2_ND41_bit(const void *const hw) |
| 9284 | { |
| 9285 | CAN_CRITICAL_SECTION_ENTER(); |
| 9286 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND41; |
| 9287 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9288 | } |
| 9289 | |
| 9290 | static inline void hri_can_toggle_NDAT2_ND41_bit(const void *const hw) |
| 9291 | { |
| 9292 | CAN_CRITICAL_SECTION_ENTER(); |
| 9293 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND41; |
| 9294 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9295 | } |
| 9296 | |
| 9297 | static inline void hri_can_set_NDAT2_ND42_bit(const void *const hw) |
| 9298 | { |
| 9299 | CAN_CRITICAL_SECTION_ENTER(); |
| 9300 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND42; |
| 9301 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9302 | } |
| 9303 | |
| 9304 | static inline bool hri_can_get_NDAT2_ND42_bit(const void *const hw) |
| 9305 | { |
| 9306 | uint32_t tmp; |
| 9307 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9308 | tmp = (tmp & CAN_NDAT2_ND42) >> CAN_NDAT2_ND42_Pos; |
| 9309 | return (bool)tmp; |
| 9310 | } |
| 9311 | |
| 9312 | static inline void hri_can_write_NDAT2_ND42_bit(const void *const hw, bool value) |
| 9313 | { |
| 9314 | uint32_t tmp; |
| 9315 | CAN_CRITICAL_SECTION_ENTER(); |
| 9316 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9317 | tmp &= ~CAN_NDAT2_ND42; |
| 9318 | tmp |= value << CAN_NDAT2_ND42_Pos; |
| 9319 | ((Can *)hw)->NDAT2.reg = tmp; |
| 9320 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9321 | } |
| 9322 | |
| 9323 | static inline void hri_can_clear_NDAT2_ND42_bit(const void *const hw) |
| 9324 | { |
| 9325 | CAN_CRITICAL_SECTION_ENTER(); |
| 9326 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND42; |
| 9327 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9328 | } |
| 9329 | |
| 9330 | static inline void hri_can_toggle_NDAT2_ND42_bit(const void *const hw) |
| 9331 | { |
| 9332 | CAN_CRITICAL_SECTION_ENTER(); |
| 9333 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND42; |
| 9334 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9335 | } |
| 9336 | |
| 9337 | static inline void hri_can_set_NDAT2_ND43_bit(const void *const hw) |
| 9338 | { |
| 9339 | CAN_CRITICAL_SECTION_ENTER(); |
| 9340 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND43; |
| 9341 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9342 | } |
| 9343 | |
| 9344 | static inline bool hri_can_get_NDAT2_ND43_bit(const void *const hw) |
| 9345 | { |
| 9346 | uint32_t tmp; |
| 9347 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9348 | tmp = (tmp & CAN_NDAT2_ND43) >> CAN_NDAT2_ND43_Pos; |
| 9349 | return (bool)tmp; |
| 9350 | } |
| 9351 | |
| 9352 | static inline void hri_can_write_NDAT2_ND43_bit(const void *const hw, bool value) |
| 9353 | { |
| 9354 | uint32_t tmp; |
| 9355 | CAN_CRITICAL_SECTION_ENTER(); |
| 9356 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9357 | tmp &= ~CAN_NDAT2_ND43; |
| 9358 | tmp |= value << CAN_NDAT2_ND43_Pos; |
| 9359 | ((Can *)hw)->NDAT2.reg = tmp; |
| 9360 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9361 | } |
| 9362 | |
| 9363 | static inline void hri_can_clear_NDAT2_ND43_bit(const void *const hw) |
| 9364 | { |
| 9365 | CAN_CRITICAL_SECTION_ENTER(); |
| 9366 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND43; |
| 9367 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9368 | } |
| 9369 | |
| 9370 | static inline void hri_can_toggle_NDAT2_ND43_bit(const void *const hw) |
| 9371 | { |
| 9372 | CAN_CRITICAL_SECTION_ENTER(); |
| 9373 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND43; |
| 9374 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9375 | } |
| 9376 | |
| 9377 | static inline void hri_can_set_NDAT2_ND44_bit(const void *const hw) |
| 9378 | { |
| 9379 | CAN_CRITICAL_SECTION_ENTER(); |
| 9380 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND44; |
| 9381 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9382 | } |
| 9383 | |
| 9384 | static inline bool hri_can_get_NDAT2_ND44_bit(const void *const hw) |
| 9385 | { |
| 9386 | uint32_t tmp; |
| 9387 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9388 | tmp = (tmp & CAN_NDAT2_ND44) >> CAN_NDAT2_ND44_Pos; |
| 9389 | return (bool)tmp; |
| 9390 | } |
| 9391 | |
| 9392 | static inline void hri_can_write_NDAT2_ND44_bit(const void *const hw, bool value) |
| 9393 | { |
| 9394 | uint32_t tmp; |
| 9395 | CAN_CRITICAL_SECTION_ENTER(); |
| 9396 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9397 | tmp &= ~CAN_NDAT2_ND44; |
| 9398 | tmp |= value << CAN_NDAT2_ND44_Pos; |
| 9399 | ((Can *)hw)->NDAT2.reg = tmp; |
| 9400 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9401 | } |
| 9402 | |
| 9403 | static inline void hri_can_clear_NDAT2_ND44_bit(const void *const hw) |
| 9404 | { |
| 9405 | CAN_CRITICAL_SECTION_ENTER(); |
| 9406 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND44; |
| 9407 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9408 | } |
| 9409 | |
| 9410 | static inline void hri_can_toggle_NDAT2_ND44_bit(const void *const hw) |
| 9411 | { |
| 9412 | CAN_CRITICAL_SECTION_ENTER(); |
| 9413 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND44; |
| 9414 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9415 | } |
| 9416 | |
| 9417 | static inline void hri_can_set_NDAT2_ND45_bit(const void *const hw) |
| 9418 | { |
| 9419 | CAN_CRITICAL_SECTION_ENTER(); |
| 9420 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND45; |
| 9421 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9422 | } |
| 9423 | |
| 9424 | static inline bool hri_can_get_NDAT2_ND45_bit(const void *const hw) |
| 9425 | { |
| 9426 | uint32_t tmp; |
| 9427 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9428 | tmp = (tmp & CAN_NDAT2_ND45) >> CAN_NDAT2_ND45_Pos; |
| 9429 | return (bool)tmp; |
| 9430 | } |
| 9431 | |
| 9432 | static inline void hri_can_write_NDAT2_ND45_bit(const void *const hw, bool value) |
| 9433 | { |
| 9434 | uint32_t tmp; |
| 9435 | CAN_CRITICAL_SECTION_ENTER(); |
| 9436 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9437 | tmp &= ~CAN_NDAT2_ND45; |
| 9438 | tmp |= value << CAN_NDAT2_ND45_Pos; |
| 9439 | ((Can *)hw)->NDAT2.reg = tmp; |
| 9440 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9441 | } |
| 9442 | |
| 9443 | static inline void hri_can_clear_NDAT2_ND45_bit(const void *const hw) |
| 9444 | { |
| 9445 | CAN_CRITICAL_SECTION_ENTER(); |
| 9446 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND45; |
| 9447 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9448 | } |
| 9449 | |
| 9450 | static inline void hri_can_toggle_NDAT2_ND45_bit(const void *const hw) |
| 9451 | { |
| 9452 | CAN_CRITICAL_SECTION_ENTER(); |
| 9453 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND45; |
| 9454 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9455 | } |
| 9456 | |
| 9457 | static inline void hri_can_set_NDAT2_ND46_bit(const void *const hw) |
| 9458 | { |
| 9459 | CAN_CRITICAL_SECTION_ENTER(); |
| 9460 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND46; |
| 9461 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9462 | } |
| 9463 | |
| 9464 | static inline bool hri_can_get_NDAT2_ND46_bit(const void *const hw) |
| 9465 | { |
| 9466 | uint32_t tmp; |
| 9467 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9468 | tmp = (tmp & CAN_NDAT2_ND46) >> CAN_NDAT2_ND46_Pos; |
| 9469 | return (bool)tmp; |
| 9470 | } |
| 9471 | |
| 9472 | static inline void hri_can_write_NDAT2_ND46_bit(const void *const hw, bool value) |
| 9473 | { |
| 9474 | uint32_t tmp; |
| 9475 | CAN_CRITICAL_SECTION_ENTER(); |
| 9476 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9477 | tmp &= ~CAN_NDAT2_ND46; |
| 9478 | tmp |= value << CAN_NDAT2_ND46_Pos; |
| 9479 | ((Can *)hw)->NDAT2.reg = tmp; |
| 9480 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9481 | } |
| 9482 | |
| 9483 | static inline void hri_can_clear_NDAT2_ND46_bit(const void *const hw) |
| 9484 | { |
| 9485 | CAN_CRITICAL_SECTION_ENTER(); |
| 9486 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND46; |
| 9487 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9488 | } |
| 9489 | |
| 9490 | static inline void hri_can_toggle_NDAT2_ND46_bit(const void *const hw) |
| 9491 | { |
| 9492 | CAN_CRITICAL_SECTION_ENTER(); |
| 9493 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND46; |
| 9494 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9495 | } |
| 9496 | |
| 9497 | static inline void hri_can_set_NDAT2_ND47_bit(const void *const hw) |
| 9498 | { |
| 9499 | CAN_CRITICAL_SECTION_ENTER(); |
| 9500 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND47; |
| 9501 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9502 | } |
| 9503 | |
| 9504 | static inline bool hri_can_get_NDAT2_ND47_bit(const void *const hw) |
| 9505 | { |
| 9506 | uint32_t tmp; |
| 9507 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9508 | tmp = (tmp & CAN_NDAT2_ND47) >> CAN_NDAT2_ND47_Pos; |
| 9509 | return (bool)tmp; |
| 9510 | } |
| 9511 | |
| 9512 | static inline void hri_can_write_NDAT2_ND47_bit(const void *const hw, bool value) |
| 9513 | { |
| 9514 | uint32_t tmp; |
| 9515 | CAN_CRITICAL_SECTION_ENTER(); |
| 9516 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9517 | tmp &= ~CAN_NDAT2_ND47; |
| 9518 | tmp |= value << CAN_NDAT2_ND47_Pos; |
| 9519 | ((Can *)hw)->NDAT2.reg = tmp; |
| 9520 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9521 | } |
| 9522 | |
| 9523 | static inline void hri_can_clear_NDAT2_ND47_bit(const void *const hw) |
| 9524 | { |
| 9525 | CAN_CRITICAL_SECTION_ENTER(); |
| 9526 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND47; |
| 9527 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9528 | } |
| 9529 | |
| 9530 | static inline void hri_can_toggle_NDAT2_ND47_bit(const void *const hw) |
| 9531 | { |
| 9532 | CAN_CRITICAL_SECTION_ENTER(); |
| 9533 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND47; |
| 9534 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9535 | } |
| 9536 | |
| 9537 | static inline void hri_can_set_NDAT2_ND48_bit(const void *const hw) |
| 9538 | { |
| 9539 | CAN_CRITICAL_SECTION_ENTER(); |
| 9540 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND48; |
| 9541 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9542 | } |
| 9543 | |
| 9544 | static inline bool hri_can_get_NDAT2_ND48_bit(const void *const hw) |
| 9545 | { |
| 9546 | uint32_t tmp; |
| 9547 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9548 | tmp = (tmp & CAN_NDAT2_ND48) >> CAN_NDAT2_ND48_Pos; |
| 9549 | return (bool)tmp; |
| 9550 | } |
| 9551 | |
| 9552 | static inline void hri_can_write_NDAT2_ND48_bit(const void *const hw, bool value) |
| 9553 | { |
| 9554 | uint32_t tmp; |
| 9555 | CAN_CRITICAL_SECTION_ENTER(); |
| 9556 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9557 | tmp &= ~CAN_NDAT2_ND48; |
| 9558 | tmp |= value << CAN_NDAT2_ND48_Pos; |
| 9559 | ((Can *)hw)->NDAT2.reg = tmp; |
| 9560 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9561 | } |
| 9562 | |
| 9563 | static inline void hri_can_clear_NDAT2_ND48_bit(const void *const hw) |
| 9564 | { |
| 9565 | CAN_CRITICAL_SECTION_ENTER(); |
| 9566 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND48; |
| 9567 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9568 | } |
| 9569 | |
| 9570 | static inline void hri_can_toggle_NDAT2_ND48_bit(const void *const hw) |
| 9571 | { |
| 9572 | CAN_CRITICAL_SECTION_ENTER(); |
| 9573 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND48; |
| 9574 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9575 | } |
| 9576 | |
| 9577 | static inline void hri_can_set_NDAT2_ND49_bit(const void *const hw) |
| 9578 | { |
| 9579 | CAN_CRITICAL_SECTION_ENTER(); |
| 9580 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND49; |
| 9581 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9582 | } |
| 9583 | |
| 9584 | static inline bool hri_can_get_NDAT2_ND49_bit(const void *const hw) |
| 9585 | { |
| 9586 | uint32_t tmp; |
| 9587 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9588 | tmp = (tmp & CAN_NDAT2_ND49) >> CAN_NDAT2_ND49_Pos; |
| 9589 | return (bool)tmp; |
| 9590 | } |
| 9591 | |
| 9592 | static inline void hri_can_write_NDAT2_ND49_bit(const void *const hw, bool value) |
| 9593 | { |
| 9594 | uint32_t tmp; |
| 9595 | CAN_CRITICAL_SECTION_ENTER(); |
| 9596 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9597 | tmp &= ~CAN_NDAT2_ND49; |
| 9598 | tmp |= value << CAN_NDAT2_ND49_Pos; |
| 9599 | ((Can *)hw)->NDAT2.reg = tmp; |
| 9600 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9601 | } |
| 9602 | |
| 9603 | static inline void hri_can_clear_NDAT2_ND49_bit(const void *const hw) |
| 9604 | { |
| 9605 | CAN_CRITICAL_SECTION_ENTER(); |
| 9606 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND49; |
| 9607 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9608 | } |
| 9609 | |
| 9610 | static inline void hri_can_toggle_NDAT2_ND49_bit(const void *const hw) |
| 9611 | { |
| 9612 | CAN_CRITICAL_SECTION_ENTER(); |
| 9613 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND49; |
| 9614 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9615 | } |
| 9616 | |
| 9617 | static inline void hri_can_set_NDAT2_ND50_bit(const void *const hw) |
| 9618 | { |
| 9619 | CAN_CRITICAL_SECTION_ENTER(); |
| 9620 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND50; |
| 9621 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9622 | } |
| 9623 | |
| 9624 | static inline bool hri_can_get_NDAT2_ND50_bit(const void *const hw) |
| 9625 | { |
| 9626 | uint32_t tmp; |
| 9627 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9628 | tmp = (tmp & CAN_NDAT2_ND50) >> CAN_NDAT2_ND50_Pos; |
| 9629 | return (bool)tmp; |
| 9630 | } |
| 9631 | |
| 9632 | static inline void hri_can_write_NDAT2_ND50_bit(const void *const hw, bool value) |
| 9633 | { |
| 9634 | uint32_t tmp; |
| 9635 | CAN_CRITICAL_SECTION_ENTER(); |
| 9636 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9637 | tmp &= ~CAN_NDAT2_ND50; |
| 9638 | tmp |= value << CAN_NDAT2_ND50_Pos; |
| 9639 | ((Can *)hw)->NDAT2.reg = tmp; |
| 9640 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9641 | } |
| 9642 | |
| 9643 | static inline void hri_can_clear_NDAT2_ND50_bit(const void *const hw) |
| 9644 | { |
| 9645 | CAN_CRITICAL_SECTION_ENTER(); |
| 9646 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND50; |
| 9647 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9648 | } |
| 9649 | |
| 9650 | static inline void hri_can_toggle_NDAT2_ND50_bit(const void *const hw) |
| 9651 | { |
| 9652 | CAN_CRITICAL_SECTION_ENTER(); |
| 9653 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND50; |
| 9654 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9655 | } |
| 9656 | |
| 9657 | static inline void hri_can_set_NDAT2_ND51_bit(const void *const hw) |
| 9658 | { |
| 9659 | CAN_CRITICAL_SECTION_ENTER(); |
| 9660 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND51; |
| 9661 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9662 | } |
| 9663 | |
| 9664 | static inline bool hri_can_get_NDAT2_ND51_bit(const void *const hw) |
| 9665 | { |
| 9666 | uint32_t tmp; |
| 9667 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9668 | tmp = (tmp & CAN_NDAT2_ND51) >> CAN_NDAT2_ND51_Pos; |
| 9669 | return (bool)tmp; |
| 9670 | } |
| 9671 | |
| 9672 | static inline void hri_can_write_NDAT2_ND51_bit(const void *const hw, bool value) |
| 9673 | { |
| 9674 | uint32_t tmp; |
| 9675 | CAN_CRITICAL_SECTION_ENTER(); |
| 9676 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9677 | tmp &= ~CAN_NDAT2_ND51; |
| 9678 | tmp |= value << CAN_NDAT2_ND51_Pos; |
| 9679 | ((Can *)hw)->NDAT2.reg = tmp; |
| 9680 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9681 | } |
| 9682 | |
| 9683 | static inline void hri_can_clear_NDAT2_ND51_bit(const void *const hw) |
| 9684 | { |
| 9685 | CAN_CRITICAL_SECTION_ENTER(); |
| 9686 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND51; |
| 9687 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9688 | } |
| 9689 | |
| 9690 | static inline void hri_can_toggle_NDAT2_ND51_bit(const void *const hw) |
| 9691 | { |
| 9692 | CAN_CRITICAL_SECTION_ENTER(); |
| 9693 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND51; |
| 9694 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9695 | } |
| 9696 | |
| 9697 | static inline void hri_can_set_NDAT2_ND52_bit(const void *const hw) |
| 9698 | { |
| 9699 | CAN_CRITICAL_SECTION_ENTER(); |
| 9700 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND52; |
| 9701 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9702 | } |
| 9703 | |
| 9704 | static inline bool hri_can_get_NDAT2_ND52_bit(const void *const hw) |
| 9705 | { |
| 9706 | uint32_t tmp; |
| 9707 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9708 | tmp = (tmp & CAN_NDAT2_ND52) >> CAN_NDAT2_ND52_Pos; |
| 9709 | return (bool)tmp; |
| 9710 | } |
| 9711 | |
| 9712 | static inline void hri_can_write_NDAT2_ND52_bit(const void *const hw, bool value) |
| 9713 | { |
| 9714 | uint32_t tmp; |
| 9715 | CAN_CRITICAL_SECTION_ENTER(); |
| 9716 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9717 | tmp &= ~CAN_NDAT2_ND52; |
| 9718 | tmp |= value << CAN_NDAT2_ND52_Pos; |
| 9719 | ((Can *)hw)->NDAT2.reg = tmp; |
| 9720 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9721 | } |
| 9722 | |
| 9723 | static inline void hri_can_clear_NDAT2_ND52_bit(const void *const hw) |
| 9724 | { |
| 9725 | CAN_CRITICAL_SECTION_ENTER(); |
| 9726 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND52; |
| 9727 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9728 | } |
| 9729 | |
| 9730 | static inline void hri_can_toggle_NDAT2_ND52_bit(const void *const hw) |
| 9731 | { |
| 9732 | CAN_CRITICAL_SECTION_ENTER(); |
| 9733 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND52; |
| 9734 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9735 | } |
| 9736 | |
| 9737 | static inline void hri_can_set_NDAT2_ND53_bit(const void *const hw) |
| 9738 | { |
| 9739 | CAN_CRITICAL_SECTION_ENTER(); |
| 9740 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND53; |
| 9741 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9742 | } |
| 9743 | |
| 9744 | static inline bool hri_can_get_NDAT2_ND53_bit(const void *const hw) |
| 9745 | { |
| 9746 | uint32_t tmp; |
| 9747 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9748 | tmp = (tmp & CAN_NDAT2_ND53) >> CAN_NDAT2_ND53_Pos; |
| 9749 | return (bool)tmp; |
| 9750 | } |
| 9751 | |
| 9752 | static inline void hri_can_write_NDAT2_ND53_bit(const void *const hw, bool value) |
| 9753 | { |
| 9754 | uint32_t tmp; |
| 9755 | CAN_CRITICAL_SECTION_ENTER(); |
| 9756 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9757 | tmp &= ~CAN_NDAT2_ND53; |
| 9758 | tmp |= value << CAN_NDAT2_ND53_Pos; |
| 9759 | ((Can *)hw)->NDAT2.reg = tmp; |
| 9760 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9761 | } |
| 9762 | |
| 9763 | static inline void hri_can_clear_NDAT2_ND53_bit(const void *const hw) |
| 9764 | { |
| 9765 | CAN_CRITICAL_SECTION_ENTER(); |
| 9766 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND53; |
| 9767 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9768 | } |
| 9769 | |
| 9770 | static inline void hri_can_toggle_NDAT2_ND53_bit(const void *const hw) |
| 9771 | { |
| 9772 | CAN_CRITICAL_SECTION_ENTER(); |
| 9773 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND53; |
| 9774 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9775 | } |
| 9776 | |
| 9777 | static inline void hri_can_set_NDAT2_ND54_bit(const void *const hw) |
| 9778 | { |
| 9779 | CAN_CRITICAL_SECTION_ENTER(); |
| 9780 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND54; |
| 9781 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9782 | } |
| 9783 | |
| 9784 | static inline bool hri_can_get_NDAT2_ND54_bit(const void *const hw) |
| 9785 | { |
| 9786 | uint32_t tmp; |
| 9787 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9788 | tmp = (tmp & CAN_NDAT2_ND54) >> CAN_NDAT2_ND54_Pos; |
| 9789 | return (bool)tmp; |
| 9790 | } |
| 9791 | |
| 9792 | static inline void hri_can_write_NDAT2_ND54_bit(const void *const hw, bool value) |
| 9793 | { |
| 9794 | uint32_t tmp; |
| 9795 | CAN_CRITICAL_SECTION_ENTER(); |
| 9796 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9797 | tmp &= ~CAN_NDAT2_ND54; |
| 9798 | tmp |= value << CAN_NDAT2_ND54_Pos; |
| 9799 | ((Can *)hw)->NDAT2.reg = tmp; |
| 9800 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9801 | } |
| 9802 | |
| 9803 | static inline void hri_can_clear_NDAT2_ND54_bit(const void *const hw) |
| 9804 | { |
| 9805 | CAN_CRITICAL_SECTION_ENTER(); |
| 9806 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND54; |
| 9807 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9808 | } |
| 9809 | |
| 9810 | static inline void hri_can_toggle_NDAT2_ND54_bit(const void *const hw) |
| 9811 | { |
| 9812 | CAN_CRITICAL_SECTION_ENTER(); |
| 9813 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND54; |
| 9814 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9815 | } |
| 9816 | |
| 9817 | static inline void hri_can_set_NDAT2_ND55_bit(const void *const hw) |
| 9818 | { |
| 9819 | CAN_CRITICAL_SECTION_ENTER(); |
| 9820 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND55; |
| 9821 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9822 | } |
| 9823 | |
| 9824 | static inline bool hri_can_get_NDAT2_ND55_bit(const void *const hw) |
| 9825 | { |
| 9826 | uint32_t tmp; |
| 9827 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9828 | tmp = (tmp & CAN_NDAT2_ND55) >> CAN_NDAT2_ND55_Pos; |
| 9829 | return (bool)tmp; |
| 9830 | } |
| 9831 | |
| 9832 | static inline void hri_can_write_NDAT2_ND55_bit(const void *const hw, bool value) |
| 9833 | { |
| 9834 | uint32_t tmp; |
| 9835 | CAN_CRITICAL_SECTION_ENTER(); |
| 9836 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9837 | tmp &= ~CAN_NDAT2_ND55; |
| 9838 | tmp |= value << CAN_NDAT2_ND55_Pos; |
| 9839 | ((Can *)hw)->NDAT2.reg = tmp; |
| 9840 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9841 | } |
| 9842 | |
| 9843 | static inline void hri_can_clear_NDAT2_ND55_bit(const void *const hw) |
| 9844 | { |
| 9845 | CAN_CRITICAL_SECTION_ENTER(); |
| 9846 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND55; |
| 9847 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9848 | } |
| 9849 | |
| 9850 | static inline void hri_can_toggle_NDAT2_ND55_bit(const void *const hw) |
| 9851 | { |
| 9852 | CAN_CRITICAL_SECTION_ENTER(); |
| 9853 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND55; |
| 9854 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9855 | } |
| 9856 | |
| 9857 | static inline void hri_can_set_NDAT2_ND56_bit(const void *const hw) |
| 9858 | { |
| 9859 | CAN_CRITICAL_SECTION_ENTER(); |
| 9860 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND56; |
| 9861 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9862 | } |
| 9863 | |
| 9864 | static inline bool hri_can_get_NDAT2_ND56_bit(const void *const hw) |
| 9865 | { |
| 9866 | uint32_t tmp; |
| 9867 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9868 | tmp = (tmp & CAN_NDAT2_ND56) >> CAN_NDAT2_ND56_Pos; |
| 9869 | return (bool)tmp; |
| 9870 | } |
| 9871 | |
| 9872 | static inline void hri_can_write_NDAT2_ND56_bit(const void *const hw, bool value) |
| 9873 | { |
| 9874 | uint32_t tmp; |
| 9875 | CAN_CRITICAL_SECTION_ENTER(); |
| 9876 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9877 | tmp &= ~CAN_NDAT2_ND56; |
| 9878 | tmp |= value << CAN_NDAT2_ND56_Pos; |
| 9879 | ((Can *)hw)->NDAT2.reg = tmp; |
| 9880 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9881 | } |
| 9882 | |
| 9883 | static inline void hri_can_clear_NDAT2_ND56_bit(const void *const hw) |
| 9884 | { |
| 9885 | CAN_CRITICAL_SECTION_ENTER(); |
| 9886 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND56; |
| 9887 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9888 | } |
| 9889 | |
| 9890 | static inline void hri_can_toggle_NDAT2_ND56_bit(const void *const hw) |
| 9891 | { |
| 9892 | CAN_CRITICAL_SECTION_ENTER(); |
| 9893 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND56; |
| 9894 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9895 | } |
| 9896 | |
| 9897 | static inline void hri_can_set_NDAT2_ND57_bit(const void *const hw) |
| 9898 | { |
| 9899 | CAN_CRITICAL_SECTION_ENTER(); |
| 9900 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND57; |
| 9901 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9902 | } |
| 9903 | |
| 9904 | static inline bool hri_can_get_NDAT2_ND57_bit(const void *const hw) |
| 9905 | { |
| 9906 | uint32_t tmp; |
| 9907 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9908 | tmp = (tmp & CAN_NDAT2_ND57) >> CAN_NDAT2_ND57_Pos; |
| 9909 | return (bool)tmp; |
| 9910 | } |
| 9911 | |
| 9912 | static inline void hri_can_write_NDAT2_ND57_bit(const void *const hw, bool value) |
| 9913 | { |
| 9914 | uint32_t tmp; |
| 9915 | CAN_CRITICAL_SECTION_ENTER(); |
| 9916 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9917 | tmp &= ~CAN_NDAT2_ND57; |
| 9918 | tmp |= value << CAN_NDAT2_ND57_Pos; |
| 9919 | ((Can *)hw)->NDAT2.reg = tmp; |
| 9920 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9921 | } |
| 9922 | |
| 9923 | static inline void hri_can_clear_NDAT2_ND57_bit(const void *const hw) |
| 9924 | { |
| 9925 | CAN_CRITICAL_SECTION_ENTER(); |
| 9926 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND57; |
| 9927 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9928 | } |
| 9929 | |
| 9930 | static inline void hri_can_toggle_NDAT2_ND57_bit(const void *const hw) |
| 9931 | { |
| 9932 | CAN_CRITICAL_SECTION_ENTER(); |
| 9933 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND57; |
| 9934 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9935 | } |
| 9936 | |
| 9937 | static inline void hri_can_set_NDAT2_ND58_bit(const void *const hw) |
| 9938 | { |
| 9939 | CAN_CRITICAL_SECTION_ENTER(); |
| 9940 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND58; |
| 9941 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9942 | } |
| 9943 | |
| 9944 | static inline bool hri_can_get_NDAT2_ND58_bit(const void *const hw) |
| 9945 | { |
| 9946 | uint32_t tmp; |
| 9947 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9948 | tmp = (tmp & CAN_NDAT2_ND58) >> CAN_NDAT2_ND58_Pos; |
| 9949 | return (bool)tmp; |
| 9950 | } |
| 9951 | |
| 9952 | static inline void hri_can_write_NDAT2_ND58_bit(const void *const hw, bool value) |
| 9953 | { |
| 9954 | uint32_t tmp; |
| 9955 | CAN_CRITICAL_SECTION_ENTER(); |
| 9956 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9957 | tmp &= ~CAN_NDAT2_ND58; |
| 9958 | tmp |= value << CAN_NDAT2_ND58_Pos; |
| 9959 | ((Can *)hw)->NDAT2.reg = tmp; |
| 9960 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9961 | } |
| 9962 | |
| 9963 | static inline void hri_can_clear_NDAT2_ND58_bit(const void *const hw) |
| 9964 | { |
| 9965 | CAN_CRITICAL_SECTION_ENTER(); |
| 9966 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND58; |
| 9967 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9968 | } |
| 9969 | |
| 9970 | static inline void hri_can_toggle_NDAT2_ND58_bit(const void *const hw) |
| 9971 | { |
| 9972 | CAN_CRITICAL_SECTION_ENTER(); |
| 9973 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND58; |
| 9974 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9975 | } |
| 9976 | |
| 9977 | static inline void hri_can_set_NDAT2_ND59_bit(const void *const hw) |
| 9978 | { |
| 9979 | CAN_CRITICAL_SECTION_ENTER(); |
| 9980 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND59; |
| 9981 | CAN_CRITICAL_SECTION_LEAVE(); |
| 9982 | } |
| 9983 | |
| 9984 | static inline bool hri_can_get_NDAT2_ND59_bit(const void *const hw) |
| 9985 | { |
| 9986 | uint32_t tmp; |
| 9987 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9988 | tmp = (tmp & CAN_NDAT2_ND59) >> CAN_NDAT2_ND59_Pos; |
| 9989 | return (bool)tmp; |
| 9990 | } |
| 9991 | |
| 9992 | static inline void hri_can_write_NDAT2_ND59_bit(const void *const hw, bool value) |
| 9993 | { |
| 9994 | uint32_t tmp; |
| 9995 | CAN_CRITICAL_SECTION_ENTER(); |
| 9996 | tmp = ((Can *)hw)->NDAT2.reg; |
| 9997 | tmp &= ~CAN_NDAT2_ND59; |
| 9998 | tmp |= value << CAN_NDAT2_ND59_Pos; |
| 9999 | ((Can *)hw)->NDAT2.reg = tmp; |
| 10000 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10001 | } |
| 10002 | |
| 10003 | static inline void hri_can_clear_NDAT2_ND59_bit(const void *const hw) |
| 10004 | { |
| 10005 | CAN_CRITICAL_SECTION_ENTER(); |
| 10006 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND59; |
| 10007 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10008 | } |
| 10009 | |
| 10010 | static inline void hri_can_toggle_NDAT2_ND59_bit(const void *const hw) |
| 10011 | { |
| 10012 | CAN_CRITICAL_SECTION_ENTER(); |
| 10013 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND59; |
| 10014 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10015 | } |
| 10016 | |
| 10017 | static inline void hri_can_set_NDAT2_ND60_bit(const void *const hw) |
| 10018 | { |
| 10019 | CAN_CRITICAL_SECTION_ENTER(); |
| 10020 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND60; |
| 10021 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10022 | } |
| 10023 | |
| 10024 | static inline bool hri_can_get_NDAT2_ND60_bit(const void *const hw) |
| 10025 | { |
| 10026 | uint32_t tmp; |
| 10027 | tmp = ((Can *)hw)->NDAT2.reg; |
| 10028 | tmp = (tmp & CAN_NDAT2_ND60) >> CAN_NDAT2_ND60_Pos; |
| 10029 | return (bool)tmp; |
| 10030 | } |
| 10031 | |
| 10032 | static inline void hri_can_write_NDAT2_ND60_bit(const void *const hw, bool value) |
| 10033 | { |
| 10034 | uint32_t tmp; |
| 10035 | CAN_CRITICAL_SECTION_ENTER(); |
| 10036 | tmp = ((Can *)hw)->NDAT2.reg; |
| 10037 | tmp &= ~CAN_NDAT2_ND60; |
| 10038 | tmp |= value << CAN_NDAT2_ND60_Pos; |
| 10039 | ((Can *)hw)->NDAT2.reg = tmp; |
| 10040 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10041 | } |
| 10042 | |
| 10043 | static inline void hri_can_clear_NDAT2_ND60_bit(const void *const hw) |
| 10044 | { |
| 10045 | CAN_CRITICAL_SECTION_ENTER(); |
| 10046 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND60; |
| 10047 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10048 | } |
| 10049 | |
| 10050 | static inline void hri_can_toggle_NDAT2_ND60_bit(const void *const hw) |
| 10051 | { |
| 10052 | CAN_CRITICAL_SECTION_ENTER(); |
| 10053 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND60; |
| 10054 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10055 | } |
| 10056 | |
| 10057 | static inline void hri_can_set_NDAT2_ND61_bit(const void *const hw) |
| 10058 | { |
| 10059 | CAN_CRITICAL_SECTION_ENTER(); |
| 10060 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND61; |
| 10061 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10062 | } |
| 10063 | |
| 10064 | static inline bool hri_can_get_NDAT2_ND61_bit(const void *const hw) |
| 10065 | { |
| 10066 | uint32_t tmp; |
| 10067 | tmp = ((Can *)hw)->NDAT2.reg; |
| 10068 | tmp = (tmp & CAN_NDAT2_ND61) >> CAN_NDAT2_ND61_Pos; |
| 10069 | return (bool)tmp; |
| 10070 | } |
| 10071 | |
| 10072 | static inline void hri_can_write_NDAT2_ND61_bit(const void *const hw, bool value) |
| 10073 | { |
| 10074 | uint32_t tmp; |
| 10075 | CAN_CRITICAL_SECTION_ENTER(); |
| 10076 | tmp = ((Can *)hw)->NDAT2.reg; |
| 10077 | tmp &= ~CAN_NDAT2_ND61; |
| 10078 | tmp |= value << CAN_NDAT2_ND61_Pos; |
| 10079 | ((Can *)hw)->NDAT2.reg = tmp; |
| 10080 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10081 | } |
| 10082 | |
| 10083 | static inline void hri_can_clear_NDAT2_ND61_bit(const void *const hw) |
| 10084 | { |
| 10085 | CAN_CRITICAL_SECTION_ENTER(); |
| 10086 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND61; |
| 10087 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10088 | } |
| 10089 | |
| 10090 | static inline void hri_can_toggle_NDAT2_ND61_bit(const void *const hw) |
| 10091 | { |
| 10092 | CAN_CRITICAL_SECTION_ENTER(); |
| 10093 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND61; |
| 10094 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10095 | } |
| 10096 | |
| 10097 | static inline void hri_can_set_NDAT2_ND62_bit(const void *const hw) |
| 10098 | { |
| 10099 | CAN_CRITICAL_SECTION_ENTER(); |
| 10100 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND62; |
| 10101 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10102 | } |
| 10103 | |
| 10104 | static inline bool hri_can_get_NDAT2_ND62_bit(const void *const hw) |
| 10105 | { |
| 10106 | uint32_t tmp; |
| 10107 | tmp = ((Can *)hw)->NDAT2.reg; |
| 10108 | tmp = (tmp & CAN_NDAT2_ND62) >> CAN_NDAT2_ND62_Pos; |
| 10109 | return (bool)tmp; |
| 10110 | } |
| 10111 | |
| 10112 | static inline void hri_can_write_NDAT2_ND62_bit(const void *const hw, bool value) |
| 10113 | { |
| 10114 | uint32_t tmp; |
| 10115 | CAN_CRITICAL_SECTION_ENTER(); |
| 10116 | tmp = ((Can *)hw)->NDAT2.reg; |
| 10117 | tmp &= ~CAN_NDAT2_ND62; |
| 10118 | tmp |= value << CAN_NDAT2_ND62_Pos; |
| 10119 | ((Can *)hw)->NDAT2.reg = tmp; |
| 10120 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10121 | } |
| 10122 | |
| 10123 | static inline void hri_can_clear_NDAT2_ND62_bit(const void *const hw) |
| 10124 | { |
| 10125 | CAN_CRITICAL_SECTION_ENTER(); |
| 10126 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND62; |
| 10127 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10128 | } |
| 10129 | |
| 10130 | static inline void hri_can_toggle_NDAT2_ND62_bit(const void *const hw) |
| 10131 | { |
| 10132 | CAN_CRITICAL_SECTION_ENTER(); |
| 10133 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND62; |
| 10134 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10135 | } |
| 10136 | |
| 10137 | static inline void hri_can_set_NDAT2_ND63_bit(const void *const hw) |
| 10138 | { |
| 10139 | CAN_CRITICAL_SECTION_ENTER(); |
| 10140 | ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND63; |
| 10141 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10142 | } |
| 10143 | |
| 10144 | static inline bool hri_can_get_NDAT2_ND63_bit(const void *const hw) |
| 10145 | { |
| 10146 | uint32_t tmp; |
| 10147 | tmp = ((Can *)hw)->NDAT2.reg; |
| 10148 | tmp = (tmp & CAN_NDAT2_ND63) >> CAN_NDAT2_ND63_Pos; |
| 10149 | return (bool)tmp; |
| 10150 | } |
| 10151 | |
| 10152 | static inline void hri_can_write_NDAT2_ND63_bit(const void *const hw, bool value) |
| 10153 | { |
| 10154 | uint32_t tmp; |
| 10155 | CAN_CRITICAL_SECTION_ENTER(); |
| 10156 | tmp = ((Can *)hw)->NDAT2.reg; |
| 10157 | tmp &= ~CAN_NDAT2_ND63; |
| 10158 | tmp |= value << CAN_NDAT2_ND63_Pos; |
| 10159 | ((Can *)hw)->NDAT2.reg = tmp; |
| 10160 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10161 | } |
| 10162 | |
| 10163 | static inline void hri_can_clear_NDAT2_ND63_bit(const void *const hw) |
| 10164 | { |
| 10165 | CAN_CRITICAL_SECTION_ENTER(); |
| 10166 | ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND63; |
| 10167 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10168 | } |
| 10169 | |
| 10170 | static inline void hri_can_toggle_NDAT2_ND63_bit(const void *const hw) |
| 10171 | { |
| 10172 | CAN_CRITICAL_SECTION_ENTER(); |
| 10173 | ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND63; |
| 10174 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10175 | } |
| 10176 | |
| 10177 | static inline void hri_can_set_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) |
| 10178 | { |
| 10179 | CAN_CRITICAL_SECTION_ENTER(); |
| 10180 | ((Can *)hw)->NDAT2.reg |= mask; |
| 10181 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10182 | } |
| 10183 | |
| 10184 | static inline hri_can_ndat2_reg_t hri_can_get_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) |
| 10185 | { |
| 10186 | uint32_t tmp; |
| 10187 | tmp = ((Can *)hw)->NDAT2.reg; |
| 10188 | tmp &= mask; |
| 10189 | return tmp; |
| 10190 | } |
| 10191 | |
| 10192 | static inline void hri_can_write_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t data) |
| 10193 | { |
| 10194 | CAN_CRITICAL_SECTION_ENTER(); |
| 10195 | ((Can *)hw)->NDAT2.reg = data; |
| 10196 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10197 | } |
| 10198 | |
| 10199 | static inline void hri_can_clear_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) |
| 10200 | { |
| 10201 | CAN_CRITICAL_SECTION_ENTER(); |
| 10202 | ((Can *)hw)->NDAT2.reg &= ~mask; |
| 10203 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10204 | } |
| 10205 | |
| 10206 | static inline void hri_can_toggle_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) |
| 10207 | { |
| 10208 | CAN_CRITICAL_SECTION_ENTER(); |
| 10209 | ((Can *)hw)->NDAT2.reg ^= mask; |
| 10210 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10211 | } |
| 10212 | |
| 10213 | static inline hri_can_ndat2_reg_t hri_can_read_NDAT2_reg(const void *const hw) |
| 10214 | { |
| 10215 | return ((Can *)hw)->NDAT2.reg; |
| 10216 | } |
| 10217 | |
| 10218 | static inline void hri_can_set_RXF0C_F0OM_bit(const void *const hw) |
| 10219 | { |
| 10220 | CAN_CRITICAL_SECTION_ENTER(); |
| 10221 | ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0OM; |
| 10222 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10223 | } |
| 10224 | |
| 10225 | static inline bool hri_can_get_RXF0C_F0OM_bit(const void *const hw) |
| 10226 | { |
| 10227 | uint32_t tmp; |
| 10228 | tmp = ((Can *)hw)->RXF0C.reg; |
| 10229 | tmp = (tmp & CAN_RXF0C_F0OM) >> CAN_RXF0C_F0OM_Pos; |
| 10230 | return (bool)tmp; |
| 10231 | } |
| 10232 | |
| 10233 | static inline void hri_can_write_RXF0C_F0OM_bit(const void *const hw, bool value) |
| 10234 | { |
| 10235 | uint32_t tmp; |
| 10236 | CAN_CRITICAL_SECTION_ENTER(); |
| 10237 | tmp = ((Can *)hw)->RXF0C.reg; |
| 10238 | tmp &= ~CAN_RXF0C_F0OM; |
| 10239 | tmp |= value << CAN_RXF0C_F0OM_Pos; |
| 10240 | ((Can *)hw)->RXF0C.reg = tmp; |
| 10241 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10242 | } |
| 10243 | |
| 10244 | static inline void hri_can_clear_RXF0C_F0OM_bit(const void *const hw) |
| 10245 | { |
| 10246 | CAN_CRITICAL_SECTION_ENTER(); |
| 10247 | ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0OM; |
| 10248 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10249 | } |
| 10250 | |
| 10251 | static inline void hri_can_toggle_RXF0C_F0OM_bit(const void *const hw) |
| 10252 | { |
| 10253 | CAN_CRITICAL_SECTION_ENTER(); |
| 10254 | ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0OM; |
| 10255 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10256 | } |
| 10257 | |
| 10258 | static inline void hri_can_set_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) |
| 10259 | { |
| 10260 | CAN_CRITICAL_SECTION_ENTER(); |
| 10261 | ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0SA(mask); |
| 10262 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10263 | } |
| 10264 | |
| 10265 | static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) |
| 10266 | { |
| 10267 | uint32_t tmp; |
| 10268 | tmp = ((Can *)hw)->RXF0C.reg; |
| 10269 | tmp = (tmp & CAN_RXF0C_F0SA(mask)) >> CAN_RXF0C_F0SA_Pos; |
| 10270 | return tmp; |
| 10271 | } |
| 10272 | |
| 10273 | static inline void hri_can_write_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t data) |
| 10274 | { |
| 10275 | uint32_t tmp; |
| 10276 | CAN_CRITICAL_SECTION_ENTER(); |
| 10277 | tmp = ((Can *)hw)->RXF0C.reg; |
| 10278 | tmp &= ~CAN_RXF0C_F0SA_Msk; |
| 10279 | tmp |= CAN_RXF0C_F0SA(data); |
| 10280 | ((Can *)hw)->RXF0C.reg = tmp; |
| 10281 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10282 | } |
| 10283 | |
| 10284 | static inline void hri_can_clear_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) |
| 10285 | { |
| 10286 | CAN_CRITICAL_SECTION_ENTER(); |
| 10287 | ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0SA(mask); |
| 10288 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10289 | } |
| 10290 | |
| 10291 | static inline void hri_can_toggle_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) |
| 10292 | { |
| 10293 | CAN_CRITICAL_SECTION_ENTER(); |
| 10294 | ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0SA(mask); |
| 10295 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10296 | } |
| 10297 | |
| 10298 | static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0SA_bf(const void *const hw) |
| 10299 | { |
| 10300 | uint32_t tmp; |
| 10301 | tmp = ((Can *)hw)->RXF0C.reg; |
| 10302 | tmp = (tmp & CAN_RXF0C_F0SA_Msk) >> CAN_RXF0C_F0SA_Pos; |
| 10303 | return tmp; |
| 10304 | } |
| 10305 | |
| 10306 | static inline void hri_can_set_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) |
| 10307 | { |
| 10308 | CAN_CRITICAL_SECTION_ENTER(); |
| 10309 | ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0S(mask); |
| 10310 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10311 | } |
| 10312 | |
| 10313 | static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) |
| 10314 | { |
| 10315 | uint32_t tmp; |
| 10316 | tmp = ((Can *)hw)->RXF0C.reg; |
| 10317 | tmp = (tmp & CAN_RXF0C_F0S(mask)) >> CAN_RXF0C_F0S_Pos; |
| 10318 | return tmp; |
| 10319 | } |
| 10320 | |
| 10321 | static inline void hri_can_write_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t data) |
| 10322 | { |
| 10323 | uint32_t tmp; |
| 10324 | CAN_CRITICAL_SECTION_ENTER(); |
| 10325 | tmp = ((Can *)hw)->RXF0C.reg; |
| 10326 | tmp &= ~CAN_RXF0C_F0S_Msk; |
| 10327 | tmp |= CAN_RXF0C_F0S(data); |
| 10328 | ((Can *)hw)->RXF0C.reg = tmp; |
| 10329 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10330 | } |
| 10331 | |
| 10332 | static inline void hri_can_clear_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) |
| 10333 | { |
| 10334 | CAN_CRITICAL_SECTION_ENTER(); |
| 10335 | ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0S(mask); |
| 10336 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10337 | } |
| 10338 | |
| 10339 | static inline void hri_can_toggle_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) |
| 10340 | { |
| 10341 | CAN_CRITICAL_SECTION_ENTER(); |
| 10342 | ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0S(mask); |
| 10343 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10344 | } |
| 10345 | |
| 10346 | static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0S_bf(const void *const hw) |
| 10347 | { |
| 10348 | uint32_t tmp; |
| 10349 | tmp = ((Can *)hw)->RXF0C.reg; |
| 10350 | tmp = (tmp & CAN_RXF0C_F0S_Msk) >> CAN_RXF0C_F0S_Pos; |
| 10351 | return tmp; |
| 10352 | } |
| 10353 | |
| 10354 | static inline void hri_can_set_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) |
| 10355 | { |
| 10356 | CAN_CRITICAL_SECTION_ENTER(); |
| 10357 | ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0WM(mask); |
| 10358 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10359 | } |
| 10360 | |
| 10361 | static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) |
| 10362 | { |
| 10363 | uint32_t tmp; |
| 10364 | tmp = ((Can *)hw)->RXF0C.reg; |
| 10365 | tmp = (tmp & CAN_RXF0C_F0WM(mask)) >> CAN_RXF0C_F0WM_Pos; |
| 10366 | return tmp; |
| 10367 | } |
| 10368 | |
| 10369 | static inline void hri_can_write_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t data) |
| 10370 | { |
| 10371 | uint32_t tmp; |
| 10372 | CAN_CRITICAL_SECTION_ENTER(); |
| 10373 | tmp = ((Can *)hw)->RXF0C.reg; |
| 10374 | tmp &= ~CAN_RXF0C_F0WM_Msk; |
| 10375 | tmp |= CAN_RXF0C_F0WM(data); |
| 10376 | ((Can *)hw)->RXF0C.reg = tmp; |
| 10377 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10378 | } |
| 10379 | |
| 10380 | static inline void hri_can_clear_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) |
| 10381 | { |
| 10382 | CAN_CRITICAL_SECTION_ENTER(); |
| 10383 | ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0WM(mask); |
| 10384 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10385 | } |
| 10386 | |
| 10387 | static inline void hri_can_toggle_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) |
| 10388 | { |
| 10389 | CAN_CRITICAL_SECTION_ENTER(); |
| 10390 | ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0WM(mask); |
| 10391 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10392 | } |
| 10393 | |
| 10394 | static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0WM_bf(const void *const hw) |
| 10395 | { |
| 10396 | uint32_t tmp; |
| 10397 | tmp = ((Can *)hw)->RXF0C.reg; |
| 10398 | tmp = (tmp & CAN_RXF0C_F0WM_Msk) >> CAN_RXF0C_F0WM_Pos; |
| 10399 | return tmp; |
| 10400 | } |
| 10401 | |
| 10402 | static inline void hri_can_set_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) |
| 10403 | { |
| 10404 | CAN_CRITICAL_SECTION_ENTER(); |
| 10405 | ((Can *)hw)->RXF0C.reg |= mask; |
| 10406 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10407 | } |
| 10408 | |
| 10409 | static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) |
| 10410 | { |
| 10411 | uint32_t tmp; |
| 10412 | tmp = ((Can *)hw)->RXF0C.reg; |
| 10413 | tmp &= mask; |
| 10414 | return tmp; |
| 10415 | } |
| 10416 | |
| 10417 | static inline void hri_can_write_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t data) |
| 10418 | { |
| 10419 | CAN_CRITICAL_SECTION_ENTER(); |
| 10420 | ((Can *)hw)->RXF0C.reg = data; |
| 10421 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10422 | } |
| 10423 | |
| 10424 | static inline void hri_can_clear_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) |
| 10425 | { |
| 10426 | CAN_CRITICAL_SECTION_ENTER(); |
| 10427 | ((Can *)hw)->RXF0C.reg &= ~mask; |
| 10428 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10429 | } |
| 10430 | |
| 10431 | static inline void hri_can_toggle_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) |
| 10432 | { |
| 10433 | CAN_CRITICAL_SECTION_ENTER(); |
| 10434 | ((Can *)hw)->RXF0C.reg ^= mask; |
| 10435 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10436 | } |
| 10437 | |
| 10438 | static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_reg(const void *const hw) |
| 10439 | { |
| 10440 | return ((Can *)hw)->RXF0C.reg; |
| 10441 | } |
| 10442 | |
| 10443 | static inline void hri_can_set_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) |
| 10444 | { |
| 10445 | CAN_CRITICAL_SECTION_ENTER(); |
| 10446 | ((Can *)hw)->RXF0A.reg |= CAN_RXF0A_F0AI(mask); |
| 10447 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10448 | } |
| 10449 | |
| 10450 | static inline hri_can_rxf0a_reg_t hri_can_get_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) |
| 10451 | { |
| 10452 | uint32_t tmp; |
| 10453 | tmp = ((Can *)hw)->RXF0A.reg; |
| 10454 | tmp = (tmp & CAN_RXF0A_F0AI(mask)) >> CAN_RXF0A_F0AI_Pos; |
| 10455 | return tmp; |
| 10456 | } |
| 10457 | |
| 10458 | static inline void hri_can_write_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t data) |
| 10459 | { |
| 10460 | uint32_t tmp; |
| 10461 | CAN_CRITICAL_SECTION_ENTER(); |
| 10462 | tmp = ((Can *)hw)->RXF0A.reg; |
| 10463 | tmp &= ~CAN_RXF0A_F0AI_Msk; |
| 10464 | tmp |= CAN_RXF0A_F0AI(data); |
| 10465 | ((Can *)hw)->RXF0A.reg = tmp; |
| 10466 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10467 | } |
| 10468 | |
| 10469 | static inline void hri_can_clear_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) |
| 10470 | { |
| 10471 | CAN_CRITICAL_SECTION_ENTER(); |
| 10472 | ((Can *)hw)->RXF0A.reg &= ~CAN_RXF0A_F0AI(mask); |
| 10473 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10474 | } |
| 10475 | |
| 10476 | static inline void hri_can_toggle_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) |
| 10477 | { |
| 10478 | CAN_CRITICAL_SECTION_ENTER(); |
| 10479 | ((Can *)hw)->RXF0A.reg ^= CAN_RXF0A_F0AI(mask); |
| 10480 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10481 | } |
| 10482 | |
| 10483 | static inline hri_can_rxf0a_reg_t hri_can_read_RXF0A_F0AI_bf(const void *const hw) |
| 10484 | { |
| 10485 | uint32_t tmp; |
| 10486 | tmp = ((Can *)hw)->RXF0A.reg; |
| 10487 | tmp = (tmp & CAN_RXF0A_F0AI_Msk) >> CAN_RXF0A_F0AI_Pos; |
| 10488 | return tmp; |
| 10489 | } |
| 10490 | |
| 10491 | static inline void hri_can_set_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) |
| 10492 | { |
| 10493 | CAN_CRITICAL_SECTION_ENTER(); |
| 10494 | ((Can *)hw)->RXF0A.reg |= mask; |
| 10495 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10496 | } |
| 10497 | |
| 10498 | static inline hri_can_rxf0a_reg_t hri_can_get_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) |
| 10499 | { |
| 10500 | uint32_t tmp; |
| 10501 | tmp = ((Can *)hw)->RXF0A.reg; |
| 10502 | tmp &= mask; |
| 10503 | return tmp; |
| 10504 | } |
| 10505 | |
| 10506 | static inline void hri_can_write_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t data) |
| 10507 | { |
| 10508 | CAN_CRITICAL_SECTION_ENTER(); |
| 10509 | ((Can *)hw)->RXF0A.reg = data; |
| 10510 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10511 | } |
| 10512 | |
| 10513 | static inline void hri_can_clear_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) |
| 10514 | { |
| 10515 | CAN_CRITICAL_SECTION_ENTER(); |
| 10516 | ((Can *)hw)->RXF0A.reg &= ~mask; |
| 10517 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10518 | } |
| 10519 | |
| 10520 | static inline void hri_can_toggle_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) |
| 10521 | { |
| 10522 | CAN_CRITICAL_SECTION_ENTER(); |
| 10523 | ((Can *)hw)->RXF0A.reg ^= mask; |
| 10524 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10525 | } |
| 10526 | |
| 10527 | static inline hri_can_rxf0a_reg_t hri_can_read_RXF0A_reg(const void *const hw) |
| 10528 | { |
| 10529 | return ((Can *)hw)->RXF0A.reg; |
| 10530 | } |
| 10531 | |
| 10532 | static inline void hri_can_set_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) |
| 10533 | { |
| 10534 | CAN_CRITICAL_SECTION_ENTER(); |
| 10535 | ((Can *)hw)->RXBC.reg |= CAN_RXBC_RBSA(mask); |
| 10536 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10537 | } |
| 10538 | |
| 10539 | static inline hri_can_rxbc_reg_t hri_can_get_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) |
| 10540 | { |
| 10541 | uint32_t tmp; |
| 10542 | tmp = ((Can *)hw)->RXBC.reg; |
| 10543 | tmp = (tmp & CAN_RXBC_RBSA(mask)) >> CAN_RXBC_RBSA_Pos; |
| 10544 | return tmp; |
| 10545 | } |
| 10546 | |
| 10547 | static inline void hri_can_write_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t data) |
| 10548 | { |
| 10549 | uint32_t tmp; |
| 10550 | CAN_CRITICAL_SECTION_ENTER(); |
| 10551 | tmp = ((Can *)hw)->RXBC.reg; |
| 10552 | tmp &= ~CAN_RXBC_RBSA_Msk; |
| 10553 | tmp |= CAN_RXBC_RBSA(data); |
| 10554 | ((Can *)hw)->RXBC.reg = tmp; |
| 10555 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10556 | } |
| 10557 | |
| 10558 | static inline void hri_can_clear_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) |
| 10559 | { |
| 10560 | CAN_CRITICAL_SECTION_ENTER(); |
| 10561 | ((Can *)hw)->RXBC.reg &= ~CAN_RXBC_RBSA(mask); |
| 10562 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10563 | } |
| 10564 | |
| 10565 | static inline void hri_can_toggle_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) |
| 10566 | { |
| 10567 | CAN_CRITICAL_SECTION_ENTER(); |
| 10568 | ((Can *)hw)->RXBC.reg ^= CAN_RXBC_RBSA(mask); |
| 10569 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10570 | } |
| 10571 | |
| 10572 | static inline hri_can_rxbc_reg_t hri_can_read_RXBC_RBSA_bf(const void *const hw) |
| 10573 | { |
| 10574 | uint32_t tmp; |
| 10575 | tmp = ((Can *)hw)->RXBC.reg; |
| 10576 | tmp = (tmp & CAN_RXBC_RBSA_Msk) >> CAN_RXBC_RBSA_Pos; |
| 10577 | return tmp; |
| 10578 | } |
| 10579 | |
| 10580 | static inline void hri_can_set_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) |
| 10581 | { |
| 10582 | CAN_CRITICAL_SECTION_ENTER(); |
| 10583 | ((Can *)hw)->RXBC.reg |= mask; |
| 10584 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10585 | } |
| 10586 | |
| 10587 | static inline hri_can_rxbc_reg_t hri_can_get_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) |
| 10588 | { |
| 10589 | uint32_t tmp; |
| 10590 | tmp = ((Can *)hw)->RXBC.reg; |
| 10591 | tmp &= mask; |
| 10592 | return tmp; |
| 10593 | } |
| 10594 | |
| 10595 | static inline void hri_can_write_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t data) |
| 10596 | { |
| 10597 | CAN_CRITICAL_SECTION_ENTER(); |
| 10598 | ((Can *)hw)->RXBC.reg = data; |
| 10599 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10600 | } |
| 10601 | |
| 10602 | static inline void hri_can_clear_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) |
| 10603 | { |
| 10604 | CAN_CRITICAL_SECTION_ENTER(); |
| 10605 | ((Can *)hw)->RXBC.reg &= ~mask; |
| 10606 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10607 | } |
| 10608 | |
| 10609 | static inline void hri_can_toggle_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) |
| 10610 | { |
| 10611 | CAN_CRITICAL_SECTION_ENTER(); |
| 10612 | ((Can *)hw)->RXBC.reg ^= mask; |
| 10613 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10614 | } |
| 10615 | |
| 10616 | static inline hri_can_rxbc_reg_t hri_can_read_RXBC_reg(const void *const hw) |
| 10617 | { |
| 10618 | return ((Can *)hw)->RXBC.reg; |
| 10619 | } |
| 10620 | |
| 10621 | static inline void hri_can_set_RXF1C_F1OM_bit(const void *const hw) |
| 10622 | { |
| 10623 | CAN_CRITICAL_SECTION_ENTER(); |
| 10624 | ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1OM; |
| 10625 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10626 | } |
| 10627 | |
| 10628 | static inline bool hri_can_get_RXF1C_F1OM_bit(const void *const hw) |
| 10629 | { |
| 10630 | uint32_t tmp; |
| 10631 | tmp = ((Can *)hw)->RXF1C.reg; |
| 10632 | tmp = (tmp & CAN_RXF1C_F1OM) >> CAN_RXF1C_F1OM_Pos; |
| 10633 | return (bool)tmp; |
| 10634 | } |
| 10635 | |
| 10636 | static inline void hri_can_write_RXF1C_F1OM_bit(const void *const hw, bool value) |
| 10637 | { |
| 10638 | uint32_t tmp; |
| 10639 | CAN_CRITICAL_SECTION_ENTER(); |
| 10640 | tmp = ((Can *)hw)->RXF1C.reg; |
| 10641 | tmp &= ~CAN_RXF1C_F1OM; |
| 10642 | tmp |= value << CAN_RXF1C_F1OM_Pos; |
| 10643 | ((Can *)hw)->RXF1C.reg = tmp; |
| 10644 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10645 | } |
| 10646 | |
| 10647 | static inline void hri_can_clear_RXF1C_F1OM_bit(const void *const hw) |
| 10648 | { |
| 10649 | CAN_CRITICAL_SECTION_ENTER(); |
| 10650 | ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1OM; |
| 10651 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10652 | } |
| 10653 | |
| 10654 | static inline void hri_can_toggle_RXF1C_F1OM_bit(const void *const hw) |
| 10655 | { |
| 10656 | CAN_CRITICAL_SECTION_ENTER(); |
| 10657 | ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1OM; |
| 10658 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10659 | } |
| 10660 | |
| 10661 | static inline void hri_can_set_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) |
| 10662 | { |
| 10663 | CAN_CRITICAL_SECTION_ENTER(); |
| 10664 | ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1SA(mask); |
| 10665 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10666 | } |
| 10667 | |
| 10668 | static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) |
| 10669 | { |
| 10670 | uint32_t tmp; |
| 10671 | tmp = ((Can *)hw)->RXF1C.reg; |
| 10672 | tmp = (tmp & CAN_RXF1C_F1SA(mask)) >> CAN_RXF1C_F1SA_Pos; |
| 10673 | return tmp; |
| 10674 | } |
| 10675 | |
| 10676 | static inline void hri_can_write_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t data) |
| 10677 | { |
| 10678 | uint32_t tmp; |
| 10679 | CAN_CRITICAL_SECTION_ENTER(); |
| 10680 | tmp = ((Can *)hw)->RXF1C.reg; |
| 10681 | tmp &= ~CAN_RXF1C_F1SA_Msk; |
| 10682 | tmp |= CAN_RXF1C_F1SA(data); |
| 10683 | ((Can *)hw)->RXF1C.reg = tmp; |
| 10684 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10685 | } |
| 10686 | |
| 10687 | static inline void hri_can_clear_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) |
| 10688 | { |
| 10689 | CAN_CRITICAL_SECTION_ENTER(); |
| 10690 | ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1SA(mask); |
| 10691 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10692 | } |
| 10693 | |
| 10694 | static inline void hri_can_toggle_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) |
| 10695 | { |
| 10696 | CAN_CRITICAL_SECTION_ENTER(); |
| 10697 | ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1SA(mask); |
| 10698 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10699 | } |
| 10700 | |
| 10701 | static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1SA_bf(const void *const hw) |
| 10702 | { |
| 10703 | uint32_t tmp; |
| 10704 | tmp = ((Can *)hw)->RXF1C.reg; |
| 10705 | tmp = (tmp & CAN_RXF1C_F1SA_Msk) >> CAN_RXF1C_F1SA_Pos; |
| 10706 | return tmp; |
| 10707 | } |
| 10708 | |
| 10709 | static inline void hri_can_set_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) |
| 10710 | { |
| 10711 | CAN_CRITICAL_SECTION_ENTER(); |
| 10712 | ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1S(mask); |
| 10713 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10714 | } |
| 10715 | |
| 10716 | static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) |
| 10717 | { |
| 10718 | uint32_t tmp; |
| 10719 | tmp = ((Can *)hw)->RXF1C.reg; |
| 10720 | tmp = (tmp & CAN_RXF1C_F1S(mask)) >> CAN_RXF1C_F1S_Pos; |
| 10721 | return tmp; |
| 10722 | } |
| 10723 | |
| 10724 | static inline void hri_can_write_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t data) |
| 10725 | { |
| 10726 | uint32_t tmp; |
| 10727 | CAN_CRITICAL_SECTION_ENTER(); |
| 10728 | tmp = ((Can *)hw)->RXF1C.reg; |
| 10729 | tmp &= ~CAN_RXF1C_F1S_Msk; |
| 10730 | tmp |= CAN_RXF1C_F1S(data); |
| 10731 | ((Can *)hw)->RXF1C.reg = tmp; |
| 10732 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10733 | } |
| 10734 | |
| 10735 | static inline void hri_can_clear_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) |
| 10736 | { |
| 10737 | CAN_CRITICAL_SECTION_ENTER(); |
| 10738 | ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1S(mask); |
| 10739 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10740 | } |
| 10741 | |
| 10742 | static inline void hri_can_toggle_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) |
| 10743 | { |
| 10744 | CAN_CRITICAL_SECTION_ENTER(); |
| 10745 | ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1S(mask); |
| 10746 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10747 | } |
| 10748 | |
| 10749 | static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1S_bf(const void *const hw) |
| 10750 | { |
| 10751 | uint32_t tmp; |
| 10752 | tmp = ((Can *)hw)->RXF1C.reg; |
| 10753 | tmp = (tmp & CAN_RXF1C_F1S_Msk) >> CAN_RXF1C_F1S_Pos; |
| 10754 | return tmp; |
| 10755 | } |
| 10756 | |
| 10757 | static inline void hri_can_set_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) |
| 10758 | { |
| 10759 | CAN_CRITICAL_SECTION_ENTER(); |
| 10760 | ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1WM(mask); |
| 10761 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10762 | } |
| 10763 | |
| 10764 | static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) |
| 10765 | { |
| 10766 | uint32_t tmp; |
| 10767 | tmp = ((Can *)hw)->RXF1C.reg; |
| 10768 | tmp = (tmp & CAN_RXF1C_F1WM(mask)) >> CAN_RXF1C_F1WM_Pos; |
| 10769 | return tmp; |
| 10770 | } |
| 10771 | |
| 10772 | static inline void hri_can_write_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t data) |
| 10773 | { |
| 10774 | uint32_t tmp; |
| 10775 | CAN_CRITICAL_SECTION_ENTER(); |
| 10776 | tmp = ((Can *)hw)->RXF1C.reg; |
| 10777 | tmp &= ~CAN_RXF1C_F1WM_Msk; |
| 10778 | tmp |= CAN_RXF1C_F1WM(data); |
| 10779 | ((Can *)hw)->RXF1C.reg = tmp; |
| 10780 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10781 | } |
| 10782 | |
| 10783 | static inline void hri_can_clear_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) |
| 10784 | { |
| 10785 | CAN_CRITICAL_SECTION_ENTER(); |
| 10786 | ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1WM(mask); |
| 10787 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10788 | } |
| 10789 | |
| 10790 | static inline void hri_can_toggle_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) |
| 10791 | { |
| 10792 | CAN_CRITICAL_SECTION_ENTER(); |
| 10793 | ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1WM(mask); |
| 10794 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10795 | } |
| 10796 | |
| 10797 | static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1WM_bf(const void *const hw) |
| 10798 | { |
| 10799 | uint32_t tmp; |
| 10800 | tmp = ((Can *)hw)->RXF1C.reg; |
| 10801 | tmp = (tmp & CAN_RXF1C_F1WM_Msk) >> CAN_RXF1C_F1WM_Pos; |
| 10802 | return tmp; |
| 10803 | } |
| 10804 | |
| 10805 | static inline void hri_can_set_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) |
| 10806 | { |
| 10807 | CAN_CRITICAL_SECTION_ENTER(); |
| 10808 | ((Can *)hw)->RXF1C.reg |= mask; |
| 10809 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10810 | } |
| 10811 | |
| 10812 | static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) |
| 10813 | { |
| 10814 | uint32_t tmp; |
| 10815 | tmp = ((Can *)hw)->RXF1C.reg; |
| 10816 | tmp &= mask; |
| 10817 | return tmp; |
| 10818 | } |
| 10819 | |
| 10820 | static inline void hri_can_write_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t data) |
| 10821 | { |
| 10822 | CAN_CRITICAL_SECTION_ENTER(); |
| 10823 | ((Can *)hw)->RXF1C.reg = data; |
| 10824 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10825 | } |
| 10826 | |
| 10827 | static inline void hri_can_clear_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) |
| 10828 | { |
| 10829 | CAN_CRITICAL_SECTION_ENTER(); |
| 10830 | ((Can *)hw)->RXF1C.reg &= ~mask; |
| 10831 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10832 | } |
| 10833 | |
| 10834 | static inline void hri_can_toggle_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) |
| 10835 | { |
| 10836 | CAN_CRITICAL_SECTION_ENTER(); |
| 10837 | ((Can *)hw)->RXF1C.reg ^= mask; |
| 10838 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10839 | } |
| 10840 | |
| 10841 | static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_reg(const void *const hw) |
| 10842 | { |
| 10843 | return ((Can *)hw)->RXF1C.reg; |
| 10844 | } |
| 10845 | |
| 10846 | static inline void hri_can_set_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) |
| 10847 | { |
| 10848 | CAN_CRITICAL_SECTION_ENTER(); |
| 10849 | ((Can *)hw)->RXF1A.reg |= CAN_RXF1A_F1AI(mask); |
| 10850 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10851 | } |
| 10852 | |
| 10853 | static inline hri_can_rxf1a_reg_t hri_can_get_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) |
| 10854 | { |
| 10855 | uint32_t tmp; |
| 10856 | tmp = ((Can *)hw)->RXF1A.reg; |
| 10857 | tmp = (tmp & CAN_RXF1A_F1AI(mask)) >> CAN_RXF1A_F1AI_Pos; |
| 10858 | return tmp; |
| 10859 | } |
| 10860 | |
| 10861 | static inline void hri_can_write_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t data) |
| 10862 | { |
| 10863 | uint32_t tmp; |
| 10864 | CAN_CRITICAL_SECTION_ENTER(); |
| 10865 | tmp = ((Can *)hw)->RXF1A.reg; |
| 10866 | tmp &= ~CAN_RXF1A_F1AI_Msk; |
| 10867 | tmp |= CAN_RXF1A_F1AI(data); |
| 10868 | ((Can *)hw)->RXF1A.reg = tmp; |
| 10869 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10870 | } |
| 10871 | |
| 10872 | static inline void hri_can_clear_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) |
| 10873 | { |
| 10874 | CAN_CRITICAL_SECTION_ENTER(); |
| 10875 | ((Can *)hw)->RXF1A.reg &= ~CAN_RXF1A_F1AI(mask); |
| 10876 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10877 | } |
| 10878 | |
| 10879 | static inline void hri_can_toggle_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) |
| 10880 | { |
| 10881 | CAN_CRITICAL_SECTION_ENTER(); |
| 10882 | ((Can *)hw)->RXF1A.reg ^= CAN_RXF1A_F1AI(mask); |
| 10883 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10884 | } |
| 10885 | |
| 10886 | static inline hri_can_rxf1a_reg_t hri_can_read_RXF1A_F1AI_bf(const void *const hw) |
| 10887 | { |
| 10888 | uint32_t tmp; |
| 10889 | tmp = ((Can *)hw)->RXF1A.reg; |
| 10890 | tmp = (tmp & CAN_RXF1A_F1AI_Msk) >> CAN_RXF1A_F1AI_Pos; |
| 10891 | return tmp; |
| 10892 | } |
| 10893 | |
| 10894 | static inline void hri_can_set_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) |
| 10895 | { |
| 10896 | CAN_CRITICAL_SECTION_ENTER(); |
| 10897 | ((Can *)hw)->RXF1A.reg |= mask; |
| 10898 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10899 | } |
| 10900 | |
| 10901 | static inline hri_can_rxf1a_reg_t hri_can_get_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) |
| 10902 | { |
| 10903 | uint32_t tmp; |
| 10904 | tmp = ((Can *)hw)->RXF1A.reg; |
| 10905 | tmp &= mask; |
| 10906 | return tmp; |
| 10907 | } |
| 10908 | |
| 10909 | static inline void hri_can_write_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t data) |
| 10910 | { |
| 10911 | CAN_CRITICAL_SECTION_ENTER(); |
| 10912 | ((Can *)hw)->RXF1A.reg = data; |
| 10913 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10914 | } |
| 10915 | |
| 10916 | static inline void hri_can_clear_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) |
| 10917 | { |
| 10918 | CAN_CRITICAL_SECTION_ENTER(); |
| 10919 | ((Can *)hw)->RXF1A.reg &= ~mask; |
| 10920 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10921 | } |
| 10922 | |
| 10923 | static inline void hri_can_toggle_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) |
| 10924 | { |
| 10925 | CAN_CRITICAL_SECTION_ENTER(); |
| 10926 | ((Can *)hw)->RXF1A.reg ^= mask; |
| 10927 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10928 | } |
| 10929 | |
| 10930 | static inline hri_can_rxf1a_reg_t hri_can_read_RXF1A_reg(const void *const hw) |
| 10931 | { |
| 10932 | return ((Can *)hw)->RXF1A.reg; |
| 10933 | } |
| 10934 | |
| 10935 | static inline void hri_can_set_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) |
| 10936 | { |
| 10937 | CAN_CRITICAL_SECTION_ENTER(); |
| 10938 | ((Can *)hw)->RXESC.reg |= CAN_RXESC_F0DS(mask); |
| 10939 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10940 | } |
| 10941 | |
| 10942 | static inline hri_can_rxesc_reg_t hri_can_get_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) |
| 10943 | { |
| 10944 | uint32_t tmp; |
| 10945 | tmp = ((Can *)hw)->RXESC.reg; |
| 10946 | tmp = (tmp & CAN_RXESC_F0DS(mask)) >> CAN_RXESC_F0DS_Pos; |
| 10947 | return tmp; |
| 10948 | } |
| 10949 | |
| 10950 | static inline void hri_can_write_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t data) |
| 10951 | { |
| 10952 | uint32_t tmp; |
| 10953 | CAN_CRITICAL_SECTION_ENTER(); |
| 10954 | tmp = ((Can *)hw)->RXESC.reg; |
| 10955 | tmp &= ~CAN_RXESC_F0DS_Msk; |
| 10956 | tmp |= CAN_RXESC_F0DS(data); |
| 10957 | ((Can *)hw)->RXESC.reg = tmp; |
| 10958 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10959 | } |
| 10960 | |
| 10961 | static inline void hri_can_clear_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) |
| 10962 | { |
| 10963 | CAN_CRITICAL_SECTION_ENTER(); |
| 10964 | ((Can *)hw)->RXESC.reg &= ~CAN_RXESC_F0DS(mask); |
| 10965 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10966 | } |
| 10967 | |
| 10968 | static inline void hri_can_toggle_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) |
| 10969 | { |
| 10970 | CAN_CRITICAL_SECTION_ENTER(); |
| 10971 | ((Can *)hw)->RXESC.reg ^= CAN_RXESC_F0DS(mask); |
| 10972 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10973 | } |
| 10974 | |
| 10975 | static inline hri_can_rxesc_reg_t hri_can_read_RXESC_F0DS_bf(const void *const hw) |
| 10976 | { |
| 10977 | uint32_t tmp; |
| 10978 | tmp = ((Can *)hw)->RXESC.reg; |
| 10979 | tmp = (tmp & CAN_RXESC_F0DS_Msk) >> CAN_RXESC_F0DS_Pos; |
| 10980 | return tmp; |
| 10981 | } |
| 10982 | |
| 10983 | static inline void hri_can_set_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) |
| 10984 | { |
| 10985 | CAN_CRITICAL_SECTION_ENTER(); |
| 10986 | ((Can *)hw)->RXESC.reg |= CAN_RXESC_F1DS(mask); |
| 10987 | CAN_CRITICAL_SECTION_LEAVE(); |
| 10988 | } |
| 10989 | |
| 10990 | static inline hri_can_rxesc_reg_t hri_can_get_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) |
| 10991 | { |
| 10992 | uint32_t tmp; |
| 10993 | tmp = ((Can *)hw)->RXESC.reg; |
| 10994 | tmp = (tmp & CAN_RXESC_F1DS(mask)) >> CAN_RXESC_F1DS_Pos; |
| 10995 | return tmp; |
| 10996 | } |
| 10997 | |
| 10998 | static inline void hri_can_write_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t data) |
| 10999 | { |
| 11000 | uint32_t tmp; |
| 11001 | CAN_CRITICAL_SECTION_ENTER(); |
| 11002 | tmp = ((Can *)hw)->RXESC.reg; |
| 11003 | tmp &= ~CAN_RXESC_F1DS_Msk; |
| 11004 | tmp |= CAN_RXESC_F1DS(data); |
| 11005 | ((Can *)hw)->RXESC.reg = tmp; |
| 11006 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11007 | } |
| 11008 | |
| 11009 | static inline void hri_can_clear_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) |
| 11010 | { |
| 11011 | CAN_CRITICAL_SECTION_ENTER(); |
| 11012 | ((Can *)hw)->RXESC.reg &= ~CAN_RXESC_F1DS(mask); |
| 11013 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11014 | } |
| 11015 | |
| 11016 | static inline void hri_can_toggle_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) |
| 11017 | { |
| 11018 | CAN_CRITICAL_SECTION_ENTER(); |
| 11019 | ((Can *)hw)->RXESC.reg ^= CAN_RXESC_F1DS(mask); |
| 11020 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11021 | } |
| 11022 | |
| 11023 | static inline hri_can_rxesc_reg_t hri_can_read_RXESC_F1DS_bf(const void *const hw) |
| 11024 | { |
| 11025 | uint32_t tmp; |
| 11026 | tmp = ((Can *)hw)->RXESC.reg; |
| 11027 | tmp = (tmp & CAN_RXESC_F1DS_Msk) >> CAN_RXESC_F1DS_Pos; |
| 11028 | return tmp; |
| 11029 | } |
| 11030 | |
| 11031 | static inline void hri_can_set_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) |
| 11032 | { |
| 11033 | CAN_CRITICAL_SECTION_ENTER(); |
| 11034 | ((Can *)hw)->RXESC.reg |= CAN_RXESC_RBDS(mask); |
| 11035 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11036 | } |
| 11037 | |
| 11038 | static inline hri_can_rxesc_reg_t hri_can_get_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) |
| 11039 | { |
| 11040 | uint32_t tmp; |
| 11041 | tmp = ((Can *)hw)->RXESC.reg; |
| 11042 | tmp = (tmp & CAN_RXESC_RBDS(mask)) >> CAN_RXESC_RBDS_Pos; |
| 11043 | return tmp; |
| 11044 | } |
| 11045 | |
| 11046 | static inline void hri_can_write_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t data) |
| 11047 | { |
| 11048 | uint32_t tmp; |
| 11049 | CAN_CRITICAL_SECTION_ENTER(); |
| 11050 | tmp = ((Can *)hw)->RXESC.reg; |
| 11051 | tmp &= ~CAN_RXESC_RBDS_Msk; |
| 11052 | tmp |= CAN_RXESC_RBDS(data); |
| 11053 | ((Can *)hw)->RXESC.reg = tmp; |
| 11054 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11055 | } |
| 11056 | |
| 11057 | static inline void hri_can_clear_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) |
| 11058 | { |
| 11059 | CAN_CRITICAL_SECTION_ENTER(); |
| 11060 | ((Can *)hw)->RXESC.reg &= ~CAN_RXESC_RBDS(mask); |
| 11061 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11062 | } |
| 11063 | |
| 11064 | static inline void hri_can_toggle_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) |
| 11065 | { |
| 11066 | CAN_CRITICAL_SECTION_ENTER(); |
| 11067 | ((Can *)hw)->RXESC.reg ^= CAN_RXESC_RBDS(mask); |
| 11068 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11069 | } |
| 11070 | |
| 11071 | static inline hri_can_rxesc_reg_t hri_can_read_RXESC_RBDS_bf(const void *const hw) |
| 11072 | { |
| 11073 | uint32_t tmp; |
| 11074 | tmp = ((Can *)hw)->RXESC.reg; |
| 11075 | tmp = (tmp & CAN_RXESC_RBDS_Msk) >> CAN_RXESC_RBDS_Pos; |
| 11076 | return tmp; |
| 11077 | } |
| 11078 | |
| 11079 | static inline void hri_can_set_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) |
| 11080 | { |
| 11081 | CAN_CRITICAL_SECTION_ENTER(); |
| 11082 | ((Can *)hw)->RXESC.reg |= mask; |
| 11083 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11084 | } |
| 11085 | |
| 11086 | static inline hri_can_rxesc_reg_t hri_can_get_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) |
| 11087 | { |
| 11088 | uint32_t tmp; |
| 11089 | tmp = ((Can *)hw)->RXESC.reg; |
| 11090 | tmp &= mask; |
| 11091 | return tmp; |
| 11092 | } |
| 11093 | |
| 11094 | static inline void hri_can_write_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t data) |
| 11095 | { |
| 11096 | CAN_CRITICAL_SECTION_ENTER(); |
| 11097 | ((Can *)hw)->RXESC.reg = data; |
| 11098 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11099 | } |
| 11100 | |
| 11101 | static inline void hri_can_clear_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) |
| 11102 | { |
| 11103 | CAN_CRITICAL_SECTION_ENTER(); |
| 11104 | ((Can *)hw)->RXESC.reg &= ~mask; |
| 11105 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11106 | } |
| 11107 | |
| 11108 | static inline void hri_can_toggle_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) |
| 11109 | { |
| 11110 | CAN_CRITICAL_SECTION_ENTER(); |
| 11111 | ((Can *)hw)->RXESC.reg ^= mask; |
| 11112 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11113 | } |
| 11114 | |
| 11115 | static inline hri_can_rxesc_reg_t hri_can_read_RXESC_reg(const void *const hw) |
| 11116 | { |
| 11117 | return ((Can *)hw)->RXESC.reg; |
| 11118 | } |
| 11119 | |
| 11120 | static inline void hri_can_set_TXBC_TFQM_bit(const void *const hw) |
| 11121 | { |
| 11122 | CAN_CRITICAL_SECTION_ENTER(); |
| 11123 | ((Can *)hw)->TXBC.reg |= CAN_TXBC_TFQM; |
| 11124 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11125 | } |
| 11126 | |
| 11127 | static inline bool hri_can_get_TXBC_TFQM_bit(const void *const hw) |
| 11128 | { |
| 11129 | uint32_t tmp; |
| 11130 | tmp = ((Can *)hw)->TXBC.reg; |
| 11131 | tmp = (tmp & CAN_TXBC_TFQM) >> CAN_TXBC_TFQM_Pos; |
| 11132 | return (bool)tmp; |
| 11133 | } |
| 11134 | |
| 11135 | static inline void hri_can_write_TXBC_TFQM_bit(const void *const hw, bool value) |
| 11136 | { |
| 11137 | uint32_t tmp; |
| 11138 | CAN_CRITICAL_SECTION_ENTER(); |
| 11139 | tmp = ((Can *)hw)->TXBC.reg; |
| 11140 | tmp &= ~CAN_TXBC_TFQM; |
| 11141 | tmp |= value << CAN_TXBC_TFQM_Pos; |
| 11142 | ((Can *)hw)->TXBC.reg = tmp; |
| 11143 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11144 | } |
| 11145 | |
| 11146 | static inline void hri_can_clear_TXBC_TFQM_bit(const void *const hw) |
| 11147 | { |
| 11148 | CAN_CRITICAL_SECTION_ENTER(); |
| 11149 | ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TFQM; |
| 11150 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11151 | } |
| 11152 | |
| 11153 | static inline void hri_can_toggle_TXBC_TFQM_bit(const void *const hw) |
| 11154 | { |
| 11155 | CAN_CRITICAL_SECTION_ENTER(); |
| 11156 | ((Can *)hw)->TXBC.reg ^= CAN_TXBC_TFQM; |
| 11157 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11158 | } |
| 11159 | |
| 11160 | static inline void hri_can_set_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) |
| 11161 | { |
| 11162 | CAN_CRITICAL_SECTION_ENTER(); |
| 11163 | ((Can *)hw)->TXBC.reg |= CAN_TXBC_TBSA(mask); |
| 11164 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11165 | } |
| 11166 | |
| 11167 | static inline hri_can_txbc_reg_t hri_can_get_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) |
| 11168 | { |
| 11169 | uint32_t tmp; |
| 11170 | tmp = ((Can *)hw)->TXBC.reg; |
| 11171 | tmp = (tmp & CAN_TXBC_TBSA(mask)) >> CAN_TXBC_TBSA_Pos; |
| 11172 | return tmp; |
| 11173 | } |
| 11174 | |
| 11175 | static inline void hri_can_write_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t data) |
| 11176 | { |
| 11177 | uint32_t tmp; |
| 11178 | CAN_CRITICAL_SECTION_ENTER(); |
| 11179 | tmp = ((Can *)hw)->TXBC.reg; |
| 11180 | tmp &= ~CAN_TXBC_TBSA_Msk; |
| 11181 | tmp |= CAN_TXBC_TBSA(data); |
| 11182 | ((Can *)hw)->TXBC.reg = tmp; |
| 11183 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11184 | } |
| 11185 | |
| 11186 | static inline void hri_can_clear_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) |
| 11187 | { |
| 11188 | CAN_CRITICAL_SECTION_ENTER(); |
| 11189 | ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TBSA(mask); |
| 11190 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11191 | } |
| 11192 | |
| 11193 | static inline void hri_can_toggle_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) |
| 11194 | { |
| 11195 | CAN_CRITICAL_SECTION_ENTER(); |
| 11196 | ((Can *)hw)->TXBC.reg ^= CAN_TXBC_TBSA(mask); |
| 11197 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11198 | } |
| 11199 | |
| 11200 | static inline hri_can_txbc_reg_t hri_can_read_TXBC_TBSA_bf(const void *const hw) |
| 11201 | { |
| 11202 | uint32_t tmp; |
| 11203 | tmp = ((Can *)hw)->TXBC.reg; |
| 11204 | tmp = (tmp & CAN_TXBC_TBSA_Msk) >> CAN_TXBC_TBSA_Pos; |
| 11205 | return tmp; |
| 11206 | } |
| 11207 | |
| 11208 | static inline void hri_can_set_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) |
| 11209 | { |
| 11210 | CAN_CRITICAL_SECTION_ENTER(); |
| 11211 | ((Can *)hw)->TXBC.reg |= CAN_TXBC_NDTB(mask); |
| 11212 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11213 | } |
| 11214 | |
| 11215 | static inline hri_can_txbc_reg_t hri_can_get_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) |
| 11216 | { |
| 11217 | uint32_t tmp; |
| 11218 | tmp = ((Can *)hw)->TXBC.reg; |
| 11219 | tmp = (tmp & CAN_TXBC_NDTB(mask)) >> CAN_TXBC_NDTB_Pos; |
| 11220 | return tmp; |
| 11221 | } |
| 11222 | |
| 11223 | static inline void hri_can_write_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t data) |
| 11224 | { |
| 11225 | uint32_t tmp; |
| 11226 | CAN_CRITICAL_SECTION_ENTER(); |
| 11227 | tmp = ((Can *)hw)->TXBC.reg; |
| 11228 | tmp &= ~CAN_TXBC_NDTB_Msk; |
| 11229 | tmp |= CAN_TXBC_NDTB(data); |
| 11230 | ((Can *)hw)->TXBC.reg = tmp; |
| 11231 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11232 | } |
| 11233 | |
| 11234 | static inline void hri_can_clear_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) |
| 11235 | { |
| 11236 | CAN_CRITICAL_SECTION_ENTER(); |
| 11237 | ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_NDTB(mask); |
| 11238 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11239 | } |
| 11240 | |
| 11241 | static inline void hri_can_toggle_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) |
| 11242 | { |
| 11243 | CAN_CRITICAL_SECTION_ENTER(); |
| 11244 | ((Can *)hw)->TXBC.reg ^= CAN_TXBC_NDTB(mask); |
| 11245 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11246 | } |
| 11247 | |
| 11248 | static inline hri_can_txbc_reg_t hri_can_read_TXBC_NDTB_bf(const void *const hw) |
| 11249 | { |
| 11250 | uint32_t tmp; |
| 11251 | tmp = ((Can *)hw)->TXBC.reg; |
| 11252 | tmp = (tmp & CAN_TXBC_NDTB_Msk) >> CAN_TXBC_NDTB_Pos; |
| 11253 | return tmp; |
| 11254 | } |
| 11255 | |
| 11256 | static inline void hri_can_set_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) |
| 11257 | { |
| 11258 | CAN_CRITICAL_SECTION_ENTER(); |
| 11259 | ((Can *)hw)->TXBC.reg |= CAN_TXBC_TFQS(mask); |
| 11260 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11261 | } |
| 11262 | |
| 11263 | static inline hri_can_txbc_reg_t hri_can_get_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) |
| 11264 | { |
| 11265 | uint32_t tmp; |
| 11266 | tmp = ((Can *)hw)->TXBC.reg; |
| 11267 | tmp = (tmp & CAN_TXBC_TFQS(mask)) >> CAN_TXBC_TFQS_Pos; |
| 11268 | return tmp; |
| 11269 | } |
| 11270 | |
| 11271 | static inline void hri_can_write_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t data) |
| 11272 | { |
| 11273 | uint32_t tmp; |
| 11274 | CAN_CRITICAL_SECTION_ENTER(); |
| 11275 | tmp = ((Can *)hw)->TXBC.reg; |
| 11276 | tmp &= ~CAN_TXBC_TFQS_Msk; |
| 11277 | tmp |= CAN_TXBC_TFQS(data); |
| 11278 | ((Can *)hw)->TXBC.reg = tmp; |
| 11279 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11280 | } |
| 11281 | |
| 11282 | static inline void hri_can_clear_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) |
| 11283 | { |
| 11284 | CAN_CRITICAL_SECTION_ENTER(); |
| 11285 | ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TFQS(mask); |
| 11286 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11287 | } |
| 11288 | |
| 11289 | static inline void hri_can_toggle_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) |
| 11290 | { |
| 11291 | CAN_CRITICAL_SECTION_ENTER(); |
| 11292 | ((Can *)hw)->TXBC.reg ^= CAN_TXBC_TFQS(mask); |
| 11293 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11294 | } |
| 11295 | |
| 11296 | static inline hri_can_txbc_reg_t hri_can_read_TXBC_TFQS_bf(const void *const hw) |
| 11297 | { |
| 11298 | uint32_t tmp; |
| 11299 | tmp = ((Can *)hw)->TXBC.reg; |
| 11300 | tmp = (tmp & CAN_TXBC_TFQS_Msk) >> CAN_TXBC_TFQS_Pos; |
| 11301 | return tmp; |
| 11302 | } |
| 11303 | |
| 11304 | static inline void hri_can_set_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) |
| 11305 | { |
| 11306 | CAN_CRITICAL_SECTION_ENTER(); |
| 11307 | ((Can *)hw)->TXBC.reg |= mask; |
| 11308 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11309 | } |
| 11310 | |
| 11311 | static inline hri_can_txbc_reg_t hri_can_get_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) |
| 11312 | { |
| 11313 | uint32_t tmp; |
| 11314 | tmp = ((Can *)hw)->TXBC.reg; |
| 11315 | tmp &= mask; |
| 11316 | return tmp; |
| 11317 | } |
| 11318 | |
| 11319 | static inline void hri_can_write_TXBC_reg(const void *const hw, hri_can_txbc_reg_t data) |
| 11320 | { |
| 11321 | CAN_CRITICAL_SECTION_ENTER(); |
| 11322 | ((Can *)hw)->TXBC.reg = data; |
| 11323 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11324 | } |
| 11325 | |
| 11326 | static inline void hri_can_clear_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) |
| 11327 | { |
| 11328 | CAN_CRITICAL_SECTION_ENTER(); |
| 11329 | ((Can *)hw)->TXBC.reg &= ~mask; |
| 11330 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11331 | } |
| 11332 | |
| 11333 | static inline void hri_can_toggle_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) |
| 11334 | { |
| 11335 | CAN_CRITICAL_SECTION_ENTER(); |
| 11336 | ((Can *)hw)->TXBC.reg ^= mask; |
| 11337 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11338 | } |
| 11339 | |
| 11340 | static inline hri_can_txbc_reg_t hri_can_read_TXBC_reg(const void *const hw) |
| 11341 | { |
| 11342 | return ((Can *)hw)->TXBC.reg; |
| 11343 | } |
| 11344 | |
| 11345 | static inline void hri_can_set_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) |
| 11346 | { |
| 11347 | CAN_CRITICAL_SECTION_ENTER(); |
| 11348 | ((Can *)hw)->TXESC.reg |= CAN_TXESC_TBDS(mask); |
| 11349 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11350 | } |
| 11351 | |
| 11352 | static inline hri_can_txesc_reg_t hri_can_get_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) |
| 11353 | { |
| 11354 | uint32_t tmp; |
| 11355 | tmp = ((Can *)hw)->TXESC.reg; |
| 11356 | tmp = (tmp & CAN_TXESC_TBDS(mask)) >> CAN_TXESC_TBDS_Pos; |
| 11357 | return tmp; |
| 11358 | } |
| 11359 | |
| 11360 | static inline void hri_can_write_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t data) |
| 11361 | { |
| 11362 | uint32_t tmp; |
| 11363 | CAN_CRITICAL_SECTION_ENTER(); |
| 11364 | tmp = ((Can *)hw)->TXESC.reg; |
| 11365 | tmp &= ~CAN_TXESC_TBDS_Msk; |
| 11366 | tmp |= CAN_TXESC_TBDS(data); |
| 11367 | ((Can *)hw)->TXESC.reg = tmp; |
| 11368 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11369 | } |
| 11370 | |
| 11371 | static inline void hri_can_clear_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) |
| 11372 | { |
| 11373 | CAN_CRITICAL_SECTION_ENTER(); |
| 11374 | ((Can *)hw)->TXESC.reg &= ~CAN_TXESC_TBDS(mask); |
| 11375 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11376 | } |
| 11377 | |
| 11378 | static inline void hri_can_toggle_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) |
| 11379 | { |
| 11380 | CAN_CRITICAL_SECTION_ENTER(); |
| 11381 | ((Can *)hw)->TXESC.reg ^= CAN_TXESC_TBDS(mask); |
| 11382 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11383 | } |
| 11384 | |
| 11385 | static inline hri_can_txesc_reg_t hri_can_read_TXESC_TBDS_bf(const void *const hw) |
| 11386 | { |
| 11387 | uint32_t tmp; |
| 11388 | tmp = ((Can *)hw)->TXESC.reg; |
| 11389 | tmp = (tmp & CAN_TXESC_TBDS_Msk) >> CAN_TXESC_TBDS_Pos; |
| 11390 | return tmp; |
| 11391 | } |
| 11392 | |
| 11393 | static inline void hri_can_set_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) |
| 11394 | { |
| 11395 | CAN_CRITICAL_SECTION_ENTER(); |
| 11396 | ((Can *)hw)->TXESC.reg |= mask; |
| 11397 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11398 | } |
| 11399 | |
| 11400 | static inline hri_can_txesc_reg_t hri_can_get_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) |
| 11401 | { |
| 11402 | uint32_t tmp; |
| 11403 | tmp = ((Can *)hw)->TXESC.reg; |
| 11404 | tmp &= mask; |
| 11405 | return tmp; |
| 11406 | } |
| 11407 | |
| 11408 | static inline void hri_can_write_TXESC_reg(const void *const hw, hri_can_txesc_reg_t data) |
| 11409 | { |
| 11410 | CAN_CRITICAL_SECTION_ENTER(); |
| 11411 | ((Can *)hw)->TXESC.reg = data; |
| 11412 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11413 | } |
| 11414 | |
| 11415 | static inline void hri_can_clear_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) |
| 11416 | { |
| 11417 | CAN_CRITICAL_SECTION_ENTER(); |
| 11418 | ((Can *)hw)->TXESC.reg &= ~mask; |
| 11419 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11420 | } |
| 11421 | |
| 11422 | static inline void hri_can_toggle_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) |
| 11423 | { |
| 11424 | CAN_CRITICAL_SECTION_ENTER(); |
| 11425 | ((Can *)hw)->TXESC.reg ^= mask; |
| 11426 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11427 | } |
| 11428 | |
| 11429 | static inline hri_can_txesc_reg_t hri_can_read_TXESC_reg(const void *const hw) |
| 11430 | { |
| 11431 | return ((Can *)hw)->TXESC.reg; |
| 11432 | } |
| 11433 | |
| 11434 | static inline void hri_can_set_TXBAR_AR0_bit(const void *const hw) |
| 11435 | { |
| 11436 | CAN_CRITICAL_SECTION_ENTER(); |
| 11437 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR0; |
| 11438 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11439 | } |
| 11440 | |
| 11441 | static inline bool hri_can_get_TXBAR_AR0_bit(const void *const hw) |
| 11442 | { |
| 11443 | uint32_t tmp; |
| 11444 | tmp = ((Can *)hw)->TXBAR.reg; |
| 11445 | tmp = (tmp & CAN_TXBAR_AR0) >> CAN_TXBAR_AR0_Pos; |
| 11446 | return (bool)tmp; |
| 11447 | } |
| 11448 | |
| 11449 | static inline void hri_can_write_TXBAR_AR0_bit(const void *const hw, bool value) |
| 11450 | { |
| 11451 | uint32_t tmp; |
| 11452 | CAN_CRITICAL_SECTION_ENTER(); |
| 11453 | tmp = ((Can *)hw)->TXBAR.reg; |
| 11454 | tmp &= ~CAN_TXBAR_AR0; |
| 11455 | tmp |= value << CAN_TXBAR_AR0_Pos; |
| 11456 | ((Can *)hw)->TXBAR.reg = tmp; |
| 11457 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11458 | } |
| 11459 | |
| 11460 | static inline void hri_can_clear_TXBAR_AR0_bit(const void *const hw) |
| 11461 | { |
| 11462 | CAN_CRITICAL_SECTION_ENTER(); |
| 11463 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR0; |
| 11464 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11465 | } |
| 11466 | |
| 11467 | static inline void hri_can_toggle_TXBAR_AR0_bit(const void *const hw) |
| 11468 | { |
| 11469 | CAN_CRITICAL_SECTION_ENTER(); |
| 11470 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR0; |
| 11471 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11472 | } |
| 11473 | |
| 11474 | static inline void hri_can_set_TXBAR_AR1_bit(const void *const hw) |
| 11475 | { |
| 11476 | CAN_CRITICAL_SECTION_ENTER(); |
| 11477 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR1; |
| 11478 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11479 | } |
| 11480 | |
| 11481 | static inline bool hri_can_get_TXBAR_AR1_bit(const void *const hw) |
| 11482 | { |
| 11483 | uint32_t tmp; |
| 11484 | tmp = ((Can *)hw)->TXBAR.reg; |
| 11485 | tmp = (tmp & CAN_TXBAR_AR1) >> CAN_TXBAR_AR1_Pos; |
| 11486 | return (bool)tmp; |
| 11487 | } |
| 11488 | |
| 11489 | static inline void hri_can_write_TXBAR_AR1_bit(const void *const hw, bool value) |
| 11490 | { |
| 11491 | uint32_t tmp; |
| 11492 | CAN_CRITICAL_SECTION_ENTER(); |
| 11493 | tmp = ((Can *)hw)->TXBAR.reg; |
| 11494 | tmp &= ~CAN_TXBAR_AR1; |
| 11495 | tmp |= value << CAN_TXBAR_AR1_Pos; |
| 11496 | ((Can *)hw)->TXBAR.reg = tmp; |
| 11497 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11498 | } |
| 11499 | |
| 11500 | static inline void hri_can_clear_TXBAR_AR1_bit(const void *const hw) |
| 11501 | { |
| 11502 | CAN_CRITICAL_SECTION_ENTER(); |
| 11503 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR1; |
| 11504 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11505 | } |
| 11506 | |
| 11507 | static inline void hri_can_toggle_TXBAR_AR1_bit(const void *const hw) |
| 11508 | { |
| 11509 | CAN_CRITICAL_SECTION_ENTER(); |
| 11510 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR1; |
| 11511 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11512 | } |
| 11513 | |
| 11514 | static inline void hri_can_set_TXBAR_AR2_bit(const void *const hw) |
| 11515 | { |
| 11516 | CAN_CRITICAL_SECTION_ENTER(); |
| 11517 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR2; |
| 11518 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11519 | } |
| 11520 | |
| 11521 | static inline bool hri_can_get_TXBAR_AR2_bit(const void *const hw) |
| 11522 | { |
| 11523 | uint32_t tmp; |
| 11524 | tmp = ((Can *)hw)->TXBAR.reg; |
| 11525 | tmp = (tmp & CAN_TXBAR_AR2) >> CAN_TXBAR_AR2_Pos; |
| 11526 | return (bool)tmp; |
| 11527 | } |
| 11528 | |
| 11529 | static inline void hri_can_write_TXBAR_AR2_bit(const void *const hw, bool value) |
| 11530 | { |
| 11531 | uint32_t tmp; |
| 11532 | CAN_CRITICAL_SECTION_ENTER(); |
| 11533 | tmp = ((Can *)hw)->TXBAR.reg; |
| 11534 | tmp &= ~CAN_TXBAR_AR2; |
| 11535 | tmp |= value << CAN_TXBAR_AR2_Pos; |
| 11536 | ((Can *)hw)->TXBAR.reg = tmp; |
| 11537 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11538 | } |
| 11539 | |
| 11540 | static inline void hri_can_clear_TXBAR_AR2_bit(const void *const hw) |
| 11541 | { |
| 11542 | CAN_CRITICAL_SECTION_ENTER(); |
| 11543 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR2; |
| 11544 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11545 | } |
| 11546 | |
| 11547 | static inline void hri_can_toggle_TXBAR_AR2_bit(const void *const hw) |
| 11548 | { |
| 11549 | CAN_CRITICAL_SECTION_ENTER(); |
| 11550 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR2; |
| 11551 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11552 | } |
| 11553 | |
| 11554 | static inline void hri_can_set_TXBAR_AR3_bit(const void *const hw) |
| 11555 | { |
| 11556 | CAN_CRITICAL_SECTION_ENTER(); |
| 11557 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR3; |
| 11558 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11559 | } |
| 11560 | |
| 11561 | static inline bool hri_can_get_TXBAR_AR3_bit(const void *const hw) |
| 11562 | { |
| 11563 | uint32_t tmp; |
| 11564 | tmp = ((Can *)hw)->TXBAR.reg; |
| 11565 | tmp = (tmp & CAN_TXBAR_AR3) >> CAN_TXBAR_AR3_Pos; |
| 11566 | return (bool)tmp; |
| 11567 | } |
| 11568 | |
| 11569 | static inline void hri_can_write_TXBAR_AR3_bit(const void *const hw, bool value) |
| 11570 | { |
| 11571 | uint32_t tmp; |
| 11572 | CAN_CRITICAL_SECTION_ENTER(); |
| 11573 | tmp = ((Can *)hw)->TXBAR.reg; |
| 11574 | tmp &= ~CAN_TXBAR_AR3; |
| 11575 | tmp |= value << CAN_TXBAR_AR3_Pos; |
| 11576 | ((Can *)hw)->TXBAR.reg = tmp; |
| 11577 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11578 | } |
| 11579 | |
| 11580 | static inline void hri_can_clear_TXBAR_AR3_bit(const void *const hw) |
| 11581 | { |
| 11582 | CAN_CRITICAL_SECTION_ENTER(); |
| 11583 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR3; |
| 11584 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11585 | } |
| 11586 | |
| 11587 | static inline void hri_can_toggle_TXBAR_AR3_bit(const void *const hw) |
| 11588 | { |
| 11589 | CAN_CRITICAL_SECTION_ENTER(); |
| 11590 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR3; |
| 11591 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11592 | } |
| 11593 | |
| 11594 | static inline void hri_can_set_TXBAR_AR4_bit(const void *const hw) |
| 11595 | { |
| 11596 | CAN_CRITICAL_SECTION_ENTER(); |
| 11597 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR4; |
| 11598 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11599 | } |
| 11600 | |
| 11601 | static inline bool hri_can_get_TXBAR_AR4_bit(const void *const hw) |
| 11602 | { |
| 11603 | uint32_t tmp; |
| 11604 | tmp = ((Can *)hw)->TXBAR.reg; |
| 11605 | tmp = (tmp & CAN_TXBAR_AR4) >> CAN_TXBAR_AR4_Pos; |
| 11606 | return (bool)tmp; |
| 11607 | } |
| 11608 | |
| 11609 | static inline void hri_can_write_TXBAR_AR4_bit(const void *const hw, bool value) |
| 11610 | { |
| 11611 | uint32_t tmp; |
| 11612 | CAN_CRITICAL_SECTION_ENTER(); |
| 11613 | tmp = ((Can *)hw)->TXBAR.reg; |
| 11614 | tmp &= ~CAN_TXBAR_AR4; |
| 11615 | tmp |= value << CAN_TXBAR_AR4_Pos; |
| 11616 | ((Can *)hw)->TXBAR.reg = tmp; |
| 11617 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11618 | } |
| 11619 | |
| 11620 | static inline void hri_can_clear_TXBAR_AR4_bit(const void *const hw) |
| 11621 | { |
| 11622 | CAN_CRITICAL_SECTION_ENTER(); |
| 11623 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR4; |
| 11624 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11625 | } |
| 11626 | |
| 11627 | static inline void hri_can_toggle_TXBAR_AR4_bit(const void *const hw) |
| 11628 | { |
| 11629 | CAN_CRITICAL_SECTION_ENTER(); |
| 11630 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR4; |
| 11631 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11632 | } |
| 11633 | |
| 11634 | static inline void hri_can_set_TXBAR_AR5_bit(const void *const hw) |
| 11635 | { |
| 11636 | CAN_CRITICAL_SECTION_ENTER(); |
| 11637 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR5; |
| 11638 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11639 | } |
| 11640 | |
| 11641 | static inline bool hri_can_get_TXBAR_AR5_bit(const void *const hw) |
| 11642 | { |
| 11643 | uint32_t tmp; |
| 11644 | tmp = ((Can *)hw)->TXBAR.reg; |
| 11645 | tmp = (tmp & CAN_TXBAR_AR5) >> CAN_TXBAR_AR5_Pos; |
| 11646 | return (bool)tmp; |
| 11647 | } |
| 11648 | |
| 11649 | static inline void hri_can_write_TXBAR_AR5_bit(const void *const hw, bool value) |
| 11650 | { |
| 11651 | uint32_t tmp; |
| 11652 | CAN_CRITICAL_SECTION_ENTER(); |
| 11653 | tmp = ((Can *)hw)->TXBAR.reg; |
| 11654 | tmp &= ~CAN_TXBAR_AR5; |
| 11655 | tmp |= value << CAN_TXBAR_AR5_Pos; |
| 11656 | ((Can *)hw)->TXBAR.reg = tmp; |
| 11657 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11658 | } |
| 11659 | |
| 11660 | static inline void hri_can_clear_TXBAR_AR5_bit(const void *const hw) |
| 11661 | { |
| 11662 | CAN_CRITICAL_SECTION_ENTER(); |
| 11663 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR5; |
| 11664 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11665 | } |
| 11666 | |
| 11667 | static inline void hri_can_toggle_TXBAR_AR5_bit(const void *const hw) |
| 11668 | { |
| 11669 | CAN_CRITICAL_SECTION_ENTER(); |
| 11670 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR5; |
| 11671 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11672 | } |
| 11673 | |
| 11674 | static inline void hri_can_set_TXBAR_AR6_bit(const void *const hw) |
| 11675 | { |
| 11676 | CAN_CRITICAL_SECTION_ENTER(); |
| 11677 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR6; |
| 11678 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11679 | } |
| 11680 | |
| 11681 | static inline bool hri_can_get_TXBAR_AR6_bit(const void *const hw) |
| 11682 | { |
| 11683 | uint32_t tmp; |
| 11684 | tmp = ((Can *)hw)->TXBAR.reg; |
| 11685 | tmp = (tmp & CAN_TXBAR_AR6) >> CAN_TXBAR_AR6_Pos; |
| 11686 | return (bool)tmp; |
| 11687 | } |
| 11688 | |
| 11689 | static inline void hri_can_write_TXBAR_AR6_bit(const void *const hw, bool value) |
| 11690 | { |
| 11691 | uint32_t tmp; |
| 11692 | CAN_CRITICAL_SECTION_ENTER(); |
| 11693 | tmp = ((Can *)hw)->TXBAR.reg; |
| 11694 | tmp &= ~CAN_TXBAR_AR6; |
| 11695 | tmp |= value << CAN_TXBAR_AR6_Pos; |
| 11696 | ((Can *)hw)->TXBAR.reg = tmp; |
| 11697 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11698 | } |
| 11699 | |
| 11700 | static inline void hri_can_clear_TXBAR_AR6_bit(const void *const hw) |
| 11701 | { |
| 11702 | CAN_CRITICAL_SECTION_ENTER(); |
| 11703 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR6; |
| 11704 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11705 | } |
| 11706 | |
| 11707 | static inline void hri_can_toggle_TXBAR_AR6_bit(const void *const hw) |
| 11708 | { |
| 11709 | CAN_CRITICAL_SECTION_ENTER(); |
| 11710 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR6; |
| 11711 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11712 | } |
| 11713 | |
| 11714 | static inline void hri_can_set_TXBAR_AR7_bit(const void *const hw) |
| 11715 | { |
| 11716 | CAN_CRITICAL_SECTION_ENTER(); |
| 11717 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR7; |
| 11718 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11719 | } |
| 11720 | |
| 11721 | static inline bool hri_can_get_TXBAR_AR7_bit(const void *const hw) |
| 11722 | { |
| 11723 | uint32_t tmp; |
| 11724 | tmp = ((Can *)hw)->TXBAR.reg; |
| 11725 | tmp = (tmp & CAN_TXBAR_AR7) >> CAN_TXBAR_AR7_Pos; |
| 11726 | return (bool)tmp; |
| 11727 | } |
| 11728 | |
| 11729 | static inline void hri_can_write_TXBAR_AR7_bit(const void *const hw, bool value) |
| 11730 | { |
| 11731 | uint32_t tmp; |
| 11732 | CAN_CRITICAL_SECTION_ENTER(); |
| 11733 | tmp = ((Can *)hw)->TXBAR.reg; |
| 11734 | tmp &= ~CAN_TXBAR_AR7; |
| 11735 | tmp |= value << CAN_TXBAR_AR7_Pos; |
| 11736 | ((Can *)hw)->TXBAR.reg = tmp; |
| 11737 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11738 | } |
| 11739 | |
| 11740 | static inline void hri_can_clear_TXBAR_AR7_bit(const void *const hw) |
| 11741 | { |
| 11742 | CAN_CRITICAL_SECTION_ENTER(); |
| 11743 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR7; |
| 11744 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11745 | } |
| 11746 | |
| 11747 | static inline void hri_can_toggle_TXBAR_AR7_bit(const void *const hw) |
| 11748 | { |
| 11749 | CAN_CRITICAL_SECTION_ENTER(); |
| 11750 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR7; |
| 11751 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11752 | } |
| 11753 | |
| 11754 | static inline void hri_can_set_TXBAR_AR8_bit(const void *const hw) |
| 11755 | { |
| 11756 | CAN_CRITICAL_SECTION_ENTER(); |
| 11757 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR8; |
| 11758 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11759 | } |
| 11760 | |
| 11761 | static inline bool hri_can_get_TXBAR_AR8_bit(const void *const hw) |
| 11762 | { |
| 11763 | uint32_t tmp; |
| 11764 | tmp = ((Can *)hw)->TXBAR.reg; |
| 11765 | tmp = (tmp & CAN_TXBAR_AR8) >> CAN_TXBAR_AR8_Pos; |
| 11766 | return (bool)tmp; |
| 11767 | } |
| 11768 | |
| 11769 | static inline void hri_can_write_TXBAR_AR8_bit(const void *const hw, bool value) |
| 11770 | { |
| 11771 | uint32_t tmp; |
| 11772 | CAN_CRITICAL_SECTION_ENTER(); |
| 11773 | tmp = ((Can *)hw)->TXBAR.reg; |
| 11774 | tmp &= ~CAN_TXBAR_AR8; |
| 11775 | tmp |= value << CAN_TXBAR_AR8_Pos; |
| 11776 | ((Can *)hw)->TXBAR.reg = tmp; |
| 11777 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11778 | } |
| 11779 | |
| 11780 | static inline void hri_can_clear_TXBAR_AR8_bit(const void *const hw) |
| 11781 | { |
| 11782 | CAN_CRITICAL_SECTION_ENTER(); |
| 11783 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR8; |
| 11784 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11785 | } |
| 11786 | |
| 11787 | static inline void hri_can_toggle_TXBAR_AR8_bit(const void *const hw) |
| 11788 | { |
| 11789 | CAN_CRITICAL_SECTION_ENTER(); |
| 11790 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR8; |
| 11791 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11792 | } |
| 11793 | |
| 11794 | static inline void hri_can_set_TXBAR_AR9_bit(const void *const hw) |
| 11795 | { |
| 11796 | CAN_CRITICAL_SECTION_ENTER(); |
| 11797 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR9; |
| 11798 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11799 | } |
| 11800 | |
| 11801 | static inline bool hri_can_get_TXBAR_AR9_bit(const void *const hw) |
| 11802 | { |
| 11803 | uint32_t tmp; |
| 11804 | tmp = ((Can *)hw)->TXBAR.reg; |
| 11805 | tmp = (tmp & CAN_TXBAR_AR9) >> CAN_TXBAR_AR9_Pos; |
| 11806 | return (bool)tmp; |
| 11807 | } |
| 11808 | |
| 11809 | static inline void hri_can_write_TXBAR_AR9_bit(const void *const hw, bool value) |
| 11810 | { |
| 11811 | uint32_t tmp; |
| 11812 | CAN_CRITICAL_SECTION_ENTER(); |
| 11813 | tmp = ((Can *)hw)->TXBAR.reg; |
| 11814 | tmp &= ~CAN_TXBAR_AR9; |
| 11815 | tmp |= value << CAN_TXBAR_AR9_Pos; |
| 11816 | ((Can *)hw)->TXBAR.reg = tmp; |
| 11817 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11818 | } |
| 11819 | |
| 11820 | static inline void hri_can_clear_TXBAR_AR9_bit(const void *const hw) |
| 11821 | { |
| 11822 | CAN_CRITICAL_SECTION_ENTER(); |
| 11823 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR9; |
| 11824 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11825 | } |
| 11826 | |
| 11827 | static inline void hri_can_toggle_TXBAR_AR9_bit(const void *const hw) |
| 11828 | { |
| 11829 | CAN_CRITICAL_SECTION_ENTER(); |
| 11830 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR9; |
| 11831 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11832 | } |
| 11833 | |
| 11834 | static inline void hri_can_set_TXBAR_AR10_bit(const void *const hw) |
| 11835 | { |
| 11836 | CAN_CRITICAL_SECTION_ENTER(); |
| 11837 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR10; |
| 11838 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11839 | } |
| 11840 | |
| 11841 | static inline bool hri_can_get_TXBAR_AR10_bit(const void *const hw) |
| 11842 | { |
| 11843 | uint32_t tmp; |
| 11844 | tmp = ((Can *)hw)->TXBAR.reg; |
| 11845 | tmp = (tmp & CAN_TXBAR_AR10) >> CAN_TXBAR_AR10_Pos; |
| 11846 | return (bool)tmp; |
| 11847 | } |
| 11848 | |
| 11849 | static inline void hri_can_write_TXBAR_AR10_bit(const void *const hw, bool value) |
| 11850 | { |
| 11851 | uint32_t tmp; |
| 11852 | CAN_CRITICAL_SECTION_ENTER(); |
| 11853 | tmp = ((Can *)hw)->TXBAR.reg; |
| 11854 | tmp &= ~CAN_TXBAR_AR10; |
| 11855 | tmp |= value << CAN_TXBAR_AR10_Pos; |
| 11856 | ((Can *)hw)->TXBAR.reg = tmp; |
| 11857 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11858 | } |
| 11859 | |
| 11860 | static inline void hri_can_clear_TXBAR_AR10_bit(const void *const hw) |
| 11861 | { |
| 11862 | CAN_CRITICAL_SECTION_ENTER(); |
| 11863 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR10; |
| 11864 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11865 | } |
| 11866 | |
| 11867 | static inline void hri_can_toggle_TXBAR_AR10_bit(const void *const hw) |
| 11868 | { |
| 11869 | CAN_CRITICAL_SECTION_ENTER(); |
| 11870 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR10; |
| 11871 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11872 | } |
| 11873 | |
| 11874 | static inline void hri_can_set_TXBAR_AR11_bit(const void *const hw) |
| 11875 | { |
| 11876 | CAN_CRITICAL_SECTION_ENTER(); |
| 11877 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR11; |
| 11878 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11879 | } |
| 11880 | |
| 11881 | static inline bool hri_can_get_TXBAR_AR11_bit(const void *const hw) |
| 11882 | { |
| 11883 | uint32_t tmp; |
| 11884 | tmp = ((Can *)hw)->TXBAR.reg; |
| 11885 | tmp = (tmp & CAN_TXBAR_AR11) >> CAN_TXBAR_AR11_Pos; |
| 11886 | return (bool)tmp; |
| 11887 | } |
| 11888 | |
| 11889 | static inline void hri_can_write_TXBAR_AR11_bit(const void *const hw, bool value) |
| 11890 | { |
| 11891 | uint32_t tmp; |
| 11892 | CAN_CRITICAL_SECTION_ENTER(); |
| 11893 | tmp = ((Can *)hw)->TXBAR.reg; |
| 11894 | tmp &= ~CAN_TXBAR_AR11; |
| 11895 | tmp |= value << CAN_TXBAR_AR11_Pos; |
| 11896 | ((Can *)hw)->TXBAR.reg = tmp; |
| 11897 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11898 | } |
| 11899 | |
| 11900 | static inline void hri_can_clear_TXBAR_AR11_bit(const void *const hw) |
| 11901 | { |
| 11902 | CAN_CRITICAL_SECTION_ENTER(); |
| 11903 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR11; |
| 11904 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11905 | } |
| 11906 | |
| 11907 | static inline void hri_can_toggle_TXBAR_AR11_bit(const void *const hw) |
| 11908 | { |
| 11909 | CAN_CRITICAL_SECTION_ENTER(); |
| 11910 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR11; |
| 11911 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11912 | } |
| 11913 | |
| 11914 | static inline void hri_can_set_TXBAR_AR12_bit(const void *const hw) |
| 11915 | { |
| 11916 | CAN_CRITICAL_SECTION_ENTER(); |
| 11917 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR12; |
| 11918 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11919 | } |
| 11920 | |
| 11921 | static inline bool hri_can_get_TXBAR_AR12_bit(const void *const hw) |
| 11922 | { |
| 11923 | uint32_t tmp; |
| 11924 | tmp = ((Can *)hw)->TXBAR.reg; |
| 11925 | tmp = (tmp & CAN_TXBAR_AR12) >> CAN_TXBAR_AR12_Pos; |
| 11926 | return (bool)tmp; |
| 11927 | } |
| 11928 | |
| 11929 | static inline void hri_can_write_TXBAR_AR12_bit(const void *const hw, bool value) |
| 11930 | { |
| 11931 | uint32_t tmp; |
| 11932 | CAN_CRITICAL_SECTION_ENTER(); |
| 11933 | tmp = ((Can *)hw)->TXBAR.reg; |
| 11934 | tmp &= ~CAN_TXBAR_AR12; |
| 11935 | tmp |= value << CAN_TXBAR_AR12_Pos; |
| 11936 | ((Can *)hw)->TXBAR.reg = tmp; |
| 11937 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11938 | } |
| 11939 | |
| 11940 | static inline void hri_can_clear_TXBAR_AR12_bit(const void *const hw) |
| 11941 | { |
| 11942 | CAN_CRITICAL_SECTION_ENTER(); |
| 11943 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR12; |
| 11944 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11945 | } |
| 11946 | |
| 11947 | static inline void hri_can_toggle_TXBAR_AR12_bit(const void *const hw) |
| 11948 | { |
| 11949 | CAN_CRITICAL_SECTION_ENTER(); |
| 11950 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR12; |
| 11951 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11952 | } |
| 11953 | |
| 11954 | static inline void hri_can_set_TXBAR_AR13_bit(const void *const hw) |
| 11955 | { |
| 11956 | CAN_CRITICAL_SECTION_ENTER(); |
| 11957 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR13; |
| 11958 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11959 | } |
| 11960 | |
| 11961 | static inline bool hri_can_get_TXBAR_AR13_bit(const void *const hw) |
| 11962 | { |
| 11963 | uint32_t tmp; |
| 11964 | tmp = ((Can *)hw)->TXBAR.reg; |
| 11965 | tmp = (tmp & CAN_TXBAR_AR13) >> CAN_TXBAR_AR13_Pos; |
| 11966 | return (bool)tmp; |
| 11967 | } |
| 11968 | |
| 11969 | static inline void hri_can_write_TXBAR_AR13_bit(const void *const hw, bool value) |
| 11970 | { |
| 11971 | uint32_t tmp; |
| 11972 | CAN_CRITICAL_SECTION_ENTER(); |
| 11973 | tmp = ((Can *)hw)->TXBAR.reg; |
| 11974 | tmp &= ~CAN_TXBAR_AR13; |
| 11975 | tmp |= value << CAN_TXBAR_AR13_Pos; |
| 11976 | ((Can *)hw)->TXBAR.reg = tmp; |
| 11977 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11978 | } |
| 11979 | |
| 11980 | static inline void hri_can_clear_TXBAR_AR13_bit(const void *const hw) |
| 11981 | { |
| 11982 | CAN_CRITICAL_SECTION_ENTER(); |
| 11983 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR13; |
| 11984 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11985 | } |
| 11986 | |
| 11987 | static inline void hri_can_toggle_TXBAR_AR13_bit(const void *const hw) |
| 11988 | { |
| 11989 | CAN_CRITICAL_SECTION_ENTER(); |
| 11990 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR13; |
| 11991 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11992 | } |
| 11993 | |
| 11994 | static inline void hri_can_set_TXBAR_AR14_bit(const void *const hw) |
| 11995 | { |
| 11996 | CAN_CRITICAL_SECTION_ENTER(); |
| 11997 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR14; |
| 11998 | CAN_CRITICAL_SECTION_LEAVE(); |
| 11999 | } |
| 12000 | |
| 12001 | static inline bool hri_can_get_TXBAR_AR14_bit(const void *const hw) |
| 12002 | { |
| 12003 | uint32_t tmp; |
| 12004 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12005 | tmp = (tmp & CAN_TXBAR_AR14) >> CAN_TXBAR_AR14_Pos; |
| 12006 | return (bool)tmp; |
| 12007 | } |
| 12008 | |
| 12009 | static inline void hri_can_write_TXBAR_AR14_bit(const void *const hw, bool value) |
| 12010 | { |
| 12011 | uint32_t tmp; |
| 12012 | CAN_CRITICAL_SECTION_ENTER(); |
| 12013 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12014 | tmp &= ~CAN_TXBAR_AR14; |
| 12015 | tmp |= value << CAN_TXBAR_AR14_Pos; |
| 12016 | ((Can *)hw)->TXBAR.reg = tmp; |
| 12017 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12018 | } |
| 12019 | |
| 12020 | static inline void hri_can_clear_TXBAR_AR14_bit(const void *const hw) |
| 12021 | { |
| 12022 | CAN_CRITICAL_SECTION_ENTER(); |
| 12023 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR14; |
| 12024 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12025 | } |
| 12026 | |
| 12027 | static inline void hri_can_toggle_TXBAR_AR14_bit(const void *const hw) |
| 12028 | { |
| 12029 | CAN_CRITICAL_SECTION_ENTER(); |
| 12030 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR14; |
| 12031 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12032 | } |
| 12033 | |
| 12034 | static inline void hri_can_set_TXBAR_AR15_bit(const void *const hw) |
| 12035 | { |
| 12036 | CAN_CRITICAL_SECTION_ENTER(); |
| 12037 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR15; |
| 12038 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12039 | } |
| 12040 | |
| 12041 | static inline bool hri_can_get_TXBAR_AR15_bit(const void *const hw) |
| 12042 | { |
| 12043 | uint32_t tmp; |
| 12044 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12045 | tmp = (tmp & CAN_TXBAR_AR15) >> CAN_TXBAR_AR15_Pos; |
| 12046 | return (bool)tmp; |
| 12047 | } |
| 12048 | |
| 12049 | static inline void hri_can_write_TXBAR_AR15_bit(const void *const hw, bool value) |
| 12050 | { |
| 12051 | uint32_t tmp; |
| 12052 | CAN_CRITICAL_SECTION_ENTER(); |
| 12053 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12054 | tmp &= ~CAN_TXBAR_AR15; |
| 12055 | tmp |= value << CAN_TXBAR_AR15_Pos; |
| 12056 | ((Can *)hw)->TXBAR.reg = tmp; |
| 12057 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12058 | } |
| 12059 | |
| 12060 | static inline void hri_can_clear_TXBAR_AR15_bit(const void *const hw) |
| 12061 | { |
| 12062 | CAN_CRITICAL_SECTION_ENTER(); |
| 12063 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR15; |
| 12064 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12065 | } |
| 12066 | |
| 12067 | static inline void hri_can_toggle_TXBAR_AR15_bit(const void *const hw) |
| 12068 | { |
| 12069 | CAN_CRITICAL_SECTION_ENTER(); |
| 12070 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR15; |
| 12071 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12072 | } |
| 12073 | |
| 12074 | static inline void hri_can_set_TXBAR_AR16_bit(const void *const hw) |
| 12075 | { |
| 12076 | CAN_CRITICAL_SECTION_ENTER(); |
| 12077 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR16; |
| 12078 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12079 | } |
| 12080 | |
| 12081 | static inline bool hri_can_get_TXBAR_AR16_bit(const void *const hw) |
| 12082 | { |
| 12083 | uint32_t tmp; |
| 12084 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12085 | tmp = (tmp & CAN_TXBAR_AR16) >> CAN_TXBAR_AR16_Pos; |
| 12086 | return (bool)tmp; |
| 12087 | } |
| 12088 | |
| 12089 | static inline void hri_can_write_TXBAR_AR16_bit(const void *const hw, bool value) |
| 12090 | { |
| 12091 | uint32_t tmp; |
| 12092 | CAN_CRITICAL_SECTION_ENTER(); |
| 12093 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12094 | tmp &= ~CAN_TXBAR_AR16; |
| 12095 | tmp |= value << CAN_TXBAR_AR16_Pos; |
| 12096 | ((Can *)hw)->TXBAR.reg = tmp; |
| 12097 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12098 | } |
| 12099 | |
| 12100 | static inline void hri_can_clear_TXBAR_AR16_bit(const void *const hw) |
| 12101 | { |
| 12102 | CAN_CRITICAL_SECTION_ENTER(); |
| 12103 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR16; |
| 12104 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12105 | } |
| 12106 | |
| 12107 | static inline void hri_can_toggle_TXBAR_AR16_bit(const void *const hw) |
| 12108 | { |
| 12109 | CAN_CRITICAL_SECTION_ENTER(); |
| 12110 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR16; |
| 12111 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12112 | } |
| 12113 | |
| 12114 | static inline void hri_can_set_TXBAR_AR17_bit(const void *const hw) |
| 12115 | { |
| 12116 | CAN_CRITICAL_SECTION_ENTER(); |
| 12117 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR17; |
| 12118 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12119 | } |
| 12120 | |
| 12121 | static inline bool hri_can_get_TXBAR_AR17_bit(const void *const hw) |
| 12122 | { |
| 12123 | uint32_t tmp; |
| 12124 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12125 | tmp = (tmp & CAN_TXBAR_AR17) >> CAN_TXBAR_AR17_Pos; |
| 12126 | return (bool)tmp; |
| 12127 | } |
| 12128 | |
| 12129 | static inline void hri_can_write_TXBAR_AR17_bit(const void *const hw, bool value) |
| 12130 | { |
| 12131 | uint32_t tmp; |
| 12132 | CAN_CRITICAL_SECTION_ENTER(); |
| 12133 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12134 | tmp &= ~CAN_TXBAR_AR17; |
| 12135 | tmp |= value << CAN_TXBAR_AR17_Pos; |
| 12136 | ((Can *)hw)->TXBAR.reg = tmp; |
| 12137 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12138 | } |
| 12139 | |
| 12140 | static inline void hri_can_clear_TXBAR_AR17_bit(const void *const hw) |
| 12141 | { |
| 12142 | CAN_CRITICAL_SECTION_ENTER(); |
| 12143 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR17; |
| 12144 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12145 | } |
| 12146 | |
| 12147 | static inline void hri_can_toggle_TXBAR_AR17_bit(const void *const hw) |
| 12148 | { |
| 12149 | CAN_CRITICAL_SECTION_ENTER(); |
| 12150 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR17; |
| 12151 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12152 | } |
| 12153 | |
| 12154 | static inline void hri_can_set_TXBAR_AR18_bit(const void *const hw) |
| 12155 | { |
| 12156 | CAN_CRITICAL_SECTION_ENTER(); |
| 12157 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR18; |
| 12158 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12159 | } |
| 12160 | |
| 12161 | static inline bool hri_can_get_TXBAR_AR18_bit(const void *const hw) |
| 12162 | { |
| 12163 | uint32_t tmp; |
| 12164 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12165 | tmp = (tmp & CAN_TXBAR_AR18) >> CAN_TXBAR_AR18_Pos; |
| 12166 | return (bool)tmp; |
| 12167 | } |
| 12168 | |
| 12169 | static inline void hri_can_write_TXBAR_AR18_bit(const void *const hw, bool value) |
| 12170 | { |
| 12171 | uint32_t tmp; |
| 12172 | CAN_CRITICAL_SECTION_ENTER(); |
| 12173 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12174 | tmp &= ~CAN_TXBAR_AR18; |
| 12175 | tmp |= value << CAN_TXBAR_AR18_Pos; |
| 12176 | ((Can *)hw)->TXBAR.reg = tmp; |
| 12177 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12178 | } |
| 12179 | |
| 12180 | static inline void hri_can_clear_TXBAR_AR18_bit(const void *const hw) |
| 12181 | { |
| 12182 | CAN_CRITICAL_SECTION_ENTER(); |
| 12183 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR18; |
| 12184 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12185 | } |
| 12186 | |
| 12187 | static inline void hri_can_toggle_TXBAR_AR18_bit(const void *const hw) |
| 12188 | { |
| 12189 | CAN_CRITICAL_SECTION_ENTER(); |
| 12190 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR18; |
| 12191 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12192 | } |
| 12193 | |
| 12194 | static inline void hri_can_set_TXBAR_AR19_bit(const void *const hw) |
| 12195 | { |
| 12196 | CAN_CRITICAL_SECTION_ENTER(); |
| 12197 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR19; |
| 12198 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12199 | } |
| 12200 | |
| 12201 | static inline bool hri_can_get_TXBAR_AR19_bit(const void *const hw) |
| 12202 | { |
| 12203 | uint32_t tmp; |
| 12204 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12205 | tmp = (tmp & CAN_TXBAR_AR19) >> CAN_TXBAR_AR19_Pos; |
| 12206 | return (bool)tmp; |
| 12207 | } |
| 12208 | |
| 12209 | static inline void hri_can_write_TXBAR_AR19_bit(const void *const hw, bool value) |
| 12210 | { |
| 12211 | uint32_t tmp; |
| 12212 | CAN_CRITICAL_SECTION_ENTER(); |
| 12213 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12214 | tmp &= ~CAN_TXBAR_AR19; |
| 12215 | tmp |= value << CAN_TXBAR_AR19_Pos; |
| 12216 | ((Can *)hw)->TXBAR.reg = tmp; |
| 12217 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12218 | } |
| 12219 | |
| 12220 | static inline void hri_can_clear_TXBAR_AR19_bit(const void *const hw) |
| 12221 | { |
| 12222 | CAN_CRITICAL_SECTION_ENTER(); |
| 12223 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR19; |
| 12224 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12225 | } |
| 12226 | |
| 12227 | static inline void hri_can_toggle_TXBAR_AR19_bit(const void *const hw) |
| 12228 | { |
| 12229 | CAN_CRITICAL_SECTION_ENTER(); |
| 12230 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR19; |
| 12231 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12232 | } |
| 12233 | |
| 12234 | static inline void hri_can_set_TXBAR_AR20_bit(const void *const hw) |
| 12235 | { |
| 12236 | CAN_CRITICAL_SECTION_ENTER(); |
| 12237 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR20; |
| 12238 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12239 | } |
| 12240 | |
| 12241 | static inline bool hri_can_get_TXBAR_AR20_bit(const void *const hw) |
| 12242 | { |
| 12243 | uint32_t tmp; |
| 12244 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12245 | tmp = (tmp & CAN_TXBAR_AR20) >> CAN_TXBAR_AR20_Pos; |
| 12246 | return (bool)tmp; |
| 12247 | } |
| 12248 | |
| 12249 | static inline void hri_can_write_TXBAR_AR20_bit(const void *const hw, bool value) |
| 12250 | { |
| 12251 | uint32_t tmp; |
| 12252 | CAN_CRITICAL_SECTION_ENTER(); |
| 12253 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12254 | tmp &= ~CAN_TXBAR_AR20; |
| 12255 | tmp |= value << CAN_TXBAR_AR20_Pos; |
| 12256 | ((Can *)hw)->TXBAR.reg = tmp; |
| 12257 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12258 | } |
| 12259 | |
| 12260 | static inline void hri_can_clear_TXBAR_AR20_bit(const void *const hw) |
| 12261 | { |
| 12262 | CAN_CRITICAL_SECTION_ENTER(); |
| 12263 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR20; |
| 12264 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12265 | } |
| 12266 | |
| 12267 | static inline void hri_can_toggle_TXBAR_AR20_bit(const void *const hw) |
| 12268 | { |
| 12269 | CAN_CRITICAL_SECTION_ENTER(); |
| 12270 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR20; |
| 12271 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12272 | } |
| 12273 | |
| 12274 | static inline void hri_can_set_TXBAR_AR21_bit(const void *const hw) |
| 12275 | { |
| 12276 | CAN_CRITICAL_SECTION_ENTER(); |
| 12277 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR21; |
| 12278 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12279 | } |
| 12280 | |
| 12281 | static inline bool hri_can_get_TXBAR_AR21_bit(const void *const hw) |
| 12282 | { |
| 12283 | uint32_t tmp; |
| 12284 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12285 | tmp = (tmp & CAN_TXBAR_AR21) >> CAN_TXBAR_AR21_Pos; |
| 12286 | return (bool)tmp; |
| 12287 | } |
| 12288 | |
| 12289 | static inline void hri_can_write_TXBAR_AR21_bit(const void *const hw, bool value) |
| 12290 | { |
| 12291 | uint32_t tmp; |
| 12292 | CAN_CRITICAL_SECTION_ENTER(); |
| 12293 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12294 | tmp &= ~CAN_TXBAR_AR21; |
| 12295 | tmp |= value << CAN_TXBAR_AR21_Pos; |
| 12296 | ((Can *)hw)->TXBAR.reg = tmp; |
| 12297 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12298 | } |
| 12299 | |
| 12300 | static inline void hri_can_clear_TXBAR_AR21_bit(const void *const hw) |
| 12301 | { |
| 12302 | CAN_CRITICAL_SECTION_ENTER(); |
| 12303 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR21; |
| 12304 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12305 | } |
| 12306 | |
| 12307 | static inline void hri_can_toggle_TXBAR_AR21_bit(const void *const hw) |
| 12308 | { |
| 12309 | CAN_CRITICAL_SECTION_ENTER(); |
| 12310 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR21; |
| 12311 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12312 | } |
| 12313 | |
| 12314 | static inline void hri_can_set_TXBAR_AR22_bit(const void *const hw) |
| 12315 | { |
| 12316 | CAN_CRITICAL_SECTION_ENTER(); |
| 12317 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR22; |
| 12318 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12319 | } |
| 12320 | |
| 12321 | static inline bool hri_can_get_TXBAR_AR22_bit(const void *const hw) |
| 12322 | { |
| 12323 | uint32_t tmp; |
| 12324 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12325 | tmp = (tmp & CAN_TXBAR_AR22) >> CAN_TXBAR_AR22_Pos; |
| 12326 | return (bool)tmp; |
| 12327 | } |
| 12328 | |
| 12329 | static inline void hri_can_write_TXBAR_AR22_bit(const void *const hw, bool value) |
| 12330 | { |
| 12331 | uint32_t tmp; |
| 12332 | CAN_CRITICAL_SECTION_ENTER(); |
| 12333 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12334 | tmp &= ~CAN_TXBAR_AR22; |
| 12335 | tmp |= value << CAN_TXBAR_AR22_Pos; |
| 12336 | ((Can *)hw)->TXBAR.reg = tmp; |
| 12337 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12338 | } |
| 12339 | |
| 12340 | static inline void hri_can_clear_TXBAR_AR22_bit(const void *const hw) |
| 12341 | { |
| 12342 | CAN_CRITICAL_SECTION_ENTER(); |
| 12343 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR22; |
| 12344 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12345 | } |
| 12346 | |
| 12347 | static inline void hri_can_toggle_TXBAR_AR22_bit(const void *const hw) |
| 12348 | { |
| 12349 | CAN_CRITICAL_SECTION_ENTER(); |
| 12350 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR22; |
| 12351 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12352 | } |
| 12353 | |
| 12354 | static inline void hri_can_set_TXBAR_AR23_bit(const void *const hw) |
| 12355 | { |
| 12356 | CAN_CRITICAL_SECTION_ENTER(); |
| 12357 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR23; |
| 12358 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12359 | } |
| 12360 | |
| 12361 | static inline bool hri_can_get_TXBAR_AR23_bit(const void *const hw) |
| 12362 | { |
| 12363 | uint32_t tmp; |
| 12364 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12365 | tmp = (tmp & CAN_TXBAR_AR23) >> CAN_TXBAR_AR23_Pos; |
| 12366 | return (bool)tmp; |
| 12367 | } |
| 12368 | |
| 12369 | static inline void hri_can_write_TXBAR_AR23_bit(const void *const hw, bool value) |
| 12370 | { |
| 12371 | uint32_t tmp; |
| 12372 | CAN_CRITICAL_SECTION_ENTER(); |
| 12373 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12374 | tmp &= ~CAN_TXBAR_AR23; |
| 12375 | tmp |= value << CAN_TXBAR_AR23_Pos; |
| 12376 | ((Can *)hw)->TXBAR.reg = tmp; |
| 12377 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12378 | } |
| 12379 | |
| 12380 | static inline void hri_can_clear_TXBAR_AR23_bit(const void *const hw) |
| 12381 | { |
| 12382 | CAN_CRITICAL_SECTION_ENTER(); |
| 12383 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR23; |
| 12384 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12385 | } |
| 12386 | |
| 12387 | static inline void hri_can_toggle_TXBAR_AR23_bit(const void *const hw) |
| 12388 | { |
| 12389 | CAN_CRITICAL_SECTION_ENTER(); |
| 12390 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR23; |
| 12391 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12392 | } |
| 12393 | |
| 12394 | static inline void hri_can_set_TXBAR_AR24_bit(const void *const hw) |
| 12395 | { |
| 12396 | CAN_CRITICAL_SECTION_ENTER(); |
| 12397 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR24; |
| 12398 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12399 | } |
| 12400 | |
| 12401 | static inline bool hri_can_get_TXBAR_AR24_bit(const void *const hw) |
| 12402 | { |
| 12403 | uint32_t tmp; |
| 12404 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12405 | tmp = (tmp & CAN_TXBAR_AR24) >> CAN_TXBAR_AR24_Pos; |
| 12406 | return (bool)tmp; |
| 12407 | } |
| 12408 | |
| 12409 | static inline void hri_can_write_TXBAR_AR24_bit(const void *const hw, bool value) |
| 12410 | { |
| 12411 | uint32_t tmp; |
| 12412 | CAN_CRITICAL_SECTION_ENTER(); |
| 12413 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12414 | tmp &= ~CAN_TXBAR_AR24; |
| 12415 | tmp |= value << CAN_TXBAR_AR24_Pos; |
| 12416 | ((Can *)hw)->TXBAR.reg = tmp; |
| 12417 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12418 | } |
| 12419 | |
| 12420 | static inline void hri_can_clear_TXBAR_AR24_bit(const void *const hw) |
| 12421 | { |
| 12422 | CAN_CRITICAL_SECTION_ENTER(); |
| 12423 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR24; |
| 12424 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12425 | } |
| 12426 | |
| 12427 | static inline void hri_can_toggle_TXBAR_AR24_bit(const void *const hw) |
| 12428 | { |
| 12429 | CAN_CRITICAL_SECTION_ENTER(); |
| 12430 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR24; |
| 12431 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12432 | } |
| 12433 | |
| 12434 | static inline void hri_can_set_TXBAR_AR25_bit(const void *const hw) |
| 12435 | { |
| 12436 | CAN_CRITICAL_SECTION_ENTER(); |
| 12437 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR25; |
| 12438 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12439 | } |
| 12440 | |
| 12441 | static inline bool hri_can_get_TXBAR_AR25_bit(const void *const hw) |
| 12442 | { |
| 12443 | uint32_t tmp; |
| 12444 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12445 | tmp = (tmp & CAN_TXBAR_AR25) >> CAN_TXBAR_AR25_Pos; |
| 12446 | return (bool)tmp; |
| 12447 | } |
| 12448 | |
| 12449 | static inline void hri_can_write_TXBAR_AR25_bit(const void *const hw, bool value) |
| 12450 | { |
| 12451 | uint32_t tmp; |
| 12452 | CAN_CRITICAL_SECTION_ENTER(); |
| 12453 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12454 | tmp &= ~CAN_TXBAR_AR25; |
| 12455 | tmp |= value << CAN_TXBAR_AR25_Pos; |
| 12456 | ((Can *)hw)->TXBAR.reg = tmp; |
| 12457 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12458 | } |
| 12459 | |
| 12460 | static inline void hri_can_clear_TXBAR_AR25_bit(const void *const hw) |
| 12461 | { |
| 12462 | CAN_CRITICAL_SECTION_ENTER(); |
| 12463 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR25; |
| 12464 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12465 | } |
| 12466 | |
| 12467 | static inline void hri_can_toggle_TXBAR_AR25_bit(const void *const hw) |
| 12468 | { |
| 12469 | CAN_CRITICAL_SECTION_ENTER(); |
| 12470 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR25; |
| 12471 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12472 | } |
| 12473 | |
| 12474 | static inline void hri_can_set_TXBAR_AR26_bit(const void *const hw) |
| 12475 | { |
| 12476 | CAN_CRITICAL_SECTION_ENTER(); |
| 12477 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR26; |
| 12478 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12479 | } |
| 12480 | |
| 12481 | static inline bool hri_can_get_TXBAR_AR26_bit(const void *const hw) |
| 12482 | { |
| 12483 | uint32_t tmp; |
| 12484 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12485 | tmp = (tmp & CAN_TXBAR_AR26) >> CAN_TXBAR_AR26_Pos; |
| 12486 | return (bool)tmp; |
| 12487 | } |
| 12488 | |
| 12489 | static inline void hri_can_write_TXBAR_AR26_bit(const void *const hw, bool value) |
| 12490 | { |
| 12491 | uint32_t tmp; |
| 12492 | CAN_CRITICAL_SECTION_ENTER(); |
| 12493 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12494 | tmp &= ~CAN_TXBAR_AR26; |
| 12495 | tmp |= value << CAN_TXBAR_AR26_Pos; |
| 12496 | ((Can *)hw)->TXBAR.reg = tmp; |
| 12497 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12498 | } |
| 12499 | |
| 12500 | static inline void hri_can_clear_TXBAR_AR26_bit(const void *const hw) |
| 12501 | { |
| 12502 | CAN_CRITICAL_SECTION_ENTER(); |
| 12503 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR26; |
| 12504 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12505 | } |
| 12506 | |
| 12507 | static inline void hri_can_toggle_TXBAR_AR26_bit(const void *const hw) |
| 12508 | { |
| 12509 | CAN_CRITICAL_SECTION_ENTER(); |
| 12510 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR26; |
| 12511 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12512 | } |
| 12513 | |
| 12514 | static inline void hri_can_set_TXBAR_AR27_bit(const void *const hw) |
| 12515 | { |
| 12516 | CAN_CRITICAL_SECTION_ENTER(); |
| 12517 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR27; |
| 12518 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12519 | } |
| 12520 | |
| 12521 | static inline bool hri_can_get_TXBAR_AR27_bit(const void *const hw) |
| 12522 | { |
| 12523 | uint32_t tmp; |
| 12524 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12525 | tmp = (tmp & CAN_TXBAR_AR27) >> CAN_TXBAR_AR27_Pos; |
| 12526 | return (bool)tmp; |
| 12527 | } |
| 12528 | |
| 12529 | static inline void hri_can_write_TXBAR_AR27_bit(const void *const hw, bool value) |
| 12530 | { |
| 12531 | uint32_t tmp; |
| 12532 | CAN_CRITICAL_SECTION_ENTER(); |
| 12533 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12534 | tmp &= ~CAN_TXBAR_AR27; |
| 12535 | tmp |= value << CAN_TXBAR_AR27_Pos; |
| 12536 | ((Can *)hw)->TXBAR.reg = tmp; |
| 12537 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12538 | } |
| 12539 | |
| 12540 | static inline void hri_can_clear_TXBAR_AR27_bit(const void *const hw) |
| 12541 | { |
| 12542 | CAN_CRITICAL_SECTION_ENTER(); |
| 12543 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR27; |
| 12544 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12545 | } |
| 12546 | |
| 12547 | static inline void hri_can_toggle_TXBAR_AR27_bit(const void *const hw) |
| 12548 | { |
| 12549 | CAN_CRITICAL_SECTION_ENTER(); |
| 12550 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR27; |
| 12551 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12552 | } |
| 12553 | |
| 12554 | static inline void hri_can_set_TXBAR_AR28_bit(const void *const hw) |
| 12555 | { |
| 12556 | CAN_CRITICAL_SECTION_ENTER(); |
| 12557 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR28; |
| 12558 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12559 | } |
| 12560 | |
| 12561 | static inline bool hri_can_get_TXBAR_AR28_bit(const void *const hw) |
| 12562 | { |
| 12563 | uint32_t tmp; |
| 12564 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12565 | tmp = (tmp & CAN_TXBAR_AR28) >> CAN_TXBAR_AR28_Pos; |
| 12566 | return (bool)tmp; |
| 12567 | } |
| 12568 | |
| 12569 | static inline void hri_can_write_TXBAR_AR28_bit(const void *const hw, bool value) |
| 12570 | { |
| 12571 | uint32_t tmp; |
| 12572 | CAN_CRITICAL_SECTION_ENTER(); |
| 12573 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12574 | tmp &= ~CAN_TXBAR_AR28; |
| 12575 | tmp |= value << CAN_TXBAR_AR28_Pos; |
| 12576 | ((Can *)hw)->TXBAR.reg = tmp; |
| 12577 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12578 | } |
| 12579 | |
| 12580 | static inline void hri_can_clear_TXBAR_AR28_bit(const void *const hw) |
| 12581 | { |
| 12582 | CAN_CRITICAL_SECTION_ENTER(); |
| 12583 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR28; |
| 12584 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12585 | } |
| 12586 | |
| 12587 | static inline void hri_can_toggle_TXBAR_AR28_bit(const void *const hw) |
| 12588 | { |
| 12589 | CAN_CRITICAL_SECTION_ENTER(); |
| 12590 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR28; |
| 12591 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12592 | } |
| 12593 | |
| 12594 | static inline void hri_can_set_TXBAR_AR29_bit(const void *const hw) |
| 12595 | { |
| 12596 | CAN_CRITICAL_SECTION_ENTER(); |
| 12597 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR29; |
| 12598 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12599 | } |
| 12600 | |
| 12601 | static inline bool hri_can_get_TXBAR_AR29_bit(const void *const hw) |
| 12602 | { |
| 12603 | uint32_t tmp; |
| 12604 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12605 | tmp = (tmp & CAN_TXBAR_AR29) >> CAN_TXBAR_AR29_Pos; |
| 12606 | return (bool)tmp; |
| 12607 | } |
| 12608 | |
| 12609 | static inline void hri_can_write_TXBAR_AR29_bit(const void *const hw, bool value) |
| 12610 | { |
| 12611 | uint32_t tmp; |
| 12612 | CAN_CRITICAL_SECTION_ENTER(); |
| 12613 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12614 | tmp &= ~CAN_TXBAR_AR29; |
| 12615 | tmp |= value << CAN_TXBAR_AR29_Pos; |
| 12616 | ((Can *)hw)->TXBAR.reg = tmp; |
| 12617 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12618 | } |
| 12619 | |
| 12620 | static inline void hri_can_clear_TXBAR_AR29_bit(const void *const hw) |
| 12621 | { |
| 12622 | CAN_CRITICAL_SECTION_ENTER(); |
| 12623 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR29; |
| 12624 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12625 | } |
| 12626 | |
| 12627 | static inline void hri_can_toggle_TXBAR_AR29_bit(const void *const hw) |
| 12628 | { |
| 12629 | CAN_CRITICAL_SECTION_ENTER(); |
| 12630 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR29; |
| 12631 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12632 | } |
| 12633 | |
| 12634 | static inline void hri_can_set_TXBAR_AR30_bit(const void *const hw) |
| 12635 | { |
| 12636 | CAN_CRITICAL_SECTION_ENTER(); |
| 12637 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR30; |
| 12638 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12639 | } |
| 12640 | |
| 12641 | static inline bool hri_can_get_TXBAR_AR30_bit(const void *const hw) |
| 12642 | { |
| 12643 | uint32_t tmp; |
| 12644 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12645 | tmp = (tmp & CAN_TXBAR_AR30) >> CAN_TXBAR_AR30_Pos; |
| 12646 | return (bool)tmp; |
| 12647 | } |
| 12648 | |
| 12649 | static inline void hri_can_write_TXBAR_AR30_bit(const void *const hw, bool value) |
| 12650 | { |
| 12651 | uint32_t tmp; |
| 12652 | CAN_CRITICAL_SECTION_ENTER(); |
| 12653 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12654 | tmp &= ~CAN_TXBAR_AR30; |
| 12655 | tmp |= value << CAN_TXBAR_AR30_Pos; |
| 12656 | ((Can *)hw)->TXBAR.reg = tmp; |
| 12657 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12658 | } |
| 12659 | |
| 12660 | static inline void hri_can_clear_TXBAR_AR30_bit(const void *const hw) |
| 12661 | { |
| 12662 | CAN_CRITICAL_SECTION_ENTER(); |
| 12663 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR30; |
| 12664 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12665 | } |
| 12666 | |
| 12667 | static inline void hri_can_toggle_TXBAR_AR30_bit(const void *const hw) |
| 12668 | { |
| 12669 | CAN_CRITICAL_SECTION_ENTER(); |
| 12670 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR30; |
| 12671 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12672 | } |
| 12673 | |
| 12674 | static inline void hri_can_set_TXBAR_AR31_bit(const void *const hw) |
| 12675 | { |
| 12676 | CAN_CRITICAL_SECTION_ENTER(); |
| 12677 | ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR31; |
| 12678 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12679 | } |
| 12680 | |
| 12681 | static inline bool hri_can_get_TXBAR_AR31_bit(const void *const hw) |
| 12682 | { |
| 12683 | uint32_t tmp; |
| 12684 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12685 | tmp = (tmp & CAN_TXBAR_AR31) >> CAN_TXBAR_AR31_Pos; |
| 12686 | return (bool)tmp; |
| 12687 | } |
| 12688 | |
| 12689 | static inline void hri_can_write_TXBAR_AR31_bit(const void *const hw, bool value) |
| 12690 | { |
| 12691 | uint32_t tmp; |
| 12692 | CAN_CRITICAL_SECTION_ENTER(); |
| 12693 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12694 | tmp &= ~CAN_TXBAR_AR31; |
| 12695 | tmp |= value << CAN_TXBAR_AR31_Pos; |
| 12696 | ((Can *)hw)->TXBAR.reg = tmp; |
| 12697 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12698 | } |
| 12699 | |
| 12700 | static inline void hri_can_clear_TXBAR_AR31_bit(const void *const hw) |
| 12701 | { |
| 12702 | CAN_CRITICAL_SECTION_ENTER(); |
| 12703 | ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR31; |
| 12704 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12705 | } |
| 12706 | |
| 12707 | static inline void hri_can_toggle_TXBAR_AR31_bit(const void *const hw) |
| 12708 | { |
| 12709 | CAN_CRITICAL_SECTION_ENTER(); |
| 12710 | ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR31; |
| 12711 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12712 | } |
| 12713 | |
| 12714 | static inline void hri_can_set_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) |
| 12715 | { |
| 12716 | CAN_CRITICAL_SECTION_ENTER(); |
| 12717 | ((Can *)hw)->TXBAR.reg |= mask; |
| 12718 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12719 | } |
| 12720 | |
| 12721 | static inline hri_can_txbar_reg_t hri_can_get_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) |
| 12722 | { |
| 12723 | uint32_t tmp; |
| 12724 | tmp = ((Can *)hw)->TXBAR.reg; |
| 12725 | tmp &= mask; |
| 12726 | return tmp; |
| 12727 | } |
| 12728 | |
| 12729 | static inline void hri_can_write_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t data) |
| 12730 | { |
| 12731 | CAN_CRITICAL_SECTION_ENTER(); |
| 12732 | ((Can *)hw)->TXBAR.reg = data; |
| 12733 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12734 | } |
| 12735 | |
| 12736 | static inline void hri_can_clear_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) |
| 12737 | { |
| 12738 | CAN_CRITICAL_SECTION_ENTER(); |
| 12739 | ((Can *)hw)->TXBAR.reg &= ~mask; |
| 12740 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12741 | } |
| 12742 | |
| 12743 | static inline void hri_can_toggle_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) |
| 12744 | { |
| 12745 | CAN_CRITICAL_SECTION_ENTER(); |
| 12746 | ((Can *)hw)->TXBAR.reg ^= mask; |
| 12747 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12748 | } |
| 12749 | |
| 12750 | static inline hri_can_txbar_reg_t hri_can_read_TXBAR_reg(const void *const hw) |
| 12751 | { |
| 12752 | return ((Can *)hw)->TXBAR.reg; |
| 12753 | } |
| 12754 | |
| 12755 | static inline void hri_can_set_TXBCR_CR0_bit(const void *const hw) |
| 12756 | { |
| 12757 | CAN_CRITICAL_SECTION_ENTER(); |
| 12758 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR0; |
| 12759 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12760 | } |
| 12761 | |
| 12762 | static inline bool hri_can_get_TXBCR_CR0_bit(const void *const hw) |
| 12763 | { |
| 12764 | uint32_t tmp; |
| 12765 | tmp = ((Can *)hw)->TXBCR.reg; |
| 12766 | tmp = (tmp & CAN_TXBCR_CR0) >> CAN_TXBCR_CR0_Pos; |
| 12767 | return (bool)tmp; |
| 12768 | } |
| 12769 | |
| 12770 | static inline void hri_can_write_TXBCR_CR0_bit(const void *const hw, bool value) |
| 12771 | { |
| 12772 | uint32_t tmp; |
| 12773 | CAN_CRITICAL_SECTION_ENTER(); |
| 12774 | tmp = ((Can *)hw)->TXBCR.reg; |
| 12775 | tmp &= ~CAN_TXBCR_CR0; |
| 12776 | tmp |= value << CAN_TXBCR_CR0_Pos; |
| 12777 | ((Can *)hw)->TXBCR.reg = tmp; |
| 12778 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12779 | } |
| 12780 | |
| 12781 | static inline void hri_can_clear_TXBCR_CR0_bit(const void *const hw) |
| 12782 | { |
| 12783 | CAN_CRITICAL_SECTION_ENTER(); |
| 12784 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR0; |
| 12785 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12786 | } |
| 12787 | |
| 12788 | static inline void hri_can_toggle_TXBCR_CR0_bit(const void *const hw) |
| 12789 | { |
| 12790 | CAN_CRITICAL_SECTION_ENTER(); |
| 12791 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR0; |
| 12792 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12793 | } |
| 12794 | |
| 12795 | static inline void hri_can_set_TXBCR_CR1_bit(const void *const hw) |
| 12796 | { |
| 12797 | CAN_CRITICAL_SECTION_ENTER(); |
| 12798 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR1; |
| 12799 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12800 | } |
| 12801 | |
| 12802 | static inline bool hri_can_get_TXBCR_CR1_bit(const void *const hw) |
| 12803 | { |
| 12804 | uint32_t tmp; |
| 12805 | tmp = ((Can *)hw)->TXBCR.reg; |
| 12806 | tmp = (tmp & CAN_TXBCR_CR1) >> CAN_TXBCR_CR1_Pos; |
| 12807 | return (bool)tmp; |
| 12808 | } |
| 12809 | |
| 12810 | static inline void hri_can_write_TXBCR_CR1_bit(const void *const hw, bool value) |
| 12811 | { |
| 12812 | uint32_t tmp; |
| 12813 | CAN_CRITICAL_SECTION_ENTER(); |
| 12814 | tmp = ((Can *)hw)->TXBCR.reg; |
| 12815 | tmp &= ~CAN_TXBCR_CR1; |
| 12816 | tmp |= value << CAN_TXBCR_CR1_Pos; |
| 12817 | ((Can *)hw)->TXBCR.reg = tmp; |
| 12818 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12819 | } |
| 12820 | |
| 12821 | static inline void hri_can_clear_TXBCR_CR1_bit(const void *const hw) |
| 12822 | { |
| 12823 | CAN_CRITICAL_SECTION_ENTER(); |
| 12824 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR1; |
| 12825 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12826 | } |
| 12827 | |
| 12828 | static inline void hri_can_toggle_TXBCR_CR1_bit(const void *const hw) |
| 12829 | { |
| 12830 | CAN_CRITICAL_SECTION_ENTER(); |
| 12831 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR1; |
| 12832 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12833 | } |
| 12834 | |
| 12835 | static inline void hri_can_set_TXBCR_CR2_bit(const void *const hw) |
| 12836 | { |
| 12837 | CAN_CRITICAL_SECTION_ENTER(); |
| 12838 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR2; |
| 12839 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12840 | } |
| 12841 | |
| 12842 | static inline bool hri_can_get_TXBCR_CR2_bit(const void *const hw) |
| 12843 | { |
| 12844 | uint32_t tmp; |
| 12845 | tmp = ((Can *)hw)->TXBCR.reg; |
| 12846 | tmp = (tmp & CAN_TXBCR_CR2) >> CAN_TXBCR_CR2_Pos; |
| 12847 | return (bool)tmp; |
| 12848 | } |
| 12849 | |
| 12850 | static inline void hri_can_write_TXBCR_CR2_bit(const void *const hw, bool value) |
| 12851 | { |
| 12852 | uint32_t tmp; |
| 12853 | CAN_CRITICAL_SECTION_ENTER(); |
| 12854 | tmp = ((Can *)hw)->TXBCR.reg; |
| 12855 | tmp &= ~CAN_TXBCR_CR2; |
| 12856 | tmp |= value << CAN_TXBCR_CR2_Pos; |
| 12857 | ((Can *)hw)->TXBCR.reg = tmp; |
| 12858 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12859 | } |
| 12860 | |
| 12861 | static inline void hri_can_clear_TXBCR_CR2_bit(const void *const hw) |
| 12862 | { |
| 12863 | CAN_CRITICAL_SECTION_ENTER(); |
| 12864 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR2; |
| 12865 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12866 | } |
| 12867 | |
| 12868 | static inline void hri_can_toggle_TXBCR_CR2_bit(const void *const hw) |
| 12869 | { |
| 12870 | CAN_CRITICAL_SECTION_ENTER(); |
| 12871 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR2; |
| 12872 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12873 | } |
| 12874 | |
| 12875 | static inline void hri_can_set_TXBCR_CR3_bit(const void *const hw) |
| 12876 | { |
| 12877 | CAN_CRITICAL_SECTION_ENTER(); |
| 12878 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR3; |
| 12879 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12880 | } |
| 12881 | |
| 12882 | static inline bool hri_can_get_TXBCR_CR3_bit(const void *const hw) |
| 12883 | { |
| 12884 | uint32_t tmp; |
| 12885 | tmp = ((Can *)hw)->TXBCR.reg; |
| 12886 | tmp = (tmp & CAN_TXBCR_CR3) >> CAN_TXBCR_CR3_Pos; |
| 12887 | return (bool)tmp; |
| 12888 | } |
| 12889 | |
| 12890 | static inline void hri_can_write_TXBCR_CR3_bit(const void *const hw, bool value) |
| 12891 | { |
| 12892 | uint32_t tmp; |
| 12893 | CAN_CRITICAL_SECTION_ENTER(); |
| 12894 | tmp = ((Can *)hw)->TXBCR.reg; |
| 12895 | tmp &= ~CAN_TXBCR_CR3; |
| 12896 | tmp |= value << CAN_TXBCR_CR3_Pos; |
| 12897 | ((Can *)hw)->TXBCR.reg = tmp; |
| 12898 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12899 | } |
| 12900 | |
| 12901 | static inline void hri_can_clear_TXBCR_CR3_bit(const void *const hw) |
| 12902 | { |
| 12903 | CAN_CRITICAL_SECTION_ENTER(); |
| 12904 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR3; |
| 12905 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12906 | } |
| 12907 | |
| 12908 | static inline void hri_can_toggle_TXBCR_CR3_bit(const void *const hw) |
| 12909 | { |
| 12910 | CAN_CRITICAL_SECTION_ENTER(); |
| 12911 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR3; |
| 12912 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12913 | } |
| 12914 | |
| 12915 | static inline void hri_can_set_TXBCR_CR4_bit(const void *const hw) |
| 12916 | { |
| 12917 | CAN_CRITICAL_SECTION_ENTER(); |
| 12918 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR4; |
| 12919 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12920 | } |
| 12921 | |
| 12922 | static inline bool hri_can_get_TXBCR_CR4_bit(const void *const hw) |
| 12923 | { |
| 12924 | uint32_t tmp; |
| 12925 | tmp = ((Can *)hw)->TXBCR.reg; |
| 12926 | tmp = (tmp & CAN_TXBCR_CR4) >> CAN_TXBCR_CR4_Pos; |
| 12927 | return (bool)tmp; |
| 12928 | } |
| 12929 | |
| 12930 | static inline void hri_can_write_TXBCR_CR4_bit(const void *const hw, bool value) |
| 12931 | { |
| 12932 | uint32_t tmp; |
| 12933 | CAN_CRITICAL_SECTION_ENTER(); |
| 12934 | tmp = ((Can *)hw)->TXBCR.reg; |
| 12935 | tmp &= ~CAN_TXBCR_CR4; |
| 12936 | tmp |= value << CAN_TXBCR_CR4_Pos; |
| 12937 | ((Can *)hw)->TXBCR.reg = tmp; |
| 12938 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12939 | } |
| 12940 | |
| 12941 | static inline void hri_can_clear_TXBCR_CR4_bit(const void *const hw) |
| 12942 | { |
| 12943 | CAN_CRITICAL_SECTION_ENTER(); |
| 12944 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR4; |
| 12945 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12946 | } |
| 12947 | |
| 12948 | static inline void hri_can_toggle_TXBCR_CR4_bit(const void *const hw) |
| 12949 | { |
| 12950 | CAN_CRITICAL_SECTION_ENTER(); |
| 12951 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR4; |
| 12952 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12953 | } |
| 12954 | |
| 12955 | static inline void hri_can_set_TXBCR_CR5_bit(const void *const hw) |
| 12956 | { |
| 12957 | CAN_CRITICAL_SECTION_ENTER(); |
| 12958 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR5; |
| 12959 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12960 | } |
| 12961 | |
| 12962 | static inline bool hri_can_get_TXBCR_CR5_bit(const void *const hw) |
| 12963 | { |
| 12964 | uint32_t tmp; |
| 12965 | tmp = ((Can *)hw)->TXBCR.reg; |
| 12966 | tmp = (tmp & CAN_TXBCR_CR5) >> CAN_TXBCR_CR5_Pos; |
| 12967 | return (bool)tmp; |
| 12968 | } |
| 12969 | |
| 12970 | static inline void hri_can_write_TXBCR_CR5_bit(const void *const hw, bool value) |
| 12971 | { |
| 12972 | uint32_t tmp; |
| 12973 | CAN_CRITICAL_SECTION_ENTER(); |
| 12974 | tmp = ((Can *)hw)->TXBCR.reg; |
| 12975 | tmp &= ~CAN_TXBCR_CR5; |
| 12976 | tmp |= value << CAN_TXBCR_CR5_Pos; |
| 12977 | ((Can *)hw)->TXBCR.reg = tmp; |
| 12978 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12979 | } |
| 12980 | |
| 12981 | static inline void hri_can_clear_TXBCR_CR5_bit(const void *const hw) |
| 12982 | { |
| 12983 | CAN_CRITICAL_SECTION_ENTER(); |
| 12984 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR5; |
| 12985 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12986 | } |
| 12987 | |
| 12988 | static inline void hri_can_toggle_TXBCR_CR5_bit(const void *const hw) |
| 12989 | { |
| 12990 | CAN_CRITICAL_SECTION_ENTER(); |
| 12991 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR5; |
| 12992 | CAN_CRITICAL_SECTION_LEAVE(); |
| 12993 | } |
| 12994 | |
| 12995 | static inline void hri_can_set_TXBCR_CR6_bit(const void *const hw) |
| 12996 | { |
| 12997 | CAN_CRITICAL_SECTION_ENTER(); |
| 12998 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR6; |
| 12999 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13000 | } |
| 13001 | |
| 13002 | static inline bool hri_can_get_TXBCR_CR6_bit(const void *const hw) |
| 13003 | { |
| 13004 | uint32_t tmp; |
| 13005 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13006 | tmp = (tmp & CAN_TXBCR_CR6) >> CAN_TXBCR_CR6_Pos; |
| 13007 | return (bool)tmp; |
| 13008 | } |
| 13009 | |
| 13010 | static inline void hri_can_write_TXBCR_CR6_bit(const void *const hw, bool value) |
| 13011 | { |
| 13012 | uint32_t tmp; |
| 13013 | CAN_CRITICAL_SECTION_ENTER(); |
| 13014 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13015 | tmp &= ~CAN_TXBCR_CR6; |
| 13016 | tmp |= value << CAN_TXBCR_CR6_Pos; |
| 13017 | ((Can *)hw)->TXBCR.reg = tmp; |
| 13018 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13019 | } |
| 13020 | |
| 13021 | static inline void hri_can_clear_TXBCR_CR6_bit(const void *const hw) |
| 13022 | { |
| 13023 | CAN_CRITICAL_SECTION_ENTER(); |
| 13024 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR6; |
| 13025 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13026 | } |
| 13027 | |
| 13028 | static inline void hri_can_toggle_TXBCR_CR6_bit(const void *const hw) |
| 13029 | { |
| 13030 | CAN_CRITICAL_SECTION_ENTER(); |
| 13031 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR6; |
| 13032 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13033 | } |
| 13034 | |
| 13035 | static inline void hri_can_set_TXBCR_CR7_bit(const void *const hw) |
| 13036 | { |
| 13037 | CAN_CRITICAL_SECTION_ENTER(); |
| 13038 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR7; |
| 13039 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13040 | } |
| 13041 | |
| 13042 | static inline bool hri_can_get_TXBCR_CR7_bit(const void *const hw) |
| 13043 | { |
| 13044 | uint32_t tmp; |
| 13045 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13046 | tmp = (tmp & CAN_TXBCR_CR7) >> CAN_TXBCR_CR7_Pos; |
| 13047 | return (bool)tmp; |
| 13048 | } |
| 13049 | |
| 13050 | static inline void hri_can_write_TXBCR_CR7_bit(const void *const hw, bool value) |
| 13051 | { |
| 13052 | uint32_t tmp; |
| 13053 | CAN_CRITICAL_SECTION_ENTER(); |
| 13054 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13055 | tmp &= ~CAN_TXBCR_CR7; |
| 13056 | tmp |= value << CAN_TXBCR_CR7_Pos; |
| 13057 | ((Can *)hw)->TXBCR.reg = tmp; |
| 13058 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13059 | } |
| 13060 | |
| 13061 | static inline void hri_can_clear_TXBCR_CR7_bit(const void *const hw) |
| 13062 | { |
| 13063 | CAN_CRITICAL_SECTION_ENTER(); |
| 13064 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR7; |
| 13065 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13066 | } |
| 13067 | |
| 13068 | static inline void hri_can_toggle_TXBCR_CR7_bit(const void *const hw) |
| 13069 | { |
| 13070 | CAN_CRITICAL_SECTION_ENTER(); |
| 13071 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR7; |
| 13072 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13073 | } |
| 13074 | |
| 13075 | static inline void hri_can_set_TXBCR_CR8_bit(const void *const hw) |
| 13076 | { |
| 13077 | CAN_CRITICAL_SECTION_ENTER(); |
| 13078 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR8; |
| 13079 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13080 | } |
| 13081 | |
| 13082 | static inline bool hri_can_get_TXBCR_CR8_bit(const void *const hw) |
| 13083 | { |
| 13084 | uint32_t tmp; |
| 13085 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13086 | tmp = (tmp & CAN_TXBCR_CR8) >> CAN_TXBCR_CR8_Pos; |
| 13087 | return (bool)tmp; |
| 13088 | } |
| 13089 | |
| 13090 | static inline void hri_can_write_TXBCR_CR8_bit(const void *const hw, bool value) |
| 13091 | { |
| 13092 | uint32_t tmp; |
| 13093 | CAN_CRITICAL_SECTION_ENTER(); |
| 13094 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13095 | tmp &= ~CAN_TXBCR_CR8; |
| 13096 | tmp |= value << CAN_TXBCR_CR8_Pos; |
| 13097 | ((Can *)hw)->TXBCR.reg = tmp; |
| 13098 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13099 | } |
| 13100 | |
| 13101 | static inline void hri_can_clear_TXBCR_CR8_bit(const void *const hw) |
| 13102 | { |
| 13103 | CAN_CRITICAL_SECTION_ENTER(); |
| 13104 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR8; |
| 13105 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13106 | } |
| 13107 | |
| 13108 | static inline void hri_can_toggle_TXBCR_CR8_bit(const void *const hw) |
| 13109 | { |
| 13110 | CAN_CRITICAL_SECTION_ENTER(); |
| 13111 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR8; |
| 13112 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13113 | } |
| 13114 | |
| 13115 | static inline void hri_can_set_TXBCR_CR9_bit(const void *const hw) |
| 13116 | { |
| 13117 | CAN_CRITICAL_SECTION_ENTER(); |
| 13118 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR9; |
| 13119 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13120 | } |
| 13121 | |
| 13122 | static inline bool hri_can_get_TXBCR_CR9_bit(const void *const hw) |
| 13123 | { |
| 13124 | uint32_t tmp; |
| 13125 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13126 | tmp = (tmp & CAN_TXBCR_CR9) >> CAN_TXBCR_CR9_Pos; |
| 13127 | return (bool)tmp; |
| 13128 | } |
| 13129 | |
| 13130 | static inline void hri_can_write_TXBCR_CR9_bit(const void *const hw, bool value) |
| 13131 | { |
| 13132 | uint32_t tmp; |
| 13133 | CAN_CRITICAL_SECTION_ENTER(); |
| 13134 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13135 | tmp &= ~CAN_TXBCR_CR9; |
| 13136 | tmp |= value << CAN_TXBCR_CR9_Pos; |
| 13137 | ((Can *)hw)->TXBCR.reg = tmp; |
| 13138 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13139 | } |
| 13140 | |
| 13141 | static inline void hri_can_clear_TXBCR_CR9_bit(const void *const hw) |
| 13142 | { |
| 13143 | CAN_CRITICAL_SECTION_ENTER(); |
| 13144 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR9; |
| 13145 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13146 | } |
| 13147 | |
| 13148 | static inline void hri_can_toggle_TXBCR_CR9_bit(const void *const hw) |
| 13149 | { |
| 13150 | CAN_CRITICAL_SECTION_ENTER(); |
| 13151 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR9; |
| 13152 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13153 | } |
| 13154 | |
| 13155 | static inline void hri_can_set_TXBCR_CR10_bit(const void *const hw) |
| 13156 | { |
| 13157 | CAN_CRITICAL_SECTION_ENTER(); |
| 13158 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR10; |
| 13159 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13160 | } |
| 13161 | |
| 13162 | static inline bool hri_can_get_TXBCR_CR10_bit(const void *const hw) |
| 13163 | { |
| 13164 | uint32_t tmp; |
| 13165 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13166 | tmp = (tmp & CAN_TXBCR_CR10) >> CAN_TXBCR_CR10_Pos; |
| 13167 | return (bool)tmp; |
| 13168 | } |
| 13169 | |
| 13170 | static inline void hri_can_write_TXBCR_CR10_bit(const void *const hw, bool value) |
| 13171 | { |
| 13172 | uint32_t tmp; |
| 13173 | CAN_CRITICAL_SECTION_ENTER(); |
| 13174 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13175 | tmp &= ~CAN_TXBCR_CR10; |
| 13176 | tmp |= value << CAN_TXBCR_CR10_Pos; |
| 13177 | ((Can *)hw)->TXBCR.reg = tmp; |
| 13178 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13179 | } |
| 13180 | |
| 13181 | static inline void hri_can_clear_TXBCR_CR10_bit(const void *const hw) |
| 13182 | { |
| 13183 | CAN_CRITICAL_SECTION_ENTER(); |
| 13184 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR10; |
| 13185 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13186 | } |
| 13187 | |
| 13188 | static inline void hri_can_toggle_TXBCR_CR10_bit(const void *const hw) |
| 13189 | { |
| 13190 | CAN_CRITICAL_SECTION_ENTER(); |
| 13191 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR10; |
| 13192 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13193 | } |
| 13194 | |
| 13195 | static inline void hri_can_set_TXBCR_CR11_bit(const void *const hw) |
| 13196 | { |
| 13197 | CAN_CRITICAL_SECTION_ENTER(); |
| 13198 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR11; |
| 13199 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13200 | } |
| 13201 | |
| 13202 | static inline bool hri_can_get_TXBCR_CR11_bit(const void *const hw) |
| 13203 | { |
| 13204 | uint32_t tmp; |
| 13205 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13206 | tmp = (tmp & CAN_TXBCR_CR11) >> CAN_TXBCR_CR11_Pos; |
| 13207 | return (bool)tmp; |
| 13208 | } |
| 13209 | |
| 13210 | static inline void hri_can_write_TXBCR_CR11_bit(const void *const hw, bool value) |
| 13211 | { |
| 13212 | uint32_t tmp; |
| 13213 | CAN_CRITICAL_SECTION_ENTER(); |
| 13214 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13215 | tmp &= ~CAN_TXBCR_CR11; |
| 13216 | tmp |= value << CAN_TXBCR_CR11_Pos; |
| 13217 | ((Can *)hw)->TXBCR.reg = tmp; |
| 13218 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13219 | } |
| 13220 | |
| 13221 | static inline void hri_can_clear_TXBCR_CR11_bit(const void *const hw) |
| 13222 | { |
| 13223 | CAN_CRITICAL_SECTION_ENTER(); |
| 13224 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR11; |
| 13225 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13226 | } |
| 13227 | |
| 13228 | static inline void hri_can_toggle_TXBCR_CR11_bit(const void *const hw) |
| 13229 | { |
| 13230 | CAN_CRITICAL_SECTION_ENTER(); |
| 13231 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR11; |
| 13232 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13233 | } |
| 13234 | |
| 13235 | static inline void hri_can_set_TXBCR_CR12_bit(const void *const hw) |
| 13236 | { |
| 13237 | CAN_CRITICAL_SECTION_ENTER(); |
| 13238 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR12; |
| 13239 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13240 | } |
| 13241 | |
| 13242 | static inline bool hri_can_get_TXBCR_CR12_bit(const void *const hw) |
| 13243 | { |
| 13244 | uint32_t tmp; |
| 13245 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13246 | tmp = (tmp & CAN_TXBCR_CR12) >> CAN_TXBCR_CR12_Pos; |
| 13247 | return (bool)tmp; |
| 13248 | } |
| 13249 | |
| 13250 | static inline void hri_can_write_TXBCR_CR12_bit(const void *const hw, bool value) |
| 13251 | { |
| 13252 | uint32_t tmp; |
| 13253 | CAN_CRITICAL_SECTION_ENTER(); |
| 13254 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13255 | tmp &= ~CAN_TXBCR_CR12; |
| 13256 | tmp |= value << CAN_TXBCR_CR12_Pos; |
| 13257 | ((Can *)hw)->TXBCR.reg = tmp; |
| 13258 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13259 | } |
| 13260 | |
| 13261 | static inline void hri_can_clear_TXBCR_CR12_bit(const void *const hw) |
| 13262 | { |
| 13263 | CAN_CRITICAL_SECTION_ENTER(); |
| 13264 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR12; |
| 13265 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13266 | } |
| 13267 | |
| 13268 | static inline void hri_can_toggle_TXBCR_CR12_bit(const void *const hw) |
| 13269 | { |
| 13270 | CAN_CRITICAL_SECTION_ENTER(); |
| 13271 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR12; |
| 13272 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13273 | } |
| 13274 | |
| 13275 | static inline void hri_can_set_TXBCR_CR13_bit(const void *const hw) |
| 13276 | { |
| 13277 | CAN_CRITICAL_SECTION_ENTER(); |
| 13278 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR13; |
| 13279 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13280 | } |
| 13281 | |
| 13282 | static inline bool hri_can_get_TXBCR_CR13_bit(const void *const hw) |
| 13283 | { |
| 13284 | uint32_t tmp; |
| 13285 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13286 | tmp = (tmp & CAN_TXBCR_CR13) >> CAN_TXBCR_CR13_Pos; |
| 13287 | return (bool)tmp; |
| 13288 | } |
| 13289 | |
| 13290 | static inline void hri_can_write_TXBCR_CR13_bit(const void *const hw, bool value) |
| 13291 | { |
| 13292 | uint32_t tmp; |
| 13293 | CAN_CRITICAL_SECTION_ENTER(); |
| 13294 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13295 | tmp &= ~CAN_TXBCR_CR13; |
| 13296 | tmp |= value << CAN_TXBCR_CR13_Pos; |
| 13297 | ((Can *)hw)->TXBCR.reg = tmp; |
| 13298 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13299 | } |
| 13300 | |
| 13301 | static inline void hri_can_clear_TXBCR_CR13_bit(const void *const hw) |
| 13302 | { |
| 13303 | CAN_CRITICAL_SECTION_ENTER(); |
| 13304 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR13; |
| 13305 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13306 | } |
| 13307 | |
| 13308 | static inline void hri_can_toggle_TXBCR_CR13_bit(const void *const hw) |
| 13309 | { |
| 13310 | CAN_CRITICAL_SECTION_ENTER(); |
| 13311 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR13; |
| 13312 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13313 | } |
| 13314 | |
| 13315 | static inline void hri_can_set_TXBCR_CR14_bit(const void *const hw) |
| 13316 | { |
| 13317 | CAN_CRITICAL_SECTION_ENTER(); |
| 13318 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR14; |
| 13319 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13320 | } |
| 13321 | |
| 13322 | static inline bool hri_can_get_TXBCR_CR14_bit(const void *const hw) |
| 13323 | { |
| 13324 | uint32_t tmp; |
| 13325 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13326 | tmp = (tmp & CAN_TXBCR_CR14) >> CAN_TXBCR_CR14_Pos; |
| 13327 | return (bool)tmp; |
| 13328 | } |
| 13329 | |
| 13330 | static inline void hri_can_write_TXBCR_CR14_bit(const void *const hw, bool value) |
| 13331 | { |
| 13332 | uint32_t tmp; |
| 13333 | CAN_CRITICAL_SECTION_ENTER(); |
| 13334 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13335 | tmp &= ~CAN_TXBCR_CR14; |
| 13336 | tmp |= value << CAN_TXBCR_CR14_Pos; |
| 13337 | ((Can *)hw)->TXBCR.reg = tmp; |
| 13338 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13339 | } |
| 13340 | |
| 13341 | static inline void hri_can_clear_TXBCR_CR14_bit(const void *const hw) |
| 13342 | { |
| 13343 | CAN_CRITICAL_SECTION_ENTER(); |
| 13344 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR14; |
| 13345 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13346 | } |
| 13347 | |
| 13348 | static inline void hri_can_toggle_TXBCR_CR14_bit(const void *const hw) |
| 13349 | { |
| 13350 | CAN_CRITICAL_SECTION_ENTER(); |
| 13351 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR14; |
| 13352 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13353 | } |
| 13354 | |
| 13355 | static inline void hri_can_set_TXBCR_CR15_bit(const void *const hw) |
| 13356 | { |
| 13357 | CAN_CRITICAL_SECTION_ENTER(); |
| 13358 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR15; |
| 13359 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13360 | } |
| 13361 | |
| 13362 | static inline bool hri_can_get_TXBCR_CR15_bit(const void *const hw) |
| 13363 | { |
| 13364 | uint32_t tmp; |
| 13365 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13366 | tmp = (tmp & CAN_TXBCR_CR15) >> CAN_TXBCR_CR15_Pos; |
| 13367 | return (bool)tmp; |
| 13368 | } |
| 13369 | |
| 13370 | static inline void hri_can_write_TXBCR_CR15_bit(const void *const hw, bool value) |
| 13371 | { |
| 13372 | uint32_t tmp; |
| 13373 | CAN_CRITICAL_SECTION_ENTER(); |
| 13374 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13375 | tmp &= ~CAN_TXBCR_CR15; |
| 13376 | tmp |= value << CAN_TXBCR_CR15_Pos; |
| 13377 | ((Can *)hw)->TXBCR.reg = tmp; |
| 13378 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13379 | } |
| 13380 | |
| 13381 | static inline void hri_can_clear_TXBCR_CR15_bit(const void *const hw) |
| 13382 | { |
| 13383 | CAN_CRITICAL_SECTION_ENTER(); |
| 13384 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR15; |
| 13385 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13386 | } |
| 13387 | |
| 13388 | static inline void hri_can_toggle_TXBCR_CR15_bit(const void *const hw) |
| 13389 | { |
| 13390 | CAN_CRITICAL_SECTION_ENTER(); |
| 13391 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR15; |
| 13392 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13393 | } |
| 13394 | |
| 13395 | static inline void hri_can_set_TXBCR_CR16_bit(const void *const hw) |
| 13396 | { |
| 13397 | CAN_CRITICAL_SECTION_ENTER(); |
| 13398 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR16; |
| 13399 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13400 | } |
| 13401 | |
| 13402 | static inline bool hri_can_get_TXBCR_CR16_bit(const void *const hw) |
| 13403 | { |
| 13404 | uint32_t tmp; |
| 13405 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13406 | tmp = (tmp & CAN_TXBCR_CR16) >> CAN_TXBCR_CR16_Pos; |
| 13407 | return (bool)tmp; |
| 13408 | } |
| 13409 | |
| 13410 | static inline void hri_can_write_TXBCR_CR16_bit(const void *const hw, bool value) |
| 13411 | { |
| 13412 | uint32_t tmp; |
| 13413 | CAN_CRITICAL_SECTION_ENTER(); |
| 13414 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13415 | tmp &= ~CAN_TXBCR_CR16; |
| 13416 | tmp |= value << CAN_TXBCR_CR16_Pos; |
| 13417 | ((Can *)hw)->TXBCR.reg = tmp; |
| 13418 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13419 | } |
| 13420 | |
| 13421 | static inline void hri_can_clear_TXBCR_CR16_bit(const void *const hw) |
| 13422 | { |
| 13423 | CAN_CRITICAL_SECTION_ENTER(); |
| 13424 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR16; |
| 13425 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13426 | } |
| 13427 | |
| 13428 | static inline void hri_can_toggle_TXBCR_CR16_bit(const void *const hw) |
| 13429 | { |
| 13430 | CAN_CRITICAL_SECTION_ENTER(); |
| 13431 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR16; |
| 13432 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13433 | } |
| 13434 | |
| 13435 | static inline void hri_can_set_TXBCR_CR17_bit(const void *const hw) |
| 13436 | { |
| 13437 | CAN_CRITICAL_SECTION_ENTER(); |
| 13438 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR17; |
| 13439 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13440 | } |
| 13441 | |
| 13442 | static inline bool hri_can_get_TXBCR_CR17_bit(const void *const hw) |
| 13443 | { |
| 13444 | uint32_t tmp; |
| 13445 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13446 | tmp = (tmp & CAN_TXBCR_CR17) >> CAN_TXBCR_CR17_Pos; |
| 13447 | return (bool)tmp; |
| 13448 | } |
| 13449 | |
| 13450 | static inline void hri_can_write_TXBCR_CR17_bit(const void *const hw, bool value) |
| 13451 | { |
| 13452 | uint32_t tmp; |
| 13453 | CAN_CRITICAL_SECTION_ENTER(); |
| 13454 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13455 | tmp &= ~CAN_TXBCR_CR17; |
| 13456 | tmp |= value << CAN_TXBCR_CR17_Pos; |
| 13457 | ((Can *)hw)->TXBCR.reg = tmp; |
| 13458 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13459 | } |
| 13460 | |
| 13461 | static inline void hri_can_clear_TXBCR_CR17_bit(const void *const hw) |
| 13462 | { |
| 13463 | CAN_CRITICAL_SECTION_ENTER(); |
| 13464 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR17; |
| 13465 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13466 | } |
| 13467 | |
| 13468 | static inline void hri_can_toggle_TXBCR_CR17_bit(const void *const hw) |
| 13469 | { |
| 13470 | CAN_CRITICAL_SECTION_ENTER(); |
| 13471 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR17; |
| 13472 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13473 | } |
| 13474 | |
| 13475 | static inline void hri_can_set_TXBCR_CR18_bit(const void *const hw) |
| 13476 | { |
| 13477 | CAN_CRITICAL_SECTION_ENTER(); |
| 13478 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR18; |
| 13479 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13480 | } |
| 13481 | |
| 13482 | static inline bool hri_can_get_TXBCR_CR18_bit(const void *const hw) |
| 13483 | { |
| 13484 | uint32_t tmp; |
| 13485 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13486 | tmp = (tmp & CAN_TXBCR_CR18) >> CAN_TXBCR_CR18_Pos; |
| 13487 | return (bool)tmp; |
| 13488 | } |
| 13489 | |
| 13490 | static inline void hri_can_write_TXBCR_CR18_bit(const void *const hw, bool value) |
| 13491 | { |
| 13492 | uint32_t tmp; |
| 13493 | CAN_CRITICAL_SECTION_ENTER(); |
| 13494 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13495 | tmp &= ~CAN_TXBCR_CR18; |
| 13496 | tmp |= value << CAN_TXBCR_CR18_Pos; |
| 13497 | ((Can *)hw)->TXBCR.reg = tmp; |
| 13498 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13499 | } |
| 13500 | |
| 13501 | static inline void hri_can_clear_TXBCR_CR18_bit(const void *const hw) |
| 13502 | { |
| 13503 | CAN_CRITICAL_SECTION_ENTER(); |
| 13504 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR18; |
| 13505 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13506 | } |
| 13507 | |
| 13508 | static inline void hri_can_toggle_TXBCR_CR18_bit(const void *const hw) |
| 13509 | { |
| 13510 | CAN_CRITICAL_SECTION_ENTER(); |
| 13511 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR18; |
| 13512 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13513 | } |
| 13514 | |
| 13515 | static inline void hri_can_set_TXBCR_CR19_bit(const void *const hw) |
| 13516 | { |
| 13517 | CAN_CRITICAL_SECTION_ENTER(); |
| 13518 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR19; |
| 13519 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13520 | } |
| 13521 | |
| 13522 | static inline bool hri_can_get_TXBCR_CR19_bit(const void *const hw) |
| 13523 | { |
| 13524 | uint32_t tmp; |
| 13525 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13526 | tmp = (tmp & CAN_TXBCR_CR19) >> CAN_TXBCR_CR19_Pos; |
| 13527 | return (bool)tmp; |
| 13528 | } |
| 13529 | |
| 13530 | static inline void hri_can_write_TXBCR_CR19_bit(const void *const hw, bool value) |
| 13531 | { |
| 13532 | uint32_t tmp; |
| 13533 | CAN_CRITICAL_SECTION_ENTER(); |
| 13534 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13535 | tmp &= ~CAN_TXBCR_CR19; |
| 13536 | tmp |= value << CAN_TXBCR_CR19_Pos; |
| 13537 | ((Can *)hw)->TXBCR.reg = tmp; |
| 13538 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13539 | } |
| 13540 | |
| 13541 | static inline void hri_can_clear_TXBCR_CR19_bit(const void *const hw) |
| 13542 | { |
| 13543 | CAN_CRITICAL_SECTION_ENTER(); |
| 13544 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR19; |
| 13545 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13546 | } |
| 13547 | |
| 13548 | static inline void hri_can_toggle_TXBCR_CR19_bit(const void *const hw) |
| 13549 | { |
| 13550 | CAN_CRITICAL_SECTION_ENTER(); |
| 13551 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR19; |
| 13552 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13553 | } |
| 13554 | |
| 13555 | static inline void hri_can_set_TXBCR_CR20_bit(const void *const hw) |
| 13556 | { |
| 13557 | CAN_CRITICAL_SECTION_ENTER(); |
| 13558 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR20; |
| 13559 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13560 | } |
| 13561 | |
| 13562 | static inline bool hri_can_get_TXBCR_CR20_bit(const void *const hw) |
| 13563 | { |
| 13564 | uint32_t tmp; |
| 13565 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13566 | tmp = (tmp & CAN_TXBCR_CR20) >> CAN_TXBCR_CR20_Pos; |
| 13567 | return (bool)tmp; |
| 13568 | } |
| 13569 | |
| 13570 | static inline void hri_can_write_TXBCR_CR20_bit(const void *const hw, bool value) |
| 13571 | { |
| 13572 | uint32_t tmp; |
| 13573 | CAN_CRITICAL_SECTION_ENTER(); |
| 13574 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13575 | tmp &= ~CAN_TXBCR_CR20; |
| 13576 | tmp |= value << CAN_TXBCR_CR20_Pos; |
| 13577 | ((Can *)hw)->TXBCR.reg = tmp; |
| 13578 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13579 | } |
| 13580 | |
| 13581 | static inline void hri_can_clear_TXBCR_CR20_bit(const void *const hw) |
| 13582 | { |
| 13583 | CAN_CRITICAL_SECTION_ENTER(); |
| 13584 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR20; |
| 13585 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13586 | } |
| 13587 | |
| 13588 | static inline void hri_can_toggle_TXBCR_CR20_bit(const void *const hw) |
| 13589 | { |
| 13590 | CAN_CRITICAL_SECTION_ENTER(); |
| 13591 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR20; |
| 13592 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13593 | } |
| 13594 | |
| 13595 | static inline void hri_can_set_TXBCR_CR21_bit(const void *const hw) |
| 13596 | { |
| 13597 | CAN_CRITICAL_SECTION_ENTER(); |
| 13598 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR21; |
| 13599 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13600 | } |
| 13601 | |
| 13602 | static inline bool hri_can_get_TXBCR_CR21_bit(const void *const hw) |
| 13603 | { |
| 13604 | uint32_t tmp; |
| 13605 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13606 | tmp = (tmp & CAN_TXBCR_CR21) >> CAN_TXBCR_CR21_Pos; |
| 13607 | return (bool)tmp; |
| 13608 | } |
| 13609 | |
| 13610 | static inline void hri_can_write_TXBCR_CR21_bit(const void *const hw, bool value) |
| 13611 | { |
| 13612 | uint32_t tmp; |
| 13613 | CAN_CRITICAL_SECTION_ENTER(); |
| 13614 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13615 | tmp &= ~CAN_TXBCR_CR21; |
| 13616 | tmp |= value << CAN_TXBCR_CR21_Pos; |
| 13617 | ((Can *)hw)->TXBCR.reg = tmp; |
| 13618 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13619 | } |
| 13620 | |
| 13621 | static inline void hri_can_clear_TXBCR_CR21_bit(const void *const hw) |
| 13622 | { |
| 13623 | CAN_CRITICAL_SECTION_ENTER(); |
| 13624 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR21; |
| 13625 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13626 | } |
| 13627 | |
| 13628 | static inline void hri_can_toggle_TXBCR_CR21_bit(const void *const hw) |
| 13629 | { |
| 13630 | CAN_CRITICAL_SECTION_ENTER(); |
| 13631 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR21; |
| 13632 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13633 | } |
| 13634 | |
| 13635 | static inline void hri_can_set_TXBCR_CR22_bit(const void *const hw) |
| 13636 | { |
| 13637 | CAN_CRITICAL_SECTION_ENTER(); |
| 13638 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR22; |
| 13639 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13640 | } |
| 13641 | |
| 13642 | static inline bool hri_can_get_TXBCR_CR22_bit(const void *const hw) |
| 13643 | { |
| 13644 | uint32_t tmp; |
| 13645 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13646 | tmp = (tmp & CAN_TXBCR_CR22) >> CAN_TXBCR_CR22_Pos; |
| 13647 | return (bool)tmp; |
| 13648 | } |
| 13649 | |
| 13650 | static inline void hri_can_write_TXBCR_CR22_bit(const void *const hw, bool value) |
| 13651 | { |
| 13652 | uint32_t tmp; |
| 13653 | CAN_CRITICAL_SECTION_ENTER(); |
| 13654 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13655 | tmp &= ~CAN_TXBCR_CR22; |
| 13656 | tmp |= value << CAN_TXBCR_CR22_Pos; |
| 13657 | ((Can *)hw)->TXBCR.reg = tmp; |
| 13658 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13659 | } |
| 13660 | |
| 13661 | static inline void hri_can_clear_TXBCR_CR22_bit(const void *const hw) |
| 13662 | { |
| 13663 | CAN_CRITICAL_SECTION_ENTER(); |
| 13664 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR22; |
| 13665 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13666 | } |
| 13667 | |
| 13668 | static inline void hri_can_toggle_TXBCR_CR22_bit(const void *const hw) |
| 13669 | { |
| 13670 | CAN_CRITICAL_SECTION_ENTER(); |
| 13671 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR22; |
| 13672 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13673 | } |
| 13674 | |
| 13675 | static inline void hri_can_set_TXBCR_CR23_bit(const void *const hw) |
| 13676 | { |
| 13677 | CAN_CRITICAL_SECTION_ENTER(); |
| 13678 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR23; |
| 13679 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13680 | } |
| 13681 | |
| 13682 | static inline bool hri_can_get_TXBCR_CR23_bit(const void *const hw) |
| 13683 | { |
| 13684 | uint32_t tmp; |
| 13685 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13686 | tmp = (tmp & CAN_TXBCR_CR23) >> CAN_TXBCR_CR23_Pos; |
| 13687 | return (bool)tmp; |
| 13688 | } |
| 13689 | |
| 13690 | static inline void hri_can_write_TXBCR_CR23_bit(const void *const hw, bool value) |
| 13691 | { |
| 13692 | uint32_t tmp; |
| 13693 | CAN_CRITICAL_SECTION_ENTER(); |
| 13694 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13695 | tmp &= ~CAN_TXBCR_CR23; |
| 13696 | tmp |= value << CAN_TXBCR_CR23_Pos; |
| 13697 | ((Can *)hw)->TXBCR.reg = tmp; |
| 13698 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13699 | } |
| 13700 | |
| 13701 | static inline void hri_can_clear_TXBCR_CR23_bit(const void *const hw) |
| 13702 | { |
| 13703 | CAN_CRITICAL_SECTION_ENTER(); |
| 13704 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR23; |
| 13705 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13706 | } |
| 13707 | |
| 13708 | static inline void hri_can_toggle_TXBCR_CR23_bit(const void *const hw) |
| 13709 | { |
| 13710 | CAN_CRITICAL_SECTION_ENTER(); |
| 13711 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR23; |
| 13712 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13713 | } |
| 13714 | |
| 13715 | static inline void hri_can_set_TXBCR_CR24_bit(const void *const hw) |
| 13716 | { |
| 13717 | CAN_CRITICAL_SECTION_ENTER(); |
| 13718 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR24; |
| 13719 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13720 | } |
| 13721 | |
| 13722 | static inline bool hri_can_get_TXBCR_CR24_bit(const void *const hw) |
| 13723 | { |
| 13724 | uint32_t tmp; |
| 13725 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13726 | tmp = (tmp & CAN_TXBCR_CR24) >> CAN_TXBCR_CR24_Pos; |
| 13727 | return (bool)tmp; |
| 13728 | } |
| 13729 | |
| 13730 | static inline void hri_can_write_TXBCR_CR24_bit(const void *const hw, bool value) |
| 13731 | { |
| 13732 | uint32_t tmp; |
| 13733 | CAN_CRITICAL_SECTION_ENTER(); |
| 13734 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13735 | tmp &= ~CAN_TXBCR_CR24; |
| 13736 | tmp |= value << CAN_TXBCR_CR24_Pos; |
| 13737 | ((Can *)hw)->TXBCR.reg = tmp; |
| 13738 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13739 | } |
| 13740 | |
| 13741 | static inline void hri_can_clear_TXBCR_CR24_bit(const void *const hw) |
| 13742 | { |
| 13743 | CAN_CRITICAL_SECTION_ENTER(); |
| 13744 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR24; |
| 13745 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13746 | } |
| 13747 | |
| 13748 | static inline void hri_can_toggle_TXBCR_CR24_bit(const void *const hw) |
| 13749 | { |
| 13750 | CAN_CRITICAL_SECTION_ENTER(); |
| 13751 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR24; |
| 13752 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13753 | } |
| 13754 | |
| 13755 | static inline void hri_can_set_TXBCR_CR25_bit(const void *const hw) |
| 13756 | { |
| 13757 | CAN_CRITICAL_SECTION_ENTER(); |
| 13758 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR25; |
| 13759 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13760 | } |
| 13761 | |
| 13762 | static inline bool hri_can_get_TXBCR_CR25_bit(const void *const hw) |
| 13763 | { |
| 13764 | uint32_t tmp; |
| 13765 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13766 | tmp = (tmp & CAN_TXBCR_CR25) >> CAN_TXBCR_CR25_Pos; |
| 13767 | return (bool)tmp; |
| 13768 | } |
| 13769 | |
| 13770 | static inline void hri_can_write_TXBCR_CR25_bit(const void *const hw, bool value) |
| 13771 | { |
| 13772 | uint32_t tmp; |
| 13773 | CAN_CRITICAL_SECTION_ENTER(); |
| 13774 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13775 | tmp &= ~CAN_TXBCR_CR25; |
| 13776 | tmp |= value << CAN_TXBCR_CR25_Pos; |
| 13777 | ((Can *)hw)->TXBCR.reg = tmp; |
| 13778 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13779 | } |
| 13780 | |
| 13781 | static inline void hri_can_clear_TXBCR_CR25_bit(const void *const hw) |
| 13782 | { |
| 13783 | CAN_CRITICAL_SECTION_ENTER(); |
| 13784 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR25; |
| 13785 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13786 | } |
| 13787 | |
| 13788 | static inline void hri_can_toggle_TXBCR_CR25_bit(const void *const hw) |
| 13789 | { |
| 13790 | CAN_CRITICAL_SECTION_ENTER(); |
| 13791 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR25; |
| 13792 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13793 | } |
| 13794 | |
| 13795 | static inline void hri_can_set_TXBCR_CR26_bit(const void *const hw) |
| 13796 | { |
| 13797 | CAN_CRITICAL_SECTION_ENTER(); |
| 13798 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR26; |
| 13799 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13800 | } |
| 13801 | |
| 13802 | static inline bool hri_can_get_TXBCR_CR26_bit(const void *const hw) |
| 13803 | { |
| 13804 | uint32_t tmp; |
| 13805 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13806 | tmp = (tmp & CAN_TXBCR_CR26) >> CAN_TXBCR_CR26_Pos; |
| 13807 | return (bool)tmp; |
| 13808 | } |
| 13809 | |
| 13810 | static inline void hri_can_write_TXBCR_CR26_bit(const void *const hw, bool value) |
| 13811 | { |
| 13812 | uint32_t tmp; |
| 13813 | CAN_CRITICAL_SECTION_ENTER(); |
| 13814 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13815 | tmp &= ~CAN_TXBCR_CR26; |
| 13816 | tmp |= value << CAN_TXBCR_CR26_Pos; |
| 13817 | ((Can *)hw)->TXBCR.reg = tmp; |
| 13818 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13819 | } |
| 13820 | |
| 13821 | static inline void hri_can_clear_TXBCR_CR26_bit(const void *const hw) |
| 13822 | { |
| 13823 | CAN_CRITICAL_SECTION_ENTER(); |
| 13824 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR26; |
| 13825 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13826 | } |
| 13827 | |
| 13828 | static inline void hri_can_toggle_TXBCR_CR26_bit(const void *const hw) |
| 13829 | { |
| 13830 | CAN_CRITICAL_SECTION_ENTER(); |
| 13831 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR26; |
| 13832 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13833 | } |
| 13834 | |
| 13835 | static inline void hri_can_set_TXBCR_CR27_bit(const void *const hw) |
| 13836 | { |
| 13837 | CAN_CRITICAL_SECTION_ENTER(); |
| 13838 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR27; |
| 13839 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13840 | } |
| 13841 | |
| 13842 | static inline bool hri_can_get_TXBCR_CR27_bit(const void *const hw) |
| 13843 | { |
| 13844 | uint32_t tmp; |
| 13845 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13846 | tmp = (tmp & CAN_TXBCR_CR27) >> CAN_TXBCR_CR27_Pos; |
| 13847 | return (bool)tmp; |
| 13848 | } |
| 13849 | |
| 13850 | static inline void hri_can_write_TXBCR_CR27_bit(const void *const hw, bool value) |
| 13851 | { |
| 13852 | uint32_t tmp; |
| 13853 | CAN_CRITICAL_SECTION_ENTER(); |
| 13854 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13855 | tmp &= ~CAN_TXBCR_CR27; |
| 13856 | tmp |= value << CAN_TXBCR_CR27_Pos; |
| 13857 | ((Can *)hw)->TXBCR.reg = tmp; |
| 13858 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13859 | } |
| 13860 | |
| 13861 | static inline void hri_can_clear_TXBCR_CR27_bit(const void *const hw) |
| 13862 | { |
| 13863 | CAN_CRITICAL_SECTION_ENTER(); |
| 13864 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR27; |
| 13865 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13866 | } |
| 13867 | |
| 13868 | static inline void hri_can_toggle_TXBCR_CR27_bit(const void *const hw) |
| 13869 | { |
| 13870 | CAN_CRITICAL_SECTION_ENTER(); |
| 13871 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR27; |
| 13872 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13873 | } |
| 13874 | |
| 13875 | static inline void hri_can_set_TXBCR_CR28_bit(const void *const hw) |
| 13876 | { |
| 13877 | CAN_CRITICAL_SECTION_ENTER(); |
| 13878 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR28; |
| 13879 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13880 | } |
| 13881 | |
| 13882 | static inline bool hri_can_get_TXBCR_CR28_bit(const void *const hw) |
| 13883 | { |
| 13884 | uint32_t tmp; |
| 13885 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13886 | tmp = (tmp & CAN_TXBCR_CR28) >> CAN_TXBCR_CR28_Pos; |
| 13887 | return (bool)tmp; |
| 13888 | } |
| 13889 | |
| 13890 | static inline void hri_can_write_TXBCR_CR28_bit(const void *const hw, bool value) |
| 13891 | { |
| 13892 | uint32_t tmp; |
| 13893 | CAN_CRITICAL_SECTION_ENTER(); |
| 13894 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13895 | tmp &= ~CAN_TXBCR_CR28; |
| 13896 | tmp |= value << CAN_TXBCR_CR28_Pos; |
| 13897 | ((Can *)hw)->TXBCR.reg = tmp; |
| 13898 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13899 | } |
| 13900 | |
| 13901 | static inline void hri_can_clear_TXBCR_CR28_bit(const void *const hw) |
| 13902 | { |
| 13903 | CAN_CRITICAL_SECTION_ENTER(); |
| 13904 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR28; |
| 13905 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13906 | } |
| 13907 | |
| 13908 | static inline void hri_can_toggle_TXBCR_CR28_bit(const void *const hw) |
| 13909 | { |
| 13910 | CAN_CRITICAL_SECTION_ENTER(); |
| 13911 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR28; |
| 13912 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13913 | } |
| 13914 | |
| 13915 | static inline void hri_can_set_TXBCR_CR29_bit(const void *const hw) |
| 13916 | { |
| 13917 | CAN_CRITICAL_SECTION_ENTER(); |
| 13918 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR29; |
| 13919 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13920 | } |
| 13921 | |
| 13922 | static inline bool hri_can_get_TXBCR_CR29_bit(const void *const hw) |
| 13923 | { |
| 13924 | uint32_t tmp; |
| 13925 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13926 | tmp = (tmp & CAN_TXBCR_CR29) >> CAN_TXBCR_CR29_Pos; |
| 13927 | return (bool)tmp; |
| 13928 | } |
| 13929 | |
| 13930 | static inline void hri_can_write_TXBCR_CR29_bit(const void *const hw, bool value) |
| 13931 | { |
| 13932 | uint32_t tmp; |
| 13933 | CAN_CRITICAL_SECTION_ENTER(); |
| 13934 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13935 | tmp &= ~CAN_TXBCR_CR29; |
| 13936 | tmp |= value << CAN_TXBCR_CR29_Pos; |
| 13937 | ((Can *)hw)->TXBCR.reg = tmp; |
| 13938 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13939 | } |
| 13940 | |
| 13941 | static inline void hri_can_clear_TXBCR_CR29_bit(const void *const hw) |
| 13942 | { |
| 13943 | CAN_CRITICAL_SECTION_ENTER(); |
| 13944 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR29; |
| 13945 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13946 | } |
| 13947 | |
| 13948 | static inline void hri_can_toggle_TXBCR_CR29_bit(const void *const hw) |
| 13949 | { |
| 13950 | CAN_CRITICAL_SECTION_ENTER(); |
| 13951 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR29; |
| 13952 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13953 | } |
| 13954 | |
| 13955 | static inline void hri_can_set_TXBCR_CR30_bit(const void *const hw) |
| 13956 | { |
| 13957 | CAN_CRITICAL_SECTION_ENTER(); |
| 13958 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR30; |
| 13959 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13960 | } |
| 13961 | |
| 13962 | static inline bool hri_can_get_TXBCR_CR30_bit(const void *const hw) |
| 13963 | { |
| 13964 | uint32_t tmp; |
| 13965 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13966 | tmp = (tmp & CAN_TXBCR_CR30) >> CAN_TXBCR_CR30_Pos; |
| 13967 | return (bool)tmp; |
| 13968 | } |
| 13969 | |
| 13970 | static inline void hri_can_write_TXBCR_CR30_bit(const void *const hw, bool value) |
| 13971 | { |
| 13972 | uint32_t tmp; |
| 13973 | CAN_CRITICAL_SECTION_ENTER(); |
| 13974 | tmp = ((Can *)hw)->TXBCR.reg; |
| 13975 | tmp &= ~CAN_TXBCR_CR30; |
| 13976 | tmp |= value << CAN_TXBCR_CR30_Pos; |
| 13977 | ((Can *)hw)->TXBCR.reg = tmp; |
| 13978 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13979 | } |
| 13980 | |
| 13981 | static inline void hri_can_clear_TXBCR_CR30_bit(const void *const hw) |
| 13982 | { |
| 13983 | CAN_CRITICAL_SECTION_ENTER(); |
| 13984 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR30; |
| 13985 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13986 | } |
| 13987 | |
| 13988 | static inline void hri_can_toggle_TXBCR_CR30_bit(const void *const hw) |
| 13989 | { |
| 13990 | CAN_CRITICAL_SECTION_ENTER(); |
| 13991 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR30; |
| 13992 | CAN_CRITICAL_SECTION_LEAVE(); |
| 13993 | } |
| 13994 | |
| 13995 | static inline void hri_can_set_TXBCR_CR31_bit(const void *const hw) |
| 13996 | { |
| 13997 | CAN_CRITICAL_SECTION_ENTER(); |
| 13998 | ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR31; |
| 13999 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14000 | } |
| 14001 | |
| 14002 | static inline bool hri_can_get_TXBCR_CR31_bit(const void *const hw) |
| 14003 | { |
| 14004 | uint32_t tmp; |
| 14005 | tmp = ((Can *)hw)->TXBCR.reg; |
| 14006 | tmp = (tmp & CAN_TXBCR_CR31) >> CAN_TXBCR_CR31_Pos; |
| 14007 | return (bool)tmp; |
| 14008 | } |
| 14009 | |
| 14010 | static inline void hri_can_write_TXBCR_CR31_bit(const void *const hw, bool value) |
| 14011 | { |
| 14012 | uint32_t tmp; |
| 14013 | CAN_CRITICAL_SECTION_ENTER(); |
| 14014 | tmp = ((Can *)hw)->TXBCR.reg; |
| 14015 | tmp &= ~CAN_TXBCR_CR31; |
| 14016 | tmp |= value << CAN_TXBCR_CR31_Pos; |
| 14017 | ((Can *)hw)->TXBCR.reg = tmp; |
| 14018 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14019 | } |
| 14020 | |
| 14021 | static inline void hri_can_clear_TXBCR_CR31_bit(const void *const hw) |
| 14022 | { |
| 14023 | CAN_CRITICAL_SECTION_ENTER(); |
| 14024 | ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR31; |
| 14025 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14026 | } |
| 14027 | |
| 14028 | static inline void hri_can_toggle_TXBCR_CR31_bit(const void *const hw) |
| 14029 | { |
| 14030 | CAN_CRITICAL_SECTION_ENTER(); |
| 14031 | ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR31; |
| 14032 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14033 | } |
| 14034 | |
| 14035 | static inline void hri_can_set_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) |
| 14036 | { |
| 14037 | CAN_CRITICAL_SECTION_ENTER(); |
| 14038 | ((Can *)hw)->TXBCR.reg |= mask; |
| 14039 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14040 | } |
| 14041 | |
| 14042 | static inline hri_can_txbcr_reg_t hri_can_get_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) |
| 14043 | { |
| 14044 | uint32_t tmp; |
| 14045 | tmp = ((Can *)hw)->TXBCR.reg; |
| 14046 | tmp &= mask; |
| 14047 | return tmp; |
| 14048 | } |
| 14049 | |
| 14050 | static inline void hri_can_write_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t data) |
| 14051 | { |
| 14052 | CAN_CRITICAL_SECTION_ENTER(); |
| 14053 | ((Can *)hw)->TXBCR.reg = data; |
| 14054 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14055 | } |
| 14056 | |
| 14057 | static inline void hri_can_clear_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) |
| 14058 | { |
| 14059 | CAN_CRITICAL_SECTION_ENTER(); |
| 14060 | ((Can *)hw)->TXBCR.reg &= ~mask; |
| 14061 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14062 | } |
| 14063 | |
| 14064 | static inline void hri_can_toggle_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) |
| 14065 | { |
| 14066 | CAN_CRITICAL_SECTION_ENTER(); |
| 14067 | ((Can *)hw)->TXBCR.reg ^= mask; |
| 14068 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14069 | } |
| 14070 | |
| 14071 | static inline hri_can_txbcr_reg_t hri_can_read_TXBCR_reg(const void *const hw) |
| 14072 | { |
| 14073 | return ((Can *)hw)->TXBCR.reg; |
| 14074 | } |
| 14075 | |
| 14076 | static inline void hri_can_set_TXBTIE_TIE0_bit(const void *const hw) |
| 14077 | { |
| 14078 | CAN_CRITICAL_SECTION_ENTER(); |
| 14079 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE0; |
| 14080 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14081 | } |
| 14082 | |
| 14083 | static inline bool hri_can_get_TXBTIE_TIE0_bit(const void *const hw) |
| 14084 | { |
| 14085 | uint32_t tmp; |
| 14086 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14087 | tmp = (tmp & CAN_TXBTIE_TIE0) >> CAN_TXBTIE_TIE0_Pos; |
| 14088 | return (bool)tmp; |
| 14089 | } |
| 14090 | |
| 14091 | static inline void hri_can_write_TXBTIE_TIE0_bit(const void *const hw, bool value) |
| 14092 | { |
| 14093 | uint32_t tmp; |
| 14094 | CAN_CRITICAL_SECTION_ENTER(); |
| 14095 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14096 | tmp &= ~CAN_TXBTIE_TIE0; |
| 14097 | tmp |= value << CAN_TXBTIE_TIE0_Pos; |
| 14098 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 14099 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14100 | } |
| 14101 | |
| 14102 | static inline void hri_can_clear_TXBTIE_TIE0_bit(const void *const hw) |
| 14103 | { |
| 14104 | CAN_CRITICAL_SECTION_ENTER(); |
| 14105 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE0; |
| 14106 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14107 | } |
| 14108 | |
| 14109 | static inline void hri_can_toggle_TXBTIE_TIE0_bit(const void *const hw) |
| 14110 | { |
| 14111 | CAN_CRITICAL_SECTION_ENTER(); |
| 14112 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE0; |
| 14113 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14114 | } |
| 14115 | |
| 14116 | static inline void hri_can_set_TXBTIE_TIE1_bit(const void *const hw) |
| 14117 | { |
| 14118 | CAN_CRITICAL_SECTION_ENTER(); |
| 14119 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE1; |
| 14120 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14121 | } |
| 14122 | |
| 14123 | static inline bool hri_can_get_TXBTIE_TIE1_bit(const void *const hw) |
| 14124 | { |
| 14125 | uint32_t tmp; |
| 14126 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14127 | tmp = (tmp & CAN_TXBTIE_TIE1) >> CAN_TXBTIE_TIE1_Pos; |
| 14128 | return (bool)tmp; |
| 14129 | } |
| 14130 | |
| 14131 | static inline void hri_can_write_TXBTIE_TIE1_bit(const void *const hw, bool value) |
| 14132 | { |
| 14133 | uint32_t tmp; |
| 14134 | CAN_CRITICAL_SECTION_ENTER(); |
| 14135 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14136 | tmp &= ~CAN_TXBTIE_TIE1; |
| 14137 | tmp |= value << CAN_TXBTIE_TIE1_Pos; |
| 14138 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 14139 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14140 | } |
| 14141 | |
| 14142 | static inline void hri_can_clear_TXBTIE_TIE1_bit(const void *const hw) |
| 14143 | { |
| 14144 | CAN_CRITICAL_SECTION_ENTER(); |
| 14145 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE1; |
| 14146 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14147 | } |
| 14148 | |
| 14149 | static inline void hri_can_toggle_TXBTIE_TIE1_bit(const void *const hw) |
| 14150 | { |
| 14151 | CAN_CRITICAL_SECTION_ENTER(); |
| 14152 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE1; |
| 14153 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14154 | } |
| 14155 | |
| 14156 | static inline void hri_can_set_TXBTIE_TIE2_bit(const void *const hw) |
| 14157 | { |
| 14158 | CAN_CRITICAL_SECTION_ENTER(); |
| 14159 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE2; |
| 14160 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14161 | } |
| 14162 | |
| 14163 | static inline bool hri_can_get_TXBTIE_TIE2_bit(const void *const hw) |
| 14164 | { |
| 14165 | uint32_t tmp; |
| 14166 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14167 | tmp = (tmp & CAN_TXBTIE_TIE2) >> CAN_TXBTIE_TIE2_Pos; |
| 14168 | return (bool)tmp; |
| 14169 | } |
| 14170 | |
| 14171 | static inline void hri_can_write_TXBTIE_TIE2_bit(const void *const hw, bool value) |
| 14172 | { |
| 14173 | uint32_t tmp; |
| 14174 | CAN_CRITICAL_SECTION_ENTER(); |
| 14175 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14176 | tmp &= ~CAN_TXBTIE_TIE2; |
| 14177 | tmp |= value << CAN_TXBTIE_TIE2_Pos; |
| 14178 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 14179 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14180 | } |
| 14181 | |
| 14182 | static inline void hri_can_clear_TXBTIE_TIE2_bit(const void *const hw) |
| 14183 | { |
| 14184 | CAN_CRITICAL_SECTION_ENTER(); |
| 14185 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE2; |
| 14186 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14187 | } |
| 14188 | |
| 14189 | static inline void hri_can_toggle_TXBTIE_TIE2_bit(const void *const hw) |
| 14190 | { |
| 14191 | CAN_CRITICAL_SECTION_ENTER(); |
| 14192 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE2; |
| 14193 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14194 | } |
| 14195 | |
| 14196 | static inline void hri_can_set_TXBTIE_TIE3_bit(const void *const hw) |
| 14197 | { |
| 14198 | CAN_CRITICAL_SECTION_ENTER(); |
| 14199 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE3; |
| 14200 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14201 | } |
| 14202 | |
| 14203 | static inline bool hri_can_get_TXBTIE_TIE3_bit(const void *const hw) |
| 14204 | { |
| 14205 | uint32_t tmp; |
| 14206 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14207 | tmp = (tmp & CAN_TXBTIE_TIE3) >> CAN_TXBTIE_TIE3_Pos; |
| 14208 | return (bool)tmp; |
| 14209 | } |
| 14210 | |
| 14211 | static inline void hri_can_write_TXBTIE_TIE3_bit(const void *const hw, bool value) |
| 14212 | { |
| 14213 | uint32_t tmp; |
| 14214 | CAN_CRITICAL_SECTION_ENTER(); |
| 14215 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14216 | tmp &= ~CAN_TXBTIE_TIE3; |
| 14217 | tmp |= value << CAN_TXBTIE_TIE3_Pos; |
| 14218 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 14219 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14220 | } |
| 14221 | |
| 14222 | static inline void hri_can_clear_TXBTIE_TIE3_bit(const void *const hw) |
| 14223 | { |
| 14224 | CAN_CRITICAL_SECTION_ENTER(); |
| 14225 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE3; |
| 14226 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14227 | } |
| 14228 | |
| 14229 | static inline void hri_can_toggle_TXBTIE_TIE3_bit(const void *const hw) |
| 14230 | { |
| 14231 | CAN_CRITICAL_SECTION_ENTER(); |
| 14232 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE3; |
| 14233 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14234 | } |
| 14235 | |
| 14236 | static inline void hri_can_set_TXBTIE_TIE4_bit(const void *const hw) |
| 14237 | { |
| 14238 | CAN_CRITICAL_SECTION_ENTER(); |
| 14239 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE4; |
| 14240 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14241 | } |
| 14242 | |
| 14243 | static inline bool hri_can_get_TXBTIE_TIE4_bit(const void *const hw) |
| 14244 | { |
| 14245 | uint32_t tmp; |
| 14246 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14247 | tmp = (tmp & CAN_TXBTIE_TIE4) >> CAN_TXBTIE_TIE4_Pos; |
| 14248 | return (bool)tmp; |
| 14249 | } |
| 14250 | |
| 14251 | static inline void hri_can_write_TXBTIE_TIE4_bit(const void *const hw, bool value) |
| 14252 | { |
| 14253 | uint32_t tmp; |
| 14254 | CAN_CRITICAL_SECTION_ENTER(); |
| 14255 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14256 | tmp &= ~CAN_TXBTIE_TIE4; |
| 14257 | tmp |= value << CAN_TXBTIE_TIE4_Pos; |
| 14258 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 14259 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14260 | } |
| 14261 | |
| 14262 | static inline void hri_can_clear_TXBTIE_TIE4_bit(const void *const hw) |
| 14263 | { |
| 14264 | CAN_CRITICAL_SECTION_ENTER(); |
| 14265 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE4; |
| 14266 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14267 | } |
| 14268 | |
| 14269 | static inline void hri_can_toggle_TXBTIE_TIE4_bit(const void *const hw) |
| 14270 | { |
| 14271 | CAN_CRITICAL_SECTION_ENTER(); |
| 14272 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE4; |
| 14273 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14274 | } |
| 14275 | |
| 14276 | static inline void hri_can_set_TXBTIE_TIE5_bit(const void *const hw) |
| 14277 | { |
| 14278 | CAN_CRITICAL_SECTION_ENTER(); |
| 14279 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE5; |
| 14280 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14281 | } |
| 14282 | |
| 14283 | static inline bool hri_can_get_TXBTIE_TIE5_bit(const void *const hw) |
| 14284 | { |
| 14285 | uint32_t tmp; |
| 14286 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14287 | tmp = (tmp & CAN_TXBTIE_TIE5) >> CAN_TXBTIE_TIE5_Pos; |
| 14288 | return (bool)tmp; |
| 14289 | } |
| 14290 | |
| 14291 | static inline void hri_can_write_TXBTIE_TIE5_bit(const void *const hw, bool value) |
| 14292 | { |
| 14293 | uint32_t tmp; |
| 14294 | CAN_CRITICAL_SECTION_ENTER(); |
| 14295 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14296 | tmp &= ~CAN_TXBTIE_TIE5; |
| 14297 | tmp |= value << CAN_TXBTIE_TIE5_Pos; |
| 14298 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 14299 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14300 | } |
| 14301 | |
| 14302 | static inline void hri_can_clear_TXBTIE_TIE5_bit(const void *const hw) |
| 14303 | { |
| 14304 | CAN_CRITICAL_SECTION_ENTER(); |
| 14305 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE5; |
| 14306 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14307 | } |
| 14308 | |
| 14309 | static inline void hri_can_toggle_TXBTIE_TIE5_bit(const void *const hw) |
| 14310 | { |
| 14311 | CAN_CRITICAL_SECTION_ENTER(); |
| 14312 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE5; |
| 14313 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14314 | } |
| 14315 | |
| 14316 | static inline void hri_can_set_TXBTIE_TIE6_bit(const void *const hw) |
| 14317 | { |
| 14318 | CAN_CRITICAL_SECTION_ENTER(); |
| 14319 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE6; |
| 14320 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14321 | } |
| 14322 | |
| 14323 | static inline bool hri_can_get_TXBTIE_TIE6_bit(const void *const hw) |
| 14324 | { |
| 14325 | uint32_t tmp; |
| 14326 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14327 | tmp = (tmp & CAN_TXBTIE_TIE6) >> CAN_TXBTIE_TIE6_Pos; |
| 14328 | return (bool)tmp; |
| 14329 | } |
| 14330 | |
| 14331 | static inline void hri_can_write_TXBTIE_TIE6_bit(const void *const hw, bool value) |
| 14332 | { |
| 14333 | uint32_t tmp; |
| 14334 | CAN_CRITICAL_SECTION_ENTER(); |
| 14335 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14336 | tmp &= ~CAN_TXBTIE_TIE6; |
| 14337 | tmp |= value << CAN_TXBTIE_TIE6_Pos; |
| 14338 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 14339 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14340 | } |
| 14341 | |
| 14342 | static inline void hri_can_clear_TXBTIE_TIE6_bit(const void *const hw) |
| 14343 | { |
| 14344 | CAN_CRITICAL_SECTION_ENTER(); |
| 14345 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE6; |
| 14346 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14347 | } |
| 14348 | |
| 14349 | static inline void hri_can_toggle_TXBTIE_TIE6_bit(const void *const hw) |
| 14350 | { |
| 14351 | CAN_CRITICAL_SECTION_ENTER(); |
| 14352 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE6; |
| 14353 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14354 | } |
| 14355 | |
| 14356 | static inline void hri_can_set_TXBTIE_TIE7_bit(const void *const hw) |
| 14357 | { |
| 14358 | CAN_CRITICAL_SECTION_ENTER(); |
| 14359 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE7; |
| 14360 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14361 | } |
| 14362 | |
| 14363 | static inline bool hri_can_get_TXBTIE_TIE7_bit(const void *const hw) |
| 14364 | { |
| 14365 | uint32_t tmp; |
| 14366 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14367 | tmp = (tmp & CAN_TXBTIE_TIE7) >> CAN_TXBTIE_TIE7_Pos; |
| 14368 | return (bool)tmp; |
| 14369 | } |
| 14370 | |
| 14371 | static inline void hri_can_write_TXBTIE_TIE7_bit(const void *const hw, bool value) |
| 14372 | { |
| 14373 | uint32_t tmp; |
| 14374 | CAN_CRITICAL_SECTION_ENTER(); |
| 14375 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14376 | tmp &= ~CAN_TXBTIE_TIE7; |
| 14377 | tmp |= value << CAN_TXBTIE_TIE7_Pos; |
| 14378 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 14379 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14380 | } |
| 14381 | |
| 14382 | static inline void hri_can_clear_TXBTIE_TIE7_bit(const void *const hw) |
| 14383 | { |
| 14384 | CAN_CRITICAL_SECTION_ENTER(); |
| 14385 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE7; |
| 14386 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14387 | } |
| 14388 | |
| 14389 | static inline void hri_can_toggle_TXBTIE_TIE7_bit(const void *const hw) |
| 14390 | { |
| 14391 | CAN_CRITICAL_SECTION_ENTER(); |
| 14392 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE7; |
| 14393 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14394 | } |
| 14395 | |
| 14396 | static inline void hri_can_set_TXBTIE_TIE8_bit(const void *const hw) |
| 14397 | { |
| 14398 | CAN_CRITICAL_SECTION_ENTER(); |
| 14399 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE8; |
| 14400 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14401 | } |
| 14402 | |
| 14403 | static inline bool hri_can_get_TXBTIE_TIE8_bit(const void *const hw) |
| 14404 | { |
| 14405 | uint32_t tmp; |
| 14406 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14407 | tmp = (tmp & CAN_TXBTIE_TIE8) >> CAN_TXBTIE_TIE8_Pos; |
| 14408 | return (bool)tmp; |
| 14409 | } |
| 14410 | |
| 14411 | static inline void hri_can_write_TXBTIE_TIE8_bit(const void *const hw, bool value) |
| 14412 | { |
| 14413 | uint32_t tmp; |
| 14414 | CAN_CRITICAL_SECTION_ENTER(); |
| 14415 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14416 | tmp &= ~CAN_TXBTIE_TIE8; |
| 14417 | tmp |= value << CAN_TXBTIE_TIE8_Pos; |
| 14418 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 14419 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14420 | } |
| 14421 | |
| 14422 | static inline void hri_can_clear_TXBTIE_TIE8_bit(const void *const hw) |
| 14423 | { |
| 14424 | CAN_CRITICAL_SECTION_ENTER(); |
| 14425 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE8; |
| 14426 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14427 | } |
| 14428 | |
| 14429 | static inline void hri_can_toggle_TXBTIE_TIE8_bit(const void *const hw) |
| 14430 | { |
| 14431 | CAN_CRITICAL_SECTION_ENTER(); |
| 14432 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE8; |
| 14433 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14434 | } |
| 14435 | |
| 14436 | static inline void hri_can_set_TXBTIE_TIE9_bit(const void *const hw) |
| 14437 | { |
| 14438 | CAN_CRITICAL_SECTION_ENTER(); |
| 14439 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE9; |
| 14440 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14441 | } |
| 14442 | |
| 14443 | static inline bool hri_can_get_TXBTIE_TIE9_bit(const void *const hw) |
| 14444 | { |
| 14445 | uint32_t tmp; |
| 14446 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14447 | tmp = (tmp & CAN_TXBTIE_TIE9) >> CAN_TXBTIE_TIE9_Pos; |
| 14448 | return (bool)tmp; |
| 14449 | } |
| 14450 | |
| 14451 | static inline void hri_can_write_TXBTIE_TIE9_bit(const void *const hw, bool value) |
| 14452 | { |
| 14453 | uint32_t tmp; |
| 14454 | CAN_CRITICAL_SECTION_ENTER(); |
| 14455 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14456 | tmp &= ~CAN_TXBTIE_TIE9; |
| 14457 | tmp |= value << CAN_TXBTIE_TIE9_Pos; |
| 14458 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 14459 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14460 | } |
| 14461 | |
| 14462 | static inline void hri_can_clear_TXBTIE_TIE9_bit(const void *const hw) |
| 14463 | { |
| 14464 | CAN_CRITICAL_SECTION_ENTER(); |
| 14465 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE9; |
| 14466 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14467 | } |
| 14468 | |
| 14469 | static inline void hri_can_toggle_TXBTIE_TIE9_bit(const void *const hw) |
| 14470 | { |
| 14471 | CAN_CRITICAL_SECTION_ENTER(); |
| 14472 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE9; |
| 14473 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14474 | } |
| 14475 | |
| 14476 | static inline void hri_can_set_TXBTIE_TIE10_bit(const void *const hw) |
| 14477 | { |
| 14478 | CAN_CRITICAL_SECTION_ENTER(); |
| 14479 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE10; |
| 14480 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14481 | } |
| 14482 | |
| 14483 | static inline bool hri_can_get_TXBTIE_TIE10_bit(const void *const hw) |
| 14484 | { |
| 14485 | uint32_t tmp; |
| 14486 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14487 | tmp = (tmp & CAN_TXBTIE_TIE10) >> CAN_TXBTIE_TIE10_Pos; |
| 14488 | return (bool)tmp; |
| 14489 | } |
| 14490 | |
| 14491 | static inline void hri_can_write_TXBTIE_TIE10_bit(const void *const hw, bool value) |
| 14492 | { |
| 14493 | uint32_t tmp; |
| 14494 | CAN_CRITICAL_SECTION_ENTER(); |
| 14495 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14496 | tmp &= ~CAN_TXBTIE_TIE10; |
| 14497 | tmp |= value << CAN_TXBTIE_TIE10_Pos; |
| 14498 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 14499 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14500 | } |
| 14501 | |
| 14502 | static inline void hri_can_clear_TXBTIE_TIE10_bit(const void *const hw) |
| 14503 | { |
| 14504 | CAN_CRITICAL_SECTION_ENTER(); |
| 14505 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE10; |
| 14506 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14507 | } |
| 14508 | |
| 14509 | static inline void hri_can_toggle_TXBTIE_TIE10_bit(const void *const hw) |
| 14510 | { |
| 14511 | CAN_CRITICAL_SECTION_ENTER(); |
| 14512 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE10; |
| 14513 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14514 | } |
| 14515 | |
| 14516 | static inline void hri_can_set_TXBTIE_TIE11_bit(const void *const hw) |
| 14517 | { |
| 14518 | CAN_CRITICAL_SECTION_ENTER(); |
| 14519 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE11; |
| 14520 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14521 | } |
| 14522 | |
| 14523 | static inline bool hri_can_get_TXBTIE_TIE11_bit(const void *const hw) |
| 14524 | { |
| 14525 | uint32_t tmp; |
| 14526 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14527 | tmp = (tmp & CAN_TXBTIE_TIE11) >> CAN_TXBTIE_TIE11_Pos; |
| 14528 | return (bool)tmp; |
| 14529 | } |
| 14530 | |
| 14531 | static inline void hri_can_write_TXBTIE_TIE11_bit(const void *const hw, bool value) |
| 14532 | { |
| 14533 | uint32_t tmp; |
| 14534 | CAN_CRITICAL_SECTION_ENTER(); |
| 14535 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14536 | tmp &= ~CAN_TXBTIE_TIE11; |
| 14537 | tmp |= value << CAN_TXBTIE_TIE11_Pos; |
| 14538 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 14539 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14540 | } |
| 14541 | |
| 14542 | static inline void hri_can_clear_TXBTIE_TIE11_bit(const void *const hw) |
| 14543 | { |
| 14544 | CAN_CRITICAL_SECTION_ENTER(); |
| 14545 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE11; |
| 14546 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14547 | } |
| 14548 | |
| 14549 | static inline void hri_can_toggle_TXBTIE_TIE11_bit(const void *const hw) |
| 14550 | { |
| 14551 | CAN_CRITICAL_SECTION_ENTER(); |
| 14552 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE11; |
| 14553 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14554 | } |
| 14555 | |
| 14556 | static inline void hri_can_set_TXBTIE_TIE12_bit(const void *const hw) |
| 14557 | { |
| 14558 | CAN_CRITICAL_SECTION_ENTER(); |
| 14559 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE12; |
| 14560 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14561 | } |
| 14562 | |
| 14563 | static inline bool hri_can_get_TXBTIE_TIE12_bit(const void *const hw) |
| 14564 | { |
| 14565 | uint32_t tmp; |
| 14566 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14567 | tmp = (tmp & CAN_TXBTIE_TIE12) >> CAN_TXBTIE_TIE12_Pos; |
| 14568 | return (bool)tmp; |
| 14569 | } |
| 14570 | |
| 14571 | static inline void hri_can_write_TXBTIE_TIE12_bit(const void *const hw, bool value) |
| 14572 | { |
| 14573 | uint32_t tmp; |
| 14574 | CAN_CRITICAL_SECTION_ENTER(); |
| 14575 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14576 | tmp &= ~CAN_TXBTIE_TIE12; |
| 14577 | tmp |= value << CAN_TXBTIE_TIE12_Pos; |
| 14578 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 14579 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14580 | } |
| 14581 | |
| 14582 | static inline void hri_can_clear_TXBTIE_TIE12_bit(const void *const hw) |
| 14583 | { |
| 14584 | CAN_CRITICAL_SECTION_ENTER(); |
| 14585 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE12; |
| 14586 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14587 | } |
| 14588 | |
| 14589 | static inline void hri_can_toggle_TXBTIE_TIE12_bit(const void *const hw) |
| 14590 | { |
| 14591 | CAN_CRITICAL_SECTION_ENTER(); |
| 14592 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE12; |
| 14593 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14594 | } |
| 14595 | |
| 14596 | static inline void hri_can_set_TXBTIE_TIE13_bit(const void *const hw) |
| 14597 | { |
| 14598 | CAN_CRITICAL_SECTION_ENTER(); |
| 14599 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE13; |
| 14600 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14601 | } |
| 14602 | |
| 14603 | static inline bool hri_can_get_TXBTIE_TIE13_bit(const void *const hw) |
| 14604 | { |
| 14605 | uint32_t tmp; |
| 14606 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14607 | tmp = (tmp & CAN_TXBTIE_TIE13) >> CAN_TXBTIE_TIE13_Pos; |
| 14608 | return (bool)tmp; |
| 14609 | } |
| 14610 | |
| 14611 | static inline void hri_can_write_TXBTIE_TIE13_bit(const void *const hw, bool value) |
| 14612 | { |
| 14613 | uint32_t tmp; |
| 14614 | CAN_CRITICAL_SECTION_ENTER(); |
| 14615 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14616 | tmp &= ~CAN_TXBTIE_TIE13; |
| 14617 | tmp |= value << CAN_TXBTIE_TIE13_Pos; |
| 14618 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 14619 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14620 | } |
| 14621 | |
| 14622 | static inline void hri_can_clear_TXBTIE_TIE13_bit(const void *const hw) |
| 14623 | { |
| 14624 | CAN_CRITICAL_SECTION_ENTER(); |
| 14625 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE13; |
| 14626 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14627 | } |
| 14628 | |
| 14629 | static inline void hri_can_toggle_TXBTIE_TIE13_bit(const void *const hw) |
| 14630 | { |
| 14631 | CAN_CRITICAL_SECTION_ENTER(); |
| 14632 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE13; |
| 14633 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14634 | } |
| 14635 | |
| 14636 | static inline void hri_can_set_TXBTIE_TIE14_bit(const void *const hw) |
| 14637 | { |
| 14638 | CAN_CRITICAL_SECTION_ENTER(); |
| 14639 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE14; |
| 14640 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14641 | } |
| 14642 | |
| 14643 | static inline bool hri_can_get_TXBTIE_TIE14_bit(const void *const hw) |
| 14644 | { |
| 14645 | uint32_t tmp; |
| 14646 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14647 | tmp = (tmp & CAN_TXBTIE_TIE14) >> CAN_TXBTIE_TIE14_Pos; |
| 14648 | return (bool)tmp; |
| 14649 | } |
| 14650 | |
| 14651 | static inline void hri_can_write_TXBTIE_TIE14_bit(const void *const hw, bool value) |
| 14652 | { |
| 14653 | uint32_t tmp; |
| 14654 | CAN_CRITICAL_SECTION_ENTER(); |
| 14655 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14656 | tmp &= ~CAN_TXBTIE_TIE14; |
| 14657 | tmp |= value << CAN_TXBTIE_TIE14_Pos; |
| 14658 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 14659 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14660 | } |
| 14661 | |
| 14662 | static inline void hri_can_clear_TXBTIE_TIE14_bit(const void *const hw) |
| 14663 | { |
| 14664 | CAN_CRITICAL_SECTION_ENTER(); |
| 14665 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE14; |
| 14666 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14667 | } |
| 14668 | |
| 14669 | static inline void hri_can_toggle_TXBTIE_TIE14_bit(const void *const hw) |
| 14670 | { |
| 14671 | CAN_CRITICAL_SECTION_ENTER(); |
| 14672 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE14; |
| 14673 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14674 | } |
| 14675 | |
| 14676 | static inline void hri_can_set_TXBTIE_TIE15_bit(const void *const hw) |
| 14677 | { |
| 14678 | CAN_CRITICAL_SECTION_ENTER(); |
| 14679 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE15; |
| 14680 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14681 | } |
| 14682 | |
| 14683 | static inline bool hri_can_get_TXBTIE_TIE15_bit(const void *const hw) |
| 14684 | { |
| 14685 | uint32_t tmp; |
| 14686 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14687 | tmp = (tmp & CAN_TXBTIE_TIE15) >> CAN_TXBTIE_TIE15_Pos; |
| 14688 | return (bool)tmp; |
| 14689 | } |
| 14690 | |
| 14691 | static inline void hri_can_write_TXBTIE_TIE15_bit(const void *const hw, bool value) |
| 14692 | { |
| 14693 | uint32_t tmp; |
| 14694 | CAN_CRITICAL_SECTION_ENTER(); |
| 14695 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14696 | tmp &= ~CAN_TXBTIE_TIE15; |
| 14697 | tmp |= value << CAN_TXBTIE_TIE15_Pos; |
| 14698 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 14699 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14700 | } |
| 14701 | |
| 14702 | static inline void hri_can_clear_TXBTIE_TIE15_bit(const void *const hw) |
| 14703 | { |
| 14704 | CAN_CRITICAL_SECTION_ENTER(); |
| 14705 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE15; |
| 14706 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14707 | } |
| 14708 | |
| 14709 | static inline void hri_can_toggle_TXBTIE_TIE15_bit(const void *const hw) |
| 14710 | { |
| 14711 | CAN_CRITICAL_SECTION_ENTER(); |
| 14712 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE15; |
| 14713 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14714 | } |
| 14715 | |
| 14716 | static inline void hri_can_set_TXBTIE_TIE16_bit(const void *const hw) |
| 14717 | { |
| 14718 | CAN_CRITICAL_SECTION_ENTER(); |
| 14719 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE16; |
| 14720 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14721 | } |
| 14722 | |
| 14723 | static inline bool hri_can_get_TXBTIE_TIE16_bit(const void *const hw) |
| 14724 | { |
| 14725 | uint32_t tmp; |
| 14726 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14727 | tmp = (tmp & CAN_TXBTIE_TIE16) >> CAN_TXBTIE_TIE16_Pos; |
| 14728 | return (bool)tmp; |
| 14729 | } |
| 14730 | |
| 14731 | static inline void hri_can_write_TXBTIE_TIE16_bit(const void *const hw, bool value) |
| 14732 | { |
| 14733 | uint32_t tmp; |
| 14734 | CAN_CRITICAL_SECTION_ENTER(); |
| 14735 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14736 | tmp &= ~CAN_TXBTIE_TIE16; |
| 14737 | tmp |= value << CAN_TXBTIE_TIE16_Pos; |
| 14738 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 14739 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14740 | } |
| 14741 | |
| 14742 | static inline void hri_can_clear_TXBTIE_TIE16_bit(const void *const hw) |
| 14743 | { |
| 14744 | CAN_CRITICAL_SECTION_ENTER(); |
| 14745 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE16; |
| 14746 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14747 | } |
| 14748 | |
| 14749 | static inline void hri_can_toggle_TXBTIE_TIE16_bit(const void *const hw) |
| 14750 | { |
| 14751 | CAN_CRITICAL_SECTION_ENTER(); |
| 14752 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE16; |
| 14753 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14754 | } |
| 14755 | |
| 14756 | static inline void hri_can_set_TXBTIE_TIE17_bit(const void *const hw) |
| 14757 | { |
| 14758 | CAN_CRITICAL_SECTION_ENTER(); |
| 14759 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE17; |
| 14760 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14761 | } |
| 14762 | |
| 14763 | static inline bool hri_can_get_TXBTIE_TIE17_bit(const void *const hw) |
| 14764 | { |
| 14765 | uint32_t tmp; |
| 14766 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14767 | tmp = (tmp & CAN_TXBTIE_TIE17) >> CAN_TXBTIE_TIE17_Pos; |
| 14768 | return (bool)tmp; |
| 14769 | } |
| 14770 | |
| 14771 | static inline void hri_can_write_TXBTIE_TIE17_bit(const void *const hw, bool value) |
| 14772 | { |
| 14773 | uint32_t tmp; |
| 14774 | CAN_CRITICAL_SECTION_ENTER(); |
| 14775 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14776 | tmp &= ~CAN_TXBTIE_TIE17; |
| 14777 | tmp |= value << CAN_TXBTIE_TIE17_Pos; |
| 14778 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 14779 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14780 | } |
| 14781 | |
| 14782 | static inline void hri_can_clear_TXBTIE_TIE17_bit(const void *const hw) |
| 14783 | { |
| 14784 | CAN_CRITICAL_SECTION_ENTER(); |
| 14785 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE17; |
| 14786 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14787 | } |
| 14788 | |
| 14789 | static inline void hri_can_toggle_TXBTIE_TIE17_bit(const void *const hw) |
| 14790 | { |
| 14791 | CAN_CRITICAL_SECTION_ENTER(); |
| 14792 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE17; |
| 14793 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14794 | } |
| 14795 | |
| 14796 | static inline void hri_can_set_TXBTIE_TIE18_bit(const void *const hw) |
| 14797 | { |
| 14798 | CAN_CRITICAL_SECTION_ENTER(); |
| 14799 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE18; |
| 14800 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14801 | } |
| 14802 | |
| 14803 | static inline bool hri_can_get_TXBTIE_TIE18_bit(const void *const hw) |
| 14804 | { |
| 14805 | uint32_t tmp; |
| 14806 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14807 | tmp = (tmp & CAN_TXBTIE_TIE18) >> CAN_TXBTIE_TIE18_Pos; |
| 14808 | return (bool)tmp; |
| 14809 | } |
| 14810 | |
| 14811 | static inline void hri_can_write_TXBTIE_TIE18_bit(const void *const hw, bool value) |
| 14812 | { |
| 14813 | uint32_t tmp; |
| 14814 | CAN_CRITICAL_SECTION_ENTER(); |
| 14815 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14816 | tmp &= ~CAN_TXBTIE_TIE18; |
| 14817 | tmp |= value << CAN_TXBTIE_TIE18_Pos; |
| 14818 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 14819 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14820 | } |
| 14821 | |
| 14822 | static inline void hri_can_clear_TXBTIE_TIE18_bit(const void *const hw) |
| 14823 | { |
| 14824 | CAN_CRITICAL_SECTION_ENTER(); |
| 14825 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE18; |
| 14826 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14827 | } |
| 14828 | |
| 14829 | static inline void hri_can_toggle_TXBTIE_TIE18_bit(const void *const hw) |
| 14830 | { |
| 14831 | CAN_CRITICAL_SECTION_ENTER(); |
| 14832 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE18; |
| 14833 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14834 | } |
| 14835 | |
| 14836 | static inline void hri_can_set_TXBTIE_TIE19_bit(const void *const hw) |
| 14837 | { |
| 14838 | CAN_CRITICAL_SECTION_ENTER(); |
| 14839 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE19; |
| 14840 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14841 | } |
| 14842 | |
| 14843 | static inline bool hri_can_get_TXBTIE_TIE19_bit(const void *const hw) |
| 14844 | { |
| 14845 | uint32_t tmp; |
| 14846 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14847 | tmp = (tmp & CAN_TXBTIE_TIE19) >> CAN_TXBTIE_TIE19_Pos; |
| 14848 | return (bool)tmp; |
| 14849 | } |
| 14850 | |
| 14851 | static inline void hri_can_write_TXBTIE_TIE19_bit(const void *const hw, bool value) |
| 14852 | { |
| 14853 | uint32_t tmp; |
| 14854 | CAN_CRITICAL_SECTION_ENTER(); |
| 14855 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14856 | tmp &= ~CAN_TXBTIE_TIE19; |
| 14857 | tmp |= value << CAN_TXBTIE_TIE19_Pos; |
| 14858 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 14859 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14860 | } |
| 14861 | |
| 14862 | static inline void hri_can_clear_TXBTIE_TIE19_bit(const void *const hw) |
| 14863 | { |
| 14864 | CAN_CRITICAL_SECTION_ENTER(); |
| 14865 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE19; |
| 14866 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14867 | } |
| 14868 | |
| 14869 | static inline void hri_can_toggle_TXBTIE_TIE19_bit(const void *const hw) |
| 14870 | { |
| 14871 | CAN_CRITICAL_SECTION_ENTER(); |
| 14872 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE19; |
| 14873 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14874 | } |
| 14875 | |
| 14876 | static inline void hri_can_set_TXBTIE_TIE20_bit(const void *const hw) |
| 14877 | { |
| 14878 | CAN_CRITICAL_SECTION_ENTER(); |
| 14879 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE20; |
| 14880 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14881 | } |
| 14882 | |
| 14883 | static inline bool hri_can_get_TXBTIE_TIE20_bit(const void *const hw) |
| 14884 | { |
| 14885 | uint32_t tmp; |
| 14886 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14887 | tmp = (tmp & CAN_TXBTIE_TIE20) >> CAN_TXBTIE_TIE20_Pos; |
| 14888 | return (bool)tmp; |
| 14889 | } |
| 14890 | |
| 14891 | static inline void hri_can_write_TXBTIE_TIE20_bit(const void *const hw, bool value) |
| 14892 | { |
| 14893 | uint32_t tmp; |
| 14894 | CAN_CRITICAL_SECTION_ENTER(); |
| 14895 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14896 | tmp &= ~CAN_TXBTIE_TIE20; |
| 14897 | tmp |= value << CAN_TXBTIE_TIE20_Pos; |
| 14898 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 14899 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14900 | } |
| 14901 | |
| 14902 | static inline void hri_can_clear_TXBTIE_TIE20_bit(const void *const hw) |
| 14903 | { |
| 14904 | CAN_CRITICAL_SECTION_ENTER(); |
| 14905 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE20; |
| 14906 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14907 | } |
| 14908 | |
| 14909 | static inline void hri_can_toggle_TXBTIE_TIE20_bit(const void *const hw) |
| 14910 | { |
| 14911 | CAN_CRITICAL_SECTION_ENTER(); |
| 14912 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE20; |
| 14913 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14914 | } |
| 14915 | |
| 14916 | static inline void hri_can_set_TXBTIE_TIE21_bit(const void *const hw) |
| 14917 | { |
| 14918 | CAN_CRITICAL_SECTION_ENTER(); |
| 14919 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE21; |
| 14920 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14921 | } |
| 14922 | |
| 14923 | static inline bool hri_can_get_TXBTIE_TIE21_bit(const void *const hw) |
| 14924 | { |
| 14925 | uint32_t tmp; |
| 14926 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14927 | tmp = (tmp & CAN_TXBTIE_TIE21) >> CAN_TXBTIE_TIE21_Pos; |
| 14928 | return (bool)tmp; |
| 14929 | } |
| 14930 | |
| 14931 | static inline void hri_can_write_TXBTIE_TIE21_bit(const void *const hw, bool value) |
| 14932 | { |
| 14933 | uint32_t tmp; |
| 14934 | CAN_CRITICAL_SECTION_ENTER(); |
| 14935 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14936 | tmp &= ~CAN_TXBTIE_TIE21; |
| 14937 | tmp |= value << CAN_TXBTIE_TIE21_Pos; |
| 14938 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 14939 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14940 | } |
| 14941 | |
| 14942 | static inline void hri_can_clear_TXBTIE_TIE21_bit(const void *const hw) |
| 14943 | { |
| 14944 | CAN_CRITICAL_SECTION_ENTER(); |
| 14945 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE21; |
| 14946 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14947 | } |
| 14948 | |
| 14949 | static inline void hri_can_toggle_TXBTIE_TIE21_bit(const void *const hw) |
| 14950 | { |
| 14951 | CAN_CRITICAL_SECTION_ENTER(); |
| 14952 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE21; |
| 14953 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14954 | } |
| 14955 | |
| 14956 | static inline void hri_can_set_TXBTIE_TIE22_bit(const void *const hw) |
| 14957 | { |
| 14958 | CAN_CRITICAL_SECTION_ENTER(); |
| 14959 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE22; |
| 14960 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14961 | } |
| 14962 | |
| 14963 | static inline bool hri_can_get_TXBTIE_TIE22_bit(const void *const hw) |
| 14964 | { |
| 14965 | uint32_t tmp; |
| 14966 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14967 | tmp = (tmp & CAN_TXBTIE_TIE22) >> CAN_TXBTIE_TIE22_Pos; |
| 14968 | return (bool)tmp; |
| 14969 | } |
| 14970 | |
| 14971 | static inline void hri_can_write_TXBTIE_TIE22_bit(const void *const hw, bool value) |
| 14972 | { |
| 14973 | uint32_t tmp; |
| 14974 | CAN_CRITICAL_SECTION_ENTER(); |
| 14975 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 14976 | tmp &= ~CAN_TXBTIE_TIE22; |
| 14977 | tmp |= value << CAN_TXBTIE_TIE22_Pos; |
| 14978 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 14979 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14980 | } |
| 14981 | |
| 14982 | static inline void hri_can_clear_TXBTIE_TIE22_bit(const void *const hw) |
| 14983 | { |
| 14984 | CAN_CRITICAL_SECTION_ENTER(); |
| 14985 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE22; |
| 14986 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14987 | } |
| 14988 | |
| 14989 | static inline void hri_can_toggle_TXBTIE_TIE22_bit(const void *const hw) |
| 14990 | { |
| 14991 | CAN_CRITICAL_SECTION_ENTER(); |
| 14992 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE22; |
| 14993 | CAN_CRITICAL_SECTION_LEAVE(); |
| 14994 | } |
| 14995 | |
| 14996 | static inline void hri_can_set_TXBTIE_TIE23_bit(const void *const hw) |
| 14997 | { |
| 14998 | CAN_CRITICAL_SECTION_ENTER(); |
| 14999 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE23; |
| 15000 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15001 | } |
| 15002 | |
| 15003 | static inline bool hri_can_get_TXBTIE_TIE23_bit(const void *const hw) |
| 15004 | { |
| 15005 | uint32_t tmp; |
| 15006 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 15007 | tmp = (tmp & CAN_TXBTIE_TIE23) >> CAN_TXBTIE_TIE23_Pos; |
| 15008 | return (bool)tmp; |
| 15009 | } |
| 15010 | |
| 15011 | static inline void hri_can_write_TXBTIE_TIE23_bit(const void *const hw, bool value) |
| 15012 | { |
| 15013 | uint32_t tmp; |
| 15014 | CAN_CRITICAL_SECTION_ENTER(); |
| 15015 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 15016 | tmp &= ~CAN_TXBTIE_TIE23; |
| 15017 | tmp |= value << CAN_TXBTIE_TIE23_Pos; |
| 15018 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 15019 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15020 | } |
| 15021 | |
| 15022 | static inline void hri_can_clear_TXBTIE_TIE23_bit(const void *const hw) |
| 15023 | { |
| 15024 | CAN_CRITICAL_SECTION_ENTER(); |
| 15025 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE23; |
| 15026 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15027 | } |
| 15028 | |
| 15029 | static inline void hri_can_toggle_TXBTIE_TIE23_bit(const void *const hw) |
| 15030 | { |
| 15031 | CAN_CRITICAL_SECTION_ENTER(); |
| 15032 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE23; |
| 15033 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15034 | } |
| 15035 | |
| 15036 | static inline void hri_can_set_TXBTIE_TIE24_bit(const void *const hw) |
| 15037 | { |
| 15038 | CAN_CRITICAL_SECTION_ENTER(); |
| 15039 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE24; |
| 15040 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15041 | } |
| 15042 | |
| 15043 | static inline bool hri_can_get_TXBTIE_TIE24_bit(const void *const hw) |
| 15044 | { |
| 15045 | uint32_t tmp; |
| 15046 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 15047 | tmp = (tmp & CAN_TXBTIE_TIE24) >> CAN_TXBTIE_TIE24_Pos; |
| 15048 | return (bool)tmp; |
| 15049 | } |
| 15050 | |
| 15051 | static inline void hri_can_write_TXBTIE_TIE24_bit(const void *const hw, bool value) |
| 15052 | { |
| 15053 | uint32_t tmp; |
| 15054 | CAN_CRITICAL_SECTION_ENTER(); |
| 15055 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 15056 | tmp &= ~CAN_TXBTIE_TIE24; |
| 15057 | tmp |= value << CAN_TXBTIE_TIE24_Pos; |
| 15058 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 15059 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15060 | } |
| 15061 | |
| 15062 | static inline void hri_can_clear_TXBTIE_TIE24_bit(const void *const hw) |
| 15063 | { |
| 15064 | CAN_CRITICAL_SECTION_ENTER(); |
| 15065 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE24; |
| 15066 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15067 | } |
| 15068 | |
| 15069 | static inline void hri_can_toggle_TXBTIE_TIE24_bit(const void *const hw) |
| 15070 | { |
| 15071 | CAN_CRITICAL_SECTION_ENTER(); |
| 15072 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE24; |
| 15073 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15074 | } |
| 15075 | |
| 15076 | static inline void hri_can_set_TXBTIE_TIE25_bit(const void *const hw) |
| 15077 | { |
| 15078 | CAN_CRITICAL_SECTION_ENTER(); |
| 15079 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE25; |
| 15080 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15081 | } |
| 15082 | |
| 15083 | static inline bool hri_can_get_TXBTIE_TIE25_bit(const void *const hw) |
| 15084 | { |
| 15085 | uint32_t tmp; |
| 15086 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 15087 | tmp = (tmp & CAN_TXBTIE_TIE25) >> CAN_TXBTIE_TIE25_Pos; |
| 15088 | return (bool)tmp; |
| 15089 | } |
| 15090 | |
| 15091 | static inline void hri_can_write_TXBTIE_TIE25_bit(const void *const hw, bool value) |
| 15092 | { |
| 15093 | uint32_t tmp; |
| 15094 | CAN_CRITICAL_SECTION_ENTER(); |
| 15095 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 15096 | tmp &= ~CAN_TXBTIE_TIE25; |
| 15097 | tmp |= value << CAN_TXBTIE_TIE25_Pos; |
| 15098 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 15099 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15100 | } |
| 15101 | |
| 15102 | static inline void hri_can_clear_TXBTIE_TIE25_bit(const void *const hw) |
| 15103 | { |
| 15104 | CAN_CRITICAL_SECTION_ENTER(); |
| 15105 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE25; |
| 15106 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15107 | } |
| 15108 | |
| 15109 | static inline void hri_can_toggle_TXBTIE_TIE25_bit(const void *const hw) |
| 15110 | { |
| 15111 | CAN_CRITICAL_SECTION_ENTER(); |
| 15112 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE25; |
| 15113 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15114 | } |
| 15115 | |
| 15116 | static inline void hri_can_set_TXBTIE_TIE26_bit(const void *const hw) |
| 15117 | { |
| 15118 | CAN_CRITICAL_SECTION_ENTER(); |
| 15119 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE26; |
| 15120 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15121 | } |
| 15122 | |
| 15123 | static inline bool hri_can_get_TXBTIE_TIE26_bit(const void *const hw) |
| 15124 | { |
| 15125 | uint32_t tmp; |
| 15126 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 15127 | tmp = (tmp & CAN_TXBTIE_TIE26) >> CAN_TXBTIE_TIE26_Pos; |
| 15128 | return (bool)tmp; |
| 15129 | } |
| 15130 | |
| 15131 | static inline void hri_can_write_TXBTIE_TIE26_bit(const void *const hw, bool value) |
| 15132 | { |
| 15133 | uint32_t tmp; |
| 15134 | CAN_CRITICAL_SECTION_ENTER(); |
| 15135 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 15136 | tmp &= ~CAN_TXBTIE_TIE26; |
| 15137 | tmp |= value << CAN_TXBTIE_TIE26_Pos; |
| 15138 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 15139 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15140 | } |
| 15141 | |
| 15142 | static inline void hri_can_clear_TXBTIE_TIE26_bit(const void *const hw) |
| 15143 | { |
| 15144 | CAN_CRITICAL_SECTION_ENTER(); |
| 15145 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE26; |
| 15146 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15147 | } |
| 15148 | |
| 15149 | static inline void hri_can_toggle_TXBTIE_TIE26_bit(const void *const hw) |
| 15150 | { |
| 15151 | CAN_CRITICAL_SECTION_ENTER(); |
| 15152 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE26; |
| 15153 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15154 | } |
| 15155 | |
| 15156 | static inline void hri_can_set_TXBTIE_TIE27_bit(const void *const hw) |
| 15157 | { |
| 15158 | CAN_CRITICAL_SECTION_ENTER(); |
| 15159 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE27; |
| 15160 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15161 | } |
| 15162 | |
| 15163 | static inline bool hri_can_get_TXBTIE_TIE27_bit(const void *const hw) |
| 15164 | { |
| 15165 | uint32_t tmp; |
| 15166 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 15167 | tmp = (tmp & CAN_TXBTIE_TIE27) >> CAN_TXBTIE_TIE27_Pos; |
| 15168 | return (bool)tmp; |
| 15169 | } |
| 15170 | |
| 15171 | static inline void hri_can_write_TXBTIE_TIE27_bit(const void *const hw, bool value) |
| 15172 | { |
| 15173 | uint32_t tmp; |
| 15174 | CAN_CRITICAL_SECTION_ENTER(); |
| 15175 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 15176 | tmp &= ~CAN_TXBTIE_TIE27; |
| 15177 | tmp |= value << CAN_TXBTIE_TIE27_Pos; |
| 15178 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 15179 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15180 | } |
| 15181 | |
| 15182 | static inline void hri_can_clear_TXBTIE_TIE27_bit(const void *const hw) |
| 15183 | { |
| 15184 | CAN_CRITICAL_SECTION_ENTER(); |
| 15185 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE27; |
| 15186 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15187 | } |
| 15188 | |
| 15189 | static inline void hri_can_toggle_TXBTIE_TIE27_bit(const void *const hw) |
| 15190 | { |
| 15191 | CAN_CRITICAL_SECTION_ENTER(); |
| 15192 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE27; |
| 15193 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15194 | } |
| 15195 | |
| 15196 | static inline void hri_can_set_TXBTIE_TIE28_bit(const void *const hw) |
| 15197 | { |
| 15198 | CAN_CRITICAL_SECTION_ENTER(); |
| 15199 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE28; |
| 15200 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15201 | } |
| 15202 | |
| 15203 | static inline bool hri_can_get_TXBTIE_TIE28_bit(const void *const hw) |
| 15204 | { |
| 15205 | uint32_t tmp; |
| 15206 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 15207 | tmp = (tmp & CAN_TXBTIE_TIE28) >> CAN_TXBTIE_TIE28_Pos; |
| 15208 | return (bool)tmp; |
| 15209 | } |
| 15210 | |
| 15211 | static inline void hri_can_write_TXBTIE_TIE28_bit(const void *const hw, bool value) |
| 15212 | { |
| 15213 | uint32_t tmp; |
| 15214 | CAN_CRITICAL_SECTION_ENTER(); |
| 15215 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 15216 | tmp &= ~CAN_TXBTIE_TIE28; |
| 15217 | tmp |= value << CAN_TXBTIE_TIE28_Pos; |
| 15218 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 15219 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15220 | } |
| 15221 | |
| 15222 | static inline void hri_can_clear_TXBTIE_TIE28_bit(const void *const hw) |
| 15223 | { |
| 15224 | CAN_CRITICAL_SECTION_ENTER(); |
| 15225 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE28; |
| 15226 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15227 | } |
| 15228 | |
| 15229 | static inline void hri_can_toggle_TXBTIE_TIE28_bit(const void *const hw) |
| 15230 | { |
| 15231 | CAN_CRITICAL_SECTION_ENTER(); |
| 15232 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE28; |
| 15233 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15234 | } |
| 15235 | |
| 15236 | static inline void hri_can_set_TXBTIE_TIE29_bit(const void *const hw) |
| 15237 | { |
| 15238 | CAN_CRITICAL_SECTION_ENTER(); |
| 15239 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE29; |
| 15240 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15241 | } |
| 15242 | |
| 15243 | static inline bool hri_can_get_TXBTIE_TIE29_bit(const void *const hw) |
| 15244 | { |
| 15245 | uint32_t tmp; |
| 15246 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 15247 | tmp = (tmp & CAN_TXBTIE_TIE29) >> CAN_TXBTIE_TIE29_Pos; |
| 15248 | return (bool)tmp; |
| 15249 | } |
| 15250 | |
| 15251 | static inline void hri_can_write_TXBTIE_TIE29_bit(const void *const hw, bool value) |
| 15252 | { |
| 15253 | uint32_t tmp; |
| 15254 | CAN_CRITICAL_SECTION_ENTER(); |
| 15255 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 15256 | tmp &= ~CAN_TXBTIE_TIE29; |
| 15257 | tmp |= value << CAN_TXBTIE_TIE29_Pos; |
| 15258 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 15259 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15260 | } |
| 15261 | |
| 15262 | static inline void hri_can_clear_TXBTIE_TIE29_bit(const void *const hw) |
| 15263 | { |
| 15264 | CAN_CRITICAL_SECTION_ENTER(); |
| 15265 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE29; |
| 15266 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15267 | } |
| 15268 | |
| 15269 | static inline void hri_can_toggle_TXBTIE_TIE29_bit(const void *const hw) |
| 15270 | { |
| 15271 | CAN_CRITICAL_SECTION_ENTER(); |
| 15272 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE29; |
| 15273 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15274 | } |
| 15275 | |
| 15276 | static inline void hri_can_set_TXBTIE_TIE30_bit(const void *const hw) |
| 15277 | { |
| 15278 | CAN_CRITICAL_SECTION_ENTER(); |
| 15279 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE30; |
| 15280 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15281 | } |
| 15282 | |
| 15283 | static inline bool hri_can_get_TXBTIE_TIE30_bit(const void *const hw) |
| 15284 | { |
| 15285 | uint32_t tmp; |
| 15286 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 15287 | tmp = (tmp & CAN_TXBTIE_TIE30) >> CAN_TXBTIE_TIE30_Pos; |
| 15288 | return (bool)tmp; |
| 15289 | } |
| 15290 | |
| 15291 | static inline void hri_can_write_TXBTIE_TIE30_bit(const void *const hw, bool value) |
| 15292 | { |
| 15293 | uint32_t tmp; |
| 15294 | CAN_CRITICAL_SECTION_ENTER(); |
| 15295 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 15296 | tmp &= ~CAN_TXBTIE_TIE30; |
| 15297 | tmp |= value << CAN_TXBTIE_TIE30_Pos; |
| 15298 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 15299 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15300 | } |
| 15301 | |
| 15302 | static inline void hri_can_clear_TXBTIE_TIE30_bit(const void *const hw) |
| 15303 | { |
| 15304 | CAN_CRITICAL_SECTION_ENTER(); |
| 15305 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE30; |
| 15306 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15307 | } |
| 15308 | |
| 15309 | static inline void hri_can_toggle_TXBTIE_TIE30_bit(const void *const hw) |
| 15310 | { |
| 15311 | CAN_CRITICAL_SECTION_ENTER(); |
| 15312 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE30; |
| 15313 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15314 | } |
| 15315 | |
| 15316 | static inline void hri_can_set_TXBTIE_TIE31_bit(const void *const hw) |
| 15317 | { |
| 15318 | CAN_CRITICAL_SECTION_ENTER(); |
| 15319 | ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE31; |
| 15320 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15321 | } |
| 15322 | |
| 15323 | static inline bool hri_can_get_TXBTIE_TIE31_bit(const void *const hw) |
| 15324 | { |
| 15325 | uint32_t tmp; |
| 15326 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 15327 | tmp = (tmp & CAN_TXBTIE_TIE31) >> CAN_TXBTIE_TIE31_Pos; |
| 15328 | return (bool)tmp; |
| 15329 | } |
| 15330 | |
| 15331 | static inline void hri_can_write_TXBTIE_TIE31_bit(const void *const hw, bool value) |
| 15332 | { |
| 15333 | uint32_t tmp; |
| 15334 | CAN_CRITICAL_SECTION_ENTER(); |
| 15335 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 15336 | tmp &= ~CAN_TXBTIE_TIE31; |
| 15337 | tmp |= value << CAN_TXBTIE_TIE31_Pos; |
| 15338 | ((Can *)hw)->TXBTIE.reg = tmp; |
| 15339 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15340 | } |
| 15341 | |
| 15342 | static inline void hri_can_clear_TXBTIE_TIE31_bit(const void *const hw) |
| 15343 | { |
| 15344 | CAN_CRITICAL_SECTION_ENTER(); |
| 15345 | ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE31; |
| 15346 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15347 | } |
| 15348 | |
| 15349 | static inline void hri_can_toggle_TXBTIE_TIE31_bit(const void *const hw) |
| 15350 | { |
| 15351 | CAN_CRITICAL_SECTION_ENTER(); |
| 15352 | ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE31; |
| 15353 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15354 | } |
| 15355 | |
| 15356 | static inline void hri_can_set_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) |
| 15357 | { |
| 15358 | CAN_CRITICAL_SECTION_ENTER(); |
| 15359 | ((Can *)hw)->TXBTIE.reg |= mask; |
| 15360 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15361 | } |
| 15362 | |
| 15363 | static inline hri_can_txbtie_reg_t hri_can_get_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) |
| 15364 | { |
| 15365 | uint32_t tmp; |
| 15366 | tmp = ((Can *)hw)->TXBTIE.reg; |
| 15367 | tmp &= mask; |
| 15368 | return tmp; |
| 15369 | } |
| 15370 | |
| 15371 | static inline void hri_can_write_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t data) |
| 15372 | { |
| 15373 | CAN_CRITICAL_SECTION_ENTER(); |
| 15374 | ((Can *)hw)->TXBTIE.reg = data; |
| 15375 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15376 | } |
| 15377 | |
| 15378 | static inline void hri_can_clear_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) |
| 15379 | { |
| 15380 | CAN_CRITICAL_SECTION_ENTER(); |
| 15381 | ((Can *)hw)->TXBTIE.reg &= ~mask; |
| 15382 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15383 | } |
| 15384 | |
| 15385 | static inline void hri_can_toggle_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) |
| 15386 | { |
| 15387 | CAN_CRITICAL_SECTION_ENTER(); |
| 15388 | ((Can *)hw)->TXBTIE.reg ^= mask; |
| 15389 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15390 | } |
| 15391 | |
| 15392 | static inline hri_can_txbtie_reg_t hri_can_read_TXBTIE_reg(const void *const hw) |
| 15393 | { |
| 15394 | return ((Can *)hw)->TXBTIE.reg; |
| 15395 | } |
| 15396 | |
| 15397 | static inline void hri_can_set_TXBCIE_CFIE0_bit(const void *const hw) |
| 15398 | { |
| 15399 | CAN_CRITICAL_SECTION_ENTER(); |
| 15400 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE0; |
| 15401 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15402 | } |
| 15403 | |
| 15404 | static inline bool hri_can_get_TXBCIE_CFIE0_bit(const void *const hw) |
| 15405 | { |
| 15406 | uint32_t tmp; |
| 15407 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15408 | tmp = (tmp & CAN_TXBCIE_CFIE0) >> CAN_TXBCIE_CFIE0_Pos; |
| 15409 | return (bool)tmp; |
| 15410 | } |
| 15411 | |
| 15412 | static inline void hri_can_write_TXBCIE_CFIE0_bit(const void *const hw, bool value) |
| 15413 | { |
| 15414 | uint32_t tmp; |
| 15415 | CAN_CRITICAL_SECTION_ENTER(); |
| 15416 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15417 | tmp &= ~CAN_TXBCIE_CFIE0; |
| 15418 | tmp |= value << CAN_TXBCIE_CFIE0_Pos; |
| 15419 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 15420 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15421 | } |
| 15422 | |
| 15423 | static inline void hri_can_clear_TXBCIE_CFIE0_bit(const void *const hw) |
| 15424 | { |
| 15425 | CAN_CRITICAL_SECTION_ENTER(); |
| 15426 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE0; |
| 15427 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15428 | } |
| 15429 | |
| 15430 | static inline void hri_can_toggle_TXBCIE_CFIE0_bit(const void *const hw) |
| 15431 | { |
| 15432 | CAN_CRITICAL_SECTION_ENTER(); |
| 15433 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE0; |
| 15434 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15435 | } |
| 15436 | |
| 15437 | static inline void hri_can_set_TXBCIE_CFIE1_bit(const void *const hw) |
| 15438 | { |
| 15439 | CAN_CRITICAL_SECTION_ENTER(); |
| 15440 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE1; |
| 15441 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15442 | } |
| 15443 | |
| 15444 | static inline bool hri_can_get_TXBCIE_CFIE1_bit(const void *const hw) |
| 15445 | { |
| 15446 | uint32_t tmp; |
| 15447 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15448 | tmp = (tmp & CAN_TXBCIE_CFIE1) >> CAN_TXBCIE_CFIE1_Pos; |
| 15449 | return (bool)tmp; |
| 15450 | } |
| 15451 | |
| 15452 | static inline void hri_can_write_TXBCIE_CFIE1_bit(const void *const hw, bool value) |
| 15453 | { |
| 15454 | uint32_t tmp; |
| 15455 | CAN_CRITICAL_SECTION_ENTER(); |
| 15456 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15457 | tmp &= ~CAN_TXBCIE_CFIE1; |
| 15458 | tmp |= value << CAN_TXBCIE_CFIE1_Pos; |
| 15459 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 15460 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15461 | } |
| 15462 | |
| 15463 | static inline void hri_can_clear_TXBCIE_CFIE1_bit(const void *const hw) |
| 15464 | { |
| 15465 | CAN_CRITICAL_SECTION_ENTER(); |
| 15466 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE1; |
| 15467 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15468 | } |
| 15469 | |
| 15470 | static inline void hri_can_toggle_TXBCIE_CFIE1_bit(const void *const hw) |
| 15471 | { |
| 15472 | CAN_CRITICAL_SECTION_ENTER(); |
| 15473 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE1; |
| 15474 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15475 | } |
| 15476 | |
| 15477 | static inline void hri_can_set_TXBCIE_CFIE2_bit(const void *const hw) |
| 15478 | { |
| 15479 | CAN_CRITICAL_SECTION_ENTER(); |
| 15480 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE2; |
| 15481 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15482 | } |
| 15483 | |
| 15484 | static inline bool hri_can_get_TXBCIE_CFIE2_bit(const void *const hw) |
| 15485 | { |
| 15486 | uint32_t tmp; |
| 15487 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15488 | tmp = (tmp & CAN_TXBCIE_CFIE2) >> CAN_TXBCIE_CFIE2_Pos; |
| 15489 | return (bool)tmp; |
| 15490 | } |
| 15491 | |
| 15492 | static inline void hri_can_write_TXBCIE_CFIE2_bit(const void *const hw, bool value) |
| 15493 | { |
| 15494 | uint32_t tmp; |
| 15495 | CAN_CRITICAL_SECTION_ENTER(); |
| 15496 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15497 | tmp &= ~CAN_TXBCIE_CFIE2; |
| 15498 | tmp |= value << CAN_TXBCIE_CFIE2_Pos; |
| 15499 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 15500 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15501 | } |
| 15502 | |
| 15503 | static inline void hri_can_clear_TXBCIE_CFIE2_bit(const void *const hw) |
| 15504 | { |
| 15505 | CAN_CRITICAL_SECTION_ENTER(); |
| 15506 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE2; |
| 15507 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15508 | } |
| 15509 | |
| 15510 | static inline void hri_can_toggle_TXBCIE_CFIE2_bit(const void *const hw) |
| 15511 | { |
| 15512 | CAN_CRITICAL_SECTION_ENTER(); |
| 15513 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE2; |
| 15514 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15515 | } |
| 15516 | |
| 15517 | static inline void hri_can_set_TXBCIE_CFIE3_bit(const void *const hw) |
| 15518 | { |
| 15519 | CAN_CRITICAL_SECTION_ENTER(); |
| 15520 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE3; |
| 15521 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15522 | } |
| 15523 | |
| 15524 | static inline bool hri_can_get_TXBCIE_CFIE3_bit(const void *const hw) |
| 15525 | { |
| 15526 | uint32_t tmp; |
| 15527 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15528 | tmp = (tmp & CAN_TXBCIE_CFIE3) >> CAN_TXBCIE_CFIE3_Pos; |
| 15529 | return (bool)tmp; |
| 15530 | } |
| 15531 | |
| 15532 | static inline void hri_can_write_TXBCIE_CFIE3_bit(const void *const hw, bool value) |
| 15533 | { |
| 15534 | uint32_t tmp; |
| 15535 | CAN_CRITICAL_SECTION_ENTER(); |
| 15536 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15537 | tmp &= ~CAN_TXBCIE_CFIE3; |
| 15538 | tmp |= value << CAN_TXBCIE_CFIE3_Pos; |
| 15539 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 15540 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15541 | } |
| 15542 | |
| 15543 | static inline void hri_can_clear_TXBCIE_CFIE3_bit(const void *const hw) |
| 15544 | { |
| 15545 | CAN_CRITICAL_SECTION_ENTER(); |
| 15546 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE3; |
| 15547 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15548 | } |
| 15549 | |
| 15550 | static inline void hri_can_toggle_TXBCIE_CFIE3_bit(const void *const hw) |
| 15551 | { |
| 15552 | CAN_CRITICAL_SECTION_ENTER(); |
| 15553 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE3; |
| 15554 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15555 | } |
| 15556 | |
| 15557 | static inline void hri_can_set_TXBCIE_CFIE4_bit(const void *const hw) |
| 15558 | { |
| 15559 | CAN_CRITICAL_SECTION_ENTER(); |
| 15560 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE4; |
| 15561 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15562 | } |
| 15563 | |
| 15564 | static inline bool hri_can_get_TXBCIE_CFIE4_bit(const void *const hw) |
| 15565 | { |
| 15566 | uint32_t tmp; |
| 15567 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15568 | tmp = (tmp & CAN_TXBCIE_CFIE4) >> CAN_TXBCIE_CFIE4_Pos; |
| 15569 | return (bool)tmp; |
| 15570 | } |
| 15571 | |
| 15572 | static inline void hri_can_write_TXBCIE_CFIE4_bit(const void *const hw, bool value) |
| 15573 | { |
| 15574 | uint32_t tmp; |
| 15575 | CAN_CRITICAL_SECTION_ENTER(); |
| 15576 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15577 | tmp &= ~CAN_TXBCIE_CFIE4; |
| 15578 | tmp |= value << CAN_TXBCIE_CFIE4_Pos; |
| 15579 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 15580 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15581 | } |
| 15582 | |
| 15583 | static inline void hri_can_clear_TXBCIE_CFIE4_bit(const void *const hw) |
| 15584 | { |
| 15585 | CAN_CRITICAL_SECTION_ENTER(); |
| 15586 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE4; |
| 15587 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15588 | } |
| 15589 | |
| 15590 | static inline void hri_can_toggle_TXBCIE_CFIE4_bit(const void *const hw) |
| 15591 | { |
| 15592 | CAN_CRITICAL_SECTION_ENTER(); |
| 15593 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE4; |
| 15594 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15595 | } |
| 15596 | |
| 15597 | static inline void hri_can_set_TXBCIE_CFIE5_bit(const void *const hw) |
| 15598 | { |
| 15599 | CAN_CRITICAL_SECTION_ENTER(); |
| 15600 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE5; |
| 15601 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15602 | } |
| 15603 | |
| 15604 | static inline bool hri_can_get_TXBCIE_CFIE5_bit(const void *const hw) |
| 15605 | { |
| 15606 | uint32_t tmp; |
| 15607 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15608 | tmp = (tmp & CAN_TXBCIE_CFIE5) >> CAN_TXBCIE_CFIE5_Pos; |
| 15609 | return (bool)tmp; |
| 15610 | } |
| 15611 | |
| 15612 | static inline void hri_can_write_TXBCIE_CFIE5_bit(const void *const hw, bool value) |
| 15613 | { |
| 15614 | uint32_t tmp; |
| 15615 | CAN_CRITICAL_SECTION_ENTER(); |
| 15616 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15617 | tmp &= ~CAN_TXBCIE_CFIE5; |
| 15618 | tmp |= value << CAN_TXBCIE_CFIE5_Pos; |
| 15619 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 15620 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15621 | } |
| 15622 | |
| 15623 | static inline void hri_can_clear_TXBCIE_CFIE5_bit(const void *const hw) |
| 15624 | { |
| 15625 | CAN_CRITICAL_SECTION_ENTER(); |
| 15626 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE5; |
| 15627 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15628 | } |
| 15629 | |
| 15630 | static inline void hri_can_toggle_TXBCIE_CFIE5_bit(const void *const hw) |
| 15631 | { |
| 15632 | CAN_CRITICAL_SECTION_ENTER(); |
| 15633 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE5; |
| 15634 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15635 | } |
| 15636 | |
| 15637 | static inline void hri_can_set_TXBCIE_CFIE6_bit(const void *const hw) |
| 15638 | { |
| 15639 | CAN_CRITICAL_SECTION_ENTER(); |
| 15640 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE6; |
| 15641 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15642 | } |
| 15643 | |
| 15644 | static inline bool hri_can_get_TXBCIE_CFIE6_bit(const void *const hw) |
| 15645 | { |
| 15646 | uint32_t tmp; |
| 15647 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15648 | tmp = (tmp & CAN_TXBCIE_CFIE6) >> CAN_TXBCIE_CFIE6_Pos; |
| 15649 | return (bool)tmp; |
| 15650 | } |
| 15651 | |
| 15652 | static inline void hri_can_write_TXBCIE_CFIE6_bit(const void *const hw, bool value) |
| 15653 | { |
| 15654 | uint32_t tmp; |
| 15655 | CAN_CRITICAL_SECTION_ENTER(); |
| 15656 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15657 | tmp &= ~CAN_TXBCIE_CFIE6; |
| 15658 | tmp |= value << CAN_TXBCIE_CFIE6_Pos; |
| 15659 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 15660 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15661 | } |
| 15662 | |
| 15663 | static inline void hri_can_clear_TXBCIE_CFIE6_bit(const void *const hw) |
| 15664 | { |
| 15665 | CAN_CRITICAL_SECTION_ENTER(); |
| 15666 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE6; |
| 15667 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15668 | } |
| 15669 | |
| 15670 | static inline void hri_can_toggle_TXBCIE_CFIE6_bit(const void *const hw) |
| 15671 | { |
| 15672 | CAN_CRITICAL_SECTION_ENTER(); |
| 15673 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE6; |
| 15674 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15675 | } |
| 15676 | |
| 15677 | static inline void hri_can_set_TXBCIE_CFIE7_bit(const void *const hw) |
| 15678 | { |
| 15679 | CAN_CRITICAL_SECTION_ENTER(); |
| 15680 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE7; |
| 15681 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15682 | } |
| 15683 | |
| 15684 | static inline bool hri_can_get_TXBCIE_CFIE7_bit(const void *const hw) |
| 15685 | { |
| 15686 | uint32_t tmp; |
| 15687 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15688 | tmp = (tmp & CAN_TXBCIE_CFIE7) >> CAN_TXBCIE_CFIE7_Pos; |
| 15689 | return (bool)tmp; |
| 15690 | } |
| 15691 | |
| 15692 | static inline void hri_can_write_TXBCIE_CFIE7_bit(const void *const hw, bool value) |
| 15693 | { |
| 15694 | uint32_t tmp; |
| 15695 | CAN_CRITICAL_SECTION_ENTER(); |
| 15696 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15697 | tmp &= ~CAN_TXBCIE_CFIE7; |
| 15698 | tmp |= value << CAN_TXBCIE_CFIE7_Pos; |
| 15699 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 15700 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15701 | } |
| 15702 | |
| 15703 | static inline void hri_can_clear_TXBCIE_CFIE7_bit(const void *const hw) |
| 15704 | { |
| 15705 | CAN_CRITICAL_SECTION_ENTER(); |
| 15706 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE7; |
| 15707 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15708 | } |
| 15709 | |
| 15710 | static inline void hri_can_toggle_TXBCIE_CFIE7_bit(const void *const hw) |
| 15711 | { |
| 15712 | CAN_CRITICAL_SECTION_ENTER(); |
| 15713 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE7; |
| 15714 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15715 | } |
| 15716 | |
| 15717 | static inline void hri_can_set_TXBCIE_CFIE8_bit(const void *const hw) |
| 15718 | { |
| 15719 | CAN_CRITICAL_SECTION_ENTER(); |
| 15720 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE8; |
| 15721 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15722 | } |
| 15723 | |
| 15724 | static inline bool hri_can_get_TXBCIE_CFIE8_bit(const void *const hw) |
| 15725 | { |
| 15726 | uint32_t tmp; |
| 15727 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15728 | tmp = (tmp & CAN_TXBCIE_CFIE8) >> CAN_TXBCIE_CFIE8_Pos; |
| 15729 | return (bool)tmp; |
| 15730 | } |
| 15731 | |
| 15732 | static inline void hri_can_write_TXBCIE_CFIE8_bit(const void *const hw, bool value) |
| 15733 | { |
| 15734 | uint32_t tmp; |
| 15735 | CAN_CRITICAL_SECTION_ENTER(); |
| 15736 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15737 | tmp &= ~CAN_TXBCIE_CFIE8; |
| 15738 | tmp |= value << CAN_TXBCIE_CFIE8_Pos; |
| 15739 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 15740 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15741 | } |
| 15742 | |
| 15743 | static inline void hri_can_clear_TXBCIE_CFIE8_bit(const void *const hw) |
| 15744 | { |
| 15745 | CAN_CRITICAL_SECTION_ENTER(); |
| 15746 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE8; |
| 15747 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15748 | } |
| 15749 | |
| 15750 | static inline void hri_can_toggle_TXBCIE_CFIE8_bit(const void *const hw) |
| 15751 | { |
| 15752 | CAN_CRITICAL_SECTION_ENTER(); |
| 15753 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE8; |
| 15754 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15755 | } |
| 15756 | |
| 15757 | static inline void hri_can_set_TXBCIE_CFIE9_bit(const void *const hw) |
| 15758 | { |
| 15759 | CAN_CRITICAL_SECTION_ENTER(); |
| 15760 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE9; |
| 15761 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15762 | } |
| 15763 | |
| 15764 | static inline bool hri_can_get_TXBCIE_CFIE9_bit(const void *const hw) |
| 15765 | { |
| 15766 | uint32_t tmp; |
| 15767 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15768 | tmp = (tmp & CAN_TXBCIE_CFIE9) >> CAN_TXBCIE_CFIE9_Pos; |
| 15769 | return (bool)tmp; |
| 15770 | } |
| 15771 | |
| 15772 | static inline void hri_can_write_TXBCIE_CFIE9_bit(const void *const hw, bool value) |
| 15773 | { |
| 15774 | uint32_t tmp; |
| 15775 | CAN_CRITICAL_SECTION_ENTER(); |
| 15776 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15777 | tmp &= ~CAN_TXBCIE_CFIE9; |
| 15778 | tmp |= value << CAN_TXBCIE_CFIE9_Pos; |
| 15779 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 15780 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15781 | } |
| 15782 | |
| 15783 | static inline void hri_can_clear_TXBCIE_CFIE9_bit(const void *const hw) |
| 15784 | { |
| 15785 | CAN_CRITICAL_SECTION_ENTER(); |
| 15786 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE9; |
| 15787 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15788 | } |
| 15789 | |
| 15790 | static inline void hri_can_toggle_TXBCIE_CFIE9_bit(const void *const hw) |
| 15791 | { |
| 15792 | CAN_CRITICAL_SECTION_ENTER(); |
| 15793 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE9; |
| 15794 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15795 | } |
| 15796 | |
| 15797 | static inline void hri_can_set_TXBCIE_CFIE10_bit(const void *const hw) |
| 15798 | { |
| 15799 | CAN_CRITICAL_SECTION_ENTER(); |
| 15800 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE10; |
| 15801 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15802 | } |
| 15803 | |
| 15804 | static inline bool hri_can_get_TXBCIE_CFIE10_bit(const void *const hw) |
| 15805 | { |
| 15806 | uint32_t tmp; |
| 15807 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15808 | tmp = (tmp & CAN_TXBCIE_CFIE10) >> CAN_TXBCIE_CFIE10_Pos; |
| 15809 | return (bool)tmp; |
| 15810 | } |
| 15811 | |
| 15812 | static inline void hri_can_write_TXBCIE_CFIE10_bit(const void *const hw, bool value) |
| 15813 | { |
| 15814 | uint32_t tmp; |
| 15815 | CAN_CRITICAL_SECTION_ENTER(); |
| 15816 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15817 | tmp &= ~CAN_TXBCIE_CFIE10; |
| 15818 | tmp |= value << CAN_TXBCIE_CFIE10_Pos; |
| 15819 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 15820 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15821 | } |
| 15822 | |
| 15823 | static inline void hri_can_clear_TXBCIE_CFIE10_bit(const void *const hw) |
| 15824 | { |
| 15825 | CAN_CRITICAL_SECTION_ENTER(); |
| 15826 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE10; |
| 15827 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15828 | } |
| 15829 | |
| 15830 | static inline void hri_can_toggle_TXBCIE_CFIE10_bit(const void *const hw) |
| 15831 | { |
| 15832 | CAN_CRITICAL_SECTION_ENTER(); |
| 15833 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE10; |
| 15834 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15835 | } |
| 15836 | |
| 15837 | static inline void hri_can_set_TXBCIE_CFIE11_bit(const void *const hw) |
| 15838 | { |
| 15839 | CAN_CRITICAL_SECTION_ENTER(); |
| 15840 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE11; |
| 15841 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15842 | } |
| 15843 | |
| 15844 | static inline bool hri_can_get_TXBCIE_CFIE11_bit(const void *const hw) |
| 15845 | { |
| 15846 | uint32_t tmp; |
| 15847 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15848 | tmp = (tmp & CAN_TXBCIE_CFIE11) >> CAN_TXBCIE_CFIE11_Pos; |
| 15849 | return (bool)tmp; |
| 15850 | } |
| 15851 | |
| 15852 | static inline void hri_can_write_TXBCIE_CFIE11_bit(const void *const hw, bool value) |
| 15853 | { |
| 15854 | uint32_t tmp; |
| 15855 | CAN_CRITICAL_SECTION_ENTER(); |
| 15856 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15857 | tmp &= ~CAN_TXBCIE_CFIE11; |
| 15858 | tmp |= value << CAN_TXBCIE_CFIE11_Pos; |
| 15859 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 15860 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15861 | } |
| 15862 | |
| 15863 | static inline void hri_can_clear_TXBCIE_CFIE11_bit(const void *const hw) |
| 15864 | { |
| 15865 | CAN_CRITICAL_SECTION_ENTER(); |
| 15866 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE11; |
| 15867 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15868 | } |
| 15869 | |
| 15870 | static inline void hri_can_toggle_TXBCIE_CFIE11_bit(const void *const hw) |
| 15871 | { |
| 15872 | CAN_CRITICAL_SECTION_ENTER(); |
| 15873 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE11; |
| 15874 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15875 | } |
| 15876 | |
| 15877 | static inline void hri_can_set_TXBCIE_CFIE12_bit(const void *const hw) |
| 15878 | { |
| 15879 | CAN_CRITICAL_SECTION_ENTER(); |
| 15880 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE12; |
| 15881 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15882 | } |
| 15883 | |
| 15884 | static inline bool hri_can_get_TXBCIE_CFIE12_bit(const void *const hw) |
| 15885 | { |
| 15886 | uint32_t tmp; |
| 15887 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15888 | tmp = (tmp & CAN_TXBCIE_CFIE12) >> CAN_TXBCIE_CFIE12_Pos; |
| 15889 | return (bool)tmp; |
| 15890 | } |
| 15891 | |
| 15892 | static inline void hri_can_write_TXBCIE_CFIE12_bit(const void *const hw, bool value) |
| 15893 | { |
| 15894 | uint32_t tmp; |
| 15895 | CAN_CRITICAL_SECTION_ENTER(); |
| 15896 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15897 | tmp &= ~CAN_TXBCIE_CFIE12; |
| 15898 | tmp |= value << CAN_TXBCIE_CFIE12_Pos; |
| 15899 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 15900 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15901 | } |
| 15902 | |
| 15903 | static inline void hri_can_clear_TXBCIE_CFIE12_bit(const void *const hw) |
| 15904 | { |
| 15905 | CAN_CRITICAL_SECTION_ENTER(); |
| 15906 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE12; |
| 15907 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15908 | } |
| 15909 | |
| 15910 | static inline void hri_can_toggle_TXBCIE_CFIE12_bit(const void *const hw) |
| 15911 | { |
| 15912 | CAN_CRITICAL_SECTION_ENTER(); |
| 15913 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE12; |
| 15914 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15915 | } |
| 15916 | |
| 15917 | static inline void hri_can_set_TXBCIE_CFIE13_bit(const void *const hw) |
| 15918 | { |
| 15919 | CAN_CRITICAL_SECTION_ENTER(); |
| 15920 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE13; |
| 15921 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15922 | } |
| 15923 | |
| 15924 | static inline bool hri_can_get_TXBCIE_CFIE13_bit(const void *const hw) |
| 15925 | { |
| 15926 | uint32_t tmp; |
| 15927 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15928 | tmp = (tmp & CAN_TXBCIE_CFIE13) >> CAN_TXBCIE_CFIE13_Pos; |
| 15929 | return (bool)tmp; |
| 15930 | } |
| 15931 | |
| 15932 | static inline void hri_can_write_TXBCIE_CFIE13_bit(const void *const hw, bool value) |
| 15933 | { |
| 15934 | uint32_t tmp; |
| 15935 | CAN_CRITICAL_SECTION_ENTER(); |
| 15936 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15937 | tmp &= ~CAN_TXBCIE_CFIE13; |
| 15938 | tmp |= value << CAN_TXBCIE_CFIE13_Pos; |
| 15939 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 15940 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15941 | } |
| 15942 | |
| 15943 | static inline void hri_can_clear_TXBCIE_CFIE13_bit(const void *const hw) |
| 15944 | { |
| 15945 | CAN_CRITICAL_SECTION_ENTER(); |
| 15946 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE13; |
| 15947 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15948 | } |
| 15949 | |
| 15950 | static inline void hri_can_toggle_TXBCIE_CFIE13_bit(const void *const hw) |
| 15951 | { |
| 15952 | CAN_CRITICAL_SECTION_ENTER(); |
| 15953 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE13; |
| 15954 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15955 | } |
| 15956 | |
| 15957 | static inline void hri_can_set_TXBCIE_CFIE14_bit(const void *const hw) |
| 15958 | { |
| 15959 | CAN_CRITICAL_SECTION_ENTER(); |
| 15960 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE14; |
| 15961 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15962 | } |
| 15963 | |
| 15964 | static inline bool hri_can_get_TXBCIE_CFIE14_bit(const void *const hw) |
| 15965 | { |
| 15966 | uint32_t tmp; |
| 15967 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15968 | tmp = (tmp & CAN_TXBCIE_CFIE14) >> CAN_TXBCIE_CFIE14_Pos; |
| 15969 | return (bool)tmp; |
| 15970 | } |
| 15971 | |
| 15972 | static inline void hri_can_write_TXBCIE_CFIE14_bit(const void *const hw, bool value) |
| 15973 | { |
| 15974 | uint32_t tmp; |
| 15975 | CAN_CRITICAL_SECTION_ENTER(); |
| 15976 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 15977 | tmp &= ~CAN_TXBCIE_CFIE14; |
| 15978 | tmp |= value << CAN_TXBCIE_CFIE14_Pos; |
| 15979 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 15980 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15981 | } |
| 15982 | |
| 15983 | static inline void hri_can_clear_TXBCIE_CFIE14_bit(const void *const hw) |
| 15984 | { |
| 15985 | CAN_CRITICAL_SECTION_ENTER(); |
| 15986 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE14; |
| 15987 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15988 | } |
| 15989 | |
| 15990 | static inline void hri_can_toggle_TXBCIE_CFIE14_bit(const void *const hw) |
| 15991 | { |
| 15992 | CAN_CRITICAL_SECTION_ENTER(); |
| 15993 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE14; |
| 15994 | CAN_CRITICAL_SECTION_LEAVE(); |
| 15995 | } |
| 15996 | |
| 15997 | static inline void hri_can_set_TXBCIE_CFIE15_bit(const void *const hw) |
| 15998 | { |
| 15999 | CAN_CRITICAL_SECTION_ENTER(); |
| 16000 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE15; |
| 16001 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16002 | } |
| 16003 | |
| 16004 | static inline bool hri_can_get_TXBCIE_CFIE15_bit(const void *const hw) |
| 16005 | { |
| 16006 | uint32_t tmp; |
| 16007 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16008 | tmp = (tmp & CAN_TXBCIE_CFIE15) >> CAN_TXBCIE_CFIE15_Pos; |
| 16009 | return (bool)tmp; |
| 16010 | } |
| 16011 | |
| 16012 | static inline void hri_can_write_TXBCIE_CFIE15_bit(const void *const hw, bool value) |
| 16013 | { |
| 16014 | uint32_t tmp; |
| 16015 | CAN_CRITICAL_SECTION_ENTER(); |
| 16016 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16017 | tmp &= ~CAN_TXBCIE_CFIE15; |
| 16018 | tmp |= value << CAN_TXBCIE_CFIE15_Pos; |
| 16019 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 16020 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16021 | } |
| 16022 | |
| 16023 | static inline void hri_can_clear_TXBCIE_CFIE15_bit(const void *const hw) |
| 16024 | { |
| 16025 | CAN_CRITICAL_SECTION_ENTER(); |
| 16026 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE15; |
| 16027 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16028 | } |
| 16029 | |
| 16030 | static inline void hri_can_toggle_TXBCIE_CFIE15_bit(const void *const hw) |
| 16031 | { |
| 16032 | CAN_CRITICAL_SECTION_ENTER(); |
| 16033 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE15; |
| 16034 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16035 | } |
| 16036 | |
| 16037 | static inline void hri_can_set_TXBCIE_CFIE16_bit(const void *const hw) |
| 16038 | { |
| 16039 | CAN_CRITICAL_SECTION_ENTER(); |
| 16040 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE16; |
| 16041 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16042 | } |
| 16043 | |
| 16044 | static inline bool hri_can_get_TXBCIE_CFIE16_bit(const void *const hw) |
| 16045 | { |
| 16046 | uint32_t tmp; |
| 16047 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16048 | tmp = (tmp & CAN_TXBCIE_CFIE16) >> CAN_TXBCIE_CFIE16_Pos; |
| 16049 | return (bool)tmp; |
| 16050 | } |
| 16051 | |
| 16052 | static inline void hri_can_write_TXBCIE_CFIE16_bit(const void *const hw, bool value) |
| 16053 | { |
| 16054 | uint32_t tmp; |
| 16055 | CAN_CRITICAL_SECTION_ENTER(); |
| 16056 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16057 | tmp &= ~CAN_TXBCIE_CFIE16; |
| 16058 | tmp |= value << CAN_TXBCIE_CFIE16_Pos; |
| 16059 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 16060 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16061 | } |
| 16062 | |
| 16063 | static inline void hri_can_clear_TXBCIE_CFIE16_bit(const void *const hw) |
| 16064 | { |
| 16065 | CAN_CRITICAL_SECTION_ENTER(); |
| 16066 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE16; |
| 16067 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16068 | } |
| 16069 | |
| 16070 | static inline void hri_can_toggle_TXBCIE_CFIE16_bit(const void *const hw) |
| 16071 | { |
| 16072 | CAN_CRITICAL_SECTION_ENTER(); |
| 16073 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE16; |
| 16074 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16075 | } |
| 16076 | |
| 16077 | static inline void hri_can_set_TXBCIE_CFIE17_bit(const void *const hw) |
| 16078 | { |
| 16079 | CAN_CRITICAL_SECTION_ENTER(); |
| 16080 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE17; |
| 16081 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16082 | } |
| 16083 | |
| 16084 | static inline bool hri_can_get_TXBCIE_CFIE17_bit(const void *const hw) |
| 16085 | { |
| 16086 | uint32_t tmp; |
| 16087 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16088 | tmp = (tmp & CAN_TXBCIE_CFIE17) >> CAN_TXBCIE_CFIE17_Pos; |
| 16089 | return (bool)tmp; |
| 16090 | } |
| 16091 | |
| 16092 | static inline void hri_can_write_TXBCIE_CFIE17_bit(const void *const hw, bool value) |
| 16093 | { |
| 16094 | uint32_t tmp; |
| 16095 | CAN_CRITICAL_SECTION_ENTER(); |
| 16096 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16097 | tmp &= ~CAN_TXBCIE_CFIE17; |
| 16098 | tmp |= value << CAN_TXBCIE_CFIE17_Pos; |
| 16099 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 16100 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16101 | } |
| 16102 | |
| 16103 | static inline void hri_can_clear_TXBCIE_CFIE17_bit(const void *const hw) |
| 16104 | { |
| 16105 | CAN_CRITICAL_SECTION_ENTER(); |
| 16106 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE17; |
| 16107 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16108 | } |
| 16109 | |
| 16110 | static inline void hri_can_toggle_TXBCIE_CFIE17_bit(const void *const hw) |
| 16111 | { |
| 16112 | CAN_CRITICAL_SECTION_ENTER(); |
| 16113 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE17; |
| 16114 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16115 | } |
| 16116 | |
| 16117 | static inline void hri_can_set_TXBCIE_CFIE18_bit(const void *const hw) |
| 16118 | { |
| 16119 | CAN_CRITICAL_SECTION_ENTER(); |
| 16120 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE18; |
| 16121 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16122 | } |
| 16123 | |
| 16124 | static inline bool hri_can_get_TXBCIE_CFIE18_bit(const void *const hw) |
| 16125 | { |
| 16126 | uint32_t tmp; |
| 16127 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16128 | tmp = (tmp & CAN_TXBCIE_CFIE18) >> CAN_TXBCIE_CFIE18_Pos; |
| 16129 | return (bool)tmp; |
| 16130 | } |
| 16131 | |
| 16132 | static inline void hri_can_write_TXBCIE_CFIE18_bit(const void *const hw, bool value) |
| 16133 | { |
| 16134 | uint32_t tmp; |
| 16135 | CAN_CRITICAL_SECTION_ENTER(); |
| 16136 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16137 | tmp &= ~CAN_TXBCIE_CFIE18; |
| 16138 | tmp |= value << CAN_TXBCIE_CFIE18_Pos; |
| 16139 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 16140 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16141 | } |
| 16142 | |
| 16143 | static inline void hri_can_clear_TXBCIE_CFIE18_bit(const void *const hw) |
| 16144 | { |
| 16145 | CAN_CRITICAL_SECTION_ENTER(); |
| 16146 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE18; |
| 16147 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16148 | } |
| 16149 | |
| 16150 | static inline void hri_can_toggle_TXBCIE_CFIE18_bit(const void *const hw) |
| 16151 | { |
| 16152 | CAN_CRITICAL_SECTION_ENTER(); |
| 16153 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE18; |
| 16154 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16155 | } |
| 16156 | |
| 16157 | static inline void hri_can_set_TXBCIE_CFIE19_bit(const void *const hw) |
| 16158 | { |
| 16159 | CAN_CRITICAL_SECTION_ENTER(); |
| 16160 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE19; |
| 16161 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16162 | } |
| 16163 | |
| 16164 | static inline bool hri_can_get_TXBCIE_CFIE19_bit(const void *const hw) |
| 16165 | { |
| 16166 | uint32_t tmp; |
| 16167 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16168 | tmp = (tmp & CAN_TXBCIE_CFIE19) >> CAN_TXBCIE_CFIE19_Pos; |
| 16169 | return (bool)tmp; |
| 16170 | } |
| 16171 | |
| 16172 | static inline void hri_can_write_TXBCIE_CFIE19_bit(const void *const hw, bool value) |
| 16173 | { |
| 16174 | uint32_t tmp; |
| 16175 | CAN_CRITICAL_SECTION_ENTER(); |
| 16176 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16177 | tmp &= ~CAN_TXBCIE_CFIE19; |
| 16178 | tmp |= value << CAN_TXBCIE_CFIE19_Pos; |
| 16179 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 16180 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16181 | } |
| 16182 | |
| 16183 | static inline void hri_can_clear_TXBCIE_CFIE19_bit(const void *const hw) |
| 16184 | { |
| 16185 | CAN_CRITICAL_SECTION_ENTER(); |
| 16186 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE19; |
| 16187 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16188 | } |
| 16189 | |
| 16190 | static inline void hri_can_toggle_TXBCIE_CFIE19_bit(const void *const hw) |
| 16191 | { |
| 16192 | CAN_CRITICAL_SECTION_ENTER(); |
| 16193 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE19; |
| 16194 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16195 | } |
| 16196 | |
| 16197 | static inline void hri_can_set_TXBCIE_CFIE20_bit(const void *const hw) |
| 16198 | { |
| 16199 | CAN_CRITICAL_SECTION_ENTER(); |
| 16200 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE20; |
| 16201 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16202 | } |
| 16203 | |
| 16204 | static inline bool hri_can_get_TXBCIE_CFIE20_bit(const void *const hw) |
| 16205 | { |
| 16206 | uint32_t tmp; |
| 16207 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16208 | tmp = (tmp & CAN_TXBCIE_CFIE20) >> CAN_TXBCIE_CFIE20_Pos; |
| 16209 | return (bool)tmp; |
| 16210 | } |
| 16211 | |
| 16212 | static inline void hri_can_write_TXBCIE_CFIE20_bit(const void *const hw, bool value) |
| 16213 | { |
| 16214 | uint32_t tmp; |
| 16215 | CAN_CRITICAL_SECTION_ENTER(); |
| 16216 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16217 | tmp &= ~CAN_TXBCIE_CFIE20; |
| 16218 | tmp |= value << CAN_TXBCIE_CFIE20_Pos; |
| 16219 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 16220 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16221 | } |
| 16222 | |
| 16223 | static inline void hri_can_clear_TXBCIE_CFIE20_bit(const void *const hw) |
| 16224 | { |
| 16225 | CAN_CRITICAL_SECTION_ENTER(); |
| 16226 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE20; |
| 16227 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16228 | } |
| 16229 | |
| 16230 | static inline void hri_can_toggle_TXBCIE_CFIE20_bit(const void *const hw) |
| 16231 | { |
| 16232 | CAN_CRITICAL_SECTION_ENTER(); |
| 16233 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE20; |
| 16234 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16235 | } |
| 16236 | |
| 16237 | static inline void hri_can_set_TXBCIE_CFIE21_bit(const void *const hw) |
| 16238 | { |
| 16239 | CAN_CRITICAL_SECTION_ENTER(); |
| 16240 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE21; |
| 16241 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16242 | } |
| 16243 | |
| 16244 | static inline bool hri_can_get_TXBCIE_CFIE21_bit(const void *const hw) |
| 16245 | { |
| 16246 | uint32_t tmp; |
| 16247 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16248 | tmp = (tmp & CAN_TXBCIE_CFIE21) >> CAN_TXBCIE_CFIE21_Pos; |
| 16249 | return (bool)tmp; |
| 16250 | } |
| 16251 | |
| 16252 | static inline void hri_can_write_TXBCIE_CFIE21_bit(const void *const hw, bool value) |
| 16253 | { |
| 16254 | uint32_t tmp; |
| 16255 | CAN_CRITICAL_SECTION_ENTER(); |
| 16256 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16257 | tmp &= ~CAN_TXBCIE_CFIE21; |
| 16258 | tmp |= value << CAN_TXBCIE_CFIE21_Pos; |
| 16259 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 16260 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16261 | } |
| 16262 | |
| 16263 | static inline void hri_can_clear_TXBCIE_CFIE21_bit(const void *const hw) |
| 16264 | { |
| 16265 | CAN_CRITICAL_SECTION_ENTER(); |
| 16266 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE21; |
| 16267 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16268 | } |
| 16269 | |
| 16270 | static inline void hri_can_toggle_TXBCIE_CFIE21_bit(const void *const hw) |
| 16271 | { |
| 16272 | CAN_CRITICAL_SECTION_ENTER(); |
| 16273 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE21; |
| 16274 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16275 | } |
| 16276 | |
| 16277 | static inline void hri_can_set_TXBCIE_CFIE22_bit(const void *const hw) |
| 16278 | { |
| 16279 | CAN_CRITICAL_SECTION_ENTER(); |
| 16280 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE22; |
| 16281 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16282 | } |
| 16283 | |
| 16284 | static inline bool hri_can_get_TXBCIE_CFIE22_bit(const void *const hw) |
| 16285 | { |
| 16286 | uint32_t tmp; |
| 16287 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16288 | tmp = (tmp & CAN_TXBCIE_CFIE22) >> CAN_TXBCIE_CFIE22_Pos; |
| 16289 | return (bool)tmp; |
| 16290 | } |
| 16291 | |
| 16292 | static inline void hri_can_write_TXBCIE_CFIE22_bit(const void *const hw, bool value) |
| 16293 | { |
| 16294 | uint32_t tmp; |
| 16295 | CAN_CRITICAL_SECTION_ENTER(); |
| 16296 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16297 | tmp &= ~CAN_TXBCIE_CFIE22; |
| 16298 | tmp |= value << CAN_TXBCIE_CFIE22_Pos; |
| 16299 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 16300 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16301 | } |
| 16302 | |
| 16303 | static inline void hri_can_clear_TXBCIE_CFIE22_bit(const void *const hw) |
| 16304 | { |
| 16305 | CAN_CRITICAL_SECTION_ENTER(); |
| 16306 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE22; |
| 16307 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16308 | } |
| 16309 | |
| 16310 | static inline void hri_can_toggle_TXBCIE_CFIE22_bit(const void *const hw) |
| 16311 | { |
| 16312 | CAN_CRITICAL_SECTION_ENTER(); |
| 16313 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE22; |
| 16314 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16315 | } |
| 16316 | |
| 16317 | static inline void hri_can_set_TXBCIE_CFIE23_bit(const void *const hw) |
| 16318 | { |
| 16319 | CAN_CRITICAL_SECTION_ENTER(); |
| 16320 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE23; |
| 16321 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16322 | } |
| 16323 | |
| 16324 | static inline bool hri_can_get_TXBCIE_CFIE23_bit(const void *const hw) |
| 16325 | { |
| 16326 | uint32_t tmp; |
| 16327 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16328 | tmp = (tmp & CAN_TXBCIE_CFIE23) >> CAN_TXBCIE_CFIE23_Pos; |
| 16329 | return (bool)tmp; |
| 16330 | } |
| 16331 | |
| 16332 | static inline void hri_can_write_TXBCIE_CFIE23_bit(const void *const hw, bool value) |
| 16333 | { |
| 16334 | uint32_t tmp; |
| 16335 | CAN_CRITICAL_SECTION_ENTER(); |
| 16336 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16337 | tmp &= ~CAN_TXBCIE_CFIE23; |
| 16338 | tmp |= value << CAN_TXBCIE_CFIE23_Pos; |
| 16339 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 16340 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16341 | } |
| 16342 | |
| 16343 | static inline void hri_can_clear_TXBCIE_CFIE23_bit(const void *const hw) |
| 16344 | { |
| 16345 | CAN_CRITICAL_SECTION_ENTER(); |
| 16346 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE23; |
| 16347 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16348 | } |
| 16349 | |
| 16350 | static inline void hri_can_toggle_TXBCIE_CFIE23_bit(const void *const hw) |
| 16351 | { |
| 16352 | CAN_CRITICAL_SECTION_ENTER(); |
| 16353 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE23; |
| 16354 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16355 | } |
| 16356 | |
| 16357 | static inline void hri_can_set_TXBCIE_CFIE24_bit(const void *const hw) |
| 16358 | { |
| 16359 | CAN_CRITICAL_SECTION_ENTER(); |
| 16360 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE24; |
| 16361 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16362 | } |
| 16363 | |
| 16364 | static inline bool hri_can_get_TXBCIE_CFIE24_bit(const void *const hw) |
| 16365 | { |
| 16366 | uint32_t tmp; |
| 16367 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16368 | tmp = (tmp & CAN_TXBCIE_CFIE24) >> CAN_TXBCIE_CFIE24_Pos; |
| 16369 | return (bool)tmp; |
| 16370 | } |
| 16371 | |
| 16372 | static inline void hri_can_write_TXBCIE_CFIE24_bit(const void *const hw, bool value) |
| 16373 | { |
| 16374 | uint32_t tmp; |
| 16375 | CAN_CRITICAL_SECTION_ENTER(); |
| 16376 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16377 | tmp &= ~CAN_TXBCIE_CFIE24; |
| 16378 | tmp |= value << CAN_TXBCIE_CFIE24_Pos; |
| 16379 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 16380 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16381 | } |
| 16382 | |
| 16383 | static inline void hri_can_clear_TXBCIE_CFIE24_bit(const void *const hw) |
| 16384 | { |
| 16385 | CAN_CRITICAL_SECTION_ENTER(); |
| 16386 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE24; |
| 16387 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16388 | } |
| 16389 | |
| 16390 | static inline void hri_can_toggle_TXBCIE_CFIE24_bit(const void *const hw) |
| 16391 | { |
| 16392 | CAN_CRITICAL_SECTION_ENTER(); |
| 16393 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE24; |
| 16394 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16395 | } |
| 16396 | |
| 16397 | static inline void hri_can_set_TXBCIE_CFIE25_bit(const void *const hw) |
| 16398 | { |
| 16399 | CAN_CRITICAL_SECTION_ENTER(); |
| 16400 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE25; |
| 16401 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16402 | } |
| 16403 | |
| 16404 | static inline bool hri_can_get_TXBCIE_CFIE25_bit(const void *const hw) |
| 16405 | { |
| 16406 | uint32_t tmp; |
| 16407 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16408 | tmp = (tmp & CAN_TXBCIE_CFIE25) >> CAN_TXBCIE_CFIE25_Pos; |
| 16409 | return (bool)tmp; |
| 16410 | } |
| 16411 | |
| 16412 | static inline void hri_can_write_TXBCIE_CFIE25_bit(const void *const hw, bool value) |
| 16413 | { |
| 16414 | uint32_t tmp; |
| 16415 | CAN_CRITICAL_SECTION_ENTER(); |
| 16416 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16417 | tmp &= ~CAN_TXBCIE_CFIE25; |
| 16418 | tmp |= value << CAN_TXBCIE_CFIE25_Pos; |
| 16419 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 16420 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16421 | } |
| 16422 | |
| 16423 | static inline void hri_can_clear_TXBCIE_CFIE25_bit(const void *const hw) |
| 16424 | { |
| 16425 | CAN_CRITICAL_SECTION_ENTER(); |
| 16426 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE25; |
| 16427 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16428 | } |
| 16429 | |
| 16430 | static inline void hri_can_toggle_TXBCIE_CFIE25_bit(const void *const hw) |
| 16431 | { |
| 16432 | CAN_CRITICAL_SECTION_ENTER(); |
| 16433 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE25; |
| 16434 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16435 | } |
| 16436 | |
| 16437 | static inline void hri_can_set_TXBCIE_CFIE26_bit(const void *const hw) |
| 16438 | { |
| 16439 | CAN_CRITICAL_SECTION_ENTER(); |
| 16440 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE26; |
| 16441 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16442 | } |
| 16443 | |
| 16444 | static inline bool hri_can_get_TXBCIE_CFIE26_bit(const void *const hw) |
| 16445 | { |
| 16446 | uint32_t tmp; |
| 16447 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16448 | tmp = (tmp & CAN_TXBCIE_CFIE26) >> CAN_TXBCIE_CFIE26_Pos; |
| 16449 | return (bool)tmp; |
| 16450 | } |
| 16451 | |
| 16452 | static inline void hri_can_write_TXBCIE_CFIE26_bit(const void *const hw, bool value) |
| 16453 | { |
| 16454 | uint32_t tmp; |
| 16455 | CAN_CRITICAL_SECTION_ENTER(); |
| 16456 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16457 | tmp &= ~CAN_TXBCIE_CFIE26; |
| 16458 | tmp |= value << CAN_TXBCIE_CFIE26_Pos; |
| 16459 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 16460 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16461 | } |
| 16462 | |
| 16463 | static inline void hri_can_clear_TXBCIE_CFIE26_bit(const void *const hw) |
| 16464 | { |
| 16465 | CAN_CRITICAL_SECTION_ENTER(); |
| 16466 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE26; |
| 16467 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16468 | } |
| 16469 | |
| 16470 | static inline void hri_can_toggle_TXBCIE_CFIE26_bit(const void *const hw) |
| 16471 | { |
| 16472 | CAN_CRITICAL_SECTION_ENTER(); |
| 16473 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE26; |
| 16474 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16475 | } |
| 16476 | |
| 16477 | static inline void hri_can_set_TXBCIE_CFIE27_bit(const void *const hw) |
| 16478 | { |
| 16479 | CAN_CRITICAL_SECTION_ENTER(); |
| 16480 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE27; |
| 16481 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16482 | } |
| 16483 | |
| 16484 | static inline bool hri_can_get_TXBCIE_CFIE27_bit(const void *const hw) |
| 16485 | { |
| 16486 | uint32_t tmp; |
| 16487 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16488 | tmp = (tmp & CAN_TXBCIE_CFIE27) >> CAN_TXBCIE_CFIE27_Pos; |
| 16489 | return (bool)tmp; |
| 16490 | } |
| 16491 | |
| 16492 | static inline void hri_can_write_TXBCIE_CFIE27_bit(const void *const hw, bool value) |
| 16493 | { |
| 16494 | uint32_t tmp; |
| 16495 | CAN_CRITICAL_SECTION_ENTER(); |
| 16496 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16497 | tmp &= ~CAN_TXBCIE_CFIE27; |
| 16498 | tmp |= value << CAN_TXBCIE_CFIE27_Pos; |
| 16499 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 16500 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16501 | } |
| 16502 | |
| 16503 | static inline void hri_can_clear_TXBCIE_CFIE27_bit(const void *const hw) |
| 16504 | { |
| 16505 | CAN_CRITICAL_SECTION_ENTER(); |
| 16506 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE27; |
| 16507 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16508 | } |
| 16509 | |
| 16510 | static inline void hri_can_toggle_TXBCIE_CFIE27_bit(const void *const hw) |
| 16511 | { |
| 16512 | CAN_CRITICAL_SECTION_ENTER(); |
| 16513 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE27; |
| 16514 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16515 | } |
| 16516 | |
| 16517 | static inline void hri_can_set_TXBCIE_CFIE28_bit(const void *const hw) |
| 16518 | { |
| 16519 | CAN_CRITICAL_SECTION_ENTER(); |
| 16520 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE28; |
| 16521 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16522 | } |
| 16523 | |
| 16524 | static inline bool hri_can_get_TXBCIE_CFIE28_bit(const void *const hw) |
| 16525 | { |
| 16526 | uint32_t tmp; |
| 16527 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16528 | tmp = (tmp & CAN_TXBCIE_CFIE28) >> CAN_TXBCIE_CFIE28_Pos; |
| 16529 | return (bool)tmp; |
| 16530 | } |
| 16531 | |
| 16532 | static inline void hri_can_write_TXBCIE_CFIE28_bit(const void *const hw, bool value) |
| 16533 | { |
| 16534 | uint32_t tmp; |
| 16535 | CAN_CRITICAL_SECTION_ENTER(); |
| 16536 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16537 | tmp &= ~CAN_TXBCIE_CFIE28; |
| 16538 | tmp |= value << CAN_TXBCIE_CFIE28_Pos; |
| 16539 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 16540 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16541 | } |
| 16542 | |
| 16543 | static inline void hri_can_clear_TXBCIE_CFIE28_bit(const void *const hw) |
| 16544 | { |
| 16545 | CAN_CRITICAL_SECTION_ENTER(); |
| 16546 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE28; |
| 16547 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16548 | } |
| 16549 | |
| 16550 | static inline void hri_can_toggle_TXBCIE_CFIE28_bit(const void *const hw) |
| 16551 | { |
| 16552 | CAN_CRITICAL_SECTION_ENTER(); |
| 16553 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE28; |
| 16554 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16555 | } |
| 16556 | |
| 16557 | static inline void hri_can_set_TXBCIE_CFIE29_bit(const void *const hw) |
| 16558 | { |
| 16559 | CAN_CRITICAL_SECTION_ENTER(); |
| 16560 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE29; |
| 16561 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16562 | } |
| 16563 | |
| 16564 | static inline bool hri_can_get_TXBCIE_CFIE29_bit(const void *const hw) |
| 16565 | { |
| 16566 | uint32_t tmp; |
| 16567 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16568 | tmp = (tmp & CAN_TXBCIE_CFIE29) >> CAN_TXBCIE_CFIE29_Pos; |
| 16569 | return (bool)tmp; |
| 16570 | } |
| 16571 | |
| 16572 | static inline void hri_can_write_TXBCIE_CFIE29_bit(const void *const hw, bool value) |
| 16573 | { |
| 16574 | uint32_t tmp; |
| 16575 | CAN_CRITICAL_SECTION_ENTER(); |
| 16576 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16577 | tmp &= ~CAN_TXBCIE_CFIE29; |
| 16578 | tmp |= value << CAN_TXBCIE_CFIE29_Pos; |
| 16579 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 16580 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16581 | } |
| 16582 | |
| 16583 | static inline void hri_can_clear_TXBCIE_CFIE29_bit(const void *const hw) |
| 16584 | { |
| 16585 | CAN_CRITICAL_SECTION_ENTER(); |
| 16586 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE29; |
| 16587 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16588 | } |
| 16589 | |
| 16590 | static inline void hri_can_toggle_TXBCIE_CFIE29_bit(const void *const hw) |
| 16591 | { |
| 16592 | CAN_CRITICAL_SECTION_ENTER(); |
| 16593 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE29; |
| 16594 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16595 | } |
| 16596 | |
| 16597 | static inline void hri_can_set_TXBCIE_CFIE30_bit(const void *const hw) |
| 16598 | { |
| 16599 | CAN_CRITICAL_SECTION_ENTER(); |
| 16600 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE30; |
| 16601 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16602 | } |
| 16603 | |
| 16604 | static inline bool hri_can_get_TXBCIE_CFIE30_bit(const void *const hw) |
| 16605 | { |
| 16606 | uint32_t tmp; |
| 16607 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16608 | tmp = (tmp & CAN_TXBCIE_CFIE30) >> CAN_TXBCIE_CFIE30_Pos; |
| 16609 | return (bool)tmp; |
| 16610 | } |
| 16611 | |
| 16612 | static inline void hri_can_write_TXBCIE_CFIE30_bit(const void *const hw, bool value) |
| 16613 | { |
| 16614 | uint32_t tmp; |
| 16615 | CAN_CRITICAL_SECTION_ENTER(); |
| 16616 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16617 | tmp &= ~CAN_TXBCIE_CFIE30; |
| 16618 | tmp |= value << CAN_TXBCIE_CFIE30_Pos; |
| 16619 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 16620 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16621 | } |
| 16622 | |
| 16623 | static inline void hri_can_clear_TXBCIE_CFIE30_bit(const void *const hw) |
| 16624 | { |
| 16625 | CAN_CRITICAL_SECTION_ENTER(); |
| 16626 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE30; |
| 16627 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16628 | } |
| 16629 | |
| 16630 | static inline void hri_can_toggle_TXBCIE_CFIE30_bit(const void *const hw) |
| 16631 | { |
| 16632 | CAN_CRITICAL_SECTION_ENTER(); |
| 16633 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE30; |
| 16634 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16635 | } |
| 16636 | |
| 16637 | static inline void hri_can_set_TXBCIE_CFIE31_bit(const void *const hw) |
| 16638 | { |
| 16639 | CAN_CRITICAL_SECTION_ENTER(); |
| 16640 | ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE31; |
| 16641 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16642 | } |
| 16643 | |
| 16644 | static inline bool hri_can_get_TXBCIE_CFIE31_bit(const void *const hw) |
| 16645 | { |
| 16646 | uint32_t tmp; |
| 16647 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16648 | tmp = (tmp & CAN_TXBCIE_CFIE31) >> CAN_TXBCIE_CFIE31_Pos; |
| 16649 | return (bool)tmp; |
| 16650 | } |
| 16651 | |
| 16652 | static inline void hri_can_write_TXBCIE_CFIE31_bit(const void *const hw, bool value) |
| 16653 | { |
| 16654 | uint32_t tmp; |
| 16655 | CAN_CRITICAL_SECTION_ENTER(); |
| 16656 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16657 | tmp &= ~CAN_TXBCIE_CFIE31; |
| 16658 | tmp |= value << CAN_TXBCIE_CFIE31_Pos; |
| 16659 | ((Can *)hw)->TXBCIE.reg = tmp; |
| 16660 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16661 | } |
| 16662 | |
| 16663 | static inline void hri_can_clear_TXBCIE_CFIE31_bit(const void *const hw) |
| 16664 | { |
| 16665 | CAN_CRITICAL_SECTION_ENTER(); |
| 16666 | ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE31; |
| 16667 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16668 | } |
| 16669 | |
| 16670 | static inline void hri_can_toggle_TXBCIE_CFIE31_bit(const void *const hw) |
| 16671 | { |
| 16672 | CAN_CRITICAL_SECTION_ENTER(); |
| 16673 | ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE31; |
| 16674 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16675 | } |
| 16676 | |
| 16677 | static inline void hri_can_set_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) |
| 16678 | { |
| 16679 | CAN_CRITICAL_SECTION_ENTER(); |
| 16680 | ((Can *)hw)->TXBCIE.reg |= mask; |
| 16681 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16682 | } |
| 16683 | |
| 16684 | static inline hri_can_txbcie_reg_t hri_can_get_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) |
| 16685 | { |
| 16686 | uint32_t tmp; |
| 16687 | tmp = ((Can *)hw)->TXBCIE.reg; |
| 16688 | tmp &= mask; |
| 16689 | return tmp; |
| 16690 | } |
| 16691 | |
| 16692 | static inline void hri_can_write_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t data) |
| 16693 | { |
| 16694 | CAN_CRITICAL_SECTION_ENTER(); |
| 16695 | ((Can *)hw)->TXBCIE.reg = data; |
| 16696 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16697 | } |
| 16698 | |
| 16699 | static inline void hri_can_clear_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) |
| 16700 | { |
| 16701 | CAN_CRITICAL_SECTION_ENTER(); |
| 16702 | ((Can *)hw)->TXBCIE.reg &= ~mask; |
| 16703 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16704 | } |
| 16705 | |
| 16706 | static inline void hri_can_toggle_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) |
| 16707 | { |
| 16708 | CAN_CRITICAL_SECTION_ENTER(); |
| 16709 | ((Can *)hw)->TXBCIE.reg ^= mask; |
| 16710 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16711 | } |
| 16712 | |
| 16713 | static inline hri_can_txbcie_reg_t hri_can_read_TXBCIE_reg(const void *const hw) |
| 16714 | { |
| 16715 | return ((Can *)hw)->TXBCIE.reg; |
| 16716 | } |
| 16717 | |
| 16718 | static inline void hri_can_set_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) |
| 16719 | { |
| 16720 | CAN_CRITICAL_SECTION_ENTER(); |
| 16721 | ((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFSA(mask); |
| 16722 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16723 | } |
| 16724 | |
| 16725 | static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) |
| 16726 | { |
| 16727 | uint32_t tmp; |
| 16728 | tmp = ((Can *)hw)->TXEFC.reg; |
| 16729 | tmp = (tmp & CAN_TXEFC_EFSA(mask)) >> CAN_TXEFC_EFSA_Pos; |
| 16730 | return tmp; |
| 16731 | } |
| 16732 | |
| 16733 | static inline void hri_can_write_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t data) |
| 16734 | { |
| 16735 | uint32_t tmp; |
| 16736 | CAN_CRITICAL_SECTION_ENTER(); |
| 16737 | tmp = ((Can *)hw)->TXEFC.reg; |
| 16738 | tmp &= ~CAN_TXEFC_EFSA_Msk; |
| 16739 | tmp |= CAN_TXEFC_EFSA(data); |
| 16740 | ((Can *)hw)->TXEFC.reg = tmp; |
| 16741 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16742 | } |
| 16743 | |
| 16744 | static inline void hri_can_clear_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) |
| 16745 | { |
| 16746 | CAN_CRITICAL_SECTION_ENTER(); |
| 16747 | ((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFSA(mask); |
| 16748 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16749 | } |
| 16750 | |
| 16751 | static inline void hri_can_toggle_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) |
| 16752 | { |
| 16753 | CAN_CRITICAL_SECTION_ENTER(); |
| 16754 | ((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFSA(mask); |
| 16755 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16756 | } |
| 16757 | |
| 16758 | static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFSA_bf(const void *const hw) |
| 16759 | { |
| 16760 | uint32_t tmp; |
| 16761 | tmp = ((Can *)hw)->TXEFC.reg; |
| 16762 | tmp = (tmp & CAN_TXEFC_EFSA_Msk) >> CAN_TXEFC_EFSA_Pos; |
| 16763 | return tmp; |
| 16764 | } |
| 16765 | |
| 16766 | static inline void hri_can_set_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) |
| 16767 | { |
| 16768 | CAN_CRITICAL_SECTION_ENTER(); |
| 16769 | ((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFS(mask); |
| 16770 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16771 | } |
| 16772 | |
| 16773 | static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) |
| 16774 | { |
| 16775 | uint32_t tmp; |
| 16776 | tmp = ((Can *)hw)->TXEFC.reg; |
| 16777 | tmp = (tmp & CAN_TXEFC_EFS(mask)) >> CAN_TXEFC_EFS_Pos; |
| 16778 | return tmp; |
| 16779 | } |
| 16780 | |
| 16781 | static inline void hri_can_write_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t data) |
| 16782 | { |
| 16783 | uint32_t tmp; |
| 16784 | CAN_CRITICAL_SECTION_ENTER(); |
| 16785 | tmp = ((Can *)hw)->TXEFC.reg; |
| 16786 | tmp &= ~CAN_TXEFC_EFS_Msk; |
| 16787 | tmp |= CAN_TXEFC_EFS(data); |
| 16788 | ((Can *)hw)->TXEFC.reg = tmp; |
| 16789 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16790 | } |
| 16791 | |
| 16792 | static inline void hri_can_clear_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) |
| 16793 | { |
| 16794 | CAN_CRITICAL_SECTION_ENTER(); |
| 16795 | ((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFS(mask); |
| 16796 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16797 | } |
| 16798 | |
| 16799 | static inline void hri_can_toggle_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) |
| 16800 | { |
| 16801 | CAN_CRITICAL_SECTION_ENTER(); |
| 16802 | ((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFS(mask); |
| 16803 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16804 | } |
| 16805 | |
| 16806 | static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFS_bf(const void *const hw) |
| 16807 | { |
| 16808 | uint32_t tmp; |
| 16809 | tmp = ((Can *)hw)->TXEFC.reg; |
| 16810 | tmp = (tmp & CAN_TXEFC_EFS_Msk) >> CAN_TXEFC_EFS_Pos; |
| 16811 | return tmp; |
| 16812 | } |
| 16813 | |
| 16814 | static inline void hri_can_set_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) |
| 16815 | { |
| 16816 | CAN_CRITICAL_SECTION_ENTER(); |
| 16817 | ((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFWM(mask); |
| 16818 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16819 | } |
| 16820 | |
| 16821 | static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) |
| 16822 | { |
| 16823 | uint32_t tmp; |
| 16824 | tmp = ((Can *)hw)->TXEFC.reg; |
| 16825 | tmp = (tmp & CAN_TXEFC_EFWM(mask)) >> CAN_TXEFC_EFWM_Pos; |
| 16826 | return tmp; |
| 16827 | } |
| 16828 | |
| 16829 | static inline void hri_can_write_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t data) |
| 16830 | { |
| 16831 | uint32_t tmp; |
| 16832 | CAN_CRITICAL_SECTION_ENTER(); |
| 16833 | tmp = ((Can *)hw)->TXEFC.reg; |
| 16834 | tmp &= ~CAN_TXEFC_EFWM_Msk; |
| 16835 | tmp |= CAN_TXEFC_EFWM(data); |
| 16836 | ((Can *)hw)->TXEFC.reg = tmp; |
| 16837 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16838 | } |
| 16839 | |
| 16840 | static inline void hri_can_clear_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) |
| 16841 | { |
| 16842 | CAN_CRITICAL_SECTION_ENTER(); |
| 16843 | ((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFWM(mask); |
| 16844 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16845 | } |
| 16846 | |
| 16847 | static inline void hri_can_toggle_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) |
| 16848 | { |
| 16849 | CAN_CRITICAL_SECTION_ENTER(); |
| 16850 | ((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFWM(mask); |
| 16851 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16852 | } |
| 16853 | |
| 16854 | static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFWM_bf(const void *const hw) |
| 16855 | { |
| 16856 | uint32_t tmp; |
| 16857 | tmp = ((Can *)hw)->TXEFC.reg; |
| 16858 | tmp = (tmp & CAN_TXEFC_EFWM_Msk) >> CAN_TXEFC_EFWM_Pos; |
| 16859 | return tmp; |
| 16860 | } |
| 16861 | |
| 16862 | static inline void hri_can_set_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) |
| 16863 | { |
| 16864 | CAN_CRITICAL_SECTION_ENTER(); |
| 16865 | ((Can *)hw)->TXEFC.reg |= mask; |
| 16866 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16867 | } |
| 16868 | |
| 16869 | static inline hri_can_txefc_reg_t hri_can_get_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) |
| 16870 | { |
| 16871 | uint32_t tmp; |
| 16872 | tmp = ((Can *)hw)->TXEFC.reg; |
| 16873 | tmp &= mask; |
| 16874 | return tmp; |
| 16875 | } |
| 16876 | |
| 16877 | static inline void hri_can_write_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t data) |
| 16878 | { |
| 16879 | CAN_CRITICAL_SECTION_ENTER(); |
| 16880 | ((Can *)hw)->TXEFC.reg = data; |
| 16881 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16882 | } |
| 16883 | |
| 16884 | static inline void hri_can_clear_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) |
| 16885 | { |
| 16886 | CAN_CRITICAL_SECTION_ENTER(); |
| 16887 | ((Can *)hw)->TXEFC.reg &= ~mask; |
| 16888 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16889 | } |
| 16890 | |
| 16891 | static inline void hri_can_toggle_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) |
| 16892 | { |
| 16893 | CAN_CRITICAL_SECTION_ENTER(); |
| 16894 | ((Can *)hw)->TXEFC.reg ^= mask; |
| 16895 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16896 | } |
| 16897 | |
| 16898 | static inline hri_can_txefc_reg_t hri_can_read_TXEFC_reg(const void *const hw) |
| 16899 | { |
| 16900 | return ((Can *)hw)->TXEFC.reg; |
| 16901 | } |
| 16902 | |
| 16903 | static inline void hri_can_set_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) |
| 16904 | { |
| 16905 | CAN_CRITICAL_SECTION_ENTER(); |
| 16906 | ((Can *)hw)->TXEFA.reg |= CAN_TXEFA_EFAI(mask); |
| 16907 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16908 | } |
| 16909 | |
| 16910 | static inline hri_can_txefa_reg_t hri_can_get_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) |
| 16911 | { |
| 16912 | uint32_t tmp; |
| 16913 | tmp = ((Can *)hw)->TXEFA.reg; |
| 16914 | tmp = (tmp & CAN_TXEFA_EFAI(mask)) >> CAN_TXEFA_EFAI_Pos; |
| 16915 | return tmp; |
| 16916 | } |
| 16917 | |
| 16918 | static inline void hri_can_write_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t data) |
| 16919 | { |
| 16920 | uint32_t tmp; |
| 16921 | CAN_CRITICAL_SECTION_ENTER(); |
| 16922 | tmp = ((Can *)hw)->TXEFA.reg; |
| 16923 | tmp &= ~CAN_TXEFA_EFAI_Msk; |
| 16924 | tmp |= CAN_TXEFA_EFAI(data); |
| 16925 | ((Can *)hw)->TXEFA.reg = tmp; |
| 16926 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16927 | } |
| 16928 | |
| 16929 | static inline void hri_can_clear_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) |
| 16930 | { |
| 16931 | CAN_CRITICAL_SECTION_ENTER(); |
| 16932 | ((Can *)hw)->TXEFA.reg &= ~CAN_TXEFA_EFAI(mask); |
| 16933 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16934 | } |
| 16935 | |
| 16936 | static inline void hri_can_toggle_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) |
| 16937 | { |
| 16938 | CAN_CRITICAL_SECTION_ENTER(); |
| 16939 | ((Can *)hw)->TXEFA.reg ^= CAN_TXEFA_EFAI(mask); |
| 16940 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16941 | } |
| 16942 | |
| 16943 | static inline hri_can_txefa_reg_t hri_can_read_TXEFA_EFAI_bf(const void *const hw) |
| 16944 | { |
| 16945 | uint32_t tmp; |
| 16946 | tmp = ((Can *)hw)->TXEFA.reg; |
| 16947 | tmp = (tmp & CAN_TXEFA_EFAI_Msk) >> CAN_TXEFA_EFAI_Pos; |
| 16948 | return tmp; |
| 16949 | } |
| 16950 | |
| 16951 | static inline void hri_can_set_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) |
| 16952 | { |
| 16953 | CAN_CRITICAL_SECTION_ENTER(); |
| 16954 | ((Can *)hw)->TXEFA.reg |= mask; |
| 16955 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16956 | } |
| 16957 | |
| 16958 | static inline hri_can_txefa_reg_t hri_can_get_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) |
| 16959 | { |
| 16960 | uint32_t tmp; |
| 16961 | tmp = ((Can *)hw)->TXEFA.reg; |
| 16962 | tmp &= mask; |
| 16963 | return tmp; |
| 16964 | } |
| 16965 | |
| 16966 | static inline void hri_can_write_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t data) |
| 16967 | { |
| 16968 | CAN_CRITICAL_SECTION_ENTER(); |
| 16969 | ((Can *)hw)->TXEFA.reg = data; |
| 16970 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16971 | } |
| 16972 | |
| 16973 | static inline void hri_can_clear_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) |
| 16974 | { |
| 16975 | CAN_CRITICAL_SECTION_ENTER(); |
| 16976 | ((Can *)hw)->TXEFA.reg &= ~mask; |
| 16977 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16978 | } |
| 16979 | |
| 16980 | static inline void hri_can_toggle_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) |
| 16981 | { |
| 16982 | CAN_CRITICAL_SECTION_ENTER(); |
| 16983 | ((Can *)hw)->TXEFA.reg ^= mask; |
| 16984 | CAN_CRITICAL_SECTION_LEAVE(); |
| 16985 | } |
| 16986 | |
| 16987 | static inline hri_can_txefa_reg_t hri_can_read_TXEFA_reg(const void *const hw) |
| 16988 | { |
| 16989 | return ((Can *)hw)->TXEFA.reg; |
| 16990 | } |
| 16991 | |
| 16992 | #ifdef __cplusplus |
| 16993 | } |
| 16994 | #endif |
| 16995 | |
| 16996 | #endif /* _HRI_CAN_E54_H_INCLUDED */ |
| 16997 | #endif /* _SAME54_CAN_COMPONENT_ */ |