Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM AES |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_AES_COMPONENT_ |
| 35 | #ifndef _HRI_AES_E54_H_INCLUDED_ |
| 36 | #define _HRI_AES_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_AES_CRITICAL_SECTIONS) |
| 46 | #define AES_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define AES_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define AES_CRITICAL_SECTION_ENTER() |
| 50 | #define AES_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint32_t hri_aes_ciplen_reg_t; |
| 54 | typedef uint32_t hri_aes_ctrla_reg_t; |
| 55 | typedef uint32_t hri_aes_ghash_reg_t; |
| 56 | typedef uint32_t hri_aes_hashkey_reg_t; |
| 57 | typedef uint32_t hri_aes_indata_reg_t; |
| 58 | typedef uint32_t hri_aes_intvectv_reg_t; |
| 59 | typedef uint32_t hri_aes_keyword_reg_t; |
| 60 | typedef uint32_t hri_aes_randseed_reg_t; |
| 61 | typedef uint8_t hri_aes_ctrlb_reg_t; |
| 62 | typedef uint8_t hri_aes_databufptr_reg_t; |
| 63 | typedef uint8_t hri_aes_dbgctrl_reg_t; |
| 64 | typedef uint8_t hri_aes_intenset_reg_t; |
| 65 | typedef uint8_t hri_aes_intflag_reg_t; |
| 66 | |
| 67 | static inline bool hri_aes_get_INTFLAG_ENCCMP_bit(const void *const hw) |
| 68 | { |
| 69 | return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos; |
| 70 | } |
| 71 | |
| 72 | static inline void hri_aes_clear_INTFLAG_ENCCMP_bit(const void *const hw) |
| 73 | { |
| 74 | ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP; |
| 75 | } |
| 76 | |
| 77 | static inline bool hri_aes_get_INTFLAG_GFMCMP_bit(const void *const hw) |
| 78 | { |
| 79 | return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos; |
| 80 | } |
| 81 | |
| 82 | static inline void hri_aes_clear_INTFLAG_GFMCMP_bit(const void *const hw) |
| 83 | { |
| 84 | ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP; |
| 85 | } |
| 86 | |
| 87 | static inline bool hri_aes_get_interrupt_ENCCMP_bit(const void *const hw) |
| 88 | { |
| 89 | return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos; |
| 90 | } |
| 91 | |
| 92 | static inline void hri_aes_clear_interrupt_ENCCMP_bit(const void *const hw) |
| 93 | { |
| 94 | ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP; |
| 95 | } |
| 96 | |
| 97 | static inline bool hri_aes_get_interrupt_GFMCMP_bit(const void *const hw) |
| 98 | { |
| 99 | return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos; |
| 100 | } |
| 101 | |
| 102 | static inline void hri_aes_clear_interrupt_GFMCMP_bit(const void *const hw) |
| 103 | { |
| 104 | ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP; |
| 105 | } |
| 106 | |
| 107 | static inline hri_aes_intflag_reg_t hri_aes_get_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask) |
| 108 | { |
| 109 | uint8_t tmp; |
| 110 | tmp = ((Aes *)hw)->INTFLAG.reg; |
| 111 | tmp &= mask; |
| 112 | return tmp; |
| 113 | } |
| 114 | |
| 115 | static inline hri_aes_intflag_reg_t hri_aes_read_INTFLAG_reg(const void *const hw) |
| 116 | { |
| 117 | return ((Aes *)hw)->INTFLAG.reg; |
| 118 | } |
| 119 | |
| 120 | static inline void hri_aes_clear_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask) |
| 121 | { |
| 122 | ((Aes *)hw)->INTFLAG.reg = mask; |
| 123 | } |
| 124 | |
| 125 | static inline void hri_aes_set_INTEN_ENCCMP_bit(const void *const hw) |
| 126 | { |
| 127 | ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; |
| 128 | } |
| 129 | |
| 130 | static inline bool hri_aes_get_INTEN_ENCCMP_bit(const void *const hw) |
| 131 | { |
| 132 | return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_ENCCMP) >> AES_INTENSET_ENCCMP_Pos; |
| 133 | } |
| 134 | |
| 135 | static inline void hri_aes_write_INTEN_ENCCMP_bit(const void *const hw, bool value) |
| 136 | { |
| 137 | if (value == 0x0) { |
| 138 | ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; |
| 139 | } else { |
| 140 | ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; |
| 141 | } |
| 142 | } |
| 143 | |
| 144 | static inline void hri_aes_clear_INTEN_ENCCMP_bit(const void *const hw) |
| 145 | { |
| 146 | ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; |
| 147 | } |
| 148 | |
| 149 | static inline void hri_aes_set_INTEN_GFMCMP_bit(const void *const hw) |
| 150 | { |
| 151 | ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; |
| 152 | } |
| 153 | |
| 154 | static inline bool hri_aes_get_INTEN_GFMCMP_bit(const void *const hw) |
| 155 | { |
| 156 | return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_GFMCMP) >> AES_INTENSET_GFMCMP_Pos; |
| 157 | } |
| 158 | |
| 159 | static inline void hri_aes_write_INTEN_GFMCMP_bit(const void *const hw, bool value) |
| 160 | { |
| 161 | if (value == 0x0) { |
| 162 | ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; |
| 163 | } else { |
| 164 | ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; |
| 165 | } |
| 166 | } |
| 167 | |
| 168 | static inline void hri_aes_clear_INTEN_GFMCMP_bit(const void *const hw) |
| 169 | { |
| 170 | ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; |
| 171 | } |
| 172 | |
| 173 | static inline void hri_aes_set_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) |
| 174 | { |
| 175 | ((Aes *)hw)->INTENSET.reg = mask; |
| 176 | } |
| 177 | |
| 178 | static inline hri_aes_intenset_reg_t hri_aes_get_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) |
| 179 | { |
| 180 | uint8_t tmp; |
| 181 | tmp = ((Aes *)hw)->INTENSET.reg; |
| 182 | tmp &= mask; |
| 183 | return tmp; |
| 184 | } |
| 185 | |
| 186 | static inline hri_aes_intenset_reg_t hri_aes_read_INTEN_reg(const void *const hw) |
| 187 | { |
| 188 | return ((Aes *)hw)->INTENSET.reg; |
| 189 | } |
| 190 | |
| 191 | static inline void hri_aes_write_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t data) |
| 192 | { |
| 193 | ((Aes *)hw)->INTENSET.reg = data; |
| 194 | ((Aes *)hw)->INTENCLR.reg = ~data; |
| 195 | } |
| 196 | |
| 197 | static inline void hri_aes_clear_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) |
| 198 | { |
| 199 | ((Aes *)hw)->INTENCLR.reg = mask; |
| 200 | } |
| 201 | |
| 202 | static inline void hri_aes_set_CTRLA_SWRST_bit(const void *const hw) |
| 203 | { |
| 204 | AES_CRITICAL_SECTION_ENTER(); |
| 205 | ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_SWRST; |
| 206 | AES_CRITICAL_SECTION_LEAVE(); |
| 207 | } |
| 208 | |
| 209 | static inline bool hri_aes_get_CTRLA_SWRST_bit(const void *const hw) |
| 210 | { |
| 211 | uint32_t tmp; |
| 212 | tmp = ((Aes *)hw)->CTRLA.reg; |
| 213 | tmp = (tmp & AES_CTRLA_SWRST) >> AES_CTRLA_SWRST_Pos; |
| 214 | return (bool)tmp; |
| 215 | } |
| 216 | |
| 217 | static inline void hri_aes_set_CTRLA_ENABLE_bit(const void *const hw) |
| 218 | { |
| 219 | AES_CRITICAL_SECTION_ENTER(); |
| 220 | ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_ENABLE; |
| 221 | AES_CRITICAL_SECTION_LEAVE(); |
| 222 | } |
| 223 | |
| 224 | static inline bool hri_aes_get_CTRLA_ENABLE_bit(const void *const hw) |
| 225 | { |
| 226 | uint32_t tmp; |
| 227 | tmp = ((Aes *)hw)->CTRLA.reg; |
| 228 | tmp = (tmp & AES_CTRLA_ENABLE) >> AES_CTRLA_ENABLE_Pos; |
| 229 | return (bool)tmp; |
| 230 | } |
| 231 | |
| 232 | static inline void hri_aes_write_CTRLA_ENABLE_bit(const void *const hw, bool value) |
| 233 | { |
| 234 | uint32_t tmp; |
| 235 | AES_CRITICAL_SECTION_ENTER(); |
| 236 | tmp = ((Aes *)hw)->CTRLA.reg; |
| 237 | tmp &= ~AES_CTRLA_ENABLE; |
| 238 | tmp |= value << AES_CTRLA_ENABLE_Pos; |
| 239 | ((Aes *)hw)->CTRLA.reg = tmp; |
| 240 | AES_CRITICAL_SECTION_LEAVE(); |
| 241 | } |
| 242 | |
| 243 | static inline void hri_aes_clear_CTRLA_ENABLE_bit(const void *const hw) |
| 244 | { |
| 245 | AES_CRITICAL_SECTION_ENTER(); |
| 246 | ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_ENABLE; |
| 247 | AES_CRITICAL_SECTION_LEAVE(); |
| 248 | } |
| 249 | |
| 250 | static inline void hri_aes_toggle_CTRLA_ENABLE_bit(const void *const hw) |
| 251 | { |
| 252 | AES_CRITICAL_SECTION_ENTER(); |
| 253 | ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_ENABLE; |
| 254 | AES_CRITICAL_SECTION_LEAVE(); |
| 255 | } |
| 256 | |
| 257 | static inline void hri_aes_set_CTRLA_CIPHER_bit(const void *const hw) |
| 258 | { |
| 259 | AES_CRITICAL_SECTION_ENTER(); |
| 260 | ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CIPHER; |
| 261 | AES_CRITICAL_SECTION_LEAVE(); |
| 262 | } |
| 263 | |
| 264 | static inline bool hri_aes_get_CTRLA_CIPHER_bit(const void *const hw) |
| 265 | { |
| 266 | uint32_t tmp; |
| 267 | tmp = ((Aes *)hw)->CTRLA.reg; |
| 268 | tmp = (tmp & AES_CTRLA_CIPHER) >> AES_CTRLA_CIPHER_Pos; |
| 269 | return (bool)tmp; |
| 270 | } |
| 271 | |
| 272 | static inline void hri_aes_write_CTRLA_CIPHER_bit(const void *const hw, bool value) |
| 273 | { |
| 274 | uint32_t tmp; |
| 275 | AES_CRITICAL_SECTION_ENTER(); |
| 276 | tmp = ((Aes *)hw)->CTRLA.reg; |
| 277 | tmp &= ~AES_CTRLA_CIPHER; |
| 278 | tmp |= value << AES_CTRLA_CIPHER_Pos; |
| 279 | ((Aes *)hw)->CTRLA.reg = tmp; |
| 280 | AES_CRITICAL_SECTION_LEAVE(); |
| 281 | } |
| 282 | |
| 283 | static inline void hri_aes_clear_CTRLA_CIPHER_bit(const void *const hw) |
| 284 | { |
| 285 | AES_CRITICAL_SECTION_ENTER(); |
| 286 | ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CIPHER; |
| 287 | AES_CRITICAL_SECTION_LEAVE(); |
| 288 | } |
| 289 | |
| 290 | static inline void hri_aes_toggle_CTRLA_CIPHER_bit(const void *const hw) |
| 291 | { |
| 292 | AES_CRITICAL_SECTION_ENTER(); |
| 293 | ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CIPHER; |
| 294 | AES_CRITICAL_SECTION_LEAVE(); |
| 295 | } |
| 296 | |
| 297 | static inline void hri_aes_set_CTRLA_STARTMODE_bit(const void *const hw) |
| 298 | { |
| 299 | AES_CRITICAL_SECTION_ENTER(); |
| 300 | ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_STARTMODE; |
| 301 | AES_CRITICAL_SECTION_LEAVE(); |
| 302 | } |
| 303 | |
| 304 | static inline bool hri_aes_get_CTRLA_STARTMODE_bit(const void *const hw) |
| 305 | { |
| 306 | uint32_t tmp; |
| 307 | tmp = ((Aes *)hw)->CTRLA.reg; |
| 308 | tmp = (tmp & AES_CTRLA_STARTMODE) >> AES_CTRLA_STARTMODE_Pos; |
| 309 | return (bool)tmp; |
| 310 | } |
| 311 | |
| 312 | static inline void hri_aes_write_CTRLA_STARTMODE_bit(const void *const hw, bool value) |
| 313 | { |
| 314 | uint32_t tmp; |
| 315 | AES_CRITICAL_SECTION_ENTER(); |
| 316 | tmp = ((Aes *)hw)->CTRLA.reg; |
| 317 | tmp &= ~AES_CTRLA_STARTMODE; |
| 318 | tmp |= value << AES_CTRLA_STARTMODE_Pos; |
| 319 | ((Aes *)hw)->CTRLA.reg = tmp; |
| 320 | AES_CRITICAL_SECTION_LEAVE(); |
| 321 | } |
| 322 | |
| 323 | static inline void hri_aes_clear_CTRLA_STARTMODE_bit(const void *const hw) |
| 324 | { |
| 325 | AES_CRITICAL_SECTION_ENTER(); |
| 326 | ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_STARTMODE; |
| 327 | AES_CRITICAL_SECTION_LEAVE(); |
| 328 | } |
| 329 | |
| 330 | static inline void hri_aes_toggle_CTRLA_STARTMODE_bit(const void *const hw) |
| 331 | { |
| 332 | AES_CRITICAL_SECTION_ENTER(); |
| 333 | ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_STARTMODE; |
| 334 | AES_CRITICAL_SECTION_LEAVE(); |
| 335 | } |
| 336 | |
| 337 | static inline void hri_aes_set_CTRLA_LOD_bit(const void *const hw) |
| 338 | { |
| 339 | AES_CRITICAL_SECTION_ENTER(); |
| 340 | ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_LOD; |
| 341 | AES_CRITICAL_SECTION_LEAVE(); |
| 342 | } |
| 343 | |
| 344 | static inline bool hri_aes_get_CTRLA_LOD_bit(const void *const hw) |
| 345 | { |
| 346 | uint32_t tmp; |
| 347 | tmp = ((Aes *)hw)->CTRLA.reg; |
| 348 | tmp = (tmp & AES_CTRLA_LOD) >> AES_CTRLA_LOD_Pos; |
| 349 | return (bool)tmp; |
| 350 | } |
| 351 | |
| 352 | static inline void hri_aes_write_CTRLA_LOD_bit(const void *const hw, bool value) |
| 353 | { |
| 354 | uint32_t tmp; |
| 355 | AES_CRITICAL_SECTION_ENTER(); |
| 356 | tmp = ((Aes *)hw)->CTRLA.reg; |
| 357 | tmp &= ~AES_CTRLA_LOD; |
| 358 | tmp |= value << AES_CTRLA_LOD_Pos; |
| 359 | ((Aes *)hw)->CTRLA.reg = tmp; |
| 360 | AES_CRITICAL_SECTION_LEAVE(); |
| 361 | } |
| 362 | |
| 363 | static inline void hri_aes_clear_CTRLA_LOD_bit(const void *const hw) |
| 364 | { |
| 365 | AES_CRITICAL_SECTION_ENTER(); |
| 366 | ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_LOD; |
| 367 | AES_CRITICAL_SECTION_LEAVE(); |
| 368 | } |
| 369 | |
| 370 | static inline void hri_aes_toggle_CTRLA_LOD_bit(const void *const hw) |
| 371 | { |
| 372 | AES_CRITICAL_SECTION_ENTER(); |
| 373 | ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_LOD; |
| 374 | AES_CRITICAL_SECTION_LEAVE(); |
| 375 | } |
| 376 | |
| 377 | static inline void hri_aes_set_CTRLA_KEYGEN_bit(const void *const hw) |
| 378 | { |
| 379 | AES_CRITICAL_SECTION_ENTER(); |
| 380 | ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYGEN; |
| 381 | AES_CRITICAL_SECTION_LEAVE(); |
| 382 | } |
| 383 | |
| 384 | static inline bool hri_aes_get_CTRLA_KEYGEN_bit(const void *const hw) |
| 385 | { |
| 386 | uint32_t tmp; |
| 387 | tmp = ((Aes *)hw)->CTRLA.reg; |
| 388 | tmp = (tmp & AES_CTRLA_KEYGEN) >> AES_CTRLA_KEYGEN_Pos; |
| 389 | return (bool)tmp; |
| 390 | } |
| 391 | |
| 392 | static inline void hri_aes_write_CTRLA_KEYGEN_bit(const void *const hw, bool value) |
| 393 | { |
| 394 | uint32_t tmp; |
| 395 | AES_CRITICAL_SECTION_ENTER(); |
| 396 | tmp = ((Aes *)hw)->CTRLA.reg; |
| 397 | tmp &= ~AES_CTRLA_KEYGEN; |
| 398 | tmp |= value << AES_CTRLA_KEYGEN_Pos; |
| 399 | ((Aes *)hw)->CTRLA.reg = tmp; |
| 400 | AES_CRITICAL_SECTION_LEAVE(); |
| 401 | } |
| 402 | |
| 403 | static inline void hri_aes_clear_CTRLA_KEYGEN_bit(const void *const hw) |
| 404 | { |
| 405 | AES_CRITICAL_SECTION_ENTER(); |
| 406 | ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYGEN; |
| 407 | AES_CRITICAL_SECTION_LEAVE(); |
| 408 | } |
| 409 | |
| 410 | static inline void hri_aes_toggle_CTRLA_KEYGEN_bit(const void *const hw) |
| 411 | { |
| 412 | AES_CRITICAL_SECTION_ENTER(); |
| 413 | ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYGEN; |
| 414 | AES_CRITICAL_SECTION_LEAVE(); |
| 415 | } |
| 416 | |
| 417 | static inline void hri_aes_set_CTRLA_XORKEY_bit(const void *const hw) |
| 418 | { |
| 419 | AES_CRITICAL_SECTION_ENTER(); |
| 420 | ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_XORKEY; |
| 421 | AES_CRITICAL_SECTION_LEAVE(); |
| 422 | } |
| 423 | |
| 424 | static inline bool hri_aes_get_CTRLA_XORKEY_bit(const void *const hw) |
| 425 | { |
| 426 | uint32_t tmp; |
| 427 | tmp = ((Aes *)hw)->CTRLA.reg; |
| 428 | tmp = (tmp & AES_CTRLA_XORKEY) >> AES_CTRLA_XORKEY_Pos; |
| 429 | return (bool)tmp; |
| 430 | } |
| 431 | |
| 432 | static inline void hri_aes_write_CTRLA_XORKEY_bit(const void *const hw, bool value) |
| 433 | { |
| 434 | uint32_t tmp; |
| 435 | AES_CRITICAL_SECTION_ENTER(); |
| 436 | tmp = ((Aes *)hw)->CTRLA.reg; |
| 437 | tmp &= ~AES_CTRLA_XORKEY; |
| 438 | tmp |= value << AES_CTRLA_XORKEY_Pos; |
| 439 | ((Aes *)hw)->CTRLA.reg = tmp; |
| 440 | AES_CRITICAL_SECTION_LEAVE(); |
| 441 | } |
| 442 | |
| 443 | static inline void hri_aes_clear_CTRLA_XORKEY_bit(const void *const hw) |
| 444 | { |
| 445 | AES_CRITICAL_SECTION_ENTER(); |
| 446 | ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_XORKEY; |
| 447 | AES_CRITICAL_SECTION_LEAVE(); |
| 448 | } |
| 449 | |
| 450 | static inline void hri_aes_toggle_CTRLA_XORKEY_bit(const void *const hw) |
| 451 | { |
| 452 | AES_CRITICAL_SECTION_ENTER(); |
| 453 | ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_XORKEY; |
| 454 | AES_CRITICAL_SECTION_LEAVE(); |
| 455 | } |
| 456 | |
| 457 | static inline void hri_aes_set_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) |
| 458 | { |
| 459 | AES_CRITICAL_SECTION_ENTER(); |
| 460 | ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_AESMODE(mask); |
| 461 | AES_CRITICAL_SECTION_LEAVE(); |
| 462 | } |
| 463 | |
| 464 | static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) |
| 465 | { |
| 466 | uint32_t tmp; |
| 467 | tmp = ((Aes *)hw)->CTRLA.reg; |
| 468 | tmp = (tmp & AES_CTRLA_AESMODE(mask)) >> AES_CTRLA_AESMODE_Pos; |
| 469 | return tmp; |
| 470 | } |
| 471 | |
| 472 | static inline void hri_aes_write_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t data) |
| 473 | { |
| 474 | uint32_t tmp; |
| 475 | AES_CRITICAL_SECTION_ENTER(); |
| 476 | tmp = ((Aes *)hw)->CTRLA.reg; |
| 477 | tmp &= ~AES_CTRLA_AESMODE_Msk; |
| 478 | tmp |= AES_CTRLA_AESMODE(data); |
| 479 | ((Aes *)hw)->CTRLA.reg = tmp; |
| 480 | AES_CRITICAL_SECTION_LEAVE(); |
| 481 | } |
| 482 | |
| 483 | static inline void hri_aes_clear_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) |
| 484 | { |
| 485 | AES_CRITICAL_SECTION_ENTER(); |
| 486 | ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_AESMODE(mask); |
| 487 | AES_CRITICAL_SECTION_LEAVE(); |
| 488 | } |
| 489 | |
| 490 | static inline void hri_aes_toggle_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) |
| 491 | { |
| 492 | AES_CRITICAL_SECTION_ENTER(); |
| 493 | ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_AESMODE(mask); |
| 494 | AES_CRITICAL_SECTION_LEAVE(); |
| 495 | } |
| 496 | |
| 497 | static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_AESMODE_bf(const void *const hw) |
| 498 | { |
| 499 | uint32_t tmp; |
| 500 | tmp = ((Aes *)hw)->CTRLA.reg; |
| 501 | tmp = (tmp & AES_CTRLA_AESMODE_Msk) >> AES_CTRLA_AESMODE_Pos; |
| 502 | return tmp; |
| 503 | } |
| 504 | |
| 505 | static inline void hri_aes_set_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) |
| 506 | { |
| 507 | AES_CRITICAL_SECTION_ENTER(); |
| 508 | ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CFBS(mask); |
| 509 | AES_CRITICAL_SECTION_LEAVE(); |
| 510 | } |
| 511 | |
| 512 | static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) |
| 513 | { |
| 514 | uint32_t tmp; |
| 515 | tmp = ((Aes *)hw)->CTRLA.reg; |
| 516 | tmp = (tmp & AES_CTRLA_CFBS(mask)) >> AES_CTRLA_CFBS_Pos; |
| 517 | return tmp; |
| 518 | } |
| 519 | |
| 520 | static inline void hri_aes_write_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t data) |
| 521 | { |
| 522 | uint32_t tmp; |
| 523 | AES_CRITICAL_SECTION_ENTER(); |
| 524 | tmp = ((Aes *)hw)->CTRLA.reg; |
| 525 | tmp &= ~AES_CTRLA_CFBS_Msk; |
| 526 | tmp |= AES_CTRLA_CFBS(data); |
| 527 | ((Aes *)hw)->CTRLA.reg = tmp; |
| 528 | AES_CRITICAL_SECTION_LEAVE(); |
| 529 | } |
| 530 | |
| 531 | static inline void hri_aes_clear_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) |
| 532 | { |
| 533 | AES_CRITICAL_SECTION_ENTER(); |
| 534 | ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CFBS(mask); |
| 535 | AES_CRITICAL_SECTION_LEAVE(); |
| 536 | } |
| 537 | |
| 538 | static inline void hri_aes_toggle_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) |
| 539 | { |
| 540 | AES_CRITICAL_SECTION_ENTER(); |
| 541 | ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CFBS(mask); |
| 542 | AES_CRITICAL_SECTION_LEAVE(); |
| 543 | } |
| 544 | |
| 545 | static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CFBS_bf(const void *const hw) |
| 546 | { |
| 547 | uint32_t tmp; |
| 548 | tmp = ((Aes *)hw)->CTRLA.reg; |
| 549 | tmp = (tmp & AES_CTRLA_CFBS_Msk) >> AES_CTRLA_CFBS_Pos; |
| 550 | return tmp; |
| 551 | } |
| 552 | |
| 553 | static inline void hri_aes_set_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) |
| 554 | { |
| 555 | AES_CRITICAL_SECTION_ENTER(); |
| 556 | ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYSIZE(mask); |
| 557 | AES_CRITICAL_SECTION_LEAVE(); |
| 558 | } |
| 559 | |
| 560 | static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) |
| 561 | { |
| 562 | uint32_t tmp; |
| 563 | tmp = ((Aes *)hw)->CTRLA.reg; |
| 564 | tmp = (tmp & AES_CTRLA_KEYSIZE(mask)) >> AES_CTRLA_KEYSIZE_Pos; |
| 565 | return tmp; |
| 566 | } |
| 567 | |
| 568 | static inline void hri_aes_write_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t data) |
| 569 | { |
| 570 | uint32_t tmp; |
| 571 | AES_CRITICAL_SECTION_ENTER(); |
| 572 | tmp = ((Aes *)hw)->CTRLA.reg; |
| 573 | tmp &= ~AES_CTRLA_KEYSIZE_Msk; |
| 574 | tmp |= AES_CTRLA_KEYSIZE(data); |
| 575 | ((Aes *)hw)->CTRLA.reg = tmp; |
| 576 | AES_CRITICAL_SECTION_LEAVE(); |
| 577 | } |
| 578 | |
| 579 | static inline void hri_aes_clear_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) |
| 580 | { |
| 581 | AES_CRITICAL_SECTION_ENTER(); |
| 582 | ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYSIZE(mask); |
| 583 | AES_CRITICAL_SECTION_LEAVE(); |
| 584 | } |
| 585 | |
| 586 | static inline void hri_aes_toggle_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) |
| 587 | { |
| 588 | AES_CRITICAL_SECTION_ENTER(); |
| 589 | ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYSIZE(mask); |
| 590 | AES_CRITICAL_SECTION_LEAVE(); |
| 591 | } |
| 592 | |
| 593 | static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_KEYSIZE_bf(const void *const hw) |
| 594 | { |
| 595 | uint32_t tmp; |
| 596 | tmp = ((Aes *)hw)->CTRLA.reg; |
| 597 | tmp = (tmp & AES_CTRLA_KEYSIZE_Msk) >> AES_CTRLA_KEYSIZE_Pos; |
| 598 | return tmp; |
| 599 | } |
| 600 | |
| 601 | static inline void hri_aes_set_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) |
| 602 | { |
| 603 | AES_CRITICAL_SECTION_ENTER(); |
| 604 | ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CTYPE(mask); |
| 605 | AES_CRITICAL_SECTION_LEAVE(); |
| 606 | } |
| 607 | |
| 608 | static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) |
| 609 | { |
| 610 | uint32_t tmp; |
| 611 | tmp = ((Aes *)hw)->CTRLA.reg; |
| 612 | tmp = (tmp & AES_CTRLA_CTYPE(mask)) >> AES_CTRLA_CTYPE_Pos; |
| 613 | return tmp; |
| 614 | } |
| 615 | |
| 616 | static inline void hri_aes_write_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t data) |
| 617 | { |
| 618 | uint32_t tmp; |
| 619 | AES_CRITICAL_SECTION_ENTER(); |
| 620 | tmp = ((Aes *)hw)->CTRLA.reg; |
| 621 | tmp &= ~AES_CTRLA_CTYPE_Msk; |
| 622 | tmp |= AES_CTRLA_CTYPE(data); |
| 623 | ((Aes *)hw)->CTRLA.reg = tmp; |
| 624 | AES_CRITICAL_SECTION_LEAVE(); |
| 625 | } |
| 626 | |
| 627 | static inline void hri_aes_clear_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) |
| 628 | { |
| 629 | AES_CRITICAL_SECTION_ENTER(); |
| 630 | ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CTYPE(mask); |
| 631 | AES_CRITICAL_SECTION_LEAVE(); |
| 632 | } |
| 633 | |
| 634 | static inline void hri_aes_toggle_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) |
| 635 | { |
| 636 | AES_CRITICAL_SECTION_ENTER(); |
| 637 | ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CTYPE(mask); |
| 638 | AES_CRITICAL_SECTION_LEAVE(); |
| 639 | } |
| 640 | |
| 641 | static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CTYPE_bf(const void *const hw) |
| 642 | { |
| 643 | uint32_t tmp; |
| 644 | tmp = ((Aes *)hw)->CTRLA.reg; |
| 645 | tmp = (tmp & AES_CTRLA_CTYPE_Msk) >> AES_CTRLA_CTYPE_Pos; |
| 646 | return tmp; |
| 647 | } |
| 648 | |
| 649 | static inline void hri_aes_set_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) |
| 650 | { |
| 651 | AES_CRITICAL_SECTION_ENTER(); |
| 652 | ((Aes *)hw)->CTRLA.reg |= mask; |
| 653 | AES_CRITICAL_SECTION_LEAVE(); |
| 654 | } |
| 655 | |
| 656 | static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) |
| 657 | { |
| 658 | uint32_t tmp; |
| 659 | tmp = ((Aes *)hw)->CTRLA.reg; |
| 660 | tmp &= mask; |
| 661 | return tmp; |
| 662 | } |
| 663 | |
| 664 | static inline void hri_aes_write_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t data) |
| 665 | { |
| 666 | AES_CRITICAL_SECTION_ENTER(); |
| 667 | ((Aes *)hw)->CTRLA.reg = data; |
| 668 | AES_CRITICAL_SECTION_LEAVE(); |
| 669 | } |
| 670 | |
| 671 | static inline void hri_aes_clear_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) |
| 672 | { |
| 673 | AES_CRITICAL_SECTION_ENTER(); |
| 674 | ((Aes *)hw)->CTRLA.reg &= ~mask; |
| 675 | AES_CRITICAL_SECTION_LEAVE(); |
| 676 | } |
| 677 | |
| 678 | static inline void hri_aes_toggle_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) |
| 679 | { |
| 680 | AES_CRITICAL_SECTION_ENTER(); |
| 681 | ((Aes *)hw)->CTRLA.reg ^= mask; |
| 682 | AES_CRITICAL_SECTION_LEAVE(); |
| 683 | } |
| 684 | |
| 685 | static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_reg(const void *const hw) |
| 686 | { |
| 687 | return ((Aes *)hw)->CTRLA.reg; |
| 688 | } |
| 689 | |
| 690 | static inline void hri_aes_set_CTRLB_START_bit(const void *const hw) |
| 691 | { |
| 692 | AES_CRITICAL_SECTION_ENTER(); |
| 693 | ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_START; |
| 694 | AES_CRITICAL_SECTION_LEAVE(); |
| 695 | } |
| 696 | |
| 697 | static inline bool hri_aes_get_CTRLB_START_bit(const void *const hw) |
| 698 | { |
| 699 | uint8_t tmp; |
| 700 | tmp = ((Aes *)hw)->CTRLB.reg; |
| 701 | tmp = (tmp & AES_CTRLB_START) >> AES_CTRLB_START_Pos; |
| 702 | return (bool)tmp; |
| 703 | } |
| 704 | |
| 705 | static inline void hri_aes_write_CTRLB_START_bit(const void *const hw, bool value) |
| 706 | { |
| 707 | uint8_t tmp; |
| 708 | AES_CRITICAL_SECTION_ENTER(); |
| 709 | tmp = ((Aes *)hw)->CTRLB.reg; |
| 710 | tmp &= ~AES_CTRLB_START; |
| 711 | tmp |= value << AES_CTRLB_START_Pos; |
| 712 | ((Aes *)hw)->CTRLB.reg = tmp; |
| 713 | AES_CRITICAL_SECTION_LEAVE(); |
| 714 | } |
| 715 | |
| 716 | static inline void hri_aes_clear_CTRLB_START_bit(const void *const hw) |
| 717 | { |
| 718 | AES_CRITICAL_SECTION_ENTER(); |
| 719 | ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_START; |
| 720 | AES_CRITICAL_SECTION_LEAVE(); |
| 721 | } |
| 722 | |
| 723 | static inline void hri_aes_toggle_CTRLB_START_bit(const void *const hw) |
| 724 | { |
| 725 | AES_CRITICAL_SECTION_ENTER(); |
| 726 | ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_START; |
| 727 | AES_CRITICAL_SECTION_LEAVE(); |
| 728 | } |
| 729 | |
| 730 | static inline void hri_aes_set_CTRLB_NEWMSG_bit(const void *const hw) |
| 731 | { |
| 732 | AES_CRITICAL_SECTION_ENTER(); |
| 733 | ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_NEWMSG; |
| 734 | AES_CRITICAL_SECTION_LEAVE(); |
| 735 | } |
| 736 | |
| 737 | static inline bool hri_aes_get_CTRLB_NEWMSG_bit(const void *const hw) |
| 738 | { |
| 739 | uint8_t tmp; |
| 740 | tmp = ((Aes *)hw)->CTRLB.reg; |
| 741 | tmp = (tmp & AES_CTRLB_NEWMSG) >> AES_CTRLB_NEWMSG_Pos; |
| 742 | return (bool)tmp; |
| 743 | } |
| 744 | |
| 745 | static inline void hri_aes_write_CTRLB_NEWMSG_bit(const void *const hw, bool value) |
| 746 | { |
| 747 | uint8_t tmp; |
| 748 | AES_CRITICAL_SECTION_ENTER(); |
| 749 | tmp = ((Aes *)hw)->CTRLB.reg; |
| 750 | tmp &= ~AES_CTRLB_NEWMSG; |
| 751 | tmp |= value << AES_CTRLB_NEWMSG_Pos; |
| 752 | ((Aes *)hw)->CTRLB.reg = tmp; |
| 753 | AES_CRITICAL_SECTION_LEAVE(); |
| 754 | } |
| 755 | |
| 756 | static inline void hri_aes_clear_CTRLB_NEWMSG_bit(const void *const hw) |
| 757 | { |
| 758 | AES_CRITICAL_SECTION_ENTER(); |
| 759 | ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_NEWMSG; |
| 760 | AES_CRITICAL_SECTION_LEAVE(); |
| 761 | } |
| 762 | |
| 763 | static inline void hri_aes_toggle_CTRLB_NEWMSG_bit(const void *const hw) |
| 764 | { |
| 765 | AES_CRITICAL_SECTION_ENTER(); |
| 766 | ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_NEWMSG; |
| 767 | AES_CRITICAL_SECTION_LEAVE(); |
| 768 | } |
| 769 | |
| 770 | static inline void hri_aes_set_CTRLB_EOM_bit(const void *const hw) |
| 771 | { |
| 772 | AES_CRITICAL_SECTION_ENTER(); |
| 773 | ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_EOM; |
| 774 | AES_CRITICAL_SECTION_LEAVE(); |
| 775 | } |
| 776 | |
| 777 | static inline bool hri_aes_get_CTRLB_EOM_bit(const void *const hw) |
| 778 | { |
| 779 | uint8_t tmp; |
| 780 | tmp = ((Aes *)hw)->CTRLB.reg; |
| 781 | tmp = (tmp & AES_CTRLB_EOM) >> AES_CTRLB_EOM_Pos; |
| 782 | return (bool)tmp; |
| 783 | } |
| 784 | |
| 785 | static inline void hri_aes_write_CTRLB_EOM_bit(const void *const hw, bool value) |
| 786 | { |
| 787 | uint8_t tmp; |
| 788 | AES_CRITICAL_SECTION_ENTER(); |
| 789 | tmp = ((Aes *)hw)->CTRLB.reg; |
| 790 | tmp &= ~AES_CTRLB_EOM; |
| 791 | tmp |= value << AES_CTRLB_EOM_Pos; |
| 792 | ((Aes *)hw)->CTRLB.reg = tmp; |
| 793 | AES_CRITICAL_SECTION_LEAVE(); |
| 794 | } |
| 795 | |
| 796 | static inline void hri_aes_clear_CTRLB_EOM_bit(const void *const hw) |
| 797 | { |
| 798 | AES_CRITICAL_SECTION_ENTER(); |
| 799 | ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_EOM; |
| 800 | AES_CRITICAL_SECTION_LEAVE(); |
| 801 | } |
| 802 | |
| 803 | static inline void hri_aes_toggle_CTRLB_EOM_bit(const void *const hw) |
| 804 | { |
| 805 | AES_CRITICAL_SECTION_ENTER(); |
| 806 | ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_EOM; |
| 807 | AES_CRITICAL_SECTION_LEAVE(); |
| 808 | } |
| 809 | |
| 810 | static inline void hri_aes_set_CTRLB_GFMUL_bit(const void *const hw) |
| 811 | { |
| 812 | AES_CRITICAL_SECTION_ENTER(); |
| 813 | ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_GFMUL; |
| 814 | AES_CRITICAL_SECTION_LEAVE(); |
| 815 | } |
| 816 | |
| 817 | static inline bool hri_aes_get_CTRLB_GFMUL_bit(const void *const hw) |
| 818 | { |
| 819 | uint8_t tmp; |
| 820 | tmp = ((Aes *)hw)->CTRLB.reg; |
| 821 | tmp = (tmp & AES_CTRLB_GFMUL) >> AES_CTRLB_GFMUL_Pos; |
| 822 | return (bool)tmp; |
| 823 | } |
| 824 | |
| 825 | static inline void hri_aes_write_CTRLB_GFMUL_bit(const void *const hw, bool value) |
| 826 | { |
| 827 | uint8_t tmp; |
| 828 | AES_CRITICAL_SECTION_ENTER(); |
| 829 | tmp = ((Aes *)hw)->CTRLB.reg; |
| 830 | tmp &= ~AES_CTRLB_GFMUL; |
| 831 | tmp |= value << AES_CTRLB_GFMUL_Pos; |
| 832 | ((Aes *)hw)->CTRLB.reg = tmp; |
| 833 | AES_CRITICAL_SECTION_LEAVE(); |
| 834 | } |
| 835 | |
| 836 | static inline void hri_aes_clear_CTRLB_GFMUL_bit(const void *const hw) |
| 837 | { |
| 838 | AES_CRITICAL_SECTION_ENTER(); |
| 839 | ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_GFMUL; |
| 840 | AES_CRITICAL_SECTION_LEAVE(); |
| 841 | } |
| 842 | |
| 843 | static inline void hri_aes_toggle_CTRLB_GFMUL_bit(const void *const hw) |
| 844 | { |
| 845 | AES_CRITICAL_SECTION_ENTER(); |
| 846 | ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_GFMUL; |
| 847 | AES_CRITICAL_SECTION_LEAVE(); |
| 848 | } |
| 849 | |
| 850 | static inline void hri_aes_set_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) |
| 851 | { |
| 852 | AES_CRITICAL_SECTION_ENTER(); |
| 853 | ((Aes *)hw)->CTRLB.reg |= mask; |
| 854 | AES_CRITICAL_SECTION_LEAVE(); |
| 855 | } |
| 856 | |
| 857 | static inline hri_aes_ctrlb_reg_t hri_aes_get_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) |
| 858 | { |
| 859 | uint8_t tmp; |
| 860 | tmp = ((Aes *)hw)->CTRLB.reg; |
| 861 | tmp &= mask; |
| 862 | return tmp; |
| 863 | } |
| 864 | |
| 865 | static inline void hri_aes_write_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t data) |
| 866 | { |
| 867 | AES_CRITICAL_SECTION_ENTER(); |
| 868 | ((Aes *)hw)->CTRLB.reg = data; |
| 869 | AES_CRITICAL_SECTION_LEAVE(); |
| 870 | } |
| 871 | |
| 872 | static inline void hri_aes_clear_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) |
| 873 | { |
| 874 | AES_CRITICAL_SECTION_ENTER(); |
| 875 | ((Aes *)hw)->CTRLB.reg &= ~mask; |
| 876 | AES_CRITICAL_SECTION_LEAVE(); |
| 877 | } |
| 878 | |
| 879 | static inline void hri_aes_toggle_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) |
| 880 | { |
| 881 | AES_CRITICAL_SECTION_ENTER(); |
| 882 | ((Aes *)hw)->CTRLB.reg ^= mask; |
| 883 | AES_CRITICAL_SECTION_LEAVE(); |
| 884 | } |
| 885 | |
| 886 | static inline hri_aes_ctrlb_reg_t hri_aes_read_CTRLB_reg(const void *const hw) |
| 887 | { |
| 888 | return ((Aes *)hw)->CTRLB.reg; |
| 889 | } |
| 890 | |
| 891 | static inline void hri_aes_set_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) |
| 892 | { |
| 893 | AES_CRITICAL_SECTION_ENTER(); |
| 894 | ((Aes *)hw)->DATABUFPTR.reg |= AES_DATABUFPTR_INDATAPTR(mask); |
| 895 | AES_CRITICAL_SECTION_LEAVE(); |
| 896 | } |
| 897 | |
| 898 | static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_INDATAPTR_bf(const void *const hw, |
| 899 | hri_aes_databufptr_reg_t mask) |
| 900 | { |
| 901 | uint8_t tmp; |
| 902 | tmp = ((Aes *)hw)->DATABUFPTR.reg; |
| 903 | tmp = (tmp & AES_DATABUFPTR_INDATAPTR(mask)) >> AES_DATABUFPTR_INDATAPTR_Pos; |
| 904 | return tmp; |
| 905 | } |
| 906 | |
| 907 | static inline void hri_aes_write_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t data) |
| 908 | { |
| 909 | uint8_t tmp; |
| 910 | AES_CRITICAL_SECTION_ENTER(); |
| 911 | tmp = ((Aes *)hw)->DATABUFPTR.reg; |
| 912 | tmp &= ~AES_DATABUFPTR_INDATAPTR_Msk; |
| 913 | tmp |= AES_DATABUFPTR_INDATAPTR(data); |
| 914 | ((Aes *)hw)->DATABUFPTR.reg = tmp; |
| 915 | AES_CRITICAL_SECTION_LEAVE(); |
| 916 | } |
| 917 | |
| 918 | static inline void hri_aes_clear_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) |
| 919 | { |
| 920 | AES_CRITICAL_SECTION_ENTER(); |
| 921 | ((Aes *)hw)->DATABUFPTR.reg &= ~AES_DATABUFPTR_INDATAPTR(mask); |
| 922 | AES_CRITICAL_SECTION_LEAVE(); |
| 923 | } |
| 924 | |
| 925 | static inline void hri_aes_toggle_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) |
| 926 | { |
| 927 | AES_CRITICAL_SECTION_ENTER(); |
| 928 | ((Aes *)hw)->DATABUFPTR.reg ^= AES_DATABUFPTR_INDATAPTR(mask); |
| 929 | AES_CRITICAL_SECTION_LEAVE(); |
| 930 | } |
| 931 | |
| 932 | static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_INDATAPTR_bf(const void *const hw) |
| 933 | { |
| 934 | uint8_t tmp; |
| 935 | tmp = ((Aes *)hw)->DATABUFPTR.reg; |
| 936 | tmp = (tmp & AES_DATABUFPTR_INDATAPTR_Msk) >> AES_DATABUFPTR_INDATAPTR_Pos; |
| 937 | return tmp; |
| 938 | } |
| 939 | |
| 940 | static inline void hri_aes_set_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) |
| 941 | { |
| 942 | AES_CRITICAL_SECTION_ENTER(); |
| 943 | ((Aes *)hw)->DATABUFPTR.reg |= mask; |
| 944 | AES_CRITICAL_SECTION_LEAVE(); |
| 945 | } |
| 946 | |
| 947 | static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) |
| 948 | { |
| 949 | uint8_t tmp; |
| 950 | tmp = ((Aes *)hw)->DATABUFPTR.reg; |
| 951 | tmp &= mask; |
| 952 | return tmp; |
| 953 | } |
| 954 | |
| 955 | static inline void hri_aes_write_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t data) |
| 956 | { |
| 957 | AES_CRITICAL_SECTION_ENTER(); |
| 958 | ((Aes *)hw)->DATABUFPTR.reg = data; |
| 959 | AES_CRITICAL_SECTION_LEAVE(); |
| 960 | } |
| 961 | |
| 962 | static inline void hri_aes_clear_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) |
| 963 | { |
| 964 | AES_CRITICAL_SECTION_ENTER(); |
| 965 | ((Aes *)hw)->DATABUFPTR.reg &= ~mask; |
| 966 | AES_CRITICAL_SECTION_LEAVE(); |
| 967 | } |
| 968 | |
| 969 | static inline void hri_aes_toggle_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) |
| 970 | { |
| 971 | AES_CRITICAL_SECTION_ENTER(); |
| 972 | ((Aes *)hw)->DATABUFPTR.reg ^= mask; |
| 973 | AES_CRITICAL_SECTION_LEAVE(); |
| 974 | } |
| 975 | |
| 976 | static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_reg(const void *const hw) |
| 977 | { |
| 978 | return ((Aes *)hw)->DATABUFPTR.reg; |
| 979 | } |
| 980 | |
| 981 | static inline void hri_aes_set_DBGCTRL_DBGRUN_bit(const void *const hw) |
| 982 | { |
| 983 | AES_CRITICAL_SECTION_ENTER(); |
| 984 | ((Aes *)hw)->DBGCTRL.reg |= AES_DBGCTRL_DBGRUN; |
| 985 | AES_CRITICAL_SECTION_LEAVE(); |
| 986 | } |
| 987 | |
| 988 | static inline bool hri_aes_get_DBGCTRL_DBGRUN_bit(const void *const hw) |
| 989 | { |
| 990 | uint8_t tmp; |
| 991 | tmp = ((Aes *)hw)->DBGCTRL.reg; |
| 992 | tmp = (tmp & AES_DBGCTRL_DBGRUN) >> AES_DBGCTRL_DBGRUN_Pos; |
| 993 | return (bool)tmp; |
| 994 | } |
| 995 | |
| 996 | static inline void hri_aes_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) |
| 997 | { |
| 998 | uint8_t tmp; |
| 999 | AES_CRITICAL_SECTION_ENTER(); |
| 1000 | tmp = ((Aes *)hw)->DBGCTRL.reg; |
| 1001 | tmp &= ~AES_DBGCTRL_DBGRUN; |
| 1002 | tmp |= value << AES_DBGCTRL_DBGRUN_Pos; |
| 1003 | ((Aes *)hw)->DBGCTRL.reg = tmp; |
| 1004 | AES_CRITICAL_SECTION_LEAVE(); |
| 1005 | } |
| 1006 | |
| 1007 | static inline void hri_aes_clear_DBGCTRL_DBGRUN_bit(const void *const hw) |
| 1008 | { |
| 1009 | AES_CRITICAL_SECTION_ENTER(); |
| 1010 | ((Aes *)hw)->DBGCTRL.reg &= ~AES_DBGCTRL_DBGRUN; |
| 1011 | AES_CRITICAL_SECTION_LEAVE(); |
| 1012 | } |
| 1013 | |
| 1014 | static inline void hri_aes_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) |
| 1015 | { |
| 1016 | AES_CRITICAL_SECTION_ENTER(); |
| 1017 | ((Aes *)hw)->DBGCTRL.reg ^= AES_DBGCTRL_DBGRUN; |
| 1018 | AES_CRITICAL_SECTION_LEAVE(); |
| 1019 | } |
| 1020 | |
| 1021 | static inline void hri_aes_set_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) |
| 1022 | { |
| 1023 | AES_CRITICAL_SECTION_ENTER(); |
| 1024 | ((Aes *)hw)->DBGCTRL.reg |= mask; |
| 1025 | AES_CRITICAL_SECTION_LEAVE(); |
| 1026 | } |
| 1027 | |
| 1028 | static inline hri_aes_dbgctrl_reg_t hri_aes_get_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) |
| 1029 | { |
| 1030 | uint8_t tmp; |
| 1031 | tmp = ((Aes *)hw)->DBGCTRL.reg; |
| 1032 | tmp &= mask; |
| 1033 | return tmp; |
| 1034 | } |
| 1035 | |
| 1036 | static inline void hri_aes_write_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t data) |
| 1037 | { |
| 1038 | AES_CRITICAL_SECTION_ENTER(); |
| 1039 | ((Aes *)hw)->DBGCTRL.reg = data; |
| 1040 | AES_CRITICAL_SECTION_LEAVE(); |
| 1041 | } |
| 1042 | |
| 1043 | static inline void hri_aes_clear_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) |
| 1044 | { |
| 1045 | AES_CRITICAL_SECTION_ENTER(); |
| 1046 | ((Aes *)hw)->DBGCTRL.reg &= ~mask; |
| 1047 | AES_CRITICAL_SECTION_LEAVE(); |
| 1048 | } |
| 1049 | |
| 1050 | static inline void hri_aes_toggle_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) |
| 1051 | { |
| 1052 | AES_CRITICAL_SECTION_ENTER(); |
| 1053 | ((Aes *)hw)->DBGCTRL.reg ^= mask; |
| 1054 | AES_CRITICAL_SECTION_LEAVE(); |
| 1055 | } |
| 1056 | |
| 1057 | static inline hri_aes_dbgctrl_reg_t hri_aes_read_DBGCTRL_reg(const void *const hw) |
| 1058 | { |
| 1059 | return ((Aes *)hw)->DBGCTRL.reg; |
| 1060 | } |
| 1061 | |
| 1062 | static inline void hri_aes_set_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) |
| 1063 | { |
| 1064 | AES_CRITICAL_SECTION_ENTER(); |
| 1065 | ((Aes *)hw)->INDATA.reg |= mask; |
| 1066 | AES_CRITICAL_SECTION_LEAVE(); |
| 1067 | } |
| 1068 | |
| 1069 | static inline hri_aes_indata_reg_t hri_aes_get_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) |
| 1070 | { |
| 1071 | uint32_t tmp; |
| 1072 | tmp = ((Aes *)hw)->INDATA.reg; |
| 1073 | tmp &= mask; |
| 1074 | return tmp; |
| 1075 | } |
| 1076 | |
| 1077 | static inline void hri_aes_write_INDATA_reg(const void *const hw, hri_aes_indata_reg_t data) |
| 1078 | { |
| 1079 | AES_CRITICAL_SECTION_ENTER(); |
| 1080 | ((Aes *)hw)->INDATA.reg = data; |
| 1081 | AES_CRITICAL_SECTION_LEAVE(); |
| 1082 | } |
| 1083 | |
| 1084 | static inline void hri_aes_clear_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) |
| 1085 | { |
| 1086 | AES_CRITICAL_SECTION_ENTER(); |
| 1087 | ((Aes *)hw)->INDATA.reg &= ~mask; |
| 1088 | AES_CRITICAL_SECTION_LEAVE(); |
| 1089 | } |
| 1090 | |
| 1091 | static inline void hri_aes_toggle_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) |
| 1092 | { |
| 1093 | AES_CRITICAL_SECTION_ENTER(); |
| 1094 | ((Aes *)hw)->INDATA.reg ^= mask; |
| 1095 | AES_CRITICAL_SECTION_LEAVE(); |
| 1096 | } |
| 1097 | |
| 1098 | static inline hri_aes_indata_reg_t hri_aes_read_INDATA_reg(const void *const hw) |
| 1099 | { |
| 1100 | return ((Aes *)hw)->INDATA.reg; |
| 1101 | } |
| 1102 | |
| 1103 | static inline void hri_aes_set_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) |
| 1104 | { |
| 1105 | AES_CRITICAL_SECTION_ENTER(); |
| 1106 | ((Aes *)hw)->HASHKEY[index].reg |= mask; |
| 1107 | AES_CRITICAL_SECTION_LEAVE(); |
| 1108 | } |
| 1109 | |
| 1110 | static inline hri_aes_hashkey_reg_t hri_aes_get_HASHKEY_reg(const void *const hw, uint8_t index, |
| 1111 | hri_aes_hashkey_reg_t mask) |
| 1112 | { |
| 1113 | uint32_t tmp; |
| 1114 | tmp = ((Aes *)hw)->HASHKEY[index].reg; |
| 1115 | tmp &= mask; |
| 1116 | return tmp; |
| 1117 | } |
| 1118 | |
| 1119 | static inline void hri_aes_write_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t data) |
| 1120 | { |
| 1121 | AES_CRITICAL_SECTION_ENTER(); |
| 1122 | ((Aes *)hw)->HASHKEY[index].reg = data; |
| 1123 | AES_CRITICAL_SECTION_LEAVE(); |
| 1124 | } |
| 1125 | |
| 1126 | static inline void hri_aes_clear_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) |
| 1127 | { |
| 1128 | AES_CRITICAL_SECTION_ENTER(); |
| 1129 | ((Aes *)hw)->HASHKEY[index].reg &= ~mask; |
| 1130 | AES_CRITICAL_SECTION_LEAVE(); |
| 1131 | } |
| 1132 | |
| 1133 | static inline void hri_aes_toggle_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) |
| 1134 | { |
| 1135 | AES_CRITICAL_SECTION_ENTER(); |
| 1136 | ((Aes *)hw)->HASHKEY[index].reg ^= mask; |
| 1137 | AES_CRITICAL_SECTION_LEAVE(); |
| 1138 | } |
| 1139 | |
| 1140 | static inline hri_aes_hashkey_reg_t hri_aes_read_HASHKEY_reg(const void *const hw, uint8_t index) |
| 1141 | { |
| 1142 | return ((Aes *)hw)->HASHKEY[index].reg; |
| 1143 | } |
| 1144 | |
| 1145 | static inline void hri_aes_set_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) |
| 1146 | { |
| 1147 | AES_CRITICAL_SECTION_ENTER(); |
| 1148 | ((Aes *)hw)->GHASH[index].reg |= mask; |
| 1149 | AES_CRITICAL_SECTION_LEAVE(); |
| 1150 | } |
| 1151 | |
| 1152 | static inline hri_aes_ghash_reg_t hri_aes_get_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) |
| 1153 | { |
| 1154 | uint32_t tmp; |
| 1155 | tmp = ((Aes *)hw)->GHASH[index].reg; |
| 1156 | tmp &= mask; |
| 1157 | return tmp; |
| 1158 | } |
| 1159 | |
| 1160 | static inline void hri_aes_write_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t data) |
| 1161 | { |
| 1162 | AES_CRITICAL_SECTION_ENTER(); |
| 1163 | ((Aes *)hw)->GHASH[index].reg = data; |
| 1164 | AES_CRITICAL_SECTION_LEAVE(); |
| 1165 | } |
| 1166 | |
| 1167 | static inline void hri_aes_clear_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) |
| 1168 | { |
| 1169 | AES_CRITICAL_SECTION_ENTER(); |
| 1170 | ((Aes *)hw)->GHASH[index].reg &= ~mask; |
| 1171 | AES_CRITICAL_SECTION_LEAVE(); |
| 1172 | } |
| 1173 | |
| 1174 | static inline void hri_aes_toggle_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) |
| 1175 | { |
| 1176 | AES_CRITICAL_SECTION_ENTER(); |
| 1177 | ((Aes *)hw)->GHASH[index].reg ^= mask; |
| 1178 | AES_CRITICAL_SECTION_LEAVE(); |
| 1179 | } |
| 1180 | |
| 1181 | static inline hri_aes_ghash_reg_t hri_aes_read_GHASH_reg(const void *const hw, uint8_t index) |
| 1182 | { |
| 1183 | return ((Aes *)hw)->GHASH[index].reg; |
| 1184 | } |
| 1185 | |
| 1186 | static inline void hri_aes_set_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) |
| 1187 | { |
| 1188 | AES_CRITICAL_SECTION_ENTER(); |
| 1189 | ((Aes *)hw)->CIPLEN.reg |= mask; |
| 1190 | AES_CRITICAL_SECTION_LEAVE(); |
| 1191 | } |
| 1192 | |
| 1193 | static inline hri_aes_ciplen_reg_t hri_aes_get_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) |
| 1194 | { |
| 1195 | uint32_t tmp; |
| 1196 | tmp = ((Aes *)hw)->CIPLEN.reg; |
| 1197 | tmp &= mask; |
| 1198 | return tmp; |
| 1199 | } |
| 1200 | |
| 1201 | static inline void hri_aes_write_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t data) |
| 1202 | { |
| 1203 | AES_CRITICAL_SECTION_ENTER(); |
| 1204 | ((Aes *)hw)->CIPLEN.reg = data; |
| 1205 | AES_CRITICAL_SECTION_LEAVE(); |
| 1206 | } |
| 1207 | |
| 1208 | static inline void hri_aes_clear_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) |
| 1209 | { |
| 1210 | AES_CRITICAL_SECTION_ENTER(); |
| 1211 | ((Aes *)hw)->CIPLEN.reg &= ~mask; |
| 1212 | AES_CRITICAL_SECTION_LEAVE(); |
| 1213 | } |
| 1214 | |
| 1215 | static inline void hri_aes_toggle_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) |
| 1216 | { |
| 1217 | AES_CRITICAL_SECTION_ENTER(); |
| 1218 | ((Aes *)hw)->CIPLEN.reg ^= mask; |
| 1219 | AES_CRITICAL_SECTION_LEAVE(); |
| 1220 | } |
| 1221 | |
| 1222 | static inline hri_aes_ciplen_reg_t hri_aes_read_CIPLEN_reg(const void *const hw) |
| 1223 | { |
| 1224 | return ((Aes *)hw)->CIPLEN.reg; |
| 1225 | } |
| 1226 | |
| 1227 | static inline void hri_aes_set_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) |
| 1228 | { |
| 1229 | AES_CRITICAL_SECTION_ENTER(); |
| 1230 | ((Aes *)hw)->RANDSEED.reg |= mask; |
| 1231 | AES_CRITICAL_SECTION_LEAVE(); |
| 1232 | } |
| 1233 | |
| 1234 | static inline hri_aes_randseed_reg_t hri_aes_get_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) |
| 1235 | { |
| 1236 | uint32_t tmp; |
| 1237 | tmp = ((Aes *)hw)->RANDSEED.reg; |
| 1238 | tmp &= mask; |
| 1239 | return tmp; |
| 1240 | } |
| 1241 | |
| 1242 | static inline void hri_aes_write_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t data) |
| 1243 | { |
| 1244 | AES_CRITICAL_SECTION_ENTER(); |
| 1245 | ((Aes *)hw)->RANDSEED.reg = data; |
| 1246 | AES_CRITICAL_SECTION_LEAVE(); |
| 1247 | } |
| 1248 | |
| 1249 | static inline void hri_aes_clear_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) |
| 1250 | { |
| 1251 | AES_CRITICAL_SECTION_ENTER(); |
| 1252 | ((Aes *)hw)->RANDSEED.reg &= ~mask; |
| 1253 | AES_CRITICAL_SECTION_LEAVE(); |
| 1254 | } |
| 1255 | |
| 1256 | static inline void hri_aes_toggle_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) |
| 1257 | { |
| 1258 | AES_CRITICAL_SECTION_ENTER(); |
| 1259 | ((Aes *)hw)->RANDSEED.reg ^= mask; |
| 1260 | AES_CRITICAL_SECTION_LEAVE(); |
| 1261 | } |
| 1262 | |
| 1263 | static inline hri_aes_randseed_reg_t hri_aes_read_RANDSEED_reg(const void *const hw) |
| 1264 | { |
| 1265 | return ((Aes *)hw)->RANDSEED.reg; |
| 1266 | } |
| 1267 | |
| 1268 | static inline void hri_aes_write_KEYWORD_reg(const void *const hw, uint8_t index, hri_aes_keyword_reg_t data) |
| 1269 | { |
| 1270 | AES_CRITICAL_SECTION_ENTER(); |
| 1271 | ((Aes *)hw)->KEYWORD[index].reg = data; |
| 1272 | AES_CRITICAL_SECTION_LEAVE(); |
| 1273 | } |
| 1274 | |
| 1275 | static inline void hri_aes_write_INTVECTV_reg(const void *const hw, uint8_t index, hri_aes_intvectv_reg_t data) |
| 1276 | { |
| 1277 | AES_CRITICAL_SECTION_ENTER(); |
| 1278 | ((Aes *)hw)->INTVECTV[index].reg = data; |
| 1279 | AES_CRITICAL_SECTION_LEAVE(); |
| 1280 | } |
| 1281 | |
| 1282 | #ifdef __cplusplus |
| 1283 | } |
| 1284 | #endif |
| 1285 | |
| 1286 | #endif /* _HRI_AES_E54_H_INCLUDED */ |
| 1287 | #endif /* _SAME54_AES_COMPONENT_ */ |