| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Peripheral I/O description for SAME54N19A
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54N19A_PIO_
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| 31 | #define _SAME54N19A_PIO_
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| 32 |
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| 33 | #define PIN_PA00 0 /**< \brief Pin Number for PA00 */
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| 34 | #define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */
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| 35 | #define PIN_PA01 1 /**< \brief Pin Number for PA01 */
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| 36 | #define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */
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| 37 | #define PIN_PA02 2 /**< \brief Pin Number for PA02 */
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| 38 | #define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */
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| 39 | #define PIN_PA03 3 /**< \brief Pin Number for PA03 */
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| 40 | #define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */
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| 41 | #define PIN_PA04 4 /**< \brief Pin Number for PA04 */
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| 42 | #define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */
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| 43 | #define PIN_PA05 5 /**< \brief Pin Number for PA05 */
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| 44 | #define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */
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| 45 | #define PIN_PA06 6 /**< \brief Pin Number for PA06 */
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| 46 | #define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */
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| 47 | #define PIN_PA07 7 /**< \brief Pin Number for PA07 */
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| 48 | #define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */
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| 49 | #define PIN_PA08 8 /**< \brief Pin Number for PA08 */
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| 50 | #define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */
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| 51 | #define PIN_PA09 9 /**< \brief Pin Number for PA09 */
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| 52 | #define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */
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| 53 | #define PIN_PA10 10 /**< \brief Pin Number for PA10 */
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| 54 | #define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */
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| 55 | #define PIN_PA11 11 /**< \brief Pin Number for PA11 */
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| 56 | #define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */
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| 57 | #define PIN_PA12 12 /**< \brief Pin Number for PA12 */
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| 58 | #define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */
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| 59 | #define PIN_PA13 13 /**< \brief Pin Number for PA13 */
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| 60 | #define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */
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| 61 | #define PIN_PA14 14 /**< \brief Pin Number for PA14 */
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| 62 | #define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */
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| 63 | #define PIN_PA15 15 /**< \brief Pin Number for PA15 */
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| 64 | #define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */
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| 65 | #define PIN_PA16 16 /**< \brief Pin Number for PA16 */
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| 66 | #define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */
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| 67 | #define PIN_PA17 17 /**< \brief Pin Number for PA17 */
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| 68 | #define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */
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| 69 | #define PIN_PA18 18 /**< \brief Pin Number for PA18 */
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| 70 | #define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */
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| 71 | #define PIN_PA19 19 /**< \brief Pin Number for PA19 */
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| 72 | #define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */
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| 73 | #define PIN_PA20 20 /**< \brief Pin Number for PA20 */
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| 74 | #define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */
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| 75 | #define PIN_PA21 21 /**< \brief Pin Number for PA21 */
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| 76 | #define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */
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| 77 | #define PIN_PA22 22 /**< \brief Pin Number for PA22 */
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| 78 | #define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */
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| 79 | #define PIN_PA23 23 /**< \brief Pin Number for PA23 */
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| 80 | #define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */
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| 81 | #define PIN_PA24 24 /**< \brief Pin Number for PA24 */
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| 82 | #define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */
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| 83 | #define PIN_PA25 25 /**< \brief Pin Number for PA25 */
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| 84 | #define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */
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| 85 | #define PIN_PA27 27 /**< \brief Pin Number for PA27 */
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| 86 | #define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */
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| 87 | #define PIN_PA30 30 /**< \brief Pin Number for PA30 */
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| 88 | #define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */
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| 89 | #define PIN_PA31 31 /**< \brief Pin Number for PA31 */
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| 90 | #define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */
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| 91 | #define PIN_PB00 32 /**< \brief Pin Number for PB00 */
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| 92 | #define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */
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| 93 | #define PIN_PB01 33 /**< \brief Pin Number for PB01 */
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| 94 | #define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */
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| 95 | #define PIN_PB02 34 /**< \brief Pin Number for PB02 */
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| 96 | #define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */
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| 97 | #define PIN_PB03 35 /**< \brief Pin Number for PB03 */
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| 98 | #define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */
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| 99 | #define PIN_PB04 36 /**< \brief Pin Number for PB04 */
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| 100 | #define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */
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| 101 | #define PIN_PB05 37 /**< \brief Pin Number for PB05 */
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| 102 | #define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */
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| 103 | #define PIN_PB06 38 /**< \brief Pin Number for PB06 */
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| 104 | #define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */
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| 105 | #define PIN_PB07 39 /**< \brief Pin Number for PB07 */
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| 106 | #define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */
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| 107 | #define PIN_PB08 40 /**< \brief Pin Number for PB08 */
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| 108 | #define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */
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| 109 | #define PIN_PB09 41 /**< \brief Pin Number for PB09 */
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| 110 | #define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */
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| 111 | #define PIN_PB10 42 /**< \brief Pin Number for PB10 */
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| 112 | #define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */
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| 113 | #define PIN_PB11 43 /**< \brief Pin Number for PB11 */
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| 114 | #define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */
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| 115 | #define PIN_PB12 44 /**< \brief Pin Number for PB12 */
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| 116 | #define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */
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| 117 | #define PIN_PB13 45 /**< \brief Pin Number for PB13 */
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| 118 | #define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */
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| 119 | #define PIN_PB14 46 /**< \brief Pin Number for PB14 */
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| 120 | #define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */
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| 121 | #define PIN_PB15 47 /**< \brief Pin Number for PB15 */
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| 122 | #define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */
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| 123 | #define PIN_PB16 48 /**< \brief Pin Number for PB16 */
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| 124 | #define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */
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| 125 | #define PIN_PB17 49 /**< \brief Pin Number for PB17 */
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| 126 | #define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */
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| 127 | #define PIN_PB18 50 /**< \brief Pin Number for PB18 */
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| 128 | #define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */
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| 129 | #define PIN_PB19 51 /**< \brief Pin Number for PB19 */
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| 130 | #define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */
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| 131 | #define PIN_PB20 52 /**< \brief Pin Number for PB20 */
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| 132 | #define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */
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| 133 | #define PIN_PB21 53 /**< \brief Pin Number for PB21 */
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| 134 | #define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */
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| 135 | #define PIN_PB22 54 /**< \brief Pin Number for PB22 */
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| 136 | #define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */
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| 137 | #define PIN_PB23 55 /**< \brief Pin Number for PB23 */
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| 138 | #define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */
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| 139 | #define PIN_PB24 56 /**< \brief Pin Number for PB24 */
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| 140 | #define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */
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| 141 | #define PIN_PB25 57 /**< \brief Pin Number for PB25 */
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| 142 | #define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */
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| 143 | #define PIN_PB30 62 /**< \brief Pin Number for PB30 */
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| 144 | #define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */
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| 145 | #define PIN_PB31 63 /**< \brief Pin Number for PB31 */
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| 146 | #define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */
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| 147 | #define PIN_PC00 64 /**< \brief Pin Number for PC00 */
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| 148 | #define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */
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| 149 | #define PIN_PC01 65 /**< \brief Pin Number for PC01 */
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| 150 | #define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */
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| 151 | #define PIN_PC02 66 /**< \brief Pin Number for PC02 */
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| 152 | #define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */
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| 153 | #define PIN_PC03 67 /**< \brief Pin Number for PC03 */
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| 154 | #define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */
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| 155 | #define PIN_PC05 69 /**< \brief Pin Number for PC05 */
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| 156 | #define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */
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| 157 | #define PIN_PC06 70 /**< \brief Pin Number for PC06 */
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| 158 | #define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */
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| 159 | #define PIN_PC07 71 /**< \brief Pin Number for PC07 */
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| 160 | #define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */
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| 161 | #define PIN_PC10 74 /**< \brief Pin Number for PC10 */
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| 162 | #define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */
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| 163 | #define PIN_PC11 75 /**< \brief Pin Number for PC11 */
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| 164 | #define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */
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| 165 | #define PIN_PC12 76 /**< \brief Pin Number for PC12 */
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| 166 | #define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */
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| 167 | #define PIN_PC13 77 /**< \brief Pin Number for PC13 */
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| 168 | #define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */
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| 169 | #define PIN_PC14 78 /**< \brief Pin Number for PC14 */
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| 170 | #define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */
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| 171 | #define PIN_PC15 79 /**< \brief Pin Number for PC15 */
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| 172 | #define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */
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| 173 | #define PIN_PC16 80 /**< \brief Pin Number for PC16 */
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| 174 | #define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */
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| 175 | #define PIN_PC17 81 /**< \brief Pin Number for PC17 */
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| 176 | #define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */
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| 177 | #define PIN_PC18 82 /**< \brief Pin Number for PC18 */
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| 178 | #define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */
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| 179 | #define PIN_PC19 83 /**< \brief Pin Number for PC19 */
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| 180 | #define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */
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| 181 | #define PIN_PC20 84 /**< \brief Pin Number for PC20 */
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| 182 | #define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */
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| 183 | #define PIN_PC21 85 /**< \brief Pin Number for PC21 */
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| 184 | #define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */
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| 185 | #define PIN_PC24 88 /**< \brief Pin Number for PC24 */
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| 186 | #define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */
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| 187 | #define PIN_PC25 89 /**< \brief Pin Number for PC25 */
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| 188 | #define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */
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| 189 | #define PIN_PC26 90 /**< \brief Pin Number for PC26 */
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| 190 | #define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */
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| 191 | #define PIN_PC27 91 /**< \brief Pin Number for PC27 */
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| 192 | #define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */
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| 193 | #define PIN_PC28 92 /**< \brief Pin Number for PC28 */
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| 194 | #define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */
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| 195 | /* ========== PORT definition for CM4 peripheral ========== */
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| 196 | #define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */
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| 197 | #define MUX_PA30H_CM4_SWCLK _L_(7)
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| 198 | #define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK)
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| 199 | #define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30)
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| 200 | #define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */
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| 201 | #define MUX_PC27M_CM4_SWO _L_(12)
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| 202 | #define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO)
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| 203 | #define PORT_PC27M_CM4_SWO (_UL_(1) << 27)
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| 204 | #define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */
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| 205 | #define MUX_PB30H_CM4_SWO _L_(7)
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| 206 | #define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO)
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| 207 | #define PORT_PB30H_CM4_SWO (_UL_(1) << 30)
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| 208 | #define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */
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| 209 | #define MUX_PC27H_CM4_TRACECLK _L_(7)
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| 210 | #define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK)
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| 211 | #define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27)
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| 212 | #define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */
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| 213 | #define MUX_PC28H_CM4_TRACEDATA0 _L_(7)
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| 214 | #define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0)
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| 215 | #define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28)
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| 216 | #define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */
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| 217 | #define MUX_PC26H_CM4_TRACEDATA1 _L_(7)
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| 218 | #define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1)
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| 219 | #define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26)
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| 220 | #define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */
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| 221 | #define MUX_PC25H_CM4_TRACEDATA2 _L_(7)
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| 222 | #define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2)
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| 223 | #define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25)
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| 224 | #define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */
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| 225 | #define MUX_PC24H_CM4_TRACEDATA3 _L_(7)
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| 226 | #define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3)
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| 227 | #define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24)
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| 228 | /* ========== PORT definition for ANAREF peripheral ========== */
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| 229 | #define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */
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| 230 | #define MUX_PA03B_ANAREF_VREF0 _L_(1)
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| 231 | #define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0)
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| 232 | #define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3)
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| 233 | #define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */
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| 234 | #define MUX_PA04B_ANAREF_VREF1 _L_(1)
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| 235 | #define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1)
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| 236 | #define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4)
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| 237 | #define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */
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| 238 | #define MUX_PA06B_ANAREF_VREF2 _L_(1)
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| 239 | #define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2)
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| 240 | #define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6)
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| 241 | /* ========== PORT definition for GCLK peripheral ========== */
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| 242 | #define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */
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| 243 | #define MUX_PA30M_GCLK_IO0 _L_(12)
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| 244 | #define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0)
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| 245 | #define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30)
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| 246 | #define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */
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| 247 | #define MUX_PB14M_GCLK_IO0 _L_(12)
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| 248 | #define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0)
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| 249 | #define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14)
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| 250 | #define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */
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| 251 | #define MUX_PA14M_GCLK_IO0 _L_(12)
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| 252 | #define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0)
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| 253 | #define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14)
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| 254 | #define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */
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| 255 | #define MUX_PB22M_GCLK_IO0 _L_(12)
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| 256 | #define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0)
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| 257 | #define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22)
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| 258 | #define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */
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| 259 | #define MUX_PB15M_GCLK_IO1 _L_(12)
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| 260 | #define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1)
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| 261 | #define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15)
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| 262 | #define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */
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| 263 | #define MUX_PA15M_GCLK_IO1 _L_(12)
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| 264 | #define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1)
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| 265 | #define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15)
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| 266 | #define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */
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| 267 | #define MUX_PB23M_GCLK_IO1 _L_(12)
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| 268 | #define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1)
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| 269 | #define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23)
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| 270 | #define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */
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| 271 | #define MUX_PA27M_GCLK_IO1 _L_(12)
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| 272 | #define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1)
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| 273 | #define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27)
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| 274 | #define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */
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| 275 | #define MUX_PA16M_GCLK_IO2 _L_(12)
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| 276 | #define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2)
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| 277 | #define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16)
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| 278 | #define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */
|
| 279 | #define MUX_PB16M_GCLK_IO2 _L_(12)
|
| 280 | #define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2)
|
| 281 | #define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16)
|
| 282 | #define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */
|
| 283 | #define MUX_PA17M_GCLK_IO3 _L_(12)
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| 284 | #define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3)
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| 285 | #define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17)
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| 286 | #define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */
|
| 287 | #define MUX_PB17M_GCLK_IO3 _L_(12)
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| 288 | #define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3)
|
| 289 | #define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17)
|
| 290 | #define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */
|
| 291 | #define MUX_PA10M_GCLK_IO4 _L_(12)
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| 292 | #define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4)
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| 293 | #define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10)
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| 294 | #define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */
|
| 295 | #define MUX_PB10M_GCLK_IO4 _L_(12)
|
| 296 | #define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4)
|
| 297 | #define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10)
|
| 298 | #define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */
|
| 299 | #define MUX_PB18M_GCLK_IO4 _L_(12)
|
| 300 | #define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4)
|
| 301 | #define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18)
|
| 302 | #define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */
|
| 303 | #define MUX_PA11M_GCLK_IO5 _L_(12)
|
| 304 | #define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5)
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| 305 | #define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11)
|
| 306 | #define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */
|
| 307 | #define MUX_PB11M_GCLK_IO5 _L_(12)
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| 308 | #define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5)
|
| 309 | #define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11)
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| 310 | #define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */
|
| 311 | #define MUX_PB19M_GCLK_IO5 _L_(12)
|
| 312 | #define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5)
|
| 313 | #define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19)
|
| 314 | #define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */
|
| 315 | #define MUX_PB12M_GCLK_IO6 _L_(12)
|
| 316 | #define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6)
|
| 317 | #define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12)
|
| 318 | #define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */
|
| 319 | #define MUX_PB20M_GCLK_IO6 _L_(12)
|
| 320 | #define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6)
|
| 321 | #define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20)
|
| 322 | #define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */
|
| 323 | #define MUX_PB13M_GCLK_IO7 _L_(12)
|
| 324 | #define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7)
|
| 325 | #define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13)
|
| 326 | #define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */
|
| 327 | #define MUX_PB21M_GCLK_IO7 _L_(12)
|
| 328 | #define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7)
|
| 329 | #define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21)
|
| 330 | /* ========== PORT definition for EIC peripheral ========== */
|
| 331 | #define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
|
| 332 | #define MUX_PA00A_EIC_EXTINT0 _L_(0)
|
| 333 | #define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
|
| 334 | #define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0)
|
| 335 | #define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
|
| 336 | #define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
|
| 337 | #define MUX_PA16A_EIC_EXTINT0 _L_(0)
|
| 338 | #define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
|
| 339 | #define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16)
|
| 340 | #define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
|
| 341 | #define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */
|
| 342 | #define MUX_PB00A_EIC_EXTINT0 _L_(0)
|
| 343 | #define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
|
| 344 | #define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0)
|
| 345 | #define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */
|
| 346 | #define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */
|
| 347 | #define MUX_PB16A_EIC_EXTINT0 _L_(0)
|
| 348 | #define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
|
| 349 | #define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16)
|
| 350 | #define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */
|
| 351 | #define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */
|
| 352 | #define MUX_PC00A_EIC_EXTINT0 _L_(0)
|
| 353 | #define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0)
|
| 354 | #define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0)
|
| 355 | #define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */
|
| 356 | #define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */
|
| 357 | #define MUX_PC16A_EIC_EXTINT0 _L_(0)
|
| 358 | #define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0)
|
| 359 | #define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16)
|
| 360 | #define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */
|
| 361 | #define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
|
| 362 | #define MUX_PA01A_EIC_EXTINT1 _L_(0)
|
| 363 | #define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
|
| 364 | #define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1)
|
| 365 | #define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
|
| 366 | #define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
|
| 367 | #define MUX_PA17A_EIC_EXTINT1 _L_(0)
|
| 368 | #define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
|
| 369 | #define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17)
|
| 370 | #define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
|
| 371 | #define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */
|
| 372 | #define MUX_PB01A_EIC_EXTINT1 _L_(0)
|
| 373 | #define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
|
| 374 | #define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1)
|
| 375 | #define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */
|
| 376 | #define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */
|
| 377 | #define MUX_PB17A_EIC_EXTINT1 _L_(0)
|
| 378 | #define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
|
| 379 | #define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17)
|
| 380 | #define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */
|
| 381 | #define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */
|
| 382 | #define MUX_PC01A_EIC_EXTINT1 _L_(0)
|
| 383 | #define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1)
|
| 384 | #define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1)
|
| 385 | #define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */
|
| 386 | #define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */
|
| 387 | #define MUX_PC17A_EIC_EXTINT1 _L_(0)
|
| 388 | #define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1)
|
| 389 | #define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17)
|
| 390 | #define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */
|
| 391 | #define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
|
| 392 | #define MUX_PA02A_EIC_EXTINT2 _L_(0)
|
| 393 | #define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
|
| 394 | #define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2)
|
| 395 | #define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
|
| 396 | #define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
|
| 397 | #define MUX_PA18A_EIC_EXTINT2 _L_(0)
|
| 398 | #define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
|
| 399 | #define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18)
|
| 400 | #define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
|
| 401 | #define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */
|
| 402 | #define MUX_PB02A_EIC_EXTINT2 _L_(0)
|
| 403 | #define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
|
| 404 | #define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2)
|
| 405 | #define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */
|
| 406 | #define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */
|
| 407 | #define MUX_PB18A_EIC_EXTINT2 _L_(0)
|
| 408 | #define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2)
|
| 409 | #define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18)
|
| 410 | #define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */
|
| 411 | #define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */
|
| 412 | #define MUX_PC02A_EIC_EXTINT2 _L_(0)
|
| 413 | #define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2)
|
| 414 | #define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2)
|
| 415 | #define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */
|
| 416 | #define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */
|
| 417 | #define MUX_PC18A_EIC_EXTINT2 _L_(0)
|
| 418 | #define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2)
|
| 419 | #define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18)
|
| 420 | #define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */
|
| 421 | #define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
|
| 422 | #define MUX_PA03A_EIC_EXTINT3 _L_(0)
|
| 423 | #define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
|
| 424 | #define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3)
|
| 425 | #define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
|
| 426 | #define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
|
| 427 | #define MUX_PA19A_EIC_EXTINT3 _L_(0)
|
| 428 | #define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
|
| 429 | #define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19)
|
| 430 | #define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
|
| 431 | #define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */
|
| 432 | #define MUX_PB03A_EIC_EXTINT3 _L_(0)
|
| 433 | #define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
|
| 434 | #define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3)
|
| 435 | #define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */
|
| 436 | #define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */
|
| 437 | #define MUX_PB19A_EIC_EXTINT3 _L_(0)
|
| 438 | #define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3)
|
| 439 | #define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19)
|
| 440 | #define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */
|
| 441 | #define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */
|
| 442 | #define MUX_PC03A_EIC_EXTINT3 _L_(0)
|
| 443 | #define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3)
|
| 444 | #define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3)
|
| 445 | #define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */
|
| 446 | #define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */
|
| 447 | #define MUX_PC19A_EIC_EXTINT3 _L_(0)
|
| 448 | #define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3)
|
| 449 | #define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19)
|
| 450 | #define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */
|
| 451 | #define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
|
| 452 | #define MUX_PA04A_EIC_EXTINT4 _L_(0)
|
| 453 | #define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
|
| 454 | #define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4)
|
| 455 | #define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
|
| 456 | #define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */
|
| 457 | #define MUX_PA20A_EIC_EXTINT4 _L_(0)
|
| 458 | #define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
|
| 459 | #define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20)
|
| 460 | #define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */
|
| 461 | #define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */
|
| 462 | #define MUX_PB04A_EIC_EXTINT4 _L_(0)
|
| 463 | #define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
|
| 464 | #define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4)
|
| 465 | #define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */
|
| 466 | #define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */
|
| 467 | #define MUX_PB20A_EIC_EXTINT4 _L_(0)
|
| 468 | #define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4)
|
| 469 | #define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20)
|
| 470 | #define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */
|
| 471 | #define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */
|
| 472 | #define MUX_PC20A_EIC_EXTINT4 _L_(0)
|
| 473 | #define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4)
|
| 474 | #define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20)
|
| 475 | #define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */
|
| 476 | #define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
|
| 477 | #define MUX_PA05A_EIC_EXTINT5 _L_(0)
|
| 478 | #define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
|
| 479 | #define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5)
|
| 480 | #define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
|
| 481 | #define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */
|
| 482 | #define MUX_PA21A_EIC_EXTINT5 _L_(0)
|
| 483 | #define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
|
| 484 | #define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21)
|
| 485 | #define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */
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| 486 | #define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */
|
| 487 | #define MUX_PB05A_EIC_EXTINT5 _L_(0)
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| 488 | #define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
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| 489 | #define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5)
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| 490 | #define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */
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| 491 | #define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */
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| 492 | #define MUX_PB21A_EIC_EXTINT5 _L_(0)
|
| 493 | #define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5)
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| 494 | #define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21)
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| 495 | #define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */
|
| 496 | #define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */
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| 497 | #define MUX_PC05A_EIC_EXTINT5 _L_(0)
|
| 498 | #define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5)
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| 499 | #define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5)
|
| 500 | #define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */
|
| 501 | #define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */
|
| 502 | #define MUX_PC21A_EIC_EXTINT5 _L_(0)
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| 503 | #define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5)
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| 504 | #define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21)
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| 505 | #define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */
|
| 506 | #define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
|
| 507 | #define MUX_PA06A_EIC_EXTINT6 _L_(0)
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| 508 | #define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
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| 509 | #define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6)
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| 510 | #define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
|
| 511 | #define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
|
| 512 | #define MUX_PA22A_EIC_EXTINT6 _L_(0)
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| 513 | #define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
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| 514 | #define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22)
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| 515 | #define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
|
| 516 | #define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */
|
| 517 | #define MUX_PB06A_EIC_EXTINT6 _L_(0)
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| 518 | #define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
|
| 519 | #define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6)
|
| 520 | #define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */
|
| 521 | #define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */
|
| 522 | #define MUX_PB22A_EIC_EXTINT6 _L_(0)
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| 523 | #define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
|
| 524 | #define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22)
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| 525 | #define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */
|
| 526 | #define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */
|
| 527 | #define MUX_PC06A_EIC_EXTINT6 _L_(0)
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| 528 | #define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6)
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| 529 | #define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6)
|
| 530 | #define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */
|
| 531 | #define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
|
| 532 | #define MUX_PA07A_EIC_EXTINT7 _L_(0)
|
| 533 | #define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
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| 534 | #define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7)
|
| 535 | #define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
|
| 536 | #define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
|
| 537 | #define MUX_PA23A_EIC_EXTINT7 _L_(0)
|
| 538 | #define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
|
| 539 | #define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23)
|
| 540 | #define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
|
| 541 | #define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */
|
| 542 | #define MUX_PB07A_EIC_EXTINT7 _L_(0)
|
| 543 | #define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
|
| 544 | #define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7)
|
| 545 | #define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */
|
| 546 | #define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */
|
| 547 | #define MUX_PB23A_EIC_EXTINT7 _L_(0)
|
| 548 | #define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
|
| 549 | #define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23)
|
| 550 | #define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */
|
| 551 | #define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */
|
| 552 | #define MUX_PA24A_EIC_EXTINT8 _L_(0)
|
| 553 | #define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8)
|
| 554 | #define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24)
|
| 555 | #define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
|
| 556 | #define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */
|
| 557 | #define MUX_PB08A_EIC_EXTINT8 _L_(0)
|
| 558 | #define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
|
| 559 | #define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8)
|
| 560 | #define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */
|
| 561 | #define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */
|
| 562 | #define MUX_PB24A_EIC_EXTINT8 _L_(0)
|
| 563 | #define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8)
|
| 564 | #define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24)
|
| 565 | #define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */
|
| 566 | #define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */
|
| 567 | #define MUX_PC24A_EIC_EXTINT8 _L_(0)
|
| 568 | #define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8)
|
| 569 | #define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24)
|
| 570 | #define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */
|
| 571 | #define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
|
| 572 | #define MUX_PA09A_EIC_EXTINT9 _L_(0)
|
| 573 | #define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
|
| 574 | #define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9)
|
| 575 | #define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
|
| 576 | #define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */
|
| 577 | #define MUX_PA25A_EIC_EXTINT9 _L_(0)
|
| 578 | #define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9)
|
| 579 | #define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25)
|
| 580 | #define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
|
| 581 | #define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */
|
| 582 | #define MUX_PB09A_EIC_EXTINT9 _L_(0)
|
| 583 | #define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
|
| 584 | #define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9)
|
| 585 | #define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */
|
| 586 | #define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */
|
| 587 | #define MUX_PB25A_EIC_EXTINT9 _L_(0)
|
| 588 | #define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9)
|
| 589 | #define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25)
|
| 590 | #define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */
|
| 591 | #define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */
|
| 592 | #define MUX_PC07A_EIC_EXTINT9 _L_(0)
|
| 593 | #define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9)
|
| 594 | #define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7)
|
| 595 | #define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */
|
| 596 | #define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */
|
| 597 | #define MUX_PC25A_EIC_EXTINT9 _L_(0)
|
| 598 | #define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9)
|
| 599 | #define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25)
|
| 600 | #define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */
|
| 601 | #define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
|
| 602 | #define MUX_PA10A_EIC_EXTINT10 _L_(0)
|
| 603 | #define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
|
| 604 | #define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10)
|
| 605 | #define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
|
| 606 | #define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */
|
| 607 | #define MUX_PB10A_EIC_EXTINT10 _L_(0)
|
| 608 | #define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
|
| 609 | #define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10)
|
| 610 | #define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */
|
| 611 | #define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */
|
| 612 | #define MUX_PC10A_EIC_EXTINT10 _L_(0)
|
| 613 | #define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10)
|
| 614 | #define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10)
|
| 615 | #define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */
|
| 616 | #define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */
|
| 617 | #define MUX_PC26A_EIC_EXTINT10 _L_(0)
|
| 618 | #define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10)
|
| 619 | #define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26)
|
| 620 | #define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */
|
| 621 | #define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
|
| 622 | #define MUX_PA11A_EIC_EXTINT11 _L_(0)
|
| 623 | #define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
|
| 624 | #define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11)
|
| 625 | #define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
|
| 626 | #define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */
|
| 627 | #define MUX_PA27A_EIC_EXTINT11 _L_(0)
|
| 628 | #define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11)
|
| 629 | #define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27)
|
| 630 | #define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
|
| 631 | #define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */
|
| 632 | #define MUX_PB11A_EIC_EXTINT11 _L_(0)
|
| 633 | #define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
|
| 634 | #define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11)
|
| 635 | #define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */
|
| 636 | #define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */
|
| 637 | #define MUX_PC11A_EIC_EXTINT11 _L_(0)
|
| 638 | #define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11)
|
| 639 | #define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11)
|
| 640 | #define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */
|
| 641 | #define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */
|
| 642 | #define MUX_PC27A_EIC_EXTINT11 _L_(0)
|
| 643 | #define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11)
|
| 644 | #define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27)
|
| 645 | #define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */
|
| 646 | #define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */
|
| 647 | #define MUX_PA12A_EIC_EXTINT12 _L_(0)
|
| 648 | #define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
|
| 649 | #define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12)
|
| 650 | #define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */
|
| 651 | #define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */
|
| 652 | #define MUX_PB12A_EIC_EXTINT12 _L_(0)
|
| 653 | #define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
|
| 654 | #define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12)
|
| 655 | #define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */
|
| 656 | #define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */
|
| 657 | #define MUX_PC12A_EIC_EXTINT12 _L_(0)
|
| 658 | #define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12)
|
| 659 | #define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12)
|
| 660 | #define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */
|
| 661 | #define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */
|
| 662 | #define MUX_PC28A_EIC_EXTINT12 _L_(0)
|
| 663 | #define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12)
|
| 664 | #define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28)
|
| 665 | #define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */
|
| 666 | #define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */
|
| 667 | #define MUX_PA13A_EIC_EXTINT13 _L_(0)
|
| 668 | #define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
|
| 669 | #define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13)
|
| 670 | #define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */
|
| 671 | #define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */
|
| 672 | #define MUX_PB13A_EIC_EXTINT13 _L_(0)
|
| 673 | #define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
|
| 674 | #define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13)
|
| 675 | #define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */
|
| 676 | #define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */
|
| 677 | #define MUX_PC13A_EIC_EXTINT13 _L_(0)
|
| 678 | #define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13)
|
| 679 | #define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13)
|
| 680 | #define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */
|
| 681 | #define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */
|
| 682 | #define MUX_PA30A_EIC_EXTINT14 _L_(0)
|
| 683 | #define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14)
|
| 684 | #define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30)
|
| 685 | #define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
|
| 686 | #define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */
|
| 687 | #define MUX_PB14A_EIC_EXTINT14 _L_(0)
|
| 688 | #define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
|
| 689 | #define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14)
|
| 690 | #define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */
|
| 691 | #define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */
|
| 692 | #define MUX_PB30A_EIC_EXTINT14 _L_(0)
|
| 693 | #define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
|
| 694 | #define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30)
|
| 695 | #define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */
|
| 696 | #define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */
|
| 697 | #define MUX_PC14A_EIC_EXTINT14 _L_(0)
|
| 698 | #define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14)
|
| 699 | #define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14)
|
| 700 | #define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */
|
| 701 | #define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
|
| 702 | #define MUX_PA14A_EIC_EXTINT14 _L_(0)
|
| 703 | #define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
|
| 704 | #define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14)
|
| 705 | #define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
|
| 706 | #define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
|
| 707 | #define MUX_PA15A_EIC_EXTINT15 _L_(0)
|
| 708 | #define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
|
| 709 | #define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15)
|
| 710 | #define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
|
| 711 | #define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */
|
| 712 | #define MUX_PA31A_EIC_EXTINT15 _L_(0)
|
| 713 | #define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15)
|
| 714 | #define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31)
|
| 715 | #define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
|
| 716 | #define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */
|
| 717 | #define MUX_PB15A_EIC_EXTINT15 _L_(0)
|
| 718 | #define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
|
| 719 | #define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15)
|
| 720 | #define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */
|
| 721 | #define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */
|
| 722 | #define MUX_PB31A_EIC_EXTINT15 _L_(0)
|
| 723 | #define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
|
| 724 | #define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31)
|
| 725 | #define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */
|
| 726 | #define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */
|
| 727 | #define MUX_PC15A_EIC_EXTINT15 _L_(0)
|
| 728 | #define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15)
|
| 729 | #define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15)
|
| 730 | #define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */
|
| 731 | #define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */
|
| 732 | #define MUX_PA08A_EIC_NMI _L_(0)
|
| 733 | #define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
|
| 734 | #define PORT_PA08A_EIC_NMI (_UL_(1) << 8)
|
| 735 | /* ========== PORT definition for SERCOM0 peripheral ========== */
|
| 736 | #define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
|
| 737 | #define MUX_PA04D_SERCOM0_PAD0 _L_(3)
|
| 738 | #define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
|
| 739 | #define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4)
|
| 740 | #define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */
|
| 741 | #define MUX_PC17D_SERCOM0_PAD0 _L_(3)
|
| 742 | #define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0)
|
| 743 | #define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17)
|
| 744 | #define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
|
| 745 | #define MUX_PA08C_SERCOM0_PAD0 _L_(2)
|
| 746 | #define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
|
| 747 | #define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8)
|
| 748 | #define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */
|
| 749 | #define MUX_PB24C_SERCOM0_PAD0 _L_(2)
|
| 750 | #define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0)
|
| 751 | #define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24)
|
| 752 | #define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
|
| 753 | #define MUX_PA05D_SERCOM0_PAD1 _L_(3)
|
| 754 | #define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
|
| 755 | #define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5)
|
| 756 | #define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */
|
| 757 | #define MUX_PC16D_SERCOM0_PAD1 _L_(3)
|
| 758 | #define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1)
|
| 759 | #define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16)
|
| 760 | #define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
|
| 761 | #define MUX_PA09C_SERCOM0_PAD1 _L_(2)
|
| 762 | #define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
|
| 763 | #define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9)
|
| 764 | #define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */
|
| 765 | #define MUX_PB25C_SERCOM0_PAD1 _L_(2)
|
| 766 | #define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1)
|
| 767 | #define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25)
|
| 768 | #define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
|
| 769 | #define MUX_PA06D_SERCOM0_PAD2 _L_(3)
|
| 770 | #define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
|
| 771 | #define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6)
|
| 772 | #define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */
|
| 773 | #define MUX_PC18D_SERCOM0_PAD2 _L_(3)
|
| 774 | #define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2)
|
| 775 | #define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18)
|
| 776 | #define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
|
| 777 | #define MUX_PA10C_SERCOM0_PAD2 _L_(2)
|
| 778 | #define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
|
| 779 | #define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10)
|
| 780 | #define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */
|
| 781 | #define MUX_PC24C_SERCOM0_PAD2 _L_(2)
|
| 782 | #define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2)
|
| 783 | #define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24)
|
| 784 | #define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
|
| 785 | #define MUX_PA07D_SERCOM0_PAD3 _L_(3)
|
| 786 | #define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
|
| 787 | #define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7)
|
| 788 | #define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */
|
| 789 | #define MUX_PC19D_SERCOM0_PAD3 _L_(3)
|
| 790 | #define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3)
|
| 791 | #define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19)
|
| 792 | #define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
|
| 793 | #define MUX_PA11C_SERCOM0_PAD3 _L_(2)
|
| 794 | #define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
|
| 795 | #define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11)
|
| 796 | #define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */
|
| 797 | #define MUX_PC25C_SERCOM0_PAD3 _L_(2)
|
| 798 | #define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3)
|
| 799 | #define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25)
|
| 800 | /* ========== PORT definition for SERCOM1 peripheral ========== */
|
| 801 | #define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
|
| 802 | #define MUX_PA00D_SERCOM1_PAD0 _L_(3)
|
| 803 | #define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
|
| 804 | #define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0)
|
| 805 | #define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
|
| 806 | #define MUX_PA16C_SERCOM1_PAD0 _L_(2)
|
| 807 | #define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
|
| 808 | #define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16)
|
| 809 | #define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */
|
| 810 | #define MUX_PC27C_SERCOM1_PAD0 _L_(2)
|
| 811 | #define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0)
|
| 812 | #define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27)
|
| 813 | #define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
|
| 814 | #define MUX_PA01D_SERCOM1_PAD1 _L_(3)
|
| 815 | #define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
|
| 816 | #define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1)
|
| 817 | #define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
|
| 818 | #define MUX_PA17C_SERCOM1_PAD1 _L_(2)
|
| 819 | #define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
|
| 820 | #define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17)
|
| 821 | #define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */
|
| 822 | #define MUX_PC28C_SERCOM1_PAD1 _L_(2)
|
| 823 | #define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1)
|
| 824 | #define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28)
|
| 825 | #define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
|
| 826 | #define MUX_PA30D_SERCOM1_PAD2 _L_(3)
|
| 827 | #define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
|
| 828 | #define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30)
|
| 829 | #define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
|
| 830 | #define MUX_PA18C_SERCOM1_PAD2 _L_(2)
|
| 831 | #define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
|
| 832 | #define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18)
|
| 833 | #define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */
|
| 834 | #define MUX_PB22C_SERCOM1_PAD2 _L_(2)
|
| 835 | #define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2)
|
| 836 | #define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22)
|
| 837 | #define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
|
| 838 | #define MUX_PA31D_SERCOM1_PAD3 _L_(3)
|
| 839 | #define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
|
| 840 | #define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31)
|
| 841 | #define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
|
| 842 | #define MUX_PA19C_SERCOM1_PAD3 _L_(2)
|
| 843 | #define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
|
| 844 | #define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19)
|
| 845 | #define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */
|
| 846 | #define MUX_PB23C_SERCOM1_PAD3 _L_(2)
|
| 847 | #define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3)
|
| 848 | #define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23)
|
| 849 | /* ========== PORT definition for TC0 peripheral ========== */
|
| 850 | #define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */
|
| 851 | #define MUX_PA04E_TC0_WO0 _L_(4)
|
| 852 | #define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0)
|
| 853 | #define PORT_PA04E_TC0_WO0 (_UL_(1) << 4)
|
| 854 | #define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */
|
| 855 | #define MUX_PA08E_TC0_WO0 _L_(4)
|
| 856 | #define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
|
| 857 | #define PORT_PA08E_TC0_WO0 (_UL_(1) << 8)
|
| 858 | #define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */
|
| 859 | #define MUX_PB30E_TC0_WO0 _L_(4)
|
| 860 | #define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0)
|
| 861 | #define PORT_PB30E_TC0_WO0 (_UL_(1) << 30)
|
| 862 | #define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */
|
| 863 | #define MUX_PA05E_TC0_WO1 _L_(4)
|
| 864 | #define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1)
|
| 865 | #define PORT_PA05E_TC0_WO1 (_UL_(1) << 5)
|
| 866 | #define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */
|
| 867 | #define MUX_PA09E_TC0_WO1 _L_(4)
|
| 868 | #define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
|
| 869 | #define PORT_PA09E_TC0_WO1 (_UL_(1) << 9)
|
| 870 | #define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */
|
| 871 | #define MUX_PB31E_TC0_WO1 _L_(4)
|
| 872 | #define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1)
|
| 873 | #define PORT_PB31E_TC0_WO1 (_UL_(1) << 31)
|
| 874 | /* ========== PORT definition for TC1 peripheral ========== */
|
| 875 | #define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */
|
| 876 | #define MUX_PA06E_TC1_WO0 _L_(4)
|
| 877 | #define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0)
|
| 878 | #define PORT_PA06E_TC1_WO0 (_UL_(1) << 6)
|
| 879 | #define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */
|
| 880 | #define MUX_PA10E_TC1_WO0 _L_(4)
|
| 881 | #define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
|
| 882 | #define PORT_PA10E_TC1_WO0 (_UL_(1) << 10)
|
| 883 | #define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */
|
| 884 | #define MUX_PA07E_TC1_WO1 _L_(4)
|
| 885 | #define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1)
|
| 886 | #define PORT_PA07E_TC1_WO1 (_UL_(1) << 7)
|
| 887 | #define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */
|
| 888 | #define MUX_PA11E_TC1_WO1 _L_(4)
|
| 889 | #define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
|
| 890 | #define PORT_PA11E_TC1_WO1 (_UL_(1) << 11)
|
| 891 | /* ========== PORT definition for USB peripheral ========== */
|
| 892 | #define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */
|
| 893 | #define MUX_PA24H_USB_DM _L_(7)
|
| 894 | #define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM)
|
| 895 | #define PORT_PA24H_USB_DM (_UL_(1) << 24)
|
| 896 | #define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */
|
| 897 | #define MUX_PA25H_USB_DP _L_(7)
|
| 898 | #define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP)
|
| 899 | #define PORT_PA25H_USB_DP (_UL_(1) << 25)
|
| 900 | #define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */
|
| 901 | #define MUX_PA23H_USB_SOF_1KHZ _L_(7)
|
| 902 | #define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ)
|
| 903 | #define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23)
|
| 904 | #define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */
|
| 905 | #define MUX_PB22H_USB_SOF_1KHZ _L_(7)
|
| 906 | #define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ)
|
| 907 | #define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22)
|
| 908 | /* ========== PORT definition for SERCOM2 peripheral ========== */
|
| 909 | #define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */
|
| 910 | #define MUX_PA09D_SERCOM2_PAD0 _L_(3)
|
| 911 | #define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0)
|
| 912 | #define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9)
|
| 913 | #define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */
|
| 914 | #define MUX_PB25D_SERCOM2_PAD0 _L_(3)
|
| 915 | #define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0)
|
| 916 | #define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25)
|
| 917 | #define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
|
| 918 | #define MUX_PA12C_SERCOM2_PAD0 _L_(2)
|
| 919 | #define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
|
| 920 | #define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12)
|
| 921 | #define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */
|
| 922 | #define MUX_PA08D_SERCOM2_PAD1 _L_(3)
|
| 923 | #define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1)
|
| 924 | #define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8)
|
| 925 | #define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */
|
| 926 | #define MUX_PB24D_SERCOM2_PAD1 _L_(3)
|
| 927 | #define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1)
|
| 928 | #define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24)
|
| 929 | #define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
|
| 930 | #define MUX_PA13C_SERCOM2_PAD1 _L_(2)
|
| 931 | #define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
|
| 932 | #define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13)
|
| 933 | #define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
|
| 934 | #define MUX_PA10D_SERCOM2_PAD2 _L_(3)
|
| 935 | #define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
|
| 936 | #define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10)
|
| 937 | #define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */
|
| 938 | #define MUX_PC24D_SERCOM2_PAD2 _L_(3)
|
| 939 | #define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2)
|
| 940 | #define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24)
|
| 941 | #define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
|
| 942 | #define MUX_PA14C_SERCOM2_PAD2 _L_(2)
|
| 943 | #define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
|
| 944 | #define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14)
|
| 945 | #define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
|
| 946 | #define MUX_PA11D_SERCOM2_PAD3 _L_(3)
|
| 947 | #define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
|
| 948 | #define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11)
|
| 949 | #define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */
|
| 950 | #define MUX_PC25D_SERCOM2_PAD3 _L_(3)
|
| 951 | #define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3)
|
| 952 | #define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25)
|
| 953 | #define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
|
| 954 | #define MUX_PA15C_SERCOM2_PAD3 _L_(2)
|
| 955 | #define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
|
| 956 | #define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15)
|
| 957 | /* ========== PORT definition for SERCOM3 peripheral ========== */
|
| 958 | #define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */
|
| 959 | #define MUX_PA17D_SERCOM3_PAD0 _L_(3)
|
| 960 | #define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0)
|
| 961 | #define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17)
|
| 962 | #define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
|
| 963 | #define MUX_PA22C_SERCOM3_PAD0 _L_(2)
|
| 964 | #define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
|
| 965 | #define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22)
|
| 966 | #define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */
|
| 967 | #define MUX_PB20C_SERCOM3_PAD0 _L_(2)
|
| 968 | #define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0)
|
| 969 | #define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20)
|
| 970 | #define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */
|
| 971 | #define MUX_PA16D_SERCOM3_PAD1 _L_(3)
|
| 972 | #define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1)
|
| 973 | #define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16)
|
| 974 | #define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
|
| 975 | #define MUX_PA23C_SERCOM3_PAD1 _L_(2)
|
| 976 | #define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
|
| 977 | #define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23)
|
| 978 | #define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */
|
| 979 | #define MUX_PB21C_SERCOM3_PAD1 _L_(2)
|
| 980 | #define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1)
|
| 981 | #define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21)
|
| 982 | #define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
|
| 983 | #define MUX_PA18D_SERCOM3_PAD2 _L_(3)
|
| 984 | #define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
|
| 985 | #define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18)
|
| 986 | #define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
|
| 987 | #define MUX_PA20D_SERCOM3_PAD2 _L_(3)
|
| 988 | #define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
|
| 989 | #define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20)
|
| 990 | #define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
|
| 991 | #define MUX_PA24C_SERCOM3_PAD2 _L_(2)
|
| 992 | #define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
|
| 993 | #define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24)
|
| 994 | #define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
|
| 995 | #define MUX_PA19D_SERCOM3_PAD3 _L_(3)
|
| 996 | #define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
|
| 997 | #define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19)
|
| 998 | #define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
|
| 999 | #define MUX_PA21D_SERCOM3_PAD3 _L_(3)
|
| 1000 | #define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
|
| 1001 | #define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21)
|
| 1002 | #define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
|
| 1003 | #define MUX_PA25C_SERCOM3_PAD3 _L_(2)
|
| 1004 | #define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
|
| 1005 | #define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25)
|
| 1006 | /* ========== PORT definition for TCC0 peripheral ========== */
|
| 1007 | #define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */
|
| 1008 | #define MUX_PA20G_TCC0_WO0 _L_(6)
|
| 1009 | #define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0)
|
| 1010 | #define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20)
|
| 1011 | #define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */
|
| 1012 | #define MUX_PB12G_TCC0_WO0 _L_(6)
|
| 1013 | #define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0)
|
| 1014 | #define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12)
|
| 1015 | #define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */
|
| 1016 | #define MUX_PA08F_TCC0_WO0 _L_(5)
|
| 1017 | #define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0)
|
| 1018 | #define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8)
|
| 1019 | #define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */
|
| 1020 | #define MUX_PC10F_TCC0_WO0 _L_(5)
|
| 1021 | #define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0)
|
| 1022 | #define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10)
|
| 1023 | #define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */
|
| 1024 | #define MUX_PC16F_TCC0_WO0 _L_(5)
|
| 1025 | #define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0)
|
| 1026 | #define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16)
|
| 1027 | #define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */
|
| 1028 | #define MUX_PA21G_TCC0_WO1 _L_(6)
|
| 1029 | #define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1)
|
| 1030 | #define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21)
|
| 1031 | #define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */
|
| 1032 | #define MUX_PB13G_TCC0_WO1 _L_(6)
|
| 1033 | #define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1)
|
| 1034 | #define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13)
|
| 1035 | #define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */
|
| 1036 | #define MUX_PA09F_TCC0_WO1 _L_(5)
|
| 1037 | #define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1)
|
| 1038 | #define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9)
|
| 1039 | #define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */
|
| 1040 | #define MUX_PC11F_TCC0_WO1 _L_(5)
|
| 1041 | #define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1)
|
| 1042 | #define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11)
|
| 1043 | #define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */
|
| 1044 | #define MUX_PC17F_TCC0_WO1 _L_(5)
|
| 1045 | #define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1)
|
| 1046 | #define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17)
|
| 1047 | #define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */
|
| 1048 | #define MUX_PA22G_TCC0_WO2 _L_(6)
|
| 1049 | #define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2)
|
| 1050 | #define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22)
|
| 1051 | #define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */
|
| 1052 | #define MUX_PB14G_TCC0_WO2 _L_(6)
|
| 1053 | #define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2)
|
| 1054 | #define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14)
|
| 1055 | #define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
|
| 1056 | #define MUX_PA10F_TCC0_WO2 _L_(5)
|
| 1057 | #define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
|
| 1058 | #define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10)
|
| 1059 | #define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */
|
| 1060 | #define MUX_PC12F_TCC0_WO2 _L_(5)
|
| 1061 | #define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2)
|
| 1062 | #define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12)
|
| 1063 | #define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */
|
| 1064 | #define MUX_PC18F_TCC0_WO2 _L_(5)
|
| 1065 | #define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2)
|
| 1066 | #define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18)
|
| 1067 | #define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */
|
| 1068 | #define MUX_PA23G_TCC0_WO3 _L_(6)
|
| 1069 | #define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3)
|
| 1070 | #define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23)
|
| 1071 | #define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */
|
| 1072 | #define MUX_PB15G_TCC0_WO3 _L_(6)
|
| 1073 | #define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3)
|
| 1074 | #define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15)
|
| 1075 | #define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
|
| 1076 | #define MUX_PA11F_TCC0_WO3 _L_(5)
|
| 1077 | #define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
|
| 1078 | #define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11)
|
| 1079 | #define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */
|
| 1080 | #define MUX_PC13F_TCC0_WO3 _L_(5)
|
| 1081 | #define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3)
|
| 1082 | #define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13)
|
| 1083 | #define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */
|
| 1084 | #define MUX_PC19F_TCC0_WO3 _L_(5)
|
| 1085 | #define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3)
|
| 1086 | #define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19)
|
| 1087 | #define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */
|
| 1088 | #define MUX_PA16G_TCC0_WO4 _L_(6)
|
| 1089 | #define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4)
|
| 1090 | #define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16)
|
| 1091 | #define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */
|
| 1092 | #define MUX_PB16G_TCC0_WO4 _L_(6)
|
| 1093 | #define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4)
|
| 1094 | #define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16)
|
| 1095 | #define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */
|
| 1096 | #define MUX_PB10F_TCC0_WO4 _L_(5)
|
| 1097 | #define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
|
| 1098 | #define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10)
|
| 1099 | #define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */
|
| 1100 | #define MUX_PC14F_TCC0_WO4 _L_(5)
|
| 1101 | #define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4)
|
| 1102 | #define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14)
|
| 1103 | #define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */
|
| 1104 | #define MUX_PC20F_TCC0_WO4 _L_(5)
|
| 1105 | #define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4)
|
| 1106 | #define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20)
|
| 1107 | #define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */
|
| 1108 | #define MUX_PA17G_TCC0_WO5 _L_(6)
|
| 1109 | #define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5)
|
| 1110 | #define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17)
|
| 1111 | #define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */
|
| 1112 | #define MUX_PB17G_TCC0_WO5 _L_(6)
|
| 1113 | #define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5)
|
| 1114 | #define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17)
|
| 1115 | #define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */
|
| 1116 | #define MUX_PB11F_TCC0_WO5 _L_(5)
|
| 1117 | #define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
|
| 1118 | #define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11)
|
| 1119 | #define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */
|
| 1120 | #define MUX_PC15F_TCC0_WO5 _L_(5)
|
| 1121 | #define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5)
|
| 1122 | #define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15)
|
| 1123 | #define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */
|
| 1124 | #define MUX_PC21F_TCC0_WO5 _L_(5)
|
| 1125 | #define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5)
|
| 1126 | #define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21)
|
| 1127 | #define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */
|
| 1128 | #define MUX_PA18G_TCC0_WO6 _L_(6)
|
| 1129 | #define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6)
|
| 1130 | #define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18)
|
| 1131 | #define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */
|
| 1132 | #define MUX_PB30G_TCC0_WO6 _L_(6)
|
| 1133 | #define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6)
|
| 1134 | #define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30)
|
| 1135 | #define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */
|
| 1136 | #define MUX_PA12F_TCC0_WO6 _L_(5)
|
| 1137 | #define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
|
| 1138 | #define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12)
|
| 1139 | #define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */
|
| 1140 | #define MUX_PA19G_TCC0_WO7 _L_(6)
|
| 1141 | #define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7)
|
| 1142 | #define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19)
|
| 1143 | #define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */
|
| 1144 | #define MUX_PB31G_TCC0_WO7 _L_(6)
|
| 1145 | #define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7)
|
| 1146 | #define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31)
|
| 1147 | #define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */
|
| 1148 | #define MUX_PA13F_TCC0_WO7 _L_(5)
|
| 1149 | #define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
|
| 1150 | #define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13)
|
| 1151 | /* ========== PORT definition for TCC1 peripheral ========== */
|
| 1152 | #define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */
|
| 1153 | #define MUX_PB10G_TCC1_WO0 _L_(6)
|
| 1154 | #define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0)
|
| 1155 | #define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10)
|
| 1156 | #define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */
|
| 1157 | #define MUX_PC14G_TCC1_WO0 _L_(6)
|
| 1158 | #define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0)
|
| 1159 | #define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14)
|
| 1160 | #define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */
|
| 1161 | #define MUX_PA16F_TCC1_WO0 _L_(5)
|
| 1162 | #define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0)
|
| 1163 | #define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16)
|
| 1164 | #define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */
|
| 1165 | #define MUX_PB18F_TCC1_WO0 _L_(5)
|
| 1166 | #define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0)
|
| 1167 | #define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18)
|
| 1168 | #define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */
|
| 1169 | #define MUX_PB11G_TCC1_WO1 _L_(6)
|
| 1170 | #define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1)
|
| 1171 | #define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11)
|
| 1172 | #define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */
|
| 1173 | #define MUX_PC15G_TCC1_WO1 _L_(6)
|
| 1174 | #define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1)
|
| 1175 | #define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15)
|
| 1176 | #define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */
|
| 1177 | #define MUX_PA17F_TCC1_WO1 _L_(5)
|
| 1178 | #define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1)
|
| 1179 | #define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17)
|
| 1180 | #define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */
|
| 1181 | #define MUX_PB19F_TCC1_WO1 _L_(5)
|
| 1182 | #define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1)
|
| 1183 | #define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19)
|
| 1184 | #define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */
|
| 1185 | #define MUX_PA12G_TCC1_WO2 _L_(6)
|
| 1186 | #define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2)
|
| 1187 | #define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12)
|
| 1188 | #define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */
|
| 1189 | #define MUX_PA14G_TCC1_WO2 _L_(6)
|
| 1190 | #define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2)
|
| 1191 | #define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14)
|
| 1192 | #define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */
|
| 1193 | #define MUX_PA18F_TCC1_WO2 _L_(5)
|
| 1194 | #define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2)
|
| 1195 | #define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18)
|
| 1196 | #define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */
|
| 1197 | #define MUX_PB20F_TCC1_WO2 _L_(5)
|
| 1198 | #define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2)
|
| 1199 | #define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20)
|
| 1200 | #define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */
|
| 1201 | #define MUX_PA13G_TCC1_WO3 _L_(6)
|
| 1202 | #define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3)
|
| 1203 | #define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13)
|
| 1204 | #define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */
|
| 1205 | #define MUX_PA15G_TCC1_WO3 _L_(6)
|
| 1206 | #define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3)
|
| 1207 | #define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15)
|
| 1208 | #define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */
|
| 1209 | #define MUX_PA19F_TCC1_WO3 _L_(5)
|
| 1210 | #define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3)
|
| 1211 | #define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19)
|
| 1212 | #define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */
|
| 1213 | #define MUX_PB21F_TCC1_WO3 _L_(5)
|
| 1214 | #define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3)
|
| 1215 | #define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21)
|
| 1216 | #define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */
|
| 1217 | #define MUX_PA08G_TCC1_WO4 _L_(6)
|
| 1218 | #define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4)
|
| 1219 | #define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8)
|
| 1220 | #define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */
|
| 1221 | #define MUX_PC10G_TCC1_WO4 _L_(6)
|
| 1222 | #define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4)
|
| 1223 | #define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10)
|
| 1224 | #define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */
|
| 1225 | #define MUX_PA20F_TCC1_WO4 _L_(5)
|
| 1226 | #define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4)
|
| 1227 | #define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20)
|
| 1228 | #define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */
|
| 1229 | #define MUX_PA09G_TCC1_WO5 _L_(6)
|
| 1230 | #define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5)
|
| 1231 | #define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9)
|
| 1232 | #define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */
|
| 1233 | #define MUX_PC11G_TCC1_WO5 _L_(6)
|
| 1234 | #define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5)
|
| 1235 | #define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11)
|
| 1236 | #define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */
|
| 1237 | #define MUX_PA21F_TCC1_WO5 _L_(5)
|
| 1238 | #define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5)
|
| 1239 | #define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21)
|
| 1240 | #define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */
|
| 1241 | #define MUX_PA10G_TCC1_WO6 _L_(6)
|
| 1242 | #define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6)
|
| 1243 | #define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10)
|
| 1244 | #define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */
|
| 1245 | #define MUX_PC12G_TCC1_WO6 _L_(6)
|
| 1246 | #define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6)
|
| 1247 | #define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12)
|
| 1248 | #define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */
|
| 1249 | #define MUX_PA22F_TCC1_WO6 _L_(5)
|
| 1250 | #define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6)
|
| 1251 | #define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22)
|
| 1252 | #define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */
|
| 1253 | #define MUX_PA11G_TCC1_WO7 _L_(6)
|
| 1254 | #define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7)
|
| 1255 | #define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11)
|
| 1256 | #define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */
|
| 1257 | #define MUX_PC13G_TCC1_WO7 _L_(6)
|
| 1258 | #define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7)
|
| 1259 | #define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13)
|
| 1260 | #define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */
|
| 1261 | #define MUX_PA23F_TCC1_WO7 _L_(5)
|
| 1262 | #define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7)
|
| 1263 | #define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23)
|
| 1264 | /* ========== PORT definition for TC2 peripheral ========== */
|
| 1265 | #define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */
|
| 1266 | #define MUX_PA12E_TC2_WO0 _L_(4)
|
| 1267 | #define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)
|
| 1268 | #define PORT_PA12E_TC2_WO0 (_UL_(1) << 12)
|
| 1269 | #define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */
|
| 1270 | #define MUX_PA16E_TC2_WO0 _L_(4)
|
| 1271 | #define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0)
|
| 1272 | #define PORT_PA16E_TC2_WO0 (_UL_(1) << 16)
|
| 1273 | #define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */
|
| 1274 | #define MUX_PA00E_TC2_WO0 _L_(4)
|
| 1275 | #define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0)
|
| 1276 | #define PORT_PA00E_TC2_WO0 (_UL_(1) << 0)
|
| 1277 | #define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */
|
| 1278 | #define MUX_PA01E_TC2_WO1 _L_(4)
|
| 1279 | #define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1)
|
| 1280 | #define PORT_PA01E_TC2_WO1 (_UL_(1) << 1)
|
| 1281 | #define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */
|
| 1282 | #define MUX_PA13E_TC2_WO1 _L_(4)
|
| 1283 | #define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)
|
| 1284 | #define PORT_PA13E_TC2_WO1 (_UL_(1) << 13)
|
| 1285 | #define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */
|
| 1286 | #define MUX_PA17E_TC2_WO1 _L_(4)
|
| 1287 | #define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1)
|
| 1288 | #define PORT_PA17E_TC2_WO1 (_UL_(1) << 17)
|
| 1289 | /* ========== PORT definition for TC3 peripheral ========== */
|
| 1290 | #define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */
|
| 1291 | #define MUX_PA18E_TC3_WO0 _L_(4)
|
| 1292 | #define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
|
| 1293 | #define PORT_PA18E_TC3_WO0 (_UL_(1) << 18)
|
| 1294 | #define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */
|
| 1295 | #define MUX_PA14E_TC3_WO0 _L_(4)
|
| 1296 | #define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
|
| 1297 | #define PORT_PA14E_TC3_WO0 (_UL_(1) << 14)
|
| 1298 | #define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */
|
| 1299 | #define MUX_PA15E_TC3_WO1 _L_(4)
|
| 1300 | #define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
|
| 1301 | #define PORT_PA15E_TC3_WO1 (_UL_(1) << 15)
|
| 1302 | #define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */
|
| 1303 | #define MUX_PA19E_TC3_WO1 _L_(4)
|
| 1304 | #define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
|
| 1305 | #define PORT_PA19E_TC3_WO1 (_UL_(1) << 19)
|
| 1306 | /* ========== PORT definition for CAN0 peripheral ========== */
|
| 1307 | #define PIN_PA23I_CAN0_RX _L_(23) /**< \brief CAN0 signal: RX on PA23 mux I */
|
| 1308 | #define MUX_PA23I_CAN0_RX _L_(8)
|
| 1309 | #define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX)
|
| 1310 | #define PORT_PA23I_CAN0_RX (_UL_(1) << 23)
|
| 1311 | #define PIN_PA25I_CAN0_RX _L_(25) /**< \brief CAN0 signal: RX on PA25 mux I */
|
| 1312 | #define MUX_PA25I_CAN0_RX _L_(8)
|
| 1313 | #define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX)
|
| 1314 | #define PORT_PA25I_CAN0_RX (_UL_(1) << 25)
|
| 1315 | #define PIN_PA22I_CAN0_TX _L_(22) /**< \brief CAN0 signal: TX on PA22 mux I */
|
| 1316 | #define MUX_PA22I_CAN0_TX _L_(8)
|
| 1317 | #define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX)
|
| 1318 | #define PORT_PA22I_CAN0_TX (_UL_(1) << 22)
|
| 1319 | #define PIN_PA24I_CAN0_TX _L_(24) /**< \brief CAN0 signal: TX on PA24 mux I */
|
| 1320 | #define MUX_PA24I_CAN0_TX _L_(8)
|
| 1321 | #define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX)
|
| 1322 | #define PORT_PA24I_CAN0_TX (_UL_(1) << 24)
|
| 1323 | /* ========== PORT definition for CAN1 peripheral ========== */
|
| 1324 | #define PIN_PB13H_CAN1_RX _L_(45) /**< \brief CAN1 signal: RX on PB13 mux H */
|
| 1325 | #define MUX_PB13H_CAN1_RX _L_(7)
|
| 1326 | #define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX)
|
| 1327 | #define PORT_PB13H_CAN1_RX (_UL_(1) << 13)
|
| 1328 | #define PIN_PB15H_CAN1_RX _L_(47) /**< \brief CAN1 signal: RX on PB15 mux H */
|
| 1329 | #define MUX_PB15H_CAN1_RX _L_(7)
|
| 1330 | #define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX)
|
| 1331 | #define PORT_PB15H_CAN1_RX (_UL_(1) << 15)
|
| 1332 | #define PIN_PB12H_CAN1_TX _L_(44) /**< \brief CAN1 signal: TX on PB12 mux H */
|
| 1333 | #define MUX_PB12H_CAN1_TX _L_(7)
|
| 1334 | #define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX)
|
| 1335 | #define PORT_PB12H_CAN1_TX (_UL_(1) << 12)
|
| 1336 | #define PIN_PB14H_CAN1_TX _L_(46) /**< \brief CAN1 signal: TX on PB14 mux H */
|
| 1337 | #define MUX_PB14H_CAN1_TX _L_(7)
|
| 1338 | #define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX)
|
| 1339 | #define PORT_PB14H_CAN1_TX (_UL_(1) << 14)
|
| 1340 | /* ========== PORT definition for GMAC peripheral ========== */
|
| 1341 | #define PIN_PC21L_GMAC_GCOL _L_(85) /**< \brief GMAC signal: GCOL on PC21 mux L */
|
| 1342 | #define MUX_PC21L_GMAC_GCOL _L_(11)
|
| 1343 | #define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL)
|
| 1344 | #define PORT_PC21L_GMAC_GCOL (_UL_(1) << 21)
|
| 1345 | #define PIN_PA16L_GMAC_GCRS _L_(16) /**< \brief GMAC signal: GCRS on PA16 mux L */
|
| 1346 | #define MUX_PA16L_GMAC_GCRS _L_(11)
|
| 1347 | #define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS)
|
| 1348 | #define PORT_PA16L_GMAC_GCRS (_UL_(1) << 16)
|
| 1349 | #define PIN_PA20L_GMAC_GMDC _L_(20) /**< \brief GMAC signal: GMDC on PA20 mux L */
|
| 1350 | #define MUX_PA20L_GMAC_GMDC _L_(11)
|
| 1351 | #define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC)
|
| 1352 | #define PORT_PA20L_GMAC_GMDC (_UL_(1) << 20)
|
| 1353 | #define PIN_PB14L_GMAC_GMDC _L_(46) /**< \brief GMAC signal: GMDC on PB14 mux L */
|
| 1354 | #define MUX_PB14L_GMAC_GMDC _L_(11)
|
| 1355 | #define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC)
|
| 1356 | #define PORT_PB14L_GMAC_GMDC (_UL_(1) << 14)
|
| 1357 | #define PIN_PC11L_GMAC_GMDC _L_(75) /**< \brief GMAC signal: GMDC on PC11 mux L */
|
| 1358 | #define MUX_PC11L_GMAC_GMDC _L_(11)
|
| 1359 | #define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC)
|
| 1360 | #define PORT_PC11L_GMAC_GMDC (_UL_(1) << 11)
|
| 1361 | #define PIN_PA21L_GMAC_GMDIO _L_(21) /**< \brief GMAC signal: GMDIO on PA21 mux L */
|
| 1362 | #define MUX_PA21L_GMAC_GMDIO _L_(11)
|
| 1363 | #define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO)
|
| 1364 | #define PORT_PA21L_GMAC_GMDIO (_UL_(1) << 21)
|
| 1365 | #define PIN_PB15L_GMAC_GMDIO _L_(47) /**< \brief GMAC signal: GMDIO on PB15 mux L */
|
| 1366 | #define MUX_PB15L_GMAC_GMDIO _L_(11)
|
| 1367 | #define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO)
|
| 1368 | #define PORT_PB15L_GMAC_GMDIO (_UL_(1) << 15)
|
| 1369 | #define PIN_PC12L_GMAC_GMDIO _L_(76) /**< \brief GMAC signal: GMDIO on PC12 mux L */
|
| 1370 | #define MUX_PC12L_GMAC_GMDIO _L_(11)
|
| 1371 | #define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO)
|
| 1372 | #define PORT_PC12L_GMAC_GMDIO (_UL_(1) << 12)
|
| 1373 | #define PIN_PA13L_GMAC_GRX0 _L_(13) /**< \brief GMAC signal: GRX0 on PA13 mux L */
|
| 1374 | #define MUX_PA13L_GMAC_GRX0 _L_(11)
|
| 1375 | #define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0)
|
| 1376 | #define PORT_PA13L_GMAC_GRX0 (_UL_(1) << 13)
|
| 1377 | #define PIN_PA12L_GMAC_GRX1 _L_(12) /**< \brief GMAC signal: GRX1 on PA12 mux L */
|
| 1378 | #define MUX_PA12L_GMAC_GRX1 _L_(11)
|
| 1379 | #define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1)
|
| 1380 | #define PORT_PA12L_GMAC_GRX1 (_UL_(1) << 12)
|
| 1381 | #define PIN_PC15L_GMAC_GRX2 _L_(79) /**< \brief GMAC signal: GRX2 on PC15 mux L */
|
| 1382 | #define MUX_PC15L_GMAC_GRX2 _L_(11)
|
| 1383 | #define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2)
|
| 1384 | #define PORT_PC15L_GMAC_GRX2 (_UL_(1) << 15)
|
| 1385 | #define PIN_PC14L_GMAC_GRX3 _L_(78) /**< \brief GMAC signal: GRX3 on PC14 mux L */
|
| 1386 | #define MUX_PC14L_GMAC_GRX3 _L_(11)
|
| 1387 | #define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3)
|
| 1388 | #define PORT_PC14L_GMAC_GRX3 (_UL_(1) << 14)
|
| 1389 | #define PIN_PC18L_GMAC_GRXCK _L_(82) /**< \brief GMAC signal: GRXCK on PC18 mux L */
|
| 1390 | #define MUX_PC18L_GMAC_GRXCK _L_(11)
|
| 1391 | #define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK)
|
| 1392 | #define PORT_PC18L_GMAC_GRXCK (_UL_(1) << 18)
|
| 1393 | #define PIN_PC20L_GMAC_GRXDV _L_(84) /**< \brief GMAC signal: GRXDV on PC20 mux L */
|
| 1394 | #define MUX_PC20L_GMAC_GRXDV _L_(11)
|
| 1395 | #define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV)
|
| 1396 | #define PORT_PC20L_GMAC_GRXDV (_UL_(1) << 20)
|
| 1397 | #define PIN_PA15L_GMAC_GRXER _L_(15) /**< \brief GMAC signal: GRXER on PA15 mux L */
|
| 1398 | #define MUX_PA15L_GMAC_GRXER _L_(11)
|
| 1399 | #define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER)
|
| 1400 | #define PORT_PA15L_GMAC_GRXER (_UL_(1) << 15)
|
| 1401 | #define PIN_PA18L_GMAC_GTX0 _L_(18) /**< \brief GMAC signal: GTX0 on PA18 mux L */
|
| 1402 | #define MUX_PA18L_GMAC_GTX0 _L_(11)
|
| 1403 | #define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0)
|
| 1404 | #define PORT_PA18L_GMAC_GTX0 (_UL_(1) << 18)
|
| 1405 | #define PIN_PA19L_GMAC_GTX1 _L_(19) /**< \brief GMAC signal: GTX1 on PA19 mux L */
|
| 1406 | #define MUX_PA19L_GMAC_GTX1 _L_(11)
|
| 1407 | #define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1)
|
| 1408 | #define PORT_PA19L_GMAC_GTX1 (_UL_(1) << 19)
|
| 1409 | #define PIN_PC16L_GMAC_GTX2 _L_(80) /**< \brief GMAC signal: GTX2 on PC16 mux L */
|
| 1410 | #define MUX_PC16L_GMAC_GTX2 _L_(11)
|
| 1411 | #define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2)
|
| 1412 | #define PORT_PC16L_GMAC_GTX2 (_UL_(1) << 16)
|
| 1413 | #define PIN_PC17L_GMAC_GTX3 _L_(81) /**< \brief GMAC signal: GTX3 on PC17 mux L */
|
| 1414 | #define MUX_PC17L_GMAC_GTX3 _L_(11)
|
| 1415 | #define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3)
|
| 1416 | #define PORT_PC17L_GMAC_GTX3 (_UL_(1) << 17)
|
| 1417 | #define PIN_PA14L_GMAC_GTXCK _L_(14) /**< \brief GMAC signal: GTXCK on PA14 mux L */
|
| 1418 | #define MUX_PA14L_GMAC_GTXCK _L_(11)
|
| 1419 | #define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK)
|
| 1420 | #define PORT_PA14L_GMAC_GTXCK (_UL_(1) << 14)
|
| 1421 | #define PIN_PA17L_GMAC_GTXEN _L_(17) /**< \brief GMAC signal: GTXEN on PA17 mux L */
|
| 1422 | #define MUX_PA17L_GMAC_GTXEN _L_(11)
|
| 1423 | #define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN)
|
| 1424 | #define PORT_PA17L_GMAC_GTXEN (_UL_(1) << 17)
|
| 1425 | #define PIN_PC19L_GMAC_GTXER _L_(83) /**< \brief GMAC signal: GTXER on PC19 mux L */
|
| 1426 | #define MUX_PC19L_GMAC_GTXER _L_(11)
|
| 1427 | #define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER)
|
| 1428 | #define PORT_PC19L_GMAC_GTXER (_UL_(1) << 19)
|
| 1429 | /* ========== PORT definition for TCC2 peripheral ========== */
|
| 1430 | #define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */
|
| 1431 | #define MUX_PA14F_TCC2_WO0 _L_(5)
|
| 1432 | #define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0)
|
| 1433 | #define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14)
|
| 1434 | #define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */
|
| 1435 | #define MUX_PA30F_TCC2_WO0 _L_(5)
|
| 1436 | #define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0)
|
| 1437 | #define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30)
|
| 1438 | #define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */
|
| 1439 | #define MUX_PA15F_TCC2_WO1 _L_(5)
|
| 1440 | #define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1)
|
| 1441 | #define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15)
|
| 1442 | #define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */
|
| 1443 | #define MUX_PA31F_TCC2_WO1 _L_(5)
|
| 1444 | #define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1)
|
| 1445 | #define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31)
|
| 1446 | #define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */
|
| 1447 | #define MUX_PA24F_TCC2_WO2 _L_(5)
|
| 1448 | #define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2)
|
| 1449 | #define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24)
|
| 1450 | #define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */
|
| 1451 | #define MUX_PB02F_TCC2_WO2 _L_(5)
|
| 1452 | #define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2)
|
| 1453 | #define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2)
|
| 1454 | /* ========== PORT definition for TCC3 peripheral ========== */
|
| 1455 | #define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */
|
| 1456 | #define MUX_PB12F_TCC3_WO0 _L_(5)
|
| 1457 | #define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0)
|
| 1458 | #define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12)
|
| 1459 | #define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */
|
| 1460 | #define MUX_PB16F_TCC3_WO0 _L_(5)
|
| 1461 | #define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0)
|
| 1462 | #define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16)
|
| 1463 | #define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */
|
| 1464 | #define MUX_PB13F_TCC3_WO1 _L_(5)
|
| 1465 | #define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1)
|
| 1466 | #define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13)
|
| 1467 | #define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */
|
| 1468 | #define MUX_PB17F_TCC3_WO1 _L_(5)
|
| 1469 | #define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1)
|
| 1470 | #define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17)
|
| 1471 | /* ========== PORT definition for TC4 peripheral ========== */
|
| 1472 | #define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */
|
| 1473 | #define MUX_PA22E_TC4_WO0 _L_(4)
|
| 1474 | #define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
|
| 1475 | #define PORT_PA22E_TC4_WO0 (_UL_(1) << 22)
|
| 1476 | #define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */
|
| 1477 | #define MUX_PB08E_TC4_WO0 _L_(4)
|
| 1478 | #define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
|
| 1479 | #define PORT_PB08E_TC4_WO0 (_UL_(1) << 8)
|
| 1480 | #define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */
|
| 1481 | #define MUX_PB12E_TC4_WO0 _L_(4)
|
| 1482 | #define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
|
| 1483 | #define PORT_PB12E_TC4_WO0 (_UL_(1) << 12)
|
| 1484 | #define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */
|
| 1485 | #define MUX_PA23E_TC4_WO1 _L_(4)
|
| 1486 | #define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
|
| 1487 | #define PORT_PA23E_TC4_WO1 (_UL_(1) << 23)
|
| 1488 | #define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */
|
| 1489 | #define MUX_PB09E_TC4_WO1 _L_(4)
|
| 1490 | #define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
|
| 1491 | #define PORT_PB09E_TC4_WO1 (_UL_(1) << 9)
|
| 1492 | #define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */
|
| 1493 | #define MUX_PB13E_TC4_WO1 _L_(4)
|
| 1494 | #define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
|
| 1495 | #define PORT_PB13E_TC4_WO1 (_UL_(1) << 13)
|
| 1496 | /* ========== PORT definition for TC5 peripheral ========== */
|
| 1497 | #define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */
|
| 1498 | #define MUX_PA24E_TC5_WO0 _L_(4)
|
| 1499 | #define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
|
| 1500 | #define PORT_PA24E_TC5_WO0 (_UL_(1) << 24)
|
| 1501 | #define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */
|
| 1502 | #define MUX_PB10E_TC5_WO0 _L_(4)
|
| 1503 | #define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
|
| 1504 | #define PORT_PB10E_TC5_WO0 (_UL_(1) << 10)
|
| 1505 | #define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */
|
| 1506 | #define MUX_PB14E_TC5_WO0 _L_(4)
|
| 1507 | #define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
|
| 1508 | #define PORT_PB14E_TC5_WO0 (_UL_(1) << 14)
|
| 1509 | #define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */
|
| 1510 | #define MUX_PA25E_TC5_WO1 _L_(4)
|
| 1511 | #define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
|
| 1512 | #define PORT_PA25E_TC5_WO1 (_UL_(1) << 25)
|
| 1513 | #define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */
|
| 1514 | #define MUX_PB11E_TC5_WO1 _L_(4)
|
| 1515 | #define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
|
| 1516 | #define PORT_PB11E_TC5_WO1 (_UL_(1) << 11)
|
| 1517 | #define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */
|
| 1518 | #define MUX_PB15E_TC5_WO1 _L_(4)
|
| 1519 | #define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
|
| 1520 | #define PORT_PB15E_TC5_WO1 (_UL_(1) << 15)
|
| 1521 | /* ========== PORT definition for PDEC peripheral ========== */
|
| 1522 | #define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */
|
| 1523 | #define MUX_PB18G_PDEC_QDI0 _L_(6)
|
| 1524 | #define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0)
|
| 1525 | #define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18)
|
| 1526 | #define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */
|
| 1527 | #define MUX_PB23G_PDEC_QDI0 _L_(6)
|
| 1528 | #define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0)
|
| 1529 | #define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23)
|
| 1530 | #define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */
|
| 1531 | #define MUX_PC16G_PDEC_QDI0 _L_(6)
|
| 1532 | #define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0)
|
| 1533 | #define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16)
|
| 1534 | #define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */
|
| 1535 | #define MUX_PA24G_PDEC_QDI0 _L_(6)
|
| 1536 | #define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0)
|
| 1537 | #define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24)
|
| 1538 | #define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */
|
| 1539 | #define MUX_PB19G_PDEC_QDI1 _L_(6)
|
| 1540 | #define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1)
|
| 1541 | #define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19)
|
| 1542 | #define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */
|
| 1543 | #define MUX_PB24G_PDEC_QDI1 _L_(6)
|
| 1544 | #define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1)
|
| 1545 | #define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24)
|
| 1546 | #define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */
|
| 1547 | #define MUX_PC17G_PDEC_QDI1 _L_(6)
|
| 1548 | #define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1)
|
| 1549 | #define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17)
|
| 1550 | #define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */
|
| 1551 | #define MUX_PA25G_PDEC_QDI1 _L_(6)
|
| 1552 | #define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1)
|
| 1553 | #define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25)
|
| 1554 | #define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */
|
| 1555 | #define MUX_PB20G_PDEC_QDI2 _L_(6)
|
| 1556 | #define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2)
|
| 1557 | #define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20)
|
| 1558 | #define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */
|
| 1559 | #define MUX_PB25G_PDEC_QDI2 _L_(6)
|
| 1560 | #define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2)
|
| 1561 | #define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25)
|
| 1562 | #define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */
|
| 1563 | #define MUX_PC18G_PDEC_QDI2 _L_(6)
|
| 1564 | #define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2)
|
| 1565 | #define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18)
|
| 1566 | #define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */
|
| 1567 | #define MUX_PB22G_PDEC_QDI2 _L_(6)
|
| 1568 | #define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2)
|
| 1569 | #define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22)
|
| 1570 | /* ========== PORT definition for AC peripheral ========== */
|
| 1571 | #define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */
|
| 1572 | #define MUX_PA04B_AC_AIN0 _L_(1)
|
| 1573 | #define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
|
| 1574 | #define PORT_PA04B_AC_AIN0 (_UL_(1) << 4)
|
| 1575 | #define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */
|
| 1576 | #define MUX_PA05B_AC_AIN1 _L_(1)
|
| 1577 | #define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
|
| 1578 | #define PORT_PA05B_AC_AIN1 (_UL_(1) << 5)
|
| 1579 | #define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */
|
| 1580 | #define MUX_PA06B_AC_AIN2 _L_(1)
|
| 1581 | #define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
|
| 1582 | #define PORT_PA06B_AC_AIN2 (_UL_(1) << 6)
|
| 1583 | #define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */
|
| 1584 | #define MUX_PA07B_AC_AIN3 _L_(1)
|
| 1585 | #define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
|
| 1586 | #define PORT_PA07B_AC_AIN3 (_UL_(1) << 7)
|
| 1587 | #define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */
|
| 1588 | #define MUX_PA12M_AC_CMP0 _L_(12)
|
| 1589 | #define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0)
|
| 1590 | #define PORT_PA12M_AC_CMP0 (_UL_(1) << 12)
|
| 1591 | #define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */
|
| 1592 | #define MUX_PA18M_AC_CMP0 _L_(12)
|
| 1593 | #define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0)
|
| 1594 | #define PORT_PA18M_AC_CMP0 (_UL_(1) << 18)
|
| 1595 | #define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */
|
| 1596 | #define MUX_PB24M_AC_CMP0 _L_(12)
|
| 1597 | #define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0)
|
| 1598 | #define PORT_PB24M_AC_CMP0 (_UL_(1) << 24)
|
| 1599 | #define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */
|
| 1600 | #define MUX_PA13M_AC_CMP1 _L_(12)
|
| 1601 | #define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1)
|
| 1602 | #define PORT_PA13M_AC_CMP1 (_UL_(1) << 13)
|
| 1603 | #define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */
|
| 1604 | #define MUX_PA19M_AC_CMP1 _L_(12)
|
| 1605 | #define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1)
|
| 1606 | #define PORT_PA19M_AC_CMP1 (_UL_(1) << 19)
|
| 1607 | #define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */
|
| 1608 | #define MUX_PB25M_AC_CMP1 _L_(12)
|
| 1609 | #define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1)
|
| 1610 | #define PORT_PB25M_AC_CMP1 (_UL_(1) << 25)
|
| 1611 | /* ========== PORT definition for QSPI peripheral ========== */
|
| 1612 | #define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */
|
| 1613 | #define MUX_PB11H_QSPI_CS _L_(7)
|
| 1614 | #define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS)
|
| 1615 | #define PORT_PB11H_QSPI_CS (_UL_(1) << 11)
|
| 1616 | #define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */
|
| 1617 | #define MUX_PA08H_QSPI_DATA0 _L_(7)
|
| 1618 | #define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0)
|
| 1619 | #define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8)
|
| 1620 | #define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */
|
| 1621 | #define MUX_PA09H_QSPI_DATA1 _L_(7)
|
| 1622 | #define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1)
|
| 1623 | #define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9)
|
| 1624 | #define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */
|
| 1625 | #define MUX_PA10H_QSPI_DATA2 _L_(7)
|
| 1626 | #define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2)
|
| 1627 | #define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10)
|
| 1628 | #define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */
|
| 1629 | #define MUX_PA11H_QSPI_DATA3 _L_(7)
|
| 1630 | #define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3)
|
| 1631 | #define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11)
|
| 1632 | #define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */
|
| 1633 | #define MUX_PB10H_QSPI_SCK _L_(7)
|
| 1634 | #define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK)
|
| 1635 | #define PORT_PB10H_QSPI_SCK (_UL_(1) << 10)
|
| 1636 | /* ========== PORT definition for CCL peripheral ========== */
|
| 1637 | #define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */
|
| 1638 | #define MUX_PA04N_CCL_IN0 _L_(13)
|
| 1639 | #define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0)
|
| 1640 | #define PORT_PA04N_CCL_IN0 (_UL_(1) << 4)
|
| 1641 | #define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */
|
| 1642 | #define MUX_PA16N_CCL_IN0 _L_(13)
|
| 1643 | #define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0)
|
| 1644 | #define PORT_PA16N_CCL_IN0 (_UL_(1) << 16)
|
| 1645 | #define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */
|
| 1646 | #define MUX_PB22N_CCL_IN0 _L_(13)
|
| 1647 | #define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0)
|
| 1648 | #define PORT_PB22N_CCL_IN0 (_UL_(1) << 22)
|
| 1649 | #define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */
|
| 1650 | #define MUX_PA05N_CCL_IN1 _L_(13)
|
| 1651 | #define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1)
|
| 1652 | #define PORT_PA05N_CCL_IN1 (_UL_(1) << 5)
|
| 1653 | #define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */
|
| 1654 | #define MUX_PA17N_CCL_IN1 _L_(13)
|
| 1655 | #define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1)
|
| 1656 | #define PORT_PA17N_CCL_IN1 (_UL_(1) << 17)
|
| 1657 | #define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */
|
| 1658 | #define MUX_PB00N_CCL_IN1 _L_(13)
|
| 1659 | #define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1)
|
| 1660 | #define PORT_PB00N_CCL_IN1 (_UL_(1) << 0)
|
| 1661 | #define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */
|
| 1662 | #define MUX_PA06N_CCL_IN2 _L_(13)
|
| 1663 | #define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2)
|
| 1664 | #define PORT_PA06N_CCL_IN2 (_UL_(1) << 6)
|
| 1665 | #define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */
|
| 1666 | #define MUX_PA18N_CCL_IN2 _L_(13)
|
| 1667 | #define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2)
|
| 1668 | #define PORT_PA18N_CCL_IN2 (_UL_(1) << 18)
|
| 1669 | #define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */
|
| 1670 | #define MUX_PB01N_CCL_IN2 _L_(13)
|
| 1671 | #define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2)
|
| 1672 | #define PORT_PB01N_CCL_IN2 (_UL_(1) << 1)
|
| 1673 | #define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */
|
| 1674 | #define MUX_PA08N_CCL_IN3 _L_(13)
|
| 1675 | #define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3)
|
| 1676 | #define PORT_PA08N_CCL_IN3 (_UL_(1) << 8)
|
| 1677 | #define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */
|
| 1678 | #define MUX_PA30N_CCL_IN3 _L_(13)
|
| 1679 | #define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3)
|
| 1680 | #define PORT_PA30N_CCL_IN3 (_UL_(1) << 30)
|
| 1681 | #define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */
|
| 1682 | #define MUX_PA09N_CCL_IN4 _L_(13)
|
| 1683 | #define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4)
|
| 1684 | #define PORT_PA09N_CCL_IN4 (_UL_(1) << 9)
|
| 1685 | #define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */
|
| 1686 | #define MUX_PC27N_CCL_IN4 _L_(13)
|
| 1687 | #define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4)
|
| 1688 | #define PORT_PC27N_CCL_IN4 (_UL_(1) << 27)
|
| 1689 | #define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */
|
| 1690 | #define MUX_PA10N_CCL_IN5 _L_(13)
|
| 1691 | #define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5)
|
| 1692 | #define PORT_PA10N_CCL_IN5 (_UL_(1) << 10)
|
| 1693 | #define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */
|
| 1694 | #define MUX_PC28N_CCL_IN5 _L_(13)
|
| 1695 | #define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5)
|
| 1696 | #define PORT_PC28N_CCL_IN5 (_UL_(1) << 28)
|
| 1697 | #define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */
|
| 1698 | #define MUX_PA22N_CCL_IN6 _L_(13)
|
| 1699 | #define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6)
|
| 1700 | #define PORT_PA22N_CCL_IN6 (_UL_(1) << 22)
|
| 1701 | #define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */
|
| 1702 | #define MUX_PB06N_CCL_IN6 _L_(13)
|
| 1703 | #define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6)
|
| 1704 | #define PORT_PB06N_CCL_IN6 (_UL_(1) << 6)
|
| 1705 | #define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */
|
| 1706 | #define MUX_PA23N_CCL_IN7 _L_(13)
|
| 1707 | #define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7)
|
| 1708 | #define PORT_PA23N_CCL_IN7 (_UL_(1) << 23)
|
| 1709 | #define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */
|
| 1710 | #define MUX_PB07N_CCL_IN7 _L_(13)
|
| 1711 | #define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7)
|
| 1712 | #define PORT_PB07N_CCL_IN7 (_UL_(1) << 7)
|
| 1713 | #define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */
|
| 1714 | #define MUX_PA24N_CCL_IN8 _L_(13)
|
| 1715 | #define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8)
|
| 1716 | #define PORT_PA24N_CCL_IN8 (_UL_(1) << 24)
|
| 1717 | #define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */
|
| 1718 | #define MUX_PB08N_CCL_IN8 _L_(13)
|
| 1719 | #define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8)
|
| 1720 | #define PORT_PB08N_CCL_IN8 (_UL_(1) << 8)
|
| 1721 | #define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */
|
| 1722 | #define MUX_PB14N_CCL_IN9 _L_(13)
|
| 1723 | #define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9)
|
| 1724 | #define PORT_PB14N_CCL_IN9 (_UL_(1) << 14)
|
| 1725 | #define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */
|
| 1726 | #define MUX_PC20N_CCL_IN9 _L_(13)
|
| 1727 | #define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9)
|
| 1728 | #define PORT_PC20N_CCL_IN9 (_UL_(1) << 20)
|
| 1729 | #define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */
|
| 1730 | #define MUX_PB15N_CCL_IN10 _L_(13)
|
| 1731 | #define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10)
|
| 1732 | #define PORT_PB15N_CCL_IN10 (_UL_(1) << 15)
|
| 1733 | #define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */
|
| 1734 | #define MUX_PC21N_CCL_IN10 _L_(13)
|
| 1735 | #define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10)
|
| 1736 | #define PORT_PC21N_CCL_IN10 (_UL_(1) << 21)
|
| 1737 | #define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */
|
| 1738 | #define MUX_PB10N_CCL_IN11 _L_(13)
|
| 1739 | #define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11)
|
| 1740 | #define PORT_PB10N_CCL_IN11 (_UL_(1) << 10)
|
| 1741 | #define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */
|
| 1742 | #define MUX_PB16N_CCL_IN11 _L_(13)
|
| 1743 | #define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11)
|
| 1744 | #define PORT_PB16N_CCL_IN11 (_UL_(1) << 16)
|
| 1745 | #define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */
|
| 1746 | #define MUX_PA07N_CCL_OUT0 _L_(13)
|
| 1747 | #define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0)
|
| 1748 | #define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7)
|
| 1749 | #define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */
|
| 1750 | #define MUX_PA19N_CCL_OUT0 _L_(13)
|
| 1751 | #define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0)
|
| 1752 | #define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19)
|
| 1753 | #define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */
|
| 1754 | #define MUX_PB02N_CCL_OUT0 _L_(13)
|
| 1755 | #define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0)
|
| 1756 | #define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2)
|
| 1757 | #define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */
|
| 1758 | #define MUX_PB23N_CCL_OUT0 _L_(13)
|
| 1759 | #define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0)
|
| 1760 | #define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23)
|
| 1761 | #define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */
|
| 1762 | #define MUX_PA11N_CCL_OUT1 _L_(13)
|
| 1763 | #define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1)
|
| 1764 | #define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11)
|
| 1765 | #define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */
|
| 1766 | #define MUX_PA31N_CCL_OUT1 _L_(13)
|
| 1767 | #define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1)
|
| 1768 | #define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31)
|
| 1769 | #define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */
|
| 1770 | #define MUX_PB11N_CCL_OUT1 _L_(13)
|
| 1771 | #define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1)
|
| 1772 | #define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11)
|
| 1773 | #define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */
|
| 1774 | #define MUX_PA25N_CCL_OUT2 _L_(13)
|
| 1775 | #define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2)
|
| 1776 | #define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25)
|
| 1777 | #define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */
|
| 1778 | #define MUX_PB09N_CCL_OUT2 _L_(13)
|
| 1779 | #define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2)
|
| 1780 | #define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9)
|
| 1781 | #define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */
|
| 1782 | #define MUX_PB17N_CCL_OUT3 _L_(13)
|
| 1783 | #define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3)
|
| 1784 | #define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17)
|
| 1785 | /* ========== PORT definition for SERCOM4 peripheral ========== */
|
| 1786 | #define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */
|
| 1787 | #define MUX_PA13D_SERCOM4_PAD0 _L_(3)
|
| 1788 | #define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0)
|
| 1789 | #define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13)
|
| 1790 | #define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
|
| 1791 | #define MUX_PB08D_SERCOM4_PAD0 _L_(3)
|
| 1792 | #define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
|
| 1793 | #define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8)
|
| 1794 | #define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
|
| 1795 | #define MUX_PB12C_SERCOM4_PAD0 _L_(2)
|
| 1796 | #define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
|
| 1797 | #define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12)
|
| 1798 | #define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */
|
| 1799 | #define MUX_PA12D_SERCOM4_PAD1 _L_(3)
|
| 1800 | #define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1)
|
| 1801 | #define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12)
|
| 1802 | #define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
|
| 1803 | #define MUX_PB09D_SERCOM4_PAD1 _L_(3)
|
| 1804 | #define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
|
| 1805 | #define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9)
|
| 1806 | #define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
|
| 1807 | #define MUX_PB13C_SERCOM4_PAD1 _L_(2)
|
| 1808 | #define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
|
| 1809 | #define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13)
|
| 1810 | #define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
|
| 1811 | #define MUX_PA14D_SERCOM4_PAD2 _L_(3)
|
| 1812 | #define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
|
| 1813 | #define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14)
|
| 1814 | #define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
|
| 1815 | #define MUX_PB10D_SERCOM4_PAD2 _L_(3)
|
| 1816 | #define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
|
| 1817 | #define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10)
|
| 1818 | #define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
|
| 1819 | #define MUX_PB14C_SERCOM4_PAD2 _L_(2)
|
| 1820 | #define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
|
| 1821 | #define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14)
|
| 1822 | #define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
|
| 1823 | #define MUX_PB11D_SERCOM4_PAD3 _L_(3)
|
| 1824 | #define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
|
| 1825 | #define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11)
|
| 1826 | #define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
|
| 1827 | #define MUX_PA15D_SERCOM4_PAD3 _L_(3)
|
| 1828 | #define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
|
| 1829 | #define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15)
|
| 1830 | #define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
|
| 1831 | #define MUX_PB15C_SERCOM4_PAD3 _L_(2)
|
| 1832 | #define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
|
| 1833 | #define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15)
|
| 1834 | /* ========== PORT definition for SERCOM5 peripheral ========== */
|
| 1835 | #define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */
|
| 1836 | #define MUX_PA23D_SERCOM5_PAD0 _L_(3)
|
| 1837 | #define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0)
|
| 1838 | #define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23)
|
| 1839 | #define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
|
| 1840 | #define MUX_PB02D_SERCOM5_PAD0 _L_(3)
|
| 1841 | #define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
|
| 1842 | #define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2)
|
| 1843 | #define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */
|
| 1844 | #define MUX_PB31D_SERCOM5_PAD0 _L_(3)
|
| 1845 | #define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0)
|
| 1846 | #define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31)
|
| 1847 | #define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
|
| 1848 | #define MUX_PB16C_SERCOM5_PAD0 _L_(2)
|
| 1849 | #define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
|
| 1850 | #define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16)
|
| 1851 | #define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */
|
| 1852 | #define MUX_PA22D_SERCOM5_PAD1 _L_(3)
|
| 1853 | #define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1)
|
| 1854 | #define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22)
|
| 1855 | #define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
|
| 1856 | #define MUX_PB03D_SERCOM5_PAD1 _L_(3)
|
| 1857 | #define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
|
| 1858 | #define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3)
|
| 1859 | #define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */
|
| 1860 | #define MUX_PB30D_SERCOM5_PAD1 _L_(3)
|
| 1861 | #define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1)
|
| 1862 | #define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30)
|
| 1863 | #define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
|
| 1864 | #define MUX_PB17C_SERCOM5_PAD1 _L_(2)
|
| 1865 | #define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
|
| 1866 | #define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17)
|
| 1867 | #define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
|
| 1868 | #define MUX_PA24D_SERCOM5_PAD2 _L_(3)
|
| 1869 | #define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
|
| 1870 | #define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24)
|
| 1871 | #define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
|
| 1872 | #define MUX_PB00D_SERCOM5_PAD2 _L_(3)
|
| 1873 | #define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
|
| 1874 | #define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0)
|
| 1875 | #define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
|
| 1876 | #define MUX_PB22D_SERCOM5_PAD2 _L_(3)
|
| 1877 | #define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
|
| 1878 | #define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22)
|
| 1879 | #define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
|
| 1880 | #define MUX_PA20C_SERCOM5_PAD2 _L_(2)
|
| 1881 | #define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
|
| 1882 | #define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20)
|
| 1883 | #define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */
|
| 1884 | #define MUX_PB18C_SERCOM5_PAD2 _L_(2)
|
| 1885 | #define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2)
|
| 1886 | #define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18)
|
| 1887 | #define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
|
| 1888 | #define MUX_PA25D_SERCOM5_PAD3 _L_(3)
|
| 1889 | #define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
|
| 1890 | #define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25)
|
| 1891 | #define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
|
| 1892 | #define MUX_PB01D_SERCOM5_PAD3 _L_(3)
|
| 1893 | #define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
|
| 1894 | #define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1)
|
| 1895 | #define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
|
| 1896 | #define MUX_PB23D_SERCOM5_PAD3 _L_(3)
|
| 1897 | #define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
|
| 1898 | #define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23)
|
| 1899 | #define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
|
| 1900 | #define MUX_PA21C_SERCOM5_PAD3 _L_(2)
|
| 1901 | #define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
|
| 1902 | #define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21)
|
| 1903 | #define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */
|
| 1904 | #define MUX_PB19C_SERCOM5_PAD3 _L_(2)
|
| 1905 | #define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3)
|
| 1906 | #define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19)
|
| 1907 | /* ========== PORT definition for SERCOM6 peripheral ========== */
|
| 1908 | #define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */
|
| 1909 | #define MUX_PC13D_SERCOM6_PAD0 _L_(3)
|
| 1910 | #define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0)
|
| 1911 | #define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13)
|
| 1912 | #define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */
|
| 1913 | #define MUX_PC16C_SERCOM6_PAD0 _L_(2)
|
| 1914 | #define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0)
|
| 1915 | #define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16)
|
| 1916 | #define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */
|
| 1917 | #define MUX_PC12D_SERCOM6_PAD1 _L_(3)
|
| 1918 | #define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1)
|
| 1919 | #define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12)
|
| 1920 | #define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */
|
| 1921 | #define MUX_PC05C_SERCOM6_PAD1 _L_(2)
|
| 1922 | #define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1)
|
| 1923 | #define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5)
|
| 1924 | #define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */
|
| 1925 | #define MUX_PC17C_SERCOM6_PAD1 _L_(2)
|
| 1926 | #define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1)
|
| 1927 | #define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17)
|
| 1928 | #define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */
|
| 1929 | #define MUX_PC14D_SERCOM6_PAD2 _L_(3)
|
| 1930 | #define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2)
|
| 1931 | #define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14)
|
| 1932 | #define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */
|
| 1933 | #define MUX_PC06C_SERCOM6_PAD2 _L_(2)
|
| 1934 | #define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2)
|
| 1935 | #define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6)
|
| 1936 | #define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */
|
| 1937 | #define MUX_PC10C_SERCOM6_PAD2 _L_(2)
|
| 1938 | #define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2)
|
| 1939 | #define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10)
|
| 1940 | #define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */
|
| 1941 | #define MUX_PC18C_SERCOM6_PAD2 _L_(2)
|
| 1942 | #define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2)
|
| 1943 | #define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18)
|
| 1944 | #define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */
|
| 1945 | #define MUX_PC15D_SERCOM6_PAD3 _L_(3)
|
| 1946 | #define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3)
|
| 1947 | #define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15)
|
| 1948 | #define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */
|
| 1949 | #define MUX_PC07C_SERCOM6_PAD3 _L_(2)
|
| 1950 | #define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3)
|
| 1951 | #define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7)
|
| 1952 | #define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */
|
| 1953 | #define MUX_PC11C_SERCOM6_PAD3 _L_(2)
|
| 1954 | #define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3)
|
| 1955 | #define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11)
|
| 1956 | #define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */
|
| 1957 | #define MUX_PC19C_SERCOM6_PAD3 _L_(2)
|
| 1958 | #define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3)
|
| 1959 | #define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19)
|
| 1960 | /* ========== PORT definition for SERCOM7 peripheral ========== */
|
| 1961 | #define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */
|
| 1962 | #define MUX_PB21D_SERCOM7_PAD0 _L_(3)
|
| 1963 | #define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0)
|
| 1964 | #define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21)
|
| 1965 | #define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */
|
| 1966 | #define MUX_PB30C_SERCOM7_PAD0 _L_(2)
|
| 1967 | #define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0)
|
| 1968 | #define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30)
|
| 1969 | #define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */
|
| 1970 | #define MUX_PC12C_SERCOM7_PAD0 _L_(2)
|
| 1971 | #define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0)
|
| 1972 | #define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12)
|
| 1973 | #define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */
|
| 1974 | #define MUX_PB20D_SERCOM7_PAD1 _L_(3)
|
| 1975 | #define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1)
|
| 1976 | #define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20)
|
| 1977 | #define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */
|
| 1978 | #define MUX_PB31C_SERCOM7_PAD1 _L_(2)
|
| 1979 | #define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1)
|
| 1980 | #define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31)
|
| 1981 | #define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */
|
| 1982 | #define MUX_PC13C_SERCOM7_PAD1 _L_(2)
|
| 1983 | #define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1)
|
| 1984 | #define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13)
|
| 1985 | #define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */
|
| 1986 | #define MUX_PB18D_SERCOM7_PAD2 _L_(3)
|
| 1987 | #define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2)
|
| 1988 | #define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18)
|
| 1989 | #define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */
|
| 1990 | #define MUX_PC10D_SERCOM7_PAD2 _L_(3)
|
| 1991 | #define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2)
|
| 1992 | #define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10)
|
| 1993 | #define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */
|
| 1994 | #define MUX_PC14C_SERCOM7_PAD2 _L_(2)
|
| 1995 | #define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2)
|
| 1996 | #define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14)
|
| 1997 | #define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */
|
| 1998 | #define MUX_PA30C_SERCOM7_PAD2 _L_(2)
|
| 1999 | #define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2)
|
| 2000 | #define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30)
|
| 2001 | #define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */
|
| 2002 | #define MUX_PB19D_SERCOM7_PAD3 _L_(3)
|
| 2003 | #define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3)
|
| 2004 | #define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19)
|
| 2005 | #define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */
|
| 2006 | #define MUX_PC11D_SERCOM7_PAD3 _L_(3)
|
| 2007 | #define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3)
|
| 2008 | #define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11)
|
| 2009 | #define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */
|
| 2010 | #define MUX_PC15C_SERCOM7_PAD3 _L_(2)
|
| 2011 | #define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3)
|
| 2012 | #define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15)
|
| 2013 | #define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */
|
| 2014 | #define MUX_PA31C_SERCOM7_PAD3 _L_(2)
|
| 2015 | #define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3)
|
| 2016 | #define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31)
|
| 2017 | /* ========== PORT definition for TCC4 peripheral ========== */
|
| 2018 | #define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */
|
| 2019 | #define MUX_PB14F_TCC4_WO0 _L_(5)
|
| 2020 | #define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0)
|
| 2021 | #define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14)
|
| 2022 | #define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */
|
| 2023 | #define MUX_PB30F_TCC4_WO0 _L_(5)
|
| 2024 | #define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0)
|
| 2025 | #define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30)
|
| 2026 | #define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */
|
| 2027 | #define MUX_PB15F_TCC4_WO1 _L_(5)
|
| 2028 | #define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1)
|
| 2029 | #define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15)
|
| 2030 | #define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */
|
| 2031 | #define MUX_PB31F_TCC4_WO1 _L_(5)
|
| 2032 | #define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1)
|
| 2033 | #define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31)
|
| 2034 | /* ========== PORT definition for TC6 peripheral ========== */
|
| 2035 | #define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */
|
| 2036 | #define MUX_PA30E_TC6_WO0 _L_(4)
|
| 2037 | #define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0)
|
| 2038 | #define PORT_PA30E_TC6_WO0 (_UL_(1) << 30)
|
| 2039 | #define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */
|
| 2040 | #define MUX_PB02E_TC6_WO0 _L_(4)
|
| 2041 | #define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
|
| 2042 | #define PORT_PB02E_TC6_WO0 (_UL_(1) << 2)
|
| 2043 | #define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */
|
| 2044 | #define MUX_PB16E_TC6_WO0 _L_(4)
|
| 2045 | #define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
|
| 2046 | #define PORT_PB16E_TC6_WO0 (_UL_(1) << 16)
|
| 2047 | #define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */
|
| 2048 | #define MUX_PA31E_TC6_WO1 _L_(4)
|
| 2049 | #define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1)
|
| 2050 | #define PORT_PA31E_TC6_WO1 (_UL_(1) << 31)
|
| 2051 | #define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */
|
| 2052 | #define MUX_PB03E_TC6_WO1 _L_(4)
|
| 2053 | #define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
|
| 2054 | #define PORT_PB03E_TC6_WO1 (_UL_(1) << 3)
|
| 2055 | #define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */
|
| 2056 | #define MUX_PB17E_TC6_WO1 _L_(4)
|
| 2057 | #define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
|
| 2058 | #define PORT_PB17E_TC6_WO1 (_UL_(1) << 17)
|
| 2059 | /* ========== PORT definition for TC7 peripheral ========== */
|
| 2060 | #define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */
|
| 2061 | #define MUX_PA20E_TC7_WO0 _L_(4)
|
| 2062 | #define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
|
| 2063 | #define PORT_PA20E_TC7_WO0 (_UL_(1) << 20)
|
| 2064 | #define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */
|
| 2065 | #define MUX_PB00E_TC7_WO0 _L_(4)
|
| 2066 | #define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
|
| 2067 | #define PORT_PB00E_TC7_WO0 (_UL_(1) << 0)
|
| 2068 | #define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */
|
| 2069 | #define MUX_PB22E_TC7_WO0 _L_(4)
|
| 2070 | #define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
|
| 2071 | #define PORT_PB22E_TC7_WO0 (_UL_(1) << 22)
|
| 2072 | #define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */
|
| 2073 | #define MUX_PA21E_TC7_WO1 _L_(4)
|
| 2074 | #define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
|
| 2075 | #define PORT_PA21E_TC7_WO1 (_UL_(1) << 21)
|
| 2076 | #define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */
|
| 2077 | #define MUX_PB01E_TC7_WO1 _L_(4)
|
| 2078 | #define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
|
| 2079 | #define PORT_PB01E_TC7_WO1 (_UL_(1) << 1)
|
| 2080 | #define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */
|
| 2081 | #define MUX_PB23E_TC7_WO1 _L_(4)
|
| 2082 | #define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
|
| 2083 | #define PORT_PB23E_TC7_WO1 (_UL_(1) << 23)
|
| 2084 | /* ========== PORT definition for ADC0 peripheral ========== */
|
| 2085 | #define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */
|
| 2086 | #define MUX_PA02B_ADC0_AIN0 _L_(1)
|
| 2087 | #define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0)
|
| 2088 | #define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2)
|
| 2089 | #define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */
|
| 2090 | #define MUX_PA03B_ADC0_AIN1 _L_(1)
|
| 2091 | #define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1)
|
| 2092 | #define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3)
|
| 2093 | #define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */
|
| 2094 | #define MUX_PB08B_ADC0_AIN2 _L_(1)
|
| 2095 | #define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2)
|
| 2096 | #define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8)
|
| 2097 | #define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */
|
| 2098 | #define MUX_PB09B_ADC0_AIN3 _L_(1)
|
| 2099 | #define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3)
|
| 2100 | #define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9)
|
| 2101 | #define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */
|
| 2102 | #define MUX_PA04B_ADC0_AIN4 _L_(1)
|
| 2103 | #define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4)
|
| 2104 | #define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4)
|
| 2105 | #define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */
|
| 2106 | #define MUX_PA05B_ADC0_AIN5 _L_(1)
|
| 2107 | #define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5)
|
| 2108 | #define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5)
|
| 2109 | #define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */
|
| 2110 | #define MUX_PA06B_ADC0_AIN6 _L_(1)
|
| 2111 | #define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6)
|
| 2112 | #define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6)
|
| 2113 | #define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */
|
| 2114 | #define MUX_PA07B_ADC0_AIN7 _L_(1)
|
| 2115 | #define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7)
|
| 2116 | #define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7)
|
| 2117 | #define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */
|
| 2118 | #define MUX_PA08B_ADC0_AIN8 _L_(1)
|
| 2119 | #define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8)
|
| 2120 | #define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8)
|
| 2121 | #define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */
|
| 2122 | #define MUX_PA09B_ADC0_AIN9 _L_(1)
|
| 2123 | #define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9)
|
| 2124 | #define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9)
|
| 2125 | #define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */
|
| 2126 | #define MUX_PA10B_ADC0_AIN10 _L_(1)
|
| 2127 | #define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10)
|
| 2128 | #define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10)
|
| 2129 | #define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */
|
| 2130 | #define MUX_PA11B_ADC0_AIN11 _L_(1)
|
| 2131 | #define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11)
|
| 2132 | #define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11)
|
| 2133 | #define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */
|
| 2134 | #define MUX_PB00B_ADC0_AIN12 _L_(1)
|
| 2135 | #define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12)
|
| 2136 | #define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0)
|
| 2137 | #define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */
|
| 2138 | #define MUX_PB01B_ADC0_AIN13 _L_(1)
|
| 2139 | #define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13)
|
| 2140 | #define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1)
|
| 2141 | #define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */
|
| 2142 | #define MUX_PB02B_ADC0_AIN14 _L_(1)
|
| 2143 | #define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14)
|
| 2144 | #define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2)
|
| 2145 | #define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */
|
| 2146 | #define MUX_PB03B_ADC0_AIN15 _L_(1)
|
| 2147 | #define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15)
|
| 2148 | #define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3)
|
| 2149 | #define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */
|
| 2150 | #define MUX_PA03O_ADC0_DRV0 _L_(14)
|
| 2151 | #define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0)
|
| 2152 | #define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3)
|
| 2153 | #define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */
|
| 2154 | #define MUX_PB08O_ADC0_DRV1 _L_(14)
|
| 2155 | #define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1)
|
| 2156 | #define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8)
|
| 2157 | #define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */
|
| 2158 | #define MUX_PB09O_ADC0_DRV2 _L_(14)
|
| 2159 | #define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2)
|
| 2160 | #define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9)
|
| 2161 | #define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */
|
| 2162 | #define MUX_PA04O_ADC0_DRV3 _L_(14)
|
| 2163 | #define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3)
|
| 2164 | #define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4)
|
| 2165 | #define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */
|
| 2166 | #define MUX_PA06O_ADC0_DRV4 _L_(14)
|
| 2167 | #define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4)
|
| 2168 | #define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6)
|
| 2169 | #define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */
|
| 2170 | #define MUX_PA07O_ADC0_DRV5 _L_(14)
|
| 2171 | #define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
|
| 2172 | #define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7)
|
| 2173 | #define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */
|
| 2174 | #define MUX_PA08O_ADC0_DRV6 _L_(14)
|
| 2175 | #define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6)
|
| 2176 | #define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8)
|
| 2177 | #define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */
|
| 2178 | #define MUX_PA09O_ADC0_DRV7 _L_(14)
|
| 2179 | #define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7)
|
| 2180 | #define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9)
|
| 2181 | #define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */
|
| 2182 | #define MUX_PA10O_ADC0_DRV8 _L_(14)
|
| 2183 | #define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8)
|
| 2184 | #define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10)
|
| 2185 | #define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */
|
| 2186 | #define MUX_PA11O_ADC0_DRV9 _L_(14)
|
| 2187 | #define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9)
|
| 2188 | #define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11)
|
| 2189 | #define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */
|
| 2190 | #define MUX_PA16O_ADC0_DRV10 _L_(14)
|
| 2191 | #define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10)
|
| 2192 | #define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16)
|
| 2193 | #define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */
|
| 2194 | #define MUX_PA17O_ADC0_DRV11 _L_(14)
|
| 2195 | #define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11)
|
| 2196 | #define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17)
|
| 2197 | #define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */
|
| 2198 | #define MUX_PA18O_ADC0_DRV12 _L_(14)
|
| 2199 | #define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12)
|
| 2200 | #define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18)
|
| 2201 | #define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */
|
| 2202 | #define MUX_PA19O_ADC0_DRV13 _L_(14)
|
| 2203 | #define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13)
|
| 2204 | #define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19)
|
| 2205 | #define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */
|
| 2206 | #define MUX_PA20O_ADC0_DRV14 _L_(14)
|
| 2207 | #define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14)
|
| 2208 | #define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20)
|
| 2209 | #define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */
|
| 2210 | #define MUX_PA21O_ADC0_DRV15 _L_(14)
|
| 2211 | #define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15)
|
| 2212 | #define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21)
|
| 2213 | #define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */
|
| 2214 | #define MUX_PA22O_ADC0_DRV16 _L_(14)
|
| 2215 | #define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16)
|
| 2216 | #define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22)
|
| 2217 | #define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */
|
| 2218 | #define MUX_PA23O_ADC0_DRV17 _L_(14)
|
| 2219 | #define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17)
|
| 2220 | #define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23)
|
| 2221 | #define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */
|
| 2222 | #define MUX_PA27O_ADC0_DRV18 _L_(14)
|
| 2223 | #define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18)
|
| 2224 | #define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27)
|
| 2225 | #define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */
|
| 2226 | #define MUX_PA30O_ADC0_DRV19 _L_(14)
|
| 2227 | #define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19)
|
| 2228 | #define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30)
|
| 2229 | #define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */
|
| 2230 | #define MUX_PB02O_ADC0_DRV20 _L_(14)
|
| 2231 | #define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20)
|
| 2232 | #define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2)
|
| 2233 | #define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */
|
| 2234 | #define MUX_PB03O_ADC0_DRV21 _L_(14)
|
| 2235 | #define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21)
|
| 2236 | #define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3)
|
| 2237 | #define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */
|
| 2238 | #define MUX_PB04O_ADC0_DRV22 _L_(14)
|
| 2239 | #define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22)
|
| 2240 | #define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4)
|
| 2241 | #define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */
|
| 2242 | #define MUX_PB05O_ADC0_DRV23 _L_(14)
|
| 2243 | #define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23)
|
| 2244 | #define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5)
|
| 2245 | #define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */
|
| 2246 | #define MUX_PB06O_ADC0_DRV24 _L_(14)
|
| 2247 | #define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24)
|
| 2248 | #define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6)
|
| 2249 | #define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */
|
| 2250 | #define MUX_PB07O_ADC0_DRV25 _L_(14)
|
| 2251 | #define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25)
|
| 2252 | #define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7)
|
| 2253 | #define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */
|
| 2254 | #define MUX_PB12O_ADC0_DRV26 _L_(14)
|
| 2255 | #define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26)
|
| 2256 | #define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12)
|
| 2257 | #define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */
|
| 2258 | #define MUX_PB13O_ADC0_DRV27 _L_(14)
|
| 2259 | #define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27)
|
| 2260 | #define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13)
|
| 2261 | #define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */
|
| 2262 | #define MUX_PB14O_ADC0_DRV28 _L_(14)
|
| 2263 | #define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28)
|
| 2264 | #define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14)
|
| 2265 | #define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */
|
| 2266 | #define MUX_PB15O_ADC0_DRV29 _L_(14)
|
| 2267 | #define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29)
|
| 2268 | #define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15)
|
| 2269 | #define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */
|
| 2270 | #define MUX_PB00O_ADC0_DRV30 _L_(14)
|
| 2271 | #define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30)
|
| 2272 | #define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0)
|
| 2273 | #define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */
|
| 2274 | #define MUX_PB01O_ADC0_DRV31 _L_(14)
|
| 2275 | #define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31)
|
| 2276 | #define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1)
|
| 2277 | #define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */
|
| 2278 | #define MUX_PA03B_ADC0_PTCXY0 _L_(1)
|
| 2279 | #define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0)
|
| 2280 | #define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3)
|
| 2281 | #define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */
|
| 2282 | #define MUX_PB08B_ADC0_PTCXY1 _L_(1)
|
| 2283 | #define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1)
|
| 2284 | #define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8)
|
| 2285 | #define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */
|
| 2286 | #define MUX_PB09B_ADC0_PTCXY2 _L_(1)
|
| 2287 | #define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2)
|
| 2288 | #define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9)
|
| 2289 | #define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */
|
| 2290 | #define MUX_PA04B_ADC0_PTCXY3 _L_(1)
|
| 2291 | #define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3)
|
| 2292 | #define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4)
|
| 2293 | #define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */
|
| 2294 | #define MUX_PA06B_ADC0_PTCXY4 _L_(1)
|
| 2295 | #define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4)
|
| 2296 | #define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6)
|
| 2297 | #define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */
|
| 2298 | #define MUX_PA07B_ADC0_PTCXY5 _L_(1)
|
| 2299 | #define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5)
|
| 2300 | #define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7)
|
| 2301 | #define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */
|
| 2302 | #define MUX_PA08B_ADC0_PTCXY6 _L_(1)
|
| 2303 | #define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6)
|
| 2304 | #define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8)
|
| 2305 | #define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */
|
| 2306 | #define MUX_PA09B_ADC0_PTCXY7 _L_(1)
|
| 2307 | #define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7)
|
| 2308 | #define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9)
|
| 2309 | #define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */
|
| 2310 | #define MUX_PA10B_ADC0_PTCXY8 _L_(1)
|
| 2311 | #define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8)
|
| 2312 | #define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10)
|
| 2313 | #define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */
|
| 2314 | #define MUX_PA11B_ADC0_PTCXY9 _L_(1)
|
| 2315 | #define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9)
|
| 2316 | #define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11)
|
| 2317 | #define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */
|
| 2318 | #define MUX_PA16B_ADC0_PTCXY10 _L_(1)
|
| 2319 | #define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10)
|
| 2320 | #define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16)
|
| 2321 | #define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */
|
| 2322 | #define MUX_PA17B_ADC0_PTCXY11 _L_(1)
|
| 2323 | #define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11)
|
| 2324 | #define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17)
|
| 2325 | #define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */
|
| 2326 | #define MUX_PA18B_ADC0_PTCXY12 _L_(1)
|
| 2327 | #define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12)
|
| 2328 | #define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18)
|
| 2329 | #define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */
|
| 2330 | #define MUX_PA19B_ADC0_PTCXY13 _L_(1)
|
| 2331 | #define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13)
|
| 2332 | #define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19)
|
| 2333 | #define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */
|
| 2334 | #define MUX_PA20B_ADC0_PTCXY14 _L_(1)
|
| 2335 | #define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14)
|
| 2336 | #define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20)
|
| 2337 | #define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */
|
| 2338 | #define MUX_PA21B_ADC0_PTCXY15 _L_(1)
|
| 2339 | #define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15)
|
| 2340 | #define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21)
|
| 2341 | #define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */
|
| 2342 | #define MUX_PA22B_ADC0_PTCXY16 _L_(1)
|
| 2343 | #define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16)
|
| 2344 | #define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22)
|
| 2345 | #define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */
|
| 2346 | #define MUX_PA23B_ADC0_PTCXY17 _L_(1)
|
| 2347 | #define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17)
|
| 2348 | #define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23)
|
| 2349 | #define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */
|
| 2350 | #define MUX_PA27B_ADC0_PTCXY18 _L_(1)
|
| 2351 | #define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18)
|
| 2352 | #define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27)
|
| 2353 | #define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */
|
| 2354 | #define MUX_PA30B_ADC0_PTCXY19 _L_(1)
|
| 2355 | #define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19)
|
| 2356 | #define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30)
|
| 2357 | #define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */
|
| 2358 | #define MUX_PB02B_ADC0_PTCXY20 _L_(1)
|
| 2359 | #define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20)
|
| 2360 | #define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2)
|
| 2361 | #define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */
|
| 2362 | #define MUX_PB03B_ADC0_PTCXY21 _L_(1)
|
| 2363 | #define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21)
|
| 2364 | #define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3)
|
| 2365 | #define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */
|
| 2366 | #define MUX_PB04B_ADC0_PTCXY22 _L_(1)
|
| 2367 | #define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22)
|
| 2368 | #define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4)
|
| 2369 | #define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */
|
| 2370 | #define MUX_PB05B_ADC0_PTCXY23 _L_(1)
|
| 2371 | #define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23)
|
| 2372 | #define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5)
|
| 2373 | #define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */
|
| 2374 | #define MUX_PB06B_ADC0_PTCXY24 _L_(1)
|
| 2375 | #define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24)
|
| 2376 | #define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6)
|
| 2377 | #define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */
|
| 2378 | #define MUX_PB07B_ADC0_PTCXY25 _L_(1)
|
| 2379 | #define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25)
|
| 2380 | #define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7)
|
| 2381 | #define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */
|
| 2382 | #define MUX_PB12B_ADC0_PTCXY26 _L_(1)
|
| 2383 | #define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26)
|
| 2384 | #define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12)
|
| 2385 | #define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */
|
| 2386 | #define MUX_PB13B_ADC0_PTCXY27 _L_(1)
|
| 2387 | #define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27)
|
| 2388 | #define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13)
|
| 2389 | #define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */
|
| 2390 | #define MUX_PB14B_ADC0_PTCXY28 _L_(1)
|
| 2391 | #define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28)
|
| 2392 | #define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14)
|
| 2393 | #define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */
|
| 2394 | #define MUX_PB15B_ADC0_PTCXY29 _L_(1)
|
| 2395 | #define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29)
|
| 2396 | #define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15)
|
| 2397 | #define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */
|
| 2398 | #define MUX_PB00B_ADC0_PTCXY30 _L_(1)
|
| 2399 | #define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30)
|
| 2400 | #define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0)
|
| 2401 | #define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */
|
| 2402 | #define MUX_PB01B_ADC0_PTCXY31 _L_(1)
|
| 2403 | #define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31)
|
| 2404 | #define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1)
|
| 2405 | /* ========== PORT definition for ADC1 peripheral ========== */
|
| 2406 | #define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */
|
| 2407 | #define MUX_PB08B_ADC1_AIN0 _L_(1)
|
| 2408 | #define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0)
|
| 2409 | #define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8)
|
| 2410 | #define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */
|
| 2411 | #define MUX_PB09B_ADC1_AIN1 _L_(1)
|
| 2412 | #define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1)
|
| 2413 | #define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9)
|
| 2414 | #define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */
|
| 2415 | #define MUX_PA08B_ADC1_AIN2 _L_(1)
|
| 2416 | #define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2)
|
| 2417 | #define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8)
|
| 2418 | #define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */
|
| 2419 | #define MUX_PA09B_ADC1_AIN3 _L_(1)
|
| 2420 | #define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3)
|
| 2421 | #define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9)
|
| 2422 | #define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */
|
| 2423 | #define MUX_PC02B_ADC1_AIN4 _L_(1)
|
| 2424 | #define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4)
|
| 2425 | #define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2)
|
| 2426 | #define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */
|
| 2427 | #define MUX_PC03B_ADC1_AIN5 _L_(1)
|
| 2428 | #define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5)
|
| 2429 | #define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3)
|
| 2430 | #define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */
|
| 2431 | #define MUX_PB04B_ADC1_AIN6 _L_(1)
|
| 2432 | #define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6)
|
| 2433 | #define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4)
|
| 2434 | #define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */
|
| 2435 | #define MUX_PB05B_ADC1_AIN7 _L_(1)
|
| 2436 | #define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7)
|
| 2437 | #define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5)
|
| 2438 | #define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */
|
| 2439 | #define MUX_PB06B_ADC1_AIN8 _L_(1)
|
| 2440 | #define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8)
|
| 2441 | #define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6)
|
| 2442 | #define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */
|
| 2443 | #define MUX_PB07B_ADC1_AIN9 _L_(1)
|
| 2444 | #define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9)
|
| 2445 | #define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7)
|
| 2446 | #define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */
|
| 2447 | #define MUX_PC00B_ADC1_AIN10 _L_(1)
|
| 2448 | #define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10)
|
| 2449 | #define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0)
|
| 2450 | #define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */
|
| 2451 | #define MUX_PC01B_ADC1_AIN11 _L_(1)
|
| 2452 | #define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11)
|
| 2453 | #define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1)
|
| 2454 | /* ========== PORT definition for DAC peripheral ========== */
|
| 2455 | #define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */
|
| 2456 | #define MUX_PA02B_DAC_VOUT0 _L_(1)
|
| 2457 | #define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0)
|
| 2458 | #define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2)
|
| 2459 | #define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */
|
| 2460 | #define MUX_PA05B_DAC_VOUT1 _L_(1)
|
| 2461 | #define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1)
|
| 2462 | #define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5)
|
| 2463 | /* ========== PORT definition for I2S peripheral ========== */
|
| 2464 | #define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */
|
| 2465 | #define MUX_PA09J_I2S_FS0 _L_(9)
|
| 2466 | #define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0)
|
| 2467 | #define PORT_PA09J_I2S_FS0 (_UL_(1) << 9)
|
| 2468 | #define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */
|
| 2469 | #define MUX_PA20J_I2S_FS0 _L_(9)
|
| 2470 | #define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0)
|
| 2471 | #define PORT_PA20J_I2S_FS0 (_UL_(1) << 20)
|
| 2472 | #define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */
|
| 2473 | #define MUX_PA23J_I2S_FS1 _L_(9)
|
| 2474 | #define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1)
|
| 2475 | #define PORT_PA23J_I2S_FS1 (_UL_(1) << 23)
|
| 2476 | #define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */
|
| 2477 | #define MUX_PB11J_I2S_FS1 _L_(9)
|
| 2478 | #define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1)
|
| 2479 | #define PORT_PB11J_I2S_FS1 (_UL_(1) << 11)
|
| 2480 | #define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */
|
| 2481 | #define MUX_PA08J_I2S_MCK0 _L_(9)
|
| 2482 | #define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0)
|
| 2483 | #define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8)
|
| 2484 | #define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */
|
| 2485 | #define MUX_PB17J_I2S_MCK0 _L_(9)
|
| 2486 | #define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0)
|
| 2487 | #define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17)
|
| 2488 | #define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */
|
| 2489 | #define MUX_PB13J_I2S_MCK1 _L_(9)
|
| 2490 | #define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1)
|
| 2491 | #define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13)
|
| 2492 | #define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */
|
| 2493 | #define MUX_PA10J_I2S_SCK0 _L_(9)
|
| 2494 | #define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0)
|
| 2495 | #define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10)
|
| 2496 | #define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */
|
| 2497 | #define MUX_PB16J_I2S_SCK0 _L_(9)
|
| 2498 | #define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0)
|
| 2499 | #define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16)
|
| 2500 | #define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */
|
| 2501 | #define MUX_PB12J_I2S_SCK1 _L_(9)
|
| 2502 | #define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1)
|
| 2503 | #define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12)
|
| 2504 | #define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */
|
| 2505 | #define MUX_PA22J_I2S_SDI _L_(9)
|
| 2506 | #define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI)
|
| 2507 | #define PORT_PA22J_I2S_SDI (_UL_(1) << 22)
|
| 2508 | #define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */
|
| 2509 | #define MUX_PB10J_I2S_SDI _L_(9)
|
| 2510 | #define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI)
|
| 2511 | #define PORT_PB10J_I2S_SDI (_UL_(1) << 10)
|
| 2512 | #define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */
|
| 2513 | #define MUX_PA11J_I2S_SDO _L_(9)
|
| 2514 | #define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO)
|
| 2515 | #define PORT_PA11J_I2S_SDO (_UL_(1) << 11)
|
| 2516 | #define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */
|
| 2517 | #define MUX_PA21J_I2S_SDO _L_(9)
|
| 2518 | #define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO)
|
| 2519 | #define PORT_PA21J_I2S_SDO (_UL_(1) << 21)
|
| 2520 | /* ========== PORT definition for PCC peripheral ========== */
|
| 2521 | #define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */
|
| 2522 | #define MUX_PA14K_PCC_CLK _L_(10)
|
| 2523 | #define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK)
|
| 2524 | #define PORT_PA14K_PCC_CLK (_UL_(1) << 14)
|
| 2525 | #define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */
|
| 2526 | #define MUX_PA16K_PCC_DATA0 _L_(10)
|
| 2527 | #define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0)
|
| 2528 | #define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16)
|
| 2529 | #define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */
|
| 2530 | #define MUX_PA17K_PCC_DATA1 _L_(10)
|
| 2531 | #define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1)
|
| 2532 | #define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17)
|
| 2533 | #define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */
|
| 2534 | #define MUX_PA18K_PCC_DATA2 _L_(10)
|
| 2535 | #define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2)
|
| 2536 | #define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18)
|
| 2537 | #define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */
|
| 2538 | #define MUX_PA19K_PCC_DATA3 _L_(10)
|
| 2539 | #define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3)
|
| 2540 | #define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19)
|
| 2541 | #define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */
|
| 2542 | #define MUX_PA20K_PCC_DATA4 _L_(10)
|
| 2543 | #define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4)
|
| 2544 | #define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20)
|
| 2545 | #define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */
|
| 2546 | #define MUX_PA21K_PCC_DATA5 _L_(10)
|
| 2547 | #define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5)
|
| 2548 | #define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21)
|
| 2549 | #define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */
|
| 2550 | #define MUX_PA22K_PCC_DATA6 _L_(10)
|
| 2551 | #define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6)
|
| 2552 | #define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22)
|
| 2553 | #define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */
|
| 2554 | #define MUX_PA23K_PCC_DATA7 _L_(10)
|
| 2555 | #define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7)
|
| 2556 | #define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23)
|
| 2557 | #define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */
|
| 2558 | #define MUX_PB14K_PCC_DATA8 _L_(10)
|
| 2559 | #define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8)
|
| 2560 | #define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14)
|
| 2561 | #define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */
|
| 2562 | #define MUX_PB15K_PCC_DATA9 _L_(10)
|
| 2563 | #define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9)
|
| 2564 | #define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15)
|
| 2565 | #define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */
|
| 2566 | #define MUX_PC12K_PCC_DATA10 _L_(10)
|
| 2567 | #define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10)
|
| 2568 | #define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12)
|
| 2569 | #define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */
|
| 2570 | #define MUX_PC13K_PCC_DATA11 _L_(10)
|
| 2571 | #define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11)
|
| 2572 | #define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13)
|
| 2573 | #define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */
|
| 2574 | #define MUX_PC14K_PCC_DATA12 _L_(10)
|
| 2575 | #define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12)
|
| 2576 | #define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14)
|
| 2577 | #define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */
|
| 2578 | #define MUX_PC15K_PCC_DATA13 _L_(10)
|
| 2579 | #define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13)
|
| 2580 | #define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15)
|
| 2581 | #define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */
|
| 2582 | #define MUX_PA12K_PCC_DEN1 _L_(10)
|
| 2583 | #define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1)
|
| 2584 | #define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12)
|
| 2585 | #define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */
|
| 2586 | #define MUX_PA13K_PCC_DEN2 _L_(10)
|
| 2587 | #define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2)
|
| 2588 | #define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13)
|
| 2589 | /* ========== PORT definition for SDHC0 peripheral ========== */
|
| 2590 | #define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */
|
| 2591 | #define MUX_PA06I_SDHC0_SDCD _L_(8)
|
| 2592 | #define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD)
|
| 2593 | #define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6)
|
| 2594 | #define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */
|
| 2595 | #define MUX_PA12I_SDHC0_SDCD _L_(8)
|
| 2596 | #define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD)
|
| 2597 | #define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12)
|
| 2598 | #define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */
|
| 2599 | #define MUX_PB12I_SDHC0_SDCD _L_(8)
|
| 2600 | #define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD)
|
| 2601 | #define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12)
|
| 2602 | #define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */
|
| 2603 | #define MUX_PC06I_SDHC0_SDCD _L_(8)
|
| 2604 | #define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD)
|
| 2605 | #define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6)
|
| 2606 | #define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */
|
| 2607 | #define MUX_PB11I_SDHC0_SDCK _L_(8)
|
| 2608 | #define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK)
|
| 2609 | #define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11)
|
| 2610 | #define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */
|
| 2611 | #define MUX_PA08I_SDHC0_SDCMD _L_(8)
|
| 2612 | #define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD)
|
| 2613 | #define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8)
|
| 2614 | #define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */
|
| 2615 | #define MUX_PA09I_SDHC0_SDDAT0 _L_(8)
|
| 2616 | #define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0)
|
| 2617 | #define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9)
|
| 2618 | #define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */
|
| 2619 | #define MUX_PA10I_SDHC0_SDDAT1 _L_(8)
|
| 2620 | #define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1)
|
| 2621 | #define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10)
|
| 2622 | #define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */
|
| 2623 | #define MUX_PA11I_SDHC0_SDDAT2 _L_(8)
|
| 2624 | #define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2)
|
| 2625 | #define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11)
|
| 2626 | #define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */
|
| 2627 | #define MUX_PB10I_SDHC0_SDDAT3 _L_(8)
|
| 2628 | #define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3)
|
| 2629 | #define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10)
|
| 2630 | #define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */
|
| 2631 | #define MUX_PA07I_SDHC0_SDWP _L_(8)
|
| 2632 | #define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP)
|
| 2633 | #define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7)
|
| 2634 | #define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */
|
| 2635 | #define MUX_PA13I_SDHC0_SDWP _L_(8)
|
| 2636 | #define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP)
|
| 2637 | #define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13)
|
| 2638 | #define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */
|
| 2639 | #define MUX_PB13I_SDHC0_SDWP _L_(8)
|
| 2640 | #define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP)
|
| 2641 | #define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13)
|
| 2642 | #define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */
|
| 2643 | #define MUX_PC07I_SDHC0_SDWP _L_(8)
|
| 2644 | #define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP)
|
| 2645 | #define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7)
|
| 2646 | /* ========== PORT definition for SDHC1 peripheral ========== */
|
| 2647 | #define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */
|
| 2648 | #define MUX_PB16I_SDHC1_SDCD _L_(8)
|
| 2649 | #define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD)
|
| 2650 | #define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16)
|
| 2651 | #define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */
|
| 2652 | #define MUX_PC20I_SDHC1_SDCD _L_(8)
|
| 2653 | #define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD)
|
| 2654 | #define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20)
|
| 2655 | #define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */
|
| 2656 | #define MUX_PA21I_SDHC1_SDCK _L_(8)
|
| 2657 | #define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK)
|
| 2658 | #define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21)
|
| 2659 | #define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */
|
| 2660 | #define MUX_PA20I_SDHC1_SDCMD _L_(8)
|
| 2661 | #define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD)
|
| 2662 | #define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20)
|
| 2663 | #define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */
|
| 2664 | #define MUX_PB18I_SDHC1_SDDAT0 _L_(8)
|
| 2665 | #define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0)
|
| 2666 | #define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18)
|
| 2667 | #define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */
|
| 2668 | #define MUX_PB19I_SDHC1_SDDAT1 _L_(8)
|
| 2669 | #define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1)
|
| 2670 | #define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19)
|
| 2671 | #define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */
|
| 2672 | #define MUX_PB20I_SDHC1_SDDAT2 _L_(8)
|
| 2673 | #define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2)
|
| 2674 | #define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20)
|
| 2675 | #define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */
|
| 2676 | #define MUX_PB21I_SDHC1_SDDAT3 _L_(8)
|
| 2677 | #define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3)
|
| 2678 | #define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21)
|
| 2679 | #define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */
|
| 2680 | #define MUX_PB17I_SDHC1_SDWP _L_(8)
|
| 2681 | #define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP)
|
| 2682 | #define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17)
|
| 2683 | #define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */
|
| 2684 | #define MUX_PC21I_SDHC1_SDWP _L_(8)
|
| 2685 | #define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP)
|
| 2686 | #define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21)
|
| 2687 |
|
| 2688 | #endif /* _SAME54N19A_PIO_ */
|