| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Instance description for TCC3
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_TCC3_INSTANCE_
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| 31 | #define _SAME54_TCC3_INSTANCE_
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| 32 |
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| 33 | /* ========== Register definition for TCC3 peripheral ========== */
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| 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 35 | #define REG_TCC3_CTRLA (0x42001000) /**< \brief (TCC3) Control A */
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| 36 | #define REG_TCC3_CTRLBCLR (0x42001004) /**< \brief (TCC3) Control B Clear */
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| 37 | #define REG_TCC3_CTRLBSET (0x42001005) /**< \brief (TCC3) Control B Set */
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| 38 | #define REG_TCC3_SYNCBUSY (0x42001008) /**< \brief (TCC3) Synchronization Busy */
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| 39 | #define REG_TCC3_FCTRLA (0x4200100C) /**< \brief (TCC3) Recoverable Fault A Configuration */
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| 40 | #define REG_TCC3_FCTRLB (0x42001010) /**< \brief (TCC3) Recoverable Fault B Configuration */
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| 41 | #define REG_TCC3_DRVCTRL (0x42001018) /**< \brief (TCC3) Driver Control */
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| 42 | #define REG_TCC3_DBGCTRL (0x4200101E) /**< \brief (TCC3) Debug Control */
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| 43 | #define REG_TCC3_EVCTRL (0x42001020) /**< \brief (TCC3) Event Control */
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| 44 | #define REG_TCC3_INTENCLR (0x42001024) /**< \brief (TCC3) Interrupt Enable Clear */
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| 45 | #define REG_TCC3_INTENSET (0x42001028) /**< \brief (TCC3) Interrupt Enable Set */
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| 46 | #define REG_TCC3_INTFLAG (0x4200102C) /**< \brief (TCC3) Interrupt Flag Status and Clear */
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| 47 | #define REG_TCC3_STATUS (0x42001030) /**< \brief (TCC3) Status */
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| 48 | #define REG_TCC3_COUNT (0x42001034) /**< \brief (TCC3) Count */
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| 49 | #define REG_TCC3_WAVE (0x4200103C) /**< \brief (TCC3) Waveform Control */
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| 50 | #define REG_TCC3_PER (0x42001040) /**< \brief (TCC3) Period */
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| 51 | #define REG_TCC3_CC0 (0x42001044) /**< \brief (TCC3) Compare and Capture 0 */
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| 52 | #define REG_TCC3_CC1 (0x42001048) /**< \brief (TCC3) Compare and Capture 1 */
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| 53 | #define REG_TCC3_PERBUF (0x4200106C) /**< \brief (TCC3) Period Buffer */
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| 54 | #define REG_TCC3_CCBUF0 (0x42001070) /**< \brief (TCC3) Compare and Capture Buffer 0 */
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| 55 | #define REG_TCC3_CCBUF1 (0x42001074) /**< \brief (TCC3) Compare and Capture Buffer 1 */
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| 56 | #else
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| 57 | #define REG_TCC3_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (TCC3) Control A */
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| 58 | #define REG_TCC3_CTRLBCLR (*(RwReg8 *)0x42001004UL) /**< \brief (TCC3) Control B Clear */
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| 59 | #define REG_TCC3_CTRLBSET (*(RwReg8 *)0x42001005UL) /**< \brief (TCC3) Control B Set */
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| 60 | #define REG_TCC3_SYNCBUSY (*(RoReg *)0x42001008UL) /**< \brief (TCC3) Synchronization Busy */
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| 61 | #define REG_TCC3_FCTRLA (*(RwReg *)0x4200100CUL) /**< \brief (TCC3) Recoverable Fault A Configuration */
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| 62 | #define REG_TCC3_FCTRLB (*(RwReg *)0x42001010UL) /**< \brief (TCC3) Recoverable Fault B Configuration */
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| 63 | #define REG_TCC3_DRVCTRL (*(RwReg *)0x42001018UL) /**< \brief (TCC3) Driver Control */
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| 64 | #define REG_TCC3_DBGCTRL (*(RwReg8 *)0x4200101EUL) /**< \brief (TCC3) Debug Control */
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| 65 | #define REG_TCC3_EVCTRL (*(RwReg *)0x42001020UL) /**< \brief (TCC3) Event Control */
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| 66 | #define REG_TCC3_INTENCLR (*(RwReg *)0x42001024UL) /**< \brief (TCC3) Interrupt Enable Clear */
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| 67 | #define REG_TCC3_INTENSET (*(RwReg *)0x42001028UL) /**< \brief (TCC3) Interrupt Enable Set */
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| 68 | #define REG_TCC3_INTFLAG (*(RwReg *)0x4200102CUL) /**< \brief (TCC3) Interrupt Flag Status and Clear */
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| 69 | #define REG_TCC3_STATUS (*(RwReg *)0x42001030UL) /**< \brief (TCC3) Status */
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| 70 | #define REG_TCC3_COUNT (*(RwReg *)0x42001034UL) /**< \brief (TCC3) Count */
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| 71 | #define REG_TCC3_WAVE (*(RwReg *)0x4200103CUL) /**< \brief (TCC3) Waveform Control */
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| 72 | #define REG_TCC3_PER (*(RwReg *)0x42001040UL) /**< \brief (TCC3) Period */
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| 73 | #define REG_TCC3_CC0 (*(RwReg *)0x42001044UL) /**< \brief (TCC3) Compare and Capture 0 */
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| 74 | #define REG_TCC3_CC1 (*(RwReg *)0x42001048UL) /**< \brief (TCC3) Compare and Capture 1 */
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| 75 | #define REG_TCC3_PERBUF (*(RwReg *)0x4200106CUL) /**< \brief (TCC3) Period Buffer */
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| 76 | #define REG_TCC3_CCBUF0 (*(RwReg *)0x42001070UL) /**< \brief (TCC3) Compare and Capture Buffer 0 */
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| 77 | #define REG_TCC3_CCBUF1 (*(RwReg *)0x42001074UL) /**< \brief (TCC3) Compare and Capture Buffer 1 */
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| 78 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 79 |
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| 80 | /* ========== Instance parameters for TCC3 peripheral ========== */
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| 81 | #define TCC3_CC_NUM 2 // Number of Compare/Capture units
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| 82 | #define TCC3_DITHERING 0 // Dithering feature implemented
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| 83 | #define TCC3_DMAC_ID_MC_0 39
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| 84 | #define TCC3_DMAC_ID_MC_1 40
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| 85 | #define TCC3_DMAC_ID_MC_LSB 39
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| 86 | #define TCC3_DMAC_ID_MC_MSB 40
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| 87 | #define TCC3_DMAC_ID_MC_SIZE 2
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| 88 | #define TCC3_DMAC_ID_OVF 38 // DMA overflow/underflow/retrigger trigger
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| 89 | #define TCC3_DTI 0 // Dead-Time-Insertion feature implemented
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| 90 | #define TCC3_EXT 0 // Coding of implemented extended features
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| 91 | #define TCC3_GCLK_ID 29 // Index of Generic Clock
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| 92 | #define TCC3_MASTER_SLAVE_MODE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
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| 93 | #define TCC3_OTMX 0 // Output Matrix feature implemented
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| 94 | #define TCC3_OW_NUM 2 // Number of Output Waveforms
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| 95 | #define TCC3_PG 0 // Pattern Generation feature implemented
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| 96 | #define TCC3_SIZE 16
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| 97 | #define TCC3_SWAP 0 // DTI outputs swap feature implemented
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| 98 |
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| 99 | #endif /* _SAME54_TCC3_INSTANCE_ */
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