| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Instance description for CMCC
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_CMCC_INSTANCE_
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| 31 | #define _SAME54_CMCC_INSTANCE_
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| 32 |
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| 33 | /* ========== Register definition for CMCC peripheral ========== */
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| 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 35 | #define REG_CMCC_TYPE (0x41006000) /**< \brief (CMCC) Cache Type Register */
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| 36 | #define REG_CMCC_CFG (0x41006004) /**< \brief (CMCC) Cache Configuration Register */
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| 37 | #define REG_CMCC_CTRL (0x41006008) /**< \brief (CMCC) Cache Control Register */
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| 38 | #define REG_CMCC_SR (0x4100600C) /**< \brief (CMCC) Cache Status Register */
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| 39 | #define REG_CMCC_LCKWAY (0x41006010) /**< \brief (CMCC) Cache Lock per Way Register */
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| 40 | #define REG_CMCC_MAINT0 (0x41006020) /**< \brief (CMCC) Cache Maintenance Register 0 */
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| 41 | #define REG_CMCC_MAINT1 (0x41006024) /**< \brief (CMCC) Cache Maintenance Register 1 */
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| 42 | #define REG_CMCC_MCFG (0x41006028) /**< \brief (CMCC) Cache Monitor Configuration Register */
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| 43 | #define REG_CMCC_MEN (0x4100602C) /**< \brief (CMCC) Cache Monitor Enable Register */
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| 44 | #define REG_CMCC_MCTRL (0x41006030) /**< \brief (CMCC) Cache Monitor Control Register */
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| 45 | #define REG_CMCC_MSR (0x41006034) /**< \brief (CMCC) Cache Monitor Status Register */
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| 46 | #else
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| 47 | #define REG_CMCC_TYPE (*(RoReg *)0x41006000UL) /**< \brief (CMCC) Cache Type Register */
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| 48 | #define REG_CMCC_CFG (*(RwReg *)0x41006004UL) /**< \brief (CMCC) Cache Configuration Register */
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| 49 | #define REG_CMCC_CTRL (*(WoReg *)0x41006008UL) /**< \brief (CMCC) Cache Control Register */
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| 50 | #define REG_CMCC_SR (*(RoReg *)0x4100600CUL) /**< \brief (CMCC) Cache Status Register */
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| 51 | #define REG_CMCC_LCKWAY (*(RwReg *)0x41006010UL) /**< \brief (CMCC) Cache Lock per Way Register */
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| 52 | #define REG_CMCC_MAINT0 (*(WoReg *)0x41006020UL) /**< \brief (CMCC) Cache Maintenance Register 0 */
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| 53 | #define REG_CMCC_MAINT1 (*(WoReg *)0x41006024UL) /**< \brief (CMCC) Cache Maintenance Register 1 */
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| 54 | #define REG_CMCC_MCFG (*(RwReg *)0x41006028UL) /**< \brief (CMCC) Cache Monitor Configuration Register */
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| 55 | #define REG_CMCC_MEN (*(RwReg *)0x4100602CUL) /**< \brief (CMCC) Cache Monitor Enable Register */
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| 56 | #define REG_CMCC_MCTRL (*(WoReg *)0x41006030UL) /**< \brief (CMCC) Cache Monitor Control Register */
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| 57 | #define REG_CMCC_MSR (*(RoReg *)0x41006034UL) /**< \brief (CMCC) Cache Monitor Status Register */
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| 58 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 59 |
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| 60 |
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| 61 | #endif /* _SAME54_CMCC_INSTANCE_ */
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