| Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Component description for I2S
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_I2S_COMPONENT_
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| 31 | #define _SAME54_I2S_COMPONENT_
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| 32 |
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| 33 | /* ========================================================================== */
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| 34 | /** SOFTWARE API DEFINITION FOR I2S */
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| 35 | /* ========================================================================== */
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| 36 | /** \addtogroup SAME54_I2S Inter-IC Sound Interface */
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| 37 | /*@{*/
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| 38 |
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| 39 | #define I2S_U2224
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| 40 | #define REV_I2S 0x200
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| 41 |
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| 42 | /* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W 8) Control A -------- */
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| 43 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 44 | typedef union {
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| 45 | struct {
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| 46 | uint8_t SWRST:1; /*!< bit: 0 Software Reset */
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| 47 | uint8_t ENABLE:1; /*!< bit: 1 Enable */
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| 48 | uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */
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| 49 | uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */
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| 50 | uint8_t TXEN:1; /*!< bit: 4 Tx Serializer Enable */
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| 51 | uint8_t RXEN:1; /*!< bit: 5 Rx Serializer Enable */
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| 52 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
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| 53 | } bit; /*!< Structure used for bit access */
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| 54 | struct {
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| 55 | uint8_t :2; /*!< bit: 0.. 1 Reserved */
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| 56 | uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */
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| 57 | uint8_t :4; /*!< bit: 4.. 7 Reserved */
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| 58 | } vec; /*!< Structure used for vec access */
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| 59 | uint8_t reg; /*!< Type used for register access */
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| 60 | } I2S_CTRLA_Type;
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| 61 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 62 |
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| 63 | #define I2S_CTRLA_OFFSET 0x00 /**< \brief (I2S_CTRLA offset) Control A */
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| 64 | #define I2S_CTRLA_RESETVALUE _U_(0x00) /**< \brief (I2S_CTRLA reset_value) Control A */
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| 65 |
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| 66 | #define I2S_CTRLA_SWRST_Pos 0 /**< \brief (I2S_CTRLA) Software Reset */
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| 67 | #define I2S_CTRLA_SWRST (_U_(0x1) << I2S_CTRLA_SWRST_Pos)
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| 68 | #define I2S_CTRLA_ENABLE_Pos 1 /**< \brief (I2S_CTRLA) Enable */
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| 69 | #define I2S_CTRLA_ENABLE (_U_(0x1) << I2S_CTRLA_ENABLE_Pos)
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| 70 | #define I2S_CTRLA_CKEN0_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit 0 Enable */
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| 71 | #define I2S_CTRLA_CKEN0 (_U_(1) << I2S_CTRLA_CKEN0_Pos)
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| 72 | #define I2S_CTRLA_CKEN1_Pos 3 /**< \brief (I2S_CTRLA) Clock Unit 1 Enable */
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| 73 | #define I2S_CTRLA_CKEN1 (_U_(1) << I2S_CTRLA_CKEN1_Pos)
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| 74 | #define I2S_CTRLA_CKEN_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit x Enable */
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| 75 | #define I2S_CTRLA_CKEN_Msk (_U_(0x3) << I2S_CTRLA_CKEN_Pos)
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| 76 | #define I2S_CTRLA_CKEN(value) (I2S_CTRLA_CKEN_Msk & ((value) << I2S_CTRLA_CKEN_Pos))
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| 77 | #define I2S_CTRLA_TXEN_Pos 4 /**< \brief (I2S_CTRLA) Tx Serializer Enable */
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| 78 | #define I2S_CTRLA_TXEN (_U_(0x1) << I2S_CTRLA_TXEN_Pos)
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| 79 | #define I2S_CTRLA_RXEN_Pos 5 /**< \brief (I2S_CTRLA) Rx Serializer Enable */
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| 80 | #define I2S_CTRLA_RXEN (_U_(0x1) << I2S_CTRLA_RXEN_Pos)
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| 81 | #define I2S_CTRLA_MASK _U_(0x3F) /**< \brief (I2S_CTRLA) MASK Register */
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| 82 |
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| 83 | /* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */
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| 84 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 85 | typedef union {
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| 86 | struct {
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| 87 | uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */
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| 88 | uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */
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| 89 | uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */
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| 90 | uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */
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| 91 | uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */
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| 92 | uint32_t FSINV:1; /*!< bit: 9 Frame Sync Invert */
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| 93 | uint32_t FSOUTINV:1; /*!< bit: 10 Frame Sync Output Invert */
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| 94 | uint32_t SCKSEL:1; /*!< bit: 11 Serial Clock Select */
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| 95 | uint32_t SCKOUTINV:1; /*!< bit: 12 Serial Clock Output Invert */
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| 96 | uint32_t MCKSEL:1; /*!< bit: 13 Master Clock Select */
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| 97 | uint32_t MCKEN:1; /*!< bit: 14 Master Clock Enable */
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| 98 | uint32_t MCKOUTINV:1; /*!< bit: 15 Master Clock Output Invert */
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| 99 | uint32_t MCKDIV:6; /*!< bit: 16..21 Master Clock Division Factor */
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| 100 | uint32_t :2; /*!< bit: 22..23 Reserved */
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| 101 | uint32_t MCKOUTDIV:6; /*!< bit: 24..29 Master Clock Output Division Factor */
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| 102 | uint32_t :2; /*!< bit: 30..31 Reserved */
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| 103 | } bit; /*!< Structure used for bit access */
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| 104 | uint32_t reg; /*!< Type used for register access */
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| 105 | } I2S_CLKCTRL_Type;
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| 106 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 107 |
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| 108 | #define I2S_CLKCTRL_OFFSET 0x04 /**< \brief (I2S_CLKCTRL offset) Clock Unit n Control */
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| 109 | #define I2S_CLKCTRL_RESETVALUE _U_(0x00000000) /**< \brief (I2S_CLKCTRL reset_value) Clock Unit n Control */
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| 110 |
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| 111 | #define I2S_CLKCTRL_SLOTSIZE_Pos 0 /**< \brief (I2S_CLKCTRL) Slot Size */
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| 112 | #define I2S_CLKCTRL_SLOTSIZE_Msk (_U_(0x3) << I2S_CLKCTRL_SLOTSIZE_Pos)
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| 113 | #define I2S_CLKCTRL_SLOTSIZE(value) (I2S_CLKCTRL_SLOTSIZE_Msk & ((value) << I2S_CLKCTRL_SLOTSIZE_Pos))
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| 114 | #define I2S_CLKCTRL_SLOTSIZE_8_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) 8-bit Slot for Clock Unit n */
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| 115 | #define I2S_CLKCTRL_SLOTSIZE_16_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) 16-bit Slot for Clock Unit n */
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| 116 | #define I2S_CLKCTRL_SLOTSIZE_24_Val _U_(0x2) /**< \brief (I2S_CLKCTRL) 24-bit Slot for Clock Unit n */
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| 117 | #define I2S_CLKCTRL_SLOTSIZE_32_Val _U_(0x3) /**< \brief (I2S_CLKCTRL) 32-bit Slot for Clock Unit n */
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| 118 | #define I2S_CLKCTRL_SLOTSIZE_8 (I2S_CLKCTRL_SLOTSIZE_8_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
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| 119 | #define I2S_CLKCTRL_SLOTSIZE_16 (I2S_CLKCTRL_SLOTSIZE_16_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
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| 120 | #define I2S_CLKCTRL_SLOTSIZE_24 (I2S_CLKCTRL_SLOTSIZE_24_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
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| 121 | #define I2S_CLKCTRL_SLOTSIZE_32 (I2S_CLKCTRL_SLOTSIZE_32_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
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| 122 | #define I2S_CLKCTRL_NBSLOTS_Pos 2 /**< \brief (I2S_CLKCTRL) Number of Slots in Frame */
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| 123 | #define I2S_CLKCTRL_NBSLOTS_Msk (_U_(0x7) << I2S_CLKCTRL_NBSLOTS_Pos)
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| 124 | #define I2S_CLKCTRL_NBSLOTS(value) (I2S_CLKCTRL_NBSLOTS_Msk & ((value) << I2S_CLKCTRL_NBSLOTS_Pos))
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| 125 | #define I2S_CLKCTRL_FSWIDTH_Pos 5 /**< \brief (I2S_CLKCTRL) Frame Sync Width */
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| 126 | #define I2S_CLKCTRL_FSWIDTH_Msk (_U_(0x3) << I2S_CLKCTRL_FSWIDTH_Pos)
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| 127 | #define I2S_CLKCTRL_FSWIDTH(value) (I2S_CLKCTRL_FSWIDTH_Msk & ((value) << I2S_CLKCTRL_FSWIDTH_Pos))
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| 128 | #define I2S_CLKCTRL_FSWIDTH_SLOT_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) */
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| 129 | #define I2S_CLKCTRL_FSWIDTH_HALF_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide */
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| 130 | #define I2S_CLKCTRL_FSWIDTH_BIT_Val _U_(0x2) /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide */
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| 131 | #define I2S_CLKCTRL_FSWIDTH_BURST_Val _U_(0x3) /**< \brief (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested */
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| 132 | #define I2S_CLKCTRL_FSWIDTH_SLOT (I2S_CLKCTRL_FSWIDTH_SLOT_Val << I2S_CLKCTRL_FSWIDTH_Pos)
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| 133 | #define I2S_CLKCTRL_FSWIDTH_HALF (I2S_CLKCTRL_FSWIDTH_HALF_Val << I2S_CLKCTRL_FSWIDTH_Pos)
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| 134 | #define I2S_CLKCTRL_FSWIDTH_BIT (I2S_CLKCTRL_FSWIDTH_BIT_Val << I2S_CLKCTRL_FSWIDTH_Pos)
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| 135 | #define I2S_CLKCTRL_FSWIDTH_BURST (I2S_CLKCTRL_FSWIDTH_BURST_Val << I2S_CLKCTRL_FSWIDTH_Pos)
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| 136 | #define I2S_CLKCTRL_BITDELAY_Pos 7 /**< \brief (I2S_CLKCTRL) Data Delay from Frame Sync */
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| 137 | #define I2S_CLKCTRL_BITDELAY (_U_(0x1) << I2S_CLKCTRL_BITDELAY_Pos)
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| 138 | #define I2S_CLKCTRL_BITDELAY_LJ_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) Left Justified (0 Bit Delay) */
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| 139 | #define I2S_CLKCTRL_BITDELAY_I2S_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) I2S (1 Bit Delay) */
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| 140 | #define I2S_CLKCTRL_BITDELAY_LJ (I2S_CLKCTRL_BITDELAY_LJ_Val << I2S_CLKCTRL_BITDELAY_Pos)
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| 141 | #define I2S_CLKCTRL_BITDELAY_I2S (I2S_CLKCTRL_BITDELAY_I2S_Val << I2S_CLKCTRL_BITDELAY_Pos)
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| 142 | #define I2S_CLKCTRL_FSSEL_Pos 8 /**< \brief (I2S_CLKCTRL) Frame Sync Select */
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| 143 | #define I2S_CLKCTRL_FSSEL (_U_(0x1) << I2S_CLKCTRL_FSSEL_Pos)
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| 144 | #define I2S_CLKCTRL_FSSEL_SCKDIV_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source */
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| 145 | #define I2S_CLKCTRL_FSSEL_FSPIN_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source */
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| 146 | #define I2S_CLKCTRL_FSSEL_SCKDIV (I2S_CLKCTRL_FSSEL_SCKDIV_Val << I2S_CLKCTRL_FSSEL_Pos)
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| 147 | #define I2S_CLKCTRL_FSSEL_FSPIN (I2S_CLKCTRL_FSSEL_FSPIN_Val << I2S_CLKCTRL_FSSEL_Pos)
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| 148 | #define I2S_CLKCTRL_FSINV_Pos 9 /**< \brief (I2S_CLKCTRL) Frame Sync Invert */
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| 149 | #define I2S_CLKCTRL_FSINV (_U_(0x1) << I2S_CLKCTRL_FSINV_Pos)
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| 150 | #define I2S_CLKCTRL_FSOUTINV_Pos 10 /**< \brief (I2S_CLKCTRL) Frame Sync Output Invert */
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| 151 | #define I2S_CLKCTRL_FSOUTINV (_U_(0x1) << I2S_CLKCTRL_FSOUTINV_Pos)
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| 152 | #define I2S_CLKCTRL_SCKSEL_Pos 11 /**< \brief (I2S_CLKCTRL) Serial Clock Select */
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| 153 | #define I2S_CLKCTRL_SCKSEL (_U_(0x1) << I2S_CLKCTRL_SCKSEL_Pos)
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| 154 | #define I2S_CLKCTRL_SCKSEL_MCKDIV_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source */
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| 155 | #define I2S_CLKCTRL_SCKSEL_SCKPIN_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source */
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| 156 | #define I2S_CLKCTRL_SCKSEL_MCKDIV (I2S_CLKCTRL_SCKSEL_MCKDIV_Val << I2S_CLKCTRL_SCKSEL_Pos)
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| 157 | #define I2S_CLKCTRL_SCKSEL_SCKPIN (I2S_CLKCTRL_SCKSEL_SCKPIN_Val << I2S_CLKCTRL_SCKSEL_Pos)
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| 158 | #define I2S_CLKCTRL_SCKOUTINV_Pos 12 /**< \brief (I2S_CLKCTRL) Serial Clock Output Invert */
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| 159 | #define I2S_CLKCTRL_SCKOUTINV (_U_(0x1) << I2S_CLKCTRL_SCKOUTINV_Pos)
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| 160 | #define I2S_CLKCTRL_MCKSEL_Pos 13 /**< \brief (I2S_CLKCTRL) Master Clock Select */
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| 161 | #define I2S_CLKCTRL_MCKSEL (_U_(0x1) << I2S_CLKCTRL_MCKSEL_Pos)
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| 162 | #define I2S_CLKCTRL_MCKSEL_GCLK_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source */
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| 163 | #define I2S_CLKCTRL_MCKSEL_MCKPIN_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source */
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| 164 | #define I2S_CLKCTRL_MCKSEL_GCLK (I2S_CLKCTRL_MCKSEL_GCLK_Val << I2S_CLKCTRL_MCKSEL_Pos)
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| 165 | #define I2S_CLKCTRL_MCKSEL_MCKPIN (I2S_CLKCTRL_MCKSEL_MCKPIN_Val << I2S_CLKCTRL_MCKSEL_Pos)
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| 166 | #define I2S_CLKCTRL_MCKEN_Pos 14 /**< \brief (I2S_CLKCTRL) Master Clock Enable */
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| 167 | #define I2S_CLKCTRL_MCKEN (_U_(0x1) << I2S_CLKCTRL_MCKEN_Pos)
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| 168 | #define I2S_CLKCTRL_MCKOUTINV_Pos 15 /**< \brief (I2S_CLKCTRL) Master Clock Output Invert */
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| 169 | #define I2S_CLKCTRL_MCKOUTINV (_U_(0x1) << I2S_CLKCTRL_MCKOUTINV_Pos)
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| 170 | #define I2S_CLKCTRL_MCKDIV_Pos 16 /**< \brief (I2S_CLKCTRL) Master Clock Division Factor */
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| 171 | #define I2S_CLKCTRL_MCKDIV_Msk (_U_(0x3F) << I2S_CLKCTRL_MCKDIV_Pos)
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| 172 | #define I2S_CLKCTRL_MCKDIV(value) (I2S_CLKCTRL_MCKDIV_Msk & ((value) << I2S_CLKCTRL_MCKDIV_Pos))
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| 173 | #define I2S_CLKCTRL_MCKOUTDIV_Pos 24 /**< \brief (I2S_CLKCTRL) Master Clock Output Division Factor */
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| 174 | #define I2S_CLKCTRL_MCKOUTDIV_Msk (_U_(0x3F) << I2S_CLKCTRL_MCKOUTDIV_Pos)
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| 175 | #define I2S_CLKCTRL_MCKOUTDIV(value) (I2S_CLKCTRL_MCKOUTDIV_Msk & ((value) << I2S_CLKCTRL_MCKOUTDIV_Pos))
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| 176 | #define I2S_CLKCTRL_MASK _U_(0x3F3FFFFF) /**< \brief (I2S_CLKCTRL) MASK Register */
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| 177 |
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| 178 | /* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
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| 179 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 180 | typedef union {
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| 181 | struct {
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| 182 | uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
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| 183 | uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
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| 184 | uint16_t :2; /*!< bit: 2.. 3 Reserved */
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| 185 | uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
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| 186 | uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
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| 187 | uint16_t :2; /*!< bit: 6.. 7 Reserved */
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| 188 | uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
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| 189 | uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
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| 190 | uint16_t :2; /*!< bit: 10..11 Reserved */
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| 191 | uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
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| 192 | uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
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| 193 | uint16_t :2; /*!< bit: 14..15 Reserved */
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| 194 | } bit; /*!< Structure used for bit access */
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| 195 | struct {
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| 196 | uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
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| 197 | uint16_t :2; /*!< bit: 2.. 3 Reserved */
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| 198 | uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
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| 199 | uint16_t :2; /*!< bit: 6.. 7 Reserved */
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| 200 | uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
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| 201 | uint16_t :2; /*!< bit: 10..11 Reserved */
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| 202 | uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
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| 203 | uint16_t :2; /*!< bit: 14..15 Reserved */
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| 204 | } vec; /*!< Structure used for vec access */
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| 205 | uint16_t reg; /*!< Type used for register access */
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| 206 | } I2S_INTENCLR_Type;
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| 207 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 208 |
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| 209 | #define I2S_INTENCLR_OFFSET 0x0C /**< \brief (I2S_INTENCLR offset) Interrupt Enable Clear */
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| 210 | #define I2S_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (I2S_INTENCLR reset_value) Interrupt Enable Clear */
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| 211 |
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| 212 | #define I2S_INTENCLR_RXRDY0_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready 0 Interrupt Enable */
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| 213 | #define I2S_INTENCLR_RXRDY0 (_U_(1) << I2S_INTENCLR_RXRDY0_Pos)
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| 214 | #define I2S_INTENCLR_RXRDY1_Pos 1 /**< \brief (I2S_INTENCLR) Receive Ready 1 Interrupt Enable */
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| 215 | #define I2S_INTENCLR_RXRDY1 (_U_(1) << I2S_INTENCLR_RXRDY1_Pos)
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| 216 | #define I2S_INTENCLR_RXRDY_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready x Interrupt Enable */
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| 217 | #define I2S_INTENCLR_RXRDY_Msk (_U_(0x3) << I2S_INTENCLR_RXRDY_Pos)
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| 218 | #define I2S_INTENCLR_RXRDY(value) (I2S_INTENCLR_RXRDY_Msk & ((value) << I2S_INTENCLR_RXRDY_Pos))
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| 219 | #define I2S_INTENCLR_RXOR0_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable */
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| 220 | #define I2S_INTENCLR_RXOR0 (_U_(1) << I2S_INTENCLR_RXOR0_Pos)
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| 221 | #define I2S_INTENCLR_RXOR1_Pos 5 /**< \brief (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable */
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| 222 | #define I2S_INTENCLR_RXOR1 (_U_(1) << I2S_INTENCLR_RXOR1_Pos)
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| 223 | #define I2S_INTENCLR_RXOR_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun x Interrupt Enable */
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| 224 | #define I2S_INTENCLR_RXOR_Msk (_U_(0x3) << I2S_INTENCLR_RXOR_Pos)
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| 225 | #define I2S_INTENCLR_RXOR(value) (I2S_INTENCLR_RXOR_Msk & ((value) << I2S_INTENCLR_RXOR_Pos))
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| 226 | #define I2S_INTENCLR_TXRDY0_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable */
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| 227 | #define I2S_INTENCLR_TXRDY0 (_U_(1) << I2S_INTENCLR_TXRDY0_Pos)
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| 228 | #define I2S_INTENCLR_TXRDY1_Pos 9 /**< \brief (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable */
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| 229 | #define I2S_INTENCLR_TXRDY1 (_U_(1) << I2S_INTENCLR_TXRDY1_Pos)
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| 230 | #define I2S_INTENCLR_TXRDY_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready x Interrupt Enable */
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| 231 | #define I2S_INTENCLR_TXRDY_Msk (_U_(0x3) << I2S_INTENCLR_TXRDY_Pos)
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| 232 | #define I2S_INTENCLR_TXRDY(value) (I2S_INTENCLR_TXRDY_Msk & ((value) << I2S_INTENCLR_TXRDY_Pos))
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| 233 | #define I2S_INTENCLR_TXUR0_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable */
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| 234 | #define I2S_INTENCLR_TXUR0 (_U_(1) << I2S_INTENCLR_TXUR0_Pos)
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| 235 | #define I2S_INTENCLR_TXUR1_Pos 13 /**< \brief (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable */
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| 236 | #define I2S_INTENCLR_TXUR1 (_U_(1) << I2S_INTENCLR_TXUR1_Pos)
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| 237 | #define I2S_INTENCLR_TXUR_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun x Interrupt Enable */
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| 238 | #define I2S_INTENCLR_TXUR_Msk (_U_(0x3) << I2S_INTENCLR_TXUR_Pos)
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| 239 | #define I2S_INTENCLR_TXUR(value) (I2S_INTENCLR_TXUR_Msk & ((value) << I2S_INTENCLR_TXUR_Pos))
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| 240 | #define I2S_INTENCLR_MASK _U_(0x3333) /**< \brief (I2S_INTENCLR) MASK Register */
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| 241 |
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| 242 | /* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */
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| 243 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 244 | typedef union {
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| 245 | struct {
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| 246 | uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
|
| 247 | uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
|
| 248 | uint16_t :2; /*!< bit: 2.. 3 Reserved */
|
| 249 | uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
|
| 250 | uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
|
| 251 | uint16_t :2; /*!< bit: 6.. 7 Reserved */
|
| 252 | uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
|
| 253 | uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
|
| 254 | uint16_t :2; /*!< bit: 10..11 Reserved */
|
| 255 | uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
|
| 256 | uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
|
| 257 | uint16_t :2; /*!< bit: 14..15 Reserved */
|
| 258 | } bit; /*!< Structure used for bit access */
|
| 259 | struct {
|
| 260 | uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
|
| 261 | uint16_t :2; /*!< bit: 2.. 3 Reserved */
|
| 262 | uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
|
| 263 | uint16_t :2; /*!< bit: 6.. 7 Reserved */
|
| 264 | uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
|
| 265 | uint16_t :2; /*!< bit: 10..11 Reserved */
|
| 266 | uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
|
| 267 | uint16_t :2; /*!< bit: 14..15 Reserved */
|
| 268 | } vec; /*!< Structure used for vec access */
|
| 269 | uint16_t reg; /*!< Type used for register access */
|
| 270 | } I2S_INTENSET_Type;
|
| 271 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 272 |
|
| 273 | #define I2S_INTENSET_OFFSET 0x10 /**< \brief (I2S_INTENSET offset) Interrupt Enable Set */
|
| 274 | #define I2S_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (I2S_INTENSET reset_value) Interrupt Enable Set */
|
| 275 |
|
| 276 | #define I2S_INTENSET_RXRDY0_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready 0 Interrupt Enable */
|
| 277 | #define I2S_INTENSET_RXRDY0 (_U_(1) << I2S_INTENSET_RXRDY0_Pos)
|
| 278 | #define I2S_INTENSET_RXRDY1_Pos 1 /**< \brief (I2S_INTENSET) Receive Ready 1 Interrupt Enable */
|
| 279 | #define I2S_INTENSET_RXRDY1 (_U_(1) << I2S_INTENSET_RXRDY1_Pos)
|
| 280 | #define I2S_INTENSET_RXRDY_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready x Interrupt Enable */
|
| 281 | #define I2S_INTENSET_RXRDY_Msk (_U_(0x3) << I2S_INTENSET_RXRDY_Pos)
|
| 282 | #define I2S_INTENSET_RXRDY(value) (I2S_INTENSET_RXRDY_Msk & ((value) << I2S_INTENSET_RXRDY_Pos))
|
| 283 | #define I2S_INTENSET_RXOR0_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun 0 Interrupt Enable */
|
| 284 | #define I2S_INTENSET_RXOR0 (_U_(1) << I2S_INTENSET_RXOR0_Pos)
|
| 285 | #define I2S_INTENSET_RXOR1_Pos 5 /**< \brief (I2S_INTENSET) Receive Overrun 1 Interrupt Enable */
|
| 286 | #define I2S_INTENSET_RXOR1 (_U_(1) << I2S_INTENSET_RXOR1_Pos)
|
| 287 | #define I2S_INTENSET_RXOR_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun x Interrupt Enable */
|
| 288 | #define I2S_INTENSET_RXOR_Msk (_U_(0x3) << I2S_INTENSET_RXOR_Pos)
|
| 289 | #define I2S_INTENSET_RXOR(value) (I2S_INTENSET_RXOR_Msk & ((value) << I2S_INTENSET_RXOR_Pos))
|
| 290 | #define I2S_INTENSET_TXRDY0_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready 0 Interrupt Enable */
|
| 291 | #define I2S_INTENSET_TXRDY0 (_U_(1) << I2S_INTENSET_TXRDY0_Pos)
|
| 292 | #define I2S_INTENSET_TXRDY1_Pos 9 /**< \brief (I2S_INTENSET) Transmit Ready 1 Interrupt Enable */
|
| 293 | #define I2S_INTENSET_TXRDY1 (_U_(1) << I2S_INTENSET_TXRDY1_Pos)
|
| 294 | #define I2S_INTENSET_TXRDY_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready x Interrupt Enable */
|
| 295 | #define I2S_INTENSET_TXRDY_Msk (_U_(0x3) << I2S_INTENSET_TXRDY_Pos)
|
| 296 | #define I2S_INTENSET_TXRDY(value) (I2S_INTENSET_TXRDY_Msk & ((value) << I2S_INTENSET_TXRDY_Pos))
|
| 297 | #define I2S_INTENSET_TXUR0_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable */
|
| 298 | #define I2S_INTENSET_TXUR0 (_U_(1) << I2S_INTENSET_TXUR0_Pos)
|
| 299 | #define I2S_INTENSET_TXUR1_Pos 13 /**< \brief (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable */
|
| 300 | #define I2S_INTENSET_TXUR1 (_U_(1) << I2S_INTENSET_TXUR1_Pos)
|
| 301 | #define I2S_INTENSET_TXUR_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun x Interrupt Enable */
|
| 302 | #define I2S_INTENSET_TXUR_Msk (_U_(0x3) << I2S_INTENSET_TXUR_Pos)
|
| 303 | #define I2S_INTENSET_TXUR(value) (I2S_INTENSET_TXUR_Msk & ((value) << I2S_INTENSET_TXUR_Pos))
|
| 304 | #define I2S_INTENSET_MASK _U_(0x3333) /**< \brief (I2S_INTENSET) MASK Register */
|
| 305 |
|
| 306 | /* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
|
| 307 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 308 | typedef union { // __I to avoid read-modify-write on write-to-clear register
|
| 309 | struct {
|
| 310 | __I uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */
|
| 311 | __I uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */
|
| 312 | __I uint16_t :2; /*!< bit: 2.. 3 Reserved */
|
| 313 | __I uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */
|
| 314 | __I uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */
|
| 315 | __I uint16_t :2; /*!< bit: 6.. 7 Reserved */
|
| 316 | __I uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */
|
| 317 | __I uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */
|
| 318 | __I uint16_t :2; /*!< bit: 10..11 Reserved */
|
| 319 | __I uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */
|
| 320 | __I uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */
|
| 321 | __I uint16_t :2; /*!< bit: 14..15 Reserved */
|
| 322 | } bit; /*!< Structure used for bit access */
|
| 323 | struct {
|
| 324 | __I uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */
|
| 325 | __I uint16_t :2; /*!< bit: 2.. 3 Reserved */
|
| 326 | __I uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */
|
| 327 | __I uint16_t :2; /*!< bit: 6.. 7 Reserved */
|
| 328 | __I uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */
|
| 329 | __I uint16_t :2; /*!< bit: 10..11 Reserved */
|
| 330 | __I uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */
|
| 331 | __I uint16_t :2; /*!< bit: 14..15 Reserved */
|
| 332 | } vec; /*!< Structure used for vec access */
|
| 333 | uint16_t reg; /*!< Type used for register access */
|
| 334 | } I2S_INTFLAG_Type;
|
| 335 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 336 |
|
| 337 | #define I2S_INTFLAG_OFFSET 0x14 /**< \brief (I2S_INTFLAG offset) Interrupt Flag Status and Clear */
|
| 338 | #define I2S_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (I2S_INTFLAG reset_value) Interrupt Flag Status and Clear */
|
| 339 |
|
| 340 | #define I2S_INTFLAG_RXRDY0_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready 0 */
|
| 341 | #define I2S_INTFLAG_RXRDY0 (_U_(1) << I2S_INTFLAG_RXRDY0_Pos)
|
| 342 | #define I2S_INTFLAG_RXRDY1_Pos 1 /**< \brief (I2S_INTFLAG) Receive Ready 1 */
|
| 343 | #define I2S_INTFLAG_RXRDY1 (_U_(1) << I2S_INTFLAG_RXRDY1_Pos)
|
| 344 | #define I2S_INTFLAG_RXRDY_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready x */
|
| 345 | #define I2S_INTFLAG_RXRDY_Msk (_U_(0x3) << I2S_INTFLAG_RXRDY_Pos)
|
| 346 | #define I2S_INTFLAG_RXRDY(value) (I2S_INTFLAG_RXRDY_Msk & ((value) << I2S_INTFLAG_RXRDY_Pos))
|
| 347 | #define I2S_INTFLAG_RXOR0_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun 0 */
|
| 348 | #define I2S_INTFLAG_RXOR0 (_U_(1) << I2S_INTFLAG_RXOR0_Pos)
|
| 349 | #define I2S_INTFLAG_RXOR1_Pos 5 /**< \brief (I2S_INTFLAG) Receive Overrun 1 */
|
| 350 | #define I2S_INTFLAG_RXOR1 (_U_(1) << I2S_INTFLAG_RXOR1_Pos)
|
| 351 | #define I2S_INTFLAG_RXOR_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun x */
|
| 352 | #define I2S_INTFLAG_RXOR_Msk (_U_(0x3) << I2S_INTFLAG_RXOR_Pos)
|
| 353 | #define I2S_INTFLAG_RXOR(value) (I2S_INTFLAG_RXOR_Msk & ((value) << I2S_INTFLAG_RXOR_Pos))
|
| 354 | #define I2S_INTFLAG_TXRDY0_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready 0 */
|
| 355 | #define I2S_INTFLAG_TXRDY0 (_U_(1) << I2S_INTFLAG_TXRDY0_Pos)
|
| 356 | #define I2S_INTFLAG_TXRDY1_Pos 9 /**< \brief (I2S_INTFLAG) Transmit Ready 1 */
|
| 357 | #define I2S_INTFLAG_TXRDY1 (_U_(1) << I2S_INTFLAG_TXRDY1_Pos)
|
| 358 | #define I2S_INTFLAG_TXRDY_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready x */
|
| 359 | #define I2S_INTFLAG_TXRDY_Msk (_U_(0x3) << I2S_INTFLAG_TXRDY_Pos)
|
| 360 | #define I2S_INTFLAG_TXRDY(value) (I2S_INTFLAG_TXRDY_Msk & ((value) << I2S_INTFLAG_TXRDY_Pos))
|
| 361 | #define I2S_INTFLAG_TXUR0_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun 0 */
|
| 362 | #define I2S_INTFLAG_TXUR0 (_U_(1) << I2S_INTFLAG_TXUR0_Pos)
|
| 363 | #define I2S_INTFLAG_TXUR1_Pos 13 /**< \brief (I2S_INTFLAG) Transmit Underrun 1 */
|
| 364 | #define I2S_INTFLAG_TXUR1 (_U_(1) << I2S_INTFLAG_TXUR1_Pos)
|
| 365 | #define I2S_INTFLAG_TXUR_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun x */
|
| 366 | #define I2S_INTFLAG_TXUR_Msk (_U_(0x3) << I2S_INTFLAG_TXUR_Pos)
|
| 367 | #define I2S_INTFLAG_TXUR(value) (I2S_INTFLAG_TXUR_Msk & ((value) << I2S_INTFLAG_TXUR_Pos))
|
| 368 | #define I2S_INTFLAG_MASK _U_(0x3333) /**< \brief (I2S_INTFLAG) MASK Register */
|
| 369 |
|
| 370 | /* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/ 16) Synchronization Status -------- */
|
| 371 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 372 | typedef union {
|
| 373 | struct {
|
| 374 | uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */
|
| 375 | uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */
|
| 376 | uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */
|
| 377 | uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */
|
| 378 | uint16_t TXEN:1; /*!< bit: 4 Tx Serializer Enable Synchronization Status */
|
| 379 | uint16_t RXEN:1; /*!< bit: 5 Rx Serializer Enable Synchronization Status */
|
| 380 | uint16_t :2; /*!< bit: 6.. 7 Reserved */
|
| 381 | uint16_t TXDATA:1; /*!< bit: 8 Tx Data Synchronization Status */
|
| 382 | uint16_t RXDATA:1; /*!< bit: 9 Rx Data Synchronization Status */
|
| 383 | uint16_t :6; /*!< bit: 10..15 Reserved */
|
| 384 | } bit; /*!< Structure used for bit access */
|
| 385 | struct {
|
| 386 | uint16_t :2; /*!< bit: 0.. 1 Reserved */
|
| 387 | uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */
|
| 388 | uint16_t :12; /*!< bit: 4..15 Reserved */
|
| 389 | } vec; /*!< Structure used for vec access */
|
| 390 | uint16_t reg; /*!< Type used for register access */
|
| 391 | } I2S_SYNCBUSY_Type;
|
| 392 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 393 |
|
| 394 | #define I2S_SYNCBUSY_OFFSET 0x18 /**< \brief (I2S_SYNCBUSY offset) Synchronization Status */
|
| 395 | #define I2S_SYNCBUSY_RESETVALUE _U_(0x0000) /**< \brief (I2S_SYNCBUSY reset_value) Synchronization Status */
|
| 396 |
|
| 397 | #define I2S_SYNCBUSY_SWRST_Pos 0 /**< \brief (I2S_SYNCBUSY) Software Reset Synchronization Status */
|
| 398 | #define I2S_SYNCBUSY_SWRST (_U_(0x1) << I2S_SYNCBUSY_SWRST_Pos)
|
| 399 | #define I2S_SYNCBUSY_ENABLE_Pos 1 /**< \brief (I2S_SYNCBUSY) Enable Synchronization Status */
|
| 400 | #define I2S_SYNCBUSY_ENABLE (_U_(0x1) << I2S_SYNCBUSY_ENABLE_Pos)
|
| 401 | #define I2S_SYNCBUSY_CKEN0_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status */
|
| 402 | #define I2S_SYNCBUSY_CKEN0 (_U_(1) << I2S_SYNCBUSY_CKEN0_Pos)
|
| 403 | #define I2S_SYNCBUSY_CKEN1_Pos 3 /**< \brief (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status */
|
| 404 | #define I2S_SYNCBUSY_CKEN1 (_U_(1) << I2S_SYNCBUSY_CKEN1_Pos)
|
| 405 | #define I2S_SYNCBUSY_CKEN_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit x Enable Synchronization Status */
|
| 406 | #define I2S_SYNCBUSY_CKEN_Msk (_U_(0x3) << I2S_SYNCBUSY_CKEN_Pos)
|
| 407 | #define I2S_SYNCBUSY_CKEN(value) (I2S_SYNCBUSY_CKEN_Msk & ((value) << I2S_SYNCBUSY_CKEN_Pos))
|
| 408 | #define I2S_SYNCBUSY_TXEN_Pos 4 /**< \brief (I2S_SYNCBUSY) Tx Serializer Enable Synchronization Status */
|
| 409 | #define I2S_SYNCBUSY_TXEN (_U_(0x1) << I2S_SYNCBUSY_TXEN_Pos)
|
| 410 | #define I2S_SYNCBUSY_RXEN_Pos 5 /**< \brief (I2S_SYNCBUSY) Rx Serializer Enable Synchronization Status */
|
| 411 | #define I2S_SYNCBUSY_RXEN (_U_(0x1) << I2S_SYNCBUSY_RXEN_Pos)
|
| 412 | #define I2S_SYNCBUSY_TXDATA_Pos 8 /**< \brief (I2S_SYNCBUSY) Tx Data Synchronization Status */
|
| 413 | #define I2S_SYNCBUSY_TXDATA (_U_(0x1) << I2S_SYNCBUSY_TXDATA_Pos)
|
| 414 | #define I2S_SYNCBUSY_RXDATA_Pos 9 /**< \brief (I2S_SYNCBUSY) Rx Data Synchronization Status */
|
| 415 | #define I2S_SYNCBUSY_RXDATA (_U_(0x1) << I2S_SYNCBUSY_RXDATA_Pos)
|
| 416 | #define I2S_SYNCBUSY_MASK _U_(0x033F) /**< \brief (I2S_SYNCBUSY) MASK Register */
|
| 417 |
|
| 418 | /* -------- I2S_TXCTRL : (I2S Offset: 0x20) (R/W 32) Tx Serializer Control -------- */
|
| 419 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 420 | typedef union {
|
| 421 | struct {
|
| 422 | uint32_t :2; /*!< bit: 0.. 1 Reserved */
|
| 423 | uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */
|
| 424 | uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */
|
| 425 | uint32_t :2; /*!< bit: 5.. 6 Reserved */
|
| 426 | uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */
|
| 427 | uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */
|
| 428 | uint32_t :1; /*!< bit: 11 Reserved */
|
| 429 | uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */
|
| 430 | uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */
|
| 431 | uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */
|
| 432 | uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */
|
| 433 | uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */
|
| 434 | uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */
|
| 435 | uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */
|
| 436 | uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */
|
| 437 | uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */
|
| 438 | uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */
|
| 439 | uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */
|
| 440 | uint32_t MONO:1; /*!< bit: 24 Mono Mode */
|
| 441 | uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */
|
| 442 | uint32_t :6; /*!< bit: 26..31 Reserved */
|
| 443 | } bit; /*!< Structure used for bit access */
|
| 444 | struct {
|
| 445 | uint32_t :16; /*!< bit: 0..15 Reserved */
|
| 446 | uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */
|
| 447 | uint32_t :8; /*!< bit: 24..31 Reserved */
|
| 448 | } vec; /*!< Structure used for vec access */
|
| 449 | uint32_t reg; /*!< Type used for register access */
|
| 450 | } I2S_TXCTRL_Type;
|
| 451 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 452 |
|
| 453 | #define I2S_TXCTRL_OFFSET 0x20 /**< \brief (I2S_TXCTRL offset) Tx Serializer Control */
|
| 454 | #define I2S_TXCTRL_RESETVALUE _U_(0x00000000) /**< \brief (I2S_TXCTRL reset_value) Tx Serializer Control */
|
| 455 |
|
| 456 | #define I2S_TXCTRL_TXDEFAULT_Pos 2 /**< \brief (I2S_TXCTRL) Line Default Line when Slot Disabled */
|
| 457 | #define I2S_TXCTRL_TXDEFAULT_Msk (_U_(0x3) << I2S_TXCTRL_TXDEFAULT_Pos)
|
| 458 | #define I2S_TXCTRL_TXDEFAULT(value) (I2S_TXCTRL_TXDEFAULT_Msk & ((value) << I2S_TXCTRL_TXDEFAULT_Pos))
|
| 459 | #define I2S_TXCTRL_TXDEFAULT_ZERO_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Output Default Value is 0 */
|
| 460 | #define I2S_TXCTRL_TXDEFAULT_ONE_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Output Default Value is 1 */
|
| 461 | #define I2S_TXCTRL_TXDEFAULT_HIZ_Val _U_(0x3) /**< \brief (I2S_TXCTRL) Output Default Value is high impedance */
|
| 462 | #define I2S_TXCTRL_TXDEFAULT_ZERO (I2S_TXCTRL_TXDEFAULT_ZERO_Val << I2S_TXCTRL_TXDEFAULT_Pos)
|
| 463 | #define I2S_TXCTRL_TXDEFAULT_ONE (I2S_TXCTRL_TXDEFAULT_ONE_Val << I2S_TXCTRL_TXDEFAULT_Pos)
|
| 464 | #define I2S_TXCTRL_TXDEFAULT_HIZ (I2S_TXCTRL_TXDEFAULT_HIZ_Val << I2S_TXCTRL_TXDEFAULT_Pos)
|
| 465 | #define I2S_TXCTRL_TXSAME_Pos 4 /**< \brief (I2S_TXCTRL) Transmit Data when Underrun */
|
| 466 | #define I2S_TXCTRL_TXSAME (_U_(0x1) << I2S_TXCTRL_TXSAME_Pos)
|
| 467 | #define I2S_TXCTRL_TXSAME_ZERO_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Zero data transmitted in case of underrun */
|
| 468 | #define I2S_TXCTRL_TXSAME_SAME_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Last data transmitted in case of underrun */
|
| 469 | #define I2S_TXCTRL_TXSAME_ZERO (I2S_TXCTRL_TXSAME_ZERO_Val << I2S_TXCTRL_TXSAME_Pos)
|
| 470 | #define I2S_TXCTRL_TXSAME_SAME (I2S_TXCTRL_TXSAME_SAME_Val << I2S_TXCTRL_TXSAME_Pos)
|
| 471 | #define I2S_TXCTRL_SLOTADJ_Pos 7 /**< \brief (I2S_TXCTRL) Data Slot Formatting Adjust */
|
| 472 | #define I2S_TXCTRL_SLOTADJ (_U_(0x1) << I2S_TXCTRL_SLOTADJ_Pos)
|
| 473 | #define I2S_TXCTRL_SLOTADJ_RIGHT_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Data is right adjusted in slot */
|
| 474 | #define I2S_TXCTRL_SLOTADJ_LEFT_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Data is left adjusted in slot */
|
| 475 | #define I2S_TXCTRL_SLOTADJ_RIGHT (I2S_TXCTRL_SLOTADJ_RIGHT_Val << I2S_TXCTRL_SLOTADJ_Pos)
|
| 476 | #define I2S_TXCTRL_SLOTADJ_LEFT (I2S_TXCTRL_SLOTADJ_LEFT_Val << I2S_TXCTRL_SLOTADJ_Pos)
|
| 477 | #define I2S_TXCTRL_DATASIZE_Pos 8 /**< \brief (I2S_TXCTRL) Data Word Size */
|
| 478 | #define I2S_TXCTRL_DATASIZE_Msk (_U_(0x7) << I2S_TXCTRL_DATASIZE_Pos)
|
| 479 | #define I2S_TXCTRL_DATASIZE(value) (I2S_TXCTRL_DATASIZE_Msk & ((value) << I2S_TXCTRL_DATASIZE_Pos))
|
| 480 | #define I2S_TXCTRL_DATASIZE_32_Val _U_(0x0) /**< \brief (I2S_TXCTRL) 32 bits */
|
| 481 | #define I2S_TXCTRL_DATASIZE_24_Val _U_(0x1) /**< \brief (I2S_TXCTRL) 24 bits */
|
| 482 | #define I2S_TXCTRL_DATASIZE_20_Val _U_(0x2) /**< \brief (I2S_TXCTRL) 20 bits */
|
| 483 | #define I2S_TXCTRL_DATASIZE_18_Val _U_(0x3) /**< \brief (I2S_TXCTRL) 18 bits */
|
| 484 | #define I2S_TXCTRL_DATASIZE_16_Val _U_(0x4) /**< \brief (I2S_TXCTRL) 16 bits */
|
| 485 | #define I2S_TXCTRL_DATASIZE_16C_Val _U_(0x5) /**< \brief (I2S_TXCTRL) 16 bits compact stereo */
|
| 486 | #define I2S_TXCTRL_DATASIZE_8_Val _U_(0x6) /**< \brief (I2S_TXCTRL) 8 bits */
|
| 487 | #define I2S_TXCTRL_DATASIZE_8C_Val _U_(0x7) /**< \brief (I2S_TXCTRL) 8 bits compact stereo */
|
| 488 | #define I2S_TXCTRL_DATASIZE_32 (I2S_TXCTRL_DATASIZE_32_Val << I2S_TXCTRL_DATASIZE_Pos)
|
| 489 | #define I2S_TXCTRL_DATASIZE_24 (I2S_TXCTRL_DATASIZE_24_Val << I2S_TXCTRL_DATASIZE_Pos)
|
| 490 | #define I2S_TXCTRL_DATASIZE_20 (I2S_TXCTRL_DATASIZE_20_Val << I2S_TXCTRL_DATASIZE_Pos)
|
| 491 | #define I2S_TXCTRL_DATASIZE_18 (I2S_TXCTRL_DATASIZE_18_Val << I2S_TXCTRL_DATASIZE_Pos)
|
| 492 | #define I2S_TXCTRL_DATASIZE_16 (I2S_TXCTRL_DATASIZE_16_Val << I2S_TXCTRL_DATASIZE_Pos)
|
| 493 | #define I2S_TXCTRL_DATASIZE_16C (I2S_TXCTRL_DATASIZE_16C_Val << I2S_TXCTRL_DATASIZE_Pos)
|
| 494 | #define I2S_TXCTRL_DATASIZE_8 (I2S_TXCTRL_DATASIZE_8_Val << I2S_TXCTRL_DATASIZE_Pos)
|
| 495 | #define I2S_TXCTRL_DATASIZE_8C (I2S_TXCTRL_DATASIZE_8C_Val << I2S_TXCTRL_DATASIZE_Pos)
|
| 496 | #define I2S_TXCTRL_WORDADJ_Pos 12 /**< \brief (I2S_TXCTRL) Data Word Formatting Adjust */
|
| 497 | #define I2S_TXCTRL_WORDADJ (_U_(0x1) << I2S_TXCTRL_WORDADJ_Pos)
|
| 498 | #define I2S_TXCTRL_WORDADJ_RIGHT_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Data is right adjusted in word */
|
| 499 | #define I2S_TXCTRL_WORDADJ_LEFT_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Data is left adjusted in word */
|
| 500 | #define I2S_TXCTRL_WORDADJ_RIGHT (I2S_TXCTRL_WORDADJ_RIGHT_Val << I2S_TXCTRL_WORDADJ_Pos)
|
| 501 | #define I2S_TXCTRL_WORDADJ_LEFT (I2S_TXCTRL_WORDADJ_LEFT_Val << I2S_TXCTRL_WORDADJ_Pos)
|
| 502 | #define I2S_TXCTRL_EXTEND_Pos 13 /**< \brief (I2S_TXCTRL) Data Formatting Bit Extension */
|
| 503 | #define I2S_TXCTRL_EXTEND_Msk (_U_(0x3) << I2S_TXCTRL_EXTEND_Pos)
|
| 504 | #define I2S_TXCTRL_EXTEND(value) (I2S_TXCTRL_EXTEND_Msk & ((value) << I2S_TXCTRL_EXTEND_Pos))
|
| 505 | #define I2S_TXCTRL_EXTEND_ZERO_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Extend with zeroes */
|
| 506 | #define I2S_TXCTRL_EXTEND_ONE_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Extend with ones */
|
| 507 | #define I2S_TXCTRL_EXTEND_MSBIT_Val _U_(0x2) /**< \brief (I2S_TXCTRL) Extend with Most Significant Bit */
|
| 508 | #define I2S_TXCTRL_EXTEND_LSBIT_Val _U_(0x3) /**< \brief (I2S_TXCTRL) Extend with Least Significant Bit */
|
| 509 | #define I2S_TXCTRL_EXTEND_ZERO (I2S_TXCTRL_EXTEND_ZERO_Val << I2S_TXCTRL_EXTEND_Pos)
|
| 510 | #define I2S_TXCTRL_EXTEND_ONE (I2S_TXCTRL_EXTEND_ONE_Val << I2S_TXCTRL_EXTEND_Pos)
|
| 511 | #define I2S_TXCTRL_EXTEND_MSBIT (I2S_TXCTRL_EXTEND_MSBIT_Val << I2S_TXCTRL_EXTEND_Pos)
|
| 512 | #define I2S_TXCTRL_EXTEND_LSBIT (I2S_TXCTRL_EXTEND_LSBIT_Val << I2S_TXCTRL_EXTEND_Pos)
|
| 513 | #define I2S_TXCTRL_BITREV_Pos 15 /**< \brief (I2S_TXCTRL) Data Formatting Bit Reverse */
|
| 514 | #define I2S_TXCTRL_BITREV (_U_(0x1) << I2S_TXCTRL_BITREV_Pos)
|
| 515 | #define I2S_TXCTRL_BITREV_MSBIT_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
|
| 516 | #define I2S_TXCTRL_BITREV_LSBIT_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Transfer Data Least Significant Bit (LSB) first */
|
| 517 | #define I2S_TXCTRL_BITREV_MSBIT (I2S_TXCTRL_BITREV_MSBIT_Val << I2S_TXCTRL_BITREV_Pos)
|
| 518 | #define I2S_TXCTRL_BITREV_LSBIT (I2S_TXCTRL_BITREV_LSBIT_Val << I2S_TXCTRL_BITREV_Pos)
|
| 519 | #define I2S_TXCTRL_SLOTDIS0_Pos 16 /**< \brief (I2S_TXCTRL) Slot 0 Disabled for this Serializer */
|
| 520 | #define I2S_TXCTRL_SLOTDIS0 (_U_(1) << I2S_TXCTRL_SLOTDIS0_Pos)
|
| 521 | #define I2S_TXCTRL_SLOTDIS1_Pos 17 /**< \brief (I2S_TXCTRL) Slot 1 Disabled for this Serializer */
|
| 522 | #define I2S_TXCTRL_SLOTDIS1 (_U_(1) << I2S_TXCTRL_SLOTDIS1_Pos)
|
| 523 | #define I2S_TXCTRL_SLOTDIS2_Pos 18 /**< \brief (I2S_TXCTRL) Slot 2 Disabled for this Serializer */
|
| 524 | #define I2S_TXCTRL_SLOTDIS2 (_U_(1) << I2S_TXCTRL_SLOTDIS2_Pos)
|
| 525 | #define I2S_TXCTRL_SLOTDIS3_Pos 19 /**< \brief (I2S_TXCTRL) Slot 3 Disabled for this Serializer */
|
| 526 | #define I2S_TXCTRL_SLOTDIS3 (_U_(1) << I2S_TXCTRL_SLOTDIS3_Pos)
|
| 527 | #define I2S_TXCTRL_SLOTDIS4_Pos 20 /**< \brief (I2S_TXCTRL) Slot 4 Disabled for this Serializer */
|
| 528 | #define I2S_TXCTRL_SLOTDIS4 (_U_(1) << I2S_TXCTRL_SLOTDIS4_Pos)
|
| 529 | #define I2S_TXCTRL_SLOTDIS5_Pos 21 /**< \brief (I2S_TXCTRL) Slot 5 Disabled for this Serializer */
|
| 530 | #define I2S_TXCTRL_SLOTDIS5 (_U_(1) << I2S_TXCTRL_SLOTDIS5_Pos)
|
| 531 | #define I2S_TXCTRL_SLOTDIS6_Pos 22 /**< \brief (I2S_TXCTRL) Slot 6 Disabled for this Serializer */
|
| 532 | #define I2S_TXCTRL_SLOTDIS6 (_U_(1) << I2S_TXCTRL_SLOTDIS6_Pos)
|
| 533 | #define I2S_TXCTRL_SLOTDIS7_Pos 23 /**< \brief (I2S_TXCTRL) Slot 7 Disabled for this Serializer */
|
| 534 | #define I2S_TXCTRL_SLOTDIS7 (_U_(1) << I2S_TXCTRL_SLOTDIS7_Pos)
|
| 535 | #define I2S_TXCTRL_SLOTDIS_Pos 16 /**< \brief (I2S_TXCTRL) Slot x Disabled for this Serializer */
|
| 536 | #define I2S_TXCTRL_SLOTDIS_Msk (_U_(0xFF) << I2S_TXCTRL_SLOTDIS_Pos)
|
| 537 | #define I2S_TXCTRL_SLOTDIS(value) (I2S_TXCTRL_SLOTDIS_Msk & ((value) << I2S_TXCTRL_SLOTDIS_Pos))
|
| 538 | #define I2S_TXCTRL_MONO_Pos 24 /**< \brief (I2S_TXCTRL) Mono Mode */
|
| 539 | #define I2S_TXCTRL_MONO (_U_(0x1) << I2S_TXCTRL_MONO_Pos)
|
| 540 | #define I2S_TXCTRL_MONO_STEREO_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Normal mode */
|
| 541 | #define I2S_TXCTRL_MONO_MONO_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Left channel data is duplicated to right channel */
|
| 542 | #define I2S_TXCTRL_MONO_STEREO (I2S_TXCTRL_MONO_STEREO_Val << I2S_TXCTRL_MONO_Pos)
|
| 543 | #define I2S_TXCTRL_MONO_MONO (I2S_TXCTRL_MONO_MONO_Val << I2S_TXCTRL_MONO_Pos)
|
| 544 | #define I2S_TXCTRL_DMA_Pos 25 /**< \brief (I2S_TXCTRL) Single or Multiple DMA Channels */
|
| 545 | #define I2S_TXCTRL_DMA (_U_(0x1) << I2S_TXCTRL_DMA_Pos)
|
| 546 | #define I2S_TXCTRL_DMA_SINGLE_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Single DMA channel */
|
| 547 | #define I2S_TXCTRL_DMA_MULTIPLE_Val _U_(0x1) /**< \brief (I2S_TXCTRL) One DMA channel per data channel */
|
| 548 | #define I2S_TXCTRL_DMA_SINGLE (I2S_TXCTRL_DMA_SINGLE_Val << I2S_TXCTRL_DMA_Pos)
|
| 549 | #define I2S_TXCTRL_DMA_MULTIPLE (I2S_TXCTRL_DMA_MULTIPLE_Val << I2S_TXCTRL_DMA_Pos)
|
| 550 | #define I2S_TXCTRL_MASK _U_(0x03FFF79C) /**< \brief (I2S_TXCTRL) MASK Register */
|
| 551 |
|
| 552 | /* -------- I2S_RXCTRL : (I2S Offset: 0x24) (R/W 32) Rx Serializer Control -------- */
|
| 553 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 554 | typedef union {
|
| 555 | struct {
|
| 556 | uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */
|
| 557 | uint32_t :3; /*!< bit: 2.. 4 Reserved */
|
| 558 | uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */
|
| 559 | uint32_t :1; /*!< bit: 6 Reserved */
|
| 560 | uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */
|
| 561 | uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */
|
| 562 | uint32_t :1; /*!< bit: 11 Reserved */
|
| 563 | uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */
|
| 564 | uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */
|
| 565 | uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */
|
| 566 | uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */
|
| 567 | uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */
|
| 568 | uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */
|
| 569 | uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */
|
| 570 | uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */
|
| 571 | uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */
|
| 572 | uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */
|
| 573 | uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */
|
| 574 | uint32_t MONO:1; /*!< bit: 24 Mono Mode */
|
| 575 | uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */
|
| 576 | uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */
|
| 577 | uint32_t :5; /*!< bit: 27..31 Reserved */
|
| 578 | } bit; /*!< Structure used for bit access */
|
| 579 | struct {
|
| 580 | uint32_t :16; /*!< bit: 0..15 Reserved */
|
| 581 | uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */
|
| 582 | uint32_t :8; /*!< bit: 24..31 Reserved */
|
| 583 | } vec; /*!< Structure used for vec access */
|
| 584 | uint32_t reg; /*!< Type used for register access */
|
| 585 | } I2S_RXCTRL_Type;
|
| 586 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 587 |
|
| 588 | #define I2S_RXCTRL_OFFSET 0x24 /**< \brief (I2S_RXCTRL offset) Rx Serializer Control */
|
| 589 | #define I2S_RXCTRL_RESETVALUE _U_(0x00000000) /**< \brief (I2S_RXCTRL reset_value) Rx Serializer Control */
|
| 590 |
|
| 591 | #define I2S_RXCTRL_SERMODE_Pos 0 /**< \brief (I2S_RXCTRL) Serializer Mode */
|
| 592 | #define I2S_RXCTRL_SERMODE_Msk (_U_(0x3) << I2S_RXCTRL_SERMODE_Pos)
|
| 593 | #define I2S_RXCTRL_SERMODE(value) (I2S_RXCTRL_SERMODE_Msk & ((value) << I2S_RXCTRL_SERMODE_Pos))
|
| 594 | #define I2S_RXCTRL_SERMODE_RX_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Receive */
|
| 595 | #define I2S_RXCTRL_SERMODE_PDM2_Val _U_(0x2) /**< \brief (I2S_RXCTRL) Receive one PDM data on each serial clock edge */
|
| 596 | #define I2S_RXCTRL_SERMODE_RX (I2S_RXCTRL_SERMODE_RX_Val << I2S_RXCTRL_SERMODE_Pos)
|
| 597 | #define I2S_RXCTRL_SERMODE_PDM2 (I2S_RXCTRL_SERMODE_PDM2_Val << I2S_RXCTRL_SERMODE_Pos)
|
| 598 | #define I2S_RXCTRL_CLKSEL_Pos 5 /**< \brief (I2S_RXCTRL) Clock Unit Selection */
|
| 599 | #define I2S_RXCTRL_CLKSEL (_U_(0x1) << I2S_RXCTRL_CLKSEL_Pos)
|
| 600 | #define I2S_RXCTRL_CLKSEL_CLK0_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Use Clock Unit 0 */
|
| 601 | #define I2S_RXCTRL_CLKSEL_CLK1_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Use Clock Unit 1 */
|
| 602 | #define I2S_RXCTRL_CLKSEL_CLK0 (I2S_RXCTRL_CLKSEL_CLK0_Val << I2S_RXCTRL_CLKSEL_Pos)
|
| 603 | #define I2S_RXCTRL_CLKSEL_CLK1 (I2S_RXCTRL_CLKSEL_CLK1_Val << I2S_RXCTRL_CLKSEL_Pos)
|
| 604 | #define I2S_RXCTRL_SLOTADJ_Pos 7 /**< \brief (I2S_RXCTRL) Data Slot Formatting Adjust */
|
| 605 | #define I2S_RXCTRL_SLOTADJ (_U_(0x1) << I2S_RXCTRL_SLOTADJ_Pos)
|
| 606 | #define I2S_RXCTRL_SLOTADJ_RIGHT_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Data is right adjusted in slot */
|
| 607 | #define I2S_RXCTRL_SLOTADJ_LEFT_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Data is left adjusted in slot */
|
| 608 | #define I2S_RXCTRL_SLOTADJ_RIGHT (I2S_RXCTRL_SLOTADJ_RIGHT_Val << I2S_RXCTRL_SLOTADJ_Pos)
|
| 609 | #define I2S_RXCTRL_SLOTADJ_LEFT (I2S_RXCTRL_SLOTADJ_LEFT_Val << I2S_RXCTRL_SLOTADJ_Pos)
|
| 610 | #define I2S_RXCTRL_DATASIZE_Pos 8 /**< \brief (I2S_RXCTRL) Data Word Size */
|
| 611 | #define I2S_RXCTRL_DATASIZE_Msk (_U_(0x7) << I2S_RXCTRL_DATASIZE_Pos)
|
| 612 | #define I2S_RXCTRL_DATASIZE(value) (I2S_RXCTRL_DATASIZE_Msk & ((value) << I2S_RXCTRL_DATASIZE_Pos))
|
| 613 | #define I2S_RXCTRL_DATASIZE_32_Val _U_(0x0) /**< \brief (I2S_RXCTRL) 32 bits */
|
| 614 | #define I2S_RXCTRL_DATASIZE_24_Val _U_(0x1) /**< \brief (I2S_RXCTRL) 24 bits */
|
| 615 | #define I2S_RXCTRL_DATASIZE_20_Val _U_(0x2) /**< \brief (I2S_RXCTRL) 20 bits */
|
| 616 | #define I2S_RXCTRL_DATASIZE_18_Val _U_(0x3) /**< \brief (I2S_RXCTRL) 18 bits */
|
| 617 | #define I2S_RXCTRL_DATASIZE_16_Val _U_(0x4) /**< \brief (I2S_RXCTRL) 16 bits */
|
| 618 | #define I2S_RXCTRL_DATASIZE_16C_Val _U_(0x5) /**< \brief (I2S_RXCTRL) 16 bits compact stereo */
|
| 619 | #define I2S_RXCTRL_DATASIZE_8_Val _U_(0x6) /**< \brief (I2S_RXCTRL) 8 bits */
|
| 620 | #define I2S_RXCTRL_DATASIZE_8C_Val _U_(0x7) /**< \brief (I2S_RXCTRL) 8 bits compact stereo */
|
| 621 | #define I2S_RXCTRL_DATASIZE_32 (I2S_RXCTRL_DATASIZE_32_Val << I2S_RXCTRL_DATASIZE_Pos)
|
| 622 | #define I2S_RXCTRL_DATASIZE_24 (I2S_RXCTRL_DATASIZE_24_Val << I2S_RXCTRL_DATASIZE_Pos)
|
| 623 | #define I2S_RXCTRL_DATASIZE_20 (I2S_RXCTRL_DATASIZE_20_Val << I2S_RXCTRL_DATASIZE_Pos)
|
| 624 | #define I2S_RXCTRL_DATASIZE_18 (I2S_RXCTRL_DATASIZE_18_Val << I2S_RXCTRL_DATASIZE_Pos)
|
| 625 | #define I2S_RXCTRL_DATASIZE_16 (I2S_RXCTRL_DATASIZE_16_Val << I2S_RXCTRL_DATASIZE_Pos)
|
| 626 | #define I2S_RXCTRL_DATASIZE_16C (I2S_RXCTRL_DATASIZE_16C_Val << I2S_RXCTRL_DATASIZE_Pos)
|
| 627 | #define I2S_RXCTRL_DATASIZE_8 (I2S_RXCTRL_DATASIZE_8_Val << I2S_RXCTRL_DATASIZE_Pos)
|
| 628 | #define I2S_RXCTRL_DATASIZE_8C (I2S_RXCTRL_DATASIZE_8C_Val << I2S_RXCTRL_DATASIZE_Pos)
|
| 629 | #define I2S_RXCTRL_WORDADJ_Pos 12 /**< \brief (I2S_RXCTRL) Data Word Formatting Adjust */
|
| 630 | #define I2S_RXCTRL_WORDADJ (_U_(0x1) << I2S_RXCTRL_WORDADJ_Pos)
|
| 631 | #define I2S_RXCTRL_WORDADJ_RIGHT_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Data is right adjusted in word */
|
| 632 | #define I2S_RXCTRL_WORDADJ_LEFT_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Data is left adjusted in word */
|
| 633 | #define I2S_RXCTRL_WORDADJ_RIGHT (I2S_RXCTRL_WORDADJ_RIGHT_Val << I2S_RXCTRL_WORDADJ_Pos)
|
| 634 | #define I2S_RXCTRL_WORDADJ_LEFT (I2S_RXCTRL_WORDADJ_LEFT_Val << I2S_RXCTRL_WORDADJ_Pos)
|
| 635 | #define I2S_RXCTRL_EXTEND_Pos 13 /**< \brief (I2S_RXCTRL) Data Formatting Bit Extension */
|
| 636 | #define I2S_RXCTRL_EXTEND_Msk (_U_(0x3) << I2S_RXCTRL_EXTEND_Pos)
|
| 637 | #define I2S_RXCTRL_EXTEND(value) (I2S_RXCTRL_EXTEND_Msk & ((value) << I2S_RXCTRL_EXTEND_Pos))
|
| 638 | #define I2S_RXCTRL_EXTEND_ZERO_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Extend with zeroes */
|
| 639 | #define I2S_RXCTRL_EXTEND_ONE_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Extend with ones */
|
| 640 | #define I2S_RXCTRL_EXTEND_MSBIT_Val _U_(0x2) /**< \brief (I2S_RXCTRL) Extend with Most Significant Bit */
|
| 641 | #define I2S_RXCTRL_EXTEND_LSBIT_Val _U_(0x3) /**< \brief (I2S_RXCTRL) Extend with Least Significant Bit */
|
| 642 | #define I2S_RXCTRL_EXTEND_ZERO (I2S_RXCTRL_EXTEND_ZERO_Val << I2S_RXCTRL_EXTEND_Pos)
|
| 643 | #define I2S_RXCTRL_EXTEND_ONE (I2S_RXCTRL_EXTEND_ONE_Val << I2S_RXCTRL_EXTEND_Pos)
|
| 644 | #define I2S_RXCTRL_EXTEND_MSBIT (I2S_RXCTRL_EXTEND_MSBIT_Val << I2S_RXCTRL_EXTEND_Pos)
|
| 645 | #define I2S_RXCTRL_EXTEND_LSBIT (I2S_RXCTRL_EXTEND_LSBIT_Val << I2S_RXCTRL_EXTEND_Pos)
|
| 646 | #define I2S_RXCTRL_BITREV_Pos 15 /**< \brief (I2S_RXCTRL) Data Formatting Bit Reverse */
|
| 647 | #define I2S_RXCTRL_BITREV (_U_(0x1) << I2S_RXCTRL_BITREV_Pos)
|
| 648 | #define I2S_RXCTRL_BITREV_MSBIT_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
|
| 649 | #define I2S_RXCTRL_BITREV_LSBIT_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Transfer Data Least Significant Bit (LSB) first */
|
| 650 | #define I2S_RXCTRL_BITREV_MSBIT (I2S_RXCTRL_BITREV_MSBIT_Val << I2S_RXCTRL_BITREV_Pos)
|
| 651 | #define I2S_RXCTRL_BITREV_LSBIT (I2S_RXCTRL_BITREV_LSBIT_Val << I2S_RXCTRL_BITREV_Pos)
|
| 652 | #define I2S_RXCTRL_SLOTDIS0_Pos 16 /**< \brief (I2S_RXCTRL) Slot 0 Disabled for this Serializer */
|
| 653 | #define I2S_RXCTRL_SLOTDIS0 (_U_(1) << I2S_RXCTRL_SLOTDIS0_Pos)
|
| 654 | #define I2S_RXCTRL_SLOTDIS1_Pos 17 /**< \brief (I2S_RXCTRL) Slot 1 Disabled for this Serializer */
|
| 655 | #define I2S_RXCTRL_SLOTDIS1 (_U_(1) << I2S_RXCTRL_SLOTDIS1_Pos)
|
| 656 | #define I2S_RXCTRL_SLOTDIS2_Pos 18 /**< \brief (I2S_RXCTRL) Slot 2 Disabled for this Serializer */
|
| 657 | #define I2S_RXCTRL_SLOTDIS2 (_U_(1) << I2S_RXCTRL_SLOTDIS2_Pos)
|
| 658 | #define I2S_RXCTRL_SLOTDIS3_Pos 19 /**< \brief (I2S_RXCTRL) Slot 3 Disabled for this Serializer */
|
| 659 | #define I2S_RXCTRL_SLOTDIS3 (_U_(1) << I2S_RXCTRL_SLOTDIS3_Pos)
|
| 660 | #define I2S_RXCTRL_SLOTDIS4_Pos 20 /**< \brief (I2S_RXCTRL) Slot 4 Disabled for this Serializer */
|
| 661 | #define I2S_RXCTRL_SLOTDIS4 (_U_(1) << I2S_RXCTRL_SLOTDIS4_Pos)
|
| 662 | #define I2S_RXCTRL_SLOTDIS5_Pos 21 /**< \brief (I2S_RXCTRL) Slot 5 Disabled for this Serializer */
|
| 663 | #define I2S_RXCTRL_SLOTDIS5 (_U_(1) << I2S_RXCTRL_SLOTDIS5_Pos)
|
| 664 | #define I2S_RXCTRL_SLOTDIS6_Pos 22 /**< \brief (I2S_RXCTRL) Slot 6 Disabled for this Serializer */
|
| 665 | #define I2S_RXCTRL_SLOTDIS6 (_U_(1) << I2S_RXCTRL_SLOTDIS6_Pos)
|
| 666 | #define I2S_RXCTRL_SLOTDIS7_Pos 23 /**< \brief (I2S_RXCTRL) Slot 7 Disabled for this Serializer */
|
| 667 | #define I2S_RXCTRL_SLOTDIS7 (_U_(1) << I2S_RXCTRL_SLOTDIS7_Pos)
|
| 668 | #define I2S_RXCTRL_SLOTDIS_Pos 16 /**< \brief (I2S_RXCTRL) Slot x Disabled for this Serializer */
|
| 669 | #define I2S_RXCTRL_SLOTDIS_Msk (_U_(0xFF) << I2S_RXCTRL_SLOTDIS_Pos)
|
| 670 | #define I2S_RXCTRL_SLOTDIS(value) (I2S_RXCTRL_SLOTDIS_Msk & ((value) << I2S_RXCTRL_SLOTDIS_Pos))
|
| 671 | #define I2S_RXCTRL_MONO_Pos 24 /**< \brief (I2S_RXCTRL) Mono Mode */
|
| 672 | #define I2S_RXCTRL_MONO (_U_(0x1) << I2S_RXCTRL_MONO_Pos)
|
| 673 | #define I2S_RXCTRL_MONO_STEREO_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Normal mode */
|
| 674 | #define I2S_RXCTRL_MONO_MONO_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Left channel data is duplicated to right channel */
|
| 675 | #define I2S_RXCTRL_MONO_STEREO (I2S_RXCTRL_MONO_STEREO_Val << I2S_RXCTRL_MONO_Pos)
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| 676 | #define I2S_RXCTRL_MONO_MONO (I2S_RXCTRL_MONO_MONO_Val << I2S_RXCTRL_MONO_Pos)
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| 677 | #define I2S_RXCTRL_DMA_Pos 25 /**< \brief (I2S_RXCTRL) Single or Multiple DMA Channels */
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| 678 | #define I2S_RXCTRL_DMA (_U_(0x1) << I2S_RXCTRL_DMA_Pos)
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| 679 | #define I2S_RXCTRL_DMA_SINGLE_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Single DMA channel */
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| 680 | #define I2S_RXCTRL_DMA_MULTIPLE_Val _U_(0x1) /**< \brief (I2S_RXCTRL) One DMA channel per data channel */
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| 681 | #define I2S_RXCTRL_DMA_SINGLE (I2S_RXCTRL_DMA_SINGLE_Val << I2S_RXCTRL_DMA_Pos)
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| 682 | #define I2S_RXCTRL_DMA_MULTIPLE (I2S_RXCTRL_DMA_MULTIPLE_Val << I2S_RXCTRL_DMA_Pos)
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| 683 | #define I2S_RXCTRL_RXLOOP_Pos 26 /**< \brief (I2S_RXCTRL) Loop-back Test Mode */
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| 684 | #define I2S_RXCTRL_RXLOOP (_U_(0x1) << I2S_RXCTRL_RXLOOP_Pos)
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| 685 | #define I2S_RXCTRL_MASK _U_(0x07FFF7A3) /**< \brief (I2S_RXCTRL) MASK Register */
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| 686 |
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| 687 | /* -------- I2S_TXDATA : (I2S Offset: 0x30) ( /W 32) Tx Data -------- */
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| 688 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 689 | typedef union {
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| 690 | struct {
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| 691 | uint32_t DATA:32; /*!< bit: 0..31 Sample Data */
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| 692 | } bit; /*!< Structure used for bit access */
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| 693 | uint32_t reg; /*!< Type used for register access */
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| 694 | } I2S_TXDATA_Type;
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| 695 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 696 |
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| 697 | #define I2S_TXDATA_OFFSET 0x30 /**< \brief (I2S_TXDATA offset) Tx Data */
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| 698 | #define I2S_TXDATA_RESETVALUE _U_(0x00000000) /**< \brief (I2S_TXDATA reset_value) Tx Data */
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| 699 |
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| 700 | #define I2S_TXDATA_DATA_Pos 0 /**< \brief (I2S_TXDATA) Sample Data */
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| 701 | #define I2S_TXDATA_DATA_Msk (_U_(0xFFFFFFFF) << I2S_TXDATA_DATA_Pos)
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| 702 | #define I2S_TXDATA_DATA(value) (I2S_TXDATA_DATA_Msk & ((value) << I2S_TXDATA_DATA_Pos))
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| 703 | #define I2S_TXDATA_MASK _U_(0xFFFFFFFF) /**< \brief (I2S_TXDATA) MASK Register */
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| 704 |
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| 705 | /* -------- I2S_RXDATA : (I2S Offset: 0x34) (R/ 32) Rx Data -------- */
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| 706 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 707 | typedef union {
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| 708 | struct {
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| 709 | uint32_t DATA:32; /*!< bit: 0..31 Sample Data */
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| 710 | } bit; /*!< Structure used for bit access */
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| 711 | uint32_t reg; /*!< Type used for register access */
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| 712 | } I2S_RXDATA_Type;
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| 713 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 714 |
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| 715 | #define I2S_RXDATA_OFFSET 0x34 /**< \brief (I2S_RXDATA offset) Rx Data */
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| 716 | #define I2S_RXDATA_RESETVALUE _U_(0x00000000) /**< \brief (I2S_RXDATA reset_value) Rx Data */
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| 717 |
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| 718 | #define I2S_RXDATA_DATA_Pos 0 /**< \brief (I2S_RXDATA) Sample Data */
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| 719 | #define I2S_RXDATA_DATA_Msk (_U_(0xFFFFFFFF) << I2S_RXDATA_DATA_Pos)
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| 720 | #define I2S_RXDATA_DATA(value) (I2S_RXDATA_DATA_Msk & ((value) << I2S_RXDATA_DATA_Pos))
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| 721 | #define I2S_RXDATA_MASK _U_(0xFFFFFFFF) /**< \brief (I2S_RXDATA) MASK Register */
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| 722 |
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| 723 | /** \brief I2S hardware registers */
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| 724 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 725 | typedef struct {
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| 726 | __IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
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| 727 | RoReg8 Reserved1[0x3];
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| 728 | __IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */
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| 729 | __IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
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| 730 | RoReg8 Reserved2[0x2];
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| 731 | __IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */
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| 732 | RoReg8 Reserved3[0x2];
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| 733 | __IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */
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| 734 | RoReg8 Reserved4[0x2];
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| 735 | __I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */
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| 736 | RoReg8 Reserved5[0x6];
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| 737 | __IO I2S_TXCTRL_Type TXCTRL; /**< \brief Offset: 0x20 (R/W 32) Tx Serializer Control */
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| 738 | __IO I2S_RXCTRL_Type RXCTRL; /**< \brief Offset: 0x24 (R/W 32) Rx Serializer Control */
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| 739 | RoReg8 Reserved6[0x8];
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| 740 | __O I2S_TXDATA_Type TXDATA; /**< \brief Offset: 0x30 ( /W 32) Tx Data */
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| 741 | __I I2S_RXDATA_Type RXDATA; /**< \brief Offset: 0x34 (R/ 32) Rx Data */
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| 742 | } I2s;
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| 743 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 744 |
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| 745 | /*@}*/
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| 746 |
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| 747 | #endif /* _SAME54_I2S_COMPONENT_ */
|