Kévin Redon | 4cd3f7d | 2019-01-24 17:57:13 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SPI related functionality declaration. |
| 5 | * |
| 6 | * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifndef _HPL_SPI_S_SYNC_H_INCLUDED |
| 35 | #define _HPL_SPI_S_SYNC_H_INCLUDED |
| 36 | |
| 37 | #include <hpl_spi_sync.h> |
| 38 | |
| 39 | /** |
| 40 | * \addtogroup hpl_spi HPL SPI |
| 41 | * |
| 42 | *@{ |
| 43 | */ |
| 44 | |
| 45 | #ifdef __cplusplus |
| 46 | extern "C" { |
| 47 | #endif |
| 48 | |
| 49 | /** Uses common SPI async device driver. */ |
| 50 | #define _spi_s_sync_dev _spi_sync_dev |
| 51 | |
| 52 | /** |
| 53 | * \brief Initialize SPI for access without interrupts |
| 54 | * It will load default hardware configuration and software struct. |
| 55 | * \param[in, out] dev Pointer to the SPI device instance. |
| 56 | * \param[in] hw Pointer to the hardware base. |
| 57 | * \return Operation status. |
| 58 | * \retval ERR_INVALID_ARG Input parameter problem. |
| 59 | * \retval ERR_BUSY SPI hardware not ready (resetting). |
| 60 | * \retval ERR_DENIED SPI has been enabled. |
| 61 | * \retval 0 Operation done successfully. |
| 62 | */ |
| 63 | int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw); |
| 64 | |
| 65 | /** |
| 66 | * \brief Initialize SPI for access with interrupts |
| 67 | * Disable, reset the hardware and the software struct. |
| 68 | * \param[in, out] dev Pointer to the SPI device instance. |
| 69 | * \return Operation status. |
| 70 | * \retval 0 Operation done successfully. |
| 71 | */ |
| 72 | int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev); |
| 73 | |
| 74 | /** |
| 75 | * \brief Enable SPI for access without interrupts |
| 76 | * \param[in, out] dev Pointer to the SPI device instance. |
| 77 | * \return Operation status. |
| 78 | * \retval ERR_BUSY SPI hardware not ready (resetting). |
| 79 | * \retval 0 Operation done successfully. |
| 80 | */ |
| 81 | int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev); |
| 82 | |
| 83 | /** |
| 84 | * \brief Disable SPI for access without interrupts |
| 85 | * Disable SPI. Deactivate all CS pins if works as master. |
| 86 | * \param[in, out] dev Pointer to the SPI device instance. |
| 87 | * \return Operation status. |
| 88 | * \retval 0 Operation done successfully. |
| 89 | */ |
| 90 | int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev); |
| 91 | |
| 92 | /** |
| 93 | * \brief Set SPI transfer mode |
| 94 | * Set SPI transfer mode (\ref spi_transfer_mode), |
| 95 | * which controls clock polarity and clock phase. |
| 96 | * Mode 0: leading edge is rising edge, data sample on leading edge. |
| 97 | * Mode 1: leading edge is rising edge, data sample on trailing edge. |
| 98 | * Mode 2: leading edge is falling edge, data sample on leading edge. |
| 99 | * Mode 3: leading edge is falling edge, data sample on trailing edge. |
| 100 | * \param[in, out] dev Pointer to the SPI device instance. |
| 101 | * \param[in] mode The SPI transfer mode. |
| 102 | * \return Operation status. |
| 103 | * \retval ERR_BUSY SPI is not ready to accept new setting. |
| 104 | * \retval 0 Operation done successfully. |
| 105 | */ |
| 106 | int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode); |
| 107 | |
| 108 | /** |
| 109 | * \brief Set SPI baudrate |
| 110 | * \param[in, out] dev Pointer to the SPI device instance. |
| 111 | * \param[in] char_size The character size, see \ref spi_char_size. |
| 112 | * \return Operation status. |
| 113 | * \retval ERR_INVALID_ARG The character size is not supported. |
| 114 | * \retval ERR_BUSY SPI is not ready to accept new setting. |
| 115 | * \retval 0 Operation done successfully. |
| 116 | */ |
| 117 | int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size); |
| 118 | |
| 119 | /** |
| 120 | * \brief Set SPI data order |
| 121 | * \param[in, out] dev Pointer to the SPI device instance. |
| 122 | * \param[in] dord SPI data order (LSB/MSB first). |
| 123 | * \return Operation status. |
| 124 | * \retval ERR_INVALID_ARG The character size is not supported. |
| 125 | * \retval ERR_BUSY SPI is not ready to accept new setting. |
| 126 | * \retval 0 Operation done successfully. |
| 127 | */ |
| 128 | int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord); |
| 129 | |
| 130 | /** |
| 131 | * \brief Enable interrupt on character output |
| 132 | * |
| 133 | * Enable interrupt when a new character can be written |
| 134 | * to the SPI device. |
| 135 | * |
| 136 | * \param[in] dev Pointer to the SPI device instance |
| 137 | * \param[in] state true = enable output interrupt |
| 138 | * false = disable output interrupt |
| 139 | * |
| 140 | * \return Status code |
| 141 | * \retval 0 Ok status |
| 142 | */ |
| 143 | int32_t _spi_s_sync_enable_tx(struct _spi_s_sync_dev *dev, bool state); |
| 144 | |
| 145 | /** |
| 146 | * \brief Enable interrupt on character input |
| 147 | * |
| 148 | * Enable interrupt when a new character is ready to be |
| 149 | * read from the SPI device. |
| 150 | * |
| 151 | * \param[in] dev Pointer to the SPI device instance |
| 152 | * \param[in] state true = enable input interrupts |
| 153 | * false = disable input interrupt |
| 154 | * |
| 155 | * \return Status code |
| 156 | * \retval 0 OK Status |
| 157 | */ |
| 158 | int32_t _spi_s_sync_enable_rx(struct _spi_s_sync_dev *dev, bool state); |
| 159 | |
| 160 | /** |
| 161 | * \brief Read one character to SPI device instance |
| 162 | * \param[in, out] dev Pointer to the SPI device instance. |
| 163 | * |
| 164 | * \return Character read from SPI module |
| 165 | */ |
| 166 | uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev); |
| 167 | |
| 168 | /** |
| 169 | * \brief Write one character to assigned buffer |
| 170 | * \param[in, out] dev Pointer to the SPI device instance. |
| 171 | * \param[in] data |
| 172 | * |
| 173 | * \return Status code of write operation |
| 174 | * \retval 0 Write operation OK |
| 175 | */ |
| 176 | int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data); |
| 177 | |
| 178 | /** |
| 179 | * \brief Check if TX ready |
| 180 | * |
| 181 | * \param[in] dev Pointer to the SPI device instance |
| 182 | * |
| 183 | * \return TX ready state |
| 184 | * \retval true TX ready |
| 185 | * \retval false TX not ready |
| 186 | */ |
| 187 | bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev); |
| 188 | |
| 189 | /** |
| 190 | * \brief Check if RX character ready |
| 191 | * |
| 192 | * \param[in] dev Pointer to the SPI device instance |
| 193 | * |
| 194 | * \return RX character ready state |
| 195 | * \retval true RX character ready |
| 196 | * \retval false RX character not ready |
| 197 | */ |
| 198 | bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev); |
| 199 | |
| 200 | /** |
| 201 | * \brief Check if SS deactiviation detected |
| 202 | * |
| 203 | * \param[in] dev Pointer to the SPI device instance |
| 204 | * |
| 205 | * \return SS deactiviation state |
| 206 | * \retval true SS deactiviation detected |
| 207 | * \retval false SS deactiviation not detected |
| 208 | */ |
| 209 | bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev); |
| 210 | |
| 211 | /** |
| 212 | * \brief Check if error is detected |
| 213 | * |
| 214 | * \param[in] dev Pointer to the SPI device instance |
| 215 | * |
| 216 | * \return Error detection state |
| 217 | * \retval true Error detected |
| 218 | * \retval false Error not detected |
| 219 | */ |
| 220 | bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev); |
| 221 | |
| 222 | #ifdef __cplusplus |
| 223 | } |
| 224 | #endif |
| 225 | |
| 226 | /**@}*/ |
| 227 | #endif /* ifndef _HPL_SPI_S_SYNC_H_INCLUDED */ |