blob: 01e8fc30d8fe1a4bc8098f580c63df5bc3e4ca4b [file] [log] [blame]
Kévin Redon4cd3f7d2019-01-24 17:57:13 +01001/**
2 * \file
3 *
4 * \brief SPI related functionality declaration.
5 *
6 * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Subject to your compliance with these terms, you may use Microchip
13 * software and any derivatives exclusively with Microchip products.
14 * It is your responsibility to comply with third party license terms applicable
15 * to your use of third party software (including open source software) that
16 * may accompany Microchip software.
17 *
18 * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
19 * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
20 * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
21 * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
22 * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
23 * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
24 * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
25 * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
26 * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
27 * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
28 * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
29 *
30 * \asf_license_stop
31 *
32 */
33
34#ifndef _HPL_SPI_M_SYNC_H_INCLUDED
35#define _HPL_SPI_M_SYNC_H_INCLUDED
36
37#include <hpl_spi.h>
38#include <hpl_spi_sync.h>
39
40/**
41 * \addtogroup hpl_spi HPL SPI
42 *
43 *@{
44 */
45
46#ifdef __cplusplus
47extern "C" {
48#endif
49
50/** Uses common SPI async device driver. */
51#define _spi_m_sync_dev _spi_sync_dev
52
53/**
54 * \brief Initialize SPI for access without interrupts
55 * It will load default hardware configuration and software struct.
56 * \param[in, out] dev Pointer to the SPI device instance.
57 * \param[in] hw Pointer to the hardware base.
58 * \return Operation status.
59 * \retval ERR_INVALID_ARG Input parameter problem.
60 * \retval ERR_BUSY SPI hardware not ready (resetting).
61 * \retval ERR_DENIED SPI has been enabled.
62 * \retval 0 Operation done successfully.
63 */
64int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw);
65
66/**
67 * \brief Deinitialize SPI
68 * Disable, reset the hardware and the software struct.
69 * \param[in, out] dev Pointer to the SPI device instance.
70 * \return Operation status.
71 * \retval 0 Operation done successfully.
72 */
73int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev);
74
75/**
76 * \brief Enable SPI for access without interrupts
77 * \param[in, out] dev Pointer to the SPI device instance.
78 * \return Operation status.
79 * \retval ERR_BUSY SPI hardware not ready (resetting).
80 * \retval 0 Operation done successfully.
81 */
82int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev);
83
84/**
85 * \brief Disable SPI for access without interrupts
86 * Disable SPI. Deactivate all CS pins if works as master.
87 * \param[in, out] dev Pointer to the SPI device instance.
88 * \return Operation status.
89 * \retval 0 Operation done successfully.
90 */
91int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev);
92
93/**
94 * \brief Set SPI transfer mode
95 * Set SPI transfer mode (\ref spi_transfer_mode),
96 * which controls clock polarity and clock phase.
97 * Mode 0: leading edge is rising edge, data sample on leading edge.
98 * Mode 1: leading edge is rising edge, data sample on trailing edge.
99 * Mode 2: leading edge is falling edge, data sample on leading edge.
100 * Mode 3: leading edge is falling edge, data sample on trailing edge.
101 * \param[in, out] dev Pointer to the SPI device instance.
102 * \param[in] mode The SPI transfer mode.
103 * \return Operation status.
104 * \retval ERR_BUSY SPI is not ready to accept new setting.
105 * \retval 0 Operation done successfully.
106 */
107int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode);
108
109/**
110 * \brief Set SPI baudrate
111 * \param[in, out] dev Pointer to the SPI device instance.
112 * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on
113 * how it's generated.
114 * \return Operation status.
115 * \retval ERR_BUSY SPI is not ready to accept new setting.
116 * \retval 0 Operation done successfully.
117 */
118int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val);
119
120/**
121 * \brief Set SPI baudrate
122 * \param[in, out] dev Pointer to the SPI device instance.
123 * \param[in] char_size The character size, see \ref spi_char_size.
124 * \return Operation status.
125 * \retval ERR_INVALID_ARG The character size is not supported.
126 * \retval ERR_BUSY SPI is not ready to accept new setting.
127 * \retval 0 Operation done successfully.
128 */
129int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size);
130
131/**
132 * \brief Set SPI data order
133 * \param[in, out] dev Pointer to the SPI device instance.
134 * \param[in] dord SPI data order (LSB/MSB first).
135 * \return Operation status.
136 * \retval ERR_INVALID_ARG The character size is not supported.
137 * \retval ERR_BUSY SPI is not ready to accept new setting.
138 * \retval 0 Operation done successfully.
139 */
140int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord);
141
142/**
143 * \brief Transfer the whole message without interrupt
144 * Transfer the message, it will keep waiting until the message finish or
145 * error.
146 * \param[in, out] dev Pointer to the SPI device instance.
147 * \param[in] msg Pointer to the message instance to process.
148 * \return Error or number of characters transferred.
149 * \retval ERR_BUSY SPI hardware is not ready to start transfer (not
150 * enabled, busy applying settings, ...).
151 * \retval SPI_ERR_OVERFLOW Overflow error.
152 * \retval >=0 Number of characters transferred.
153 */
154int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg);
155
156#ifdef __cplusplus
157}
158#endif
159
160/**@}*/
161#endif /* ifndef _HPL_SPI_M_SYNC_H_INCLUDED */