Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM TC |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_TC_COMPONENT_ |
| 35 | #ifndef _HRI_TC_E54_H_INCLUDED_ |
| 36 | #define _HRI_TC_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_TC_CRITICAL_SECTIONS) |
| 46 | #define TC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define TC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define TC_CRITICAL_SECTION_ENTER() |
| 50 | #define TC_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint16_t hri_tc_evctrl_reg_t; |
| 54 | typedef uint16_t hri_tccount16_cc_reg_t; |
| 55 | typedef uint16_t hri_tccount16_ccbuf_reg_t; |
| 56 | typedef uint16_t hri_tccount16_count_reg_t; |
| 57 | typedef uint32_t hri_tc_ctrla_reg_t; |
| 58 | typedef uint32_t hri_tc_syncbusy_reg_t; |
| 59 | typedef uint32_t hri_tccount32_cc_reg_t; |
| 60 | typedef uint32_t hri_tccount32_ccbuf_reg_t; |
| 61 | typedef uint32_t hri_tccount32_count_reg_t; |
| 62 | typedef uint8_t hri_tc_ctrlbset_reg_t; |
| 63 | typedef uint8_t hri_tc_dbgctrl_reg_t; |
| 64 | typedef uint8_t hri_tc_drvctrl_reg_t; |
| 65 | typedef uint8_t hri_tc_intenset_reg_t; |
| 66 | typedef uint8_t hri_tc_intflag_reg_t; |
| 67 | typedef uint8_t hri_tc_status_reg_t; |
| 68 | typedef uint8_t hri_tc_wave_reg_t; |
| 69 | typedef uint8_t hri_tccount8_cc_reg_t; |
| 70 | typedef uint8_t hri_tccount8_ccbuf_reg_t; |
| 71 | typedef uint8_t hri_tccount8_count_reg_t; |
| 72 | typedef uint8_t hri_tccount8_per_reg_t; |
| 73 | typedef uint8_t hri_tccount8_perbuf_reg_t; |
| 74 | |
| 75 | static inline void hri_tc_wait_for_sync(const void *const hw, hri_tc_syncbusy_reg_t reg) |
| 76 | { |
| 77 | while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) { |
| 78 | }; |
| 79 | } |
| 80 | |
| 81 | static inline bool hri_tc_is_syncing(const void *const hw, hri_tc_syncbusy_reg_t reg) |
| 82 | { |
| 83 | return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg; |
| 84 | } |
| 85 | |
| 86 | static inline bool hri_tc_get_INTFLAG_OVF_bit(const void *const hw) |
| 87 | { |
| 88 | return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; |
| 89 | } |
| 90 | |
| 91 | static inline void hri_tc_clear_INTFLAG_OVF_bit(const void *const hw) |
| 92 | { |
| 93 | ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; |
| 94 | } |
| 95 | |
| 96 | static inline bool hri_tc_get_INTFLAG_ERR_bit(const void *const hw) |
| 97 | { |
| 98 | return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; |
| 99 | } |
| 100 | |
| 101 | static inline void hri_tc_clear_INTFLAG_ERR_bit(const void *const hw) |
| 102 | { |
| 103 | ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR; |
| 104 | } |
| 105 | |
| 106 | static inline bool hri_tc_get_INTFLAG_MC0_bit(const void *const hw) |
| 107 | { |
| 108 | return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; |
| 109 | } |
| 110 | |
| 111 | static inline void hri_tc_clear_INTFLAG_MC0_bit(const void *const hw) |
| 112 | { |
| 113 | ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0; |
| 114 | } |
| 115 | |
| 116 | static inline bool hri_tc_get_INTFLAG_MC1_bit(const void *const hw) |
| 117 | { |
| 118 | return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; |
| 119 | } |
| 120 | |
| 121 | static inline void hri_tc_clear_INTFLAG_MC1_bit(const void *const hw) |
| 122 | { |
| 123 | ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1; |
| 124 | } |
| 125 | |
| 126 | static inline bool hri_tc_get_interrupt_OVF_bit(const void *const hw) |
| 127 | { |
| 128 | return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; |
| 129 | } |
| 130 | |
| 131 | static inline void hri_tc_clear_interrupt_OVF_bit(const void *const hw) |
| 132 | { |
| 133 | ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; |
| 134 | } |
| 135 | |
| 136 | static inline bool hri_tc_get_interrupt_ERR_bit(const void *const hw) |
| 137 | { |
| 138 | return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; |
| 139 | } |
| 140 | |
| 141 | static inline void hri_tc_clear_interrupt_ERR_bit(const void *const hw) |
| 142 | { |
| 143 | ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR; |
| 144 | } |
| 145 | |
| 146 | static inline bool hri_tc_get_interrupt_MC0_bit(const void *const hw) |
| 147 | { |
| 148 | return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; |
| 149 | } |
| 150 | |
| 151 | static inline void hri_tc_clear_interrupt_MC0_bit(const void *const hw) |
| 152 | { |
| 153 | ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0; |
| 154 | } |
| 155 | |
| 156 | static inline bool hri_tc_get_interrupt_MC1_bit(const void *const hw) |
| 157 | { |
| 158 | return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; |
| 159 | } |
| 160 | |
| 161 | static inline void hri_tc_clear_interrupt_MC1_bit(const void *const hw) |
| 162 | { |
| 163 | ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1; |
| 164 | } |
| 165 | |
| 166 | static inline hri_tc_intflag_reg_t hri_tc_get_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) |
| 167 | { |
| 168 | uint8_t tmp; |
| 169 | tmp = ((Tc *)hw)->COUNT16.INTFLAG.reg; |
| 170 | tmp &= mask; |
| 171 | return tmp; |
| 172 | } |
| 173 | |
| 174 | static inline hri_tc_intflag_reg_t hri_tc_read_INTFLAG_reg(const void *const hw) |
| 175 | { |
| 176 | return ((Tc *)hw)->COUNT16.INTFLAG.reg; |
| 177 | } |
| 178 | |
| 179 | static inline void hri_tc_clear_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) |
| 180 | { |
| 181 | ((Tc *)hw)->COUNT16.INTFLAG.reg = mask; |
| 182 | } |
| 183 | |
| 184 | static inline void hri_tc_set_CTRLB_DIR_bit(const void *const hw) |
| 185 | { |
| 186 | ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR; |
| 187 | } |
| 188 | |
| 189 | static inline bool hri_tc_get_CTRLB_DIR_bit(const void *const hw) |
| 190 | { |
| 191 | return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_DIR) >> TC_CTRLBSET_DIR_Pos; |
| 192 | } |
| 193 | |
| 194 | static inline void hri_tc_write_CTRLB_DIR_bit(const void *const hw, bool value) |
| 195 | { |
| 196 | if (value == 0x0) { |
| 197 | ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR; |
| 198 | } else { |
| 199 | ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR; |
| 200 | } |
| 201 | } |
| 202 | |
| 203 | static inline void hri_tc_clear_CTRLB_DIR_bit(const void *const hw) |
| 204 | { |
| 205 | ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR; |
| 206 | } |
| 207 | |
| 208 | static inline void hri_tc_set_CTRLB_LUPD_bit(const void *const hw) |
| 209 | { |
| 210 | ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD; |
| 211 | } |
| 212 | |
| 213 | static inline bool hri_tc_get_CTRLB_LUPD_bit(const void *const hw) |
| 214 | { |
| 215 | return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_LUPD) >> TC_CTRLBSET_LUPD_Pos; |
| 216 | } |
| 217 | |
| 218 | static inline void hri_tc_write_CTRLB_LUPD_bit(const void *const hw, bool value) |
| 219 | { |
| 220 | if (value == 0x0) { |
| 221 | ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD; |
| 222 | } else { |
| 223 | ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD; |
| 224 | } |
| 225 | } |
| 226 | |
| 227 | static inline void hri_tc_clear_CTRLB_LUPD_bit(const void *const hw) |
| 228 | { |
| 229 | ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD; |
| 230 | } |
| 231 | |
| 232 | static inline void hri_tc_set_CTRLB_ONESHOT_bit(const void *const hw) |
| 233 | { |
| 234 | ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; |
| 235 | } |
| 236 | |
| 237 | static inline bool hri_tc_get_CTRLB_ONESHOT_bit(const void *const hw) |
| 238 | { |
| 239 | return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_ONESHOT) >> TC_CTRLBSET_ONESHOT_Pos; |
| 240 | } |
| 241 | |
| 242 | static inline void hri_tc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) |
| 243 | { |
| 244 | if (value == 0x0) { |
| 245 | ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; |
| 246 | } else { |
| 247 | ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; |
| 248 | } |
| 249 | } |
| 250 | |
| 251 | static inline void hri_tc_clear_CTRLB_ONESHOT_bit(const void *const hw) |
| 252 | { |
| 253 | ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; |
| 254 | } |
| 255 | |
| 256 | static inline void hri_tc_set_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) |
| 257 | { |
| 258 | ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(mask); |
| 259 | } |
| 260 | |
| 261 | static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) |
| 262 | { |
| 263 | uint8_t tmp; |
| 264 | tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; |
| 265 | tmp = (tmp & TC_CTRLBSET_CMD(mask)) >> TC_CTRLBSET_CMD_Pos; |
| 266 | return tmp; |
| 267 | } |
| 268 | |
| 269 | static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_CMD_bf(const void *const hw) |
| 270 | { |
| 271 | uint8_t tmp; |
| 272 | tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; |
| 273 | tmp = (tmp & TC_CTRLBSET_CMD_Msk) >> TC_CTRLBSET_CMD_Pos; |
| 274 | return tmp; |
| 275 | } |
| 276 | |
| 277 | static inline void hri_tc_write_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t data) |
| 278 | { |
| 279 | ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(data); |
| 280 | ((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~TC_CTRLBSET_CMD(data); |
| 281 | } |
| 282 | |
| 283 | static inline void hri_tc_clear_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) |
| 284 | { |
| 285 | ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_CMD(mask); |
| 286 | } |
| 287 | |
| 288 | static inline void hri_tc_set_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) |
| 289 | { |
| 290 | ((Tc *)hw)->COUNT16.CTRLBSET.reg = mask; |
| 291 | } |
| 292 | |
| 293 | static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) |
| 294 | { |
| 295 | uint8_t tmp; |
| 296 | tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; |
| 297 | tmp &= mask; |
| 298 | return tmp; |
| 299 | } |
| 300 | |
| 301 | static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_reg(const void *const hw) |
| 302 | { |
| 303 | return ((Tc *)hw)->COUNT16.CTRLBSET.reg; |
| 304 | } |
| 305 | |
| 306 | static inline void hri_tc_write_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t data) |
| 307 | { |
| 308 | ((Tc *)hw)->COUNT16.CTRLBSET.reg = data; |
| 309 | ((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~data; |
| 310 | } |
| 311 | |
| 312 | static inline void hri_tc_clear_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) |
| 313 | { |
| 314 | ((Tc *)hw)->COUNT16.CTRLBCLR.reg = mask; |
| 315 | } |
| 316 | |
| 317 | static inline void hri_tc_set_INTEN_OVF_bit(const void *const hw) |
| 318 | { |
| 319 | ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; |
| 320 | } |
| 321 | |
| 322 | static inline bool hri_tc_get_INTEN_OVF_bit(const void *const hw) |
| 323 | { |
| 324 | return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_OVF) >> TC_INTENSET_OVF_Pos; |
| 325 | } |
| 326 | |
| 327 | static inline void hri_tc_write_INTEN_OVF_bit(const void *const hw, bool value) |
| 328 | { |
| 329 | if (value == 0x0) { |
| 330 | ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF; |
| 331 | } else { |
| 332 | ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; |
| 333 | } |
| 334 | } |
| 335 | |
| 336 | static inline void hri_tc_clear_INTEN_OVF_bit(const void *const hw) |
| 337 | { |
| 338 | ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF; |
| 339 | } |
| 340 | |
| 341 | static inline void hri_tc_set_INTEN_ERR_bit(const void *const hw) |
| 342 | { |
| 343 | ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR; |
| 344 | } |
| 345 | |
| 346 | static inline bool hri_tc_get_INTEN_ERR_bit(const void *const hw) |
| 347 | { |
| 348 | return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_ERR) >> TC_INTENSET_ERR_Pos; |
| 349 | } |
| 350 | |
| 351 | static inline void hri_tc_write_INTEN_ERR_bit(const void *const hw, bool value) |
| 352 | { |
| 353 | if (value == 0x0) { |
| 354 | ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR; |
| 355 | } else { |
| 356 | ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR; |
| 357 | } |
| 358 | } |
| 359 | |
| 360 | static inline void hri_tc_clear_INTEN_ERR_bit(const void *const hw) |
| 361 | { |
| 362 | ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR; |
| 363 | } |
| 364 | |
| 365 | static inline void hri_tc_set_INTEN_MC0_bit(const void *const hw) |
| 366 | { |
| 367 | ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0; |
| 368 | } |
| 369 | |
| 370 | static inline bool hri_tc_get_INTEN_MC0_bit(const void *const hw) |
| 371 | { |
| 372 | return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC0) >> TC_INTENSET_MC0_Pos; |
| 373 | } |
| 374 | |
| 375 | static inline void hri_tc_write_INTEN_MC0_bit(const void *const hw, bool value) |
| 376 | { |
| 377 | if (value == 0x0) { |
| 378 | ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0; |
| 379 | } else { |
| 380 | ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0; |
| 381 | } |
| 382 | } |
| 383 | |
| 384 | static inline void hri_tc_clear_INTEN_MC0_bit(const void *const hw) |
| 385 | { |
| 386 | ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0; |
| 387 | } |
| 388 | |
| 389 | static inline void hri_tc_set_INTEN_MC1_bit(const void *const hw) |
| 390 | { |
| 391 | ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1; |
| 392 | } |
| 393 | |
| 394 | static inline bool hri_tc_get_INTEN_MC1_bit(const void *const hw) |
| 395 | { |
| 396 | return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC1) >> TC_INTENSET_MC1_Pos; |
| 397 | } |
| 398 | |
| 399 | static inline void hri_tc_write_INTEN_MC1_bit(const void *const hw, bool value) |
| 400 | { |
| 401 | if (value == 0x0) { |
| 402 | ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1; |
| 403 | } else { |
| 404 | ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1; |
| 405 | } |
| 406 | } |
| 407 | |
| 408 | static inline void hri_tc_clear_INTEN_MC1_bit(const void *const hw) |
| 409 | { |
| 410 | ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1; |
| 411 | } |
| 412 | |
| 413 | static inline void hri_tc_set_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) |
| 414 | { |
| 415 | ((Tc *)hw)->COUNT16.INTENSET.reg = mask; |
| 416 | } |
| 417 | |
| 418 | static inline hri_tc_intenset_reg_t hri_tc_get_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) |
| 419 | { |
| 420 | uint8_t tmp; |
| 421 | tmp = ((Tc *)hw)->COUNT16.INTENSET.reg; |
| 422 | tmp &= mask; |
| 423 | return tmp; |
| 424 | } |
| 425 | |
| 426 | static inline hri_tc_intenset_reg_t hri_tc_read_INTEN_reg(const void *const hw) |
| 427 | { |
| 428 | return ((Tc *)hw)->COUNT16.INTENSET.reg; |
| 429 | } |
| 430 | |
| 431 | static inline void hri_tc_write_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t data) |
| 432 | { |
| 433 | ((Tc *)hw)->COUNT16.INTENSET.reg = data; |
| 434 | ((Tc *)hw)->COUNT16.INTENCLR.reg = ~data; |
| 435 | } |
| 436 | |
| 437 | static inline void hri_tc_clear_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) |
| 438 | { |
| 439 | ((Tc *)hw)->COUNT16.INTENCLR.reg = mask; |
| 440 | } |
| 441 | |
| 442 | static inline bool hri_tc_get_SYNCBUSY_SWRST_bit(const void *const hw) |
| 443 | { |
| 444 | return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_SWRST) >> TC_SYNCBUSY_SWRST_Pos; |
| 445 | } |
| 446 | |
| 447 | static inline bool hri_tc_get_SYNCBUSY_ENABLE_bit(const void *const hw) |
| 448 | { |
| 449 | return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_ENABLE) >> TC_SYNCBUSY_ENABLE_Pos; |
| 450 | } |
| 451 | |
| 452 | static inline bool hri_tc_get_SYNCBUSY_CTRLB_bit(const void *const hw) |
| 453 | { |
| 454 | return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CTRLB) >> TC_SYNCBUSY_CTRLB_Pos; |
| 455 | } |
| 456 | |
| 457 | static inline bool hri_tc_get_SYNCBUSY_STATUS_bit(const void *const hw) |
| 458 | { |
| 459 | return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_STATUS) >> TC_SYNCBUSY_STATUS_Pos; |
| 460 | } |
| 461 | |
| 462 | static inline bool hri_tc_get_SYNCBUSY_COUNT_bit(const void *const hw) |
| 463 | { |
| 464 | return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_COUNT) >> TC_SYNCBUSY_COUNT_Pos; |
| 465 | } |
| 466 | |
| 467 | static inline bool hri_tc_get_SYNCBUSY_PER_bit(const void *const hw) |
| 468 | { |
| 469 | return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_PER) >> TC_SYNCBUSY_PER_Pos; |
| 470 | } |
| 471 | |
| 472 | static inline bool hri_tc_get_SYNCBUSY_CC0_bit(const void *const hw) |
| 473 | { |
| 474 | return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC0) >> TC_SYNCBUSY_CC0_Pos; |
| 475 | } |
| 476 | |
| 477 | static inline bool hri_tc_get_SYNCBUSY_CC1_bit(const void *const hw) |
| 478 | { |
| 479 | return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC1) >> TC_SYNCBUSY_CC1_Pos; |
| 480 | } |
| 481 | |
| 482 | static inline hri_tc_syncbusy_reg_t hri_tc_get_SYNCBUSY_reg(const void *const hw, hri_tc_syncbusy_reg_t mask) |
| 483 | { |
| 484 | uint32_t tmp; |
| 485 | tmp = ((Tc *)hw)->COUNT16.SYNCBUSY.reg; |
| 486 | tmp &= mask; |
| 487 | return tmp; |
| 488 | } |
| 489 | |
| 490 | static inline hri_tc_syncbusy_reg_t hri_tc_read_SYNCBUSY_reg(const void *const hw) |
| 491 | { |
| 492 | return ((Tc *)hw)->COUNT16.SYNCBUSY.reg; |
| 493 | } |
| 494 | |
| 495 | static inline void hri_tc_set_CTRLA_SWRST_bit(const void *const hw) |
| 496 | { |
| 497 | TC_CRITICAL_SECTION_ENTER(); |
| 498 | ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_SWRST; |
| 499 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); |
| 500 | TC_CRITICAL_SECTION_LEAVE(); |
| 501 | } |
| 502 | |
| 503 | static inline bool hri_tc_get_CTRLA_SWRST_bit(const void *const hw) |
| 504 | { |
| 505 | uint32_t tmp; |
| 506 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); |
| 507 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 508 | tmp = (tmp & TC_CTRLA_SWRST) >> TC_CTRLA_SWRST_Pos; |
| 509 | return (bool)tmp; |
| 510 | } |
| 511 | |
| 512 | static inline void hri_tc_set_CTRLA_ENABLE_bit(const void *const hw) |
| 513 | { |
| 514 | TC_CRITICAL_SECTION_ENTER(); |
| 515 | ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE; |
| 516 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); |
| 517 | TC_CRITICAL_SECTION_LEAVE(); |
| 518 | } |
| 519 | |
| 520 | static inline bool hri_tc_get_CTRLA_ENABLE_bit(const void *const hw) |
| 521 | { |
| 522 | uint32_t tmp; |
| 523 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); |
| 524 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 525 | tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos; |
| 526 | return (bool)tmp; |
| 527 | } |
| 528 | |
| 529 | static inline void hri_tc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) |
| 530 | { |
| 531 | uint32_t tmp; |
| 532 | TC_CRITICAL_SECTION_ENTER(); |
| 533 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 534 | tmp &= ~TC_CTRLA_ENABLE; |
| 535 | tmp |= value << TC_CTRLA_ENABLE_Pos; |
| 536 | ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; |
| 537 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); |
| 538 | TC_CRITICAL_SECTION_LEAVE(); |
| 539 | } |
| 540 | |
| 541 | static inline void hri_tc_clear_CTRLA_ENABLE_bit(const void *const hw) |
| 542 | { |
| 543 | TC_CRITICAL_SECTION_ENTER(); |
| 544 | ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE; |
| 545 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); |
| 546 | TC_CRITICAL_SECTION_LEAVE(); |
| 547 | } |
| 548 | |
| 549 | static inline void hri_tc_toggle_CTRLA_ENABLE_bit(const void *const hw) |
| 550 | { |
| 551 | TC_CRITICAL_SECTION_ENTER(); |
| 552 | ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ENABLE; |
| 553 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); |
| 554 | TC_CRITICAL_SECTION_LEAVE(); |
| 555 | } |
| 556 | |
| 557 | static inline void hri_tc_set_CTRLA_RUNSTDBY_bit(const void *const hw) |
| 558 | { |
| 559 | TC_CRITICAL_SECTION_ENTER(); |
| 560 | ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_RUNSTDBY; |
| 561 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 562 | TC_CRITICAL_SECTION_LEAVE(); |
| 563 | } |
| 564 | |
| 565 | static inline bool hri_tc_get_CTRLA_RUNSTDBY_bit(const void *const hw) |
| 566 | { |
| 567 | uint32_t tmp; |
| 568 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 569 | tmp = (tmp & TC_CTRLA_RUNSTDBY) >> TC_CTRLA_RUNSTDBY_Pos; |
| 570 | return (bool)tmp; |
| 571 | } |
| 572 | |
| 573 | static inline void hri_tc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) |
| 574 | { |
| 575 | uint32_t tmp; |
| 576 | TC_CRITICAL_SECTION_ENTER(); |
| 577 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 578 | tmp &= ~TC_CTRLA_RUNSTDBY; |
| 579 | tmp |= value << TC_CTRLA_RUNSTDBY_Pos; |
| 580 | ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; |
| 581 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 582 | TC_CRITICAL_SECTION_LEAVE(); |
| 583 | } |
| 584 | |
| 585 | static inline void hri_tc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) |
| 586 | { |
| 587 | TC_CRITICAL_SECTION_ENTER(); |
| 588 | ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_RUNSTDBY; |
| 589 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 590 | TC_CRITICAL_SECTION_LEAVE(); |
| 591 | } |
| 592 | |
| 593 | static inline void hri_tc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) |
| 594 | { |
| 595 | TC_CRITICAL_SECTION_ENTER(); |
| 596 | ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_RUNSTDBY; |
| 597 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 598 | TC_CRITICAL_SECTION_LEAVE(); |
| 599 | } |
| 600 | |
| 601 | static inline void hri_tc_set_CTRLA_ONDEMAND_bit(const void *const hw) |
| 602 | { |
| 603 | TC_CRITICAL_SECTION_ENTER(); |
| 604 | ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ONDEMAND; |
| 605 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 606 | TC_CRITICAL_SECTION_LEAVE(); |
| 607 | } |
| 608 | |
| 609 | static inline bool hri_tc_get_CTRLA_ONDEMAND_bit(const void *const hw) |
| 610 | { |
| 611 | uint32_t tmp; |
| 612 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 613 | tmp = (tmp & TC_CTRLA_ONDEMAND) >> TC_CTRLA_ONDEMAND_Pos; |
| 614 | return (bool)tmp; |
| 615 | } |
| 616 | |
| 617 | static inline void hri_tc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) |
| 618 | { |
| 619 | uint32_t tmp; |
| 620 | TC_CRITICAL_SECTION_ENTER(); |
| 621 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 622 | tmp &= ~TC_CTRLA_ONDEMAND; |
| 623 | tmp |= value << TC_CTRLA_ONDEMAND_Pos; |
| 624 | ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; |
| 625 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 626 | TC_CRITICAL_SECTION_LEAVE(); |
| 627 | } |
| 628 | |
| 629 | static inline void hri_tc_clear_CTRLA_ONDEMAND_bit(const void *const hw) |
| 630 | { |
| 631 | TC_CRITICAL_SECTION_ENTER(); |
| 632 | ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ONDEMAND; |
| 633 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 634 | TC_CRITICAL_SECTION_LEAVE(); |
| 635 | } |
| 636 | |
| 637 | static inline void hri_tc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) |
| 638 | { |
| 639 | TC_CRITICAL_SECTION_ENTER(); |
| 640 | ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ONDEMAND; |
| 641 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 642 | TC_CRITICAL_SECTION_LEAVE(); |
| 643 | } |
| 644 | |
| 645 | static inline void hri_tc_set_CTRLA_ALOCK_bit(const void *const hw) |
| 646 | { |
| 647 | TC_CRITICAL_SECTION_ENTER(); |
| 648 | ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ALOCK; |
| 649 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 650 | TC_CRITICAL_SECTION_LEAVE(); |
| 651 | } |
| 652 | |
| 653 | static inline bool hri_tc_get_CTRLA_ALOCK_bit(const void *const hw) |
| 654 | { |
| 655 | uint32_t tmp; |
| 656 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 657 | tmp = (tmp & TC_CTRLA_ALOCK) >> TC_CTRLA_ALOCK_Pos; |
| 658 | return (bool)tmp; |
| 659 | } |
| 660 | |
| 661 | static inline void hri_tc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) |
| 662 | { |
| 663 | uint32_t tmp; |
| 664 | TC_CRITICAL_SECTION_ENTER(); |
| 665 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 666 | tmp &= ~TC_CTRLA_ALOCK; |
| 667 | tmp |= value << TC_CTRLA_ALOCK_Pos; |
| 668 | ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; |
| 669 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 670 | TC_CRITICAL_SECTION_LEAVE(); |
| 671 | } |
| 672 | |
| 673 | static inline void hri_tc_clear_CTRLA_ALOCK_bit(const void *const hw) |
| 674 | { |
| 675 | TC_CRITICAL_SECTION_ENTER(); |
| 676 | ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ALOCK; |
| 677 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 678 | TC_CRITICAL_SECTION_LEAVE(); |
| 679 | } |
| 680 | |
| 681 | static inline void hri_tc_toggle_CTRLA_ALOCK_bit(const void *const hw) |
| 682 | { |
| 683 | TC_CRITICAL_SECTION_ENTER(); |
| 684 | ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ALOCK; |
| 685 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 686 | TC_CRITICAL_SECTION_LEAVE(); |
| 687 | } |
| 688 | |
| 689 | static inline void hri_tc_set_CTRLA_CAPTEN0_bit(const void *const hw) |
| 690 | { |
| 691 | TC_CRITICAL_SECTION_ENTER(); |
| 692 | ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN0; |
| 693 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 694 | TC_CRITICAL_SECTION_LEAVE(); |
| 695 | } |
| 696 | |
| 697 | static inline bool hri_tc_get_CTRLA_CAPTEN0_bit(const void *const hw) |
| 698 | { |
| 699 | uint32_t tmp; |
| 700 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 701 | tmp = (tmp & TC_CTRLA_CAPTEN0) >> TC_CTRLA_CAPTEN0_Pos; |
| 702 | return (bool)tmp; |
| 703 | } |
| 704 | |
| 705 | static inline void hri_tc_write_CTRLA_CAPTEN0_bit(const void *const hw, bool value) |
| 706 | { |
| 707 | uint32_t tmp; |
| 708 | TC_CRITICAL_SECTION_ENTER(); |
| 709 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 710 | tmp &= ~TC_CTRLA_CAPTEN0; |
| 711 | tmp |= value << TC_CTRLA_CAPTEN0_Pos; |
| 712 | ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; |
| 713 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 714 | TC_CRITICAL_SECTION_LEAVE(); |
| 715 | } |
| 716 | |
| 717 | static inline void hri_tc_clear_CTRLA_CAPTEN0_bit(const void *const hw) |
| 718 | { |
| 719 | TC_CRITICAL_SECTION_ENTER(); |
| 720 | ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN0; |
| 721 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 722 | TC_CRITICAL_SECTION_LEAVE(); |
| 723 | } |
| 724 | |
| 725 | static inline void hri_tc_toggle_CTRLA_CAPTEN0_bit(const void *const hw) |
| 726 | { |
| 727 | TC_CRITICAL_SECTION_ENTER(); |
| 728 | ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN0; |
| 729 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 730 | TC_CRITICAL_SECTION_LEAVE(); |
| 731 | } |
| 732 | |
| 733 | static inline void hri_tc_set_CTRLA_CAPTEN1_bit(const void *const hw) |
| 734 | { |
| 735 | TC_CRITICAL_SECTION_ENTER(); |
| 736 | ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN1; |
| 737 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 738 | TC_CRITICAL_SECTION_LEAVE(); |
| 739 | } |
| 740 | |
| 741 | static inline bool hri_tc_get_CTRLA_CAPTEN1_bit(const void *const hw) |
| 742 | { |
| 743 | uint32_t tmp; |
| 744 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 745 | tmp = (tmp & TC_CTRLA_CAPTEN1) >> TC_CTRLA_CAPTEN1_Pos; |
| 746 | return (bool)tmp; |
| 747 | } |
| 748 | |
| 749 | static inline void hri_tc_write_CTRLA_CAPTEN1_bit(const void *const hw, bool value) |
| 750 | { |
| 751 | uint32_t tmp; |
| 752 | TC_CRITICAL_SECTION_ENTER(); |
| 753 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 754 | tmp &= ~TC_CTRLA_CAPTEN1; |
| 755 | tmp |= value << TC_CTRLA_CAPTEN1_Pos; |
| 756 | ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; |
| 757 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 758 | TC_CRITICAL_SECTION_LEAVE(); |
| 759 | } |
| 760 | |
| 761 | static inline void hri_tc_clear_CTRLA_CAPTEN1_bit(const void *const hw) |
| 762 | { |
| 763 | TC_CRITICAL_SECTION_ENTER(); |
| 764 | ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN1; |
| 765 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 766 | TC_CRITICAL_SECTION_LEAVE(); |
| 767 | } |
| 768 | |
| 769 | static inline void hri_tc_toggle_CTRLA_CAPTEN1_bit(const void *const hw) |
| 770 | { |
| 771 | TC_CRITICAL_SECTION_ENTER(); |
| 772 | ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN1; |
| 773 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 774 | TC_CRITICAL_SECTION_LEAVE(); |
| 775 | } |
| 776 | |
| 777 | static inline void hri_tc_set_CTRLA_COPEN0_bit(const void *const hw) |
| 778 | { |
| 779 | TC_CRITICAL_SECTION_ENTER(); |
| 780 | ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN0; |
| 781 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 782 | TC_CRITICAL_SECTION_LEAVE(); |
| 783 | } |
| 784 | |
| 785 | static inline bool hri_tc_get_CTRLA_COPEN0_bit(const void *const hw) |
| 786 | { |
| 787 | uint32_t tmp; |
| 788 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 789 | tmp = (tmp & TC_CTRLA_COPEN0) >> TC_CTRLA_COPEN0_Pos; |
| 790 | return (bool)tmp; |
| 791 | } |
| 792 | |
| 793 | static inline void hri_tc_write_CTRLA_COPEN0_bit(const void *const hw, bool value) |
| 794 | { |
| 795 | uint32_t tmp; |
| 796 | TC_CRITICAL_SECTION_ENTER(); |
| 797 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 798 | tmp &= ~TC_CTRLA_COPEN0; |
| 799 | tmp |= value << TC_CTRLA_COPEN0_Pos; |
| 800 | ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; |
| 801 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 802 | TC_CRITICAL_SECTION_LEAVE(); |
| 803 | } |
| 804 | |
| 805 | static inline void hri_tc_clear_CTRLA_COPEN0_bit(const void *const hw) |
| 806 | { |
| 807 | TC_CRITICAL_SECTION_ENTER(); |
| 808 | ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN0; |
| 809 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 810 | TC_CRITICAL_SECTION_LEAVE(); |
| 811 | } |
| 812 | |
| 813 | static inline void hri_tc_toggle_CTRLA_COPEN0_bit(const void *const hw) |
| 814 | { |
| 815 | TC_CRITICAL_SECTION_ENTER(); |
| 816 | ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN0; |
| 817 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 818 | TC_CRITICAL_SECTION_LEAVE(); |
| 819 | } |
| 820 | |
| 821 | static inline void hri_tc_set_CTRLA_COPEN1_bit(const void *const hw) |
| 822 | { |
| 823 | TC_CRITICAL_SECTION_ENTER(); |
| 824 | ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN1; |
| 825 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 826 | TC_CRITICAL_SECTION_LEAVE(); |
| 827 | } |
| 828 | |
| 829 | static inline bool hri_tc_get_CTRLA_COPEN1_bit(const void *const hw) |
| 830 | { |
| 831 | uint32_t tmp; |
| 832 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 833 | tmp = (tmp & TC_CTRLA_COPEN1) >> TC_CTRLA_COPEN1_Pos; |
| 834 | return (bool)tmp; |
| 835 | } |
| 836 | |
| 837 | static inline void hri_tc_write_CTRLA_COPEN1_bit(const void *const hw, bool value) |
| 838 | { |
| 839 | uint32_t tmp; |
| 840 | TC_CRITICAL_SECTION_ENTER(); |
| 841 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 842 | tmp &= ~TC_CTRLA_COPEN1; |
| 843 | tmp |= value << TC_CTRLA_COPEN1_Pos; |
| 844 | ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; |
| 845 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 846 | TC_CRITICAL_SECTION_LEAVE(); |
| 847 | } |
| 848 | |
| 849 | static inline void hri_tc_clear_CTRLA_COPEN1_bit(const void *const hw) |
| 850 | { |
| 851 | TC_CRITICAL_SECTION_ENTER(); |
| 852 | ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN1; |
| 853 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 854 | TC_CRITICAL_SECTION_LEAVE(); |
| 855 | } |
| 856 | |
| 857 | static inline void hri_tc_toggle_CTRLA_COPEN1_bit(const void *const hw) |
| 858 | { |
| 859 | TC_CRITICAL_SECTION_ENTER(); |
| 860 | ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN1; |
| 861 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 862 | TC_CRITICAL_SECTION_LEAVE(); |
| 863 | } |
| 864 | |
| 865 | static inline void hri_tc_set_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) |
| 866 | { |
| 867 | TC_CRITICAL_SECTION_ENTER(); |
| 868 | ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_MODE(mask); |
| 869 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 870 | TC_CRITICAL_SECTION_LEAVE(); |
| 871 | } |
| 872 | |
| 873 | static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) |
| 874 | { |
| 875 | uint32_t tmp; |
| 876 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 877 | tmp = (tmp & TC_CTRLA_MODE(mask)) >> TC_CTRLA_MODE_Pos; |
| 878 | return tmp; |
| 879 | } |
| 880 | |
| 881 | static inline void hri_tc_write_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t data) |
| 882 | { |
| 883 | uint32_t tmp; |
| 884 | TC_CRITICAL_SECTION_ENTER(); |
| 885 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 886 | tmp &= ~TC_CTRLA_MODE_Msk; |
| 887 | tmp |= TC_CTRLA_MODE(data); |
| 888 | ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; |
| 889 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 890 | TC_CRITICAL_SECTION_LEAVE(); |
| 891 | } |
| 892 | |
| 893 | static inline void hri_tc_clear_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) |
| 894 | { |
| 895 | TC_CRITICAL_SECTION_ENTER(); |
| 896 | ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_MODE(mask); |
| 897 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 898 | TC_CRITICAL_SECTION_LEAVE(); |
| 899 | } |
| 900 | |
| 901 | static inline void hri_tc_toggle_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) |
| 902 | { |
| 903 | TC_CRITICAL_SECTION_ENTER(); |
| 904 | ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_MODE(mask); |
| 905 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 906 | TC_CRITICAL_SECTION_LEAVE(); |
| 907 | } |
| 908 | |
| 909 | static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_MODE_bf(const void *const hw) |
| 910 | { |
| 911 | uint32_t tmp; |
| 912 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 913 | tmp = (tmp & TC_CTRLA_MODE_Msk) >> TC_CTRLA_MODE_Pos; |
| 914 | return tmp; |
| 915 | } |
| 916 | |
| 917 | static inline void hri_tc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) |
| 918 | { |
| 919 | TC_CRITICAL_SECTION_ENTER(); |
| 920 | ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCSYNC(mask); |
| 921 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 922 | TC_CRITICAL_SECTION_LEAVE(); |
| 923 | } |
| 924 | |
| 925 | static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) |
| 926 | { |
| 927 | uint32_t tmp; |
| 928 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 929 | tmp = (tmp & TC_CTRLA_PRESCSYNC(mask)) >> TC_CTRLA_PRESCSYNC_Pos; |
| 930 | return tmp; |
| 931 | } |
| 932 | |
| 933 | static inline void hri_tc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t data) |
| 934 | { |
| 935 | uint32_t tmp; |
| 936 | TC_CRITICAL_SECTION_ENTER(); |
| 937 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 938 | tmp &= ~TC_CTRLA_PRESCSYNC_Msk; |
| 939 | tmp |= TC_CTRLA_PRESCSYNC(data); |
| 940 | ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; |
| 941 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 942 | TC_CRITICAL_SECTION_LEAVE(); |
| 943 | } |
| 944 | |
| 945 | static inline void hri_tc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) |
| 946 | { |
| 947 | TC_CRITICAL_SECTION_ENTER(); |
| 948 | ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCSYNC(mask); |
| 949 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 950 | TC_CRITICAL_SECTION_LEAVE(); |
| 951 | } |
| 952 | |
| 953 | static inline void hri_tc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) |
| 954 | { |
| 955 | TC_CRITICAL_SECTION_ENTER(); |
| 956 | ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCSYNC(mask); |
| 957 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 958 | TC_CRITICAL_SECTION_LEAVE(); |
| 959 | } |
| 960 | |
| 961 | static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCSYNC_bf(const void *const hw) |
| 962 | { |
| 963 | uint32_t tmp; |
| 964 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 965 | tmp = (tmp & TC_CTRLA_PRESCSYNC_Msk) >> TC_CTRLA_PRESCSYNC_Pos; |
| 966 | return tmp; |
| 967 | } |
| 968 | |
| 969 | static inline void hri_tc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) |
| 970 | { |
| 971 | TC_CRITICAL_SECTION_ENTER(); |
| 972 | ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCALER(mask); |
| 973 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 974 | TC_CRITICAL_SECTION_LEAVE(); |
| 975 | } |
| 976 | |
| 977 | static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) |
| 978 | { |
| 979 | uint32_t tmp; |
| 980 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 981 | tmp = (tmp & TC_CTRLA_PRESCALER(mask)) >> TC_CTRLA_PRESCALER_Pos; |
| 982 | return tmp; |
| 983 | } |
| 984 | |
| 985 | static inline void hri_tc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t data) |
| 986 | { |
| 987 | uint32_t tmp; |
| 988 | TC_CRITICAL_SECTION_ENTER(); |
| 989 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 990 | tmp &= ~TC_CTRLA_PRESCALER_Msk; |
| 991 | tmp |= TC_CTRLA_PRESCALER(data); |
| 992 | ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; |
| 993 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 994 | TC_CRITICAL_SECTION_LEAVE(); |
| 995 | } |
| 996 | |
| 997 | static inline void hri_tc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) |
| 998 | { |
| 999 | TC_CRITICAL_SECTION_ENTER(); |
| 1000 | ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCALER(mask); |
| 1001 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 1002 | TC_CRITICAL_SECTION_LEAVE(); |
| 1003 | } |
| 1004 | |
| 1005 | static inline void hri_tc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) |
| 1006 | { |
| 1007 | TC_CRITICAL_SECTION_ENTER(); |
| 1008 | ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCALER(mask); |
| 1009 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 1010 | TC_CRITICAL_SECTION_LEAVE(); |
| 1011 | } |
| 1012 | |
| 1013 | static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCALER_bf(const void *const hw) |
| 1014 | { |
| 1015 | uint32_t tmp; |
| 1016 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 1017 | tmp = (tmp & TC_CTRLA_PRESCALER_Msk) >> TC_CTRLA_PRESCALER_Pos; |
| 1018 | return tmp; |
| 1019 | } |
| 1020 | |
| 1021 | static inline void hri_tc_set_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) |
| 1022 | { |
| 1023 | TC_CRITICAL_SECTION_ENTER(); |
| 1024 | ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTMODE0(mask); |
| 1025 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 1026 | TC_CRITICAL_SECTION_LEAVE(); |
| 1027 | } |
| 1028 | |
| 1029 | static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) |
| 1030 | { |
| 1031 | uint32_t tmp; |
| 1032 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 1033 | tmp = (tmp & TC_CTRLA_CAPTMODE0(mask)) >> TC_CTRLA_CAPTMODE0_Pos; |
| 1034 | return tmp; |
| 1035 | } |
| 1036 | |
| 1037 | static inline void hri_tc_write_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t data) |
| 1038 | { |
| 1039 | uint32_t tmp; |
| 1040 | TC_CRITICAL_SECTION_ENTER(); |
| 1041 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 1042 | tmp &= ~TC_CTRLA_CAPTMODE0_Msk; |
| 1043 | tmp |= TC_CTRLA_CAPTMODE0(data); |
| 1044 | ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; |
| 1045 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 1046 | TC_CRITICAL_SECTION_LEAVE(); |
| 1047 | } |
| 1048 | |
| 1049 | static inline void hri_tc_clear_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) |
| 1050 | { |
| 1051 | TC_CRITICAL_SECTION_ENTER(); |
| 1052 | ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTMODE0(mask); |
| 1053 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 1054 | TC_CRITICAL_SECTION_LEAVE(); |
| 1055 | } |
| 1056 | |
| 1057 | static inline void hri_tc_toggle_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) |
| 1058 | { |
| 1059 | TC_CRITICAL_SECTION_ENTER(); |
| 1060 | ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTMODE0(mask); |
| 1061 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 1062 | TC_CRITICAL_SECTION_LEAVE(); |
| 1063 | } |
| 1064 | |
| 1065 | static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_CAPTMODE0_bf(const void *const hw) |
| 1066 | { |
| 1067 | uint32_t tmp; |
| 1068 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 1069 | tmp = (tmp & TC_CTRLA_CAPTMODE0_Msk) >> TC_CTRLA_CAPTMODE0_Pos; |
| 1070 | return tmp; |
| 1071 | } |
| 1072 | |
| 1073 | static inline void hri_tc_set_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) |
| 1074 | { |
| 1075 | TC_CRITICAL_SECTION_ENTER(); |
| 1076 | ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTMODE1(mask); |
| 1077 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 1078 | TC_CRITICAL_SECTION_LEAVE(); |
| 1079 | } |
| 1080 | |
| 1081 | static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) |
| 1082 | { |
| 1083 | uint32_t tmp; |
| 1084 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 1085 | tmp = (tmp & TC_CTRLA_CAPTMODE1(mask)) >> TC_CTRLA_CAPTMODE1_Pos; |
| 1086 | return tmp; |
| 1087 | } |
| 1088 | |
| 1089 | static inline void hri_tc_write_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t data) |
| 1090 | { |
| 1091 | uint32_t tmp; |
| 1092 | TC_CRITICAL_SECTION_ENTER(); |
| 1093 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 1094 | tmp &= ~TC_CTRLA_CAPTMODE1_Msk; |
| 1095 | tmp |= TC_CTRLA_CAPTMODE1(data); |
| 1096 | ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; |
| 1097 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 1098 | TC_CRITICAL_SECTION_LEAVE(); |
| 1099 | } |
| 1100 | |
| 1101 | static inline void hri_tc_clear_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) |
| 1102 | { |
| 1103 | TC_CRITICAL_SECTION_ENTER(); |
| 1104 | ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTMODE1(mask); |
| 1105 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 1106 | TC_CRITICAL_SECTION_LEAVE(); |
| 1107 | } |
| 1108 | |
| 1109 | static inline void hri_tc_toggle_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) |
| 1110 | { |
| 1111 | TC_CRITICAL_SECTION_ENTER(); |
| 1112 | ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTMODE1(mask); |
| 1113 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 1114 | TC_CRITICAL_SECTION_LEAVE(); |
| 1115 | } |
| 1116 | |
| 1117 | static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_CAPTMODE1_bf(const void *const hw) |
| 1118 | { |
| 1119 | uint32_t tmp; |
| 1120 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 1121 | tmp = (tmp & TC_CTRLA_CAPTMODE1_Msk) >> TC_CTRLA_CAPTMODE1_Pos; |
| 1122 | return tmp; |
| 1123 | } |
| 1124 | |
| 1125 | static inline void hri_tc_set_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) |
| 1126 | { |
| 1127 | TC_CRITICAL_SECTION_ENTER(); |
| 1128 | ((Tc *)hw)->COUNT16.CTRLA.reg |= mask; |
| 1129 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); |
| 1130 | TC_CRITICAL_SECTION_LEAVE(); |
| 1131 | } |
| 1132 | |
| 1133 | static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) |
| 1134 | { |
| 1135 | uint32_t tmp; |
| 1136 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); |
| 1137 | tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 1138 | tmp &= mask; |
| 1139 | return tmp; |
| 1140 | } |
| 1141 | |
| 1142 | static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data) |
| 1143 | { |
| 1144 | TC_CRITICAL_SECTION_ENTER(); |
| 1145 | ((Tc *)hw)->COUNT16.CTRLA.reg = data; |
| 1146 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); |
| 1147 | TC_CRITICAL_SECTION_LEAVE(); |
| 1148 | } |
| 1149 | |
| 1150 | static inline void hri_tc_clear_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) |
| 1151 | { |
| 1152 | TC_CRITICAL_SECTION_ENTER(); |
| 1153 | ((Tc *)hw)->COUNT16.CTRLA.reg &= ~mask; |
| 1154 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); |
| 1155 | TC_CRITICAL_SECTION_LEAVE(); |
| 1156 | } |
| 1157 | |
| 1158 | static inline void hri_tc_toggle_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) |
| 1159 | { |
| 1160 | TC_CRITICAL_SECTION_ENTER(); |
| 1161 | ((Tc *)hw)->COUNT16.CTRLA.reg ^= mask; |
| 1162 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); |
| 1163 | TC_CRITICAL_SECTION_LEAVE(); |
| 1164 | } |
| 1165 | |
| 1166 | static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_reg(const void *const hw) |
| 1167 | { |
| 1168 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); |
| 1169 | return ((Tc *)hw)->COUNT16.CTRLA.reg; |
| 1170 | } |
| 1171 | |
| 1172 | static inline void hri_tc_set_EVCTRL_TCINV_bit(const void *const hw) |
| 1173 | { |
| 1174 | TC_CRITICAL_SECTION_ENTER(); |
| 1175 | ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCINV; |
| 1176 | TC_CRITICAL_SECTION_LEAVE(); |
| 1177 | } |
| 1178 | |
| 1179 | static inline bool hri_tc_get_EVCTRL_TCINV_bit(const void *const hw) |
| 1180 | { |
| 1181 | uint16_t tmp; |
| 1182 | tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; |
| 1183 | tmp = (tmp & TC_EVCTRL_TCINV) >> TC_EVCTRL_TCINV_Pos; |
| 1184 | return (bool)tmp; |
| 1185 | } |
| 1186 | |
| 1187 | static inline void hri_tc_write_EVCTRL_TCINV_bit(const void *const hw, bool value) |
| 1188 | { |
| 1189 | uint16_t tmp; |
| 1190 | TC_CRITICAL_SECTION_ENTER(); |
| 1191 | tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; |
| 1192 | tmp &= ~TC_EVCTRL_TCINV; |
| 1193 | tmp |= value << TC_EVCTRL_TCINV_Pos; |
| 1194 | ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; |
| 1195 | TC_CRITICAL_SECTION_LEAVE(); |
| 1196 | } |
| 1197 | |
| 1198 | static inline void hri_tc_clear_EVCTRL_TCINV_bit(const void *const hw) |
| 1199 | { |
| 1200 | TC_CRITICAL_SECTION_ENTER(); |
| 1201 | ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCINV; |
| 1202 | TC_CRITICAL_SECTION_LEAVE(); |
| 1203 | } |
| 1204 | |
| 1205 | static inline void hri_tc_toggle_EVCTRL_TCINV_bit(const void *const hw) |
| 1206 | { |
| 1207 | TC_CRITICAL_SECTION_ENTER(); |
| 1208 | ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCINV; |
| 1209 | TC_CRITICAL_SECTION_LEAVE(); |
| 1210 | } |
| 1211 | |
| 1212 | static inline void hri_tc_set_EVCTRL_TCEI_bit(const void *const hw) |
| 1213 | { |
| 1214 | TC_CRITICAL_SECTION_ENTER(); |
| 1215 | ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCEI; |
| 1216 | TC_CRITICAL_SECTION_LEAVE(); |
| 1217 | } |
| 1218 | |
| 1219 | static inline bool hri_tc_get_EVCTRL_TCEI_bit(const void *const hw) |
| 1220 | { |
| 1221 | uint16_t tmp; |
| 1222 | tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; |
| 1223 | tmp = (tmp & TC_EVCTRL_TCEI) >> TC_EVCTRL_TCEI_Pos; |
| 1224 | return (bool)tmp; |
| 1225 | } |
| 1226 | |
| 1227 | static inline void hri_tc_write_EVCTRL_TCEI_bit(const void *const hw, bool value) |
| 1228 | { |
| 1229 | uint16_t tmp; |
| 1230 | TC_CRITICAL_SECTION_ENTER(); |
| 1231 | tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; |
| 1232 | tmp &= ~TC_EVCTRL_TCEI; |
| 1233 | tmp |= value << TC_EVCTRL_TCEI_Pos; |
| 1234 | ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; |
| 1235 | TC_CRITICAL_SECTION_LEAVE(); |
| 1236 | } |
| 1237 | |
| 1238 | static inline void hri_tc_clear_EVCTRL_TCEI_bit(const void *const hw) |
| 1239 | { |
| 1240 | TC_CRITICAL_SECTION_ENTER(); |
| 1241 | ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCEI; |
| 1242 | TC_CRITICAL_SECTION_LEAVE(); |
| 1243 | } |
| 1244 | |
| 1245 | static inline void hri_tc_toggle_EVCTRL_TCEI_bit(const void *const hw) |
| 1246 | { |
| 1247 | TC_CRITICAL_SECTION_ENTER(); |
| 1248 | ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCEI; |
| 1249 | TC_CRITICAL_SECTION_LEAVE(); |
| 1250 | } |
| 1251 | |
| 1252 | static inline void hri_tc_set_EVCTRL_OVFEO_bit(const void *const hw) |
| 1253 | { |
| 1254 | TC_CRITICAL_SECTION_ENTER(); |
| 1255 | ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_OVFEO; |
| 1256 | TC_CRITICAL_SECTION_LEAVE(); |
| 1257 | } |
| 1258 | |
| 1259 | static inline bool hri_tc_get_EVCTRL_OVFEO_bit(const void *const hw) |
| 1260 | { |
| 1261 | uint16_t tmp; |
| 1262 | tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; |
| 1263 | tmp = (tmp & TC_EVCTRL_OVFEO) >> TC_EVCTRL_OVFEO_Pos; |
| 1264 | return (bool)tmp; |
| 1265 | } |
| 1266 | |
| 1267 | static inline void hri_tc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) |
| 1268 | { |
| 1269 | uint16_t tmp; |
| 1270 | TC_CRITICAL_SECTION_ENTER(); |
| 1271 | tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; |
| 1272 | tmp &= ~TC_EVCTRL_OVFEO; |
| 1273 | tmp |= value << TC_EVCTRL_OVFEO_Pos; |
| 1274 | ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; |
| 1275 | TC_CRITICAL_SECTION_LEAVE(); |
| 1276 | } |
| 1277 | |
| 1278 | static inline void hri_tc_clear_EVCTRL_OVFEO_bit(const void *const hw) |
| 1279 | { |
| 1280 | TC_CRITICAL_SECTION_ENTER(); |
| 1281 | ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_OVFEO; |
| 1282 | TC_CRITICAL_SECTION_LEAVE(); |
| 1283 | } |
| 1284 | |
| 1285 | static inline void hri_tc_toggle_EVCTRL_OVFEO_bit(const void *const hw) |
| 1286 | { |
| 1287 | TC_CRITICAL_SECTION_ENTER(); |
| 1288 | ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_OVFEO; |
| 1289 | TC_CRITICAL_SECTION_LEAVE(); |
| 1290 | } |
| 1291 | |
| 1292 | static inline void hri_tc_set_EVCTRL_MCEO0_bit(const void *const hw) |
| 1293 | { |
| 1294 | TC_CRITICAL_SECTION_ENTER(); |
| 1295 | ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO0; |
| 1296 | TC_CRITICAL_SECTION_LEAVE(); |
| 1297 | } |
| 1298 | |
| 1299 | static inline bool hri_tc_get_EVCTRL_MCEO0_bit(const void *const hw) |
| 1300 | { |
| 1301 | uint16_t tmp; |
| 1302 | tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; |
| 1303 | tmp = (tmp & TC_EVCTRL_MCEO0) >> TC_EVCTRL_MCEO0_Pos; |
| 1304 | return (bool)tmp; |
| 1305 | } |
| 1306 | |
| 1307 | static inline void hri_tc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) |
| 1308 | { |
| 1309 | uint16_t tmp; |
| 1310 | TC_CRITICAL_SECTION_ENTER(); |
| 1311 | tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; |
| 1312 | tmp &= ~TC_EVCTRL_MCEO0; |
| 1313 | tmp |= value << TC_EVCTRL_MCEO0_Pos; |
| 1314 | ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; |
| 1315 | TC_CRITICAL_SECTION_LEAVE(); |
| 1316 | } |
| 1317 | |
| 1318 | static inline void hri_tc_clear_EVCTRL_MCEO0_bit(const void *const hw) |
| 1319 | { |
| 1320 | TC_CRITICAL_SECTION_ENTER(); |
| 1321 | ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO0; |
| 1322 | TC_CRITICAL_SECTION_LEAVE(); |
| 1323 | } |
| 1324 | |
| 1325 | static inline void hri_tc_toggle_EVCTRL_MCEO0_bit(const void *const hw) |
| 1326 | { |
| 1327 | TC_CRITICAL_SECTION_ENTER(); |
| 1328 | ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO0; |
| 1329 | TC_CRITICAL_SECTION_LEAVE(); |
| 1330 | } |
| 1331 | |
| 1332 | static inline void hri_tc_set_EVCTRL_MCEO1_bit(const void *const hw) |
| 1333 | { |
| 1334 | TC_CRITICAL_SECTION_ENTER(); |
| 1335 | ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO1; |
| 1336 | TC_CRITICAL_SECTION_LEAVE(); |
| 1337 | } |
| 1338 | |
| 1339 | static inline bool hri_tc_get_EVCTRL_MCEO1_bit(const void *const hw) |
| 1340 | { |
| 1341 | uint16_t tmp; |
| 1342 | tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; |
| 1343 | tmp = (tmp & TC_EVCTRL_MCEO1) >> TC_EVCTRL_MCEO1_Pos; |
| 1344 | return (bool)tmp; |
| 1345 | } |
| 1346 | |
| 1347 | static inline void hri_tc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) |
| 1348 | { |
| 1349 | uint16_t tmp; |
| 1350 | TC_CRITICAL_SECTION_ENTER(); |
| 1351 | tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; |
| 1352 | tmp &= ~TC_EVCTRL_MCEO1; |
| 1353 | tmp |= value << TC_EVCTRL_MCEO1_Pos; |
| 1354 | ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; |
| 1355 | TC_CRITICAL_SECTION_LEAVE(); |
| 1356 | } |
| 1357 | |
| 1358 | static inline void hri_tc_clear_EVCTRL_MCEO1_bit(const void *const hw) |
| 1359 | { |
| 1360 | TC_CRITICAL_SECTION_ENTER(); |
| 1361 | ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO1; |
| 1362 | TC_CRITICAL_SECTION_LEAVE(); |
| 1363 | } |
| 1364 | |
| 1365 | static inline void hri_tc_toggle_EVCTRL_MCEO1_bit(const void *const hw) |
| 1366 | { |
| 1367 | TC_CRITICAL_SECTION_ENTER(); |
| 1368 | ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO1; |
| 1369 | TC_CRITICAL_SECTION_LEAVE(); |
| 1370 | } |
| 1371 | |
| 1372 | static inline void hri_tc_set_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) |
| 1373 | { |
| 1374 | TC_CRITICAL_SECTION_ENTER(); |
| 1375 | ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_EVACT(mask); |
| 1376 | TC_CRITICAL_SECTION_LEAVE(); |
| 1377 | } |
| 1378 | |
| 1379 | static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) |
| 1380 | { |
| 1381 | uint16_t tmp; |
| 1382 | tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; |
| 1383 | tmp = (tmp & TC_EVCTRL_EVACT(mask)) >> TC_EVCTRL_EVACT_Pos; |
| 1384 | return tmp; |
| 1385 | } |
| 1386 | |
| 1387 | static inline void hri_tc_write_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t data) |
| 1388 | { |
| 1389 | uint16_t tmp; |
| 1390 | TC_CRITICAL_SECTION_ENTER(); |
| 1391 | tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; |
| 1392 | tmp &= ~TC_EVCTRL_EVACT_Msk; |
| 1393 | tmp |= TC_EVCTRL_EVACT(data); |
| 1394 | ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; |
| 1395 | TC_CRITICAL_SECTION_LEAVE(); |
| 1396 | } |
| 1397 | |
| 1398 | static inline void hri_tc_clear_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) |
| 1399 | { |
| 1400 | TC_CRITICAL_SECTION_ENTER(); |
| 1401 | ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_EVACT(mask); |
| 1402 | TC_CRITICAL_SECTION_LEAVE(); |
| 1403 | } |
| 1404 | |
| 1405 | static inline void hri_tc_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) |
| 1406 | { |
| 1407 | TC_CRITICAL_SECTION_ENTER(); |
| 1408 | ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_EVACT(mask); |
| 1409 | TC_CRITICAL_SECTION_LEAVE(); |
| 1410 | } |
| 1411 | |
| 1412 | static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_EVACT_bf(const void *const hw) |
| 1413 | { |
| 1414 | uint16_t tmp; |
| 1415 | tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; |
| 1416 | tmp = (tmp & TC_EVCTRL_EVACT_Msk) >> TC_EVCTRL_EVACT_Pos; |
| 1417 | return tmp; |
| 1418 | } |
| 1419 | |
| 1420 | static inline void hri_tc_set_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) |
| 1421 | { |
| 1422 | TC_CRITICAL_SECTION_ENTER(); |
| 1423 | ((Tc *)hw)->COUNT16.EVCTRL.reg |= mask; |
| 1424 | TC_CRITICAL_SECTION_LEAVE(); |
| 1425 | } |
| 1426 | |
| 1427 | static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) |
| 1428 | { |
| 1429 | uint16_t tmp; |
| 1430 | tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; |
| 1431 | tmp &= mask; |
| 1432 | return tmp; |
| 1433 | } |
| 1434 | |
| 1435 | static inline void hri_tc_write_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t data) |
| 1436 | { |
| 1437 | TC_CRITICAL_SECTION_ENTER(); |
| 1438 | ((Tc *)hw)->COUNT16.EVCTRL.reg = data; |
| 1439 | TC_CRITICAL_SECTION_LEAVE(); |
| 1440 | } |
| 1441 | |
| 1442 | static inline void hri_tc_clear_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) |
| 1443 | { |
| 1444 | TC_CRITICAL_SECTION_ENTER(); |
| 1445 | ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~mask; |
| 1446 | TC_CRITICAL_SECTION_LEAVE(); |
| 1447 | } |
| 1448 | |
| 1449 | static inline void hri_tc_toggle_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) |
| 1450 | { |
| 1451 | TC_CRITICAL_SECTION_ENTER(); |
| 1452 | ((Tc *)hw)->COUNT16.EVCTRL.reg ^= mask; |
| 1453 | TC_CRITICAL_SECTION_LEAVE(); |
| 1454 | } |
| 1455 | |
| 1456 | static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_reg(const void *const hw) |
| 1457 | { |
| 1458 | return ((Tc *)hw)->COUNT16.EVCTRL.reg; |
| 1459 | } |
| 1460 | |
| 1461 | static inline void hri_tc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) |
| 1462 | { |
| 1463 | TC_CRITICAL_SECTION_ENTER(); |
| 1464 | ((Tc *)hw)->COUNT16.WAVE.reg |= TC_WAVE_WAVEGEN(mask); |
| 1465 | TC_CRITICAL_SECTION_LEAVE(); |
| 1466 | } |
| 1467 | |
| 1468 | static inline hri_tc_wave_reg_t hri_tc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) |
| 1469 | { |
| 1470 | uint8_t tmp; |
| 1471 | tmp = ((Tc *)hw)->COUNT16.WAVE.reg; |
| 1472 | tmp = (tmp & TC_WAVE_WAVEGEN(mask)) >> TC_WAVE_WAVEGEN_Pos; |
| 1473 | return tmp; |
| 1474 | } |
| 1475 | |
| 1476 | static inline void hri_tc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t data) |
| 1477 | { |
| 1478 | uint8_t tmp; |
| 1479 | TC_CRITICAL_SECTION_ENTER(); |
| 1480 | tmp = ((Tc *)hw)->COUNT16.WAVE.reg; |
| 1481 | tmp &= ~TC_WAVE_WAVEGEN_Msk; |
| 1482 | tmp |= TC_WAVE_WAVEGEN(data); |
| 1483 | ((Tc *)hw)->COUNT16.WAVE.reg = tmp; |
| 1484 | TC_CRITICAL_SECTION_LEAVE(); |
| 1485 | } |
| 1486 | |
| 1487 | static inline void hri_tc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) |
| 1488 | { |
| 1489 | TC_CRITICAL_SECTION_ENTER(); |
| 1490 | ((Tc *)hw)->COUNT16.WAVE.reg &= ~TC_WAVE_WAVEGEN(mask); |
| 1491 | TC_CRITICAL_SECTION_LEAVE(); |
| 1492 | } |
| 1493 | |
| 1494 | static inline void hri_tc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) |
| 1495 | { |
| 1496 | TC_CRITICAL_SECTION_ENTER(); |
| 1497 | ((Tc *)hw)->COUNT16.WAVE.reg ^= TC_WAVE_WAVEGEN(mask); |
| 1498 | TC_CRITICAL_SECTION_LEAVE(); |
| 1499 | } |
| 1500 | |
| 1501 | static inline hri_tc_wave_reg_t hri_tc_read_WAVE_WAVEGEN_bf(const void *const hw) |
| 1502 | { |
| 1503 | uint8_t tmp; |
| 1504 | tmp = ((Tc *)hw)->COUNT16.WAVE.reg; |
| 1505 | tmp = (tmp & TC_WAVE_WAVEGEN_Msk) >> TC_WAVE_WAVEGEN_Pos; |
| 1506 | return tmp; |
| 1507 | } |
| 1508 | |
| 1509 | static inline void hri_tc_set_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) |
| 1510 | { |
| 1511 | TC_CRITICAL_SECTION_ENTER(); |
| 1512 | ((Tc *)hw)->COUNT16.WAVE.reg |= mask; |
| 1513 | TC_CRITICAL_SECTION_LEAVE(); |
| 1514 | } |
| 1515 | |
| 1516 | static inline hri_tc_wave_reg_t hri_tc_get_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) |
| 1517 | { |
| 1518 | uint8_t tmp; |
| 1519 | tmp = ((Tc *)hw)->COUNT16.WAVE.reg; |
| 1520 | tmp &= mask; |
| 1521 | return tmp; |
| 1522 | } |
| 1523 | |
| 1524 | static inline void hri_tc_write_WAVE_reg(const void *const hw, hri_tc_wave_reg_t data) |
| 1525 | { |
| 1526 | TC_CRITICAL_SECTION_ENTER(); |
| 1527 | ((Tc *)hw)->COUNT16.WAVE.reg = data; |
| 1528 | TC_CRITICAL_SECTION_LEAVE(); |
| 1529 | } |
| 1530 | |
| 1531 | static inline void hri_tc_clear_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) |
| 1532 | { |
| 1533 | TC_CRITICAL_SECTION_ENTER(); |
| 1534 | ((Tc *)hw)->COUNT16.WAVE.reg &= ~mask; |
| 1535 | TC_CRITICAL_SECTION_LEAVE(); |
| 1536 | } |
| 1537 | |
| 1538 | static inline void hri_tc_toggle_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) |
| 1539 | { |
| 1540 | TC_CRITICAL_SECTION_ENTER(); |
| 1541 | ((Tc *)hw)->COUNT16.WAVE.reg ^= mask; |
| 1542 | TC_CRITICAL_SECTION_LEAVE(); |
| 1543 | } |
| 1544 | |
| 1545 | static inline hri_tc_wave_reg_t hri_tc_read_WAVE_reg(const void *const hw) |
| 1546 | { |
| 1547 | return ((Tc *)hw)->COUNT16.WAVE.reg; |
| 1548 | } |
| 1549 | |
| 1550 | static inline void hri_tc_set_DRVCTRL_INVEN0_bit(const void *const hw) |
| 1551 | { |
| 1552 | TC_CRITICAL_SECTION_ENTER(); |
| 1553 | ((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN0; |
| 1554 | TC_CRITICAL_SECTION_LEAVE(); |
| 1555 | } |
| 1556 | |
| 1557 | static inline bool hri_tc_get_DRVCTRL_INVEN0_bit(const void *const hw) |
| 1558 | { |
| 1559 | uint8_t tmp; |
| 1560 | tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; |
| 1561 | tmp = (tmp & TC_DRVCTRL_INVEN0) >> TC_DRVCTRL_INVEN0_Pos; |
| 1562 | return (bool)tmp; |
| 1563 | } |
| 1564 | |
| 1565 | static inline void hri_tc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) |
| 1566 | { |
| 1567 | uint8_t tmp; |
| 1568 | TC_CRITICAL_SECTION_ENTER(); |
| 1569 | tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; |
| 1570 | tmp &= ~TC_DRVCTRL_INVEN0; |
| 1571 | tmp |= value << TC_DRVCTRL_INVEN0_Pos; |
| 1572 | ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; |
| 1573 | TC_CRITICAL_SECTION_LEAVE(); |
| 1574 | } |
| 1575 | |
| 1576 | static inline void hri_tc_clear_DRVCTRL_INVEN0_bit(const void *const hw) |
| 1577 | { |
| 1578 | TC_CRITICAL_SECTION_ENTER(); |
| 1579 | ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN0; |
| 1580 | TC_CRITICAL_SECTION_LEAVE(); |
| 1581 | } |
| 1582 | |
| 1583 | static inline void hri_tc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) |
| 1584 | { |
| 1585 | TC_CRITICAL_SECTION_ENTER(); |
| 1586 | ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN0; |
| 1587 | TC_CRITICAL_SECTION_LEAVE(); |
| 1588 | } |
| 1589 | |
| 1590 | static inline void hri_tc_set_DRVCTRL_INVEN1_bit(const void *const hw) |
| 1591 | { |
| 1592 | TC_CRITICAL_SECTION_ENTER(); |
| 1593 | ((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN1; |
| 1594 | TC_CRITICAL_SECTION_LEAVE(); |
| 1595 | } |
| 1596 | |
| 1597 | static inline bool hri_tc_get_DRVCTRL_INVEN1_bit(const void *const hw) |
| 1598 | { |
| 1599 | uint8_t tmp; |
| 1600 | tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; |
| 1601 | tmp = (tmp & TC_DRVCTRL_INVEN1) >> TC_DRVCTRL_INVEN1_Pos; |
| 1602 | return (bool)tmp; |
| 1603 | } |
| 1604 | |
| 1605 | static inline void hri_tc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) |
| 1606 | { |
| 1607 | uint8_t tmp; |
| 1608 | TC_CRITICAL_SECTION_ENTER(); |
| 1609 | tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; |
| 1610 | tmp &= ~TC_DRVCTRL_INVEN1; |
| 1611 | tmp |= value << TC_DRVCTRL_INVEN1_Pos; |
| 1612 | ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; |
| 1613 | TC_CRITICAL_SECTION_LEAVE(); |
| 1614 | } |
| 1615 | |
| 1616 | static inline void hri_tc_clear_DRVCTRL_INVEN1_bit(const void *const hw) |
| 1617 | { |
| 1618 | TC_CRITICAL_SECTION_ENTER(); |
| 1619 | ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN1; |
| 1620 | TC_CRITICAL_SECTION_LEAVE(); |
| 1621 | } |
| 1622 | |
| 1623 | static inline void hri_tc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) |
| 1624 | { |
| 1625 | TC_CRITICAL_SECTION_ENTER(); |
| 1626 | ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN1; |
| 1627 | TC_CRITICAL_SECTION_LEAVE(); |
| 1628 | } |
| 1629 | |
| 1630 | static inline void hri_tc_set_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) |
| 1631 | { |
| 1632 | TC_CRITICAL_SECTION_ENTER(); |
| 1633 | ((Tc *)hw)->COUNT16.DRVCTRL.reg |= mask; |
| 1634 | TC_CRITICAL_SECTION_LEAVE(); |
| 1635 | } |
| 1636 | |
| 1637 | static inline hri_tc_drvctrl_reg_t hri_tc_get_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) |
| 1638 | { |
| 1639 | uint8_t tmp; |
| 1640 | tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; |
| 1641 | tmp &= mask; |
| 1642 | return tmp; |
| 1643 | } |
| 1644 | |
| 1645 | static inline void hri_tc_write_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t data) |
| 1646 | { |
| 1647 | TC_CRITICAL_SECTION_ENTER(); |
| 1648 | ((Tc *)hw)->COUNT16.DRVCTRL.reg = data; |
| 1649 | TC_CRITICAL_SECTION_LEAVE(); |
| 1650 | } |
| 1651 | |
| 1652 | static inline void hri_tc_clear_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) |
| 1653 | { |
| 1654 | TC_CRITICAL_SECTION_ENTER(); |
| 1655 | ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~mask; |
| 1656 | TC_CRITICAL_SECTION_LEAVE(); |
| 1657 | } |
| 1658 | |
| 1659 | static inline void hri_tc_toggle_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) |
| 1660 | { |
| 1661 | TC_CRITICAL_SECTION_ENTER(); |
| 1662 | ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= mask; |
| 1663 | TC_CRITICAL_SECTION_LEAVE(); |
| 1664 | } |
| 1665 | |
| 1666 | static inline hri_tc_drvctrl_reg_t hri_tc_read_DRVCTRL_reg(const void *const hw) |
| 1667 | { |
| 1668 | return ((Tc *)hw)->COUNT16.DRVCTRL.reg; |
| 1669 | } |
| 1670 | |
| 1671 | static inline void hri_tc_set_DBGCTRL_DBGRUN_bit(const void *const hw) |
| 1672 | { |
| 1673 | TC_CRITICAL_SECTION_ENTER(); |
| 1674 | ((Tc *)hw)->COUNT16.DBGCTRL.reg |= TC_DBGCTRL_DBGRUN; |
| 1675 | TC_CRITICAL_SECTION_LEAVE(); |
| 1676 | } |
| 1677 | |
| 1678 | static inline bool hri_tc_get_DBGCTRL_DBGRUN_bit(const void *const hw) |
| 1679 | { |
| 1680 | uint8_t tmp; |
| 1681 | tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; |
| 1682 | tmp = (tmp & TC_DBGCTRL_DBGRUN) >> TC_DBGCTRL_DBGRUN_Pos; |
| 1683 | return (bool)tmp; |
| 1684 | } |
| 1685 | |
| 1686 | static inline void hri_tc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) |
| 1687 | { |
| 1688 | uint8_t tmp; |
| 1689 | TC_CRITICAL_SECTION_ENTER(); |
| 1690 | tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; |
| 1691 | tmp &= ~TC_DBGCTRL_DBGRUN; |
| 1692 | tmp |= value << TC_DBGCTRL_DBGRUN_Pos; |
| 1693 | ((Tc *)hw)->COUNT16.DBGCTRL.reg = tmp; |
| 1694 | TC_CRITICAL_SECTION_LEAVE(); |
| 1695 | } |
| 1696 | |
| 1697 | static inline void hri_tc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) |
| 1698 | { |
| 1699 | TC_CRITICAL_SECTION_ENTER(); |
| 1700 | ((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~TC_DBGCTRL_DBGRUN; |
| 1701 | TC_CRITICAL_SECTION_LEAVE(); |
| 1702 | } |
| 1703 | |
| 1704 | static inline void hri_tc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) |
| 1705 | { |
| 1706 | TC_CRITICAL_SECTION_ENTER(); |
| 1707 | ((Tc *)hw)->COUNT16.DBGCTRL.reg ^= TC_DBGCTRL_DBGRUN; |
| 1708 | TC_CRITICAL_SECTION_LEAVE(); |
| 1709 | } |
| 1710 | |
| 1711 | static inline void hri_tc_set_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) |
| 1712 | { |
| 1713 | TC_CRITICAL_SECTION_ENTER(); |
| 1714 | ((Tc *)hw)->COUNT16.DBGCTRL.reg |= mask; |
| 1715 | TC_CRITICAL_SECTION_LEAVE(); |
| 1716 | } |
| 1717 | |
| 1718 | static inline hri_tc_dbgctrl_reg_t hri_tc_get_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) |
| 1719 | { |
| 1720 | uint8_t tmp; |
| 1721 | tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; |
| 1722 | tmp &= mask; |
| 1723 | return tmp; |
| 1724 | } |
| 1725 | |
| 1726 | static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data) |
| 1727 | { |
| 1728 | TC_CRITICAL_SECTION_ENTER(); |
| 1729 | ((Tc *)hw)->COUNT16.DBGCTRL.reg = data; |
| 1730 | TC_CRITICAL_SECTION_LEAVE(); |
| 1731 | } |
| 1732 | |
| 1733 | static inline void hri_tc_clear_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) |
| 1734 | { |
| 1735 | TC_CRITICAL_SECTION_ENTER(); |
| 1736 | ((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~mask; |
| 1737 | TC_CRITICAL_SECTION_LEAVE(); |
| 1738 | } |
| 1739 | |
| 1740 | static inline void hri_tc_toggle_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) |
| 1741 | { |
| 1742 | TC_CRITICAL_SECTION_ENTER(); |
| 1743 | ((Tc *)hw)->COUNT16.DBGCTRL.reg ^= mask; |
| 1744 | TC_CRITICAL_SECTION_LEAVE(); |
| 1745 | } |
| 1746 | |
| 1747 | static inline hri_tc_dbgctrl_reg_t hri_tc_read_DBGCTRL_reg(const void *const hw) |
| 1748 | { |
| 1749 | return ((Tc *)hw)->COUNT16.DBGCTRL.reg; |
| 1750 | } |
| 1751 | |
| 1752 | static inline void hri_tccount8_set_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) |
| 1753 | { |
| 1754 | TC_CRITICAL_SECTION_ENTER(); |
| 1755 | ((Tc *)hw)->COUNT8.COUNT.reg |= TC_COUNT8_COUNT_COUNT(mask); |
| 1756 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 1757 | TC_CRITICAL_SECTION_LEAVE(); |
| 1758 | } |
| 1759 | |
| 1760 | static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_COUNT_bf(const void *const hw, |
| 1761 | hri_tccount8_count_reg_t mask) |
| 1762 | { |
| 1763 | uint8_t tmp; |
| 1764 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 1765 | tmp = ((Tc *)hw)->COUNT8.COUNT.reg; |
| 1766 | tmp = (tmp & TC_COUNT8_COUNT_COUNT(mask)) >> TC_COUNT8_COUNT_COUNT_Pos; |
| 1767 | return tmp; |
| 1768 | } |
| 1769 | |
| 1770 | static inline void hri_tccount8_write_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t data) |
| 1771 | { |
| 1772 | uint8_t tmp; |
| 1773 | TC_CRITICAL_SECTION_ENTER(); |
| 1774 | tmp = ((Tc *)hw)->COUNT8.COUNT.reg; |
| 1775 | tmp &= ~TC_COUNT8_COUNT_COUNT_Msk; |
| 1776 | tmp |= TC_COUNT8_COUNT_COUNT(data); |
| 1777 | ((Tc *)hw)->COUNT8.COUNT.reg = tmp; |
| 1778 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 1779 | TC_CRITICAL_SECTION_LEAVE(); |
| 1780 | } |
| 1781 | |
| 1782 | static inline void hri_tccount8_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) |
| 1783 | { |
| 1784 | TC_CRITICAL_SECTION_ENTER(); |
| 1785 | ((Tc *)hw)->COUNT8.COUNT.reg &= ~TC_COUNT8_COUNT_COUNT(mask); |
| 1786 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 1787 | TC_CRITICAL_SECTION_LEAVE(); |
| 1788 | } |
| 1789 | |
| 1790 | static inline void hri_tccount8_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) |
| 1791 | { |
| 1792 | TC_CRITICAL_SECTION_ENTER(); |
| 1793 | ((Tc *)hw)->COUNT8.COUNT.reg ^= TC_COUNT8_COUNT_COUNT(mask); |
| 1794 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 1795 | TC_CRITICAL_SECTION_LEAVE(); |
| 1796 | } |
| 1797 | |
| 1798 | static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_COUNT_bf(const void *const hw) |
| 1799 | { |
| 1800 | uint8_t tmp; |
| 1801 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 1802 | tmp = ((Tc *)hw)->COUNT8.COUNT.reg; |
| 1803 | tmp = (tmp & TC_COUNT8_COUNT_COUNT_Msk) >> TC_COUNT8_COUNT_COUNT_Pos; |
| 1804 | return tmp; |
| 1805 | } |
| 1806 | |
| 1807 | static inline void hri_tccount8_set_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) |
| 1808 | { |
| 1809 | TC_CRITICAL_SECTION_ENTER(); |
| 1810 | ((Tc *)hw)->COUNT8.COUNT.reg |= mask; |
| 1811 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 1812 | TC_CRITICAL_SECTION_LEAVE(); |
| 1813 | } |
| 1814 | |
| 1815 | static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) |
| 1816 | { |
| 1817 | uint8_t tmp; |
| 1818 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 1819 | tmp = ((Tc *)hw)->COUNT8.COUNT.reg; |
| 1820 | tmp &= mask; |
| 1821 | return tmp; |
| 1822 | } |
| 1823 | |
| 1824 | static inline void hri_tccount8_write_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t data) |
| 1825 | { |
| 1826 | TC_CRITICAL_SECTION_ENTER(); |
| 1827 | ((Tc *)hw)->COUNT8.COUNT.reg = data; |
| 1828 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 1829 | TC_CRITICAL_SECTION_LEAVE(); |
| 1830 | } |
| 1831 | |
| 1832 | static inline void hri_tccount8_clear_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) |
| 1833 | { |
| 1834 | TC_CRITICAL_SECTION_ENTER(); |
| 1835 | ((Tc *)hw)->COUNT8.COUNT.reg &= ~mask; |
| 1836 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 1837 | TC_CRITICAL_SECTION_LEAVE(); |
| 1838 | } |
| 1839 | |
| 1840 | static inline void hri_tccount8_toggle_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) |
| 1841 | { |
| 1842 | TC_CRITICAL_SECTION_ENTER(); |
| 1843 | ((Tc *)hw)->COUNT8.COUNT.reg ^= mask; |
| 1844 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 1845 | TC_CRITICAL_SECTION_LEAVE(); |
| 1846 | } |
| 1847 | |
| 1848 | static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_reg(const void *const hw) |
| 1849 | { |
| 1850 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 1851 | return ((Tc *)hw)->COUNT8.COUNT.reg; |
| 1852 | } |
| 1853 | |
| 1854 | static inline void hri_tccount16_set_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) |
| 1855 | { |
| 1856 | TC_CRITICAL_SECTION_ENTER(); |
| 1857 | ((Tc *)hw)->COUNT16.COUNT.reg |= TC_COUNT16_COUNT_COUNT(mask); |
| 1858 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 1859 | TC_CRITICAL_SECTION_LEAVE(); |
| 1860 | } |
| 1861 | |
| 1862 | static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_COUNT_bf(const void *const hw, |
| 1863 | hri_tccount16_count_reg_t mask) |
| 1864 | { |
| 1865 | uint16_t tmp; |
| 1866 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 1867 | tmp = ((Tc *)hw)->COUNT16.COUNT.reg; |
| 1868 | tmp = (tmp & TC_COUNT16_COUNT_COUNT(mask)) >> TC_COUNT16_COUNT_COUNT_Pos; |
| 1869 | return tmp; |
| 1870 | } |
| 1871 | |
| 1872 | static inline void hri_tccount16_write_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t data) |
| 1873 | { |
| 1874 | uint16_t tmp; |
| 1875 | TC_CRITICAL_SECTION_ENTER(); |
| 1876 | tmp = ((Tc *)hw)->COUNT16.COUNT.reg; |
| 1877 | tmp &= ~TC_COUNT16_COUNT_COUNT_Msk; |
| 1878 | tmp |= TC_COUNT16_COUNT_COUNT(data); |
| 1879 | ((Tc *)hw)->COUNT16.COUNT.reg = tmp; |
| 1880 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 1881 | TC_CRITICAL_SECTION_LEAVE(); |
| 1882 | } |
| 1883 | |
| 1884 | static inline void hri_tccount16_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) |
| 1885 | { |
| 1886 | TC_CRITICAL_SECTION_ENTER(); |
| 1887 | ((Tc *)hw)->COUNT16.COUNT.reg &= ~TC_COUNT16_COUNT_COUNT(mask); |
| 1888 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 1889 | TC_CRITICAL_SECTION_LEAVE(); |
| 1890 | } |
| 1891 | |
| 1892 | static inline void hri_tccount16_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) |
| 1893 | { |
| 1894 | TC_CRITICAL_SECTION_ENTER(); |
| 1895 | ((Tc *)hw)->COUNT16.COUNT.reg ^= TC_COUNT16_COUNT_COUNT(mask); |
| 1896 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 1897 | TC_CRITICAL_SECTION_LEAVE(); |
| 1898 | } |
| 1899 | |
| 1900 | static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_COUNT_bf(const void *const hw) |
| 1901 | { |
| 1902 | uint16_t tmp; |
| 1903 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 1904 | tmp = ((Tc *)hw)->COUNT16.COUNT.reg; |
| 1905 | tmp = (tmp & TC_COUNT16_COUNT_COUNT_Msk) >> TC_COUNT16_COUNT_COUNT_Pos; |
| 1906 | return tmp; |
| 1907 | } |
| 1908 | |
| 1909 | static inline void hri_tccount16_set_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) |
| 1910 | { |
| 1911 | TC_CRITICAL_SECTION_ENTER(); |
| 1912 | ((Tc *)hw)->COUNT16.COUNT.reg |= mask; |
| 1913 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 1914 | TC_CRITICAL_SECTION_LEAVE(); |
| 1915 | } |
| 1916 | |
| 1917 | static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_reg(const void *const hw, |
| 1918 | hri_tccount16_count_reg_t mask) |
| 1919 | { |
| 1920 | uint16_t tmp; |
| 1921 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 1922 | tmp = ((Tc *)hw)->COUNT16.COUNT.reg; |
| 1923 | tmp &= mask; |
| 1924 | return tmp; |
| 1925 | } |
| 1926 | |
| 1927 | static inline void hri_tccount16_write_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t data) |
| 1928 | { |
| 1929 | TC_CRITICAL_SECTION_ENTER(); |
| 1930 | ((Tc *)hw)->COUNT16.COUNT.reg = data; |
| 1931 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 1932 | TC_CRITICAL_SECTION_LEAVE(); |
| 1933 | } |
| 1934 | |
| 1935 | static inline void hri_tccount16_clear_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) |
| 1936 | { |
| 1937 | TC_CRITICAL_SECTION_ENTER(); |
| 1938 | ((Tc *)hw)->COUNT16.COUNT.reg &= ~mask; |
| 1939 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 1940 | TC_CRITICAL_SECTION_LEAVE(); |
| 1941 | } |
| 1942 | |
| 1943 | static inline void hri_tccount16_toggle_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) |
| 1944 | { |
| 1945 | TC_CRITICAL_SECTION_ENTER(); |
| 1946 | ((Tc *)hw)->COUNT16.COUNT.reg ^= mask; |
| 1947 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 1948 | TC_CRITICAL_SECTION_LEAVE(); |
| 1949 | } |
| 1950 | |
| 1951 | static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_reg(const void *const hw) |
| 1952 | { |
| 1953 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 1954 | return ((Tc *)hw)->COUNT16.COUNT.reg; |
| 1955 | } |
| 1956 | |
| 1957 | static inline void hri_tccount32_set_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) |
| 1958 | { |
| 1959 | TC_CRITICAL_SECTION_ENTER(); |
| 1960 | ((Tc *)hw)->COUNT32.COUNT.reg |= TC_COUNT32_COUNT_COUNT(mask); |
| 1961 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 1962 | TC_CRITICAL_SECTION_LEAVE(); |
| 1963 | } |
| 1964 | |
| 1965 | static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_COUNT_bf(const void *const hw, |
| 1966 | hri_tccount32_count_reg_t mask) |
| 1967 | { |
| 1968 | uint32_t tmp; |
| 1969 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 1970 | tmp = ((Tc *)hw)->COUNT32.COUNT.reg; |
| 1971 | tmp = (tmp & TC_COUNT32_COUNT_COUNT(mask)) >> TC_COUNT32_COUNT_COUNT_Pos; |
| 1972 | return tmp; |
| 1973 | } |
| 1974 | |
| 1975 | static inline void hri_tccount32_write_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t data) |
| 1976 | { |
| 1977 | uint32_t tmp; |
| 1978 | TC_CRITICAL_SECTION_ENTER(); |
| 1979 | tmp = ((Tc *)hw)->COUNT32.COUNT.reg; |
| 1980 | tmp &= ~TC_COUNT32_COUNT_COUNT_Msk; |
| 1981 | tmp |= TC_COUNT32_COUNT_COUNT(data); |
| 1982 | ((Tc *)hw)->COUNT32.COUNT.reg = tmp; |
| 1983 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 1984 | TC_CRITICAL_SECTION_LEAVE(); |
| 1985 | } |
| 1986 | |
| 1987 | static inline void hri_tccount32_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) |
| 1988 | { |
| 1989 | TC_CRITICAL_SECTION_ENTER(); |
| 1990 | ((Tc *)hw)->COUNT32.COUNT.reg &= ~TC_COUNT32_COUNT_COUNT(mask); |
| 1991 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 1992 | TC_CRITICAL_SECTION_LEAVE(); |
| 1993 | } |
| 1994 | |
| 1995 | static inline void hri_tccount32_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) |
| 1996 | { |
| 1997 | TC_CRITICAL_SECTION_ENTER(); |
| 1998 | ((Tc *)hw)->COUNT32.COUNT.reg ^= TC_COUNT32_COUNT_COUNT(mask); |
| 1999 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 2000 | TC_CRITICAL_SECTION_LEAVE(); |
| 2001 | } |
| 2002 | |
| 2003 | static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_COUNT_bf(const void *const hw) |
| 2004 | { |
| 2005 | uint32_t tmp; |
| 2006 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 2007 | tmp = ((Tc *)hw)->COUNT32.COUNT.reg; |
| 2008 | tmp = (tmp & TC_COUNT32_COUNT_COUNT_Msk) >> TC_COUNT32_COUNT_COUNT_Pos; |
| 2009 | return tmp; |
| 2010 | } |
| 2011 | |
| 2012 | static inline void hri_tccount32_set_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) |
| 2013 | { |
| 2014 | TC_CRITICAL_SECTION_ENTER(); |
| 2015 | ((Tc *)hw)->COUNT32.COUNT.reg |= mask; |
| 2016 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 2017 | TC_CRITICAL_SECTION_LEAVE(); |
| 2018 | } |
| 2019 | |
| 2020 | static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_reg(const void *const hw, |
| 2021 | hri_tccount32_count_reg_t mask) |
| 2022 | { |
| 2023 | uint32_t tmp; |
| 2024 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 2025 | tmp = ((Tc *)hw)->COUNT32.COUNT.reg; |
| 2026 | tmp &= mask; |
| 2027 | return tmp; |
| 2028 | } |
| 2029 | |
| 2030 | static inline void hri_tccount32_write_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t data) |
| 2031 | { |
| 2032 | TC_CRITICAL_SECTION_ENTER(); |
| 2033 | ((Tc *)hw)->COUNT32.COUNT.reg = data; |
| 2034 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 2035 | TC_CRITICAL_SECTION_LEAVE(); |
| 2036 | } |
| 2037 | |
| 2038 | static inline void hri_tccount32_clear_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) |
| 2039 | { |
| 2040 | TC_CRITICAL_SECTION_ENTER(); |
| 2041 | ((Tc *)hw)->COUNT32.COUNT.reg &= ~mask; |
| 2042 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 2043 | TC_CRITICAL_SECTION_LEAVE(); |
| 2044 | } |
| 2045 | |
| 2046 | static inline void hri_tccount32_toggle_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) |
| 2047 | { |
| 2048 | TC_CRITICAL_SECTION_ENTER(); |
| 2049 | ((Tc *)hw)->COUNT32.COUNT.reg ^= mask; |
| 2050 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 2051 | TC_CRITICAL_SECTION_LEAVE(); |
| 2052 | } |
| 2053 | |
| 2054 | static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_reg(const void *const hw) |
| 2055 | { |
| 2056 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); |
| 2057 | return ((Tc *)hw)->COUNT32.COUNT.reg; |
| 2058 | } |
| 2059 | |
| 2060 | static inline void hri_tccount8_set_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) |
| 2061 | { |
| 2062 | TC_CRITICAL_SECTION_ENTER(); |
| 2063 | ((Tc *)hw)->COUNT8.PER.reg |= TC_COUNT8_PER_PER(mask); |
| 2064 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); |
| 2065 | TC_CRITICAL_SECTION_LEAVE(); |
| 2066 | } |
| 2067 | |
| 2068 | static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) |
| 2069 | { |
| 2070 | uint8_t tmp; |
| 2071 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); |
| 2072 | tmp = ((Tc *)hw)->COUNT8.PER.reg; |
| 2073 | tmp = (tmp & TC_COUNT8_PER_PER(mask)) >> TC_COUNT8_PER_PER_Pos; |
| 2074 | return tmp; |
| 2075 | } |
| 2076 | |
| 2077 | static inline void hri_tccount8_write_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t data) |
| 2078 | { |
| 2079 | uint8_t tmp; |
| 2080 | TC_CRITICAL_SECTION_ENTER(); |
| 2081 | tmp = ((Tc *)hw)->COUNT8.PER.reg; |
| 2082 | tmp &= ~TC_COUNT8_PER_PER_Msk; |
| 2083 | tmp |= TC_COUNT8_PER_PER(data); |
| 2084 | ((Tc *)hw)->COUNT8.PER.reg = tmp; |
| 2085 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); |
| 2086 | TC_CRITICAL_SECTION_LEAVE(); |
| 2087 | } |
| 2088 | |
| 2089 | static inline void hri_tccount8_clear_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) |
| 2090 | { |
| 2091 | TC_CRITICAL_SECTION_ENTER(); |
| 2092 | ((Tc *)hw)->COUNT8.PER.reg &= ~TC_COUNT8_PER_PER(mask); |
| 2093 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); |
| 2094 | TC_CRITICAL_SECTION_LEAVE(); |
| 2095 | } |
| 2096 | |
| 2097 | static inline void hri_tccount8_toggle_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) |
| 2098 | { |
| 2099 | TC_CRITICAL_SECTION_ENTER(); |
| 2100 | ((Tc *)hw)->COUNT8.PER.reg ^= TC_COUNT8_PER_PER(mask); |
| 2101 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); |
| 2102 | TC_CRITICAL_SECTION_LEAVE(); |
| 2103 | } |
| 2104 | |
| 2105 | static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_PER_bf(const void *const hw) |
| 2106 | { |
| 2107 | uint8_t tmp; |
| 2108 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); |
| 2109 | tmp = ((Tc *)hw)->COUNT8.PER.reg; |
| 2110 | tmp = (tmp & TC_COUNT8_PER_PER_Msk) >> TC_COUNT8_PER_PER_Pos; |
| 2111 | return tmp; |
| 2112 | } |
| 2113 | |
| 2114 | static inline void hri_tccount8_set_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) |
| 2115 | { |
| 2116 | TC_CRITICAL_SECTION_ENTER(); |
| 2117 | ((Tc *)hw)->COUNT8.PER.reg |= mask; |
| 2118 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); |
| 2119 | TC_CRITICAL_SECTION_LEAVE(); |
| 2120 | } |
| 2121 | |
| 2122 | static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) |
| 2123 | { |
| 2124 | uint8_t tmp; |
| 2125 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); |
| 2126 | tmp = ((Tc *)hw)->COUNT8.PER.reg; |
| 2127 | tmp &= mask; |
| 2128 | return tmp; |
| 2129 | } |
| 2130 | |
| 2131 | static inline void hri_tccount8_write_PER_reg(const void *const hw, hri_tccount8_per_reg_t data) |
| 2132 | { |
| 2133 | TC_CRITICAL_SECTION_ENTER(); |
| 2134 | ((Tc *)hw)->COUNT8.PER.reg = data; |
| 2135 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); |
| 2136 | TC_CRITICAL_SECTION_LEAVE(); |
| 2137 | } |
| 2138 | |
| 2139 | static inline void hri_tccount8_clear_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) |
| 2140 | { |
| 2141 | TC_CRITICAL_SECTION_ENTER(); |
| 2142 | ((Tc *)hw)->COUNT8.PER.reg &= ~mask; |
| 2143 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); |
| 2144 | TC_CRITICAL_SECTION_LEAVE(); |
| 2145 | } |
| 2146 | |
| 2147 | static inline void hri_tccount8_toggle_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) |
| 2148 | { |
| 2149 | TC_CRITICAL_SECTION_ENTER(); |
| 2150 | ((Tc *)hw)->COUNT8.PER.reg ^= mask; |
| 2151 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); |
| 2152 | TC_CRITICAL_SECTION_LEAVE(); |
| 2153 | } |
| 2154 | |
| 2155 | static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_reg(const void *const hw) |
| 2156 | { |
| 2157 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); |
| 2158 | return ((Tc *)hw)->COUNT8.PER.reg; |
| 2159 | } |
| 2160 | |
| 2161 | static inline void hri_tccount8_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) |
| 2162 | { |
| 2163 | TC_CRITICAL_SECTION_ENTER(); |
| 2164 | ((Tc *)hw)->COUNT8.CC[index].reg |= TC_COUNT8_CC_CC(mask); |
| 2165 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2166 | TC_CRITICAL_SECTION_LEAVE(); |
| 2167 | } |
| 2168 | |
| 2169 | static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_CC_bf(const void *const hw, uint8_t index, |
| 2170 | hri_tccount8_cc_reg_t mask) |
| 2171 | { |
| 2172 | uint8_t tmp; |
| 2173 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2174 | tmp = ((Tc *)hw)->COUNT8.CC[index].reg; |
| 2175 | tmp = (tmp & TC_COUNT8_CC_CC(mask)) >> TC_COUNT8_CC_CC_Pos; |
| 2176 | return tmp; |
| 2177 | } |
| 2178 | |
| 2179 | static inline void hri_tccount8_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data) |
| 2180 | { |
| 2181 | uint8_t tmp; |
| 2182 | TC_CRITICAL_SECTION_ENTER(); |
| 2183 | tmp = ((Tc *)hw)->COUNT8.CC[index].reg; |
| 2184 | tmp &= ~TC_COUNT8_CC_CC_Msk; |
| 2185 | tmp |= TC_COUNT8_CC_CC(data); |
| 2186 | ((Tc *)hw)->COUNT8.CC[index].reg = tmp; |
| 2187 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2188 | TC_CRITICAL_SECTION_LEAVE(); |
| 2189 | } |
| 2190 | |
| 2191 | static inline void hri_tccount8_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) |
| 2192 | { |
| 2193 | TC_CRITICAL_SECTION_ENTER(); |
| 2194 | ((Tc *)hw)->COUNT8.CC[index].reg &= ~TC_COUNT8_CC_CC(mask); |
| 2195 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2196 | TC_CRITICAL_SECTION_LEAVE(); |
| 2197 | } |
| 2198 | |
| 2199 | static inline void hri_tccount8_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) |
| 2200 | { |
| 2201 | TC_CRITICAL_SECTION_ENTER(); |
| 2202 | ((Tc *)hw)->COUNT8.CC[index].reg ^= TC_COUNT8_CC_CC(mask); |
| 2203 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2204 | TC_CRITICAL_SECTION_LEAVE(); |
| 2205 | } |
| 2206 | |
| 2207 | static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_CC_bf(const void *const hw, uint8_t index) |
| 2208 | { |
| 2209 | uint8_t tmp; |
| 2210 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2211 | tmp = ((Tc *)hw)->COUNT8.CC[index].reg; |
| 2212 | tmp = (tmp & TC_COUNT8_CC_CC_Msk) >> TC_COUNT8_CC_CC_Pos; |
| 2213 | return tmp; |
| 2214 | } |
| 2215 | |
| 2216 | static inline void hri_tccount8_set_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) |
| 2217 | { |
| 2218 | TC_CRITICAL_SECTION_ENTER(); |
| 2219 | ((Tc *)hw)->COUNT8.CC[index].reg |= mask; |
| 2220 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2221 | TC_CRITICAL_SECTION_LEAVE(); |
| 2222 | } |
| 2223 | |
| 2224 | static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_reg(const void *const hw, uint8_t index, |
| 2225 | hri_tccount8_cc_reg_t mask) |
| 2226 | { |
| 2227 | uint8_t tmp; |
| 2228 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2229 | tmp = ((Tc *)hw)->COUNT8.CC[index].reg; |
| 2230 | tmp &= mask; |
| 2231 | return tmp; |
| 2232 | } |
| 2233 | |
| 2234 | static inline void hri_tccount8_write_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data) |
| 2235 | { |
| 2236 | TC_CRITICAL_SECTION_ENTER(); |
| 2237 | ((Tc *)hw)->COUNT8.CC[index].reg = data; |
| 2238 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2239 | TC_CRITICAL_SECTION_LEAVE(); |
| 2240 | } |
| 2241 | |
| 2242 | static inline void hri_tccount8_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) |
| 2243 | { |
| 2244 | TC_CRITICAL_SECTION_ENTER(); |
| 2245 | ((Tc *)hw)->COUNT8.CC[index].reg &= ~mask; |
| 2246 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2247 | TC_CRITICAL_SECTION_LEAVE(); |
| 2248 | } |
| 2249 | |
| 2250 | static inline void hri_tccount8_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) |
| 2251 | { |
| 2252 | TC_CRITICAL_SECTION_ENTER(); |
| 2253 | ((Tc *)hw)->COUNT8.CC[index].reg ^= mask; |
| 2254 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2255 | TC_CRITICAL_SECTION_LEAVE(); |
| 2256 | } |
| 2257 | |
| 2258 | static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_reg(const void *const hw, uint8_t index) |
| 2259 | { |
| 2260 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2261 | return ((Tc *)hw)->COUNT8.CC[index].reg; |
| 2262 | } |
| 2263 | |
| 2264 | static inline void hri_tccount16_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) |
| 2265 | { |
| 2266 | TC_CRITICAL_SECTION_ENTER(); |
| 2267 | ((Tc *)hw)->COUNT16.CC[index].reg |= TC_COUNT16_CC_CC(mask); |
| 2268 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2269 | TC_CRITICAL_SECTION_LEAVE(); |
| 2270 | } |
| 2271 | |
| 2272 | static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_CC_bf(const void *const hw, uint8_t index, |
| 2273 | hri_tccount16_cc_reg_t mask) |
| 2274 | { |
| 2275 | uint16_t tmp; |
| 2276 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2277 | tmp = ((Tc *)hw)->COUNT16.CC[index].reg; |
| 2278 | tmp = (tmp & TC_COUNT16_CC_CC(mask)) >> TC_COUNT16_CC_CC_Pos; |
| 2279 | return tmp; |
| 2280 | } |
| 2281 | |
| 2282 | static inline void hri_tccount16_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data) |
| 2283 | { |
| 2284 | uint16_t tmp; |
| 2285 | TC_CRITICAL_SECTION_ENTER(); |
| 2286 | tmp = ((Tc *)hw)->COUNT16.CC[index].reg; |
| 2287 | tmp &= ~TC_COUNT16_CC_CC_Msk; |
| 2288 | tmp |= TC_COUNT16_CC_CC(data); |
| 2289 | ((Tc *)hw)->COUNT16.CC[index].reg = tmp; |
| 2290 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2291 | TC_CRITICAL_SECTION_LEAVE(); |
| 2292 | } |
| 2293 | |
| 2294 | static inline void hri_tccount16_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) |
| 2295 | { |
| 2296 | TC_CRITICAL_SECTION_ENTER(); |
| 2297 | ((Tc *)hw)->COUNT16.CC[index].reg &= ~TC_COUNT16_CC_CC(mask); |
| 2298 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2299 | TC_CRITICAL_SECTION_LEAVE(); |
| 2300 | } |
| 2301 | |
| 2302 | static inline void hri_tccount16_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) |
| 2303 | { |
| 2304 | TC_CRITICAL_SECTION_ENTER(); |
| 2305 | ((Tc *)hw)->COUNT16.CC[index].reg ^= TC_COUNT16_CC_CC(mask); |
| 2306 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2307 | TC_CRITICAL_SECTION_LEAVE(); |
| 2308 | } |
| 2309 | |
| 2310 | static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_CC_bf(const void *const hw, uint8_t index) |
| 2311 | { |
| 2312 | uint16_t tmp; |
| 2313 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2314 | tmp = ((Tc *)hw)->COUNT16.CC[index].reg; |
| 2315 | tmp = (tmp & TC_COUNT16_CC_CC_Msk) >> TC_COUNT16_CC_CC_Pos; |
| 2316 | return tmp; |
| 2317 | } |
| 2318 | |
| 2319 | static inline void hri_tccount16_set_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) |
| 2320 | { |
| 2321 | TC_CRITICAL_SECTION_ENTER(); |
| 2322 | ((Tc *)hw)->COUNT16.CC[index].reg |= mask; |
| 2323 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2324 | TC_CRITICAL_SECTION_LEAVE(); |
| 2325 | } |
| 2326 | |
| 2327 | static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_reg(const void *const hw, uint8_t index, |
| 2328 | hri_tccount16_cc_reg_t mask) |
| 2329 | { |
| 2330 | uint16_t tmp; |
| 2331 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2332 | tmp = ((Tc *)hw)->COUNT16.CC[index].reg; |
| 2333 | tmp &= mask; |
| 2334 | return tmp; |
| 2335 | } |
| 2336 | |
| 2337 | static inline void hri_tccount16_write_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data) |
| 2338 | { |
| 2339 | TC_CRITICAL_SECTION_ENTER(); |
| 2340 | ((Tc *)hw)->COUNT16.CC[index].reg = data; |
| 2341 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2342 | TC_CRITICAL_SECTION_LEAVE(); |
| 2343 | } |
| 2344 | |
| 2345 | static inline void hri_tccount16_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) |
| 2346 | { |
| 2347 | TC_CRITICAL_SECTION_ENTER(); |
| 2348 | ((Tc *)hw)->COUNT16.CC[index].reg &= ~mask; |
| 2349 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2350 | TC_CRITICAL_SECTION_LEAVE(); |
| 2351 | } |
| 2352 | |
| 2353 | static inline void hri_tccount16_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) |
| 2354 | { |
| 2355 | TC_CRITICAL_SECTION_ENTER(); |
| 2356 | ((Tc *)hw)->COUNT16.CC[index].reg ^= mask; |
| 2357 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2358 | TC_CRITICAL_SECTION_LEAVE(); |
| 2359 | } |
| 2360 | |
| 2361 | static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_reg(const void *const hw, uint8_t index) |
| 2362 | { |
| 2363 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2364 | return ((Tc *)hw)->COUNT16.CC[index].reg; |
| 2365 | } |
| 2366 | |
| 2367 | static inline void hri_tccount32_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) |
| 2368 | { |
| 2369 | TC_CRITICAL_SECTION_ENTER(); |
| 2370 | ((Tc *)hw)->COUNT32.CC[index].reg |= TC_COUNT32_CC_CC(mask); |
| 2371 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2372 | TC_CRITICAL_SECTION_LEAVE(); |
| 2373 | } |
| 2374 | |
| 2375 | static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_CC_bf(const void *const hw, uint8_t index, |
| 2376 | hri_tccount32_cc_reg_t mask) |
| 2377 | { |
| 2378 | uint32_t tmp; |
| 2379 | tmp = ((Tc *)hw)->COUNT32.CC[index].reg; |
| 2380 | tmp = (tmp & TC_COUNT32_CC_CC(mask)) >> TC_COUNT32_CC_CC_Pos; |
| 2381 | return tmp; |
| 2382 | } |
| 2383 | |
| 2384 | static inline void hri_tccount32_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) |
| 2385 | { |
| 2386 | uint32_t tmp; |
| 2387 | TC_CRITICAL_SECTION_ENTER(); |
| 2388 | tmp = ((Tc *)hw)->COUNT32.CC[index].reg; |
| 2389 | tmp &= ~TC_COUNT32_CC_CC_Msk; |
| 2390 | tmp |= TC_COUNT32_CC_CC(data); |
| 2391 | ((Tc *)hw)->COUNT32.CC[index].reg = tmp; |
| 2392 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2393 | TC_CRITICAL_SECTION_LEAVE(); |
| 2394 | } |
| 2395 | |
| 2396 | static inline void hri_tccount32_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) |
| 2397 | { |
| 2398 | TC_CRITICAL_SECTION_ENTER(); |
| 2399 | ((Tc *)hw)->COUNT32.CC[index].reg &= ~TC_COUNT32_CC_CC(mask); |
| 2400 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2401 | TC_CRITICAL_SECTION_LEAVE(); |
| 2402 | } |
| 2403 | |
| 2404 | static inline void hri_tccount32_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) |
| 2405 | { |
| 2406 | TC_CRITICAL_SECTION_ENTER(); |
| 2407 | ((Tc *)hw)->COUNT32.CC[index].reg ^= TC_COUNT32_CC_CC(mask); |
| 2408 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2409 | TC_CRITICAL_SECTION_LEAVE(); |
| 2410 | } |
| 2411 | |
| 2412 | static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_CC_bf(const void *const hw, uint8_t index) |
| 2413 | { |
| 2414 | uint32_t tmp; |
| 2415 | tmp = ((Tc *)hw)->COUNT32.CC[index].reg; |
| 2416 | tmp = (tmp & TC_COUNT32_CC_CC_Msk) >> TC_COUNT32_CC_CC_Pos; |
| 2417 | return tmp; |
| 2418 | } |
| 2419 | |
| 2420 | static inline void hri_tccount32_set_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) |
| 2421 | { |
| 2422 | TC_CRITICAL_SECTION_ENTER(); |
| 2423 | ((Tc *)hw)->COUNT32.CC[index].reg |= mask; |
| 2424 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2425 | TC_CRITICAL_SECTION_LEAVE(); |
| 2426 | } |
| 2427 | |
| 2428 | static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_reg(const void *const hw, uint8_t index, |
| 2429 | hri_tccount32_cc_reg_t mask) |
| 2430 | { |
| 2431 | uint32_t tmp; |
| 2432 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2433 | tmp = ((Tc *)hw)->COUNT32.CC[index].reg; |
| 2434 | tmp &= mask; |
| 2435 | return tmp; |
| 2436 | } |
| 2437 | |
| 2438 | static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) |
| 2439 | { |
| 2440 | TC_CRITICAL_SECTION_ENTER(); |
| 2441 | ((Tc *)hw)->COUNT32.CC[index].reg = data; |
| 2442 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2443 | TC_CRITICAL_SECTION_LEAVE(); |
| 2444 | } |
| 2445 | |
| 2446 | static inline void hri_tccount32_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) |
| 2447 | { |
| 2448 | TC_CRITICAL_SECTION_ENTER(); |
| 2449 | ((Tc *)hw)->COUNT32.CC[index].reg &= ~mask; |
| 2450 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2451 | TC_CRITICAL_SECTION_LEAVE(); |
| 2452 | } |
| 2453 | |
| 2454 | static inline void hri_tccount32_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) |
| 2455 | { |
| 2456 | TC_CRITICAL_SECTION_ENTER(); |
| 2457 | ((Tc *)hw)->COUNT32.CC[index].reg ^= mask; |
| 2458 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2459 | TC_CRITICAL_SECTION_LEAVE(); |
| 2460 | } |
| 2461 | |
| 2462 | static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_reg(const void *const hw, uint8_t index) |
| 2463 | { |
| 2464 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); |
| 2465 | return ((Tc *)hw)->COUNT32.CC[index].reg; |
| 2466 | } |
| 2467 | |
| 2468 | static inline void hri_tccount8_set_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) |
| 2469 | { |
| 2470 | TC_CRITICAL_SECTION_ENTER(); |
| 2471 | ((Tc *)hw)->COUNT8.PERBUF.reg |= TC_COUNT8_PERBUF_PERBUF(mask); |
| 2472 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2473 | TC_CRITICAL_SECTION_LEAVE(); |
| 2474 | } |
| 2475 | |
| 2476 | static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_PERBUF_bf(const void *const hw, |
| 2477 | hri_tccount8_perbuf_reg_t mask) |
| 2478 | { |
| 2479 | uint8_t tmp; |
| 2480 | tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; |
| 2481 | tmp = (tmp & TC_COUNT8_PERBUF_PERBUF(mask)) >> TC_COUNT8_PERBUF_PERBUF_Pos; |
| 2482 | return tmp; |
| 2483 | } |
| 2484 | |
| 2485 | static inline void hri_tccount8_write_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t data) |
| 2486 | { |
| 2487 | uint8_t tmp; |
| 2488 | TC_CRITICAL_SECTION_ENTER(); |
| 2489 | tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; |
| 2490 | tmp &= ~TC_COUNT8_PERBUF_PERBUF_Msk; |
| 2491 | tmp |= TC_COUNT8_PERBUF_PERBUF(data); |
| 2492 | ((Tc *)hw)->COUNT8.PERBUF.reg = tmp; |
| 2493 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2494 | TC_CRITICAL_SECTION_LEAVE(); |
| 2495 | } |
| 2496 | |
| 2497 | static inline void hri_tccount8_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) |
| 2498 | { |
| 2499 | TC_CRITICAL_SECTION_ENTER(); |
| 2500 | ((Tc *)hw)->COUNT8.PERBUF.reg &= ~TC_COUNT8_PERBUF_PERBUF(mask); |
| 2501 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2502 | TC_CRITICAL_SECTION_LEAVE(); |
| 2503 | } |
| 2504 | |
| 2505 | static inline void hri_tccount8_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) |
| 2506 | { |
| 2507 | TC_CRITICAL_SECTION_ENTER(); |
| 2508 | ((Tc *)hw)->COUNT8.PERBUF.reg ^= TC_COUNT8_PERBUF_PERBUF(mask); |
| 2509 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2510 | TC_CRITICAL_SECTION_LEAVE(); |
| 2511 | } |
| 2512 | |
| 2513 | static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_PERBUF_bf(const void *const hw) |
| 2514 | { |
| 2515 | uint8_t tmp; |
| 2516 | tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; |
| 2517 | tmp = (tmp & TC_COUNT8_PERBUF_PERBUF_Msk) >> TC_COUNT8_PERBUF_PERBUF_Pos; |
| 2518 | return tmp; |
| 2519 | } |
| 2520 | |
| 2521 | static inline void hri_tccount8_set_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) |
| 2522 | { |
| 2523 | TC_CRITICAL_SECTION_ENTER(); |
| 2524 | ((Tc *)hw)->COUNT8.PERBUF.reg |= mask; |
| 2525 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2526 | TC_CRITICAL_SECTION_LEAVE(); |
| 2527 | } |
| 2528 | |
| 2529 | static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_reg(const void *const hw, |
| 2530 | hri_tccount8_perbuf_reg_t mask) |
| 2531 | { |
| 2532 | uint8_t tmp; |
| 2533 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2534 | tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; |
| 2535 | tmp &= mask; |
| 2536 | return tmp; |
| 2537 | } |
| 2538 | |
| 2539 | static inline void hri_tccount8_write_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t data) |
| 2540 | { |
| 2541 | TC_CRITICAL_SECTION_ENTER(); |
| 2542 | ((Tc *)hw)->COUNT8.PERBUF.reg = data; |
| 2543 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2544 | TC_CRITICAL_SECTION_LEAVE(); |
| 2545 | } |
| 2546 | |
| 2547 | static inline void hri_tccount8_clear_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) |
| 2548 | { |
| 2549 | TC_CRITICAL_SECTION_ENTER(); |
| 2550 | ((Tc *)hw)->COUNT8.PERBUF.reg &= ~mask; |
| 2551 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2552 | TC_CRITICAL_SECTION_LEAVE(); |
| 2553 | } |
| 2554 | |
| 2555 | static inline void hri_tccount8_toggle_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) |
| 2556 | { |
| 2557 | TC_CRITICAL_SECTION_ENTER(); |
| 2558 | ((Tc *)hw)->COUNT8.PERBUF.reg ^= mask; |
| 2559 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2560 | TC_CRITICAL_SECTION_LEAVE(); |
| 2561 | } |
| 2562 | |
| 2563 | static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_reg(const void *const hw) |
| 2564 | { |
| 2565 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2566 | return ((Tc *)hw)->COUNT8.PERBUF.reg; |
| 2567 | } |
| 2568 | |
| 2569 | static inline void hri_tccount8_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) |
| 2570 | { |
| 2571 | TC_CRITICAL_SECTION_ENTER(); |
| 2572 | ((Tc *)hw)->COUNT8.CCBUF[index].reg |= TC_COUNT8_CCBUF_CCBUF(mask); |
| 2573 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2574 | TC_CRITICAL_SECTION_LEAVE(); |
| 2575 | } |
| 2576 | |
| 2577 | static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, |
| 2578 | hri_tccount8_ccbuf_reg_t mask) |
| 2579 | { |
| 2580 | uint8_t tmp; |
| 2581 | tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; |
| 2582 | tmp = (tmp & TC_COUNT8_CCBUF_CCBUF(mask)) >> TC_COUNT8_CCBUF_CCBUF_Pos; |
| 2583 | return tmp; |
| 2584 | } |
| 2585 | |
| 2586 | static inline void hri_tccount8_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data) |
| 2587 | { |
| 2588 | uint8_t tmp; |
| 2589 | TC_CRITICAL_SECTION_ENTER(); |
| 2590 | tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; |
| 2591 | tmp &= ~TC_COUNT8_CCBUF_CCBUF_Msk; |
| 2592 | tmp |= TC_COUNT8_CCBUF_CCBUF(data); |
| 2593 | ((Tc *)hw)->COUNT8.CCBUF[index].reg = tmp; |
| 2594 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2595 | TC_CRITICAL_SECTION_LEAVE(); |
| 2596 | } |
| 2597 | |
| 2598 | static inline void hri_tccount8_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) |
| 2599 | { |
| 2600 | TC_CRITICAL_SECTION_ENTER(); |
| 2601 | ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~TC_COUNT8_CCBUF_CCBUF(mask); |
| 2602 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2603 | TC_CRITICAL_SECTION_LEAVE(); |
| 2604 | } |
| 2605 | |
| 2606 | static inline void hri_tccount8_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, |
| 2607 | hri_tccount8_ccbuf_reg_t mask) |
| 2608 | { |
| 2609 | TC_CRITICAL_SECTION_ENTER(); |
| 2610 | ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= TC_COUNT8_CCBUF_CCBUF(mask); |
| 2611 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2612 | TC_CRITICAL_SECTION_LEAVE(); |
| 2613 | } |
| 2614 | |
| 2615 | static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) |
| 2616 | { |
| 2617 | uint8_t tmp; |
| 2618 | tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; |
| 2619 | tmp = (tmp & TC_COUNT8_CCBUF_CCBUF_Msk) >> TC_COUNT8_CCBUF_CCBUF_Pos; |
| 2620 | return tmp; |
| 2621 | } |
| 2622 | |
| 2623 | static inline void hri_tccount8_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) |
| 2624 | { |
| 2625 | TC_CRITICAL_SECTION_ENTER(); |
| 2626 | ((Tc *)hw)->COUNT8.CCBUF[index].reg |= mask; |
| 2627 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2628 | TC_CRITICAL_SECTION_LEAVE(); |
| 2629 | } |
| 2630 | |
| 2631 | static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_reg(const void *const hw, uint8_t index, |
| 2632 | hri_tccount8_ccbuf_reg_t mask) |
| 2633 | { |
| 2634 | uint8_t tmp; |
| 2635 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2636 | tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; |
| 2637 | tmp &= mask; |
| 2638 | return tmp; |
| 2639 | } |
| 2640 | |
| 2641 | static inline void hri_tccount8_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data) |
| 2642 | { |
| 2643 | TC_CRITICAL_SECTION_ENTER(); |
| 2644 | ((Tc *)hw)->COUNT8.CCBUF[index].reg = data; |
| 2645 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2646 | TC_CRITICAL_SECTION_LEAVE(); |
| 2647 | } |
| 2648 | |
| 2649 | static inline void hri_tccount8_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) |
| 2650 | { |
| 2651 | TC_CRITICAL_SECTION_ENTER(); |
| 2652 | ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~mask; |
| 2653 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2654 | TC_CRITICAL_SECTION_LEAVE(); |
| 2655 | } |
| 2656 | |
| 2657 | static inline void hri_tccount8_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) |
| 2658 | { |
| 2659 | TC_CRITICAL_SECTION_ENTER(); |
| 2660 | ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= mask; |
| 2661 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2662 | TC_CRITICAL_SECTION_LEAVE(); |
| 2663 | } |
| 2664 | |
| 2665 | static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_reg(const void *const hw, uint8_t index) |
| 2666 | { |
| 2667 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2668 | return ((Tc *)hw)->COUNT8.CCBUF[index].reg; |
| 2669 | } |
| 2670 | |
| 2671 | static inline void hri_tccount16_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) |
| 2672 | { |
| 2673 | TC_CRITICAL_SECTION_ENTER(); |
| 2674 | ((Tc *)hw)->COUNT16.CCBUF[index].reg |= TC_COUNT16_CCBUF_CCBUF(mask); |
| 2675 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2676 | TC_CRITICAL_SECTION_LEAVE(); |
| 2677 | } |
| 2678 | |
| 2679 | static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, |
| 2680 | hri_tccount16_ccbuf_reg_t mask) |
| 2681 | { |
| 2682 | uint16_t tmp; |
| 2683 | tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; |
| 2684 | tmp = (tmp & TC_COUNT16_CCBUF_CCBUF(mask)) >> TC_COUNT16_CCBUF_CCBUF_Pos; |
| 2685 | return tmp; |
| 2686 | } |
| 2687 | |
| 2688 | static inline void hri_tccount16_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, |
| 2689 | hri_tccount16_ccbuf_reg_t data) |
| 2690 | { |
| 2691 | uint16_t tmp; |
| 2692 | TC_CRITICAL_SECTION_ENTER(); |
| 2693 | tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; |
| 2694 | tmp &= ~TC_COUNT16_CCBUF_CCBUF_Msk; |
| 2695 | tmp |= TC_COUNT16_CCBUF_CCBUF(data); |
| 2696 | ((Tc *)hw)->COUNT16.CCBUF[index].reg = tmp; |
| 2697 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2698 | TC_CRITICAL_SECTION_LEAVE(); |
| 2699 | } |
| 2700 | |
| 2701 | static inline void hri_tccount16_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, |
| 2702 | hri_tccount16_ccbuf_reg_t mask) |
| 2703 | { |
| 2704 | TC_CRITICAL_SECTION_ENTER(); |
| 2705 | ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~TC_COUNT16_CCBUF_CCBUF(mask); |
| 2706 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2707 | TC_CRITICAL_SECTION_LEAVE(); |
| 2708 | } |
| 2709 | |
| 2710 | static inline void hri_tccount16_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, |
| 2711 | hri_tccount16_ccbuf_reg_t mask) |
| 2712 | { |
| 2713 | TC_CRITICAL_SECTION_ENTER(); |
| 2714 | ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= TC_COUNT16_CCBUF_CCBUF(mask); |
| 2715 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2716 | TC_CRITICAL_SECTION_LEAVE(); |
| 2717 | } |
| 2718 | |
| 2719 | static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) |
| 2720 | { |
| 2721 | uint16_t tmp; |
| 2722 | tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; |
| 2723 | tmp = (tmp & TC_COUNT16_CCBUF_CCBUF_Msk) >> TC_COUNT16_CCBUF_CCBUF_Pos; |
| 2724 | return tmp; |
| 2725 | } |
| 2726 | |
| 2727 | static inline void hri_tccount16_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) |
| 2728 | { |
| 2729 | TC_CRITICAL_SECTION_ENTER(); |
| 2730 | ((Tc *)hw)->COUNT16.CCBUF[index].reg |= mask; |
| 2731 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2732 | TC_CRITICAL_SECTION_LEAVE(); |
| 2733 | } |
| 2734 | |
| 2735 | static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_reg(const void *const hw, uint8_t index, |
| 2736 | hri_tccount16_ccbuf_reg_t mask) |
| 2737 | { |
| 2738 | uint16_t tmp; |
| 2739 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2740 | tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; |
| 2741 | tmp &= mask; |
| 2742 | return tmp; |
| 2743 | } |
| 2744 | |
| 2745 | static inline void hri_tccount16_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t data) |
| 2746 | { |
| 2747 | TC_CRITICAL_SECTION_ENTER(); |
| 2748 | ((Tc *)hw)->COUNT16.CCBUF[index].reg = data; |
| 2749 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2750 | TC_CRITICAL_SECTION_LEAVE(); |
| 2751 | } |
| 2752 | |
| 2753 | static inline void hri_tccount16_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) |
| 2754 | { |
| 2755 | TC_CRITICAL_SECTION_ENTER(); |
| 2756 | ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~mask; |
| 2757 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2758 | TC_CRITICAL_SECTION_LEAVE(); |
| 2759 | } |
| 2760 | |
| 2761 | static inline void hri_tccount16_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) |
| 2762 | { |
| 2763 | TC_CRITICAL_SECTION_ENTER(); |
| 2764 | ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= mask; |
| 2765 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2766 | TC_CRITICAL_SECTION_LEAVE(); |
| 2767 | } |
| 2768 | |
| 2769 | static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_reg(const void *const hw, uint8_t index) |
| 2770 | { |
| 2771 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2772 | return ((Tc *)hw)->COUNT16.CCBUF[index].reg; |
| 2773 | } |
| 2774 | |
| 2775 | static inline void hri_tccount32_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) |
| 2776 | { |
| 2777 | TC_CRITICAL_SECTION_ENTER(); |
| 2778 | ((Tc *)hw)->COUNT32.CCBUF[index].reg |= TC_COUNT32_CCBUF_CCBUF(mask); |
| 2779 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2780 | TC_CRITICAL_SECTION_LEAVE(); |
| 2781 | } |
| 2782 | |
| 2783 | static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, |
| 2784 | hri_tccount32_ccbuf_reg_t mask) |
| 2785 | { |
| 2786 | uint32_t tmp; |
| 2787 | tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; |
| 2788 | tmp = (tmp & TC_COUNT32_CCBUF_CCBUF(mask)) >> TC_COUNT32_CCBUF_CCBUF_Pos; |
| 2789 | return tmp; |
| 2790 | } |
| 2791 | |
| 2792 | static inline void hri_tccount32_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, |
| 2793 | hri_tccount32_ccbuf_reg_t data) |
| 2794 | { |
| 2795 | uint32_t tmp; |
| 2796 | TC_CRITICAL_SECTION_ENTER(); |
| 2797 | tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; |
| 2798 | tmp &= ~TC_COUNT32_CCBUF_CCBUF_Msk; |
| 2799 | tmp |= TC_COUNT32_CCBUF_CCBUF(data); |
| 2800 | ((Tc *)hw)->COUNT32.CCBUF[index].reg = tmp; |
| 2801 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2802 | TC_CRITICAL_SECTION_LEAVE(); |
| 2803 | } |
| 2804 | |
| 2805 | static inline void hri_tccount32_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, |
| 2806 | hri_tccount32_ccbuf_reg_t mask) |
| 2807 | { |
| 2808 | TC_CRITICAL_SECTION_ENTER(); |
| 2809 | ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~TC_COUNT32_CCBUF_CCBUF(mask); |
| 2810 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2811 | TC_CRITICAL_SECTION_LEAVE(); |
| 2812 | } |
| 2813 | |
| 2814 | static inline void hri_tccount32_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, |
| 2815 | hri_tccount32_ccbuf_reg_t mask) |
| 2816 | { |
| 2817 | TC_CRITICAL_SECTION_ENTER(); |
| 2818 | ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= TC_COUNT32_CCBUF_CCBUF(mask); |
| 2819 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2820 | TC_CRITICAL_SECTION_LEAVE(); |
| 2821 | } |
| 2822 | |
| 2823 | static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) |
| 2824 | { |
| 2825 | uint32_t tmp; |
| 2826 | tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; |
| 2827 | tmp = (tmp & TC_COUNT32_CCBUF_CCBUF_Msk) >> TC_COUNT32_CCBUF_CCBUF_Pos; |
| 2828 | return tmp; |
| 2829 | } |
| 2830 | |
| 2831 | static inline void hri_tccount32_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) |
| 2832 | { |
| 2833 | TC_CRITICAL_SECTION_ENTER(); |
| 2834 | ((Tc *)hw)->COUNT32.CCBUF[index].reg |= mask; |
| 2835 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2836 | TC_CRITICAL_SECTION_LEAVE(); |
| 2837 | } |
| 2838 | |
| 2839 | static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_reg(const void *const hw, uint8_t index, |
| 2840 | hri_tccount32_ccbuf_reg_t mask) |
| 2841 | { |
| 2842 | uint32_t tmp; |
| 2843 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2844 | tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; |
| 2845 | tmp &= mask; |
| 2846 | return tmp; |
| 2847 | } |
| 2848 | |
| 2849 | static inline void hri_tccount32_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t data) |
| 2850 | { |
| 2851 | TC_CRITICAL_SECTION_ENTER(); |
| 2852 | ((Tc *)hw)->COUNT32.CCBUF[index].reg = data; |
| 2853 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2854 | TC_CRITICAL_SECTION_LEAVE(); |
| 2855 | } |
| 2856 | |
| 2857 | static inline void hri_tccount32_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) |
| 2858 | { |
| 2859 | TC_CRITICAL_SECTION_ENTER(); |
| 2860 | ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~mask; |
| 2861 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2862 | TC_CRITICAL_SECTION_LEAVE(); |
| 2863 | } |
| 2864 | |
| 2865 | static inline void hri_tccount32_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) |
| 2866 | { |
| 2867 | TC_CRITICAL_SECTION_ENTER(); |
| 2868 | ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= mask; |
| 2869 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2870 | TC_CRITICAL_SECTION_LEAVE(); |
| 2871 | } |
| 2872 | |
| 2873 | static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_reg(const void *const hw, uint8_t index) |
| 2874 | { |
| 2875 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2876 | return ((Tc *)hw)->COUNT32.CCBUF[index].reg; |
| 2877 | } |
| 2878 | |
| 2879 | static inline bool hri_tc_get_STATUS_STOP_bit(const void *const hw) |
| 2880 | { |
| 2881 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2882 | return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_STOP) >> TC_STATUS_STOP_Pos; |
| 2883 | } |
| 2884 | |
| 2885 | static inline void hri_tc_clear_STATUS_STOP_bit(const void *const hw) |
| 2886 | { |
| 2887 | TC_CRITICAL_SECTION_ENTER(); |
| 2888 | ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_STOP; |
| 2889 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2890 | TC_CRITICAL_SECTION_LEAVE(); |
| 2891 | } |
| 2892 | |
| 2893 | static inline bool hri_tc_get_STATUS_SLAVE_bit(const void *const hw) |
| 2894 | { |
| 2895 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2896 | return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_SLAVE) >> TC_STATUS_SLAVE_Pos; |
| 2897 | } |
| 2898 | |
| 2899 | static inline void hri_tc_clear_STATUS_SLAVE_bit(const void *const hw) |
| 2900 | { |
| 2901 | TC_CRITICAL_SECTION_ENTER(); |
| 2902 | ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_SLAVE; |
| 2903 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2904 | TC_CRITICAL_SECTION_LEAVE(); |
| 2905 | } |
| 2906 | |
| 2907 | static inline bool hri_tc_get_STATUS_PERBUFV_bit(const void *const hw) |
| 2908 | { |
| 2909 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2910 | return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_PERBUFV) >> TC_STATUS_PERBUFV_Pos; |
| 2911 | } |
| 2912 | |
| 2913 | static inline void hri_tc_clear_STATUS_PERBUFV_bit(const void *const hw) |
| 2914 | { |
| 2915 | TC_CRITICAL_SECTION_ENTER(); |
| 2916 | ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_PERBUFV; |
| 2917 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2918 | TC_CRITICAL_SECTION_LEAVE(); |
| 2919 | } |
| 2920 | |
| 2921 | static inline bool hri_tc_get_STATUS_CCBUFV0_bit(const void *const hw) |
| 2922 | { |
| 2923 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2924 | return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV0) >> TC_STATUS_CCBUFV0_Pos; |
| 2925 | } |
| 2926 | |
| 2927 | static inline void hri_tc_clear_STATUS_CCBUFV0_bit(const void *const hw) |
| 2928 | { |
| 2929 | TC_CRITICAL_SECTION_ENTER(); |
| 2930 | ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV0; |
| 2931 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2932 | TC_CRITICAL_SECTION_LEAVE(); |
| 2933 | } |
| 2934 | |
| 2935 | static inline bool hri_tc_get_STATUS_CCBUFV1_bit(const void *const hw) |
| 2936 | { |
| 2937 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2938 | return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV1) >> TC_STATUS_CCBUFV1_Pos; |
| 2939 | } |
| 2940 | |
| 2941 | static inline void hri_tc_clear_STATUS_CCBUFV1_bit(const void *const hw) |
| 2942 | { |
| 2943 | TC_CRITICAL_SECTION_ENTER(); |
| 2944 | ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV1; |
| 2945 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2946 | TC_CRITICAL_SECTION_LEAVE(); |
| 2947 | } |
| 2948 | |
| 2949 | static inline hri_tc_status_reg_t hri_tc_get_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) |
| 2950 | { |
| 2951 | uint8_t tmp; |
| 2952 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2953 | tmp = ((Tc *)hw)->COUNT16.STATUS.reg; |
| 2954 | tmp &= mask; |
| 2955 | return tmp; |
| 2956 | } |
| 2957 | |
| 2958 | static inline void hri_tc_clear_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) |
| 2959 | { |
| 2960 | TC_CRITICAL_SECTION_ENTER(); |
| 2961 | ((Tc *)hw)->COUNT16.STATUS.reg = mask; |
| 2962 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2963 | TC_CRITICAL_SECTION_LEAVE(); |
| 2964 | } |
| 2965 | |
| 2966 | static inline hri_tc_status_reg_t hri_tc_read_STATUS_reg(const void *const hw) |
| 2967 | { |
| 2968 | hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); |
| 2969 | return ((Tc *)hw)->COUNT16.STATUS.reg; |
| 2970 | } |
| 2971 | |
| 2972 | /* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ |
| 2973 | #define hri_tc_set_PER_PER_bf(a, b) hri_tccount8_set_PER_PER_bf(a, b) |
| 2974 | #define hri_tc_get_PER_PER_bf(a, b) hri_tccount8_get_PER_PER_bf(a, b) |
| 2975 | #define hri_tc_write_PER_PER_bf(a, b) hri_tccount8_write_PER_PER_bf(a, b) |
| 2976 | #define hri_tc_clear_PER_PER_bf(a, b) hri_tccount8_clear_PER_PER_bf(a, b) |
| 2977 | #define hri_tc_toggle_PER_PER_bf(a, b) hri_tccount8_toggle_PER_PER_bf(a, b) |
| 2978 | #define hri_tc_read_PER_PER_bf(a) hri_tccount8_read_PER_PER_bf(a) |
| 2979 | #define hri_tc_set_PER_reg(a, b) hri_tccount8_set_PER_reg(a, b) |
| 2980 | #define hri_tc_get_PER_reg(a, b) hri_tccount8_get_PER_reg(a, b) |
| 2981 | #define hri_tc_write_PER_reg(a, b) hri_tccount8_write_PER_reg(a, b) |
| 2982 | #define hri_tc_clear_PER_reg(a, b) hri_tccount8_clear_PER_reg(a, b) |
| 2983 | #define hri_tc_toggle_PER_reg(a, b) hri_tccount8_toggle_PER_reg(a, b) |
| 2984 | #define hri_tc_read_PER_reg(a) hri_tccount8_read_PER_reg(a) |
| 2985 | #define hri_tc_set_PERBUF_PERBUF_bf(a, b) hri_tccount8_set_PERBUF_PERBUF_bf(a, b) |
| 2986 | #define hri_tc_get_PERBUF_PERBUF_bf(a, b) hri_tccount8_get_PERBUF_PERBUF_bf(a, b) |
| 2987 | #define hri_tc_write_PERBUF_PERBUF_bf(a, b) hri_tccount8_write_PERBUF_PERBUF_bf(a, b) |
| 2988 | #define hri_tc_clear_PERBUF_PERBUF_bf(a, b) hri_tccount8_clear_PERBUF_PERBUF_bf(a, b) |
| 2989 | #define hri_tc_toggle_PERBUF_PERBUF_bf(a, b) hri_tccount8_toggle_PERBUF_PERBUF_bf(a, b) |
| 2990 | #define hri_tc_read_PERBUF_PERBUF_bf(a) hri_tccount8_read_PERBUF_PERBUF_bf(a) |
| 2991 | #define hri_tc_set_PERBUF_reg(a, b) hri_tccount8_set_PERBUF_reg(a, b) |
| 2992 | #define hri_tc_get_PERBUF_reg(a, b) hri_tccount8_get_PERBUF_reg(a, b) |
| 2993 | #define hri_tc_write_PERBUF_reg(a, b) hri_tccount8_write_PERBUF_reg(a, b) |
| 2994 | #define hri_tc_clear_PERBUF_reg(a, b) hri_tccount8_clear_PERBUF_reg(a, b) |
| 2995 | #define hri_tc_toggle_PERBUF_reg(a, b) hri_tccount8_toggle_PERBUF_reg(a, b) |
| 2996 | #define hri_tc_read_PERBUF_reg(a) hri_tccount8_read_PERBUF_reg(a) |
| 2997 | |
| 2998 | #ifdef __cplusplus |
| 2999 | } |
| 3000 | #endif |
| 3001 | |
| 3002 | #endif /* _HRI_TC_E54_H_INCLUDED */ |
| 3003 | #endif /* _SAME54_TC_COMPONENT_ */ |