Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM MPU |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_MPU_COMPONENT_ |
| 35 | #ifndef _HRI_MPU_E54_H_INCLUDED_ |
| 36 | #define _HRI_MPU_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_MPU_CRITICAL_SECTIONS) |
| 46 | #define MPU_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define MPU_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define MPU_CRITICAL_SECTION_ENTER() |
| 50 | #define MPU_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint32_t hri_mpu_ctrl_reg_t; |
| 54 | typedef uint32_t hri_mpu_rasr_a1_reg_t; |
| 55 | typedef uint32_t hri_mpu_rasr_a2_reg_t; |
| 56 | typedef uint32_t hri_mpu_rasr_a3_reg_t; |
| 57 | typedef uint32_t hri_mpu_rasr_reg_t; |
| 58 | typedef uint32_t hri_mpu_rbar_a1_reg_t; |
| 59 | typedef uint32_t hri_mpu_rbar_a2_reg_t; |
| 60 | typedef uint32_t hri_mpu_rbar_a3_reg_t; |
| 61 | typedef uint32_t hri_mpu_rbar_reg_t; |
| 62 | typedef uint32_t hri_mpu_rnr_reg_t; |
| 63 | typedef uint32_t hri_mpu_type_reg_t; |
| 64 | |
| 65 | static inline bool hri_mpu_get_TYPE_SEPARATE_bit(const void *const hw) |
| 66 | { |
| 67 | return (((Mpu *)hw)->TYPE.reg & MPU_TYPE_SEPARATE) >> 0; |
| 68 | } |
| 69 | |
| 70 | static inline hri_mpu_type_reg_t hri_mpu_get_TYPE_DREGION_bf(const void *const hw, hri_mpu_type_reg_t mask) |
| 71 | { |
| 72 | return (((Mpu *)hw)->TYPE.reg & MPU_TYPE_DREGION(mask)) >> 8; |
| 73 | } |
| 74 | |
| 75 | static inline hri_mpu_type_reg_t hri_mpu_read_TYPE_DREGION_bf(const void *const hw) |
| 76 | { |
| 77 | return (((Mpu *)hw)->TYPE.reg & MPU_TYPE_DREGION_Msk) >> 8; |
| 78 | } |
| 79 | |
| 80 | static inline hri_mpu_type_reg_t hri_mpu_get_TYPE_IREGION_bf(const void *const hw, hri_mpu_type_reg_t mask) |
| 81 | { |
| 82 | return (((Mpu *)hw)->TYPE.reg & MPU_TYPE_IREGION(mask)) >> 16; |
| 83 | } |
| 84 | |
| 85 | static inline hri_mpu_type_reg_t hri_mpu_read_TYPE_IREGION_bf(const void *const hw) |
| 86 | { |
| 87 | return (((Mpu *)hw)->TYPE.reg & MPU_TYPE_IREGION_Msk) >> 16; |
| 88 | } |
| 89 | |
| 90 | static inline hri_mpu_type_reg_t hri_mpu_get_TYPE_reg(const void *const hw, hri_mpu_type_reg_t mask) |
| 91 | { |
| 92 | uint32_t tmp; |
| 93 | tmp = ((Mpu *)hw)->TYPE.reg; |
| 94 | tmp &= mask; |
| 95 | return tmp; |
| 96 | } |
| 97 | |
| 98 | static inline hri_mpu_type_reg_t hri_mpu_read_TYPE_reg(const void *const hw) |
| 99 | { |
| 100 | return ((Mpu *)hw)->TYPE.reg; |
| 101 | } |
| 102 | |
| 103 | static inline void hri_mpu_set_CTRL_reg(const void *const hw, hri_mpu_ctrl_reg_t mask) |
| 104 | { |
| 105 | MPU_CRITICAL_SECTION_ENTER(); |
| 106 | ((Mpu *)hw)->CTRL.reg |= mask; |
| 107 | MPU_CRITICAL_SECTION_LEAVE(); |
| 108 | } |
| 109 | |
| 110 | static inline hri_mpu_ctrl_reg_t hri_mpu_get_CTRL_reg(const void *const hw, hri_mpu_ctrl_reg_t mask) |
| 111 | { |
| 112 | uint32_t tmp; |
| 113 | tmp = ((Mpu *)hw)->CTRL.reg; |
| 114 | tmp &= mask; |
| 115 | return tmp; |
| 116 | } |
| 117 | |
| 118 | static inline void hri_mpu_write_CTRL_reg(const void *const hw, hri_mpu_ctrl_reg_t data) |
| 119 | { |
| 120 | MPU_CRITICAL_SECTION_ENTER(); |
| 121 | ((Mpu *)hw)->CTRL.reg = data; |
| 122 | MPU_CRITICAL_SECTION_LEAVE(); |
| 123 | } |
| 124 | |
| 125 | static inline void hri_mpu_clear_CTRL_reg(const void *const hw, hri_mpu_ctrl_reg_t mask) |
| 126 | { |
| 127 | MPU_CRITICAL_SECTION_ENTER(); |
| 128 | ((Mpu *)hw)->CTRL.reg &= ~mask; |
| 129 | MPU_CRITICAL_SECTION_LEAVE(); |
| 130 | } |
| 131 | |
| 132 | static inline void hri_mpu_toggle_CTRL_reg(const void *const hw, hri_mpu_ctrl_reg_t mask) |
| 133 | { |
| 134 | MPU_CRITICAL_SECTION_ENTER(); |
| 135 | ((Mpu *)hw)->CTRL.reg ^= mask; |
| 136 | MPU_CRITICAL_SECTION_LEAVE(); |
| 137 | } |
| 138 | |
| 139 | static inline hri_mpu_ctrl_reg_t hri_mpu_read_CTRL_reg(const void *const hw) |
| 140 | { |
| 141 | return ((Mpu *)hw)->CTRL.reg; |
| 142 | } |
| 143 | |
| 144 | static inline void hri_mpu_set_RNR_reg(const void *const hw, hri_mpu_rnr_reg_t mask) |
| 145 | { |
| 146 | MPU_CRITICAL_SECTION_ENTER(); |
| 147 | ((Mpu *)hw)->RNR.reg |= mask; |
| 148 | MPU_CRITICAL_SECTION_LEAVE(); |
| 149 | } |
| 150 | |
| 151 | static inline hri_mpu_rnr_reg_t hri_mpu_get_RNR_reg(const void *const hw, hri_mpu_rnr_reg_t mask) |
| 152 | { |
| 153 | uint32_t tmp; |
| 154 | tmp = ((Mpu *)hw)->RNR.reg; |
| 155 | tmp &= mask; |
| 156 | return tmp; |
| 157 | } |
| 158 | |
| 159 | static inline void hri_mpu_write_RNR_reg(const void *const hw, hri_mpu_rnr_reg_t data) |
| 160 | { |
| 161 | MPU_CRITICAL_SECTION_ENTER(); |
| 162 | ((Mpu *)hw)->RNR.reg = data; |
| 163 | MPU_CRITICAL_SECTION_LEAVE(); |
| 164 | } |
| 165 | |
| 166 | static inline void hri_mpu_clear_RNR_reg(const void *const hw, hri_mpu_rnr_reg_t mask) |
| 167 | { |
| 168 | MPU_CRITICAL_SECTION_ENTER(); |
| 169 | ((Mpu *)hw)->RNR.reg &= ~mask; |
| 170 | MPU_CRITICAL_SECTION_LEAVE(); |
| 171 | } |
| 172 | |
| 173 | static inline void hri_mpu_toggle_RNR_reg(const void *const hw, hri_mpu_rnr_reg_t mask) |
| 174 | { |
| 175 | MPU_CRITICAL_SECTION_ENTER(); |
| 176 | ((Mpu *)hw)->RNR.reg ^= mask; |
| 177 | MPU_CRITICAL_SECTION_LEAVE(); |
| 178 | } |
| 179 | |
| 180 | static inline hri_mpu_rnr_reg_t hri_mpu_read_RNR_reg(const void *const hw) |
| 181 | { |
| 182 | return ((Mpu *)hw)->RNR.reg; |
| 183 | } |
| 184 | |
| 185 | static inline void hri_mpu_set_RBAR_reg(const void *const hw, hri_mpu_rbar_reg_t mask) |
| 186 | { |
| 187 | MPU_CRITICAL_SECTION_ENTER(); |
| 188 | ((Mpu *)hw)->RBAR.reg |= mask; |
| 189 | MPU_CRITICAL_SECTION_LEAVE(); |
| 190 | } |
| 191 | |
| 192 | static inline hri_mpu_rbar_reg_t hri_mpu_get_RBAR_reg(const void *const hw, hri_mpu_rbar_reg_t mask) |
| 193 | { |
| 194 | uint32_t tmp; |
| 195 | tmp = ((Mpu *)hw)->RBAR.reg; |
| 196 | tmp &= mask; |
| 197 | return tmp; |
| 198 | } |
| 199 | |
| 200 | static inline void hri_mpu_write_RBAR_reg(const void *const hw, hri_mpu_rbar_reg_t data) |
| 201 | { |
| 202 | MPU_CRITICAL_SECTION_ENTER(); |
| 203 | ((Mpu *)hw)->RBAR.reg = data; |
| 204 | MPU_CRITICAL_SECTION_LEAVE(); |
| 205 | } |
| 206 | |
| 207 | static inline void hri_mpu_clear_RBAR_reg(const void *const hw, hri_mpu_rbar_reg_t mask) |
| 208 | { |
| 209 | MPU_CRITICAL_SECTION_ENTER(); |
| 210 | ((Mpu *)hw)->RBAR.reg &= ~mask; |
| 211 | MPU_CRITICAL_SECTION_LEAVE(); |
| 212 | } |
| 213 | |
| 214 | static inline void hri_mpu_toggle_RBAR_reg(const void *const hw, hri_mpu_rbar_reg_t mask) |
| 215 | { |
| 216 | MPU_CRITICAL_SECTION_ENTER(); |
| 217 | ((Mpu *)hw)->RBAR.reg ^= mask; |
| 218 | MPU_CRITICAL_SECTION_LEAVE(); |
| 219 | } |
| 220 | |
| 221 | static inline hri_mpu_rbar_reg_t hri_mpu_read_RBAR_reg(const void *const hw) |
| 222 | { |
| 223 | return ((Mpu *)hw)->RBAR.reg; |
| 224 | } |
| 225 | |
| 226 | static inline void hri_mpu_set_RASR_reg(const void *const hw, hri_mpu_rasr_reg_t mask) |
| 227 | { |
| 228 | MPU_CRITICAL_SECTION_ENTER(); |
| 229 | ((Mpu *)hw)->RASR.reg |= mask; |
| 230 | MPU_CRITICAL_SECTION_LEAVE(); |
| 231 | } |
| 232 | |
| 233 | static inline hri_mpu_rasr_reg_t hri_mpu_get_RASR_reg(const void *const hw, hri_mpu_rasr_reg_t mask) |
| 234 | { |
| 235 | uint32_t tmp; |
| 236 | tmp = ((Mpu *)hw)->RASR.reg; |
| 237 | tmp &= mask; |
| 238 | return tmp; |
| 239 | } |
| 240 | |
| 241 | static inline void hri_mpu_write_RASR_reg(const void *const hw, hri_mpu_rasr_reg_t data) |
| 242 | { |
| 243 | MPU_CRITICAL_SECTION_ENTER(); |
| 244 | ((Mpu *)hw)->RASR.reg = data; |
| 245 | MPU_CRITICAL_SECTION_LEAVE(); |
| 246 | } |
| 247 | |
| 248 | static inline void hri_mpu_clear_RASR_reg(const void *const hw, hri_mpu_rasr_reg_t mask) |
| 249 | { |
| 250 | MPU_CRITICAL_SECTION_ENTER(); |
| 251 | ((Mpu *)hw)->RASR.reg &= ~mask; |
| 252 | MPU_CRITICAL_SECTION_LEAVE(); |
| 253 | } |
| 254 | |
| 255 | static inline void hri_mpu_toggle_RASR_reg(const void *const hw, hri_mpu_rasr_reg_t mask) |
| 256 | { |
| 257 | MPU_CRITICAL_SECTION_ENTER(); |
| 258 | ((Mpu *)hw)->RASR.reg ^= mask; |
| 259 | MPU_CRITICAL_SECTION_LEAVE(); |
| 260 | } |
| 261 | |
| 262 | static inline hri_mpu_rasr_reg_t hri_mpu_read_RASR_reg(const void *const hw) |
| 263 | { |
| 264 | return ((Mpu *)hw)->RASR.reg; |
| 265 | } |
| 266 | |
| 267 | static inline void hri_mpu_set_RBAR_A1_reg(const void *const hw, hri_mpu_rbar_a1_reg_t mask) |
| 268 | { |
| 269 | MPU_CRITICAL_SECTION_ENTER(); |
| 270 | ((Mpu *)hw)->RBAR_A1.reg |= mask; |
| 271 | MPU_CRITICAL_SECTION_LEAVE(); |
| 272 | } |
| 273 | |
| 274 | static inline hri_mpu_rbar_a1_reg_t hri_mpu_get_RBAR_A1_reg(const void *const hw, hri_mpu_rbar_a1_reg_t mask) |
| 275 | { |
| 276 | uint32_t tmp; |
| 277 | tmp = ((Mpu *)hw)->RBAR_A1.reg; |
| 278 | tmp &= mask; |
| 279 | return tmp; |
| 280 | } |
| 281 | |
| 282 | static inline void hri_mpu_write_RBAR_A1_reg(const void *const hw, hri_mpu_rbar_a1_reg_t data) |
| 283 | { |
| 284 | MPU_CRITICAL_SECTION_ENTER(); |
| 285 | ((Mpu *)hw)->RBAR_A1.reg = data; |
| 286 | MPU_CRITICAL_SECTION_LEAVE(); |
| 287 | } |
| 288 | |
| 289 | static inline void hri_mpu_clear_RBAR_A1_reg(const void *const hw, hri_mpu_rbar_a1_reg_t mask) |
| 290 | { |
| 291 | MPU_CRITICAL_SECTION_ENTER(); |
| 292 | ((Mpu *)hw)->RBAR_A1.reg &= ~mask; |
| 293 | MPU_CRITICAL_SECTION_LEAVE(); |
| 294 | } |
| 295 | |
| 296 | static inline void hri_mpu_toggle_RBAR_A1_reg(const void *const hw, hri_mpu_rbar_a1_reg_t mask) |
| 297 | { |
| 298 | MPU_CRITICAL_SECTION_ENTER(); |
| 299 | ((Mpu *)hw)->RBAR_A1.reg ^= mask; |
| 300 | MPU_CRITICAL_SECTION_LEAVE(); |
| 301 | } |
| 302 | |
| 303 | static inline hri_mpu_rbar_a1_reg_t hri_mpu_read_RBAR_A1_reg(const void *const hw) |
| 304 | { |
| 305 | return ((Mpu *)hw)->RBAR_A1.reg; |
| 306 | } |
| 307 | |
| 308 | static inline void hri_mpu_set_RASR_A1_reg(const void *const hw, hri_mpu_rasr_a1_reg_t mask) |
| 309 | { |
| 310 | MPU_CRITICAL_SECTION_ENTER(); |
| 311 | ((Mpu *)hw)->RASR_A1.reg |= mask; |
| 312 | MPU_CRITICAL_SECTION_LEAVE(); |
| 313 | } |
| 314 | |
| 315 | static inline hri_mpu_rasr_a1_reg_t hri_mpu_get_RASR_A1_reg(const void *const hw, hri_mpu_rasr_a1_reg_t mask) |
| 316 | { |
| 317 | uint32_t tmp; |
| 318 | tmp = ((Mpu *)hw)->RASR_A1.reg; |
| 319 | tmp &= mask; |
| 320 | return tmp; |
| 321 | } |
| 322 | |
| 323 | static inline void hri_mpu_write_RASR_A1_reg(const void *const hw, hri_mpu_rasr_a1_reg_t data) |
| 324 | { |
| 325 | MPU_CRITICAL_SECTION_ENTER(); |
| 326 | ((Mpu *)hw)->RASR_A1.reg = data; |
| 327 | MPU_CRITICAL_SECTION_LEAVE(); |
| 328 | } |
| 329 | |
| 330 | static inline void hri_mpu_clear_RASR_A1_reg(const void *const hw, hri_mpu_rasr_a1_reg_t mask) |
| 331 | { |
| 332 | MPU_CRITICAL_SECTION_ENTER(); |
| 333 | ((Mpu *)hw)->RASR_A1.reg &= ~mask; |
| 334 | MPU_CRITICAL_SECTION_LEAVE(); |
| 335 | } |
| 336 | |
| 337 | static inline void hri_mpu_toggle_RASR_A1_reg(const void *const hw, hri_mpu_rasr_a1_reg_t mask) |
| 338 | { |
| 339 | MPU_CRITICAL_SECTION_ENTER(); |
| 340 | ((Mpu *)hw)->RASR_A1.reg ^= mask; |
| 341 | MPU_CRITICAL_SECTION_LEAVE(); |
| 342 | } |
| 343 | |
| 344 | static inline hri_mpu_rasr_a1_reg_t hri_mpu_read_RASR_A1_reg(const void *const hw) |
| 345 | { |
| 346 | return ((Mpu *)hw)->RASR_A1.reg; |
| 347 | } |
| 348 | |
| 349 | static inline void hri_mpu_set_RBAR_A2_reg(const void *const hw, hri_mpu_rbar_a2_reg_t mask) |
| 350 | { |
| 351 | MPU_CRITICAL_SECTION_ENTER(); |
| 352 | ((Mpu *)hw)->RBAR_A2.reg |= mask; |
| 353 | MPU_CRITICAL_SECTION_LEAVE(); |
| 354 | } |
| 355 | |
| 356 | static inline hri_mpu_rbar_a2_reg_t hri_mpu_get_RBAR_A2_reg(const void *const hw, hri_mpu_rbar_a2_reg_t mask) |
| 357 | { |
| 358 | uint32_t tmp; |
| 359 | tmp = ((Mpu *)hw)->RBAR_A2.reg; |
| 360 | tmp &= mask; |
| 361 | return tmp; |
| 362 | } |
| 363 | |
| 364 | static inline void hri_mpu_write_RBAR_A2_reg(const void *const hw, hri_mpu_rbar_a2_reg_t data) |
| 365 | { |
| 366 | MPU_CRITICAL_SECTION_ENTER(); |
| 367 | ((Mpu *)hw)->RBAR_A2.reg = data; |
| 368 | MPU_CRITICAL_SECTION_LEAVE(); |
| 369 | } |
| 370 | |
| 371 | static inline void hri_mpu_clear_RBAR_A2_reg(const void *const hw, hri_mpu_rbar_a2_reg_t mask) |
| 372 | { |
| 373 | MPU_CRITICAL_SECTION_ENTER(); |
| 374 | ((Mpu *)hw)->RBAR_A2.reg &= ~mask; |
| 375 | MPU_CRITICAL_SECTION_LEAVE(); |
| 376 | } |
| 377 | |
| 378 | static inline void hri_mpu_toggle_RBAR_A2_reg(const void *const hw, hri_mpu_rbar_a2_reg_t mask) |
| 379 | { |
| 380 | MPU_CRITICAL_SECTION_ENTER(); |
| 381 | ((Mpu *)hw)->RBAR_A2.reg ^= mask; |
| 382 | MPU_CRITICAL_SECTION_LEAVE(); |
| 383 | } |
| 384 | |
| 385 | static inline hri_mpu_rbar_a2_reg_t hri_mpu_read_RBAR_A2_reg(const void *const hw) |
| 386 | { |
| 387 | return ((Mpu *)hw)->RBAR_A2.reg; |
| 388 | } |
| 389 | |
| 390 | static inline void hri_mpu_set_RASR_A2_reg(const void *const hw, hri_mpu_rasr_a2_reg_t mask) |
| 391 | { |
| 392 | MPU_CRITICAL_SECTION_ENTER(); |
| 393 | ((Mpu *)hw)->RASR_A2.reg |= mask; |
| 394 | MPU_CRITICAL_SECTION_LEAVE(); |
| 395 | } |
| 396 | |
| 397 | static inline hri_mpu_rasr_a2_reg_t hri_mpu_get_RASR_A2_reg(const void *const hw, hri_mpu_rasr_a2_reg_t mask) |
| 398 | { |
| 399 | uint32_t tmp; |
| 400 | tmp = ((Mpu *)hw)->RASR_A2.reg; |
| 401 | tmp &= mask; |
| 402 | return tmp; |
| 403 | } |
| 404 | |
| 405 | static inline void hri_mpu_write_RASR_A2_reg(const void *const hw, hri_mpu_rasr_a2_reg_t data) |
| 406 | { |
| 407 | MPU_CRITICAL_SECTION_ENTER(); |
| 408 | ((Mpu *)hw)->RASR_A2.reg = data; |
| 409 | MPU_CRITICAL_SECTION_LEAVE(); |
| 410 | } |
| 411 | |
| 412 | static inline void hri_mpu_clear_RASR_A2_reg(const void *const hw, hri_mpu_rasr_a2_reg_t mask) |
| 413 | { |
| 414 | MPU_CRITICAL_SECTION_ENTER(); |
| 415 | ((Mpu *)hw)->RASR_A2.reg &= ~mask; |
| 416 | MPU_CRITICAL_SECTION_LEAVE(); |
| 417 | } |
| 418 | |
| 419 | static inline void hri_mpu_toggle_RASR_A2_reg(const void *const hw, hri_mpu_rasr_a2_reg_t mask) |
| 420 | { |
| 421 | MPU_CRITICAL_SECTION_ENTER(); |
| 422 | ((Mpu *)hw)->RASR_A2.reg ^= mask; |
| 423 | MPU_CRITICAL_SECTION_LEAVE(); |
| 424 | } |
| 425 | |
| 426 | static inline hri_mpu_rasr_a2_reg_t hri_mpu_read_RASR_A2_reg(const void *const hw) |
| 427 | { |
| 428 | return ((Mpu *)hw)->RASR_A2.reg; |
| 429 | } |
| 430 | |
| 431 | static inline void hri_mpu_set_RBAR_A3_reg(const void *const hw, hri_mpu_rbar_a3_reg_t mask) |
| 432 | { |
| 433 | MPU_CRITICAL_SECTION_ENTER(); |
| 434 | ((Mpu *)hw)->RBAR_A3.reg |= mask; |
| 435 | MPU_CRITICAL_SECTION_LEAVE(); |
| 436 | } |
| 437 | |
| 438 | static inline hri_mpu_rbar_a3_reg_t hri_mpu_get_RBAR_A3_reg(const void *const hw, hri_mpu_rbar_a3_reg_t mask) |
| 439 | { |
| 440 | uint32_t tmp; |
| 441 | tmp = ((Mpu *)hw)->RBAR_A3.reg; |
| 442 | tmp &= mask; |
| 443 | return tmp; |
| 444 | } |
| 445 | |
| 446 | static inline void hri_mpu_write_RBAR_A3_reg(const void *const hw, hri_mpu_rbar_a3_reg_t data) |
| 447 | { |
| 448 | MPU_CRITICAL_SECTION_ENTER(); |
| 449 | ((Mpu *)hw)->RBAR_A3.reg = data; |
| 450 | MPU_CRITICAL_SECTION_LEAVE(); |
| 451 | } |
| 452 | |
| 453 | static inline void hri_mpu_clear_RBAR_A3_reg(const void *const hw, hri_mpu_rbar_a3_reg_t mask) |
| 454 | { |
| 455 | MPU_CRITICAL_SECTION_ENTER(); |
| 456 | ((Mpu *)hw)->RBAR_A3.reg &= ~mask; |
| 457 | MPU_CRITICAL_SECTION_LEAVE(); |
| 458 | } |
| 459 | |
| 460 | static inline void hri_mpu_toggle_RBAR_A3_reg(const void *const hw, hri_mpu_rbar_a3_reg_t mask) |
| 461 | { |
| 462 | MPU_CRITICAL_SECTION_ENTER(); |
| 463 | ((Mpu *)hw)->RBAR_A3.reg ^= mask; |
| 464 | MPU_CRITICAL_SECTION_LEAVE(); |
| 465 | } |
| 466 | |
| 467 | static inline hri_mpu_rbar_a3_reg_t hri_mpu_read_RBAR_A3_reg(const void *const hw) |
| 468 | { |
| 469 | return ((Mpu *)hw)->RBAR_A3.reg; |
| 470 | } |
| 471 | |
| 472 | static inline void hri_mpu_set_RASR_A3_reg(const void *const hw, hri_mpu_rasr_a3_reg_t mask) |
| 473 | { |
| 474 | MPU_CRITICAL_SECTION_ENTER(); |
| 475 | ((Mpu *)hw)->RASR_A3.reg |= mask; |
| 476 | MPU_CRITICAL_SECTION_LEAVE(); |
| 477 | } |
| 478 | |
| 479 | static inline hri_mpu_rasr_a3_reg_t hri_mpu_get_RASR_A3_reg(const void *const hw, hri_mpu_rasr_a3_reg_t mask) |
| 480 | { |
| 481 | uint32_t tmp; |
| 482 | tmp = ((Mpu *)hw)->RASR_A3.reg; |
| 483 | tmp &= mask; |
| 484 | return tmp; |
| 485 | } |
| 486 | |
| 487 | static inline void hri_mpu_write_RASR_A3_reg(const void *const hw, hri_mpu_rasr_a3_reg_t data) |
| 488 | { |
| 489 | MPU_CRITICAL_SECTION_ENTER(); |
| 490 | ((Mpu *)hw)->RASR_A3.reg = data; |
| 491 | MPU_CRITICAL_SECTION_LEAVE(); |
| 492 | } |
| 493 | |
| 494 | static inline void hri_mpu_clear_RASR_A3_reg(const void *const hw, hri_mpu_rasr_a3_reg_t mask) |
| 495 | { |
| 496 | MPU_CRITICAL_SECTION_ENTER(); |
| 497 | ((Mpu *)hw)->RASR_A3.reg &= ~mask; |
| 498 | MPU_CRITICAL_SECTION_LEAVE(); |
| 499 | } |
| 500 | |
| 501 | static inline void hri_mpu_toggle_RASR_A3_reg(const void *const hw, hri_mpu_rasr_a3_reg_t mask) |
| 502 | { |
| 503 | MPU_CRITICAL_SECTION_ENTER(); |
| 504 | ((Mpu *)hw)->RASR_A3.reg ^= mask; |
| 505 | MPU_CRITICAL_SECTION_LEAVE(); |
| 506 | } |
| 507 | |
| 508 | static inline hri_mpu_rasr_a3_reg_t hri_mpu_read_RASR_A3_reg(const void *const hw) |
| 509 | { |
| 510 | return ((Mpu *)hw)->RASR_A3.reg; |
| 511 | } |
| 512 | |
| 513 | #ifdef __cplusplus |
| 514 | } |
| 515 | #endif |
| 516 | |
| 517 | #endif /* _HRI_MPU_E54_H_INCLUDED */ |
| 518 | #endif /* _SAME54_MPU_COMPONENT_ */ |