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gerrit.osmocom.org / osmo-ccid-firmware / c94e0fc0e6040ba61cec0cdb70209a00080fe2d5 / . / sysmoOCTSIM / CMSIS / Include / core_cm4.h
blob: 2da78d3983e85180abbe53a478079f26b0bf81d7 [file] [log] [blame]
Kévin Redon69b92d92019-01-24 16:39:20 +0100[diff] [blame]1/**************************************************************************//**
2 * @file core_cm4.h
3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
4 * @version V5.0.1
5 * @date 30. January 2017
6 ******************************************************************************/
7/*
8 * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25#if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
28 #pragma clang system_header /* treat file as system include file */
29#endif
30
31#ifndef __CORE_CM4_H_GENERIC
32#define __CORE_CM4_H_GENERIC
33
34#include <stdint.h>
35
36#ifdef __cplusplus
37 extern "C" {
38#endif
39
40/**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55/*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58/**
59 \ingroup Cortex_M4
60 @{
61 */
62
63/* CMSIS CM4 definitions */
64#define __CM4_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
65#define __CM4_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
66#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
67 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
68
69#define __CORTEX_M (4U) /*!< Cortex-M Core */
70
71/** __FPU_USED indicates whether an FPU is used or not.
72 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
73*/
74#if defined ( __CC_ARM )
75 #if defined __TARGET_FPU_VFP
76 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
77 #define __FPU_USED 1U
78 #else
79 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
80 #define __FPU_USED 0U
81 #endif
82 #else
83 #define __FPU_USED 0U
84 #endif
85
86#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
87 #if defined __ARM_PCS_VFP
88 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
89 #define __FPU_USED 1U
90 #else
91 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
92 #define __FPU_USED 0U
93 #endif
94 #else
95 #define __FPU_USED 0U
96 #endif
97
98#elif defined ( __GNUC__ )
99 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
100 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
101 #define __FPU_USED 1U
102 #else
103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
104 #define __FPU_USED 0U
105 #endif
106 #else
107 #define __FPU_USED 0U
108 #endif
109
110#elif defined ( __ICCARM__ )
111 #if defined __ARMVFP__
112 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
113 #define __FPU_USED 1U
114 #else
115 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
116 #define __FPU_USED 0U
117 #endif
118 #else
119 #define __FPU_USED 0U
120 #endif
121
122#elif defined ( __TI_ARM__ )
123 #if defined __TI_VFP_SUPPORT__
124 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
125 #define __FPU_USED 1U
126 #else
127 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
128 #define __FPU_USED 0U
129 #endif
130 #else
131 #define __FPU_USED 0U
132 #endif
133
134#elif defined ( __TASKING__ )
135 #if defined __FPU_VFP__
136 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
137 #define __FPU_USED 1U
138 #else
139 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
140 #define __FPU_USED 0U
141 #endif
142 #else
143 #define __FPU_USED 0U
144 #endif
145
146#elif defined ( __CSMC__ )
147 #if ( __CSMC__ & 0x400U)
148 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
149 #define __FPU_USED 1U
150 #else
151 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
152 #define __FPU_USED 0U
153 #endif
154 #else
155 #define __FPU_USED 0U
156 #endif
157
158#endif
159
160#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
161
162
163#ifdef __cplusplus
164}
165#endif
166
167#endif /* __CORE_CM4_H_GENERIC */
168
169#ifndef __CMSIS_GENERIC
170
171#ifndef __CORE_CM4_H_DEPENDANT
172#define __CORE_CM4_H_DEPENDANT
173
174#ifdef __cplusplus
175 extern "C" {
176#endif
177
178/* check device defines and use defaults */
179#if defined __CHECK_DEVICE_DEFINES
180 #ifndef __CM4_REV
181 #define __CM4_REV 0x0000U
182 #warning "__CM4_REV not defined in device header file; using default!"
183 #endif
184
185 #ifndef __FPU_PRESENT
186 #define __FPU_PRESENT 0U
187 #warning "__FPU_PRESENT not defined in device header file; using default!"
188 #endif
189
190 #ifndef __MPU_PRESENT
191 #define __MPU_PRESENT 0U
192 #warning "__MPU_PRESENT not defined in device header file; using default!"
193 #endif
194
195 #ifndef __NVIC_PRIO_BITS
196 #define __NVIC_PRIO_BITS 3U
197 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
198 #endif
199
200 #ifndef __Vendor_SysTickConfig
201 #define __Vendor_SysTickConfig 0U
202 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
203 #endif
204#endif
205
206/* IO definitions (access restrictions to peripheral registers) */
207/**
208 \defgroup CMSIS_glob_defs CMSIS Global Defines
209
210 <strong>IO Type Qualifiers</strong> are used
211 \li to specify the access to peripheral variables.
212 \li for automatic generation of peripheral register debug information.
213*/
214#ifdef __cplusplus
215 #define __I volatile /*!< Defines 'read only' permissions */
216#else
217 #define __I volatile const /*!< Defines 'read only' permissions */
218#endif
219#define __O volatile /*!< Defines 'write only' permissions */
220#define __IO volatile /*!< Defines 'read / write' permissions */
221
222/* following defines should be used for structure members */
223#define __IM volatile const /*! Defines 'read only' structure member permissions */
224#define __OM volatile /*! Defines 'write only' structure member permissions */
225#define __IOM volatile /*! Defines 'read / write' structure member permissions */
226
227/*@} end of group Cortex_M4 */
228
229
230
231/*******************************************************************************
232 * Register Abstraction
233 Core Register contain:
234 - Core Register
235 - Core NVIC Register
236 - Core SCB Register
237 - Core SysTick Register
238 - Core Debug Register
239 - Core MPU Register
240 - Core FPU Register
241 ******************************************************************************/
242/**
243 \defgroup CMSIS_core_register Defines and Type Definitions
244 \brief Type definitions and defines for Cortex-M processor based devices.
245*/
246
247/**
248 \ingroup CMSIS_core_register
249 \defgroup CMSIS_CORE Status and Control Registers
250 \brief Core Register type definitions.
251 @{
252 */
253
254/**
255 \brief Union type to access the Application Program Status Register (APSR).
256 */
257typedef union
258{
259 struct
260 {
261 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
262 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
263 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
264 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
265 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
266 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
267 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
268 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
269 } b; /*!< Structure used for bit access */
270 uint32_t w; /*!< Type used for word access */
271} APSR_Type;
272
273/* APSR Register Definitions */
274#define APSR_N_Pos 31U /*!< APSR: N Position */
275#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
276
277#define APSR_Z_Pos 30U /*!< APSR: Z Position */
278#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
279
280#define APSR_C_Pos 29U /*!< APSR: C Position */
281#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
282
283#define APSR_V_Pos 28U /*!< APSR: V Position */
284#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
285
286#define APSR_Q_Pos 27U /*!< APSR: Q Position */
287#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
288
289#define APSR_GE_Pos 16U /*!< APSR: GE Position */
290#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
291
292
293/**
294 \brief Union type to access the Interrupt Program Status Register (IPSR).
295 */
296typedef union
297{
298 struct
299 {
300 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
301 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
302 } b; /*!< Structure used for bit access */
303 uint32_t w; /*!< Type used for word access */
304} IPSR_Type;
305
306/* IPSR Register Definitions */
307#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
308#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
309
310
311/**
312 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
313 */
314typedef union
315{
316 struct
317 {
318 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
319 uint32_t _reserved0:1; /*!< bit: 9 Reserved */
320 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
321 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
322 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
323 uint32_t T:1; /*!< bit: 24 Thumb bit */
324 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
325 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
326 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
327 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
328 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
329 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
330 } b; /*!< Structure used for bit access */
331 uint32_t w; /*!< Type used for word access */
332} xPSR_Type;
333
334/* xPSR Register Definitions */
335#define xPSR_N_Pos 31U /*!< xPSR: N Position */
336#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
337
338#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
339#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
340
341#define xPSR_C_Pos 29U /*!< xPSR: C Position */
342#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
343
344#define xPSR_V_Pos 28U /*!< xPSR: V Position */
345#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
346
347#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
348#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
349
350#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
351#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
352
353#define xPSR_T_Pos 24U /*!< xPSR: T Position */
354#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
355
356#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
357#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
358
359#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
360#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
361
362#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
363#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
364
365
366/**
367 \brief Union type to access the Control Registers (CONTROL).
368 */
369typedef union
370{
371 struct
372 {
373 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
374 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
375 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
376 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
377 } b; /*!< Structure used for bit access */
378 uint32_t w; /*!< Type used for word access */
379} CONTROL_Type;
380
381/* CONTROL Register Definitions */
382#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
383#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
384
385#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
386#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
387
388#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
389#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
390
391/*@} end of group CMSIS_CORE */
392
393
394/**
395 \ingroup CMSIS_core_register
396 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
397 \brief Type definitions for the NVIC Registers
398 @{
399 */
400
401/**
402 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
403 */
404typedef struct
405{
406 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
407 uint32_t RESERVED0[24U];
408 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
409 uint32_t RSERVED1[24U];
410 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
411 uint32_t RESERVED2[24U];
412 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
413 uint32_t RESERVED3[24U];
414 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
415 uint32_t RESERVED4[56U];
416 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
417 uint32_t RESERVED5[644U];
418 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
419} NVIC_Type;
420
421/* Software Triggered Interrupt Register Definitions */
422#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
423#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
424
425/*@} end of group CMSIS_NVIC */
426
427
428/**
429 \ingroup CMSIS_core_register
430 \defgroup CMSIS_SCB System Control Block (SCB)
431 \brief Type definitions for the System Control Block Registers
432 @{
433 */
434
435/**
436 \brief Structure type to access the System Control Block (SCB).
437 */
438typedef struct
439{
440 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
441 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
442 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
443 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
444 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
445 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
446 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
447 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
448 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
449 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
450 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
451 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
452 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
453 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
454 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
455 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
456 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
457 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
458 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
459 uint32_t RESERVED0[5U];
460 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
461} SCB_Type;
462
463/* SCB CPUID Register Definitions */
464#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
465#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
466
467#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
468#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
469
470#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
471#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
472
473#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
474#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
475
476#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
477#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
478
479/* SCB Interrupt Control State Register Definitions */
480#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
481#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
482
483#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
484#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
485
486#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
487#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
488
489#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
490#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
491
492#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
493#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
494
495#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
496#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
497
498#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
499#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
500
501#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
502#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
503
504#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
505#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
506
507#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
508#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
509
510/* SCB Vector Table Offset Register Definitions */
511#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
512#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
513
514/* SCB Application Interrupt and Reset Control Register Definitions */
515#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
516#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
517
518#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
519#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
520
521#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
522#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
523
524#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
525#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
526
527#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
528#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
529
530#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
531#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
532
533#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
534#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
535
536/* SCB System Control Register Definitions */
537#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
538#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
539
540#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
541#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
542
543#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
544#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
545
546/* SCB Configuration Control Register Definitions */
547#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
548#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
549
550#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
551#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
552
553#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
554#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
555
556#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
557#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
558
559#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
560#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
561
562#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
563#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
564
565/* SCB System Handler Control and State Register Definitions */
566#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
567#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
568
569#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
570#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
571
572#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
573#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
574
575#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
576#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
577
578#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
579#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
580
581#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
582#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
583
584#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
585#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
586
587#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
588#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
589
590#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
591#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
592
593#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
594#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
595
596#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
597#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
598
599#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
600#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
601
602#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
603#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
604
605#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
606#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
607
608/* SCB Configurable Fault Status Register Definitions */
609#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
610#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
611
612#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
613#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
614
615#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
616#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
617
618/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
619#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
620#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
621
622#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
623#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
624
625#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
626#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
627
628#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
629#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
630
631#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
632#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
633
634#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
635#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
636
637/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
638#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
639#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
640
641#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
642#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
643
644#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
645#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
646
647#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
648#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
649
650#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
651#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
652
653#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
654#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
655
656#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
657#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
658
659/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
660#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
661#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
662
663#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
664#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
665
666#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
667#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
668
669#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
670#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
671
672#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
673#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
674
675#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
676#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
677
678/* SCB Hard Fault Status Register Definitions */
679#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
680#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
681
682#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
683#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
684
685#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
686#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
687
688/* SCB Debug Fault Status Register Definitions */
689#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
690#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
691
692#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
693#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
694
695#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
696#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
697
698#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
699#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
700
701#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
702#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
703
704/*@} end of group CMSIS_SCB */
705
706
707/**
708 \ingroup CMSIS_core_register
709 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
710 \brief Type definitions for the System Control and ID Register not in the SCB
711 @{
712 */
713
714/**
715 \brief Structure type to access the System Control and ID Register not in the SCB.
716 */
717typedef struct
718{
719 uint32_t RESERVED0[1U];
720 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
721 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
722} SCnSCB_Type;
723
724/* Interrupt Controller Type Register Definitions */
725#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
726#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
727
728/* Auxiliary Control Register Definitions */
729#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
730#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
731
732#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
733#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
734
735#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
736#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
737
738#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
739#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
740
741#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
742#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
743
744/*@} end of group CMSIS_SCnotSCB */
745
746
747/**
748 \ingroup CMSIS_core_register
749 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
750 \brief Type definitions for the System Timer Registers.
751 @{
752 */
753
754/**
755 \brief Structure type to access the System Timer (SysTick).
756 */
757typedef struct
758{
759 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
760 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
761 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
762 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
763} SysTick_Type;
764
765/* SysTick Control / Status Register Definitions */
766#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
767#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
768
769#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
770#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
771
772#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
773#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
774
775#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
776#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
777
778/* SysTick Reload Register Definitions */
779#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
780#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
781
782/* SysTick Current Register Definitions */
783#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
784#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
785
786/* SysTick Calibration Register Definitions */
787#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
788#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
789
790#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
791#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
792
793#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
794#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
795
796/*@} end of group CMSIS_SysTick */
797
798
799/**
800 \ingroup CMSIS_core_register
801 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
802 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
803 @{
804 */
805
806/**
807 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
808 */
809typedef struct
810{
811 __OM union
812 {
813 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
814 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
815 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
816 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
817 uint32_t RESERVED0[864U];
818 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
819 uint32_t RESERVED1[15U];
820 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
821 uint32_t RESERVED2[15U];
822 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
823 uint32_t RESERVED3[29U];
824 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
825 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
826 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
827 uint32_t RESERVED4[43U];
828 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
829 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
830 uint32_t RESERVED5[6U];
831 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
832 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
833 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
834 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
835 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
836 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
837 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
838 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
839 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
840 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
841 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
842 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
843} ITM_Type;
844
845/* ITM Trace Privilege Register Definitions */
846#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
847#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
848
849/* ITM Trace Control Register Definitions */
850#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
851#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
852
853#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
854#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
855
856#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
857#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
858
859#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
860#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
861
862#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
863#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
864
865#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
866#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
867
868#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
869#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
870
871#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
872#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
873
874#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
875#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
876
877/* ITM Integration Write Register Definitions */
878#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
879#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
880
881/* ITM Integration Read Register Definitions */
882#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
883#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
884
885/* ITM Integration Mode Control Register Definitions */
886#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
887#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
888
889/* ITM Lock Status Register Definitions */
890#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
891#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
892
893#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
894#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
895
896#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
897#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
898
899/*@}*/ /* end of group CMSIS_ITM */
900
901
902/**
903 \ingroup CMSIS_core_register
904 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
905 \brief Type definitions for the Data Watchpoint and Trace (DWT)
906 @{
907 */
908
909/**
910 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
911 */
912typedef struct
913{
914 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
915 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
916 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
917 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
918 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
919 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
920 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
921 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
922 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
923 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
924 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
925 uint32_t RESERVED0[1U];
926 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
927 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
928 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
929 uint32_t RESERVED1[1U];
930 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
931 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
932 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
933 uint32_t RESERVED2[1U];
934 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
935 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
936 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
937} DWT_Type;
938
939/* DWT Control Register Definitions */
940#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
941#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
942
943#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
944#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
945
946#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
947#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
948
949#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
950#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
951
952#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
953#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
954
955#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
956#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
957
958#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
959#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
960
961#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
962#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
963
964#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
965#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
966
967#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
968#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
969
970#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
971#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
972
973#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
974#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
975
976#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
977#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
978
979#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
980#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
981
982#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
983#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
984
985#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
986#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
987
988#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
989#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
990
991#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
992#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
993
994/* DWT CPI Count Register Definitions */
995#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
996#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
997
998/* DWT Exception Overhead Count Register Definitions */
999#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
1000#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
1001
1002/* DWT Sleep Count Register Definitions */
1003#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
1004#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
1005
1006/* DWT LSU Count Register Definitions */
1007#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
1008#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
1009
1010/* DWT Folded-instruction Count Register Definitions */
1011#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
1012#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
1013
1014/* DWT Comparator Mask Register Definitions */
1015#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
1016#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
1017
1018/* DWT Comparator Function Register Definitions */
1019#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
1020#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
1021
1022#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
1023#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
1024
1025#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
1026#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
1027
1028#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
1029#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
1030
1031#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
1032#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
1033
1034#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
1035#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
1036
1037#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
1038#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
1039
1040#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
1041#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
1042
1043#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
1044#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
1045
1046/*@}*/ /* end of group CMSIS_DWT */
1047
1048
1049/**
1050 \ingroup CMSIS_core_register
1051 \defgroup CMSIS_TPI Trace Port Interface (TPI)
1052 \brief Type definitions for the Trace Port Interface (TPI)
1053 @{
1054 */
1055
1056/**
1057 \brief Structure type to access the Trace Port Interface Register (TPI).
1058 */
1059typedef struct
1060{
1061 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
1062 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
1063 uint32_t RESERVED0[2U];
1064 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
1065 uint32_t RESERVED1[55U];
1066 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
1067 uint32_t RESERVED2[131U];
1068 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
1069 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
1070 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
1071 uint32_t RESERVED3[759U];
1072 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
1073 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1074 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1075 uint32_t RESERVED4[1U];
1076 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1077 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1078 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
1079 uint32_t RESERVED5[39U];
1080 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1081 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
1082 uint32_t RESERVED7[8U];
1083 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1084 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
1085} TPI_Type;
1086
1087/* TPI Asynchronous Clock Prescaler Register Definitions */
1088#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
1089#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
1090
1091/* TPI Selected Pin Protocol Register Definitions */
1092#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
1093#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
1094
1095/* TPI Formatter and Flush Status Register Definitions */
1096#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
1097#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
1098
1099#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
1100#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
1101
1102#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
1103#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
1104
1105#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
1106#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
1107
1108/* TPI Formatter and Flush Control Register Definitions */
1109#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
1110#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
1111
1112#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
1113#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
1114
1115/* TPI TRIGGER Register Definitions */
1116#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
1117#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
1118
1119/* TPI Integration ETM Data Register Definitions (FIFO0) */
1120#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
1121#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
1122
1123#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
1124#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
1125
1126#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
1127#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
1128
1129#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
1130#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
1131
1132#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
1133#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
1134
1135#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
1136#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
1137
1138#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
1139#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
1140
1141/* TPI ITATBCTR2 Register Definitions */
1142#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
1143#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
1144
1145/* TPI Integration ITM Data Register Definitions (FIFO1) */
1146#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
1147#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
1148
1149#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
1150#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
1151
1152#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
1153#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
1154
1155#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
1156#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
1157
1158#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
1159#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
1160
1161#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
1162#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
1163
1164#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
1165#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
1166
1167/* TPI ITATBCTR0 Register Definitions */
1168#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
1169#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
1170
1171/* TPI Integration Mode Control Register Definitions */
1172#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
1173#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
1174
1175/* TPI DEVID Register Definitions */
1176#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
1177#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1178
1179#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
1180#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1181
1182#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
1183#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1184
1185#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
1186#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
1187
1188#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
1189#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
1190
1191#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
1192#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
1193
1194/* TPI DEVTYPE Register Definitions */
1195#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
1196#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1197
1198#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
1199#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
1200
1201/*@}*/ /* end of group CMSIS_TPI */
1202
1203
1204#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1205/**
1206 \ingroup CMSIS_core_register
1207 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1208 \brief Type definitions for the Memory Protection Unit (MPU)
1209 @{
1210 */
1211
1212/**
1213 \brief Structure type to access the Memory Protection Unit (MPU).
1214 */
1215typedef struct
1216{
1217 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1218 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1219 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
1220 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1221 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1222 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1223 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1224 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1225 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1226 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1227 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1228} MPU_Type;
1229
1230/* MPU Type Register Definitions */
1231#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
1232#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1233
1234#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
1235#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1236
1237#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
1238#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1239
1240/* MPU Control Register Definitions */
1241#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
1242#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1243
1244#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
1245#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1246
1247#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
1248#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1249
1250/* MPU Region Number Register Definitions */
1251#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1252#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1253
1254/* MPU Region Base Address Register Definitions */
1255#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
1256#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1257
1258#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
1259#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1260
1261#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
1262#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
1263
1264/* MPU Region Attribute and Size Register Definitions */
1265#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
1266#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1267
1268#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
1269#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
1270
1271#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
1272#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
1273
1274#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
1275#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
1276
1277#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
1278#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
1279
1280#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
1281#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
1282
1283#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
1284#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
1285
1286#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
1287#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1288
1289#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
1290#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1291
1292#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
1293#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
1294
1295/*@} end of group CMSIS_MPU */
1296#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
1297
1298
1299/**
1300 \ingroup CMSIS_core_register
1301 \defgroup CMSIS_FPU Floating Point Unit (FPU)
1302 \brief Type definitions for the Floating Point Unit (FPU)
1303 @{
1304 */
1305
1306/**
1307 \brief Structure type to access the Floating Point Unit (FPU).
1308 */
1309typedef struct
1310{
1311 uint32_t RESERVED0[1U];
1312 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
1313 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
1314 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
1315 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
1316 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
1317} FPU_Type;
1318
1319/* Floating-Point Context Control Register Definitions */
1320#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
1321#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
1322
1323#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
1324#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
1325
1326#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
1327#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
1328
1329#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
1330#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
1331
1332#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
1333#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
1334
1335#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
1336#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
1337
1338#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
1339#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
1340
1341#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
1342#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
1343
1344#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
1345#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
1346
1347/* Floating-Point Context Address Register Definitions */
1348#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
1349#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
1350
1351/* Floating-Point Default Status Control Register Definitions */
1352#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
1353#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
1354
1355#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
1356#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
1357
1358#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
1359#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
1360
1361#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
1362#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
1363
1364/* Media and FP Feature Register 0 Definitions */
1365#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
1366#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
1367
1368#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
1369#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
1370
1371#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
1372#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
1373
1374#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
1375#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
1376
1377#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
1378#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
1379
1380#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
1381#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
1382
1383#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
1384#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
1385
1386#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
1387#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
1388
1389/* Media and FP Feature Register 1 Definitions */
1390#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
1391#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
1392
1393#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
1394#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
1395
1396#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
1397#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
1398
1399#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
1400#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
1401
1402/*@} end of group CMSIS_FPU */
1403
1404
1405/**
1406 \ingroup CMSIS_core_register
1407 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1408 \brief Type definitions for the Core Debug Registers
1409 @{
1410 */
1411
1412/**
1413 \brief Structure type to access the Core Debug Register (CoreDebug).
1414 */
1415typedef struct
1416{
1417 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1418 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1419 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1420 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1421} CoreDebug_Type;
1422
1423/* Debug Halting Control and Status Register Definitions */
1424#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
1425#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1426
1427#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
1428#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1429
1430#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1431#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1432
1433#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
1434#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1435
1436#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
1437#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1438
1439#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
1440#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1441
1442#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
1443#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1444
1445#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1446#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1447
1448#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
1449#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1450
1451#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
1452#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1453
1454#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
1455#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1456
1457#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1458#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1459
1460/* Debug Core Register Selector Register Definitions */
1461#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
1462#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1463
1464#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
1465#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
1466
1467/* Debug Exception and Monitor Control Register Definitions */
1468#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
1469#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1470
1471#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
1472#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1473
1474#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
1475#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1476
1477#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
1478#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1479
1480#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
1481#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1482
1483#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
1484#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1485
1486#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
1487#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1488
1489#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
1490#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1491
1492#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
1493#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1494
1495#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
1496#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1497
1498#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1499#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1500
1501#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
1502#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1503
1504#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
1505#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1506
1507/*@} end of group CMSIS_CoreDebug */
1508
1509
1510/**
1511 \ingroup CMSIS_core_register
1512 \defgroup CMSIS_core_bitfield Core register bit field macros
1513 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1514 @{
1515 */
1516
1517/**
1518 \brief Mask and shift a bit field value for use in a register bit range.
1519 \param[in] field Name of the register bit field.
1520 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
1521 \return Masked and shifted value.
1522*/
1523#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1524
1525/**
1526 \brief Mask and shift a register value to extract a bit filed value.
1527 \param[in] field Name of the register bit field.
1528 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
1529 \return Masked and shifted bit field value.
1530*/
1531#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1532
1533/*@} end of group CMSIS_core_bitfield */
1534
1535
1536/**
1537 \ingroup CMSIS_core_register
1538 \defgroup CMSIS_core_base Core Definitions
1539 \brief Definitions for base addresses, unions, and structures.
1540 @{
1541 */
1542
1543/* Memory mapping of Core Hardware */
1544#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1545#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1546#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1547#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1548#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1549#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1550#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1551#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1552
1553#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1554#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1555#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1556#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1557#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1558#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1559#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1560#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
1561
1562#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1563 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1564 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1565#endif
1566
1567#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
1568#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
1569
1570/*@} */
1571
1572
1573
1574/*******************************************************************************
1575 * Hardware Abstraction Layer
1576 Core Function Interface contains:
1577 - Core NVIC Functions
1578 - Core SysTick Functions
1579 - Core Debug Functions
1580 - Core Register Access Functions
1581 ******************************************************************************/
1582/**
1583 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1584*/
1585
1586
1587
1588/* ########################## NVIC functions #################################### */
1589/**
1590 \ingroup CMSIS_Core_FunctionInterface
1591 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1592 \brief Functions that manage interrupts and exceptions via the NVIC.
1593 @{
1594 */
1595
1596#ifdef CMSIS_NVIC_VIRTUAL
1597 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1598 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1599 #endif
1600 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1601#else
1602 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1603 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1604 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1605 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1606 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1607 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1608 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1609 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1610 #define NVIC_GetActive __NVIC_GetActive
1611 #define NVIC_SetPriority __NVIC_SetPriority
1612 #define NVIC_GetPriority __NVIC_GetPriority
1613 #define NVIC_SystemReset __NVIC_SystemReset
1614#endif /* CMSIS_NVIC_VIRTUAL */
1615
1616#ifdef CMSIS_VECTAB_VIRTUAL
1617 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1618 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1619 #endif
1620 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1621#else
1622 #define NVIC_SetVector __NVIC_SetVector
1623 #define NVIC_GetVector __NVIC_GetVector
1624#endif /* (CMSIS_VECTAB_VIRTUAL) */
1625
1626#define NVIC_USER_IRQ_OFFSET 16
1627
1628
1629
1630/**
1631 \brief Set Priority Grouping
1632 \details Sets the priority grouping field using the required unlock sequence.
1633 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1634 Only values from 0..7 are used.
1635 In case of a conflict between priority grouping and available
1636 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1637 \param [in] PriorityGroup Priority grouping field.
1638 */
1639__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1640{
1641 uint32_t reg_value;
1642 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1643
1644 reg_value = SCB->AIRCR; /* read old register configuration */
1645 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1646 reg_value = (reg_value |
1647 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1648 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
1649 SCB->AIRCR = reg_value;
1650}
1651
1652
1653/**
1654 \brief Get Priority Grouping
1655 \details Reads the priority grouping field from the NVIC Interrupt Controller.
1656 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1657 */
1658__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
1659{
1660 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1661}
1662
1663
1664/**
1665 \brief Enable Interrupt
1666 \details Enables a device specific interrupt in the NVIC interrupt controller.
1667 \param [in] IRQn Device specific interrupt number.
1668 \note IRQn must not be negative.
1669 */
1670__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1671{
1672 if ((int32_t)(IRQn) >= 0)
1673 {
1674 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1675 }
1676}
1677
1678
1679/**
1680 \brief Get Interrupt Enable status
1681 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
1682 \param [in] IRQn Device specific interrupt number.
1683 \return 0 Interrupt is not enabled.
1684 \return 1 Interrupt is enabled.
1685 \note IRQn must not be negative.
1686 */
1687__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1688{
1689 if ((int32_t)(IRQn) >= 0)
1690 {
1691 return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1692 }
1693 else
1694 {
1695 return(0U);
1696 }
1697}
1698
1699
1700/**
1701 \brief Disable Interrupt
1702 \details Disables a device specific interrupt in the NVIC interrupt controller.
1703 \param [in] IRQn Device specific interrupt number.
1704 \note IRQn must not be negative.
1705 */
1706__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1707{
1708 if ((int32_t)(IRQn) >= 0)
1709 {
1710 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1711 __DSB();
1712 __ISB();
1713 }
1714}
1715
1716
1717/**
1718 \brief Get Pending Interrupt
1719 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
1720 \param [in] IRQn Device specific interrupt number.
1721 \return 0 Interrupt status is not pending.
1722 \return 1 Interrupt status is pending.
1723 \note IRQn must not be negative.
1724 */
1725__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1726{
1727 if ((int32_t)(IRQn) >= 0)
1728 {
1729 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1730 }
1731 else
1732 {
1733 return(0U);
1734 }
1735}
1736
1737
1738/**
1739 \brief Set Pending Interrupt
1740 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
1741 \param [in] IRQn Device specific interrupt number.
1742 \note IRQn must not be negative.
1743 */
1744__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1745{
1746 if ((int32_t)(IRQn) >= 0)
1747 {
1748 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1749 }
1750}
1751
1752
1753/**
1754 \brief Clear Pending Interrupt
1755 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
1756 \param [in] IRQn Device specific interrupt number.
1757 \note IRQn must not be negative.
1758 */
1759__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1760{
1761 if ((int32_t)(IRQn) >= 0)
1762 {
1763 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1764 }
1765}
1766
1767
1768/**
1769 \brief Get Active Interrupt
1770 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
1771 \param [in] IRQn Device specific interrupt number.
1772 \return 0 Interrupt status is not active.
1773 \return 1 Interrupt status is active.
1774 \note IRQn must not be negative.
1775 */
1776__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
1777{
1778 if ((int32_t)(IRQn) >= 0)
1779 {
1780 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1781 }
1782 else
1783 {
1784 return(0U);
1785 }
1786}
1787
1788
1789/**
1790 \brief Set Interrupt Priority
1791 \details Sets the priority of a device specific interrupt or a processor exception.
1792 The interrupt number can be positive to specify a device specific interrupt,
1793 or negative to specify a processor exception.
1794 \param [in] IRQn Interrupt number.
1795 \param [in] priority Priority to set.
1796 \note The priority cannot be set for every processor exception.
1797 */
1798__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1799{
1800 if ((int32_t)(IRQn) >= 0)
1801 {
1802 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1803 }
1804 else
1805 {
1806 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1807 }
1808}
1809
1810
1811/**
1812 \brief Get Interrupt Priority
1813 \details Reads the priority of a device specific interrupt or a processor exception.
1814 The interrupt number can be positive to specify a device specific interrupt,
1815 or negative to specify a processor exception.
1816 \param [in] IRQn Interrupt number.
1817 \return Interrupt Priority.
1818 Value is aligned automatically to the implemented priority bits of the microcontroller.
1819 */
1820__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
1821{
1822
1823 if ((int32_t)(IRQn) >= 0)
1824 {
1825 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
1826 }
1827 else
1828 {
1829 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
1830 }
1831}
1832
1833
1834/**
1835 \brief Encode Priority
1836 \details Encodes the priority for an interrupt with the given priority group,
1837 preemptive priority value, and subpriority value.
1838 In case of a conflict between priority grouping and available
1839 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1840 \param [in] PriorityGroup Used priority group.
1841 \param [in] PreemptPriority Preemptive priority value (starting from 0).
1842 \param [in] SubPriority Subpriority value (starting from 0).
1843 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1844 */
1845__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1846{
1847 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1848 uint32_t PreemptPriorityBits;
1849 uint32_t SubPriorityBits;
1850
1851 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1852 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1853
1854 return (
1855 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1856 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1857 );
1858}
1859
1860
1861/**
1862 \brief Decode Priority
1863 \details Decodes an interrupt priority value with a given priority group to
1864 preemptive priority value and subpriority value.
1865 In case of a conflict between priority grouping and available
1866 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1867 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1868 \param [in] PriorityGroup Used priority group.
1869 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1870 \param [out] pSubPriority Subpriority value (starting from 0).
1871 */
1872__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1873{
1874 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1875 uint32_t PreemptPriorityBits;
1876 uint32_t SubPriorityBits;
1877
1878 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1879 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1880
1881 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1882 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1883}
1884
1885
1886/**
1887 \brief Set Interrupt Vector
1888 \details Sets an interrupt vector in SRAM based interrupt vector table.
1889 The interrupt number can be positive to specify a device specific interrupt,
1890 or negative to specify a processor exception.
1891 VTOR must been relocated to SRAM before.
1892 \param [in] IRQn Interrupt number
1893 \param [in] vector Address of interrupt handler function
1894 */
1895__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
1896{
1897 uint32_t *vectors = (uint32_t *)SCB->VTOR;
1898 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
1899}
1900
1901
1902/**
1903 \brief Get Interrupt Vector
1904 \details Reads an interrupt vector from interrupt vector table.
1905 The interrupt number can be positive to specify a device specific interrupt,
1906 or negative to specify a processor exception.
1907 \param [in] IRQn Interrupt number.
1908 \return Address of interrupt handler function
1909 */
1910__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
1911{
1912 uint32_t *vectors = (uint32_t *)SCB->VTOR;
1913 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
1914}
1915
1916
1917/**
1918 \brief System Reset
1919 \details Initiates a system reset request to reset the MCU.
1920 */
1921__STATIC_INLINE void __NVIC_SystemReset(void)
1922{
1923 __DSB(); /* Ensure all outstanding memory accesses included
1924 buffered write are completed before reset */
1925 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1926 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1927 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
1928 __DSB(); /* Ensure completion of memory access */
1929
1930 for(;;) /* wait until reset */
1931 {
1932 __NOP();
1933 }
1934}
1935
1936/*@} end of CMSIS_Core_NVICFunctions */
1937
1938
1939/* ########################## FPU functions #################################### */
1940/**
1941 \ingroup CMSIS_Core_FunctionInterface
1942 \defgroup CMSIS_Core_FpuFunctions FPU Functions
1943 \brief Function that provides FPU type.
1944 @{
1945 */
1946
1947/**
1948 \brief get FPU type
1949 \details returns the FPU type
1950 \returns
1951 - \b 0: No FPU
1952 - \b 1: Single precision FPU
1953 - \b 2: Double + Single precision FPU
1954 */
1955__STATIC_INLINE uint32_t SCB_GetFPUType(void)
1956{
1957 uint32_t mvfr0;
1958
1959 mvfr0 = FPU->MVFR0;
1960 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
1961 {
1962 return 1U; /* Single precision FPU */
1963 }
1964 else
1965 {
1966 return 0U; /* No FPU */
1967 }
1968}
1969
1970
1971/*@} end of CMSIS_Core_FpuFunctions */
1972
1973
1974
1975/* ################################## SysTick function ############################################ */
1976/**
1977 \ingroup CMSIS_Core_FunctionInterface
1978 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1979 \brief Functions that configure the System.
1980 @{
1981 */
1982
1983#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
1984
1985/**
1986 \brief System Tick Configuration
1987 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
1988 Counter is in free running mode to generate periodic interrupts.
1989 \param [in] ticks Number of ticks between two interrupts.
1990 \return 0 Function succeeded.
1991 \return 1 Function failed.
1992 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1993 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1994 must contain a vendor-specific implementation of this function.
1995 */
1996__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1997{
1998 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1999 {
2000 return (1UL); /* Reload value impossible */
2001 }
2002
2003 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2004 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2005 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2006 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2007 SysTick_CTRL_TICKINT_Msk |
2008 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2009 return (0UL); /* Function successful */
2010}
2011
2012#endif
2013
2014/*@} end of CMSIS_Core_SysTickFunctions */
2015
2016
2017
2018/* ##################################### Debug In/Output function ########################################### */
2019/**
2020 \ingroup CMSIS_Core_FunctionInterface
2021 \defgroup CMSIS_core_DebugFunctions ITM Functions
2022 \brief Functions that access the ITM debug interface.
2023 @{
2024 */
2025
2026extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
2027#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
2028
2029
2030/**
2031 \brief ITM Send Character
2032 \details Transmits a character via the ITM channel 0, and
2033 \li Just returns when no debugger is connected that has booked the output.
2034 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
2035 \param [in] ch Character to transmit.
2036 \returns Character to transmit.
2037 */
2038__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2039{
2040 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
2041 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
2042 {
2043 while (ITM->PORT[0U].u32 == 0UL)
2044 {
2045 __NOP();
2046 }
2047 ITM->PORT[0U].u8 = (uint8_t)ch;
2048 }
2049 return (ch);
2050}
2051
2052
2053/**
2054 \brief ITM Receive Character
2055 \details Inputs a character via the external variable \ref ITM_RxBuffer.
2056 \return Received character.
2057 \return -1 No character pending.
2058 */
2059__STATIC_INLINE int32_t ITM_ReceiveChar (void)
2060{
2061 int32_t ch = -1; /* no character available */
2062
2063 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
2064 {
2065 ch = ITM_RxBuffer;
2066 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
2067 }
2068
2069 return (ch);
2070}
2071
2072
2073/**
2074 \brief ITM Check Character
2075 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
2076 \return 0 No character available.
2077 \return 1 Character available.
2078 */
2079__STATIC_INLINE int32_t ITM_CheckChar (void)
2080{
2081
2082 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
2083 {
2084 return (0); /* no character available */
2085 }
2086 else
2087 {
2088 return (1); /* character available */
2089 }
2090}
2091
2092/*@} end of CMSIS_core_DebugFunctions */
2093
2094
2095
2096
2097#ifdef __cplusplus
2098}
2099#endif
2100
2101#endif /* __CORE_CM4_H_DEPENDANT */
2102
2103#endif /* __CMSIS_GENERIC */