Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief Generic CMCC(Cortex M Cache Controller) related functionality. |
| 5 | * |
| 6 | * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | /* |
| 34 | * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a> |
| 35 | */ |
| 36 | |
| 37 | #ifndef HPL_CMCC_H_ |
| 38 | #define HPL_CMCC_H_ |
| 39 | |
| 40 | #ifdef __cplusplus |
| 41 | extern "C" { |
| 42 | #endif |
| 43 | |
| 44 | #include <stdint.h> |
| 45 | #include <stdbool.h> |
| 46 | |
| 47 | /** |
| 48 | * \Cache driver MACROS |
| 49 | */ |
| 50 | #define CMCC_DISABLE 0U |
| 51 | #define CMCC_ENABLE 1U |
| 52 | #define IS_CMCC_DISABLED 0U |
| 53 | #define IS_CMCC_ENABLED 1U |
| 54 | #define CMCC_WAY_NOS 4U |
| 55 | #define CMCC_LINE_NOS 64U |
| 56 | #define CMCC_MONITOR_DISABLE 0U |
| 57 | |
| 58 | /** |
| 59 | * \brief Cache size configurations |
| 60 | */ |
| 61 | enum conf_cache_size { CONF_CSIZE_1KB = 0u, CONF_CSIZE_2KB, CONF_CSIZE_4KB }; |
| 62 | |
| 63 | /** |
| 64 | * \brief Way Numbers |
| 65 | */ |
| 66 | enum way_num_index { WAY0 = 1u, WAY1 = 2u, WAY2 = 4u, WAY3 = 8 }; |
| 67 | |
| 68 | /** |
| 69 | * \brief Cache monitor configurations |
| 70 | */ |
| 71 | enum conf_cache_monitor { CYCLE_COUNT = 0u, IHIT_COUNT, DHIT_COUNT }; |
| 72 | |
| 73 | /** |
| 74 | * \brief Cache configuration structure |
| 75 | */ |
| 76 | struct _cache_cfg { |
| 77 | enum conf_cache_size cache_size; |
| 78 | bool data_cache_disable; |
| 79 | bool inst_cache_disable; |
| 80 | bool gclk_gate_disable; |
| 81 | }; |
| 82 | |
| 83 | /** |
| 84 | * \brief Cache enable status |
| 85 | */ |
| 86 | static inline bool _is_cache_enabled(const void *hw) |
| 87 | { |
| 88 | return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_ENABLED ? true : false); |
| 89 | } |
| 90 | |
| 91 | /** |
| 92 | * \brief Cache disable status |
| 93 | */ |
| 94 | static inline bool _is_cache_disabled(const void *hw) |
| 95 | { |
| 96 | return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_DISABLED ? true : false); |
| 97 | } |
| 98 | |
| 99 | /** |
| 100 | * \brief Cache enable |
| 101 | */ |
| 102 | static inline int32_t _cmcc_enable(const void *hw) |
| 103 | { |
| 104 | int32_t return_value; |
| 105 | |
| 106 | if (_is_cache_disabled(hw)) { |
| 107 | hri_cmcc_write_CTRL_reg(hw, CMCC_CTRL_CEN); |
| 108 | return_value = _is_cache_enabled(hw) == true ? ERR_NONE : ERR_FAILURE; |
| 109 | } else { |
| 110 | return_value = ERR_NO_CHANGE; |
| 111 | } |
| 112 | |
| 113 | return return_value; |
| 114 | } |
| 115 | |
| 116 | /** |
| 117 | * \brief Cache disable |
| 118 | */ |
| 119 | static inline int32_t _cmcc_disable(const void *hw) |
| 120 | { |
| 121 | hri_cmcc_write_CTRL_reg(hw, (CMCC_DISABLE << CMCC_CTRL_CEN_Pos)); |
| 122 | while (!(_is_cache_disabled(hw))) |
| 123 | ; |
| 124 | |
| 125 | return ERR_NONE; |
| 126 | } |
| 127 | |
| 128 | /** |
| 129 | * \brief Initialize Cache Module |
| 130 | * |
| 131 | * This function initialize low level cmcc module configuration. |
| 132 | * |
| 133 | * \return initialize status |
| 134 | */ |
| 135 | int32_t _cmcc_init(void); |
| 136 | |
| 137 | /** |
| 138 | * \brief Configure CMCC module |
| 139 | * |
| 140 | * \param[in] pointer pointing to the starting address of CMCC module |
| 141 | * \param[in] cache configuration structure pointer |
| 142 | * |
| 143 | * \return status of operation |
| 144 | */ |
| 145 | int32_t _cmcc_configure(const void *hw, struct _cache_cfg *cache_ctrl); |
| 146 | |
| 147 | /** |
| 148 | * \brief Enable data cache in CMCC module |
| 149 | * |
| 150 | * \param[in] pointer pointing to the starting address of CMCC module |
| 151 | * \param[in] boolean 1 -> Enable the data cache, 0 -> disable the data cache |
| 152 | * |
| 153 | * \return status of operation |
| 154 | */ |
| 155 | int32_t _cmcc_enable_data_cache(const void *hw, bool value); |
| 156 | |
| 157 | /** |
| 158 | * \brief Enable instruction cache in CMCC module |
| 159 | * |
| 160 | * \param[in] pointer pointing to the starting address of CMCC module |
| 161 | * \param[in] boolean 1 -> Enable the inst cache, 0 -> disable the inst cache |
| 162 | * |
| 163 | * \return status of operation |
| 164 | */ |
| 165 | int32_t _cmcc_enable_inst_cache(const void *hw, bool value); |
| 166 | |
| 167 | /** |
| 168 | * \brief Enable clock gating in CMCC module |
| 169 | * |
| 170 | * \param[in] pointer pointing to the starting address of CMCC module |
| 171 | * \param[in] boolean 1 -> Enable the clock gate, 0 -> disable the clock gate |
| 172 | * |
| 173 | * \return status of operation |
| 174 | */ |
| 175 | int32_t _cmcc_enable_clock_gating(const void *hw, bool value); |
| 176 | |
| 177 | /** |
| 178 | * \brief Configure the cache size in CMCC module |
| 179 | * |
| 180 | * \param[in] pointer pointing to the starting address of CMCC module |
| 181 | * \param[in] element from cache size configuration enumerator |
| 182 | * 0->1K, 1->2K, 2->4K(default) |
| 183 | * |
| 184 | * \return status of operation |
| 185 | */ |
| 186 | int32_t _cmcc_configure_cache_size(const void *hw, enum conf_cache_size size); |
| 187 | |
| 188 | /** |
| 189 | * \brief Lock the mentioned WAY in CMCC module |
| 190 | * |
| 191 | * \param[in] pointer pointing to the starting address of CMCC module |
| 192 | * \param[in] element from "way_num_index" enumerator |
| 193 | * |
| 194 | * \return status of operation |
| 195 | */ |
| 196 | int32_t _cmcc_lock_way(const void *hw, enum way_num_index); |
| 197 | |
| 198 | /** |
| 199 | * \brief Unlock the mentioned WAY in CMCC module |
| 200 | * |
| 201 | * \param[in] pointer pointing to the starting address of CMCC module |
| 202 | * \param[in] element from "way_num_index" enumerator |
| 203 | * |
| 204 | * \return status of operation |
| 205 | */ |
| 206 | int32_t _cmcc_unlock_way(const void *hw, enum way_num_index); |
| 207 | |
| 208 | /** |
| 209 | * \brief Invalidate the mentioned cache line in CMCC module |
| 210 | * |
| 211 | * \param[in] pointer pointing to the starting address of CMCC module |
| 212 | * \param[in] element from "way_num" enumerator (valid arg is 0-3) |
| 213 | * \param[in] line number (valid arg is 0-63 as each way will have 64 lines) |
| 214 | * |
| 215 | * \return status of operation |
| 216 | */ |
| 217 | int32_t _cmcc_invalidate_by_line(const void *hw, uint8_t way_num, uint8_t line_num); |
| 218 | |
| 219 | /** |
| 220 | * \brief Invalidate entire cache entries in CMCC module |
| 221 | * |
| 222 | * \param[in] pointer pointing to the starting address of CMCC module |
| 223 | * |
| 224 | * \return status of operation |
| 225 | */ |
| 226 | int32_t _cmcc_invalidate_all(const void *hw); |
| 227 | |
| 228 | /** |
| 229 | * \brief Configure cache monitor in CMCC module |
| 230 | * |
| 231 | * \param[in] pointer pointing to the starting address of CMCC module |
| 232 | * \param[in] element from cache monitor configurations enumerator |
| 233 | * |
| 234 | * \return status of operation |
| 235 | */ |
| 236 | int32_t _cmcc_configure_monitor(const void *hw, enum conf_cache_monitor monitor_cfg); |
| 237 | |
| 238 | /** |
| 239 | * \brief Enable cache monitor in CMCC module |
| 240 | * |
| 241 | * \param[in] pointer pointing to the starting address of CMCC module |
| 242 | * |
| 243 | * \return status of operation |
| 244 | */ |
| 245 | int32_t _cmcc_enable_monitor(const void *hw); |
| 246 | |
| 247 | /** |
| 248 | * \brief Disable cache monitor in CMCC module |
| 249 | * |
| 250 | * \param[in] pointer pointing to the starting address of CMCC module |
| 251 | * |
| 252 | * \return status of operation |
| 253 | */ |
| 254 | int32_t _cmcc_disable_monitor(const void *hw); |
| 255 | |
| 256 | /** |
| 257 | * \brief Reset cache monitor in CMCC module |
| 258 | * |
| 259 | * \param[in] pointer pointing to the starting address of CMCC module |
| 260 | * |
| 261 | * \return status of operation |
| 262 | */ |
| 263 | int32_t _cmcc_reset_monitor(const void *hw); |
| 264 | |
| 265 | /** |
| 266 | * \brief Get cache monitor event counter value from CMCC module |
| 267 | * |
| 268 | * \param[in] pointer pointing to the starting address of CMCC module |
| 269 | * |
| 270 | * \return event counter value |
| 271 | */ |
| 272 | uint32_t _cmcc_get_monitor_event_count(const void *hw); |
| 273 | |
| 274 | #ifdef __cplusplus |
| 275 | } |
| 276 | #endif |
| 277 | #endif /* HPL_CMCC_H_ */ |