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gerrit.osmocom.org / osmo-ccid-firmware / bcbc1978e19102aae82d13880d171b9b34d455e5 / . / sysmoOCTSIM / include / component / supc.h
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Kévin Redon69b92d92019-01-24 16:39:20 +0100[diff] [blame]1/**
2 * \file
3 *
4 * \brief Component description for SUPC
5 *
6 * Copyright (c) 2018 Microchip Technology Inc.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * SPDX-License-Identifier: Apache-2.0
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License"); you may
15 * not use this file except in compliance with the License.
16 * You may obtain a copy of the Licence at
17 *
18 * http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *
26 * \asf_license_stop
27 *
28 */
29
30#ifndef _SAME54_SUPC_COMPONENT_
31#define _SAME54_SUPC_COMPONENT_
32
33/* ========================================================================== */
34/** SOFTWARE API DEFINITION FOR SUPC */
35/* ========================================================================== */
36/** \addtogroup SAME54_SUPC Supply Controller */
37/*@{*/
38
39#define SUPC_U2407
40#define REV_SUPC 0x110
41
42/* -------- SUPC_INTENCLR : (SUPC Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
43#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
44typedef union {
45 struct {
46 uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */
47 uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */
48 uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */
49 uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */
50 uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */
51 uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */
52 uint32_t :2; /*!< bit: 6.. 7 Reserved */
53 uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */
54 uint32_t :1; /*!< bit: 9 Reserved */
55 uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */
56 uint32_t :21; /*!< bit: 11..31 Reserved */
57 } bit; /*!< Structure used for bit access */
58 uint32_t reg; /*!< Type used for register access */
59} SUPC_INTENCLR_Type;
60#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
61
62#define SUPC_INTENCLR_OFFSET 0x00 /**< \brief (SUPC_INTENCLR offset) Interrupt Enable Clear */
63#define SUPC_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_INTENCLR reset_value) Interrupt Enable Clear */
64
65#define SUPC_INTENCLR_BOD33RDY_Pos 0 /**< \brief (SUPC_INTENCLR) BOD33 Ready */
66#define SUPC_INTENCLR_BOD33RDY (_U_(0x1) << SUPC_INTENCLR_BOD33RDY_Pos)
67#define SUPC_INTENCLR_BOD33DET_Pos 1 /**< \brief (SUPC_INTENCLR) BOD33 Detection */
68#define SUPC_INTENCLR_BOD33DET (_U_(0x1) << SUPC_INTENCLR_BOD33DET_Pos)
69#define SUPC_INTENCLR_B33SRDY_Pos 2 /**< \brief (SUPC_INTENCLR) BOD33 Synchronization Ready */
70#define SUPC_INTENCLR_B33SRDY (_U_(0x1) << SUPC_INTENCLR_B33SRDY_Pos)
71#define SUPC_INTENCLR_BOD12RDY_Pos 3 /**< \brief (SUPC_INTENCLR) BOD12 Ready */
72#define SUPC_INTENCLR_BOD12RDY (_U_(0x1) << SUPC_INTENCLR_BOD12RDY_Pos)
73#define SUPC_INTENCLR_BOD12DET_Pos 4 /**< \brief (SUPC_INTENCLR) BOD12 Detection */
74#define SUPC_INTENCLR_BOD12DET (_U_(0x1) << SUPC_INTENCLR_BOD12DET_Pos)
75#define SUPC_INTENCLR_B12SRDY_Pos 5 /**< \brief (SUPC_INTENCLR) BOD12 Synchronization Ready */
76#define SUPC_INTENCLR_B12SRDY (_U_(0x1) << SUPC_INTENCLR_B12SRDY_Pos)
77#define SUPC_INTENCLR_VREGRDY_Pos 8 /**< \brief (SUPC_INTENCLR) Voltage Regulator Ready */
78#define SUPC_INTENCLR_VREGRDY (_U_(0x1) << SUPC_INTENCLR_VREGRDY_Pos)
79#define SUPC_INTENCLR_VCORERDY_Pos 10 /**< \brief (SUPC_INTENCLR) VDDCORE Ready */
80#define SUPC_INTENCLR_VCORERDY (_U_(0x1) << SUPC_INTENCLR_VCORERDY_Pos)
81#define SUPC_INTENCLR_MASK _U_(0x0000053F) /**< \brief (SUPC_INTENCLR) MASK Register */
82
83/* -------- SUPC_INTENSET : (SUPC Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
84#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
85typedef union {
86 struct {
87 uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */
88 uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */
89 uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */
90 uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */
91 uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */
92 uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */
93 uint32_t :2; /*!< bit: 6.. 7 Reserved */
94 uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */
95 uint32_t :1; /*!< bit: 9 Reserved */
96 uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */
97 uint32_t :21; /*!< bit: 11..31 Reserved */
98 } bit; /*!< Structure used for bit access */
99 uint32_t reg; /*!< Type used for register access */
100} SUPC_INTENSET_Type;
101#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
102
103#define SUPC_INTENSET_OFFSET 0x04 /**< \brief (SUPC_INTENSET offset) Interrupt Enable Set */
104#define SUPC_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_INTENSET reset_value) Interrupt Enable Set */
105
106#define SUPC_INTENSET_BOD33RDY_Pos 0 /**< \brief (SUPC_INTENSET) BOD33 Ready */
107#define SUPC_INTENSET_BOD33RDY (_U_(0x1) << SUPC_INTENSET_BOD33RDY_Pos)
108#define SUPC_INTENSET_BOD33DET_Pos 1 /**< \brief (SUPC_INTENSET) BOD33 Detection */
109#define SUPC_INTENSET_BOD33DET (_U_(0x1) << SUPC_INTENSET_BOD33DET_Pos)
110#define SUPC_INTENSET_B33SRDY_Pos 2 /**< \brief (SUPC_INTENSET) BOD33 Synchronization Ready */
111#define SUPC_INTENSET_B33SRDY (_U_(0x1) << SUPC_INTENSET_B33SRDY_Pos)
112#define SUPC_INTENSET_BOD12RDY_Pos 3 /**< \brief (SUPC_INTENSET) BOD12 Ready */
113#define SUPC_INTENSET_BOD12RDY (_U_(0x1) << SUPC_INTENSET_BOD12RDY_Pos)
114#define SUPC_INTENSET_BOD12DET_Pos 4 /**< \brief (SUPC_INTENSET) BOD12 Detection */
115#define SUPC_INTENSET_BOD12DET (_U_(0x1) << SUPC_INTENSET_BOD12DET_Pos)
116#define SUPC_INTENSET_B12SRDY_Pos 5 /**< \brief (SUPC_INTENSET) BOD12 Synchronization Ready */
117#define SUPC_INTENSET_B12SRDY (_U_(0x1) << SUPC_INTENSET_B12SRDY_Pos)
118#define SUPC_INTENSET_VREGRDY_Pos 8 /**< \brief (SUPC_INTENSET) Voltage Regulator Ready */
119#define SUPC_INTENSET_VREGRDY (_U_(0x1) << SUPC_INTENSET_VREGRDY_Pos)
120#define SUPC_INTENSET_VCORERDY_Pos 10 /**< \brief (SUPC_INTENSET) VDDCORE Ready */
121#define SUPC_INTENSET_VCORERDY (_U_(0x1) << SUPC_INTENSET_VCORERDY_Pos)
122#define SUPC_INTENSET_MASK _U_(0x0000053F) /**< \brief (SUPC_INTENSET) MASK Register */
123
124/* -------- SUPC_INTFLAG : (SUPC Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
125#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
126typedef union { // __I to avoid read-modify-write on write-to-clear register
127 struct {
128 __I uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */
129 __I uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */
130 __I uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */
131 __I uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */
132 __I uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */
133 __I uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */
134 __I uint32_t :2; /*!< bit: 6.. 7 Reserved */
135 __I uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */
136 __I uint32_t :1; /*!< bit: 9 Reserved */
137 __I uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */
138 __I uint32_t :21; /*!< bit: 11..31 Reserved */
139 } bit; /*!< Structure used for bit access */
140 uint32_t reg; /*!< Type used for register access */
141} SUPC_INTFLAG_Type;
142#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
143
144#define SUPC_INTFLAG_OFFSET 0x08 /**< \brief (SUPC_INTFLAG offset) Interrupt Flag Status and Clear */
145#define SUPC_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_INTFLAG reset_value) Interrupt Flag Status and Clear */
146
147#define SUPC_INTFLAG_BOD33RDY_Pos 0 /**< \brief (SUPC_INTFLAG) BOD33 Ready */
148#define SUPC_INTFLAG_BOD33RDY (_U_(0x1) << SUPC_INTFLAG_BOD33RDY_Pos)
149#define SUPC_INTFLAG_BOD33DET_Pos 1 /**< \brief (SUPC_INTFLAG) BOD33 Detection */
150#define SUPC_INTFLAG_BOD33DET (_U_(0x1) << SUPC_INTFLAG_BOD33DET_Pos)
151#define SUPC_INTFLAG_B33SRDY_Pos 2 /**< \brief (SUPC_INTFLAG) BOD33 Synchronization Ready */
152#define SUPC_INTFLAG_B33SRDY (_U_(0x1) << SUPC_INTFLAG_B33SRDY_Pos)
153#define SUPC_INTFLAG_BOD12RDY_Pos 3 /**< \brief (SUPC_INTFLAG) BOD12 Ready */
154#define SUPC_INTFLAG_BOD12RDY (_U_(0x1) << SUPC_INTFLAG_BOD12RDY_Pos)
155#define SUPC_INTFLAG_BOD12DET_Pos 4 /**< \brief (SUPC_INTFLAG) BOD12 Detection */
156#define SUPC_INTFLAG_BOD12DET (_U_(0x1) << SUPC_INTFLAG_BOD12DET_Pos)
157#define SUPC_INTFLAG_B12SRDY_Pos 5 /**< \brief (SUPC_INTFLAG) BOD12 Synchronization Ready */
158#define SUPC_INTFLAG_B12SRDY (_U_(0x1) << SUPC_INTFLAG_B12SRDY_Pos)
159#define SUPC_INTFLAG_VREGRDY_Pos 8 /**< \brief (SUPC_INTFLAG) Voltage Regulator Ready */
160#define SUPC_INTFLAG_VREGRDY (_U_(0x1) << SUPC_INTFLAG_VREGRDY_Pos)
161#define SUPC_INTFLAG_VCORERDY_Pos 10 /**< \brief (SUPC_INTFLAG) VDDCORE Ready */
162#define SUPC_INTFLAG_VCORERDY (_U_(0x1) << SUPC_INTFLAG_VCORERDY_Pos)
163#define SUPC_INTFLAG_MASK _U_(0x0000053F) /**< \brief (SUPC_INTFLAG) MASK Register */
164
165/* -------- SUPC_STATUS : (SUPC Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */
166#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
167typedef union {
168 struct {
169 uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */
170 uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */
171 uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */
172 uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */
173 uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */
174 uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */
175 uint32_t :2; /*!< bit: 6.. 7 Reserved */
176 uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */
177 uint32_t :1; /*!< bit: 9 Reserved */
178 uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */
179 uint32_t :21; /*!< bit: 11..31 Reserved */
180 } bit; /*!< Structure used for bit access */
181 uint32_t reg; /*!< Type used for register access */
182} SUPC_STATUS_Type;
183#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
184
185#define SUPC_STATUS_OFFSET 0x0C /**< \brief (SUPC_STATUS offset) Power and Clocks Status */
186#define SUPC_STATUS_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_STATUS reset_value) Power and Clocks Status */
187
188#define SUPC_STATUS_BOD33RDY_Pos 0 /**< \brief (SUPC_STATUS) BOD33 Ready */
189#define SUPC_STATUS_BOD33RDY (_U_(0x1) << SUPC_STATUS_BOD33RDY_Pos)
190#define SUPC_STATUS_BOD33DET_Pos 1 /**< \brief (SUPC_STATUS) BOD33 Detection */
191#define SUPC_STATUS_BOD33DET (_U_(0x1) << SUPC_STATUS_BOD33DET_Pos)
192#define SUPC_STATUS_B33SRDY_Pos 2 /**< \brief (SUPC_STATUS) BOD33 Synchronization Ready */
193#define SUPC_STATUS_B33SRDY (_U_(0x1) << SUPC_STATUS_B33SRDY_Pos)
194#define SUPC_STATUS_BOD12RDY_Pos 3 /**< \brief (SUPC_STATUS) BOD12 Ready */
195#define SUPC_STATUS_BOD12RDY (_U_(0x1) << SUPC_STATUS_BOD12RDY_Pos)
196#define SUPC_STATUS_BOD12DET_Pos 4 /**< \brief (SUPC_STATUS) BOD12 Detection */
197#define SUPC_STATUS_BOD12DET (_U_(0x1) << SUPC_STATUS_BOD12DET_Pos)
198#define SUPC_STATUS_B12SRDY_Pos 5 /**< \brief (SUPC_STATUS) BOD12 Synchronization Ready */
199#define SUPC_STATUS_B12SRDY (_U_(0x1) << SUPC_STATUS_B12SRDY_Pos)
200#define SUPC_STATUS_VREGRDY_Pos 8 /**< \brief (SUPC_STATUS) Voltage Regulator Ready */
201#define SUPC_STATUS_VREGRDY (_U_(0x1) << SUPC_STATUS_VREGRDY_Pos)
202#define SUPC_STATUS_VCORERDY_Pos 10 /**< \brief (SUPC_STATUS) VDDCORE Ready */
203#define SUPC_STATUS_VCORERDY (_U_(0x1) << SUPC_STATUS_VCORERDY_Pos)
204#define SUPC_STATUS_MASK _U_(0x0000053F) /**< \brief (SUPC_STATUS) MASK Register */
205
206/* -------- SUPC_BOD33 : (SUPC Offset: 0x10) (R/W 32) BOD33 Control -------- */
207#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
208typedef union {
209 struct {
210 uint32_t :1; /*!< bit: 0 Reserved */
211 uint32_t ENABLE:1; /*!< bit: 1 Enable */
212 uint32_t ACTION:2; /*!< bit: 2.. 3 Action when Threshold Crossed */
213 uint32_t STDBYCFG:1; /*!< bit: 4 Configuration in Standby mode */
214 uint32_t RUNSTDBY:1; /*!< bit: 5 Run in Standby mode */
215 uint32_t RUNHIB:1; /*!< bit: 6 Run in Hibernate mode */
216 uint32_t RUNBKUP:1; /*!< bit: 7 Run in Backup mode */
217 uint32_t HYST:4; /*!< bit: 8..11 Hysteresis value */
218 uint32_t PSEL:3; /*!< bit: 12..14 Prescaler Select */
219 uint32_t :1; /*!< bit: 15 Reserved */
220 uint32_t LEVEL:8; /*!< bit: 16..23 Threshold Level for VDD */
221 uint32_t VBATLEVEL:8; /*!< bit: 24..31 Threshold Level in battery backup sleep mode for VBAT */
222 } bit; /*!< Structure used for bit access */
223 uint32_t reg; /*!< Type used for register access */
224} SUPC_BOD33_Type;
225#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
226
227#define SUPC_BOD33_OFFSET 0x10 /**< \brief (SUPC_BOD33 offset) BOD33 Control */
228#define SUPC_BOD33_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_BOD33 reset_value) BOD33 Control */
229
230#define SUPC_BOD33_ENABLE_Pos 1 /**< \brief (SUPC_BOD33) Enable */
231#define SUPC_BOD33_ENABLE (_U_(0x1) << SUPC_BOD33_ENABLE_Pos)
232#define SUPC_BOD33_ACTION_Pos 2 /**< \brief (SUPC_BOD33) Action when Threshold Crossed */
233#define SUPC_BOD33_ACTION_Msk (_U_(0x3) << SUPC_BOD33_ACTION_Pos)
234#define SUPC_BOD33_ACTION(value) (SUPC_BOD33_ACTION_Msk & ((value) << SUPC_BOD33_ACTION_Pos))
235#define SUPC_BOD33_ACTION_NONE_Val _U_(0x0) /**< \brief (SUPC_BOD33) No action */
236#define SUPC_BOD33_ACTION_RESET_Val _U_(0x1) /**< \brief (SUPC_BOD33) The BOD33 generates a reset */
237#define SUPC_BOD33_ACTION_INT_Val _U_(0x2) /**< \brief (SUPC_BOD33) The BOD33 generates an interrupt */
238#define SUPC_BOD33_ACTION_BKUP_Val _U_(0x3) /**< \brief (SUPC_BOD33) The BOD33 puts the device in backup sleep mode */
239#define SUPC_BOD33_ACTION_NONE (SUPC_BOD33_ACTION_NONE_Val << SUPC_BOD33_ACTION_Pos)
240#define SUPC_BOD33_ACTION_RESET (SUPC_BOD33_ACTION_RESET_Val << SUPC_BOD33_ACTION_Pos)
241#define SUPC_BOD33_ACTION_INT (SUPC_BOD33_ACTION_INT_Val << SUPC_BOD33_ACTION_Pos)
242#define SUPC_BOD33_ACTION_BKUP (SUPC_BOD33_ACTION_BKUP_Val << SUPC_BOD33_ACTION_Pos)
243#define SUPC_BOD33_STDBYCFG_Pos 4 /**< \brief (SUPC_BOD33) Configuration in Standby mode */
244#define SUPC_BOD33_STDBYCFG (_U_(0x1) << SUPC_BOD33_STDBYCFG_Pos)
245#define SUPC_BOD33_RUNSTDBY_Pos 5 /**< \brief (SUPC_BOD33) Run in Standby mode */
246#define SUPC_BOD33_RUNSTDBY (_U_(0x1) << SUPC_BOD33_RUNSTDBY_Pos)
247#define SUPC_BOD33_RUNHIB_Pos 6 /**< \brief (SUPC_BOD33) Run in Hibernate mode */
248#define SUPC_BOD33_RUNHIB (_U_(0x1) << SUPC_BOD33_RUNHIB_Pos)
249#define SUPC_BOD33_RUNBKUP_Pos 7 /**< \brief (SUPC_BOD33) Run in Backup mode */
250#define SUPC_BOD33_RUNBKUP (_U_(0x1) << SUPC_BOD33_RUNBKUP_Pos)
251#define SUPC_BOD33_HYST_Pos 8 /**< \brief (SUPC_BOD33) Hysteresis value */
252#define SUPC_BOD33_HYST_Msk (_U_(0xF) << SUPC_BOD33_HYST_Pos)
253#define SUPC_BOD33_HYST(value) (SUPC_BOD33_HYST_Msk & ((value) << SUPC_BOD33_HYST_Pos))
254#define SUPC_BOD33_PSEL_Pos 12 /**< \brief (SUPC_BOD33) Prescaler Select */
255#define SUPC_BOD33_PSEL_Msk (_U_(0x7) << SUPC_BOD33_PSEL_Pos)
256#define SUPC_BOD33_PSEL(value) (SUPC_BOD33_PSEL_Msk & ((value) << SUPC_BOD33_PSEL_Pos))
257#define SUPC_BOD33_PSEL_NODIV_Val _U_(0x0) /**< \brief (SUPC_BOD33) Not divided */
258#define SUPC_BOD33_PSEL_DIV4_Val _U_(0x1) /**< \brief (SUPC_BOD33) Divide clock by 4 */
259#define SUPC_BOD33_PSEL_DIV8_Val _U_(0x2) /**< \brief (SUPC_BOD33) Divide clock by 8 */
260#define SUPC_BOD33_PSEL_DIV16_Val _U_(0x3) /**< \brief (SUPC_BOD33) Divide clock by 16 */
261#define SUPC_BOD33_PSEL_DIV32_Val _U_(0x4) /**< \brief (SUPC_BOD33) Divide clock by 32 */
262#define SUPC_BOD33_PSEL_DIV64_Val _U_(0x5) /**< \brief (SUPC_BOD33) Divide clock by 64 */
263#define SUPC_BOD33_PSEL_DIV128_Val _U_(0x6) /**< \brief (SUPC_BOD33) Divide clock by 128 */
264#define SUPC_BOD33_PSEL_DIV256_Val _U_(0x7) /**< \brief (SUPC_BOD33) Divide clock by 256 */
265#define SUPC_BOD33_PSEL_NODIV (SUPC_BOD33_PSEL_NODIV_Val << SUPC_BOD33_PSEL_Pos)
266#define SUPC_BOD33_PSEL_DIV4 (SUPC_BOD33_PSEL_DIV4_Val << SUPC_BOD33_PSEL_Pos)
267#define SUPC_BOD33_PSEL_DIV8 (SUPC_BOD33_PSEL_DIV8_Val << SUPC_BOD33_PSEL_Pos)
268#define SUPC_BOD33_PSEL_DIV16 (SUPC_BOD33_PSEL_DIV16_Val << SUPC_BOD33_PSEL_Pos)
269#define SUPC_BOD33_PSEL_DIV32 (SUPC_BOD33_PSEL_DIV32_Val << SUPC_BOD33_PSEL_Pos)
270#define SUPC_BOD33_PSEL_DIV64 (SUPC_BOD33_PSEL_DIV64_Val << SUPC_BOD33_PSEL_Pos)
271#define SUPC_BOD33_PSEL_DIV128 (SUPC_BOD33_PSEL_DIV128_Val << SUPC_BOD33_PSEL_Pos)
272#define SUPC_BOD33_PSEL_DIV256 (SUPC_BOD33_PSEL_DIV256_Val << SUPC_BOD33_PSEL_Pos)
273#define SUPC_BOD33_LEVEL_Pos 16 /**< \brief (SUPC_BOD33) Threshold Level for VDD */
274#define SUPC_BOD33_LEVEL_Msk (_U_(0xFF) << SUPC_BOD33_LEVEL_Pos)
275#define SUPC_BOD33_LEVEL(value) (SUPC_BOD33_LEVEL_Msk & ((value) << SUPC_BOD33_LEVEL_Pos))
276#define SUPC_BOD33_VBATLEVEL_Pos 24 /**< \brief (SUPC_BOD33) Threshold Level in battery backup sleep mode for VBAT */
277#define SUPC_BOD33_VBATLEVEL_Msk (_U_(0xFF) << SUPC_BOD33_VBATLEVEL_Pos)
278#define SUPC_BOD33_VBATLEVEL(value) (SUPC_BOD33_VBATLEVEL_Msk & ((value) << SUPC_BOD33_VBATLEVEL_Pos))
279#define SUPC_BOD33_MASK _U_(0xFFFF7FFE) /**< \brief (SUPC_BOD33) MASK Register */
280
281/* -------- SUPC_BOD12 : (SUPC Offset: 0x14) (R/W 32) BOD12 Control -------- */
282#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
283typedef union {
284 struct {
285 uint32_t :1; /*!< bit: 0 Reserved */
286 uint32_t ENABLE:1; /*!< bit: 1 Enable */
287 uint32_t HYST:1; /*!< bit: 2 Hysteresis Enable */
288 uint32_t ACTION:2; /*!< bit: 3.. 4 Action when Threshold Crossed */
289 uint32_t STDBYCFG:1; /*!< bit: 5 Configuration in Standby mode */
290 uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */
291 uint32_t :1; /*!< bit: 7 Reserved */
292 uint32_t ACTCFG:1; /*!< bit: 8 Configuration in Active mode */
293 uint32_t :3; /*!< bit: 9..11 Reserved */
294 uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */
295 uint32_t LEVEL:6; /*!< bit: 16..21 Threshold Level */
296 uint32_t :10; /*!< bit: 22..31 Reserved */
297 } bit; /*!< Structure used for bit access */
298 uint32_t reg; /*!< Type used for register access */
299} SUPC_BOD12_Type;
300#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
301
302#define SUPC_BOD12_OFFSET 0x14 /**< \brief (SUPC_BOD12 offset) BOD12 Control */
303#define SUPC_BOD12_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_BOD12 reset_value) BOD12 Control */
304
305#define SUPC_BOD12_ENABLE_Pos 1 /**< \brief (SUPC_BOD12) Enable */
306#define SUPC_BOD12_ENABLE (_U_(0x1) << SUPC_BOD12_ENABLE_Pos)
307#define SUPC_BOD12_HYST_Pos 2 /**< \brief (SUPC_BOD12) Hysteresis Enable */
308#define SUPC_BOD12_HYST (_U_(0x1) << SUPC_BOD12_HYST_Pos)
309#define SUPC_BOD12_ACTION_Pos 3 /**< \brief (SUPC_BOD12) Action when Threshold Crossed */
310#define SUPC_BOD12_ACTION_Msk (_U_(0x3) << SUPC_BOD12_ACTION_Pos)
311#define SUPC_BOD12_ACTION(value) (SUPC_BOD12_ACTION_Msk & ((value) << SUPC_BOD12_ACTION_Pos))
312#define SUPC_BOD12_ACTION_NONE_Val _U_(0x0) /**< \brief (SUPC_BOD12) No action */
313#define SUPC_BOD12_ACTION_RESET_Val _U_(0x1) /**< \brief (SUPC_BOD12) The BOD12 generates a reset */
314#define SUPC_BOD12_ACTION_INT_Val _U_(0x2) /**< \brief (SUPC_BOD12) The BOD12 generates an interrupt */
315#define SUPC_BOD12_ACTION_NONE (SUPC_BOD12_ACTION_NONE_Val << SUPC_BOD12_ACTION_Pos)
316#define SUPC_BOD12_ACTION_RESET (SUPC_BOD12_ACTION_RESET_Val << SUPC_BOD12_ACTION_Pos)
317#define SUPC_BOD12_ACTION_INT (SUPC_BOD12_ACTION_INT_Val << SUPC_BOD12_ACTION_Pos)
318#define SUPC_BOD12_STDBYCFG_Pos 5 /**< \brief (SUPC_BOD12) Configuration in Standby mode */
319#define SUPC_BOD12_STDBYCFG (_U_(0x1) << SUPC_BOD12_STDBYCFG_Pos)
320#define SUPC_BOD12_RUNSTDBY_Pos 6 /**< \brief (SUPC_BOD12) Run during Standby */
321#define SUPC_BOD12_RUNSTDBY (_U_(0x1) << SUPC_BOD12_RUNSTDBY_Pos)
322#define SUPC_BOD12_ACTCFG_Pos 8 /**< \brief (SUPC_BOD12) Configuration in Active mode */
323#define SUPC_BOD12_ACTCFG (_U_(0x1) << SUPC_BOD12_ACTCFG_Pos)
324#define SUPC_BOD12_PSEL_Pos 12 /**< \brief (SUPC_BOD12) Prescaler Select */
325#define SUPC_BOD12_PSEL_Msk (_U_(0xF) << SUPC_BOD12_PSEL_Pos)
326#define SUPC_BOD12_PSEL(value) (SUPC_BOD12_PSEL_Msk & ((value) << SUPC_BOD12_PSEL_Pos))
327#define SUPC_BOD12_PSEL_DIV2_Val _U_(0x0) /**< \brief (SUPC_BOD12) Divide clock by 2 */
328#define SUPC_BOD12_PSEL_DIV4_Val _U_(0x1) /**< \brief (SUPC_BOD12) Divide clock by 4 */
329#define SUPC_BOD12_PSEL_DIV8_Val _U_(0x2) /**< \brief (SUPC_BOD12) Divide clock by 8 */
330#define SUPC_BOD12_PSEL_DIV16_Val _U_(0x3) /**< \brief (SUPC_BOD12) Divide clock by 16 */
331#define SUPC_BOD12_PSEL_DIV32_Val _U_(0x4) /**< \brief (SUPC_BOD12) Divide clock by 32 */
332#define SUPC_BOD12_PSEL_DIV64_Val _U_(0x5) /**< \brief (SUPC_BOD12) Divide clock by 64 */
333#define SUPC_BOD12_PSEL_DIV128_Val _U_(0x6) /**< \brief (SUPC_BOD12) Divide clock by 128 */
334#define SUPC_BOD12_PSEL_DIV256_Val _U_(0x7) /**< \brief (SUPC_BOD12) Divide clock by 256 */
335#define SUPC_BOD12_PSEL_DIV512_Val _U_(0x8) /**< \brief (SUPC_BOD12) Divide clock by 512 */
336#define SUPC_BOD12_PSEL_DIV1024_Val _U_(0x9) /**< \brief (SUPC_BOD12) Divide clock by 1024 */
337#define SUPC_BOD12_PSEL_DIV2048_Val _U_(0xA) /**< \brief (SUPC_BOD12) Divide clock by 2048 */
338#define SUPC_BOD12_PSEL_DIV4096_Val _U_(0xB) /**< \brief (SUPC_BOD12) Divide clock by 4096 */
339#define SUPC_BOD12_PSEL_DIV8192_Val _U_(0xC) /**< \brief (SUPC_BOD12) Divide clock by 8192 */
340#define SUPC_BOD12_PSEL_DIV16384_Val _U_(0xD) /**< \brief (SUPC_BOD12) Divide clock by 16384 */
341#define SUPC_BOD12_PSEL_DIV32768_Val _U_(0xE) /**< \brief (SUPC_BOD12) Divide clock by 32768 */
342#define SUPC_BOD12_PSEL_DIV65536_Val _U_(0xF) /**< \brief (SUPC_BOD12) Divide clock by 65536 */
343#define SUPC_BOD12_PSEL_DIV2 (SUPC_BOD12_PSEL_DIV2_Val << SUPC_BOD12_PSEL_Pos)
344#define SUPC_BOD12_PSEL_DIV4 (SUPC_BOD12_PSEL_DIV4_Val << SUPC_BOD12_PSEL_Pos)
345#define SUPC_BOD12_PSEL_DIV8 (SUPC_BOD12_PSEL_DIV8_Val << SUPC_BOD12_PSEL_Pos)
346#define SUPC_BOD12_PSEL_DIV16 (SUPC_BOD12_PSEL_DIV16_Val << SUPC_BOD12_PSEL_Pos)
347#define SUPC_BOD12_PSEL_DIV32 (SUPC_BOD12_PSEL_DIV32_Val << SUPC_BOD12_PSEL_Pos)
348#define SUPC_BOD12_PSEL_DIV64 (SUPC_BOD12_PSEL_DIV64_Val << SUPC_BOD12_PSEL_Pos)
349#define SUPC_BOD12_PSEL_DIV128 (SUPC_BOD12_PSEL_DIV128_Val << SUPC_BOD12_PSEL_Pos)
350#define SUPC_BOD12_PSEL_DIV256 (SUPC_BOD12_PSEL_DIV256_Val << SUPC_BOD12_PSEL_Pos)
351#define SUPC_BOD12_PSEL_DIV512 (SUPC_BOD12_PSEL_DIV512_Val << SUPC_BOD12_PSEL_Pos)
352#define SUPC_BOD12_PSEL_DIV1024 (SUPC_BOD12_PSEL_DIV1024_Val << SUPC_BOD12_PSEL_Pos)
353#define SUPC_BOD12_PSEL_DIV2048 (SUPC_BOD12_PSEL_DIV2048_Val << SUPC_BOD12_PSEL_Pos)
354#define SUPC_BOD12_PSEL_DIV4096 (SUPC_BOD12_PSEL_DIV4096_Val << SUPC_BOD12_PSEL_Pos)
355#define SUPC_BOD12_PSEL_DIV8192 (SUPC_BOD12_PSEL_DIV8192_Val << SUPC_BOD12_PSEL_Pos)
356#define SUPC_BOD12_PSEL_DIV16384 (SUPC_BOD12_PSEL_DIV16384_Val << SUPC_BOD12_PSEL_Pos)
357#define SUPC_BOD12_PSEL_DIV32768 (SUPC_BOD12_PSEL_DIV32768_Val << SUPC_BOD12_PSEL_Pos)
358#define SUPC_BOD12_PSEL_DIV65536 (SUPC_BOD12_PSEL_DIV65536_Val << SUPC_BOD12_PSEL_Pos)
359#define SUPC_BOD12_LEVEL_Pos 16 /**< \brief (SUPC_BOD12) Threshold Level */
360#define SUPC_BOD12_LEVEL_Msk (_U_(0x3F) << SUPC_BOD12_LEVEL_Pos)
361#define SUPC_BOD12_LEVEL(value) (SUPC_BOD12_LEVEL_Msk & ((value) << SUPC_BOD12_LEVEL_Pos))
362#define SUPC_BOD12_MASK _U_(0x003FF17E) /**< \brief (SUPC_BOD12) MASK Register */
363
364/* -------- SUPC_VREG : (SUPC Offset: 0x18) (R/W 32) VREG Control -------- */
365#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
366typedef union {
367 struct {
368 uint32_t :1; /*!< bit: 0 Reserved */
369 uint32_t ENABLE:1; /*!< bit: 1 Enable */
370 uint32_t SEL:1; /*!< bit: 2 Voltage Regulator Selection */
371 uint32_t :4; /*!< bit: 3.. 6 Reserved */
372 uint32_t RUNBKUP:1; /*!< bit: 7 Run in Backup mode */
373 uint32_t :8; /*!< bit: 8..15 Reserved */
374 uint32_t VSEN:1; /*!< bit: 16 Voltage Scaling Enable */
375 uint32_t :7; /*!< bit: 17..23 Reserved */
376 uint32_t VSPER:3; /*!< bit: 24..26 Voltage Scaling Period */
377 uint32_t :5; /*!< bit: 27..31 Reserved */
378 } bit; /*!< Structure used for bit access */
379 uint32_t reg; /*!< Type used for register access */
380} SUPC_VREG_Type;
381#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
382
383#define SUPC_VREG_OFFSET 0x18 /**< \brief (SUPC_VREG offset) VREG Control */
384#define SUPC_VREG_RESETVALUE _U_(0x00000002) /**< \brief (SUPC_VREG reset_value) VREG Control */
385
386#define SUPC_VREG_ENABLE_Pos 1 /**< \brief (SUPC_VREG) Enable */
387#define SUPC_VREG_ENABLE (_U_(0x1) << SUPC_VREG_ENABLE_Pos)
388#define SUPC_VREG_SEL_Pos 2 /**< \brief (SUPC_VREG) Voltage Regulator Selection */
389#define SUPC_VREG_SEL (_U_(0x1) << SUPC_VREG_SEL_Pos)
390#define SUPC_VREG_SEL_LDO_Val _U_(0x0) /**< \brief (SUPC_VREG) LDO selection */
391#define SUPC_VREG_SEL_BUCK_Val _U_(0x1) /**< \brief (SUPC_VREG) Buck selection */
392#define SUPC_VREG_SEL_LDO (SUPC_VREG_SEL_LDO_Val << SUPC_VREG_SEL_Pos)
393#define SUPC_VREG_SEL_BUCK (SUPC_VREG_SEL_BUCK_Val << SUPC_VREG_SEL_Pos)
394#define SUPC_VREG_RUNBKUP_Pos 7 /**< \brief (SUPC_VREG) Run in Backup mode */
395#define SUPC_VREG_RUNBKUP (_U_(0x1) << SUPC_VREG_RUNBKUP_Pos)
396#define SUPC_VREG_VSEN_Pos 16 /**< \brief (SUPC_VREG) Voltage Scaling Enable */
397#define SUPC_VREG_VSEN (_U_(0x1) << SUPC_VREG_VSEN_Pos)
398#define SUPC_VREG_VSPER_Pos 24 /**< \brief (SUPC_VREG) Voltage Scaling Period */
399#define SUPC_VREG_VSPER_Msk (_U_(0x7) << SUPC_VREG_VSPER_Pos)
400#define SUPC_VREG_VSPER(value) (SUPC_VREG_VSPER_Msk & ((value) << SUPC_VREG_VSPER_Pos))
401#define SUPC_VREG_MASK _U_(0x07010086) /**< \brief (SUPC_VREG) MASK Register */
402
403/* -------- SUPC_VREF : (SUPC Offset: 0x1C) (R/W 32) VREF Control -------- */
404#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
405typedef union {
406 struct {
407 uint32_t :1; /*!< bit: 0 Reserved */
408 uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Output Enable */
409 uint32_t VREFOE:1; /*!< bit: 2 Voltage Reference Output Enable */
410 uint32_t TSSEL:1; /*!< bit: 3 Temperature Sensor Selection */
411 uint32_t :2; /*!< bit: 4.. 5 Reserved */
412 uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */
413 uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Contrl */
414 uint32_t :8; /*!< bit: 8..15 Reserved */
415 uint32_t SEL:4; /*!< bit: 16..19 Voltage Reference Selection */
416 uint32_t :12; /*!< bit: 20..31 Reserved */
417 } bit; /*!< Structure used for bit access */
418 uint32_t reg; /*!< Type used for register access */
419} SUPC_VREF_Type;
420#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
421
422#define SUPC_VREF_OFFSET 0x1C /**< \brief (SUPC_VREF offset) VREF Control */
423#define SUPC_VREF_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_VREF reset_value) VREF Control */
424
425#define SUPC_VREF_TSEN_Pos 1 /**< \brief (SUPC_VREF) Temperature Sensor Output Enable */
426#define SUPC_VREF_TSEN (_U_(0x1) << SUPC_VREF_TSEN_Pos)
427#define SUPC_VREF_VREFOE_Pos 2 /**< \brief (SUPC_VREF) Voltage Reference Output Enable */
428#define SUPC_VREF_VREFOE (_U_(0x1) << SUPC_VREF_VREFOE_Pos)
429#define SUPC_VREF_TSSEL_Pos 3 /**< \brief (SUPC_VREF) Temperature Sensor Selection */
430#define SUPC_VREF_TSSEL (_U_(0x1) << SUPC_VREF_TSSEL_Pos)
431#define SUPC_VREF_RUNSTDBY_Pos 6 /**< \brief (SUPC_VREF) Run during Standby */
432#define SUPC_VREF_RUNSTDBY (_U_(0x1) << SUPC_VREF_RUNSTDBY_Pos)
433#define SUPC_VREF_ONDEMAND_Pos 7 /**< \brief (SUPC_VREF) On Demand Contrl */
434#define SUPC_VREF_ONDEMAND (_U_(0x1) << SUPC_VREF_ONDEMAND_Pos)
435#define SUPC_VREF_SEL_Pos 16 /**< \brief (SUPC_VREF) Voltage Reference Selection */
436#define SUPC_VREF_SEL_Msk (_U_(0xF) << SUPC_VREF_SEL_Pos)
437#define SUPC_VREF_SEL(value) (SUPC_VREF_SEL_Msk & ((value) << SUPC_VREF_SEL_Pos))
438#define SUPC_VREF_SEL_1V0_Val _U_(0x0) /**< \brief (SUPC_VREF) 1.0V voltage reference typical value */
439#define SUPC_VREF_SEL_1V1_Val _U_(0x1) /**< \brief (SUPC_VREF) 1.1V voltage reference typical value */
440#define SUPC_VREF_SEL_1V2_Val _U_(0x2) /**< \brief (SUPC_VREF) 1.2V voltage reference typical value */
441#define SUPC_VREF_SEL_1V25_Val _U_(0x3) /**< \brief (SUPC_VREF) 1.25V voltage reference typical value */
442#define SUPC_VREF_SEL_2V0_Val _U_(0x4) /**< \brief (SUPC_VREF) 2.0V voltage reference typical value */
443#define SUPC_VREF_SEL_2V2_Val _U_(0x5) /**< \brief (SUPC_VREF) 2.2V voltage reference typical value */
444#define SUPC_VREF_SEL_2V4_Val _U_(0x6) /**< \brief (SUPC_VREF) 2.4V voltage reference typical value */
445#define SUPC_VREF_SEL_2V5_Val _U_(0x7) /**< \brief (SUPC_VREF) 2.5V voltage reference typical value */
446#define SUPC_VREF_SEL_1V0 (SUPC_VREF_SEL_1V0_Val << SUPC_VREF_SEL_Pos)
447#define SUPC_VREF_SEL_1V1 (SUPC_VREF_SEL_1V1_Val << SUPC_VREF_SEL_Pos)
448#define SUPC_VREF_SEL_1V2 (SUPC_VREF_SEL_1V2_Val << SUPC_VREF_SEL_Pos)
449#define SUPC_VREF_SEL_1V25 (SUPC_VREF_SEL_1V25_Val << SUPC_VREF_SEL_Pos)
450#define SUPC_VREF_SEL_2V0 (SUPC_VREF_SEL_2V0_Val << SUPC_VREF_SEL_Pos)
451#define SUPC_VREF_SEL_2V2 (SUPC_VREF_SEL_2V2_Val << SUPC_VREF_SEL_Pos)
452#define SUPC_VREF_SEL_2V4 (SUPC_VREF_SEL_2V4_Val << SUPC_VREF_SEL_Pos)
453#define SUPC_VREF_SEL_2V5 (SUPC_VREF_SEL_2V5_Val << SUPC_VREF_SEL_Pos)
454#define SUPC_VREF_MASK _U_(0x000F00CE) /**< \brief (SUPC_VREF) MASK Register */
455
456/* -------- SUPC_BBPS : (SUPC Offset: 0x20) (R/W 32) Battery Backup Power Switch -------- */
457#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
458typedef union {
459 struct {
460 uint32_t CONF:1; /*!< bit: 0 Battery Backup Configuration */
461 uint32_t :1; /*!< bit: 1 Reserved */
462 uint32_t WAKEEN:1; /*!< bit: 2 Wake Enable */
463 uint32_t :29; /*!< bit: 3..31 Reserved */
464 } bit; /*!< Structure used for bit access */
465 uint32_t reg; /*!< Type used for register access */
466} SUPC_BBPS_Type;
467#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
468
469#define SUPC_BBPS_OFFSET 0x20 /**< \brief (SUPC_BBPS offset) Battery Backup Power Switch */
470#define SUPC_BBPS_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_BBPS reset_value) Battery Backup Power Switch */
471
472#define SUPC_BBPS_CONF_Pos 0 /**< \brief (SUPC_BBPS) Battery Backup Configuration */
473#define SUPC_BBPS_CONF (_U_(0x1) << SUPC_BBPS_CONF_Pos)
474#define SUPC_BBPS_CONF_BOD33_Val _U_(0x0) /**< \brief (SUPC_BBPS) The power switch is handled by the BOD33 */
475#define SUPC_BBPS_CONF_FORCED_Val _U_(0x1) /**< \brief (SUPC_BBPS) In Backup Domain, the backup domain is always supplied by battery backup power */
476#define SUPC_BBPS_CONF_BOD33 (SUPC_BBPS_CONF_BOD33_Val << SUPC_BBPS_CONF_Pos)
477#define SUPC_BBPS_CONF_FORCED (SUPC_BBPS_CONF_FORCED_Val << SUPC_BBPS_CONF_Pos)
478#define SUPC_BBPS_WAKEEN_Pos 2 /**< \brief (SUPC_BBPS) Wake Enable */
479#define SUPC_BBPS_WAKEEN (_U_(0x1) << SUPC_BBPS_WAKEEN_Pos)
480#define SUPC_BBPS_MASK _U_(0x00000005) /**< \brief (SUPC_BBPS) MASK Register */
481
482/* -------- SUPC_BKOUT : (SUPC Offset: 0x24) (R/W 32) Backup Output Control -------- */
483#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
484typedef union {
485 struct {
486 uint32_t EN:2; /*!< bit: 0.. 1 Enable Output */
487 uint32_t :6; /*!< bit: 2.. 7 Reserved */
488 uint32_t CLR:2; /*!< bit: 8.. 9 Clear Output */
489 uint32_t :6; /*!< bit: 10..15 Reserved */
490 uint32_t SET:2; /*!< bit: 16..17 Set Output */
491 uint32_t :6; /*!< bit: 18..23 Reserved */
492 uint32_t RTCTGL:2; /*!< bit: 24..25 RTC Toggle Output */
493 uint32_t :6; /*!< bit: 26..31 Reserved */
494 } bit; /*!< Structure used for bit access */
495 uint32_t reg; /*!< Type used for register access */
496} SUPC_BKOUT_Type;
497#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
498
499#define SUPC_BKOUT_OFFSET 0x24 /**< \brief (SUPC_BKOUT offset) Backup Output Control */
500#define SUPC_BKOUT_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_BKOUT reset_value) Backup Output Control */
501
502#define SUPC_BKOUT_EN_Pos 0 /**< \brief (SUPC_BKOUT) Enable Output */
503#define SUPC_BKOUT_EN_Msk (_U_(0x3) << SUPC_BKOUT_EN_Pos)
504#define SUPC_BKOUT_EN(value) (SUPC_BKOUT_EN_Msk & ((value) << SUPC_BKOUT_EN_Pos))
505#define SUPC_BKOUT_CLR_Pos 8 /**< \brief (SUPC_BKOUT) Clear Output */
506#define SUPC_BKOUT_CLR_Msk (_U_(0x3) << SUPC_BKOUT_CLR_Pos)
507#define SUPC_BKOUT_CLR(value) (SUPC_BKOUT_CLR_Msk & ((value) << SUPC_BKOUT_CLR_Pos))
508#define SUPC_BKOUT_SET_Pos 16 /**< \brief (SUPC_BKOUT) Set Output */
509#define SUPC_BKOUT_SET_Msk (_U_(0x3) << SUPC_BKOUT_SET_Pos)
510#define SUPC_BKOUT_SET(value) (SUPC_BKOUT_SET_Msk & ((value) << SUPC_BKOUT_SET_Pos))
511#define SUPC_BKOUT_RTCTGL_Pos 24 /**< \brief (SUPC_BKOUT) RTC Toggle Output */
512#define SUPC_BKOUT_RTCTGL_Msk (_U_(0x3) << SUPC_BKOUT_RTCTGL_Pos)
513#define SUPC_BKOUT_RTCTGL(value) (SUPC_BKOUT_RTCTGL_Msk & ((value) << SUPC_BKOUT_RTCTGL_Pos))
514#define SUPC_BKOUT_MASK _U_(0x03030303) /**< \brief (SUPC_BKOUT) MASK Register */
515
516/* -------- SUPC_BKIN : (SUPC Offset: 0x28) (R/ 32) Backup Input Control -------- */
517#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
518typedef union {
519 struct {
520 uint32_t BKIN:8; /*!< bit: 0.. 7 Backup Input Value */
521 uint32_t :24; /*!< bit: 8..31 Reserved */
522 } bit; /*!< Structure used for bit access */
523 uint32_t reg; /*!< Type used for register access */
524} SUPC_BKIN_Type;
525#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
526
527#define SUPC_BKIN_OFFSET 0x28 /**< \brief (SUPC_BKIN offset) Backup Input Control */
528#define SUPC_BKIN_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_BKIN reset_value) Backup Input Control */
529
530#define SUPC_BKIN_BKIN_Pos 0 /**< \brief (SUPC_BKIN) Backup Input Value */
531#define SUPC_BKIN_BKIN_Msk (_U_(0xFF) << SUPC_BKIN_BKIN_Pos)
532#define SUPC_BKIN_BKIN(value) (SUPC_BKIN_BKIN_Msk & ((value) << SUPC_BKIN_BKIN_Pos))
533#define SUPC_BKIN_MASK _U_(0x000000FF) /**< \brief (SUPC_BKIN) MASK Register */
534
535/** \brief SUPC hardware registers */
536#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
537typedef struct {
538 __IO SUPC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
539 __IO SUPC_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
540 __IO SUPC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
541 __I SUPC_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
542 __IO SUPC_BOD33_Type BOD33; /**< \brief Offset: 0x10 (R/W 32) BOD33 Control */
543 __IO SUPC_BOD12_Type BOD12; /**< \brief Offset: 0x14 (R/W 32) BOD12 Control */
544 __IO SUPC_VREG_Type VREG; /**< \brief Offset: 0x18 (R/W 32) VREG Control */
545 __IO SUPC_VREF_Type VREF; /**< \brief Offset: 0x1C (R/W 32) VREF Control */
546 __IO SUPC_BBPS_Type BBPS; /**< \brief Offset: 0x20 (R/W 32) Battery Backup Power Switch */
547 __IO SUPC_BKOUT_Type BKOUT; /**< \brief Offset: 0x24 (R/W 32) Backup Output Control */
548 __I SUPC_BKIN_Type BKIN; /**< \brief Offset: 0x28 (R/ 32) Backup Input Control */
549} Supc;
550#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
551
552/*@}*/
553
554#endif /* _SAME54_SUPC_COMPONENT_ */