Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief Component description for RSTC |
| 5 | * |
| 6 | * Copyright (c) 2018 Microchip Technology Inc. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * SPDX-License-Identifier: Apache-2.0 |
| 13 | * |
| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may |
| 15 | * not use this file except in compliance with the License. |
| 16 | * You may obtain a copy of the Licence at |
| 17 | * |
| 18 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 19 | * |
| 20 | * Unless required by applicable law or agreed to in writing, software |
| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 23 | * See the License for the specific language governing permissions and |
| 24 | * limitations under the License. |
| 25 | * |
| 26 | * \asf_license_stop |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #ifndef _SAME54_RSTC_COMPONENT_ |
| 31 | #define _SAME54_RSTC_COMPONENT_ |
| 32 | |
| 33 | /* ========================================================================== */ |
| 34 | /** SOFTWARE API DEFINITION FOR RSTC */ |
| 35 | /* ========================================================================== */ |
| 36 | /** \addtogroup SAME54_RSTC Reset Controller */ |
| 37 | /*@{*/ |
| 38 | |
| 39 | #define RSTC_U2239 |
| 40 | #define REV_RSTC 0x400 |
| 41 | |
| 42 | /* -------- RSTC_RCAUSE : (RSTC Offset: 0x00) (R/ 8) Reset Cause -------- */ |
| 43 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 44 | typedef union { |
| 45 | struct { |
| 46 | uint8_t POR:1; /*!< bit: 0 Power On Reset */ |
| 47 | uint8_t BODCORE:1; /*!< bit: 1 Brown Out CORE Detector Reset */ |
| 48 | uint8_t BODVDD:1; /*!< bit: 2 Brown Out VDD Detector Reset */ |
| 49 | uint8_t NVM:1; /*!< bit: 3 NVM Reset */ |
| 50 | uint8_t EXT:1; /*!< bit: 4 External Reset */ |
| 51 | uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */ |
| 52 | uint8_t SYST:1; /*!< bit: 6 System Reset Request */ |
| 53 | uint8_t BACKUP:1; /*!< bit: 7 Backup Reset */ |
| 54 | } bit; /*!< Structure used for bit access */ |
| 55 | uint8_t reg; /*!< Type used for register access */ |
| 56 | } RSTC_RCAUSE_Type; |
| 57 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 58 | |
| 59 | #define RSTC_RCAUSE_OFFSET 0x00 /**< \brief (RSTC_RCAUSE offset) Reset Cause */ |
| 60 | |
| 61 | #define RSTC_RCAUSE_POR_Pos 0 /**< \brief (RSTC_RCAUSE) Power On Reset */ |
| 62 | #define RSTC_RCAUSE_POR (_U_(0x1) << RSTC_RCAUSE_POR_Pos) |
| 63 | #define RSTC_RCAUSE_BODCORE_Pos 1 /**< \brief (RSTC_RCAUSE) Brown Out CORE Detector Reset */ |
| 64 | #define RSTC_RCAUSE_BODCORE (_U_(0x1) << RSTC_RCAUSE_BODCORE_Pos) |
| 65 | #define RSTC_RCAUSE_BODVDD_Pos 2 /**< \brief (RSTC_RCAUSE) Brown Out VDD Detector Reset */ |
| 66 | #define RSTC_RCAUSE_BODVDD (_U_(0x1) << RSTC_RCAUSE_BODVDD_Pos) |
| 67 | #define RSTC_RCAUSE_NVM_Pos 3 /**< \brief (RSTC_RCAUSE) NVM Reset */ |
| 68 | #define RSTC_RCAUSE_NVM (_U_(0x1) << RSTC_RCAUSE_NVM_Pos) |
| 69 | #define RSTC_RCAUSE_EXT_Pos 4 /**< \brief (RSTC_RCAUSE) External Reset */ |
| 70 | #define RSTC_RCAUSE_EXT (_U_(0x1) << RSTC_RCAUSE_EXT_Pos) |
| 71 | #define RSTC_RCAUSE_WDT_Pos 5 /**< \brief (RSTC_RCAUSE) Watchdog Reset */ |
| 72 | #define RSTC_RCAUSE_WDT (_U_(0x1) << RSTC_RCAUSE_WDT_Pos) |
| 73 | #define RSTC_RCAUSE_SYST_Pos 6 /**< \brief (RSTC_RCAUSE) System Reset Request */ |
| 74 | #define RSTC_RCAUSE_SYST (_U_(0x1) << RSTC_RCAUSE_SYST_Pos) |
| 75 | #define RSTC_RCAUSE_BACKUP_Pos 7 /**< \brief (RSTC_RCAUSE) Backup Reset */ |
| 76 | #define RSTC_RCAUSE_BACKUP (_U_(0x1) << RSTC_RCAUSE_BACKUP_Pos) |
| 77 | #define RSTC_RCAUSE_MASK _U_(0xFF) /**< \brief (RSTC_RCAUSE) MASK Register */ |
| 78 | |
| 79 | /* -------- RSTC_BKUPEXIT : (RSTC Offset: 0x02) (R/ 8) Backup Exit Source -------- */ |
| 80 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 81 | typedef union { |
| 82 | struct { |
| 83 | uint8_t :1; /*!< bit: 0 Reserved */ |
| 84 | uint8_t RTC:1; /*!< bit: 1 Real Timer Counter Interrupt */ |
| 85 | uint8_t BBPS:1; /*!< bit: 2 Battery Backup Power Switch */ |
| 86 | uint8_t :4; /*!< bit: 3.. 6 Reserved */ |
| 87 | uint8_t HIB:1; /*!< bit: 7 Hibernate */ |
| 88 | } bit; /*!< Structure used for bit access */ |
| 89 | uint8_t reg; /*!< Type used for register access */ |
| 90 | } RSTC_BKUPEXIT_Type; |
| 91 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 92 | |
| 93 | #define RSTC_BKUPEXIT_OFFSET 0x02 /**< \brief (RSTC_BKUPEXIT offset) Backup Exit Source */ |
| 94 | #define RSTC_BKUPEXIT_RESETVALUE _U_(0x00) /**< \brief (RSTC_BKUPEXIT reset_value) Backup Exit Source */ |
| 95 | |
| 96 | #define RSTC_BKUPEXIT_RTC_Pos 1 /**< \brief (RSTC_BKUPEXIT) Real Timer Counter Interrupt */ |
| 97 | #define RSTC_BKUPEXIT_RTC (_U_(0x1) << RSTC_BKUPEXIT_RTC_Pos) |
| 98 | #define RSTC_BKUPEXIT_BBPS_Pos 2 /**< \brief (RSTC_BKUPEXIT) Battery Backup Power Switch */ |
| 99 | #define RSTC_BKUPEXIT_BBPS (_U_(0x1) << RSTC_BKUPEXIT_BBPS_Pos) |
| 100 | #define RSTC_BKUPEXIT_HIB_Pos 7 /**< \brief (RSTC_BKUPEXIT) Hibernate */ |
| 101 | #define RSTC_BKUPEXIT_HIB (_U_(0x1) << RSTC_BKUPEXIT_HIB_Pos) |
| 102 | #define RSTC_BKUPEXIT_MASK _U_(0x86) /**< \brief (RSTC_BKUPEXIT) MASK Register */ |
| 103 | |
| 104 | /** \brief RSTC hardware registers */ |
| 105 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 106 | typedef struct { |
| 107 | __I RSTC_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x00 (R/ 8) Reset Cause */ |
| 108 | RoReg8 Reserved1[0x1]; |
| 109 | __I RSTC_BKUPEXIT_Type BKUPEXIT; /**< \brief Offset: 0x02 (R/ 8) Backup Exit Source */ |
| 110 | } Rstc; |
| 111 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 112 | |
| 113 | /*@}*/ |
| 114 | |
| 115 | #endif /* _SAME54_RSTC_COMPONENT_ */ |