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gerrit.osmocom.org / osmo-ccid-firmware / a6c44f141155342044017911c32be4bfc0ae2be2 / . / sysmoOCTSIM / include / component / aes.h
blob: 64c7121a180b8c0bd1d6eb63d2051199cf42bb4c [file] [log] [blame]
Kévin Redon69b92d92019-01-24 16:39:20 +0100[diff] [blame]1/**
2 * \file
3 *
4 * \brief Component description for AES
5 *
6 * Copyright (c) 2018 Microchip Technology Inc.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * SPDX-License-Identifier: Apache-2.0
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License"); you may
15 * not use this file except in compliance with the License.
16 * You may obtain a copy of the Licence at
17 *
18 * http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *
26 * \asf_license_stop
27 *
28 */
29
30#ifndef _SAME54_AES_COMPONENT_
31#define _SAME54_AES_COMPONENT_
32
33/* ========================================================================== */
34/** SOFTWARE API DEFINITION FOR AES */
35/* ========================================================================== */
36/** \addtogroup SAME54_AES Advanced Encryption Standard */
37/*@{*/
38
39#define AES_U2238
40#define REV_AES 0x220
41
42/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */
43#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
44typedef union {
45 struct {
46 uint32_t SWRST:1; /*!< bit: 0 Software Reset */
47 uint32_t ENABLE:1; /*!< bit: 1 Enable */
48 uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */
49 uint32_t CFBS:3; /*!< bit: 5.. 7 Cipher Feedback Block Size */
50 uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Encryption Key Size */
51 uint32_t CIPHER:1; /*!< bit: 10 Cipher Mode */
52 uint32_t STARTMODE:1; /*!< bit: 11 Start Mode Select */
53 uint32_t LOD:1; /*!< bit: 12 Last Output Data Mode */
54 uint32_t KEYGEN:1; /*!< bit: 13 Last Key Generation */
55 uint32_t XORKEY:1; /*!< bit: 14 XOR Key Operation */
56 uint32_t :1; /*!< bit: 15 Reserved */
57 uint32_t CTYPE:4; /*!< bit: 16..19 Counter Measure Type */
58 uint32_t :12; /*!< bit: 20..31 Reserved */
59 } bit; /*!< Structure used for bit access */
60 uint32_t reg; /*!< Type used for register access */
61} AES_CTRLA_Type;
62#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
63
64#define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */
65#define AES_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */
66
67#define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */
68#define AES_CTRLA_SWRST (_U_(0x1) << AES_CTRLA_SWRST_Pos)
69#define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */
70#define AES_CTRLA_ENABLE (_U_(0x1) << AES_CTRLA_ENABLE_Pos)
71#define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */
72#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos)
73#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos))
74#define AES_CTRLA_AESMODE_ECB_Val _U_(0x0) /**< \brief (AES_CTRLA) Electronic code book mode */
75#define AES_CTRLA_AESMODE_CBC_Val _U_(0x1) /**< \brief (AES_CTRLA) Cipher block chaining mode */
76#define AES_CTRLA_AESMODE_OFB_Val _U_(0x2) /**< \brief (AES_CTRLA) Output feedback mode */
77#define AES_CTRLA_AESMODE_CFB_Val _U_(0x3) /**< \brief (AES_CTRLA) Cipher feedback mode */
78#define AES_CTRLA_AESMODE_COUNTER_Val _U_(0x4) /**< \brief (AES_CTRLA) Counter mode */
79#define AES_CTRLA_AESMODE_CCM_Val _U_(0x5) /**< \brief (AES_CTRLA) CCM mode */
80#define AES_CTRLA_AESMODE_GCM_Val _U_(0x6) /**< \brief (AES_CTRLA) Galois counter mode */
81#define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos)
82#define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos)
83#define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos)
84#define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos)
85#define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos)
86#define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos)
87#define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos)
88#define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) Cipher Feedback Block Size */
89#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos)
90#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos))
91#define AES_CTRLA_CFBS_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
92#define AES_CTRLA_CFBS_64BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
93#define AES_CTRLA_CFBS_32BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
94#define AES_CTRLA_CFBS_16BIT_Val _U_(0x3) /**< \brief (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
95#define AES_CTRLA_CFBS_8BIT_Val _U_(0x4) /**< \brief (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
96#define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos)
97#define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos)
98#define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos)
99#define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos)
100#define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos)
101#define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Encryption Key Size */
102#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos)
103#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos))
104#define AES_CTRLA_KEYSIZE_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Key for Encryption / Decryption */
105#define AES_CTRLA_KEYSIZE_192BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 192-bit Key for Encryption / Decryption */
106#define AES_CTRLA_KEYSIZE_256BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 256-bit Key for Encryption / Decryption */
107#define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos)
108#define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos)
109#define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos)
110#define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher Mode */
111#define AES_CTRLA_CIPHER (_U_(0x1) << AES_CTRLA_CIPHER_Pos)
112#define AES_CTRLA_CIPHER_DEC_Val _U_(0x0) /**< \brief (AES_CTRLA) Decryption */
113#define AES_CTRLA_CIPHER_ENC_Val _U_(0x1) /**< \brief (AES_CTRLA) Encryption */
114#define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos)
115#define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos)
116#define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start Mode Select */
117#define AES_CTRLA_STARTMODE (_U_(0x1) << AES_CTRLA_STARTMODE_Pos)
118#define AES_CTRLA_STARTMODE_MANUAL_Val _U_(0x0) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Manual mode */
119#define AES_CTRLA_STARTMODE_AUTO_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Auto mode */
120#define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos)
121#define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos)
122#define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) Last Output Data Mode */
123#define AES_CTRLA_LOD (_U_(0x1) << AES_CTRLA_LOD_Pos)
124#define AES_CTRLA_LOD_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
125#define AES_CTRLA_LOD_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start encryption in Last Output Data mode */
126#define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos)
127#define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos)
128#define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last Key Generation */
129#define AES_CTRLA_KEYGEN (_U_(0x1) << AES_CTRLA_KEYGEN_Pos)
130#define AES_CTRLA_KEYGEN_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
131#define AES_CTRLA_KEYGEN_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Computation of the last NK words of the expanded key */
132#define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos)
133#define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos)
134#define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) XOR Key Operation */
135#define AES_CTRLA_XORKEY (_U_(0x1) << AES_CTRLA_XORKEY_Pos)
136#define AES_CTRLA_XORKEY_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
137#define AES_CTRLA_XORKEY_XOR_Val _U_(0x1) /**< \brief (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */
138#define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos)
139#define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos)
140#define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter Measure Type */
141#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos)
142#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos))
143#define AES_CTRLA_MASK _U_(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */
144
145/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */
146#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
147typedef union {
148 struct {
149 uint8_t START:1; /*!< bit: 0 Start Encryption/Decryption */
150 uint8_t NEWMSG:1; /*!< bit: 1 New message */
151 uint8_t EOM:1; /*!< bit: 2 End of message */
152 uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */
153 uint8_t :4; /*!< bit: 4.. 7 Reserved */
154 } bit; /*!< Structure used for bit access */
155 uint8_t reg; /*!< Type used for register access */
156} AES_CTRLB_Type;
157#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
158
159#define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */
160#define AES_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AES_CTRLB reset_value) Control B */
161
162#define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Start Encryption/Decryption */
163#define AES_CTRLB_START (_U_(0x1) << AES_CTRLB_START_Pos)
164#define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */
165#define AES_CTRLB_NEWMSG (_U_(0x1) << AES_CTRLB_NEWMSG_Pos)
166#define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */
167#define AES_CTRLB_EOM (_U_(0x1) << AES_CTRLB_EOM_Pos)
168#define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */
169#define AES_CTRLB_GFMUL (_U_(0x1) << AES_CTRLB_GFMUL_Pos)
170#define AES_CTRLB_MASK _U_(0x0F) /**< \brief (AES_CTRLB) MASK Register */
171
172/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */
173#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
174typedef union {
175 struct {
176 uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */
177 uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */
178 uint8_t :6; /*!< bit: 2.. 7 Reserved */
179 } bit; /*!< Structure used for bit access */
180 uint8_t reg; /*!< Type used for register access */
181} AES_INTENCLR_Type;
182#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
183
184#define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */
185#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */
186
187#define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete Interrupt Enable */
188#define AES_INTENCLR_ENCCMP (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos)
189#define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete Interrupt Enable */
190#define AES_INTENCLR_GFMCMP (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos)
191#define AES_INTENCLR_MASK _U_(0x03) /**< \brief (AES_INTENCLR) MASK Register */
192
193/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */
194#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
195typedef union {
196 struct {
197 uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */
198 uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */
199 uint8_t :6; /*!< bit: 2.. 7 Reserved */
200 } bit; /*!< Structure used for bit access */
201 uint8_t reg; /*!< Type used for register access */
202} AES_INTENSET_Type;
203#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
204
205#define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */
206#define AES_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */
207
208#define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete Interrupt Enable */
209#define AES_INTENSET_ENCCMP (_U_(0x1) << AES_INTENSET_ENCCMP_Pos)
210#define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete Interrupt Enable */
211#define AES_INTENSET_GFMCMP (_U_(0x1) << AES_INTENSET_GFMCMP_Pos)
212#define AES_INTENSET_MASK _U_(0x03) /**< \brief (AES_INTENSET) MASK Register */
213
214/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */
215#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
216typedef union { // __I to avoid read-modify-write on write-to-clear register
217 struct {
218 __I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */
219 __I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */
220 __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
221 } bit; /*!< Structure used for bit access */
222 uint8_t reg; /*!< Type used for register access */
223} AES_INTFLAG_Type;
224#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
225
226#define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */
227#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */
228
229#define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */
230#define AES_INTFLAG_ENCCMP (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos)
231#define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */
232#define AES_INTFLAG_GFMCMP (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos)
233#define AES_INTFLAG_MASK _U_(0x03) /**< \brief (AES_INTFLAG) MASK Register */
234
235/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */
236#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
237typedef union {
238 struct {
239 uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */
240 uint8_t :6; /*!< bit: 2.. 7 Reserved */
241 } bit; /*!< Structure used for bit access */
242 uint8_t reg; /*!< Type used for register access */
243} AES_DATABUFPTR_Type;
244#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
245
246#define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */
247#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */
248
249#define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */
250#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos)
251#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos))
252#define AES_DATABUFPTR_MASK _U_(0x03) /**< \brief (AES_DATABUFPTR) MASK Register */
253
254/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */
255#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
256typedef union {
257 struct {
258 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
259 uint8_t :7; /*!< bit: 1.. 7 Reserved */
260 } bit; /*!< Structure used for bit access */
261 uint8_t reg; /*!< Type used for register access */
262} AES_DBGCTRL_Type;
263#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
264
265#define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */
266#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AES_DBGCTRL reset_value) Debug control */
267
268#define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */
269#define AES_DBGCTRL_DBGRUN (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos)
270#define AES_DBGCTRL_MASK _U_(0x01) /**< \brief (AES_DBGCTRL) MASK Register */
271
272/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */
273#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
274typedef union {
275 uint32_t reg; /*!< Type used for register access */
276} AES_KEYWORD_Type;
277#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
278
279#define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */
280#define AES_KEYWORD_RESETVALUE _U_(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */
281#define AES_KEYWORD_MASK _U_(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */
282
283/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */
284#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
285typedef union {
286 uint32_t reg; /*!< Type used for register access */
287} AES_INDATA_Type;
288#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
289
290#define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */
291#define AES_INDATA_RESETVALUE _U_(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */
292#define AES_INDATA_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */
293
294/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */
295#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
296typedef union {
297 uint32_t reg; /*!< Type used for register access */
298} AES_INTVECTV_Type;
299#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
300
301#define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */
302#define AES_INTVECTV_RESETVALUE _U_(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */
303#define AES_INTVECTV_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */
304
305/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */
306#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
307typedef union {
308 uint32_t reg; /*!< Type used for register access */
309} AES_HASHKEY_Type;
310#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
311
312#define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */
313#define AES_HASHKEY_RESETVALUE _U_(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */
314#define AES_HASHKEY_MASK _U_(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */
315
316/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */
317#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
318typedef union {
319 uint32_t reg; /*!< Type used for register access */
320} AES_GHASH_Type;
321#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
322
323#define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */
324#define AES_GHASH_RESETVALUE _U_(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */
325#define AES_GHASH_MASK _U_(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */
326
327/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */
328#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
329typedef union {
330 uint32_t reg; /*!< Type used for register access */
331} AES_CIPLEN_Type;
332#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
333
334#define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */
335#define AES_CIPLEN_RESETVALUE _U_(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */
336#define AES_CIPLEN_MASK _U_(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */
337
338/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */
339#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
340typedef union {
341 uint32_t reg; /*!< Type used for register access */
342} AES_RANDSEED_Type;
343#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
344
345#define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */
346#define AES_RANDSEED_RESETVALUE _U_(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */
347#define AES_RANDSEED_MASK _U_(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */
348
349/** \brief AES hardware registers */
350#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
351typedef struct {
352 __IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
353 __IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */
354 __IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */
355 __IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */
356 __IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */
357 __IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */
358 __IO AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug control */
359 RoReg8 Reserved1[0x2];
360 __O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */
361 RoReg8 Reserved2[0xC];
362 __IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */
363 __O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */
364 RoReg8 Reserved3[0x10];
365 __IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */
366 __IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */
367 RoReg8 Reserved4[0x4];
368 __IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */
369 __IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */
370} Aes;
371#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
372
373/*@}*/
374
375#endif /* _SAME54_AES_COMPONENT_ */