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gerrit.osmocom.org / osmo-ccid-firmware / 9bb8bfedb3676228b7c3385844eb23b4f0582a46 / . / sysmoOCTSIM / include / component / tc.h
blob: 953416f917883bfaa26525bb85aac9d89ff066b9 [file] [log] [blame]
Kévin Redon69b92d92019-01-24 16:39:20 +0100[diff] [blame]1/**
2 * \file
3 *
4 * \brief Component description for TC
5 *
6 * Copyright (c) 2018 Microchip Technology Inc.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * SPDX-License-Identifier: Apache-2.0
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License"); you may
15 * not use this file except in compliance with the License.
16 * You may obtain a copy of the Licence at
17 *
18 * http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *
26 * \asf_license_stop
27 *
28 */
29
30#ifndef _SAME54_TC_COMPONENT_
31#define _SAME54_TC_COMPONENT_
32
33/* ========================================================================== */
34/** SOFTWARE API DEFINITION FOR TC */
35/* ========================================================================== */
36/** \addtogroup SAME54_TC Basic Timer Counter */
37/*@{*/
38
39#define TC_U2249
40#define REV_TC 0x300
41
42/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 32) Control A -------- */
43#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
44typedef union {
45 struct {
46 uint32_t SWRST:1; /*!< bit: 0 Software Reset */
47 uint32_t ENABLE:1; /*!< bit: 1 Enable */
48 uint32_t MODE:2; /*!< bit: 2.. 3 Timer Counter Mode */
49 uint32_t PRESCSYNC:2; /*!< bit: 4.. 5 Prescaler and Counter Synchronization */
50 uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */
51 uint32_t ONDEMAND:1; /*!< bit: 7 Clock On Demand */
52 uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
53 uint32_t ALOCK:1; /*!< bit: 11 Auto Lock */
54 uint32_t :4; /*!< bit: 12..15 Reserved */
55 uint32_t CAPTEN0:1; /*!< bit: 16 Capture Channel 0 Enable */
56 uint32_t CAPTEN1:1; /*!< bit: 17 Capture Channel 1 Enable */
57 uint32_t :2; /*!< bit: 18..19 Reserved */
58 uint32_t COPEN0:1; /*!< bit: 20 Capture On Pin 0 Enable */
59 uint32_t COPEN1:1; /*!< bit: 21 Capture On Pin 1 Enable */
60 uint32_t :2; /*!< bit: 22..23 Reserved */
61 uint32_t CAPTMODE0:2; /*!< bit: 24..25 Capture Mode Channel 0 */
62 uint32_t :1; /*!< bit: 26 Reserved */
63 uint32_t CAPTMODE1:2; /*!< bit: 27..28 Capture mode Channel 1 */
64 uint32_t :3; /*!< bit: 29..31 Reserved */
65 } bit; /*!< Structure used for bit access */
66 struct {
67 uint32_t :16; /*!< bit: 0..15 Reserved */
68 uint32_t CAPTEN:2; /*!< bit: 16..17 Capture Channel x Enable */
69 uint32_t :2; /*!< bit: 18..19 Reserved */
70 uint32_t COPEN:2; /*!< bit: 20..21 Capture On Pin x Enable */
71 uint32_t :10; /*!< bit: 22..31 Reserved */
72 } vec; /*!< Structure used for vec access */
73 uint32_t reg; /*!< Type used for register access */
74} TC_CTRLA_Type;
75#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
76
77#define TC_CTRLA_OFFSET 0x00 /**< \brief (TC_CTRLA offset) Control A */
78#define TC_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (TC_CTRLA reset_value) Control A */
79
80#define TC_CTRLA_SWRST_Pos 0 /**< \brief (TC_CTRLA) Software Reset */
81#define TC_CTRLA_SWRST (_U_(0x1) << TC_CTRLA_SWRST_Pos)
82#define TC_CTRLA_ENABLE_Pos 1 /**< \brief (TC_CTRLA) Enable */
83#define TC_CTRLA_ENABLE (_U_(0x1) << TC_CTRLA_ENABLE_Pos)
84#define TC_CTRLA_MODE_Pos 2 /**< \brief (TC_CTRLA) Timer Counter Mode */
85#define TC_CTRLA_MODE_Msk (_U_(0x3) << TC_CTRLA_MODE_Pos)
86#define TC_CTRLA_MODE(value) (TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos))
87#define TC_CTRLA_MODE_COUNT16_Val _U_(0x0) /**< \brief (TC_CTRLA) Counter in 16-bit mode */
88#define TC_CTRLA_MODE_COUNT8_Val _U_(0x1) /**< \brief (TC_CTRLA) Counter in 8-bit mode */
89#define TC_CTRLA_MODE_COUNT32_Val _U_(0x2) /**< \brief (TC_CTRLA) Counter in 32-bit mode */
90#define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos)
91#define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos)
92#define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos)
93#define TC_CTRLA_PRESCSYNC_Pos 4 /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */
94#define TC_CTRLA_PRESCSYNC_Msk (_U_(0x3) << TC_CTRLA_PRESCSYNC_Pos)
95#define TC_CTRLA_PRESCSYNC(value) (TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos))
96#define TC_CTRLA_PRESCSYNC_GCLK_Val _U_(0x0) /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */
97#define TC_CTRLA_PRESCSYNC_PRESC_Val _U_(0x1) /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */
98#define TC_CTRLA_PRESCSYNC_RESYNC_Val _U_(0x2) /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock and reset the prescaler counter */
99#define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos)
100#define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos)
101#define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos)
102#define TC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (TC_CTRLA) Run during Standby */
103#define TC_CTRLA_RUNSTDBY (_U_(0x1) << TC_CTRLA_RUNSTDBY_Pos)
104#define TC_CTRLA_ONDEMAND_Pos 7 /**< \brief (TC_CTRLA) Clock On Demand */
105#define TC_CTRLA_ONDEMAND (_U_(0x1) << TC_CTRLA_ONDEMAND_Pos)
106#define TC_CTRLA_PRESCALER_Pos 8 /**< \brief (TC_CTRLA) Prescaler */
107#define TC_CTRLA_PRESCALER_Msk (_U_(0x7) << TC_CTRLA_PRESCALER_Pos)
108#define TC_CTRLA_PRESCALER(value) (TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos))
109#define TC_CTRLA_PRESCALER_DIV1_Val _U_(0x0) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */
110#define TC_CTRLA_PRESCALER_DIV2_Val _U_(0x1) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */
111#define TC_CTRLA_PRESCALER_DIV4_Val _U_(0x2) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */
112#define TC_CTRLA_PRESCALER_DIV8_Val _U_(0x3) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/8 */
113#define TC_CTRLA_PRESCALER_DIV16_Val _U_(0x4) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/16 */
114#define TC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/64 */
115#define TC_CTRLA_PRESCALER_DIV256_Val _U_(0x6) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/256 */
116#define TC_CTRLA_PRESCALER_DIV1024_Val _U_(0x7) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/1024 */
117#define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos)
118#define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos)
119#define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos)
120#define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos)
121#define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos)
122#define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos)
123#define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos)
124#define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos)
125#define TC_CTRLA_ALOCK_Pos 11 /**< \brief (TC_CTRLA) Auto Lock */
126#define TC_CTRLA_ALOCK (_U_(0x1) << TC_CTRLA_ALOCK_Pos)
127#define TC_CTRLA_CAPTEN0_Pos 16 /**< \brief (TC_CTRLA) Capture Channel 0 Enable */
128#define TC_CTRLA_CAPTEN0 (_U_(1) << TC_CTRLA_CAPTEN0_Pos)
129#define TC_CTRLA_CAPTEN1_Pos 17 /**< \brief (TC_CTRLA) Capture Channel 1 Enable */
130#define TC_CTRLA_CAPTEN1 (_U_(1) << TC_CTRLA_CAPTEN1_Pos)
131#define TC_CTRLA_CAPTEN_Pos 16 /**< \brief (TC_CTRLA) Capture Channel x Enable */
132#define TC_CTRLA_CAPTEN_Msk (_U_(0x3) << TC_CTRLA_CAPTEN_Pos)
133#define TC_CTRLA_CAPTEN(value) (TC_CTRLA_CAPTEN_Msk & ((value) << TC_CTRLA_CAPTEN_Pos))
134#define TC_CTRLA_COPEN0_Pos 20 /**< \brief (TC_CTRLA) Capture On Pin 0 Enable */
135#define TC_CTRLA_COPEN0 (_U_(1) << TC_CTRLA_COPEN0_Pos)
136#define TC_CTRLA_COPEN1_Pos 21 /**< \brief (TC_CTRLA) Capture On Pin 1 Enable */
137#define TC_CTRLA_COPEN1 (_U_(1) << TC_CTRLA_COPEN1_Pos)
138#define TC_CTRLA_COPEN_Pos 20 /**< \brief (TC_CTRLA) Capture On Pin x Enable */
139#define TC_CTRLA_COPEN_Msk (_U_(0x3) << TC_CTRLA_COPEN_Pos)
140#define TC_CTRLA_COPEN(value) (TC_CTRLA_COPEN_Msk & ((value) << TC_CTRLA_COPEN_Pos))
141#define TC_CTRLA_CAPTMODE0_Pos 24 /**< \brief (TC_CTRLA) Capture Mode Channel 0 */
142#define TC_CTRLA_CAPTMODE0_Msk (_U_(0x3) << TC_CTRLA_CAPTMODE0_Pos)
143#define TC_CTRLA_CAPTMODE0(value) (TC_CTRLA_CAPTMODE0_Msk & ((value) << TC_CTRLA_CAPTMODE0_Pos))
144#define TC_CTRLA_CAPTMODE0_DEFAULT_Val _U_(0x0) /**< \brief (TC_CTRLA) Default capture */
145#define TC_CTRLA_CAPTMODE0_CAPTMIN_Val _U_(0x1) /**< \brief (TC_CTRLA) Minimum capture */
146#define TC_CTRLA_CAPTMODE0_CAPTMAX_Val _U_(0x2) /**< \brief (TC_CTRLA) Maximum capture */
147#define TC_CTRLA_CAPTMODE0_DEFAULT (TC_CTRLA_CAPTMODE0_DEFAULT_Val << TC_CTRLA_CAPTMODE0_Pos)
148#define TC_CTRLA_CAPTMODE0_CAPTMIN (TC_CTRLA_CAPTMODE0_CAPTMIN_Val << TC_CTRLA_CAPTMODE0_Pos)
149#define TC_CTRLA_CAPTMODE0_CAPTMAX (TC_CTRLA_CAPTMODE0_CAPTMAX_Val << TC_CTRLA_CAPTMODE0_Pos)
150#define TC_CTRLA_CAPTMODE1_Pos 27 /**< \brief (TC_CTRLA) Capture mode Channel 1 */
151#define TC_CTRLA_CAPTMODE1_Msk (_U_(0x3) << TC_CTRLA_CAPTMODE1_Pos)
152#define TC_CTRLA_CAPTMODE1(value) (TC_CTRLA_CAPTMODE1_Msk & ((value) << TC_CTRLA_CAPTMODE1_Pos))
153#define TC_CTRLA_CAPTMODE1_DEFAULT_Val _U_(0x0) /**< \brief (TC_CTRLA) Default capture */
154#define TC_CTRLA_CAPTMODE1_CAPTMIN_Val _U_(0x1) /**< \brief (TC_CTRLA) Minimum capture */
155#define TC_CTRLA_CAPTMODE1_CAPTMAX_Val _U_(0x2) /**< \brief (TC_CTRLA) Maximum capture */
156#define TC_CTRLA_CAPTMODE1_DEFAULT (TC_CTRLA_CAPTMODE1_DEFAULT_Val << TC_CTRLA_CAPTMODE1_Pos)
157#define TC_CTRLA_CAPTMODE1_CAPTMIN (TC_CTRLA_CAPTMODE1_CAPTMIN_Val << TC_CTRLA_CAPTMODE1_Pos)
158#define TC_CTRLA_CAPTMODE1_CAPTMAX (TC_CTRLA_CAPTMODE1_CAPTMAX_Val << TC_CTRLA_CAPTMODE1_Pos)
159#define TC_CTRLA_MASK _U_(0x1B330FFF) /**< \brief (TC_CTRLA) MASK Register */
160
161/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */
162#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
163typedef union {
164 struct {
165 uint8_t DIR:1; /*!< bit: 0 Counter Direction */
166 uint8_t LUPD:1; /*!< bit: 1 Lock Update */
167 uint8_t ONESHOT:1; /*!< bit: 2 One-Shot on Counter */
168 uint8_t :2; /*!< bit: 3.. 4 Reserved */
169 uint8_t CMD:3; /*!< bit: 5.. 7 Command */
170 } bit; /*!< Structure used for bit access */
171 uint8_t reg; /*!< Type used for register access */
172} TC_CTRLBCLR_Type;
173#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
174
175#define TC_CTRLBCLR_OFFSET 0x04 /**< \brief (TC_CTRLBCLR offset) Control B Clear */
176#define TC_CTRLBCLR_RESETVALUE _U_(0x00) /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */
177
178#define TC_CTRLBCLR_DIR_Pos 0 /**< \brief (TC_CTRLBCLR) Counter Direction */
179#define TC_CTRLBCLR_DIR (_U_(0x1) << TC_CTRLBCLR_DIR_Pos)
180#define TC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TC_CTRLBCLR) Lock Update */
181#define TC_CTRLBCLR_LUPD (_U_(0x1) << TC_CTRLBCLR_LUPD_Pos)
182#define TC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TC_CTRLBCLR) One-Shot on Counter */
183#define TC_CTRLBCLR_ONESHOT (_U_(0x1) << TC_CTRLBCLR_ONESHOT_Pos)
184#define TC_CTRLBCLR_CMD_Pos 5 /**< \brief (TC_CTRLBCLR) Command */
185#define TC_CTRLBCLR_CMD_Msk (_U_(0x7) << TC_CTRLBCLR_CMD_Pos)
186#define TC_CTRLBCLR_CMD(value) (TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos))
187#define TC_CTRLBCLR_CMD_NONE_Val _U_(0x0) /**< \brief (TC_CTRLBCLR) No action */
188#define TC_CTRLBCLR_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */
189#define TC_CTRLBCLR_CMD_STOP_Val _U_(0x2) /**< \brief (TC_CTRLBCLR) Force a stop */
190#define TC_CTRLBCLR_CMD_UPDATE_Val _U_(0x3) /**< \brief (TC_CTRLBCLR) Force update of double-buffered register */
191#define TC_CTRLBCLR_CMD_READSYNC_Val _U_(0x4) /**< \brief (TC_CTRLBCLR) Force a read synchronization of COUNT */
192#define TC_CTRLBCLR_CMD_DMAOS_Val _U_(0x5) /**< \brief (TC_CTRLBCLR) One-shot DMA trigger */
193#define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos)
194#define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos)
195#define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos)
196#define TC_CTRLBCLR_CMD_UPDATE (TC_CTRLBCLR_CMD_UPDATE_Val << TC_CTRLBCLR_CMD_Pos)
197#define TC_CTRLBCLR_CMD_READSYNC (TC_CTRLBCLR_CMD_READSYNC_Val << TC_CTRLBCLR_CMD_Pos)
198#define TC_CTRLBCLR_CMD_DMAOS (TC_CTRLBCLR_CMD_DMAOS_Val << TC_CTRLBCLR_CMD_Pos)
199#define TC_CTRLBCLR_MASK _U_(0xE7) /**< \brief (TC_CTRLBCLR) MASK Register */
200
201/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */
202#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
203typedef union {
204 struct {
205 uint8_t DIR:1; /*!< bit: 0 Counter Direction */
206 uint8_t LUPD:1; /*!< bit: 1 Lock Update */
207 uint8_t ONESHOT:1; /*!< bit: 2 One-Shot on Counter */
208 uint8_t :2; /*!< bit: 3.. 4 Reserved */
209 uint8_t CMD:3; /*!< bit: 5.. 7 Command */
210 } bit; /*!< Structure used for bit access */
211 uint8_t reg; /*!< Type used for register access */
212} TC_CTRLBSET_Type;
213#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
214
215#define TC_CTRLBSET_OFFSET 0x05 /**< \brief (TC_CTRLBSET offset) Control B Set */
216#define TC_CTRLBSET_RESETVALUE _U_(0x00) /**< \brief (TC_CTRLBSET reset_value) Control B Set */
217
218#define TC_CTRLBSET_DIR_Pos 0 /**< \brief (TC_CTRLBSET) Counter Direction */
219#define TC_CTRLBSET_DIR (_U_(0x1) << TC_CTRLBSET_DIR_Pos)
220#define TC_CTRLBSET_LUPD_Pos 1 /**< \brief (TC_CTRLBSET) Lock Update */
221#define TC_CTRLBSET_LUPD (_U_(0x1) << TC_CTRLBSET_LUPD_Pos)
222#define TC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TC_CTRLBSET) One-Shot on Counter */
223#define TC_CTRLBSET_ONESHOT (_U_(0x1) << TC_CTRLBSET_ONESHOT_Pos)
224#define TC_CTRLBSET_CMD_Pos 5 /**< \brief (TC_CTRLBSET) Command */
225#define TC_CTRLBSET_CMD_Msk (_U_(0x7) << TC_CTRLBSET_CMD_Pos)
226#define TC_CTRLBSET_CMD(value) (TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos))
227#define TC_CTRLBSET_CMD_NONE_Val _U_(0x0) /**< \brief (TC_CTRLBSET) No action */
228#define TC_CTRLBSET_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */
229#define TC_CTRLBSET_CMD_STOP_Val _U_(0x2) /**< \brief (TC_CTRLBSET) Force a stop */
230#define TC_CTRLBSET_CMD_UPDATE_Val _U_(0x3) /**< \brief (TC_CTRLBSET) Force update of double-buffered register */
231#define TC_CTRLBSET_CMD_READSYNC_Val _U_(0x4) /**< \brief (TC_CTRLBSET) Force a read synchronization of COUNT */
232#define TC_CTRLBSET_CMD_DMAOS_Val _U_(0x5) /**< \brief (TC_CTRLBSET) One-shot DMA trigger */
233#define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos)
234#define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos)
235#define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos)
236#define TC_CTRLBSET_CMD_UPDATE (TC_CTRLBSET_CMD_UPDATE_Val << TC_CTRLBSET_CMD_Pos)
237#define TC_CTRLBSET_CMD_READSYNC (TC_CTRLBSET_CMD_READSYNC_Val << TC_CTRLBSET_CMD_Pos)
238#define TC_CTRLBSET_CMD_DMAOS (TC_CTRLBSET_CMD_DMAOS_Val << TC_CTRLBSET_CMD_Pos)
239#define TC_CTRLBSET_MASK _U_(0xE7) /**< \brief (TC_CTRLBSET) MASK Register */
240
241/* -------- TC_EVCTRL : (TC Offset: 0x06) (R/W 16) Event Control -------- */
242#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
243typedef union {
244 struct {
245 uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */
246 uint16_t :1; /*!< bit: 3 Reserved */
247 uint16_t TCINV:1; /*!< bit: 4 TC Event Input Polarity */
248 uint16_t TCEI:1; /*!< bit: 5 TC Event Enable */
249 uint16_t :2; /*!< bit: 6.. 7 Reserved */
250 uint16_t OVFEO:1; /*!< bit: 8 Event Output Enable */
251 uint16_t :3; /*!< bit: 9..11 Reserved */
252 uint16_t MCEO0:1; /*!< bit: 12 MC Event Output Enable 0 */
253 uint16_t MCEO1:1; /*!< bit: 13 MC Event Output Enable 1 */
254 uint16_t :2; /*!< bit: 14..15 Reserved */
255 } bit; /*!< Structure used for bit access */
256 struct {
257 uint16_t :12; /*!< bit: 0..11 Reserved */
258 uint16_t MCEO:2; /*!< bit: 12..13 MC Event Output Enable x */
259 uint16_t :2; /*!< bit: 14..15 Reserved */
260 } vec; /*!< Structure used for vec access */
261 uint16_t reg; /*!< Type used for register access */
262} TC_EVCTRL_Type;
263#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
264
265#define TC_EVCTRL_OFFSET 0x06 /**< \brief (TC_EVCTRL offset) Event Control */
266#define TC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (TC_EVCTRL reset_value) Event Control */
267
268#define TC_EVCTRL_EVACT_Pos 0 /**< \brief (TC_EVCTRL) Event Action */
269#define TC_EVCTRL_EVACT_Msk (_U_(0x7) << TC_EVCTRL_EVACT_Pos)
270#define TC_EVCTRL_EVACT(value) (TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos))
271#define TC_EVCTRL_EVACT_OFF_Val _U_(0x0) /**< \brief (TC_EVCTRL) Event action disabled */
272#define TC_EVCTRL_EVACT_RETRIGGER_Val _U_(0x1) /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */
273#define TC_EVCTRL_EVACT_COUNT_Val _U_(0x2) /**< \brief (TC_EVCTRL) Count on event */
274#define TC_EVCTRL_EVACT_START_Val _U_(0x3) /**< \brief (TC_EVCTRL) Start TC on event */
275#define TC_EVCTRL_EVACT_STAMP_Val _U_(0x4) /**< \brief (TC_EVCTRL) Time stamp capture */
276#define TC_EVCTRL_EVACT_PPW_Val _U_(0x5) /**< \brief (TC_EVCTRL) Period catured in CC0, pulse width in CC1 */
277#define TC_EVCTRL_EVACT_PWP_Val _U_(0x6) /**< \brief (TC_EVCTRL) Period catured in CC1, pulse width in CC0 */
278#define TC_EVCTRL_EVACT_PW_Val _U_(0x7) /**< \brief (TC_EVCTRL) Pulse width capture */
279#define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos)
280#define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos)
281#define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos)
282#define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos)
283#define TC_EVCTRL_EVACT_STAMP (TC_EVCTRL_EVACT_STAMP_Val << TC_EVCTRL_EVACT_Pos)
284#define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos)
285#define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos)
286#define TC_EVCTRL_EVACT_PW (TC_EVCTRL_EVACT_PW_Val << TC_EVCTRL_EVACT_Pos)
287#define TC_EVCTRL_TCINV_Pos 4 /**< \brief (TC_EVCTRL) TC Event Input Polarity */
288#define TC_EVCTRL_TCINV (_U_(0x1) << TC_EVCTRL_TCINV_Pos)
289#define TC_EVCTRL_TCEI_Pos 5 /**< \brief (TC_EVCTRL) TC Event Enable */
290#define TC_EVCTRL_TCEI (_U_(0x1) << TC_EVCTRL_TCEI_Pos)
291#define TC_EVCTRL_OVFEO_Pos 8 /**< \brief (TC_EVCTRL) Event Output Enable */
292#define TC_EVCTRL_OVFEO (_U_(0x1) << TC_EVCTRL_OVFEO_Pos)
293#define TC_EVCTRL_MCEO0_Pos 12 /**< \brief (TC_EVCTRL) MC Event Output Enable 0 */
294#define TC_EVCTRL_MCEO0 (_U_(1) << TC_EVCTRL_MCEO0_Pos)
295#define TC_EVCTRL_MCEO1_Pos 13 /**< \brief (TC_EVCTRL) MC Event Output Enable 1 */
296#define TC_EVCTRL_MCEO1 (_U_(1) << TC_EVCTRL_MCEO1_Pos)
297#define TC_EVCTRL_MCEO_Pos 12 /**< \brief (TC_EVCTRL) MC Event Output Enable x */
298#define TC_EVCTRL_MCEO_Msk (_U_(0x3) << TC_EVCTRL_MCEO_Pos)
299#define TC_EVCTRL_MCEO(value) (TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos))
300#define TC_EVCTRL_MASK _U_(0x3137) /**< \brief (TC_EVCTRL) MASK Register */
301
302/* -------- TC_INTENCLR : (TC Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */
303#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
304typedef union {
305 struct {
306 uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Disable */
307 uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Disable */
308 uint8_t :2; /*!< bit: 2.. 3 Reserved */
309 uint8_t MC0:1; /*!< bit: 4 MC Interrupt Disable 0 */
310 uint8_t MC1:1; /*!< bit: 5 MC Interrupt Disable 1 */
311 uint8_t :2; /*!< bit: 6.. 7 Reserved */
312 } bit; /*!< Structure used for bit access */
313 struct {
314 uint8_t :4; /*!< bit: 0.. 3 Reserved */
315 uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Disable x */
316 uint8_t :2; /*!< bit: 6.. 7 Reserved */
317 } vec; /*!< Structure used for vec access */
318 uint8_t reg; /*!< Type used for register access */
319} TC_INTENCLR_Type;
320#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
321
322#define TC_INTENCLR_OFFSET 0x08 /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */
323#define TC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */
324
325#define TC_INTENCLR_OVF_Pos 0 /**< \brief (TC_INTENCLR) OVF Interrupt Disable */
326#define TC_INTENCLR_OVF (_U_(0x1) << TC_INTENCLR_OVF_Pos)
327#define TC_INTENCLR_ERR_Pos 1 /**< \brief (TC_INTENCLR) ERR Interrupt Disable */
328#define TC_INTENCLR_ERR (_U_(0x1) << TC_INTENCLR_ERR_Pos)
329#define TC_INTENCLR_MC0_Pos 4 /**< \brief (TC_INTENCLR) MC Interrupt Disable 0 */
330#define TC_INTENCLR_MC0 (_U_(1) << TC_INTENCLR_MC0_Pos)
331#define TC_INTENCLR_MC1_Pos 5 /**< \brief (TC_INTENCLR) MC Interrupt Disable 1 */
332#define TC_INTENCLR_MC1 (_U_(1) << TC_INTENCLR_MC1_Pos)
333#define TC_INTENCLR_MC_Pos 4 /**< \brief (TC_INTENCLR) MC Interrupt Disable x */
334#define TC_INTENCLR_MC_Msk (_U_(0x3) << TC_INTENCLR_MC_Pos)
335#define TC_INTENCLR_MC(value) (TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos))
336#define TC_INTENCLR_MASK _U_(0x33) /**< \brief (TC_INTENCLR) MASK Register */
337
338/* -------- TC_INTENSET : (TC Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */
339#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
340typedef union {
341 struct {
342 uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Enable */
343 uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Enable */
344 uint8_t :2; /*!< bit: 2.. 3 Reserved */
345 uint8_t MC0:1; /*!< bit: 4 MC Interrupt Enable 0 */
346 uint8_t MC1:1; /*!< bit: 5 MC Interrupt Enable 1 */
347 uint8_t :2; /*!< bit: 6.. 7 Reserved */
348 } bit; /*!< Structure used for bit access */
349 struct {
350 uint8_t :4; /*!< bit: 0.. 3 Reserved */
351 uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Enable x */
352 uint8_t :2; /*!< bit: 6.. 7 Reserved */
353 } vec; /*!< Structure used for vec access */
354 uint8_t reg; /*!< Type used for register access */
355} TC_INTENSET_Type;
356#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
357
358#define TC_INTENSET_OFFSET 0x09 /**< \brief (TC_INTENSET offset) Interrupt Enable Set */
359#define TC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */
360
361#define TC_INTENSET_OVF_Pos 0 /**< \brief (TC_INTENSET) OVF Interrupt Enable */
362#define TC_INTENSET_OVF (_U_(0x1) << TC_INTENSET_OVF_Pos)
363#define TC_INTENSET_ERR_Pos 1 /**< \brief (TC_INTENSET) ERR Interrupt Enable */
364#define TC_INTENSET_ERR (_U_(0x1) << TC_INTENSET_ERR_Pos)
365#define TC_INTENSET_MC0_Pos 4 /**< \brief (TC_INTENSET) MC Interrupt Enable 0 */
366#define TC_INTENSET_MC0 (_U_(1) << TC_INTENSET_MC0_Pos)
367#define TC_INTENSET_MC1_Pos 5 /**< \brief (TC_INTENSET) MC Interrupt Enable 1 */
368#define TC_INTENSET_MC1 (_U_(1) << TC_INTENSET_MC1_Pos)
369#define TC_INTENSET_MC_Pos 4 /**< \brief (TC_INTENSET) MC Interrupt Enable x */
370#define TC_INTENSET_MC_Msk (_U_(0x3) << TC_INTENSET_MC_Pos)
371#define TC_INTENSET_MC(value) (TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos))
372#define TC_INTENSET_MASK _U_(0x33) /**< \brief (TC_INTENSET) MASK Register */
373
374/* -------- TC_INTFLAG : (TC Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */
375#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
376typedef union { // __I to avoid read-modify-write on write-to-clear register
377 struct {
378 __I uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Flag */
379 __I uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Flag */
380 __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
381 __I uint8_t MC0:1; /*!< bit: 4 MC Interrupt Flag 0 */
382 __I uint8_t MC1:1; /*!< bit: 5 MC Interrupt Flag 1 */
383 __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
384 } bit; /*!< Structure used for bit access */
385 struct {
386 __I uint8_t :4; /*!< bit: 0.. 3 Reserved */
387 __I uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Flag x */
388 __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
389 } vec; /*!< Structure used for vec access */
390 uint8_t reg; /*!< Type used for register access */
391} TC_INTFLAG_Type;
392#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
393
394#define TC_INTFLAG_OFFSET 0x0A /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */
395#define TC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */
396
397#define TC_INTFLAG_OVF_Pos 0 /**< \brief (TC_INTFLAG) OVF Interrupt Flag */
398#define TC_INTFLAG_OVF (_U_(0x1) << TC_INTFLAG_OVF_Pos)
399#define TC_INTFLAG_ERR_Pos 1 /**< \brief (TC_INTFLAG) ERR Interrupt Flag */
400#define TC_INTFLAG_ERR (_U_(0x1) << TC_INTFLAG_ERR_Pos)
401#define TC_INTFLAG_MC0_Pos 4 /**< \brief (TC_INTFLAG) MC Interrupt Flag 0 */
402#define TC_INTFLAG_MC0 (_U_(1) << TC_INTFLAG_MC0_Pos)
403#define TC_INTFLAG_MC1_Pos 5 /**< \brief (TC_INTFLAG) MC Interrupt Flag 1 */
404#define TC_INTFLAG_MC1 (_U_(1) << TC_INTFLAG_MC1_Pos)
405#define TC_INTFLAG_MC_Pos 4 /**< \brief (TC_INTFLAG) MC Interrupt Flag x */
406#define TC_INTFLAG_MC_Msk (_U_(0x3) << TC_INTFLAG_MC_Pos)
407#define TC_INTFLAG_MC(value) (TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos))
408#define TC_INTFLAG_MASK _U_(0x33) /**< \brief (TC_INTFLAG) MASK Register */
409
410/* -------- TC_STATUS : (TC Offset: 0x0B) (R/W 8) Status -------- */
411#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
412typedef union {
413 struct {
414 uint8_t STOP:1; /*!< bit: 0 Stop Status Flag */
415 uint8_t SLAVE:1; /*!< bit: 1 Slave Status Flag */
416 uint8_t :1; /*!< bit: 2 Reserved */
417 uint8_t PERBUFV:1; /*!< bit: 3 Synchronization Busy Status */
418 uint8_t CCBUFV0:1; /*!< bit: 4 Compare channel buffer 0 valid */
419 uint8_t CCBUFV1:1; /*!< bit: 5 Compare channel buffer 1 valid */
420 uint8_t :2; /*!< bit: 6.. 7 Reserved */
421 } bit; /*!< Structure used for bit access */
422 struct {
423 uint8_t :4; /*!< bit: 0.. 3 Reserved */
424 uint8_t CCBUFV:2; /*!< bit: 4.. 5 Compare channel buffer x valid */
425 uint8_t :2; /*!< bit: 6.. 7 Reserved */
426 } vec; /*!< Structure used for vec access */
427 uint8_t reg; /*!< Type used for register access */
428} TC_STATUS_Type;
429#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
430
431#define TC_STATUS_OFFSET 0x0B /**< \brief (TC_STATUS offset) Status */
432#define TC_STATUS_RESETVALUE _U_(0x01) /**< \brief (TC_STATUS reset_value) Status */
433
434#define TC_STATUS_STOP_Pos 0 /**< \brief (TC_STATUS) Stop Status Flag */
435#define TC_STATUS_STOP (_U_(0x1) << TC_STATUS_STOP_Pos)
436#define TC_STATUS_SLAVE_Pos 1 /**< \brief (TC_STATUS) Slave Status Flag */
437#define TC_STATUS_SLAVE (_U_(0x1) << TC_STATUS_SLAVE_Pos)
438#define TC_STATUS_PERBUFV_Pos 3 /**< \brief (TC_STATUS) Synchronization Busy Status */
439#define TC_STATUS_PERBUFV (_U_(0x1) << TC_STATUS_PERBUFV_Pos)
440#define TC_STATUS_CCBUFV0_Pos 4 /**< \brief (TC_STATUS) Compare channel buffer 0 valid */
441#define TC_STATUS_CCBUFV0 (_U_(1) << TC_STATUS_CCBUFV0_Pos)
442#define TC_STATUS_CCBUFV1_Pos 5 /**< \brief (TC_STATUS) Compare channel buffer 1 valid */
443#define TC_STATUS_CCBUFV1 (_U_(1) << TC_STATUS_CCBUFV1_Pos)
444#define TC_STATUS_CCBUFV_Pos 4 /**< \brief (TC_STATUS) Compare channel buffer x valid */
445#define TC_STATUS_CCBUFV_Msk (_U_(0x3) << TC_STATUS_CCBUFV_Pos)
446#define TC_STATUS_CCBUFV(value) (TC_STATUS_CCBUFV_Msk & ((value) << TC_STATUS_CCBUFV_Pos))
447#define TC_STATUS_MASK _U_(0x3B) /**< \brief (TC_STATUS) MASK Register */
448
449/* -------- TC_WAVE : (TC Offset: 0x0C) (R/W 8) Waveform Generation Control -------- */
450#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
451typedef union {
452 struct {
453 uint8_t WAVEGEN:2; /*!< bit: 0.. 1 Waveform Generation Mode */
454 uint8_t :6; /*!< bit: 2.. 7 Reserved */
455 } bit; /*!< Structure used for bit access */
456 uint8_t reg; /*!< Type used for register access */
457} TC_WAVE_Type;
458#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
459
460#define TC_WAVE_OFFSET 0x0C /**< \brief (TC_WAVE offset) Waveform Generation Control */
461#define TC_WAVE_RESETVALUE _U_(0x00) /**< \brief (TC_WAVE reset_value) Waveform Generation Control */
462
463#define TC_WAVE_WAVEGEN_Pos 0 /**< \brief (TC_WAVE) Waveform Generation Mode */
464#define TC_WAVE_WAVEGEN_Msk (_U_(0x3) << TC_WAVE_WAVEGEN_Pos)
465#define TC_WAVE_WAVEGEN(value) (TC_WAVE_WAVEGEN_Msk & ((value) << TC_WAVE_WAVEGEN_Pos))
466#define TC_WAVE_WAVEGEN_NFRQ_Val _U_(0x0) /**< \brief (TC_WAVE) Normal frequency */
467#define TC_WAVE_WAVEGEN_MFRQ_Val _U_(0x1) /**< \brief (TC_WAVE) Match frequency */
468#define TC_WAVE_WAVEGEN_NPWM_Val _U_(0x2) /**< \brief (TC_WAVE) Normal PWM */
469#define TC_WAVE_WAVEGEN_MPWM_Val _U_(0x3) /**< \brief (TC_WAVE) Match PWM */
470#define TC_WAVE_WAVEGEN_NFRQ (TC_WAVE_WAVEGEN_NFRQ_Val << TC_WAVE_WAVEGEN_Pos)
471#define TC_WAVE_WAVEGEN_MFRQ (TC_WAVE_WAVEGEN_MFRQ_Val << TC_WAVE_WAVEGEN_Pos)
472#define TC_WAVE_WAVEGEN_NPWM (TC_WAVE_WAVEGEN_NPWM_Val << TC_WAVE_WAVEGEN_Pos)
473#define TC_WAVE_WAVEGEN_MPWM (TC_WAVE_WAVEGEN_MPWM_Val << TC_WAVE_WAVEGEN_Pos)
474#define TC_WAVE_MASK _U_(0x03) /**< \brief (TC_WAVE) MASK Register */
475
476/* -------- TC_DRVCTRL : (TC Offset: 0x0D) (R/W 8) Control C -------- */
477#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
478typedef union {
479 struct {
480 uint8_t INVEN0:1; /*!< bit: 0 Output Waveform Invert Enable 0 */
481 uint8_t INVEN1:1; /*!< bit: 1 Output Waveform Invert Enable 1 */
482 uint8_t :6; /*!< bit: 2.. 7 Reserved */
483 } bit; /*!< Structure used for bit access */
484 struct {
485 uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform Invert Enable x */
486 uint8_t :6; /*!< bit: 2.. 7 Reserved */
487 } vec; /*!< Structure used for vec access */
488 uint8_t reg; /*!< Type used for register access */
489} TC_DRVCTRL_Type;
490#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
491
492#define TC_DRVCTRL_OFFSET 0x0D /**< \brief (TC_DRVCTRL offset) Control C */
493#define TC_DRVCTRL_RESETVALUE _U_(0x00) /**< \brief (TC_DRVCTRL reset_value) Control C */
494
495#define TC_DRVCTRL_INVEN0_Pos 0 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable 0 */
496#define TC_DRVCTRL_INVEN0 (_U_(1) << TC_DRVCTRL_INVEN0_Pos)
497#define TC_DRVCTRL_INVEN1_Pos 1 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable 1 */
498#define TC_DRVCTRL_INVEN1 (_U_(1) << TC_DRVCTRL_INVEN1_Pos)
499#define TC_DRVCTRL_INVEN_Pos 0 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable x */
500#define TC_DRVCTRL_INVEN_Msk (_U_(0x3) << TC_DRVCTRL_INVEN_Pos)
501#define TC_DRVCTRL_INVEN(value) (TC_DRVCTRL_INVEN_Msk & ((value) << TC_DRVCTRL_INVEN_Pos))
502#define TC_DRVCTRL_MASK _U_(0x03) /**< \brief (TC_DRVCTRL) MASK Register */
503
504/* -------- TC_DBGCTRL : (TC Offset: 0x0F) (R/W 8) Debug Control -------- */
505#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
506typedef union {
507 struct {
508 uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
509 uint8_t :7; /*!< bit: 1.. 7 Reserved */
510 } bit; /*!< Structure used for bit access */
511 uint8_t reg; /*!< Type used for register access */
512} TC_DBGCTRL_Type;
513#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
514
515#define TC_DBGCTRL_OFFSET 0x0F /**< \brief (TC_DBGCTRL offset) Debug Control */
516#define TC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (TC_DBGCTRL reset_value) Debug Control */
517
518#define TC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TC_DBGCTRL) Run During Debug */
519#define TC_DBGCTRL_DBGRUN (_U_(0x1) << TC_DBGCTRL_DBGRUN_Pos)
520#define TC_DBGCTRL_MASK _U_(0x01) /**< \brief (TC_DBGCTRL) MASK Register */
521
522/* -------- TC_SYNCBUSY : (TC Offset: 0x10) (R/ 32) Synchronization Status -------- */
523#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
524typedef union {
525 struct {
526 uint32_t SWRST:1; /*!< bit: 0 swrst */
527 uint32_t ENABLE:1; /*!< bit: 1 enable */
528 uint32_t CTRLB:1; /*!< bit: 2 CTRLB */
529 uint32_t STATUS:1; /*!< bit: 3 STATUS */
530 uint32_t COUNT:1; /*!< bit: 4 Counter */
531 uint32_t PER:1; /*!< bit: 5 Period */
532 uint32_t CC0:1; /*!< bit: 6 Compare Channel 0 */
533 uint32_t CC1:1; /*!< bit: 7 Compare Channel 1 */
534 uint32_t :24; /*!< bit: 8..31 Reserved */
535 } bit; /*!< Structure used for bit access */
536 struct {
537 uint32_t :6; /*!< bit: 0.. 5 Reserved */
538 uint32_t CC:2; /*!< bit: 6.. 7 Compare Channel x */
539 uint32_t :24; /*!< bit: 8..31 Reserved */
540 } vec; /*!< Structure used for vec access */
541 uint32_t reg; /*!< Type used for register access */
542} TC_SYNCBUSY_Type;
543#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
544
545#define TC_SYNCBUSY_OFFSET 0x10 /**< \brief (TC_SYNCBUSY offset) Synchronization Status */
546#define TC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (TC_SYNCBUSY reset_value) Synchronization Status */
547
548#define TC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TC_SYNCBUSY) swrst */
549#define TC_SYNCBUSY_SWRST (_U_(0x1) << TC_SYNCBUSY_SWRST_Pos)
550#define TC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TC_SYNCBUSY) enable */
551#define TC_SYNCBUSY_ENABLE (_U_(0x1) << TC_SYNCBUSY_ENABLE_Pos)
552#define TC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TC_SYNCBUSY) CTRLB */
553#define TC_SYNCBUSY_CTRLB (_U_(0x1) << TC_SYNCBUSY_CTRLB_Pos)
554#define TC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TC_SYNCBUSY) STATUS */
555#define TC_SYNCBUSY_STATUS (_U_(0x1) << TC_SYNCBUSY_STATUS_Pos)
556#define TC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TC_SYNCBUSY) Counter */
557#define TC_SYNCBUSY_COUNT (_U_(0x1) << TC_SYNCBUSY_COUNT_Pos)
558#define TC_SYNCBUSY_PER_Pos 5 /**< \brief (TC_SYNCBUSY) Period */
559#define TC_SYNCBUSY_PER (_U_(0x1) << TC_SYNCBUSY_PER_Pos)
560#define TC_SYNCBUSY_CC0_Pos 6 /**< \brief (TC_SYNCBUSY) Compare Channel 0 */
561#define TC_SYNCBUSY_CC0 (_U_(1) << TC_SYNCBUSY_CC0_Pos)
562#define TC_SYNCBUSY_CC1_Pos 7 /**< \brief (TC_SYNCBUSY) Compare Channel 1 */
563#define TC_SYNCBUSY_CC1 (_U_(1) << TC_SYNCBUSY_CC1_Pos)
564#define TC_SYNCBUSY_CC_Pos 6 /**< \brief (TC_SYNCBUSY) Compare Channel x */
565#define TC_SYNCBUSY_CC_Msk (_U_(0x3) << TC_SYNCBUSY_CC_Pos)
566#define TC_SYNCBUSY_CC(value) (TC_SYNCBUSY_CC_Msk & ((value) << TC_SYNCBUSY_CC_Pos))
567#define TC_SYNCBUSY_MASK _U_(0x000000FF) /**< \brief (TC_SYNCBUSY) MASK Register */
568
569/* -------- TC_COUNT16_COUNT : (TC Offset: 0x14) (R/W 16) COUNT16 COUNT16 Count -------- */
570#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
571typedef union {
572 struct {
573 uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
574 } bit; /*!< Structure used for bit access */
575 uint16_t reg; /*!< Type used for register access */
576} TC_COUNT16_COUNT_Type;
577#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
578
579#define TC_COUNT16_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Count */
580#define TC_COUNT16_COUNT_RESETVALUE _U_(0x0000) /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Count */
581
582#define TC_COUNT16_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT16_COUNT) Counter Value */
583#define TC_COUNT16_COUNT_COUNT_Msk (_U_(0xFFFF) << TC_COUNT16_COUNT_COUNT_Pos)
584#define TC_COUNT16_COUNT_COUNT(value) (TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos))
585#define TC_COUNT16_COUNT_MASK _U_(0xFFFF) /**< \brief (TC_COUNT16_COUNT) MASK Register */
586
587/* -------- TC_COUNT32_COUNT : (TC Offset: 0x14) (R/W 32) COUNT32 COUNT32 Count -------- */
588#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
589typedef union {
590 struct {
591 uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
592 } bit; /*!< Structure used for bit access */
593 uint32_t reg; /*!< Type used for register access */
594} TC_COUNT32_COUNT_Type;
595#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
596
597#define TC_COUNT32_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Count */
598#define TC_COUNT32_COUNT_RESETVALUE _U_(0x00000000) /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Count */
599
600#define TC_COUNT32_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT32_COUNT) Counter Value */
601#define TC_COUNT32_COUNT_COUNT_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_COUNT_COUNT_Pos)
602#define TC_COUNT32_COUNT_COUNT(value) (TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos))
603#define TC_COUNT32_COUNT_MASK _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_COUNT) MASK Register */
604
605/* -------- TC_COUNT8_COUNT : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Count -------- */
606#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
607typedef union {
608 struct {
609 uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */
610 } bit; /*!< Structure used for bit access */
611 uint8_t reg; /*!< Type used for register access */
612} TC_COUNT8_COUNT_Type;
613#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
614
615#define TC_COUNT8_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Count */
616#define TC_COUNT8_COUNT_RESETVALUE _U_(0x00) /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Count */
617
618#define TC_COUNT8_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT8_COUNT) Counter Value */
619#define TC_COUNT8_COUNT_COUNT_Msk (_U_(0xFF) << TC_COUNT8_COUNT_COUNT_Pos)
620#define TC_COUNT8_COUNT_COUNT(value) (TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos))
621#define TC_COUNT8_COUNT_MASK _U_(0xFF) /**< \brief (TC_COUNT8_COUNT) MASK Register */
622
623/* -------- TC_COUNT8_PER : (TC Offset: 0x1B) (R/W 8) COUNT8 COUNT8 Period -------- */
624#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
625typedef union {
626 struct {
627 uint8_t PER:8; /*!< bit: 0.. 7 Period Value */
628 } bit; /*!< Structure used for bit access */
629 uint8_t reg; /*!< Type used for register access */
630} TC_COUNT8_PER_Type;
631#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
632
633#define TC_COUNT8_PER_OFFSET 0x1B /**< \brief (TC_COUNT8_PER offset) COUNT8 Period */
634#define TC_COUNT8_PER_RESETVALUE _U_(0xFF) /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period */
635
636#define TC_COUNT8_PER_PER_Pos 0 /**< \brief (TC_COUNT8_PER) Period Value */
637#define TC_COUNT8_PER_PER_Msk (_U_(0xFF) << TC_COUNT8_PER_PER_Pos)
638#define TC_COUNT8_PER_PER(value) (TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos))
639#define TC_COUNT8_PER_MASK _U_(0xFF) /**< \brief (TC_COUNT8_PER) MASK Register */
640
641/* -------- TC_COUNT16_CC : (TC Offset: 0x1C) (R/W 16) COUNT16 COUNT16 Compare and Capture -------- */
642#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
643typedef union {
644 struct {
645 uint16_t CC:16; /*!< bit: 0..15 Counter/Compare Value */
646 } bit; /*!< Structure used for bit access */
647 uint16_t reg; /*!< Type used for register access */
648} TC_COUNT16_CC_Type;
649#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
650
651#define TC_COUNT16_CC_OFFSET 0x1C /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare and Capture */
652#define TC_COUNT16_CC_RESETVALUE _U_(0x0000) /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare and Capture */
653
654#define TC_COUNT16_CC_CC_Pos 0 /**< \brief (TC_COUNT16_CC) Counter/Compare Value */
655#define TC_COUNT16_CC_CC_Msk (_U_(0xFFFF) << TC_COUNT16_CC_CC_Pos)
656#define TC_COUNT16_CC_CC(value) (TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos))
657#define TC_COUNT16_CC_MASK _U_(0xFFFF) /**< \brief (TC_COUNT16_CC) MASK Register */
658
659/* -------- TC_COUNT32_CC : (TC Offset: 0x1C) (R/W 32) COUNT32 COUNT32 Compare and Capture -------- */
660#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
661typedef union {
662 struct {
663 uint32_t CC:32; /*!< bit: 0..31 Counter/Compare Value */
664 } bit; /*!< Structure used for bit access */
665 uint32_t reg; /*!< Type used for register access */
666} TC_COUNT32_CC_Type;
667#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
668
669#define TC_COUNT32_CC_OFFSET 0x1C /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare and Capture */
670#define TC_COUNT32_CC_RESETVALUE _U_(0x00000000) /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare and Capture */
671
672#define TC_COUNT32_CC_CC_Pos 0 /**< \brief (TC_COUNT32_CC) Counter/Compare Value */
673#define TC_COUNT32_CC_CC_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_CC_CC_Pos)
674#define TC_COUNT32_CC_CC(value) (TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos))
675#define TC_COUNT32_CC_MASK _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_CC) MASK Register */
676
677/* -------- TC_COUNT8_CC : (TC Offset: 0x1C) (R/W 8) COUNT8 COUNT8 Compare and Capture -------- */
678#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
679typedef union {
680 struct {
681 uint8_t CC:8; /*!< bit: 0.. 7 Counter/Compare Value */
682 } bit; /*!< Structure used for bit access */
683 uint8_t reg; /*!< Type used for register access */
684} TC_COUNT8_CC_Type;
685#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
686
687#define TC_COUNT8_CC_OFFSET 0x1C /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare and Capture */
688#define TC_COUNT8_CC_RESETVALUE _U_(0x00) /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare and Capture */
689
690#define TC_COUNT8_CC_CC_Pos 0 /**< \brief (TC_COUNT8_CC) Counter/Compare Value */
691#define TC_COUNT8_CC_CC_Msk (_U_(0xFF) << TC_COUNT8_CC_CC_Pos)
692#define TC_COUNT8_CC_CC(value) (TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos))
693#define TC_COUNT8_CC_MASK _U_(0xFF) /**< \brief (TC_COUNT8_CC) MASK Register */
694
695/* -------- TC_COUNT8_PERBUF : (TC Offset: 0x2F) (R/W 8) COUNT8 COUNT8 Period Buffer -------- */
696#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
697typedef union {
698 struct {
699 uint8_t PERBUF:8; /*!< bit: 0.. 7 Period Buffer Value */
700 } bit; /*!< Structure used for bit access */
701 uint8_t reg; /*!< Type used for register access */
702} TC_COUNT8_PERBUF_Type;
703#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
704
705#define TC_COUNT8_PERBUF_OFFSET 0x2F /**< \brief (TC_COUNT8_PERBUF offset) COUNT8 Period Buffer */
706#define TC_COUNT8_PERBUF_RESETVALUE _U_(0xFF) /**< \brief (TC_COUNT8_PERBUF reset_value) COUNT8 Period Buffer */
707
708#define TC_COUNT8_PERBUF_PERBUF_Pos 0 /**< \brief (TC_COUNT8_PERBUF) Period Buffer Value */
709#define TC_COUNT8_PERBUF_PERBUF_Msk (_U_(0xFF) << TC_COUNT8_PERBUF_PERBUF_Pos)
710#define TC_COUNT8_PERBUF_PERBUF(value) (TC_COUNT8_PERBUF_PERBUF_Msk & ((value) << TC_COUNT8_PERBUF_PERBUF_Pos))
711#define TC_COUNT8_PERBUF_MASK _U_(0xFF) /**< \brief (TC_COUNT8_PERBUF) MASK Register */
712
713/* -------- TC_COUNT16_CCBUF : (TC Offset: 0x30) (R/W 16) COUNT16 COUNT16 Compare and Capture Buffer -------- */
714#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
715typedef union {
716 struct {
717 uint16_t CCBUF:16; /*!< bit: 0..15 Counter/Compare Buffer Value */
718 } bit; /*!< Structure used for bit access */
719 uint16_t reg; /*!< Type used for register access */
720} TC_COUNT16_CCBUF_Type;
721#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
722
723#define TC_COUNT16_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT16_CCBUF offset) COUNT16 Compare and Capture Buffer */
724#define TC_COUNT16_CCBUF_RESETVALUE _U_(0x0000) /**< \brief (TC_COUNT16_CCBUF reset_value) COUNT16 Compare and Capture Buffer */
725
726#define TC_COUNT16_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT16_CCBUF) Counter/Compare Buffer Value */
727#define TC_COUNT16_CCBUF_CCBUF_Msk (_U_(0xFFFF) << TC_COUNT16_CCBUF_CCBUF_Pos)
728#define TC_COUNT16_CCBUF_CCBUF(value) (TC_COUNT16_CCBUF_CCBUF_Msk & ((value) << TC_COUNT16_CCBUF_CCBUF_Pos))
729#define TC_COUNT16_CCBUF_MASK _U_(0xFFFF) /**< \brief (TC_COUNT16_CCBUF) MASK Register */
730
731/* -------- TC_COUNT32_CCBUF : (TC Offset: 0x30) (R/W 32) COUNT32 COUNT32 Compare and Capture Buffer -------- */
732#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
733typedef union {
734 struct {
735 uint32_t CCBUF:32; /*!< bit: 0..31 Counter/Compare Buffer Value */
736 } bit; /*!< Structure used for bit access */
737 uint32_t reg; /*!< Type used for register access */
738} TC_COUNT32_CCBUF_Type;
739#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
740
741#define TC_COUNT32_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT32_CCBUF offset) COUNT32 Compare and Capture Buffer */
742#define TC_COUNT32_CCBUF_RESETVALUE _U_(0x00000000) /**< \brief (TC_COUNT32_CCBUF reset_value) COUNT32 Compare and Capture Buffer */
743
744#define TC_COUNT32_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT32_CCBUF) Counter/Compare Buffer Value */
745#define TC_COUNT32_CCBUF_CCBUF_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_CCBUF_CCBUF_Pos)
746#define TC_COUNT32_CCBUF_CCBUF(value) (TC_COUNT32_CCBUF_CCBUF_Msk & ((value) << TC_COUNT32_CCBUF_CCBUF_Pos))
747#define TC_COUNT32_CCBUF_MASK _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_CCBUF) MASK Register */
748
749/* -------- TC_COUNT8_CCBUF : (TC Offset: 0x30) (R/W 8) COUNT8 COUNT8 Compare and Capture Buffer -------- */
750#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
751typedef union {
752 struct {
753 uint8_t CCBUF:8; /*!< bit: 0.. 7 Counter/Compare Buffer Value */
754 } bit; /*!< Structure used for bit access */
755 uint8_t reg; /*!< Type used for register access */
756} TC_COUNT8_CCBUF_Type;
757#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
758
759#define TC_COUNT8_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT8_CCBUF offset) COUNT8 Compare and Capture Buffer */
760#define TC_COUNT8_CCBUF_RESETVALUE _U_(0x00) /**< \brief (TC_COUNT8_CCBUF reset_value) COUNT8 Compare and Capture Buffer */
761
762#define TC_COUNT8_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT8_CCBUF) Counter/Compare Buffer Value */
763#define TC_COUNT8_CCBUF_CCBUF_Msk (_U_(0xFF) << TC_COUNT8_CCBUF_CCBUF_Pos)
764#define TC_COUNT8_CCBUF_CCBUF(value) (TC_COUNT8_CCBUF_CCBUF_Msk & ((value) << TC_COUNT8_CCBUF_CCBUF_Pos))
765#define TC_COUNT8_CCBUF_MASK _U_(0xFF) /**< \brief (TC_COUNT8_CCBUF) MASK Register */
766
767/** \brief TC_COUNT8 hardware registers */
768#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
769typedef struct { /* 8-bit Counter Mode */
770 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
771 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
772 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
773 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */
774 __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
775 __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
776 __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
777 __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */
778 __IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */
779 __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */
780 RoReg8 Reserved1[0x1];
781 __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */
782 __I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */
783 __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Count */
784 RoReg8 Reserved2[0x6];
785 __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x1B (R/W 8) COUNT8 Period */
786 __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 8) COUNT8 Compare and Capture */
787 RoReg8 Reserved3[0x11];
788 __IO TC_COUNT8_PERBUF_Type PERBUF; /**< \brief Offset: 0x2F (R/W 8) COUNT8 Period Buffer */
789 __IO TC_COUNT8_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 8) COUNT8 Compare and Capture Buffer */
790} TcCount8;
791#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
792
793/** \brief TC_COUNT16 hardware registers */
794#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
795typedef struct { /* 16-bit Counter Mode */
796 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
797 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
798 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
799 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */
800 __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
801 __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
802 __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
803 __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */
804 __IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */
805 __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */
806 RoReg8 Reserved1[0x1];
807 __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */
808 __I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */
809 __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 16) COUNT16 Count */
810 RoReg8 Reserved2[0x6];
811 __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 16) COUNT16 Compare and Capture */
812 RoReg8 Reserved3[0x10];
813 __IO TC_COUNT16_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 16) COUNT16 Compare and Capture Buffer */
814} TcCount16;
815#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
816
817/** \brief TC_COUNT32 hardware registers */
818#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
819typedef struct { /* 32-bit Counter Mode */
820 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
821 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
822 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
823 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */
824 __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
825 __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
826 __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
827 __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */
828 __IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */
829 __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */
830 RoReg8 Reserved1[0x1];
831 __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */
832 __I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */
833 __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 32) COUNT32 Count */
834 RoReg8 Reserved2[0x4];
835 __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 32) COUNT32 Compare and Capture */
836 RoReg8 Reserved3[0xC];
837 __IO TC_COUNT32_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 32) COUNT32 Compare and Capture Buffer */
838} TcCount32;
839#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
840
841#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
842typedef union {
843 TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */
844 TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */
845 TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */
846} Tc;
847#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
848
849/*@}*/
850
851#endif /* _SAME54_TC_COMPONENT_ */