Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM QSPI |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_QSPI_COMPONENT_ |
| 35 | #ifndef _HRI_QSPI_E54_H_INCLUDED_ |
| 36 | #define _HRI_QSPI_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_QSPI_CRITICAL_SECTIONS) |
| 46 | #define QSPI_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define QSPI_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define QSPI_CRITICAL_SECTION_ENTER() |
| 50 | #define QSPI_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint32_t hri_qspi_baud_reg_t; |
| 54 | typedef uint32_t hri_qspi_ctrla_reg_t; |
| 55 | typedef uint32_t hri_qspi_ctrlb_reg_t; |
| 56 | typedef uint32_t hri_qspi_instraddr_reg_t; |
| 57 | typedef uint32_t hri_qspi_instrctrl_reg_t; |
| 58 | typedef uint32_t hri_qspi_instrframe_reg_t; |
| 59 | typedef uint32_t hri_qspi_intenset_reg_t; |
| 60 | typedef uint32_t hri_qspi_intflag_reg_t; |
| 61 | typedef uint32_t hri_qspi_rxdata_reg_t; |
| 62 | typedef uint32_t hri_qspi_scrambctrl_reg_t; |
| 63 | typedef uint32_t hri_qspi_scrambkey_reg_t; |
| 64 | typedef uint32_t hri_qspi_status_reg_t; |
| 65 | typedef uint32_t hri_qspi_txdata_reg_t; |
| 66 | |
| 67 | static inline bool hri_qspi_get_INTFLAG_RXC_bit(const void *const hw) |
| 68 | { |
| 69 | return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_RXC) >> QSPI_INTFLAG_RXC_Pos; |
| 70 | } |
| 71 | |
| 72 | static inline void hri_qspi_clear_INTFLAG_RXC_bit(const void *const hw) |
| 73 | { |
| 74 | ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_RXC; |
| 75 | } |
| 76 | |
| 77 | static inline bool hri_qspi_get_INTFLAG_DRE_bit(const void *const hw) |
| 78 | { |
| 79 | return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_DRE) >> QSPI_INTFLAG_DRE_Pos; |
| 80 | } |
| 81 | |
| 82 | static inline void hri_qspi_clear_INTFLAG_DRE_bit(const void *const hw) |
| 83 | { |
| 84 | ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_DRE; |
| 85 | } |
| 86 | |
| 87 | static inline bool hri_qspi_get_INTFLAG_TXC_bit(const void *const hw) |
| 88 | { |
| 89 | return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_TXC) >> QSPI_INTFLAG_TXC_Pos; |
| 90 | } |
| 91 | |
| 92 | static inline void hri_qspi_clear_INTFLAG_TXC_bit(const void *const hw) |
| 93 | { |
| 94 | ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_TXC; |
| 95 | } |
| 96 | |
| 97 | static inline bool hri_qspi_get_INTFLAG_ERROR_bit(const void *const hw) |
| 98 | { |
| 99 | return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_ERROR) >> QSPI_INTFLAG_ERROR_Pos; |
| 100 | } |
| 101 | |
| 102 | static inline void hri_qspi_clear_INTFLAG_ERROR_bit(const void *const hw) |
| 103 | { |
| 104 | ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_ERROR; |
| 105 | } |
| 106 | |
| 107 | static inline bool hri_qspi_get_INTFLAG_CSRISE_bit(const void *const hw) |
| 108 | { |
| 109 | return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_CSRISE) >> QSPI_INTFLAG_CSRISE_Pos; |
| 110 | } |
| 111 | |
| 112 | static inline void hri_qspi_clear_INTFLAG_CSRISE_bit(const void *const hw) |
| 113 | { |
| 114 | ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_CSRISE; |
| 115 | } |
| 116 | |
| 117 | static inline bool hri_qspi_get_INTFLAG_INSTREND_bit(const void *const hw) |
| 118 | { |
| 119 | return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_INSTREND) >> QSPI_INTFLAG_INSTREND_Pos; |
| 120 | } |
| 121 | |
| 122 | static inline void hri_qspi_clear_INTFLAG_INSTREND_bit(const void *const hw) |
| 123 | { |
| 124 | ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_INSTREND; |
| 125 | } |
| 126 | |
| 127 | static inline bool hri_qspi_get_interrupt_RXC_bit(const void *const hw) |
| 128 | { |
| 129 | return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_RXC) >> QSPI_INTFLAG_RXC_Pos; |
| 130 | } |
| 131 | |
| 132 | static inline void hri_qspi_clear_interrupt_RXC_bit(const void *const hw) |
| 133 | { |
| 134 | ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_RXC; |
| 135 | } |
| 136 | |
| 137 | static inline bool hri_qspi_get_interrupt_DRE_bit(const void *const hw) |
| 138 | { |
| 139 | return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_DRE) >> QSPI_INTFLAG_DRE_Pos; |
| 140 | } |
| 141 | |
| 142 | static inline void hri_qspi_clear_interrupt_DRE_bit(const void *const hw) |
| 143 | { |
| 144 | ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_DRE; |
| 145 | } |
| 146 | |
| 147 | static inline bool hri_qspi_get_interrupt_TXC_bit(const void *const hw) |
| 148 | { |
| 149 | return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_TXC) >> QSPI_INTFLAG_TXC_Pos; |
| 150 | } |
| 151 | |
| 152 | static inline void hri_qspi_clear_interrupt_TXC_bit(const void *const hw) |
| 153 | { |
| 154 | ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_TXC; |
| 155 | } |
| 156 | |
| 157 | static inline bool hri_qspi_get_interrupt_ERROR_bit(const void *const hw) |
| 158 | { |
| 159 | return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_ERROR) >> QSPI_INTFLAG_ERROR_Pos; |
| 160 | } |
| 161 | |
| 162 | static inline void hri_qspi_clear_interrupt_ERROR_bit(const void *const hw) |
| 163 | { |
| 164 | ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_ERROR; |
| 165 | } |
| 166 | |
| 167 | static inline bool hri_qspi_get_interrupt_CSRISE_bit(const void *const hw) |
| 168 | { |
| 169 | return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_CSRISE) >> QSPI_INTFLAG_CSRISE_Pos; |
| 170 | } |
| 171 | |
| 172 | static inline void hri_qspi_clear_interrupt_CSRISE_bit(const void *const hw) |
| 173 | { |
| 174 | ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_CSRISE; |
| 175 | } |
| 176 | |
| 177 | static inline bool hri_qspi_get_interrupt_INSTREND_bit(const void *const hw) |
| 178 | { |
| 179 | return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_INSTREND) >> QSPI_INTFLAG_INSTREND_Pos; |
| 180 | } |
| 181 | |
| 182 | static inline void hri_qspi_clear_interrupt_INSTREND_bit(const void *const hw) |
| 183 | { |
| 184 | ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_INSTREND; |
| 185 | } |
| 186 | |
| 187 | static inline hri_qspi_intflag_reg_t hri_qspi_get_INTFLAG_reg(const void *const hw, hri_qspi_intflag_reg_t mask) |
| 188 | { |
| 189 | uint32_t tmp; |
| 190 | tmp = ((Qspi *)hw)->INTFLAG.reg; |
| 191 | tmp &= mask; |
| 192 | return tmp; |
| 193 | } |
| 194 | |
| 195 | static inline hri_qspi_intflag_reg_t hri_qspi_read_INTFLAG_reg(const void *const hw) |
| 196 | { |
| 197 | return ((Qspi *)hw)->INTFLAG.reg; |
| 198 | } |
| 199 | |
| 200 | static inline void hri_qspi_clear_INTFLAG_reg(const void *const hw, hri_qspi_intflag_reg_t mask) |
| 201 | { |
| 202 | ((Qspi *)hw)->INTFLAG.reg = mask; |
| 203 | } |
| 204 | |
| 205 | static inline void hri_qspi_set_INTEN_RXC_bit(const void *const hw) |
| 206 | { |
| 207 | ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_RXC; |
| 208 | } |
| 209 | |
| 210 | static inline bool hri_qspi_get_INTEN_RXC_bit(const void *const hw) |
| 211 | { |
| 212 | return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_RXC) >> QSPI_INTENSET_RXC_Pos; |
| 213 | } |
| 214 | |
| 215 | static inline void hri_qspi_write_INTEN_RXC_bit(const void *const hw, bool value) |
| 216 | { |
| 217 | if (value == 0x0) { |
| 218 | ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_RXC; |
| 219 | } else { |
| 220 | ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_RXC; |
| 221 | } |
| 222 | } |
| 223 | |
| 224 | static inline void hri_qspi_clear_INTEN_RXC_bit(const void *const hw) |
| 225 | { |
| 226 | ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_RXC; |
| 227 | } |
| 228 | |
| 229 | static inline void hri_qspi_set_INTEN_DRE_bit(const void *const hw) |
| 230 | { |
| 231 | ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_DRE; |
| 232 | } |
| 233 | |
| 234 | static inline bool hri_qspi_get_INTEN_DRE_bit(const void *const hw) |
| 235 | { |
| 236 | return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_DRE) >> QSPI_INTENSET_DRE_Pos; |
| 237 | } |
| 238 | |
| 239 | static inline void hri_qspi_write_INTEN_DRE_bit(const void *const hw, bool value) |
| 240 | { |
| 241 | if (value == 0x0) { |
| 242 | ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_DRE; |
| 243 | } else { |
| 244 | ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_DRE; |
| 245 | } |
| 246 | } |
| 247 | |
| 248 | static inline void hri_qspi_clear_INTEN_DRE_bit(const void *const hw) |
| 249 | { |
| 250 | ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_DRE; |
| 251 | } |
| 252 | |
| 253 | static inline void hri_qspi_set_INTEN_TXC_bit(const void *const hw) |
| 254 | { |
| 255 | ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_TXC; |
| 256 | } |
| 257 | |
| 258 | static inline bool hri_qspi_get_INTEN_TXC_bit(const void *const hw) |
| 259 | { |
| 260 | return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_TXC) >> QSPI_INTENSET_TXC_Pos; |
| 261 | } |
| 262 | |
| 263 | static inline void hri_qspi_write_INTEN_TXC_bit(const void *const hw, bool value) |
| 264 | { |
| 265 | if (value == 0x0) { |
| 266 | ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_TXC; |
| 267 | } else { |
| 268 | ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_TXC; |
| 269 | } |
| 270 | } |
| 271 | |
| 272 | static inline void hri_qspi_clear_INTEN_TXC_bit(const void *const hw) |
| 273 | { |
| 274 | ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_TXC; |
| 275 | } |
| 276 | |
| 277 | static inline void hri_qspi_set_INTEN_ERROR_bit(const void *const hw) |
| 278 | { |
| 279 | ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_ERROR; |
| 280 | } |
| 281 | |
| 282 | static inline bool hri_qspi_get_INTEN_ERROR_bit(const void *const hw) |
| 283 | { |
| 284 | return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_ERROR) >> QSPI_INTENSET_ERROR_Pos; |
| 285 | } |
| 286 | |
| 287 | static inline void hri_qspi_write_INTEN_ERROR_bit(const void *const hw, bool value) |
| 288 | { |
| 289 | if (value == 0x0) { |
| 290 | ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_ERROR; |
| 291 | } else { |
| 292 | ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_ERROR; |
| 293 | } |
| 294 | } |
| 295 | |
| 296 | static inline void hri_qspi_clear_INTEN_ERROR_bit(const void *const hw) |
| 297 | { |
| 298 | ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_ERROR; |
| 299 | } |
| 300 | |
| 301 | static inline void hri_qspi_set_INTEN_CSRISE_bit(const void *const hw) |
| 302 | { |
| 303 | ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_CSRISE; |
| 304 | } |
| 305 | |
| 306 | static inline bool hri_qspi_get_INTEN_CSRISE_bit(const void *const hw) |
| 307 | { |
| 308 | return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_CSRISE) >> QSPI_INTENSET_CSRISE_Pos; |
| 309 | } |
| 310 | |
| 311 | static inline void hri_qspi_write_INTEN_CSRISE_bit(const void *const hw, bool value) |
| 312 | { |
| 313 | if (value == 0x0) { |
| 314 | ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_CSRISE; |
| 315 | } else { |
| 316 | ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_CSRISE; |
| 317 | } |
| 318 | } |
| 319 | |
| 320 | static inline void hri_qspi_clear_INTEN_CSRISE_bit(const void *const hw) |
| 321 | { |
| 322 | ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_CSRISE; |
| 323 | } |
| 324 | |
| 325 | static inline void hri_qspi_set_INTEN_INSTREND_bit(const void *const hw) |
| 326 | { |
| 327 | ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_INSTREND; |
| 328 | } |
| 329 | |
| 330 | static inline bool hri_qspi_get_INTEN_INSTREND_bit(const void *const hw) |
| 331 | { |
| 332 | return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_INSTREND) >> QSPI_INTENSET_INSTREND_Pos; |
| 333 | } |
| 334 | |
| 335 | static inline void hri_qspi_write_INTEN_INSTREND_bit(const void *const hw, bool value) |
| 336 | { |
| 337 | if (value == 0x0) { |
| 338 | ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_INSTREND; |
| 339 | } else { |
| 340 | ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_INSTREND; |
| 341 | } |
| 342 | } |
| 343 | |
| 344 | static inline void hri_qspi_clear_INTEN_INSTREND_bit(const void *const hw) |
| 345 | { |
| 346 | ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_INSTREND; |
| 347 | } |
| 348 | |
| 349 | static inline void hri_qspi_set_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask) |
| 350 | { |
| 351 | ((Qspi *)hw)->INTENSET.reg = mask; |
| 352 | } |
| 353 | |
| 354 | static inline hri_qspi_intenset_reg_t hri_qspi_get_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask) |
| 355 | { |
| 356 | uint32_t tmp; |
| 357 | tmp = ((Qspi *)hw)->INTENSET.reg; |
| 358 | tmp &= mask; |
| 359 | return tmp; |
| 360 | } |
| 361 | |
| 362 | static inline hri_qspi_intenset_reg_t hri_qspi_read_INTEN_reg(const void *const hw) |
| 363 | { |
| 364 | return ((Qspi *)hw)->INTENSET.reg; |
| 365 | } |
| 366 | |
| 367 | static inline void hri_qspi_write_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t data) |
| 368 | { |
| 369 | ((Qspi *)hw)->INTENSET.reg = data; |
| 370 | ((Qspi *)hw)->INTENCLR.reg = ~data; |
| 371 | } |
| 372 | |
| 373 | static inline void hri_qspi_clear_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask) |
| 374 | { |
| 375 | ((Qspi *)hw)->INTENCLR.reg = mask; |
| 376 | } |
| 377 | |
| 378 | static inline hri_qspi_rxdata_reg_t hri_qspi_get_RXDATA_DATA_bf(const void *const hw, hri_qspi_rxdata_reg_t mask) |
| 379 | { |
| 380 | return (((Qspi *)hw)->RXDATA.reg & QSPI_RXDATA_DATA(mask)) >> QSPI_RXDATA_DATA_Pos; |
| 381 | } |
| 382 | |
| 383 | static inline hri_qspi_rxdata_reg_t hri_qspi_read_RXDATA_DATA_bf(const void *const hw) |
| 384 | { |
| 385 | return (((Qspi *)hw)->RXDATA.reg & QSPI_RXDATA_DATA_Msk) >> QSPI_RXDATA_DATA_Pos; |
| 386 | } |
| 387 | |
| 388 | static inline hri_qspi_rxdata_reg_t hri_qspi_get_RXDATA_reg(const void *const hw, hri_qspi_rxdata_reg_t mask) |
| 389 | { |
| 390 | uint32_t tmp; |
| 391 | tmp = ((Qspi *)hw)->RXDATA.reg; |
| 392 | tmp &= mask; |
| 393 | return tmp; |
| 394 | } |
| 395 | |
| 396 | static inline hri_qspi_rxdata_reg_t hri_qspi_read_RXDATA_reg(const void *const hw) |
| 397 | { |
| 398 | return ((Qspi *)hw)->RXDATA.reg; |
| 399 | } |
| 400 | |
| 401 | static inline bool hri_qspi_get_STATUS_ENABLE_bit(const void *const hw) |
| 402 | { |
| 403 | return (((Qspi *)hw)->STATUS.reg & QSPI_STATUS_ENABLE) >> QSPI_STATUS_ENABLE_Pos; |
| 404 | } |
| 405 | |
| 406 | static inline bool hri_qspi_get_STATUS_CSSTATUS_bit(const void *const hw) |
| 407 | { |
| 408 | return (((Qspi *)hw)->STATUS.reg & QSPI_STATUS_CSSTATUS) >> QSPI_STATUS_CSSTATUS_Pos; |
| 409 | } |
| 410 | |
| 411 | static inline hri_qspi_status_reg_t hri_qspi_get_STATUS_reg(const void *const hw, hri_qspi_status_reg_t mask) |
| 412 | { |
| 413 | uint32_t tmp; |
| 414 | tmp = ((Qspi *)hw)->STATUS.reg; |
| 415 | tmp &= mask; |
| 416 | return tmp; |
| 417 | } |
| 418 | |
| 419 | static inline hri_qspi_status_reg_t hri_qspi_read_STATUS_reg(const void *const hw) |
| 420 | { |
| 421 | return ((Qspi *)hw)->STATUS.reg; |
| 422 | } |
| 423 | |
| 424 | static inline void hri_qspi_set_CTRLA_SWRST_bit(const void *const hw) |
| 425 | { |
| 426 | QSPI_CRITICAL_SECTION_ENTER(); |
| 427 | ((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_SWRST; |
| 428 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 429 | } |
| 430 | |
| 431 | static inline bool hri_qspi_get_CTRLA_SWRST_bit(const void *const hw) |
| 432 | { |
| 433 | uint32_t tmp; |
| 434 | tmp = ((Qspi *)hw)->CTRLA.reg; |
| 435 | tmp = (tmp & QSPI_CTRLA_SWRST) >> QSPI_CTRLA_SWRST_Pos; |
| 436 | return (bool)tmp; |
| 437 | } |
| 438 | |
| 439 | static inline void hri_qspi_set_CTRLA_ENABLE_bit(const void *const hw) |
| 440 | { |
| 441 | QSPI_CRITICAL_SECTION_ENTER(); |
| 442 | ((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_ENABLE; |
| 443 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 444 | } |
| 445 | |
| 446 | static inline bool hri_qspi_get_CTRLA_ENABLE_bit(const void *const hw) |
| 447 | { |
| 448 | uint32_t tmp; |
| 449 | tmp = ((Qspi *)hw)->CTRLA.reg; |
| 450 | tmp = (tmp & QSPI_CTRLA_ENABLE) >> QSPI_CTRLA_ENABLE_Pos; |
| 451 | return (bool)tmp; |
| 452 | } |
| 453 | |
| 454 | static inline void hri_qspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value) |
| 455 | { |
| 456 | uint32_t tmp; |
| 457 | QSPI_CRITICAL_SECTION_ENTER(); |
| 458 | tmp = ((Qspi *)hw)->CTRLA.reg; |
| 459 | tmp &= ~QSPI_CTRLA_ENABLE; |
| 460 | tmp |= value << QSPI_CTRLA_ENABLE_Pos; |
| 461 | ((Qspi *)hw)->CTRLA.reg = tmp; |
| 462 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 463 | } |
| 464 | |
| 465 | static inline void hri_qspi_clear_CTRLA_ENABLE_bit(const void *const hw) |
| 466 | { |
| 467 | QSPI_CRITICAL_SECTION_ENTER(); |
| 468 | ((Qspi *)hw)->CTRLA.reg &= ~QSPI_CTRLA_ENABLE; |
| 469 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 470 | } |
| 471 | |
| 472 | static inline void hri_qspi_toggle_CTRLA_ENABLE_bit(const void *const hw) |
| 473 | { |
| 474 | QSPI_CRITICAL_SECTION_ENTER(); |
| 475 | ((Qspi *)hw)->CTRLA.reg ^= QSPI_CTRLA_ENABLE; |
| 476 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 477 | } |
| 478 | |
| 479 | static inline void hri_qspi_set_CTRLA_LASTXFER_bit(const void *const hw) |
| 480 | { |
| 481 | QSPI_CRITICAL_SECTION_ENTER(); |
| 482 | ((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_LASTXFER; |
| 483 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 484 | } |
| 485 | |
| 486 | static inline bool hri_qspi_get_CTRLA_LASTXFER_bit(const void *const hw) |
| 487 | { |
| 488 | uint32_t tmp; |
| 489 | tmp = ((Qspi *)hw)->CTRLA.reg; |
| 490 | tmp = (tmp & QSPI_CTRLA_LASTXFER) >> QSPI_CTRLA_LASTXFER_Pos; |
| 491 | return (bool)tmp; |
| 492 | } |
| 493 | |
| 494 | static inline void hri_qspi_write_CTRLA_LASTXFER_bit(const void *const hw, bool value) |
| 495 | { |
| 496 | uint32_t tmp; |
| 497 | QSPI_CRITICAL_SECTION_ENTER(); |
| 498 | tmp = ((Qspi *)hw)->CTRLA.reg; |
| 499 | tmp &= ~QSPI_CTRLA_LASTXFER; |
| 500 | tmp |= value << QSPI_CTRLA_LASTXFER_Pos; |
| 501 | ((Qspi *)hw)->CTRLA.reg = tmp; |
| 502 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 503 | } |
| 504 | |
| 505 | static inline void hri_qspi_clear_CTRLA_LASTXFER_bit(const void *const hw) |
| 506 | { |
| 507 | QSPI_CRITICAL_SECTION_ENTER(); |
| 508 | ((Qspi *)hw)->CTRLA.reg &= ~QSPI_CTRLA_LASTXFER; |
| 509 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 510 | } |
| 511 | |
| 512 | static inline void hri_qspi_toggle_CTRLA_LASTXFER_bit(const void *const hw) |
| 513 | { |
| 514 | QSPI_CRITICAL_SECTION_ENTER(); |
| 515 | ((Qspi *)hw)->CTRLA.reg ^= QSPI_CTRLA_LASTXFER; |
| 516 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 517 | } |
| 518 | |
| 519 | static inline void hri_qspi_set_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) |
| 520 | { |
| 521 | QSPI_CRITICAL_SECTION_ENTER(); |
| 522 | ((Qspi *)hw)->CTRLA.reg |= mask; |
| 523 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 524 | } |
| 525 | |
| 526 | static inline hri_qspi_ctrla_reg_t hri_qspi_get_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) |
| 527 | { |
| 528 | uint32_t tmp; |
| 529 | tmp = ((Qspi *)hw)->CTRLA.reg; |
| 530 | tmp &= mask; |
| 531 | return tmp; |
| 532 | } |
| 533 | |
| 534 | static inline void hri_qspi_write_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t data) |
| 535 | { |
| 536 | QSPI_CRITICAL_SECTION_ENTER(); |
| 537 | ((Qspi *)hw)->CTRLA.reg = data; |
| 538 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 539 | } |
| 540 | |
| 541 | static inline void hri_qspi_clear_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) |
| 542 | { |
| 543 | QSPI_CRITICAL_SECTION_ENTER(); |
| 544 | ((Qspi *)hw)->CTRLA.reg &= ~mask; |
| 545 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 546 | } |
| 547 | |
| 548 | static inline void hri_qspi_toggle_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) |
| 549 | { |
| 550 | QSPI_CRITICAL_SECTION_ENTER(); |
| 551 | ((Qspi *)hw)->CTRLA.reg ^= mask; |
| 552 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 553 | } |
| 554 | |
| 555 | static inline hri_qspi_ctrla_reg_t hri_qspi_read_CTRLA_reg(const void *const hw) |
| 556 | { |
| 557 | return ((Qspi *)hw)->CTRLA.reg; |
| 558 | } |
| 559 | |
| 560 | static inline void hri_qspi_set_CTRLB_MODE_bit(const void *const hw) |
| 561 | { |
| 562 | QSPI_CRITICAL_SECTION_ENTER(); |
| 563 | ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_MODE; |
| 564 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 565 | } |
| 566 | |
| 567 | static inline bool hri_qspi_get_CTRLB_MODE_bit(const void *const hw) |
| 568 | { |
| 569 | uint32_t tmp; |
| 570 | tmp = ((Qspi *)hw)->CTRLB.reg; |
| 571 | tmp = (tmp & QSPI_CTRLB_MODE) >> QSPI_CTRLB_MODE_Pos; |
| 572 | return (bool)tmp; |
| 573 | } |
| 574 | |
| 575 | static inline void hri_qspi_write_CTRLB_MODE_bit(const void *const hw, bool value) |
| 576 | { |
| 577 | uint32_t tmp; |
| 578 | QSPI_CRITICAL_SECTION_ENTER(); |
| 579 | tmp = ((Qspi *)hw)->CTRLB.reg; |
| 580 | tmp &= ~QSPI_CTRLB_MODE; |
| 581 | tmp |= value << QSPI_CTRLB_MODE_Pos; |
| 582 | ((Qspi *)hw)->CTRLB.reg = tmp; |
| 583 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 584 | } |
| 585 | |
| 586 | static inline void hri_qspi_clear_CTRLB_MODE_bit(const void *const hw) |
| 587 | { |
| 588 | QSPI_CRITICAL_SECTION_ENTER(); |
| 589 | ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_MODE; |
| 590 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 591 | } |
| 592 | |
| 593 | static inline void hri_qspi_toggle_CTRLB_MODE_bit(const void *const hw) |
| 594 | { |
| 595 | QSPI_CRITICAL_SECTION_ENTER(); |
| 596 | ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_MODE; |
| 597 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 598 | } |
| 599 | |
| 600 | static inline void hri_qspi_set_CTRLB_LOOPEN_bit(const void *const hw) |
| 601 | { |
| 602 | QSPI_CRITICAL_SECTION_ENTER(); |
| 603 | ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_LOOPEN; |
| 604 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 605 | } |
| 606 | |
| 607 | static inline bool hri_qspi_get_CTRLB_LOOPEN_bit(const void *const hw) |
| 608 | { |
| 609 | uint32_t tmp; |
| 610 | tmp = ((Qspi *)hw)->CTRLB.reg; |
| 611 | tmp = (tmp & QSPI_CTRLB_LOOPEN) >> QSPI_CTRLB_LOOPEN_Pos; |
| 612 | return (bool)tmp; |
| 613 | } |
| 614 | |
| 615 | static inline void hri_qspi_write_CTRLB_LOOPEN_bit(const void *const hw, bool value) |
| 616 | { |
| 617 | uint32_t tmp; |
| 618 | QSPI_CRITICAL_SECTION_ENTER(); |
| 619 | tmp = ((Qspi *)hw)->CTRLB.reg; |
| 620 | tmp &= ~QSPI_CTRLB_LOOPEN; |
| 621 | tmp |= value << QSPI_CTRLB_LOOPEN_Pos; |
| 622 | ((Qspi *)hw)->CTRLB.reg = tmp; |
| 623 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 624 | } |
| 625 | |
| 626 | static inline void hri_qspi_clear_CTRLB_LOOPEN_bit(const void *const hw) |
| 627 | { |
| 628 | QSPI_CRITICAL_SECTION_ENTER(); |
| 629 | ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_LOOPEN; |
| 630 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 631 | } |
| 632 | |
| 633 | static inline void hri_qspi_toggle_CTRLB_LOOPEN_bit(const void *const hw) |
| 634 | { |
| 635 | QSPI_CRITICAL_SECTION_ENTER(); |
| 636 | ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_LOOPEN; |
| 637 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 638 | } |
| 639 | |
| 640 | static inline void hri_qspi_set_CTRLB_WDRBT_bit(const void *const hw) |
| 641 | { |
| 642 | QSPI_CRITICAL_SECTION_ENTER(); |
| 643 | ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_WDRBT; |
| 644 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 645 | } |
| 646 | |
| 647 | static inline bool hri_qspi_get_CTRLB_WDRBT_bit(const void *const hw) |
| 648 | { |
| 649 | uint32_t tmp; |
| 650 | tmp = ((Qspi *)hw)->CTRLB.reg; |
| 651 | tmp = (tmp & QSPI_CTRLB_WDRBT) >> QSPI_CTRLB_WDRBT_Pos; |
| 652 | return (bool)tmp; |
| 653 | } |
| 654 | |
| 655 | static inline void hri_qspi_write_CTRLB_WDRBT_bit(const void *const hw, bool value) |
| 656 | { |
| 657 | uint32_t tmp; |
| 658 | QSPI_CRITICAL_SECTION_ENTER(); |
| 659 | tmp = ((Qspi *)hw)->CTRLB.reg; |
| 660 | tmp &= ~QSPI_CTRLB_WDRBT; |
| 661 | tmp |= value << QSPI_CTRLB_WDRBT_Pos; |
| 662 | ((Qspi *)hw)->CTRLB.reg = tmp; |
| 663 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 664 | } |
| 665 | |
| 666 | static inline void hri_qspi_clear_CTRLB_WDRBT_bit(const void *const hw) |
| 667 | { |
| 668 | QSPI_CRITICAL_SECTION_ENTER(); |
| 669 | ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_WDRBT; |
| 670 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 671 | } |
| 672 | |
| 673 | static inline void hri_qspi_toggle_CTRLB_WDRBT_bit(const void *const hw) |
| 674 | { |
| 675 | QSPI_CRITICAL_SECTION_ENTER(); |
| 676 | ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_WDRBT; |
| 677 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 678 | } |
| 679 | |
| 680 | static inline void hri_qspi_set_CTRLB_SMEMREG_bit(const void *const hw) |
| 681 | { |
| 682 | QSPI_CRITICAL_SECTION_ENTER(); |
| 683 | ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_SMEMREG; |
| 684 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 685 | } |
| 686 | |
| 687 | static inline bool hri_qspi_get_CTRLB_SMEMREG_bit(const void *const hw) |
| 688 | { |
| 689 | uint32_t tmp; |
| 690 | tmp = ((Qspi *)hw)->CTRLB.reg; |
| 691 | tmp = (tmp & QSPI_CTRLB_SMEMREG) >> QSPI_CTRLB_SMEMREG_Pos; |
| 692 | return (bool)tmp; |
| 693 | } |
| 694 | |
| 695 | static inline void hri_qspi_write_CTRLB_SMEMREG_bit(const void *const hw, bool value) |
| 696 | { |
| 697 | uint32_t tmp; |
| 698 | QSPI_CRITICAL_SECTION_ENTER(); |
| 699 | tmp = ((Qspi *)hw)->CTRLB.reg; |
| 700 | tmp &= ~QSPI_CTRLB_SMEMREG; |
| 701 | tmp |= value << QSPI_CTRLB_SMEMREG_Pos; |
| 702 | ((Qspi *)hw)->CTRLB.reg = tmp; |
| 703 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 704 | } |
| 705 | |
| 706 | static inline void hri_qspi_clear_CTRLB_SMEMREG_bit(const void *const hw) |
| 707 | { |
| 708 | QSPI_CRITICAL_SECTION_ENTER(); |
| 709 | ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_SMEMREG; |
| 710 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 711 | } |
| 712 | |
| 713 | static inline void hri_qspi_toggle_CTRLB_SMEMREG_bit(const void *const hw) |
| 714 | { |
| 715 | QSPI_CRITICAL_SECTION_ENTER(); |
| 716 | ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_SMEMREG; |
| 717 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 718 | } |
| 719 | |
| 720 | static inline void hri_qspi_set_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) |
| 721 | { |
| 722 | QSPI_CRITICAL_SECTION_ENTER(); |
| 723 | ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_CSMODE(mask); |
| 724 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 725 | } |
| 726 | |
| 727 | static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) |
| 728 | { |
| 729 | uint32_t tmp; |
| 730 | tmp = ((Qspi *)hw)->CTRLB.reg; |
| 731 | tmp = (tmp & QSPI_CTRLB_CSMODE(mask)) >> QSPI_CTRLB_CSMODE_Pos; |
| 732 | return tmp; |
| 733 | } |
| 734 | |
| 735 | static inline void hri_qspi_write_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) |
| 736 | { |
| 737 | uint32_t tmp; |
| 738 | QSPI_CRITICAL_SECTION_ENTER(); |
| 739 | tmp = ((Qspi *)hw)->CTRLB.reg; |
| 740 | tmp &= ~QSPI_CTRLB_CSMODE_Msk; |
| 741 | tmp |= QSPI_CTRLB_CSMODE(data); |
| 742 | ((Qspi *)hw)->CTRLB.reg = tmp; |
| 743 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 744 | } |
| 745 | |
| 746 | static inline void hri_qspi_clear_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) |
| 747 | { |
| 748 | QSPI_CRITICAL_SECTION_ENTER(); |
| 749 | ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_CSMODE(mask); |
| 750 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 751 | } |
| 752 | |
| 753 | static inline void hri_qspi_toggle_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) |
| 754 | { |
| 755 | QSPI_CRITICAL_SECTION_ENTER(); |
| 756 | ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_CSMODE(mask); |
| 757 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 758 | } |
| 759 | |
| 760 | static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_CSMODE_bf(const void *const hw) |
| 761 | { |
| 762 | uint32_t tmp; |
| 763 | tmp = ((Qspi *)hw)->CTRLB.reg; |
| 764 | tmp = (tmp & QSPI_CTRLB_CSMODE_Msk) >> QSPI_CTRLB_CSMODE_Pos; |
| 765 | return tmp; |
| 766 | } |
| 767 | |
| 768 | static inline void hri_qspi_set_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) |
| 769 | { |
| 770 | QSPI_CRITICAL_SECTION_ENTER(); |
| 771 | ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DATALEN(mask); |
| 772 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 773 | } |
| 774 | |
| 775 | static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) |
| 776 | { |
| 777 | uint32_t tmp; |
| 778 | tmp = ((Qspi *)hw)->CTRLB.reg; |
| 779 | tmp = (tmp & QSPI_CTRLB_DATALEN(mask)) >> QSPI_CTRLB_DATALEN_Pos; |
| 780 | return tmp; |
| 781 | } |
| 782 | |
| 783 | static inline void hri_qspi_write_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) |
| 784 | { |
| 785 | uint32_t tmp; |
| 786 | QSPI_CRITICAL_SECTION_ENTER(); |
| 787 | tmp = ((Qspi *)hw)->CTRLB.reg; |
| 788 | tmp &= ~QSPI_CTRLB_DATALEN_Msk; |
| 789 | tmp |= QSPI_CTRLB_DATALEN(data); |
| 790 | ((Qspi *)hw)->CTRLB.reg = tmp; |
| 791 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 792 | } |
| 793 | |
| 794 | static inline void hri_qspi_clear_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) |
| 795 | { |
| 796 | QSPI_CRITICAL_SECTION_ENTER(); |
| 797 | ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DATALEN(mask); |
| 798 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 799 | } |
| 800 | |
| 801 | static inline void hri_qspi_toggle_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) |
| 802 | { |
| 803 | QSPI_CRITICAL_SECTION_ENTER(); |
| 804 | ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DATALEN(mask); |
| 805 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 806 | } |
| 807 | |
| 808 | static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DATALEN_bf(const void *const hw) |
| 809 | { |
| 810 | uint32_t tmp; |
| 811 | tmp = ((Qspi *)hw)->CTRLB.reg; |
| 812 | tmp = (tmp & QSPI_CTRLB_DATALEN_Msk) >> QSPI_CTRLB_DATALEN_Pos; |
| 813 | return tmp; |
| 814 | } |
| 815 | |
| 816 | static inline void hri_qspi_set_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) |
| 817 | { |
| 818 | QSPI_CRITICAL_SECTION_ENTER(); |
| 819 | ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DLYBCT(mask); |
| 820 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 821 | } |
| 822 | |
| 823 | static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) |
| 824 | { |
| 825 | uint32_t tmp; |
| 826 | tmp = ((Qspi *)hw)->CTRLB.reg; |
| 827 | tmp = (tmp & QSPI_CTRLB_DLYBCT(mask)) >> QSPI_CTRLB_DLYBCT_Pos; |
| 828 | return tmp; |
| 829 | } |
| 830 | |
| 831 | static inline void hri_qspi_write_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) |
| 832 | { |
| 833 | uint32_t tmp; |
| 834 | QSPI_CRITICAL_SECTION_ENTER(); |
| 835 | tmp = ((Qspi *)hw)->CTRLB.reg; |
| 836 | tmp &= ~QSPI_CTRLB_DLYBCT_Msk; |
| 837 | tmp |= QSPI_CTRLB_DLYBCT(data); |
| 838 | ((Qspi *)hw)->CTRLB.reg = tmp; |
| 839 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 840 | } |
| 841 | |
| 842 | static inline void hri_qspi_clear_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) |
| 843 | { |
| 844 | QSPI_CRITICAL_SECTION_ENTER(); |
| 845 | ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DLYBCT(mask); |
| 846 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 847 | } |
| 848 | |
| 849 | static inline void hri_qspi_toggle_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) |
| 850 | { |
| 851 | QSPI_CRITICAL_SECTION_ENTER(); |
| 852 | ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DLYBCT(mask); |
| 853 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 854 | } |
| 855 | |
| 856 | static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DLYBCT_bf(const void *const hw) |
| 857 | { |
| 858 | uint32_t tmp; |
| 859 | tmp = ((Qspi *)hw)->CTRLB.reg; |
| 860 | tmp = (tmp & QSPI_CTRLB_DLYBCT_Msk) >> QSPI_CTRLB_DLYBCT_Pos; |
| 861 | return tmp; |
| 862 | } |
| 863 | |
| 864 | static inline void hri_qspi_set_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) |
| 865 | { |
| 866 | QSPI_CRITICAL_SECTION_ENTER(); |
| 867 | ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DLYCS(mask); |
| 868 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 869 | } |
| 870 | |
| 871 | static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) |
| 872 | { |
| 873 | uint32_t tmp; |
| 874 | tmp = ((Qspi *)hw)->CTRLB.reg; |
| 875 | tmp = (tmp & QSPI_CTRLB_DLYCS(mask)) >> QSPI_CTRLB_DLYCS_Pos; |
| 876 | return tmp; |
| 877 | } |
| 878 | |
| 879 | static inline void hri_qspi_write_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) |
| 880 | { |
| 881 | uint32_t tmp; |
| 882 | QSPI_CRITICAL_SECTION_ENTER(); |
| 883 | tmp = ((Qspi *)hw)->CTRLB.reg; |
| 884 | tmp &= ~QSPI_CTRLB_DLYCS_Msk; |
| 885 | tmp |= QSPI_CTRLB_DLYCS(data); |
| 886 | ((Qspi *)hw)->CTRLB.reg = tmp; |
| 887 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 888 | } |
| 889 | |
| 890 | static inline void hri_qspi_clear_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) |
| 891 | { |
| 892 | QSPI_CRITICAL_SECTION_ENTER(); |
| 893 | ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DLYCS(mask); |
| 894 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 895 | } |
| 896 | |
| 897 | static inline void hri_qspi_toggle_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) |
| 898 | { |
| 899 | QSPI_CRITICAL_SECTION_ENTER(); |
| 900 | ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DLYCS(mask); |
| 901 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 902 | } |
| 903 | |
| 904 | static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DLYCS_bf(const void *const hw) |
| 905 | { |
| 906 | uint32_t tmp; |
| 907 | tmp = ((Qspi *)hw)->CTRLB.reg; |
| 908 | tmp = (tmp & QSPI_CTRLB_DLYCS_Msk) >> QSPI_CTRLB_DLYCS_Pos; |
| 909 | return tmp; |
| 910 | } |
| 911 | |
| 912 | static inline void hri_qspi_set_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) |
| 913 | { |
| 914 | QSPI_CRITICAL_SECTION_ENTER(); |
| 915 | ((Qspi *)hw)->CTRLB.reg |= mask; |
| 916 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 917 | } |
| 918 | |
| 919 | static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) |
| 920 | { |
| 921 | uint32_t tmp; |
| 922 | tmp = ((Qspi *)hw)->CTRLB.reg; |
| 923 | tmp &= mask; |
| 924 | return tmp; |
| 925 | } |
| 926 | |
| 927 | static inline void hri_qspi_write_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t data) |
| 928 | { |
| 929 | QSPI_CRITICAL_SECTION_ENTER(); |
| 930 | ((Qspi *)hw)->CTRLB.reg = data; |
| 931 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 932 | } |
| 933 | |
| 934 | static inline void hri_qspi_clear_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) |
| 935 | { |
| 936 | QSPI_CRITICAL_SECTION_ENTER(); |
| 937 | ((Qspi *)hw)->CTRLB.reg &= ~mask; |
| 938 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 939 | } |
| 940 | |
| 941 | static inline void hri_qspi_toggle_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) |
| 942 | { |
| 943 | QSPI_CRITICAL_SECTION_ENTER(); |
| 944 | ((Qspi *)hw)->CTRLB.reg ^= mask; |
| 945 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 946 | } |
| 947 | |
| 948 | static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_reg(const void *const hw) |
| 949 | { |
| 950 | return ((Qspi *)hw)->CTRLB.reg; |
| 951 | } |
| 952 | |
| 953 | static inline void hri_qspi_set_BAUD_CPOL_bit(const void *const hw) |
| 954 | { |
| 955 | QSPI_CRITICAL_SECTION_ENTER(); |
| 956 | ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_CPOL; |
| 957 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 958 | } |
| 959 | |
| 960 | static inline bool hri_qspi_get_BAUD_CPOL_bit(const void *const hw) |
| 961 | { |
| 962 | uint32_t tmp; |
| 963 | tmp = ((Qspi *)hw)->BAUD.reg; |
| 964 | tmp = (tmp & QSPI_BAUD_CPOL) >> QSPI_BAUD_CPOL_Pos; |
| 965 | return (bool)tmp; |
| 966 | } |
| 967 | |
| 968 | static inline void hri_qspi_write_BAUD_CPOL_bit(const void *const hw, bool value) |
| 969 | { |
| 970 | uint32_t tmp; |
| 971 | QSPI_CRITICAL_SECTION_ENTER(); |
| 972 | tmp = ((Qspi *)hw)->BAUD.reg; |
| 973 | tmp &= ~QSPI_BAUD_CPOL; |
| 974 | tmp |= value << QSPI_BAUD_CPOL_Pos; |
| 975 | ((Qspi *)hw)->BAUD.reg = tmp; |
| 976 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 977 | } |
| 978 | |
| 979 | static inline void hri_qspi_clear_BAUD_CPOL_bit(const void *const hw) |
| 980 | { |
| 981 | QSPI_CRITICAL_SECTION_ENTER(); |
| 982 | ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_CPOL; |
| 983 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 984 | } |
| 985 | |
| 986 | static inline void hri_qspi_toggle_BAUD_CPOL_bit(const void *const hw) |
| 987 | { |
| 988 | QSPI_CRITICAL_SECTION_ENTER(); |
| 989 | ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_CPOL; |
| 990 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 991 | } |
| 992 | |
| 993 | static inline void hri_qspi_set_BAUD_CPHA_bit(const void *const hw) |
| 994 | { |
| 995 | QSPI_CRITICAL_SECTION_ENTER(); |
| 996 | ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_CPHA; |
| 997 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 998 | } |
| 999 | |
| 1000 | static inline bool hri_qspi_get_BAUD_CPHA_bit(const void *const hw) |
| 1001 | { |
| 1002 | uint32_t tmp; |
| 1003 | tmp = ((Qspi *)hw)->BAUD.reg; |
| 1004 | tmp = (tmp & QSPI_BAUD_CPHA) >> QSPI_BAUD_CPHA_Pos; |
| 1005 | return (bool)tmp; |
| 1006 | } |
| 1007 | |
| 1008 | static inline void hri_qspi_write_BAUD_CPHA_bit(const void *const hw, bool value) |
| 1009 | { |
| 1010 | uint32_t tmp; |
| 1011 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1012 | tmp = ((Qspi *)hw)->BAUD.reg; |
| 1013 | tmp &= ~QSPI_BAUD_CPHA; |
| 1014 | tmp |= value << QSPI_BAUD_CPHA_Pos; |
| 1015 | ((Qspi *)hw)->BAUD.reg = tmp; |
| 1016 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1017 | } |
| 1018 | |
| 1019 | static inline void hri_qspi_clear_BAUD_CPHA_bit(const void *const hw) |
| 1020 | { |
| 1021 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1022 | ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_CPHA; |
| 1023 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1024 | } |
| 1025 | |
| 1026 | static inline void hri_qspi_toggle_BAUD_CPHA_bit(const void *const hw) |
| 1027 | { |
| 1028 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1029 | ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_CPHA; |
| 1030 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1031 | } |
| 1032 | |
| 1033 | static inline void hri_qspi_set_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) |
| 1034 | { |
| 1035 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1036 | ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_BAUD(mask); |
| 1037 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1038 | } |
| 1039 | |
| 1040 | static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) |
| 1041 | { |
| 1042 | uint32_t tmp; |
| 1043 | tmp = ((Qspi *)hw)->BAUD.reg; |
| 1044 | tmp = (tmp & QSPI_BAUD_BAUD(mask)) >> QSPI_BAUD_BAUD_Pos; |
| 1045 | return tmp; |
| 1046 | } |
| 1047 | |
| 1048 | static inline void hri_qspi_write_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t data) |
| 1049 | { |
| 1050 | uint32_t tmp; |
| 1051 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1052 | tmp = ((Qspi *)hw)->BAUD.reg; |
| 1053 | tmp &= ~QSPI_BAUD_BAUD_Msk; |
| 1054 | tmp |= QSPI_BAUD_BAUD(data); |
| 1055 | ((Qspi *)hw)->BAUD.reg = tmp; |
| 1056 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1057 | } |
| 1058 | |
| 1059 | static inline void hri_qspi_clear_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) |
| 1060 | { |
| 1061 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1062 | ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_BAUD(mask); |
| 1063 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1064 | } |
| 1065 | |
| 1066 | static inline void hri_qspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) |
| 1067 | { |
| 1068 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1069 | ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_BAUD(mask); |
| 1070 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1071 | } |
| 1072 | |
| 1073 | static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_BAUD_bf(const void *const hw) |
| 1074 | { |
| 1075 | uint32_t tmp; |
| 1076 | tmp = ((Qspi *)hw)->BAUD.reg; |
| 1077 | tmp = (tmp & QSPI_BAUD_BAUD_Msk) >> QSPI_BAUD_BAUD_Pos; |
| 1078 | return tmp; |
| 1079 | } |
| 1080 | |
| 1081 | static inline void hri_qspi_set_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) |
| 1082 | { |
| 1083 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1084 | ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_DLYBS(mask); |
| 1085 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1086 | } |
| 1087 | |
| 1088 | static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) |
| 1089 | { |
| 1090 | uint32_t tmp; |
| 1091 | tmp = ((Qspi *)hw)->BAUD.reg; |
| 1092 | tmp = (tmp & QSPI_BAUD_DLYBS(mask)) >> QSPI_BAUD_DLYBS_Pos; |
| 1093 | return tmp; |
| 1094 | } |
| 1095 | |
| 1096 | static inline void hri_qspi_write_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t data) |
| 1097 | { |
| 1098 | uint32_t tmp; |
| 1099 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1100 | tmp = ((Qspi *)hw)->BAUD.reg; |
| 1101 | tmp &= ~QSPI_BAUD_DLYBS_Msk; |
| 1102 | tmp |= QSPI_BAUD_DLYBS(data); |
| 1103 | ((Qspi *)hw)->BAUD.reg = tmp; |
| 1104 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1105 | } |
| 1106 | |
| 1107 | static inline void hri_qspi_clear_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) |
| 1108 | { |
| 1109 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1110 | ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_DLYBS(mask); |
| 1111 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1112 | } |
| 1113 | |
| 1114 | static inline void hri_qspi_toggle_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) |
| 1115 | { |
| 1116 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1117 | ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_DLYBS(mask); |
| 1118 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1119 | } |
| 1120 | |
| 1121 | static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_DLYBS_bf(const void *const hw) |
| 1122 | { |
| 1123 | uint32_t tmp; |
| 1124 | tmp = ((Qspi *)hw)->BAUD.reg; |
| 1125 | tmp = (tmp & QSPI_BAUD_DLYBS_Msk) >> QSPI_BAUD_DLYBS_Pos; |
| 1126 | return tmp; |
| 1127 | } |
| 1128 | |
| 1129 | static inline void hri_qspi_set_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) |
| 1130 | { |
| 1131 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1132 | ((Qspi *)hw)->BAUD.reg |= mask; |
| 1133 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1134 | } |
| 1135 | |
| 1136 | static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) |
| 1137 | { |
| 1138 | uint32_t tmp; |
| 1139 | tmp = ((Qspi *)hw)->BAUD.reg; |
| 1140 | tmp &= mask; |
| 1141 | return tmp; |
| 1142 | } |
| 1143 | |
| 1144 | static inline void hri_qspi_write_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t data) |
| 1145 | { |
| 1146 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1147 | ((Qspi *)hw)->BAUD.reg = data; |
| 1148 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1149 | } |
| 1150 | |
| 1151 | static inline void hri_qspi_clear_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) |
| 1152 | { |
| 1153 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1154 | ((Qspi *)hw)->BAUD.reg &= ~mask; |
| 1155 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1156 | } |
| 1157 | |
| 1158 | static inline void hri_qspi_toggle_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) |
| 1159 | { |
| 1160 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1161 | ((Qspi *)hw)->BAUD.reg ^= mask; |
| 1162 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1163 | } |
| 1164 | |
| 1165 | static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_reg(const void *const hw) |
| 1166 | { |
| 1167 | return ((Qspi *)hw)->BAUD.reg; |
| 1168 | } |
| 1169 | |
| 1170 | static inline void hri_qspi_set_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask) |
| 1171 | { |
| 1172 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1173 | ((Qspi *)hw)->INSTRADDR.reg |= QSPI_INSTRADDR_ADDR(mask); |
| 1174 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1175 | } |
| 1176 | |
| 1177 | static inline hri_qspi_instraddr_reg_t hri_qspi_get_INSTRADDR_ADDR_bf(const void *const hw, |
| 1178 | hri_qspi_instraddr_reg_t mask) |
| 1179 | { |
| 1180 | uint32_t tmp; |
| 1181 | tmp = ((Qspi *)hw)->INSTRADDR.reg; |
| 1182 | tmp = (tmp & QSPI_INSTRADDR_ADDR(mask)) >> QSPI_INSTRADDR_ADDR_Pos; |
| 1183 | return tmp; |
| 1184 | } |
| 1185 | |
| 1186 | static inline void hri_qspi_write_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t data) |
| 1187 | { |
| 1188 | uint32_t tmp; |
| 1189 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1190 | tmp = ((Qspi *)hw)->INSTRADDR.reg; |
| 1191 | tmp &= ~QSPI_INSTRADDR_ADDR_Msk; |
| 1192 | tmp |= QSPI_INSTRADDR_ADDR(data); |
| 1193 | ((Qspi *)hw)->INSTRADDR.reg = tmp; |
| 1194 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1195 | } |
| 1196 | |
| 1197 | static inline void hri_qspi_clear_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask) |
| 1198 | { |
| 1199 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1200 | ((Qspi *)hw)->INSTRADDR.reg &= ~QSPI_INSTRADDR_ADDR(mask); |
| 1201 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1202 | } |
| 1203 | |
| 1204 | static inline void hri_qspi_toggle_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask) |
| 1205 | { |
| 1206 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1207 | ((Qspi *)hw)->INSTRADDR.reg ^= QSPI_INSTRADDR_ADDR(mask); |
| 1208 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1209 | } |
| 1210 | |
| 1211 | static inline hri_qspi_instraddr_reg_t hri_qspi_read_INSTRADDR_ADDR_bf(const void *const hw) |
| 1212 | { |
| 1213 | uint32_t tmp; |
| 1214 | tmp = ((Qspi *)hw)->INSTRADDR.reg; |
| 1215 | tmp = (tmp & QSPI_INSTRADDR_ADDR_Msk) >> QSPI_INSTRADDR_ADDR_Pos; |
| 1216 | return tmp; |
| 1217 | } |
| 1218 | |
| 1219 | static inline void hri_qspi_set_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) |
| 1220 | { |
| 1221 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1222 | ((Qspi *)hw)->INSTRADDR.reg |= mask; |
| 1223 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1224 | } |
| 1225 | |
| 1226 | static inline hri_qspi_instraddr_reg_t hri_qspi_get_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) |
| 1227 | { |
| 1228 | uint32_t tmp; |
| 1229 | tmp = ((Qspi *)hw)->INSTRADDR.reg; |
| 1230 | tmp &= mask; |
| 1231 | return tmp; |
| 1232 | } |
| 1233 | |
| 1234 | static inline void hri_qspi_write_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t data) |
| 1235 | { |
| 1236 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1237 | ((Qspi *)hw)->INSTRADDR.reg = data; |
| 1238 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1239 | } |
| 1240 | |
| 1241 | static inline void hri_qspi_clear_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) |
| 1242 | { |
| 1243 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1244 | ((Qspi *)hw)->INSTRADDR.reg &= ~mask; |
| 1245 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1246 | } |
| 1247 | |
| 1248 | static inline void hri_qspi_toggle_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) |
| 1249 | { |
| 1250 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1251 | ((Qspi *)hw)->INSTRADDR.reg ^= mask; |
| 1252 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1253 | } |
| 1254 | |
| 1255 | static inline hri_qspi_instraddr_reg_t hri_qspi_read_INSTRADDR_reg(const void *const hw) |
| 1256 | { |
| 1257 | return ((Qspi *)hw)->INSTRADDR.reg; |
| 1258 | } |
| 1259 | |
| 1260 | static inline void hri_qspi_set_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) |
| 1261 | { |
| 1262 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1263 | ((Qspi *)hw)->INSTRCTRL.reg |= QSPI_INSTRCTRL_INSTR(mask); |
| 1264 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1265 | } |
| 1266 | |
| 1267 | static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_INSTR_bf(const void *const hw, |
| 1268 | hri_qspi_instrctrl_reg_t mask) |
| 1269 | { |
| 1270 | uint32_t tmp; |
| 1271 | tmp = ((Qspi *)hw)->INSTRCTRL.reg; |
| 1272 | tmp = (tmp & QSPI_INSTRCTRL_INSTR(mask)) >> QSPI_INSTRCTRL_INSTR_Pos; |
| 1273 | return tmp; |
| 1274 | } |
| 1275 | |
| 1276 | static inline void hri_qspi_write_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t data) |
| 1277 | { |
| 1278 | uint32_t tmp; |
| 1279 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1280 | tmp = ((Qspi *)hw)->INSTRCTRL.reg; |
| 1281 | tmp &= ~QSPI_INSTRCTRL_INSTR_Msk; |
| 1282 | tmp |= QSPI_INSTRCTRL_INSTR(data); |
| 1283 | ((Qspi *)hw)->INSTRCTRL.reg = tmp; |
| 1284 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1285 | } |
| 1286 | |
| 1287 | static inline void hri_qspi_clear_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) |
| 1288 | { |
| 1289 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1290 | ((Qspi *)hw)->INSTRCTRL.reg &= ~QSPI_INSTRCTRL_INSTR(mask); |
| 1291 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1292 | } |
| 1293 | |
| 1294 | static inline void hri_qspi_toggle_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) |
| 1295 | { |
| 1296 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1297 | ((Qspi *)hw)->INSTRCTRL.reg ^= QSPI_INSTRCTRL_INSTR(mask); |
| 1298 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1299 | } |
| 1300 | |
| 1301 | static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_INSTR_bf(const void *const hw) |
| 1302 | { |
| 1303 | uint32_t tmp; |
| 1304 | tmp = ((Qspi *)hw)->INSTRCTRL.reg; |
| 1305 | tmp = (tmp & QSPI_INSTRCTRL_INSTR_Msk) >> QSPI_INSTRCTRL_INSTR_Pos; |
| 1306 | return tmp; |
| 1307 | } |
| 1308 | |
| 1309 | static inline void hri_qspi_set_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) |
| 1310 | { |
| 1311 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1312 | ((Qspi *)hw)->INSTRCTRL.reg |= QSPI_INSTRCTRL_OPTCODE(mask); |
| 1313 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1314 | } |
| 1315 | |
| 1316 | static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_OPTCODE_bf(const void *const hw, |
| 1317 | hri_qspi_instrctrl_reg_t mask) |
| 1318 | { |
| 1319 | uint32_t tmp; |
| 1320 | tmp = ((Qspi *)hw)->INSTRCTRL.reg; |
| 1321 | tmp = (tmp & QSPI_INSTRCTRL_OPTCODE(mask)) >> QSPI_INSTRCTRL_OPTCODE_Pos; |
| 1322 | return tmp; |
| 1323 | } |
| 1324 | |
| 1325 | static inline void hri_qspi_write_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t data) |
| 1326 | { |
| 1327 | uint32_t tmp; |
| 1328 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1329 | tmp = ((Qspi *)hw)->INSTRCTRL.reg; |
| 1330 | tmp &= ~QSPI_INSTRCTRL_OPTCODE_Msk; |
| 1331 | tmp |= QSPI_INSTRCTRL_OPTCODE(data); |
| 1332 | ((Qspi *)hw)->INSTRCTRL.reg = tmp; |
| 1333 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1334 | } |
| 1335 | |
| 1336 | static inline void hri_qspi_clear_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) |
| 1337 | { |
| 1338 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1339 | ((Qspi *)hw)->INSTRCTRL.reg &= ~QSPI_INSTRCTRL_OPTCODE(mask); |
| 1340 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1341 | } |
| 1342 | |
| 1343 | static inline void hri_qspi_toggle_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) |
| 1344 | { |
| 1345 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1346 | ((Qspi *)hw)->INSTRCTRL.reg ^= QSPI_INSTRCTRL_OPTCODE(mask); |
| 1347 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1348 | } |
| 1349 | |
| 1350 | static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_OPTCODE_bf(const void *const hw) |
| 1351 | { |
| 1352 | uint32_t tmp; |
| 1353 | tmp = ((Qspi *)hw)->INSTRCTRL.reg; |
| 1354 | tmp = (tmp & QSPI_INSTRCTRL_OPTCODE_Msk) >> QSPI_INSTRCTRL_OPTCODE_Pos; |
| 1355 | return tmp; |
| 1356 | } |
| 1357 | |
| 1358 | static inline void hri_qspi_set_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) |
| 1359 | { |
| 1360 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1361 | ((Qspi *)hw)->INSTRCTRL.reg |= mask; |
| 1362 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1363 | } |
| 1364 | |
| 1365 | static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) |
| 1366 | { |
| 1367 | uint32_t tmp; |
| 1368 | tmp = ((Qspi *)hw)->INSTRCTRL.reg; |
| 1369 | tmp &= mask; |
| 1370 | return tmp; |
| 1371 | } |
| 1372 | |
| 1373 | static inline void hri_qspi_write_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t data) |
| 1374 | { |
| 1375 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1376 | ((Qspi *)hw)->INSTRCTRL.reg = data; |
| 1377 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1378 | } |
| 1379 | |
| 1380 | static inline void hri_qspi_clear_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) |
| 1381 | { |
| 1382 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1383 | ((Qspi *)hw)->INSTRCTRL.reg &= ~mask; |
| 1384 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1385 | } |
| 1386 | |
| 1387 | static inline void hri_qspi_toggle_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) |
| 1388 | { |
| 1389 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1390 | ((Qspi *)hw)->INSTRCTRL.reg ^= mask; |
| 1391 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1392 | } |
| 1393 | |
| 1394 | static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_reg(const void *const hw) |
| 1395 | { |
| 1396 | return ((Qspi *)hw)->INSTRCTRL.reg; |
| 1397 | } |
| 1398 | |
| 1399 | static inline void hri_qspi_set_INSTRFRAME_INSTREN_bit(const void *const hw) |
| 1400 | { |
| 1401 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1402 | ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_INSTREN; |
| 1403 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1404 | } |
| 1405 | |
| 1406 | static inline bool hri_qspi_get_INSTRFRAME_INSTREN_bit(const void *const hw) |
| 1407 | { |
| 1408 | uint32_t tmp; |
| 1409 | tmp = ((Qspi *)hw)->INSTRFRAME.reg; |
| 1410 | tmp = (tmp & QSPI_INSTRFRAME_INSTREN) >> QSPI_INSTRFRAME_INSTREN_Pos; |
| 1411 | return (bool)tmp; |
| 1412 | } |
| 1413 | |
| 1414 | static inline void hri_qspi_write_INSTRFRAME_INSTREN_bit(const void *const hw, bool value) |
| 1415 | { |
| 1416 | uint32_t tmp; |
| 1417 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1418 | tmp = ((Qspi *)hw)->INSTRFRAME.reg; |
| 1419 | tmp &= ~QSPI_INSTRFRAME_INSTREN; |
| 1420 | tmp |= value << QSPI_INSTRFRAME_INSTREN_Pos; |
| 1421 | ((Qspi *)hw)->INSTRFRAME.reg = tmp; |
| 1422 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1423 | } |
| 1424 | |
| 1425 | static inline void hri_qspi_clear_INSTRFRAME_INSTREN_bit(const void *const hw) |
| 1426 | { |
| 1427 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1428 | ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_INSTREN; |
| 1429 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1430 | } |
| 1431 | |
| 1432 | static inline void hri_qspi_toggle_INSTRFRAME_INSTREN_bit(const void *const hw) |
| 1433 | { |
| 1434 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1435 | ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_INSTREN; |
| 1436 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1437 | } |
| 1438 | |
| 1439 | static inline void hri_qspi_set_INSTRFRAME_ADDREN_bit(const void *const hw) |
| 1440 | { |
| 1441 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1442 | ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_ADDREN; |
| 1443 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1444 | } |
| 1445 | |
| 1446 | static inline bool hri_qspi_get_INSTRFRAME_ADDREN_bit(const void *const hw) |
| 1447 | { |
| 1448 | uint32_t tmp; |
| 1449 | tmp = ((Qspi *)hw)->INSTRFRAME.reg; |
| 1450 | tmp = (tmp & QSPI_INSTRFRAME_ADDREN) >> QSPI_INSTRFRAME_ADDREN_Pos; |
| 1451 | return (bool)tmp; |
| 1452 | } |
| 1453 | |
| 1454 | static inline void hri_qspi_write_INSTRFRAME_ADDREN_bit(const void *const hw, bool value) |
| 1455 | { |
| 1456 | uint32_t tmp; |
| 1457 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1458 | tmp = ((Qspi *)hw)->INSTRFRAME.reg; |
| 1459 | tmp &= ~QSPI_INSTRFRAME_ADDREN; |
| 1460 | tmp |= value << QSPI_INSTRFRAME_ADDREN_Pos; |
| 1461 | ((Qspi *)hw)->INSTRFRAME.reg = tmp; |
| 1462 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1463 | } |
| 1464 | |
| 1465 | static inline void hri_qspi_clear_INSTRFRAME_ADDREN_bit(const void *const hw) |
| 1466 | { |
| 1467 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1468 | ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_ADDREN; |
| 1469 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1470 | } |
| 1471 | |
| 1472 | static inline void hri_qspi_toggle_INSTRFRAME_ADDREN_bit(const void *const hw) |
| 1473 | { |
| 1474 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1475 | ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_ADDREN; |
| 1476 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1477 | } |
| 1478 | |
| 1479 | static inline void hri_qspi_set_INSTRFRAME_OPTCODEEN_bit(const void *const hw) |
| 1480 | { |
| 1481 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1482 | ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_OPTCODEEN; |
| 1483 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1484 | } |
| 1485 | |
| 1486 | static inline bool hri_qspi_get_INSTRFRAME_OPTCODEEN_bit(const void *const hw) |
| 1487 | { |
| 1488 | uint32_t tmp; |
| 1489 | tmp = ((Qspi *)hw)->INSTRFRAME.reg; |
| 1490 | tmp = (tmp & QSPI_INSTRFRAME_OPTCODEEN) >> QSPI_INSTRFRAME_OPTCODEEN_Pos; |
| 1491 | return (bool)tmp; |
| 1492 | } |
| 1493 | |
| 1494 | static inline void hri_qspi_write_INSTRFRAME_OPTCODEEN_bit(const void *const hw, bool value) |
| 1495 | { |
| 1496 | uint32_t tmp; |
| 1497 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1498 | tmp = ((Qspi *)hw)->INSTRFRAME.reg; |
| 1499 | tmp &= ~QSPI_INSTRFRAME_OPTCODEEN; |
| 1500 | tmp |= value << QSPI_INSTRFRAME_OPTCODEEN_Pos; |
| 1501 | ((Qspi *)hw)->INSTRFRAME.reg = tmp; |
| 1502 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1503 | } |
| 1504 | |
| 1505 | static inline void hri_qspi_clear_INSTRFRAME_OPTCODEEN_bit(const void *const hw) |
| 1506 | { |
| 1507 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1508 | ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_OPTCODEEN; |
| 1509 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1510 | } |
| 1511 | |
| 1512 | static inline void hri_qspi_toggle_INSTRFRAME_OPTCODEEN_bit(const void *const hw) |
| 1513 | { |
| 1514 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1515 | ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_OPTCODEEN; |
| 1516 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1517 | } |
| 1518 | |
| 1519 | static inline void hri_qspi_set_INSTRFRAME_DATAEN_bit(const void *const hw) |
| 1520 | { |
| 1521 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1522 | ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DATAEN; |
| 1523 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1524 | } |
| 1525 | |
| 1526 | static inline bool hri_qspi_get_INSTRFRAME_DATAEN_bit(const void *const hw) |
| 1527 | { |
| 1528 | uint32_t tmp; |
| 1529 | tmp = ((Qspi *)hw)->INSTRFRAME.reg; |
| 1530 | tmp = (tmp & QSPI_INSTRFRAME_DATAEN) >> QSPI_INSTRFRAME_DATAEN_Pos; |
| 1531 | return (bool)tmp; |
| 1532 | } |
| 1533 | |
| 1534 | static inline void hri_qspi_write_INSTRFRAME_DATAEN_bit(const void *const hw, bool value) |
| 1535 | { |
| 1536 | uint32_t tmp; |
| 1537 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1538 | tmp = ((Qspi *)hw)->INSTRFRAME.reg; |
| 1539 | tmp &= ~QSPI_INSTRFRAME_DATAEN; |
| 1540 | tmp |= value << QSPI_INSTRFRAME_DATAEN_Pos; |
| 1541 | ((Qspi *)hw)->INSTRFRAME.reg = tmp; |
| 1542 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1543 | } |
| 1544 | |
| 1545 | static inline void hri_qspi_clear_INSTRFRAME_DATAEN_bit(const void *const hw) |
| 1546 | { |
| 1547 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1548 | ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DATAEN; |
| 1549 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1550 | } |
| 1551 | |
| 1552 | static inline void hri_qspi_toggle_INSTRFRAME_DATAEN_bit(const void *const hw) |
| 1553 | { |
| 1554 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1555 | ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DATAEN; |
| 1556 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1557 | } |
| 1558 | |
| 1559 | static inline void hri_qspi_set_INSTRFRAME_ADDRLEN_bit(const void *const hw) |
| 1560 | { |
| 1561 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1562 | ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_ADDRLEN; |
| 1563 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1564 | } |
| 1565 | |
| 1566 | static inline bool hri_qspi_get_INSTRFRAME_ADDRLEN_bit(const void *const hw) |
| 1567 | { |
| 1568 | uint32_t tmp; |
| 1569 | tmp = ((Qspi *)hw)->INSTRFRAME.reg; |
| 1570 | tmp = (tmp & QSPI_INSTRFRAME_ADDRLEN) >> QSPI_INSTRFRAME_ADDRLEN_Pos; |
| 1571 | return (bool)tmp; |
| 1572 | } |
| 1573 | |
| 1574 | static inline void hri_qspi_write_INSTRFRAME_ADDRLEN_bit(const void *const hw, bool value) |
| 1575 | { |
| 1576 | uint32_t tmp; |
| 1577 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1578 | tmp = ((Qspi *)hw)->INSTRFRAME.reg; |
| 1579 | tmp &= ~QSPI_INSTRFRAME_ADDRLEN; |
| 1580 | tmp |= value << QSPI_INSTRFRAME_ADDRLEN_Pos; |
| 1581 | ((Qspi *)hw)->INSTRFRAME.reg = tmp; |
| 1582 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1583 | } |
| 1584 | |
| 1585 | static inline void hri_qspi_clear_INSTRFRAME_ADDRLEN_bit(const void *const hw) |
| 1586 | { |
| 1587 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1588 | ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_ADDRLEN; |
| 1589 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1590 | } |
| 1591 | |
| 1592 | static inline void hri_qspi_toggle_INSTRFRAME_ADDRLEN_bit(const void *const hw) |
| 1593 | { |
| 1594 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1595 | ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_ADDRLEN; |
| 1596 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1597 | } |
| 1598 | |
| 1599 | static inline void hri_qspi_set_INSTRFRAME_CRMODE_bit(const void *const hw) |
| 1600 | { |
| 1601 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1602 | ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_CRMODE; |
| 1603 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1604 | } |
| 1605 | |
| 1606 | static inline bool hri_qspi_get_INSTRFRAME_CRMODE_bit(const void *const hw) |
| 1607 | { |
| 1608 | uint32_t tmp; |
| 1609 | tmp = ((Qspi *)hw)->INSTRFRAME.reg; |
| 1610 | tmp = (tmp & QSPI_INSTRFRAME_CRMODE) >> QSPI_INSTRFRAME_CRMODE_Pos; |
| 1611 | return (bool)tmp; |
| 1612 | } |
| 1613 | |
| 1614 | static inline void hri_qspi_write_INSTRFRAME_CRMODE_bit(const void *const hw, bool value) |
| 1615 | { |
| 1616 | uint32_t tmp; |
| 1617 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1618 | tmp = ((Qspi *)hw)->INSTRFRAME.reg; |
| 1619 | tmp &= ~QSPI_INSTRFRAME_CRMODE; |
| 1620 | tmp |= value << QSPI_INSTRFRAME_CRMODE_Pos; |
| 1621 | ((Qspi *)hw)->INSTRFRAME.reg = tmp; |
| 1622 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1623 | } |
| 1624 | |
| 1625 | static inline void hri_qspi_clear_INSTRFRAME_CRMODE_bit(const void *const hw) |
| 1626 | { |
| 1627 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1628 | ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_CRMODE; |
| 1629 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1630 | } |
| 1631 | |
| 1632 | static inline void hri_qspi_toggle_INSTRFRAME_CRMODE_bit(const void *const hw) |
| 1633 | { |
| 1634 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1635 | ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_CRMODE; |
| 1636 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1637 | } |
| 1638 | |
| 1639 | static inline void hri_qspi_set_INSTRFRAME_DDREN_bit(const void *const hw) |
| 1640 | { |
| 1641 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1642 | ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DDREN; |
| 1643 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1644 | } |
| 1645 | |
| 1646 | static inline bool hri_qspi_get_INSTRFRAME_DDREN_bit(const void *const hw) |
| 1647 | { |
| 1648 | uint32_t tmp; |
| 1649 | tmp = ((Qspi *)hw)->INSTRFRAME.reg; |
| 1650 | tmp = (tmp & QSPI_INSTRFRAME_DDREN) >> QSPI_INSTRFRAME_DDREN_Pos; |
| 1651 | return (bool)tmp; |
| 1652 | } |
| 1653 | |
| 1654 | static inline void hri_qspi_write_INSTRFRAME_DDREN_bit(const void *const hw, bool value) |
| 1655 | { |
| 1656 | uint32_t tmp; |
| 1657 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1658 | tmp = ((Qspi *)hw)->INSTRFRAME.reg; |
| 1659 | tmp &= ~QSPI_INSTRFRAME_DDREN; |
| 1660 | tmp |= value << QSPI_INSTRFRAME_DDREN_Pos; |
| 1661 | ((Qspi *)hw)->INSTRFRAME.reg = tmp; |
| 1662 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1663 | } |
| 1664 | |
| 1665 | static inline void hri_qspi_clear_INSTRFRAME_DDREN_bit(const void *const hw) |
| 1666 | { |
| 1667 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1668 | ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DDREN; |
| 1669 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1670 | } |
| 1671 | |
| 1672 | static inline void hri_qspi_toggle_INSTRFRAME_DDREN_bit(const void *const hw) |
| 1673 | { |
| 1674 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1675 | ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DDREN; |
| 1676 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1677 | } |
| 1678 | |
| 1679 | static inline void hri_qspi_set_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) |
| 1680 | { |
| 1681 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1682 | ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_WIDTH(mask); |
| 1683 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1684 | } |
| 1685 | |
| 1686 | static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_WIDTH_bf(const void *const hw, |
| 1687 | hri_qspi_instrframe_reg_t mask) |
| 1688 | { |
| 1689 | uint32_t tmp; |
| 1690 | tmp = ((Qspi *)hw)->INSTRFRAME.reg; |
| 1691 | tmp = (tmp & QSPI_INSTRFRAME_WIDTH(mask)) >> QSPI_INSTRFRAME_WIDTH_Pos; |
| 1692 | return tmp; |
| 1693 | } |
| 1694 | |
| 1695 | static inline void hri_qspi_write_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t data) |
| 1696 | { |
| 1697 | uint32_t tmp; |
| 1698 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1699 | tmp = ((Qspi *)hw)->INSTRFRAME.reg; |
| 1700 | tmp &= ~QSPI_INSTRFRAME_WIDTH_Msk; |
| 1701 | tmp |= QSPI_INSTRFRAME_WIDTH(data); |
| 1702 | ((Qspi *)hw)->INSTRFRAME.reg = tmp; |
| 1703 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1704 | } |
| 1705 | |
| 1706 | static inline void hri_qspi_clear_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) |
| 1707 | { |
| 1708 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1709 | ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_WIDTH(mask); |
| 1710 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1711 | } |
| 1712 | |
| 1713 | static inline void hri_qspi_toggle_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) |
| 1714 | { |
| 1715 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1716 | ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_WIDTH(mask); |
| 1717 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1718 | } |
| 1719 | |
| 1720 | static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_WIDTH_bf(const void *const hw) |
| 1721 | { |
| 1722 | uint32_t tmp; |
| 1723 | tmp = ((Qspi *)hw)->INSTRFRAME.reg; |
| 1724 | tmp = (tmp & QSPI_INSTRFRAME_WIDTH_Msk) >> QSPI_INSTRFRAME_WIDTH_Pos; |
| 1725 | return tmp; |
| 1726 | } |
| 1727 | |
| 1728 | static inline void hri_qspi_set_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) |
| 1729 | { |
| 1730 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1731 | ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_OPTCODELEN(mask); |
| 1732 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1733 | } |
| 1734 | |
| 1735 | static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_OPTCODELEN_bf(const void *const hw, |
| 1736 | hri_qspi_instrframe_reg_t mask) |
| 1737 | { |
| 1738 | uint32_t tmp; |
| 1739 | tmp = ((Qspi *)hw)->INSTRFRAME.reg; |
| 1740 | tmp = (tmp & QSPI_INSTRFRAME_OPTCODELEN(mask)) >> QSPI_INSTRFRAME_OPTCODELEN_Pos; |
| 1741 | return tmp; |
| 1742 | } |
| 1743 | |
| 1744 | static inline void hri_qspi_write_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t data) |
| 1745 | { |
| 1746 | uint32_t tmp; |
| 1747 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1748 | tmp = ((Qspi *)hw)->INSTRFRAME.reg; |
| 1749 | tmp &= ~QSPI_INSTRFRAME_OPTCODELEN_Msk; |
| 1750 | tmp |= QSPI_INSTRFRAME_OPTCODELEN(data); |
| 1751 | ((Qspi *)hw)->INSTRFRAME.reg = tmp; |
| 1752 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1753 | } |
| 1754 | |
| 1755 | static inline void hri_qspi_clear_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) |
| 1756 | { |
| 1757 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1758 | ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_OPTCODELEN(mask); |
| 1759 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1760 | } |
| 1761 | |
| 1762 | static inline void hri_qspi_toggle_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) |
| 1763 | { |
| 1764 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1765 | ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_OPTCODELEN(mask); |
| 1766 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1767 | } |
| 1768 | |
| 1769 | static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_OPTCODELEN_bf(const void *const hw) |
| 1770 | { |
| 1771 | uint32_t tmp; |
| 1772 | tmp = ((Qspi *)hw)->INSTRFRAME.reg; |
| 1773 | tmp = (tmp & QSPI_INSTRFRAME_OPTCODELEN_Msk) >> QSPI_INSTRFRAME_OPTCODELEN_Pos; |
| 1774 | return tmp; |
| 1775 | } |
| 1776 | |
| 1777 | static inline void hri_qspi_set_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) |
| 1778 | { |
| 1779 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1780 | ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_TFRTYPE(mask); |
| 1781 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1782 | } |
| 1783 | |
| 1784 | static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_TFRTYPE_bf(const void *const hw, |
| 1785 | hri_qspi_instrframe_reg_t mask) |
| 1786 | { |
| 1787 | uint32_t tmp; |
| 1788 | tmp = ((Qspi *)hw)->INSTRFRAME.reg; |
| 1789 | tmp = (tmp & QSPI_INSTRFRAME_TFRTYPE(mask)) >> QSPI_INSTRFRAME_TFRTYPE_Pos; |
| 1790 | return tmp; |
| 1791 | } |
| 1792 | |
| 1793 | static inline void hri_qspi_write_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t data) |
| 1794 | { |
| 1795 | uint32_t tmp; |
| 1796 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1797 | tmp = ((Qspi *)hw)->INSTRFRAME.reg; |
| 1798 | tmp &= ~QSPI_INSTRFRAME_TFRTYPE_Msk; |
| 1799 | tmp |= QSPI_INSTRFRAME_TFRTYPE(data); |
| 1800 | ((Qspi *)hw)->INSTRFRAME.reg = tmp; |
| 1801 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1802 | } |
| 1803 | |
| 1804 | static inline void hri_qspi_clear_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) |
| 1805 | { |
| 1806 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1807 | ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_TFRTYPE(mask); |
| 1808 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1809 | } |
| 1810 | |
| 1811 | static inline void hri_qspi_toggle_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) |
| 1812 | { |
| 1813 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1814 | ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_TFRTYPE(mask); |
| 1815 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1816 | } |
| 1817 | |
| 1818 | static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_TFRTYPE_bf(const void *const hw) |
| 1819 | { |
| 1820 | uint32_t tmp; |
| 1821 | tmp = ((Qspi *)hw)->INSTRFRAME.reg; |
| 1822 | tmp = (tmp & QSPI_INSTRFRAME_TFRTYPE_Msk) >> QSPI_INSTRFRAME_TFRTYPE_Pos; |
| 1823 | return tmp; |
| 1824 | } |
| 1825 | |
| 1826 | static inline void hri_qspi_set_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) |
| 1827 | { |
| 1828 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1829 | ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DUMMYLEN(mask); |
| 1830 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1831 | } |
| 1832 | |
| 1833 | static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_DUMMYLEN_bf(const void *const hw, |
| 1834 | hri_qspi_instrframe_reg_t mask) |
| 1835 | { |
| 1836 | uint32_t tmp; |
| 1837 | tmp = ((Qspi *)hw)->INSTRFRAME.reg; |
| 1838 | tmp = (tmp & QSPI_INSTRFRAME_DUMMYLEN(mask)) >> QSPI_INSTRFRAME_DUMMYLEN_Pos; |
| 1839 | return tmp; |
| 1840 | } |
| 1841 | |
| 1842 | static inline void hri_qspi_write_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t data) |
| 1843 | { |
| 1844 | uint32_t tmp; |
| 1845 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1846 | tmp = ((Qspi *)hw)->INSTRFRAME.reg; |
| 1847 | tmp &= ~QSPI_INSTRFRAME_DUMMYLEN_Msk; |
| 1848 | tmp |= QSPI_INSTRFRAME_DUMMYLEN(data); |
| 1849 | ((Qspi *)hw)->INSTRFRAME.reg = tmp; |
| 1850 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1851 | } |
| 1852 | |
| 1853 | static inline void hri_qspi_clear_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) |
| 1854 | { |
| 1855 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1856 | ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DUMMYLEN(mask); |
| 1857 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1858 | } |
| 1859 | |
| 1860 | static inline void hri_qspi_toggle_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) |
| 1861 | { |
| 1862 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1863 | ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DUMMYLEN(mask); |
| 1864 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1865 | } |
| 1866 | |
| 1867 | static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_DUMMYLEN_bf(const void *const hw) |
| 1868 | { |
| 1869 | uint32_t tmp; |
| 1870 | tmp = ((Qspi *)hw)->INSTRFRAME.reg; |
| 1871 | tmp = (tmp & QSPI_INSTRFRAME_DUMMYLEN_Msk) >> QSPI_INSTRFRAME_DUMMYLEN_Pos; |
| 1872 | return tmp; |
| 1873 | } |
| 1874 | |
| 1875 | static inline void hri_qspi_set_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask) |
| 1876 | { |
| 1877 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1878 | ((Qspi *)hw)->INSTRFRAME.reg |= mask; |
| 1879 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1880 | } |
| 1881 | |
| 1882 | static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_reg(const void *const hw, |
| 1883 | hri_qspi_instrframe_reg_t mask) |
| 1884 | { |
| 1885 | uint32_t tmp; |
| 1886 | tmp = ((Qspi *)hw)->INSTRFRAME.reg; |
| 1887 | tmp &= mask; |
| 1888 | return tmp; |
| 1889 | } |
| 1890 | |
| 1891 | static inline void hri_qspi_write_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t data) |
| 1892 | { |
| 1893 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1894 | ((Qspi *)hw)->INSTRFRAME.reg = data; |
| 1895 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1896 | } |
| 1897 | |
| 1898 | static inline void hri_qspi_clear_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask) |
| 1899 | { |
| 1900 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1901 | ((Qspi *)hw)->INSTRFRAME.reg &= ~mask; |
| 1902 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1903 | } |
| 1904 | |
| 1905 | static inline void hri_qspi_toggle_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask) |
| 1906 | { |
| 1907 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1908 | ((Qspi *)hw)->INSTRFRAME.reg ^= mask; |
| 1909 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1910 | } |
| 1911 | |
| 1912 | static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_reg(const void *const hw) |
| 1913 | { |
| 1914 | return ((Qspi *)hw)->INSTRFRAME.reg; |
| 1915 | } |
| 1916 | |
| 1917 | static inline void hri_qspi_set_SCRAMBCTRL_ENABLE_bit(const void *const hw) |
| 1918 | { |
| 1919 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1920 | ((Qspi *)hw)->SCRAMBCTRL.reg |= QSPI_SCRAMBCTRL_ENABLE; |
| 1921 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1922 | } |
| 1923 | |
| 1924 | static inline bool hri_qspi_get_SCRAMBCTRL_ENABLE_bit(const void *const hw) |
| 1925 | { |
| 1926 | uint32_t tmp; |
| 1927 | tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; |
| 1928 | tmp = (tmp & QSPI_SCRAMBCTRL_ENABLE) >> QSPI_SCRAMBCTRL_ENABLE_Pos; |
| 1929 | return (bool)tmp; |
| 1930 | } |
| 1931 | |
| 1932 | static inline void hri_qspi_write_SCRAMBCTRL_ENABLE_bit(const void *const hw, bool value) |
| 1933 | { |
| 1934 | uint32_t tmp; |
| 1935 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1936 | tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; |
| 1937 | tmp &= ~QSPI_SCRAMBCTRL_ENABLE; |
| 1938 | tmp |= value << QSPI_SCRAMBCTRL_ENABLE_Pos; |
| 1939 | ((Qspi *)hw)->SCRAMBCTRL.reg = tmp; |
| 1940 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1941 | } |
| 1942 | |
| 1943 | static inline void hri_qspi_clear_SCRAMBCTRL_ENABLE_bit(const void *const hw) |
| 1944 | { |
| 1945 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1946 | ((Qspi *)hw)->SCRAMBCTRL.reg &= ~QSPI_SCRAMBCTRL_ENABLE; |
| 1947 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1948 | } |
| 1949 | |
| 1950 | static inline void hri_qspi_toggle_SCRAMBCTRL_ENABLE_bit(const void *const hw) |
| 1951 | { |
| 1952 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1953 | ((Qspi *)hw)->SCRAMBCTRL.reg ^= QSPI_SCRAMBCTRL_ENABLE; |
| 1954 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1955 | } |
| 1956 | |
| 1957 | static inline void hri_qspi_set_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) |
| 1958 | { |
| 1959 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1960 | ((Qspi *)hw)->SCRAMBCTRL.reg |= QSPI_SCRAMBCTRL_RANDOMDIS; |
| 1961 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1962 | } |
| 1963 | |
| 1964 | static inline bool hri_qspi_get_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) |
| 1965 | { |
| 1966 | uint32_t tmp; |
| 1967 | tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; |
| 1968 | tmp = (tmp & QSPI_SCRAMBCTRL_RANDOMDIS) >> QSPI_SCRAMBCTRL_RANDOMDIS_Pos; |
| 1969 | return (bool)tmp; |
| 1970 | } |
| 1971 | |
| 1972 | static inline void hri_qspi_write_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw, bool value) |
| 1973 | { |
| 1974 | uint32_t tmp; |
| 1975 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1976 | tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; |
| 1977 | tmp &= ~QSPI_SCRAMBCTRL_RANDOMDIS; |
| 1978 | tmp |= value << QSPI_SCRAMBCTRL_RANDOMDIS_Pos; |
| 1979 | ((Qspi *)hw)->SCRAMBCTRL.reg = tmp; |
| 1980 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1981 | } |
| 1982 | |
| 1983 | static inline void hri_qspi_clear_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) |
| 1984 | { |
| 1985 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1986 | ((Qspi *)hw)->SCRAMBCTRL.reg &= ~QSPI_SCRAMBCTRL_RANDOMDIS; |
| 1987 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1988 | } |
| 1989 | |
| 1990 | static inline void hri_qspi_toggle_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) |
| 1991 | { |
| 1992 | QSPI_CRITICAL_SECTION_ENTER(); |
| 1993 | ((Qspi *)hw)->SCRAMBCTRL.reg ^= QSPI_SCRAMBCTRL_RANDOMDIS; |
| 1994 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 1995 | } |
| 1996 | |
| 1997 | static inline void hri_qspi_set_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask) |
| 1998 | { |
| 1999 | QSPI_CRITICAL_SECTION_ENTER(); |
| 2000 | ((Qspi *)hw)->SCRAMBCTRL.reg |= mask; |
| 2001 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 2002 | } |
| 2003 | |
| 2004 | static inline hri_qspi_scrambctrl_reg_t hri_qspi_get_SCRAMBCTRL_reg(const void *const hw, |
| 2005 | hri_qspi_scrambctrl_reg_t mask) |
| 2006 | { |
| 2007 | uint32_t tmp; |
| 2008 | tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; |
| 2009 | tmp &= mask; |
| 2010 | return tmp; |
| 2011 | } |
| 2012 | |
| 2013 | static inline void hri_qspi_write_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t data) |
| 2014 | { |
| 2015 | QSPI_CRITICAL_SECTION_ENTER(); |
| 2016 | ((Qspi *)hw)->SCRAMBCTRL.reg = data; |
| 2017 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 2018 | } |
| 2019 | |
| 2020 | static inline void hri_qspi_clear_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask) |
| 2021 | { |
| 2022 | QSPI_CRITICAL_SECTION_ENTER(); |
| 2023 | ((Qspi *)hw)->SCRAMBCTRL.reg &= ~mask; |
| 2024 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 2025 | } |
| 2026 | |
| 2027 | static inline void hri_qspi_toggle_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask) |
| 2028 | { |
| 2029 | QSPI_CRITICAL_SECTION_ENTER(); |
| 2030 | ((Qspi *)hw)->SCRAMBCTRL.reg ^= mask; |
| 2031 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 2032 | } |
| 2033 | |
| 2034 | static inline hri_qspi_scrambctrl_reg_t hri_qspi_read_SCRAMBCTRL_reg(const void *const hw) |
| 2035 | { |
| 2036 | return ((Qspi *)hw)->SCRAMBCTRL.reg; |
| 2037 | } |
| 2038 | |
| 2039 | static inline void hri_qspi_write_TXDATA_reg(const void *const hw, hri_qspi_txdata_reg_t data) |
| 2040 | { |
| 2041 | QSPI_CRITICAL_SECTION_ENTER(); |
| 2042 | ((Qspi *)hw)->TXDATA.reg = data; |
| 2043 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 2044 | } |
| 2045 | |
| 2046 | static inline void hri_qspi_write_SCRAMBKEY_reg(const void *const hw, hri_qspi_scrambkey_reg_t data) |
| 2047 | { |
| 2048 | QSPI_CRITICAL_SECTION_ENTER(); |
| 2049 | ((Qspi *)hw)->SCRAMBKEY.reg = data; |
| 2050 | QSPI_CRITICAL_SECTION_LEAVE(); |
| 2051 | } |
| 2052 | |
| 2053 | #ifdef __cplusplus |
| 2054 | } |
| 2055 | #endif |
| 2056 | |
| 2057 | #endif /* _HRI_QSPI_E54_H_INCLUDED */ |
| 2058 | #endif /* _SAME54_QSPI_COMPONENT_ */ |