Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
|
| 2 | * \file
|
| 3 | *
|
| 4 | * \brief Instance description for ADC1
|
| 5 | *
|
| 6 | * Copyright (c) 2019 Microchip Technology Inc.
|
| 7 | *
|
| 8 | * \asf_license_start
|
| 9 | *
|
| 10 | * \page License
|
| 11 | *
|
| 12 | * SPDX-License-Identifier: Apache-2.0
|
| 13 | *
|
| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
|
| 15 | * not use this file except in compliance with the License.
|
| 16 | * You may obtain a copy of the Licence at
|
| 17 | *
|
| 18 | * http://www.apache.org/licenses/LICENSE-2.0
|
| 19 | *
|
| 20 | * Unless required by applicable law or agreed to in writing, software
|
| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
| 23 | * See the License for the specific language governing permissions and
|
| 24 | * limitations under the License.
|
| 25 | *
|
| 26 | * \asf_license_stop
|
| 27 | *
|
| 28 | */
|
| 29 |
|
| 30 | #ifndef _SAME54_ADC1_INSTANCE_
|
| 31 | #define _SAME54_ADC1_INSTANCE_
|
| 32 |
|
| 33 | /* ========== Register definition for ADC1 peripheral ========== */
|
| 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
| 35 | #define REG_ADC1_CTRLA (0x43002000) /**< \brief (ADC1) Control A */
|
| 36 | #define REG_ADC1_EVCTRL (0x43002002) /**< \brief (ADC1) Event Control */
|
| 37 | #define REG_ADC1_DBGCTRL (0x43002003) /**< \brief (ADC1) Debug Control */
|
| 38 | #define REG_ADC1_INPUTCTRL (0x43002004) /**< \brief (ADC1) Input Control */
|
| 39 | #define REG_ADC1_CTRLB (0x43002006) /**< \brief (ADC1) Control B */
|
| 40 | #define REG_ADC1_REFCTRL (0x43002008) /**< \brief (ADC1) Reference Control */
|
| 41 | #define REG_ADC1_AVGCTRL (0x4300200A) /**< \brief (ADC1) Average Control */
|
| 42 | #define REG_ADC1_SAMPCTRL (0x4300200B) /**< \brief (ADC1) Sample Time Control */
|
| 43 | #define REG_ADC1_WINLT (0x4300200C) /**< \brief (ADC1) Window Monitor Lower Threshold */
|
| 44 | #define REG_ADC1_WINUT (0x4300200E) /**< \brief (ADC1) Window Monitor Upper Threshold */
|
| 45 | #define REG_ADC1_GAINCORR (0x43002010) /**< \brief (ADC1) Gain Correction */
|
| 46 | #define REG_ADC1_OFFSETCORR (0x43002012) /**< \brief (ADC1) Offset Correction */
|
| 47 | #define REG_ADC1_SWTRIG (0x43002014) /**< \brief (ADC1) Software Trigger */
|
| 48 | #define REG_ADC1_INTENCLR (0x4300202C) /**< \brief (ADC1) Interrupt Enable Clear */
|
| 49 | #define REG_ADC1_INTENSET (0x4300202D) /**< \brief (ADC1) Interrupt Enable Set */
|
| 50 | #define REG_ADC1_INTFLAG (0x4300202E) /**< \brief (ADC1) Interrupt Flag Status and Clear */
|
| 51 | #define REG_ADC1_STATUS (0x4300202F) /**< \brief (ADC1) Status */
|
| 52 | #define REG_ADC1_SYNCBUSY (0x43002030) /**< \brief (ADC1) Synchronization Busy */
|
| 53 | #define REG_ADC1_DSEQDATA (0x43002034) /**< \brief (ADC1) DMA Sequencial Data */
|
| 54 | #define REG_ADC1_DSEQCTRL (0x43002038) /**< \brief (ADC1) DMA Sequential Control */
|
| 55 | #define REG_ADC1_DSEQSTAT (0x4300203C) /**< \brief (ADC1) DMA Sequencial Status */
|
| 56 | #define REG_ADC1_RESULT (0x43002040) /**< \brief (ADC1) Result Conversion Value */
|
| 57 | #define REG_ADC1_RESS (0x43002044) /**< \brief (ADC1) Last Sample Result */
|
| 58 | #define REG_ADC1_CALIB (0x43002048) /**< \brief (ADC1) Calibration */
|
| 59 | #else
|
| 60 | #define REG_ADC1_CTRLA (*(RwReg16*)0x43002000UL) /**< \brief (ADC1) Control A */
|
| 61 | #define REG_ADC1_EVCTRL (*(RwReg8 *)0x43002002UL) /**< \brief (ADC1) Event Control */
|
| 62 | #define REG_ADC1_DBGCTRL (*(RwReg8 *)0x43002003UL) /**< \brief (ADC1) Debug Control */
|
| 63 | #define REG_ADC1_INPUTCTRL (*(RwReg16*)0x43002004UL) /**< \brief (ADC1) Input Control */
|
| 64 | #define REG_ADC1_CTRLB (*(RwReg16*)0x43002006UL) /**< \brief (ADC1) Control B */
|
| 65 | #define REG_ADC1_REFCTRL (*(RwReg8 *)0x43002008UL) /**< \brief (ADC1) Reference Control */
|
| 66 | #define REG_ADC1_AVGCTRL (*(RwReg8 *)0x4300200AUL) /**< \brief (ADC1) Average Control */
|
| 67 | #define REG_ADC1_SAMPCTRL (*(RwReg8 *)0x4300200BUL) /**< \brief (ADC1) Sample Time Control */
|
| 68 | #define REG_ADC1_WINLT (*(RwReg16*)0x4300200CUL) /**< \brief (ADC1) Window Monitor Lower Threshold */
|
| 69 | #define REG_ADC1_WINUT (*(RwReg16*)0x4300200EUL) /**< \brief (ADC1) Window Monitor Upper Threshold */
|
| 70 | #define REG_ADC1_GAINCORR (*(RwReg16*)0x43002010UL) /**< \brief (ADC1) Gain Correction */
|
| 71 | #define REG_ADC1_OFFSETCORR (*(RwReg16*)0x43002012UL) /**< \brief (ADC1) Offset Correction */
|
| 72 | #define REG_ADC1_SWTRIG (*(RwReg8 *)0x43002014UL) /**< \brief (ADC1) Software Trigger */
|
| 73 | #define REG_ADC1_INTENCLR (*(RwReg8 *)0x4300202CUL) /**< \brief (ADC1) Interrupt Enable Clear */
|
| 74 | #define REG_ADC1_INTENSET (*(RwReg8 *)0x4300202DUL) /**< \brief (ADC1) Interrupt Enable Set */
|
| 75 | #define REG_ADC1_INTFLAG (*(RwReg8 *)0x4300202EUL) /**< \brief (ADC1) Interrupt Flag Status and Clear */
|
| 76 | #define REG_ADC1_STATUS (*(RoReg8 *)0x4300202FUL) /**< \brief (ADC1) Status */
|
| 77 | #define REG_ADC1_SYNCBUSY (*(RoReg *)0x43002030UL) /**< \brief (ADC1) Synchronization Busy */
|
| 78 | #define REG_ADC1_DSEQDATA (*(WoReg *)0x43002034UL) /**< \brief (ADC1) DMA Sequencial Data */
|
| 79 | #define REG_ADC1_DSEQCTRL (*(RwReg *)0x43002038UL) /**< \brief (ADC1) DMA Sequential Control */
|
| 80 | #define REG_ADC1_DSEQSTAT (*(RoReg *)0x4300203CUL) /**< \brief (ADC1) DMA Sequencial Status */
|
| 81 | #define REG_ADC1_RESULT (*(RoReg16*)0x43002040UL) /**< \brief (ADC1) Result Conversion Value */
|
| 82 | #define REG_ADC1_RESS (*(RoReg16*)0x43002044UL) /**< \brief (ADC1) Last Sample Result */
|
| 83 | #define REG_ADC1_CALIB (*(RwReg16*)0x43002048UL) /**< \brief (ADC1) Calibration */
|
| 84 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
| 85 |
|
| 86 | /* ========== Instance parameters for ADC1 peripheral ========== */
|
| 87 | #define ADC1_BANDGAP 27 // MUXPOS value to select BANDGAP
|
| 88 | #define ADC1_CTAT 29 // MUXPOS value to select CTAT
|
| 89 | #define ADC1_DMAC_ID_RESRDY 70 // Index of DMA RESRDY trigger
|
| 90 | #define ADC1_DMAC_ID_SEQ 71 // Index of DMA SEQ trigger
|
| 91 | #define ADC1_EXTCHANNEL_MSB 15 // Number of external channels
|
| 92 | #define ADC1_GCLK_ID 41 // Index of Generic Clock
|
| 93 | #define ADC1_MASTER_SLAVE_MODE 2 // ADC Master/Slave Mode
|
| 94 | #define ADC1_OPAMP2 0 // MUXPOS value to select OPAMP2
|
| 95 | #define ADC1_OPAMP01 0 // MUXPOS value to select OPAMP01
|
| 96 | #define ADC1_PTAT 28 // MUXPOS value to select PTAT
|
| 97 | #define ADC1_TOUCH_IMPLEMENTED 0 // TOUCH implemented or not
|
| 98 | #define ADC1_TOUCH_LINES_NUM 1 // Number of touch lines
|
| 99 |
|
| 100 | #endif /* _SAME54_ADC1_INSTANCE_ */
|