Kévin Redon | f041136 | 2019-06-06 17:42:44 +0200 | [diff] [blame] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Component description for PM
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| 5 | *
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| 6 | * Copyright (c) 2019 Microchip Technology Inc.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * SPDX-License-Identifier: Apache-2.0
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| 13 | *
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| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may
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| 15 | * not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the Licence at
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| 17 | *
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| 18 | * http://www.apache.org/licenses/LICENSE-2.0
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | * \asf_license_stop
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| 27 | *
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| 28 | */
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| 29 |
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| 30 | #ifndef _SAME54_PM_COMPONENT_
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| 31 | #define _SAME54_PM_COMPONENT_
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| 32 |
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| 33 | /* ========================================================================== */
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| 34 | /** SOFTWARE API DEFINITION FOR PM */
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| 35 | /* ========================================================================== */
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| 36 | /** \addtogroup SAME54_PM Power Manager */
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| 37 | /*@{*/
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| 38 |
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| 39 | #define PM_U2406
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| 40 | #define REV_PM 0x100
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| 41 |
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| 42 | /* -------- PM_CTRLA : (PM Offset: 0x00) (R/W 8) Control A -------- */
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| 43 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 44 | typedef union {
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| 45 | struct {
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| 46 | uint8_t :2; /*!< bit: 0.. 1 Reserved */
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| 47 | uint8_t IORET:1; /*!< bit: 2 I/O Retention */
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| 48 | uint8_t :5; /*!< bit: 3.. 7 Reserved */
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| 49 | } bit; /*!< Structure used for bit access */
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| 50 | uint8_t reg; /*!< Type used for register access */
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| 51 | } PM_CTRLA_Type;
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| 52 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 53 |
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| 54 | #define PM_CTRLA_OFFSET 0x00 /**< \brief (PM_CTRLA offset) Control A */
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| 55 | #define PM_CTRLA_RESETVALUE _U_(0x00) /**< \brief (PM_CTRLA reset_value) Control A */
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| 56 |
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| 57 | #define PM_CTRLA_IORET_Pos 2 /**< \brief (PM_CTRLA) I/O Retention */
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| 58 | #define PM_CTRLA_IORET (_U_(0x1) << PM_CTRLA_IORET_Pos)
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| 59 | #define PM_CTRLA_MASK _U_(0x04) /**< \brief (PM_CTRLA) MASK Register */
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| 60 |
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| 61 | /* -------- PM_SLEEPCFG : (PM Offset: 0x01) (R/W 8) Sleep Configuration -------- */
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| 62 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 63 | typedef union {
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| 64 | struct {
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| 65 | uint8_t SLEEPMODE:3; /*!< bit: 0.. 2 Sleep Mode */
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| 66 | uint8_t :5; /*!< bit: 3.. 7 Reserved */
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| 67 | } bit; /*!< Structure used for bit access */
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| 68 | uint8_t reg; /*!< Type used for register access */
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| 69 | } PM_SLEEPCFG_Type;
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| 70 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 71 |
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| 72 | #define PM_SLEEPCFG_OFFSET 0x01 /**< \brief (PM_SLEEPCFG offset) Sleep Configuration */
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| 73 | #define PM_SLEEPCFG_RESETVALUE _U_(0x02) /**< \brief (PM_SLEEPCFG reset_value) Sleep Configuration */
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| 74 |
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| 75 | #define PM_SLEEPCFG_SLEEPMODE_Pos 0 /**< \brief (PM_SLEEPCFG) Sleep Mode */
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| 76 | #define PM_SLEEPCFG_SLEEPMODE_Msk (_U_(0x7) << PM_SLEEPCFG_SLEEPMODE_Pos)
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| 77 | #define PM_SLEEPCFG_SLEEPMODE(value) (PM_SLEEPCFG_SLEEPMODE_Msk & ((value) << PM_SLEEPCFG_SLEEPMODE_Pos))
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| 78 | #define PM_SLEEPCFG_SLEEPMODE_IDLE0_Val _U_(0x0) /**< \brief (PM_SLEEPCFG) CPU clock is OFF */
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| 79 | #define PM_SLEEPCFG_SLEEPMODE_IDLE1_Val _U_(0x1) /**< \brief (PM_SLEEPCFG) AHB clock is OFF */
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| 80 | #define PM_SLEEPCFG_SLEEPMODE_IDLE2_Val _U_(0x2) /**< \brief (PM_SLEEPCFG) APB clock are OFF */
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| 81 | #define PM_SLEEPCFG_SLEEPMODE_STANDBY_Val _U_(0x4) /**< \brief (PM_SLEEPCFG) All Clocks are OFF */
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| 82 | #define PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val _U_(0x5) /**< \brief (PM_SLEEPCFG) Backup domain is ON as well as some PDRAMs */
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| 83 | #define PM_SLEEPCFG_SLEEPMODE_BACKUP_Val _U_(0x6) /**< \brief (PM_SLEEPCFG) Only Backup domain is powered ON */
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| 84 | #define PM_SLEEPCFG_SLEEPMODE_OFF_Val _U_(0x7) /**< \brief (PM_SLEEPCFG) All power domains are powered OFF */
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| 85 | #define PM_SLEEPCFG_SLEEPMODE_IDLE0 (PM_SLEEPCFG_SLEEPMODE_IDLE0_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
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| 86 | #define PM_SLEEPCFG_SLEEPMODE_IDLE1 (PM_SLEEPCFG_SLEEPMODE_IDLE1_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
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| 87 | #define PM_SLEEPCFG_SLEEPMODE_IDLE2 (PM_SLEEPCFG_SLEEPMODE_IDLE2_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
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| 88 | #define PM_SLEEPCFG_SLEEPMODE_STANDBY (PM_SLEEPCFG_SLEEPMODE_STANDBY_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
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| 89 | #define PM_SLEEPCFG_SLEEPMODE_HIBERNATE (PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
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| 90 | #define PM_SLEEPCFG_SLEEPMODE_BACKUP (PM_SLEEPCFG_SLEEPMODE_BACKUP_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
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| 91 | #define PM_SLEEPCFG_SLEEPMODE_OFF (PM_SLEEPCFG_SLEEPMODE_OFF_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
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| 92 | #define PM_SLEEPCFG_MASK _U_(0x07) /**< \brief (PM_SLEEPCFG) MASK Register */
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| 93 |
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| 94 | /* -------- PM_INTENCLR : (PM Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
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| 95 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 96 | typedef union {
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| 97 | struct {
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| 98 | uint8_t SLEEPRDY:1; /*!< bit: 0 Sleep Mode Entry Ready Enable */
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| 99 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
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| 100 | } bit; /*!< Structure used for bit access */
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| 101 | uint8_t reg; /*!< Type used for register access */
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| 102 | } PM_INTENCLR_Type;
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| 103 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 104 |
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| 105 | #define PM_INTENCLR_OFFSET 0x04 /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */
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| 106 | #define PM_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */
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| 107 |
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| 108 | #define PM_INTENCLR_SLEEPRDY_Pos 0 /**< \brief (PM_INTENCLR) Sleep Mode Entry Ready Enable */
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| 109 | #define PM_INTENCLR_SLEEPRDY (_U_(0x1) << PM_INTENCLR_SLEEPRDY_Pos)
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| 110 | #define PM_INTENCLR_MASK _U_(0x01) /**< \brief (PM_INTENCLR) MASK Register */
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| 111 |
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| 112 | /* -------- PM_INTENSET : (PM Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
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| 113 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 114 | typedef union {
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| 115 | struct {
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| 116 | uint8_t SLEEPRDY:1; /*!< bit: 0 Sleep Mode Entry Ready Enable */
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| 117 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
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| 118 | } bit; /*!< Structure used for bit access */
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| 119 | uint8_t reg; /*!< Type used for register access */
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| 120 | } PM_INTENSET_Type;
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| 121 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 122 |
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| 123 | #define PM_INTENSET_OFFSET 0x05 /**< \brief (PM_INTENSET offset) Interrupt Enable Set */
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| 124 | #define PM_INTENSET_RESETVALUE _U_(0x00) /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */
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| 125 |
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| 126 | #define PM_INTENSET_SLEEPRDY_Pos 0 /**< \brief (PM_INTENSET) Sleep Mode Entry Ready Enable */
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| 127 | #define PM_INTENSET_SLEEPRDY (_U_(0x1) << PM_INTENSET_SLEEPRDY_Pos)
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| 128 | #define PM_INTENSET_MASK _U_(0x01) /**< \brief (PM_INTENSET) MASK Register */
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| 129 |
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| 130 | /* -------- PM_INTFLAG : (PM Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
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| 131 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 132 | typedef union { // __I to avoid read-modify-write on write-to-clear register
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| 133 | struct {
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| 134 | __I uint8_t SLEEPRDY:1; /*!< bit: 0 Sleep Mode Entry Ready */
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| 135 | __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
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| 136 | } bit; /*!< Structure used for bit access */
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| 137 | uint8_t reg; /*!< Type used for register access */
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| 138 | } PM_INTFLAG_Type;
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| 139 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 140 |
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| 141 | #define PM_INTFLAG_OFFSET 0x06 /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */
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| 142 | #define PM_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */
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| 143 |
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| 144 | #define PM_INTFLAG_SLEEPRDY_Pos 0 /**< \brief (PM_INTFLAG) Sleep Mode Entry Ready */
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| 145 | #define PM_INTFLAG_SLEEPRDY (_U_(0x1) << PM_INTFLAG_SLEEPRDY_Pos)
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| 146 | #define PM_INTFLAG_MASK _U_(0x01) /**< \brief (PM_INTFLAG) MASK Register */
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| 147 |
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| 148 | /* -------- PM_STDBYCFG : (PM Offset: 0x08) (R/W 8) Standby Configuration -------- */
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| 149 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 150 | typedef union {
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| 151 | struct {
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| 152 | uint8_t RAMCFG:2; /*!< bit: 0.. 1 Ram Configuration */
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| 153 | uint8_t :2; /*!< bit: 2.. 3 Reserved */
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| 154 | uint8_t FASTWKUP:2; /*!< bit: 4.. 5 Fast Wakeup */
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| 155 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
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| 156 | } bit; /*!< Structure used for bit access */
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| 157 | uint8_t reg; /*!< Type used for register access */
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| 158 | } PM_STDBYCFG_Type;
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| 159 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 160 |
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| 161 | #define PM_STDBYCFG_OFFSET 0x08 /**< \brief (PM_STDBYCFG offset) Standby Configuration */
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| 162 | #define PM_STDBYCFG_RESETVALUE _U_(0x00) /**< \brief (PM_STDBYCFG reset_value) Standby Configuration */
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| 163 |
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| 164 | #define PM_STDBYCFG_RAMCFG_Pos 0 /**< \brief (PM_STDBYCFG) Ram Configuration */
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| 165 | #define PM_STDBYCFG_RAMCFG_Msk (_U_(0x3) << PM_STDBYCFG_RAMCFG_Pos)
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| 166 | #define PM_STDBYCFG_RAMCFG(value) (PM_STDBYCFG_RAMCFG_Msk & ((value) << PM_STDBYCFG_RAMCFG_Pos))
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| 167 | #define PM_STDBYCFG_RAMCFG_RET_Val _U_(0x0) /**< \brief (PM_STDBYCFG) All the RAMs are retained */
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| 168 | #define PM_STDBYCFG_RAMCFG_PARTIAL_Val _U_(0x1) /**< \brief (PM_STDBYCFG) Only the first 32K bytes are retained */
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| 169 | #define PM_STDBYCFG_RAMCFG_OFF_Val _U_(0x2) /**< \brief (PM_STDBYCFG) All the RAMs are OFF */
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| 170 | #define PM_STDBYCFG_RAMCFG_RET (PM_STDBYCFG_RAMCFG_RET_Val << PM_STDBYCFG_RAMCFG_Pos)
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| 171 | #define PM_STDBYCFG_RAMCFG_PARTIAL (PM_STDBYCFG_RAMCFG_PARTIAL_Val << PM_STDBYCFG_RAMCFG_Pos)
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| 172 | #define PM_STDBYCFG_RAMCFG_OFF (PM_STDBYCFG_RAMCFG_OFF_Val << PM_STDBYCFG_RAMCFG_Pos)
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| 173 | #define PM_STDBYCFG_FASTWKUP_Pos 4 /**< \brief (PM_STDBYCFG) Fast Wakeup */
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| 174 | #define PM_STDBYCFG_FASTWKUP_Msk (_U_(0x3) << PM_STDBYCFG_FASTWKUP_Pos)
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| 175 | #define PM_STDBYCFG_FASTWKUP(value) (PM_STDBYCFG_FASTWKUP_Msk & ((value) << PM_STDBYCFG_FASTWKUP_Pos))
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| 176 | #define PM_STDBYCFG_MASK _U_(0x33) /**< \brief (PM_STDBYCFG) MASK Register */
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| 177 |
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| 178 | /* -------- PM_HIBCFG : (PM Offset: 0x09) (R/W 8) Hibernate Configuration -------- */
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| 179 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 180 | typedef union {
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| 181 | struct {
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| 182 | uint8_t RAMCFG:2; /*!< bit: 0.. 1 Ram Configuration */
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| 183 | uint8_t BRAMCFG:2; /*!< bit: 2.. 3 Backup Ram Configuration */
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| 184 | uint8_t :4; /*!< bit: 4.. 7 Reserved */
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| 185 | } bit; /*!< Structure used for bit access */
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| 186 | uint8_t reg; /*!< Type used for register access */
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| 187 | } PM_HIBCFG_Type;
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| 188 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 189 |
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| 190 | #define PM_HIBCFG_OFFSET 0x09 /**< \brief (PM_HIBCFG offset) Hibernate Configuration */
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| 191 | #define PM_HIBCFG_RESETVALUE _U_(0x00) /**< \brief (PM_HIBCFG reset_value) Hibernate Configuration */
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| 192 |
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| 193 | #define PM_HIBCFG_RAMCFG_Pos 0 /**< \brief (PM_HIBCFG) Ram Configuration */
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| 194 | #define PM_HIBCFG_RAMCFG_Msk (_U_(0x3) << PM_HIBCFG_RAMCFG_Pos)
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| 195 | #define PM_HIBCFG_RAMCFG(value) (PM_HIBCFG_RAMCFG_Msk & ((value) << PM_HIBCFG_RAMCFG_Pos))
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| 196 | #define PM_HIBCFG_BRAMCFG_Pos 2 /**< \brief (PM_HIBCFG) Backup Ram Configuration */
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| 197 | #define PM_HIBCFG_BRAMCFG_Msk (_U_(0x3) << PM_HIBCFG_BRAMCFG_Pos)
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| 198 | #define PM_HIBCFG_BRAMCFG(value) (PM_HIBCFG_BRAMCFG_Msk & ((value) << PM_HIBCFG_BRAMCFG_Pos))
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| 199 | #define PM_HIBCFG_MASK _U_(0x0F) /**< \brief (PM_HIBCFG) MASK Register */
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| 200 |
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| 201 | /* -------- PM_BKUPCFG : (PM Offset: 0x0A) (R/W 8) Backup Configuration -------- */
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| 202 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 203 | typedef union {
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| 204 | struct {
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| 205 | uint8_t BRAMCFG:2; /*!< bit: 0.. 1 Ram Configuration */
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| 206 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
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| 207 | } bit; /*!< Structure used for bit access */
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| 208 | uint8_t reg; /*!< Type used for register access */
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| 209 | } PM_BKUPCFG_Type;
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| 210 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 211 |
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| 212 | #define PM_BKUPCFG_OFFSET 0x0A /**< \brief (PM_BKUPCFG offset) Backup Configuration */
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| 213 | #define PM_BKUPCFG_RESETVALUE _U_(0x00) /**< \brief (PM_BKUPCFG reset_value) Backup Configuration */
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| 214 |
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| 215 | #define PM_BKUPCFG_BRAMCFG_Pos 0 /**< \brief (PM_BKUPCFG) Ram Configuration */
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| 216 | #define PM_BKUPCFG_BRAMCFG_Msk (_U_(0x3) << PM_BKUPCFG_BRAMCFG_Pos)
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| 217 | #define PM_BKUPCFG_BRAMCFG(value) (PM_BKUPCFG_BRAMCFG_Msk & ((value) << PM_BKUPCFG_BRAMCFG_Pos))
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| 218 | #define PM_BKUPCFG_MASK _U_(0x03) /**< \brief (PM_BKUPCFG) MASK Register */
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| 219 |
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| 220 | /* -------- PM_PWSAKDLY : (PM Offset: 0x12) (R/W 8) Power Switch Acknowledge Delay -------- */
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| 221 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 222 | typedef union {
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| 223 | struct {
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| 224 | uint8_t DLYVAL:7; /*!< bit: 0.. 6 Delay Value */
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| 225 | uint8_t IGNACK:1; /*!< bit: 7 Ignore Acknowledge */
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| 226 | } bit; /*!< Structure used for bit access */
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| 227 | uint8_t reg; /*!< Type used for register access */
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| 228 | } PM_PWSAKDLY_Type;
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| 229 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 230 |
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| 231 | #define PM_PWSAKDLY_OFFSET 0x12 /**< \brief (PM_PWSAKDLY offset) Power Switch Acknowledge Delay */
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| 232 | #define PM_PWSAKDLY_RESETVALUE _U_(0x00) /**< \brief (PM_PWSAKDLY reset_value) Power Switch Acknowledge Delay */
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| 233 |
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| 234 | #define PM_PWSAKDLY_DLYVAL_Pos 0 /**< \brief (PM_PWSAKDLY) Delay Value */
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| 235 | #define PM_PWSAKDLY_DLYVAL_Msk (_U_(0x7F) << PM_PWSAKDLY_DLYVAL_Pos)
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| 236 | #define PM_PWSAKDLY_DLYVAL(value) (PM_PWSAKDLY_DLYVAL_Msk & ((value) << PM_PWSAKDLY_DLYVAL_Pos))
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| 237 | #define PM_PWSAKDLY_IGNACK_Pos 7 /**< \brief (PM_PWSAKDLY) Ignore Acknowledge */
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| 238 | #define PM_PWSAKDLY_IGNACK (_U_(0x1) << PM_PWSAKDLY_IGNACK_Pos)
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| 239 | #define PM_PWSAKDLY_MASK _U_(0xFF) /**< \brief (PM_PWSAKDLY) MASK Register */
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| 240 |
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| 241 | /** \brief PM hardware registers */
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| 242 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 243 | typedef struct {
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| 244 | __IO PM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
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| 245 | __IO PM_SLEEPCFG_Type SLEEPCFG; /**< \brief Offset: 0x01 (R/W 8) Sleep Configuration */
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| 246 | RoReg8 Reserved1[0x2];
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| 247 | __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
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| 248 | __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
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| 249 | __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
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| 250 | RoReg8 Reserved2[0x1];
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| 251 | __IO PM_STDBYCFG_Type STDBYCFG; /**< \brief Offset: 0x08 (R/W 8) Standby Configuration */
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| 252 | __IO PM_HIBCFG_Type HIBCFG; /**< \brief Offset: 0x09 (R/W 8) Hibernate Configuration */
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| 253 | __IO PM_BKUPCFG_Type BKUPCFG; /**< \brief Offset: 0x0A (R/W 8) Backup Configuration */
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| 254 | RoReg8 Reserved3[0x7];
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| 255 | __IO PM_PWSAKDLY_Type PWSAKDLY; /**< \brief Offset: 0x12 (R/W 8) Power Switch Acknowledge Delay */
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| 256 | } Pm;
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| 257 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 258 |
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| 259 | /*@}*/
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| 260 |
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| 261 | #endif /* _SAME54_PM_COMPONENT_ */
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