Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief Component description for PICOP |
| 5 | * |
| 6 | * Copyright (c) 2015 Atmel Corporation. All rights reserved. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Redistribution and use in source and binary forms, with or without |
| 13 | * modification, are permitted provided that the following conditions are met: |
| 14 | * |
| 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| 16 | * this list of conditions and the following disclaimer. |
| 17 | * |
| 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| 19 | * this list of conditions and the following disclaimer in the documentation |
| 20 | * and/or other materials provided with the distribution. |
| 21 | * |
| 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
| 23 | * from this software without specific prior written permission. |
| 24 | * |
| 25 | * 4. This software may only be redistributed and used in connection with an |
| 26 | * Atmel microcontroller product. |
| 27 | * |
| 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
| 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
| 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
| 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
| 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
| 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 38 | * POSSIBILITY OF SUCH DAMAGE. |
| 39 | * |
| 40 | * \asf_license_stop |
| 41 | * |
| 42 | */ |
| 43 | |
| 44 | #ifndef _SAME54_PICOP_COMPONENT_ |
| 45 | #define _SAME54_PICOP_COMPONENT_ |
| 46 | |
| 47 | /* ========================================================================== */ |
| 48 | /** SOFTWARE API DEFINITION FOR PICOP */ |
| 49 | /* ========================================================================== */ |
| 50 | /** \addtogroup SAME54_PICOP PicoProcessor */ |
| 51 | /*@{*/ |
| 52 | |
| 53 | #define PICOP_U2232 |
| 54 | #define REV_PICOP 0x200 |
| 55 | |
| 56 | /* -------- PICOP_ID : (PICOP Offset: 0x000) (R/W 32) ID n -------- */ |
| 57 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 58 | typedef union { |
| 59 | struct { |
| 60 | uint32_t ID:32; /*!< bit: 0..31 ID String 0 */ |
| 61 | } bit; /*!< Structure used for bit access */ |
| 62 | uint32_t reg; /*!< Type used for register access */ |
| 63 | } PICOP_ID_Type; |
| 64 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 65 | |
| 66 | #define PICOP_ID_OFFSET 0x000 /**< \brief (PICOP_ID offset) ID n */ |
| 67 | #define PICOP_ID_RESETVALUE 0x00000000ul /**< \brief (PICOP_ID reset_value) ID n */ |
| 68 | |
| 69 | #define PICOP_ID_ID_Pos 0 /**< \brief (PICOP_ID) ID String 0 */ |
| 70 | #define PICOP_ID_ID_Msk (0xFFFFFFFFul << PICOP_ID_ID_Pos) |
| 71 | #define PICOP_ID_ID(value) (PICOP_ID_ID_Msk & ((value) << PICOP_ID_ID_Pos)) |
| 72 | #define PICOP_ID_MASK 0xFFFFFFFFul /**< \brief (PICOP_ID) MASK Register */ |
| 73 | |
| 74 | /* -------- PICOP_CONFIG : (PICOP Offset: 0x020) (R/W 32) Configuration -------- */ |
| 75 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 76 | typedef union { |
| 77 | struct { |
| 78 | uint32_t ISA:2; /*!< bit: 0.. 1 Instruction Set Architecture */ |
| 79 | uint32_t ASP:1; /*!< bit: 2 Aligned Stack Pointer */ |
| 80 | uint32_t MARRET:1; /*!< bit: 3 Misaligned implicit long return register (GCC compatibility) */ |
| 81 | uint32_t RRET:4; /*!< bit: 4.. 7 Implicit return word register */ |
| 82 | uint32_t PCEXEN:1; /*!< bit: 8 PC_EX register enabled for reduced interrupt latency */ |
| 83 | uint32_t :23; /*!< bit: 9..31 Reserved */ |
| 84 | } bit; /*!< Structure used for bit access */ |
| 85 | uint32_t reg; /*!< Type used for register access */ |
| 86 | } PICOP_CONFIG_Type; |
| 87 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 88 | |
| 89 | #define PICOP_CONFIG_OFFSET 0x020 /**< \brief (PICOP_CONFIG offset) Configuration */ |
| 90 | #define PICOP_CONFIG_RESETVALUE 0x00000000ul /**< \brief (PICOP_CONFIG reset_value) Configuration */ |
| 91 | |
| 92 | #define PICOP_CONFIG_ISA_Pos 0 /**< \brief (PICOP_CONFIG) Instruction Set Architecture */ |
| 93 | #define PICOP_CONFIG_ISA_Msk (0x3ul << PICOP_CONFIG_ISA_Pos) |
| 94 | #define PICOP_CONFIG_ISA(value) (PICOP_CONFIG_ISA_Msk & ((value) << PICOP_CONFIG_ISA_Pos)) |
| 95 | #define PICOP_CONFIG_ISA_AVR8_Val 0x0ul /**< \brief (PICOP_CONFIG) AVR8 ISA, AVR8SP=1 */ |
| 96 | #define PICOP_CONFIG_ISA_AVR16C_Val 0x1ul /**< \brief (PICOP_CONFIG) AVR16 ISA fully compatible with AVR8 ISA, AVR8SP=1 */ |
| 97 | #define PICOP_CONFIG_ISA_AVR16E_Val 0x2ul /**< \brief (PICOP_CONFIG) AVR16 ISA extended, AVR8SP=1 */ |
| 98 | #define PICOP_CONFIG_ISA_AVR16_Val 0x3ul /**< \brief (PICOP_CONFIG) AVR16 ISA extended, AVR8SP=0 */ |
| 99 | #define PICOP_CONFIG_ISA_AVR8 (PICOP_CONFIG_ISA_AVR8_Val << PICOP_CONFIG_ISA_Pos) |
| 100 | #define PICOP_CONFIG_ISA_AVR16C (PICOP_CONFIG_ISA_AVR16C_Val << PICOP_CONFIG_ISA_Pos) |
| 101 | #define PICOP_CONFIG_ISA_AVR16E (PICOP_CONFIG_ISA_AVR16E_Val << PICOP_CONFIG_ISA_Pos) |
| 102 | #define PICOP_CONFIG_ISA_AVR16 (PICOP_CONFIG_ISA_AVR16_Val << PICOP_CONFIG_ISA_Pos) |
| 103 | #define PICOP_CONFIG_ASP_Pos 2 /**< \brief (PICOP_CONFIG) Aligned Stack Pointer */ |
| 104 | #define PICOP_CONFIG_ASP (0x1ul << PICOP_CONFIG_ASP_Pos) |
| 105 | #define PICOP_CONFIG_MARRET_Pos 3 /**< \brief (PICOP_CONFIG) Misaligned implicit long return register (GCC compatibility) */ |
| 106 | #define PICOP_CONFIG_MARRET (0x1ul << PICOP_CONFIG_MARRET_Pos) |
| 107 | #define PICOP_CONFIG_RRET_Pos 4 /**< \brief (PICOP_CONFIG) Implicit return word register */ |
| 108 | #define PICOP_CONFIG_RRET_Msk (0xFul << PICOP_CONFIG_RRET_Pos) |
| 109 | #define PICOP_CONFIG_RRET(value) (PICOP_CONFIG_RRET_Msk & ((value) << PICOP_CONFIG_RRET_Pos)) |
| 110 | #define PICOP_CONFIG_PCEXEN_Pos 8 /**< \brief (PICOP_CONFIG) PC_EX register enabled for reduced interrupt latency */ |
| 111 | #define PICOP_CONFIG_PCEXEN (0x1ul << PICOP_CONFIG_PCEXEN_Pos) |
| 112 | #define PICOP_CONFIG_MASK 0x000001FFul /**< \brief (PICOP_CONFIG) MASK Register */ |
| 113 | |
| 114 | /* -------- PICOP_CTRL : (PICOP Offset: 0x024) (R/W 32) Control -------- */ |
| 115 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 116 | typedef union { |
| 117 | struct { |
| 118 | uint32_t MAPUEXCEPT:1; /*!< bit: 0 Enable exception for illegal access */ |
| 119 | uint32_t WPICACHE:1; /*!< bit: 1 Write protect iCache */ |
| 120 | uint32_t WPVEC:2; /*!< bit: 2.. 3 Write protect vectors */ |
| 121 | uint32_t WPCTX:2; /*!< bit: 4.. 5 Write protect contexts */ |
| 122 | uint32_t WPCODE:4; /*!< bit: 6.. 9 Write protect code */ |
| 123 | uint32_t :22; /*!< bit: 10..31 Reserved */ |
| 124 | } bit; /*!< Structure used for bit access */ |
| 125 | uint32_t reg; /*!< Type used for register access */ |
| 126 | } PICOP_CTRL_Type; |
| 127 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 128 | |
| 129 | #define PICOP_CTRL_OFFSET 0x024 /**< \brief (PICOP_CTRL offset) Control */ |
| 130 | #define PICOP_CTRL_RESETVALUE 0x00000000ul /**< \brief (PICOP_CTRL reset_value) Control */ |
| 131 | |
| 132 | #define PICOP_CTRL_MAPUEXCEPT_Pos 0 /**< \brief (PICOP_CTRL) Enable exception for illegal access */ |
| 133 | #define PICOP_CTRL_MAPUEXCEPT (0x1ul << PICOP_CTRL_MAPUEXCEPT_Pos) |
| 134 | #define PICOP_CTRL_WPICACHE_Pos 1 /**< \brief (PICOP_CTRL) Write protect iCache */ |
| 135 | #define PICOP_CTRL_WPICACHE (0x1ul << PICOP_CTRL_WPICACHE_Pos) |
| 136 | #define PICOP_CTRL_WPVEC_Pos 2 /**< \brief (PICOP_CTRL) Write protect vectors */ |
| 137 | #define PICOP_CTRL_WPVEC_Msk (0x3ul << PICOP_CTRL_WPVEC_Pos) |
| 138 | #define PICOP_CTRL_WPVEC(value) (PICOP_CTRL_WPVEC_Msk & ((value) << PICOP_CTRL_WPVEC_Pos)) |
| 139 | #define PICOP_CTRL_WPVEC_NONE_Val 0x0ul /**< \brief (PICOP_CTRL) */ |
| 140 | #define PICOP_CTRL_WPVEC_RSTNMI_Val 0x1ul /**< \brief (PICOP_CTRL) */ |
| 141 | #define PICOP_CTRL_WPVEC_NONE (PICOP_CTRL_WPVEC_NONE_Val << PICOP_CTRL_WPVEC_Pos) |
| 142 | #define PICOP_CTRL_WPVEC_RSTNMI (PICOP_CTRL_WPVEC_RSTNMI_Val << PICOP_CTRL_WPVEC_Pos) |
| 143 | #define PICOP_CTRL_WPCTX_Pos 4 /**< \brief (PICOP_CTRL) Write protect contexts */ |
| 144 | #define PICOP_CTRL_WPCTX_Msk (0x3ul << PICOP_CTRL_WPCTX_Pos) |
| 145 | #define PICOP_CTRL_WPCTX(value) (PICOP_CTRL_WPCTX_Msk & ((value) << PICOP_CTRL_WPCTX_Pos)) |
| 146 | #define PICOP_CTRL_WPCTX_NONE_Val 0x0ul /**< \brief (PICOP_CTRL) */ |
| 147 | #define PICOP_CTRL_WPCTX_CTX0_Val 0x1ul /**< \brief (PICOP_CTRL) */ |
| 148 | #define PICOP_CTRL_WPCTX_CTX01_Val 0x2ul /**< \brief (PICOP_CTRL) */ |
| 149 | #define PICOP_CTRL_WPCTX_CTX012_Val 0x3ul /**< \brief (PICOP_CTRL) */ |
| 150 | #define PICOP_CTRL_WPCTX_NONE (PICOP_CTRL_WPCTX_NONE_Val << PICOP_CTRL_WPCTX_Pos) |
| 151 | #define PICOP_CTRL_WPCTX_CTX0 (PICOP_CTRL_WPCTX_CTX0_Val << PICOP_CTRL_WPCTX_Pos) |
| 152 | #define PICOP_CTRL_WPCTX_CTX01 (PICOP_CTRL_WPCTX_CTX01_Val << PICOP_CTRL_WPCTX_Pos) |
| 153 | #define PICOP_CTRL_WPCTX_CTX012 (PICOP_CTRL_WPCTX_CTX012_Val << PICOP_CTRL_WPCTX_Pos) |
| 154 | #define PICOP_CTRL_WPCODE_Pos 6 /**< \brief (PICOP_CTRL) Write protect code */ |
| 155 | #define PICOP_CTRL_WPCODE_Msk (0xFul << PICOP_CTRL_WPCODE_Pos) |
| 156 | #define PICOP_CTRL_WPCODE(value) (PICOP_CTRL_WPCODE_Msk & ((value) << PICOP_CTRL_WPCODE_Pos)) |
| 157 | #define PICOP_CTRL_WPCODE_NONE_Val 0x0ul /**< \brief (PICOP_CTRL) */ |
| 158 | #define PICOP_CTRL_WPCODE_256B_Val 0x1ul /**< \brief (PICOP_CTRL) */ |
| 159 | #define PICOP_CTRL_WPCODE_512B_Val 0x2ul /**< \brief (PICOP_CTRL) */ |
| 160 | #define PICOP_CTRL_WPCODE_768B_Val 0x3ul /**< \brief (PICOP_CTRL) */ |
| 161 | #define PICOP_CTRL_WPCODE_1024B_Val 0x4ul /**< \brief (PICOP_CTRL) */ |
| 162 | #define PICOP_CTRL_WPCODE_1280B_Val 0x5ul /**< \brief (PICOP_CTRL) */ |
| 163 | #define PICOP_CTRL_WPCODE_1536B_Val 0x6ul /**< \brief (PICOP_CTRL) */ |
| 164 | #define PICOP_CTRL_WPCODE_1792B_Val 0x7ul /**< \brief (PICOP_CTRL) */ |
| 165 | #define PICOP_CTRL_WPCODE_2048B_Val 0x8ul /**< \brief (PICOP_CTRL) */ |
| 166 | #define PICOP_CTRL_WPCODE_2304B_Val 0x9ul /**< \brief (PICOP_CTRL) */ |
| 167 | #define PICOP_CTRL_WPCODE_2560B_Val 0xAul /**< \brief (PICOP_CTRL) */ |
| 168 | #define PICOP_CTRL_WPCODE_2816B_Val 0xBul /**< \brief (PICOP_CTRL) */ |
| 169 | #define PICOP_CTRL_WPCODE_3072B_Val 0xCul /**< \brief (PICOP_CTRL) */ |
| 170 | #define PICOP_CTRL_WPCODE_3328B_Val 0xDul /**< \brief (PICOP_CTRL) */ |
| 171 | #define PICOP_CTRL_WPCODE_3584B_Val 0xEul /**< \brief (PICOP_CTRL) */ |
| 172 | #define PICOP_CTRL_WPCODE_3840B_Val 0xFul /**< \brief (PICOP_CTRL) */ |
| 173 | #define PICOP_CTRL_WPCODE_NONE (PICOP_CTRL_WPCODE_NONE_Val << PICOP_CTRL_WPCODE_Pos) |
| 174 | #define PICOP_CTRL_WPCODE_256B (PICOP_CTRL_WPCODE_256B_Val << PICOP_CTRL_WPCODE_Pos) |
| 175 | #define PICOP_CTRL_WPCODE_512B (PICOP_CTRL_WPCODE_512B_Val << PICOP_CTRL_WPCODE_Pos) |
| 176 | #define PICOP_CTRL_WPCODE_768B (PICOP_CTRL_WPCODE_768B_Val << PICOP_CTRL_WPCODE_Pos) |
| 177 | #define PICOP_CTRL_WPCODE_1024B (PICOP_CTRL_WPCODE_1024B_Val << PICOP_CTRL_WPCODE_Pos) |
| 178 | #define PICOP_CTRL_WPCODE_1280B (PICOP_CTRL_WPCODE_1280B_Val << PICOP_CTRL_WPCODE_Pos) |
| 179 | #define PICOP_CTRL_WPCODE_1536B (PICOP_CTRL_WPCODE_1536B_Val << PICOP_CTRL_WPCODE_Pos) |
| 180 | #define PICOP_CTRL_WPCODE_1792B (PICOP_CTRL_WPCODE_1792B_Val << PICOP_CTRL_WPCODE_Pos) |
| 181 | #define PICOP_CTRL_WPCODE_2048B (PICOP_CTRL_WPCODE_2048B_Val << PICOP_CTRL_WPCODE_Pos) |
| 182 | #define PICOP_CTRL_WPCODE_2304B (PICOP_CTRL_WPCODE_2304B_Val << PICOP_CTRL_WPCODE_Pos) |
| 183 | #define PICOP_CTRL_WPCODE_2560B (PICOP_CTRL_WPCODE_2560B_Val << PICOP_CTRL_WPCODE_Pos) |
| 184 | #define PICOP_CTRL_WPCODE_2816B (PICOP_CTRL_WPCODE_2816B_Val << PICOP_CTRL_WPCODE_Pos) |
| 185 | #define PICOP_CTRL_WPCODE_3072B (PICOP_CTRL_WPCODE_3072B_Val << PICOP_CTRL_WPCODE_Pos) |
| 186 | #define PICOP_CTRL_WPCODE_3328B (PICOP_CTRL_WPCODE_3328B_Val << PICOP_CTRL_WPCODE_Pos) |
| 187 | #define PICOP_CTRL_WPCODE_3584B (PICOP_CTRL_WPCODE_3584B_Val << PICOP_CTRL_WPCODE_Pos) |
| 188 | #define PICOP_CTRL_WPCODE_3840B (PICOP_CTRL_WPCODE_3840B_Val << PICOP_CTRL_WPCODE_Pos) |
| 189 | #define PICOP_CTRL_MASK 0x000003FFul /**< \brief (PICOP_CTRL) MASK Register */ |
| 190 | |
| 191 | /* -------- PICOP_CMD : (PICOP Offset: 0x028) (R/W 32) Command -------- */ |
| 192 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 193 | typedef union { |
| 194 | struct { // CMD mode |
| 195 | uint32_t CMD:4; /*!< bit: 0.. 3 Command */ |
| 196 | uint32_t :12; /*!< bit: 4..15 Reserved */ |
| 197 | uint32_t UNLOCK:16; /*!< bit: 16..31 Unlock */ |
| 198 | } CMD; /*!< Structure used for CMD */ |
| 199 | struct { // STATUS mode |
| 200 | uint32_t CTTSEX:1; /*!< bit: 0 Context Task Switch */ |
| 201 | uint32_t IL0EX:1; /*!< bit: 1 Interrupt Level 0 Exception */ |
| 202 | uint32_t IL1EX:1; /*!< bit: 2 Interrupt Level 1 Exception */ |
| 203 | uint32_t IL2EX:1; /*!< bit: 3 Interrupt Level 2 Exception */ |
| 204 | uint32_t IL3EX:1; /*!< bit: 4 Interrupt Level 3 Exception */ |
| 205 | uint32_t IL4EX:1; /*!< bit: 5 Interrupt Level 4 Exception */ |
| 206 | uint32_t NMIEX:1; /*!< bit: 6 NMI Exception */ |
| 207 | uint32_t :1; /*!< bit: 7 Reserved */ |
| 208 | uint32_t EXCEPT:1; /*!< bit: 8 Exception */ |
| 209 | uint32_t AVR16:1; /*!< bit: 9 AVR16 Mode */ |
| 210 | uint32_t OCDCOF:1; /*!< bit: 10 OCD Change of Flow */ |
| 211 | uint32_t :5; /*!< bit: 11..15 Reserved */ |
| 212 | uint32_t UPC:8; /*!< bit: 16..23 Microcode State */ |
| 213 | uint32_t :3; /*!< bit: 24..26 Reserved */ |
| 214 | uint32_t STATE:5; /*!< bit: 27..31 System State */ |
| 215 | } STATUS; /*!< Structure used for STATUS */ |
| 216 | uint32_t reg; /*!< Type used for register access */ |
| 217 | } PICOP_CMD_Type; |
| 218 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 219 | |
| 220 | #define PICOP_CMD_OFFSET 0x028 /**< \brief (PICOP_CMD offset) Command */ |
| 221 | #define PICOP_CMD_RESETVALUE 0x00000000ul /**< \brief (PICOP_CMD reset_value) Command */ |
| 222 | |
| 223 | // CMD mode |
| 224 | #define PICOP_CMD_CMD_CMD_Pos 0 /**< \brief (PICOP_CMD_CMD) Command */ |
| 225 | #define PICOP_CMD_CMD_CMD_Msk (0xFul << PICOP_CMD_CMD_CMD_Pos) |
| 226 | #define PICOP_CMD_CMD_CMD(value) (PICOP_CMD_CMD_CMD_Msk & ((value) << PICOP_CMD_CMD_CMD_Pos)) |
| 227 | #define PICOP_CMD_CMD_CMD_NOACTION_Val 0x0ul /**< \brief (PICOP_CMD_CMD) No action */ |
| 228 | #define PICOP_CMD_CMD_CMD_STOP_Val 0x1ul /**< \brief (PICOP_CMD_CMD) Wait for ongoing execution to complete, then stop */ |
| 229 | #define PICOP_CMD_CMD_CMD_RESET_Val 0x2ul /**< \brief (PICOP_CMD_CMD) Stop, reset and stop */ |
| 230 | #define PICOP_CMD_CMD_CMD_RESTART_Val 0x3ul /**< \brief (PICOP_CMD_CMD) Stop, reset and run */ |
| 231 | #define PICOP_CMD_CMD_CMD_ABORT_Val 0x4ul /**< \brief (PICOP_CMD_CMD) Abort, reset and stop */ |
| 232 | #define PICOP_CMD_CMD_CMD_RUN_Val 0x5ul /**< \brief (PICOP_CMD_CMD) Start execution (from unlocked stopped state) */ |
| 233 | #define PICOP_CMD_CMD_CMD_RUNLOCK_Val 0x6ul /**< \brief (PICOP_CMD_CMD) Start execution and lock */ |
| 234 | #define PICOP_CMD_CMD_CMD_RUNOCD_Val 0x7ul /**< \brief (PICOP_CMD_CMD) Start execution and enable host-controlled OCD */ |
| 235 | #define PICOP_CMD_CMD_CMD_UNLOCK_Val 0x8ul /**< \brief (PICOP_CMD_CMD) Unlock and run */ |
| 236 | #define PICOP_CMD_CMD_CMD_NMI_Val 0x9ul /**< \brief (PICOP_CMD_CMD) Trigger a NMI */ |
| 237 | #define PICOP_CMD_CMD_CMD_WAKEUP_Val 0xAul /**< \brief (PICOP_CMD_CMD) Force a wakeup from sleep (if in sleep) */ |
| 238 | #define PICOP_CMD_CMD_CMD_NOACTION (PICOP_CMD_CMD_CMD_NOACTION_Val << PICOP_CMD_CMD_CMD_Pos) |
| 239 | #define PICOP_CMD_CMD_CMD_STOP (PICOP_CMD_CMD_CMD_STOP_Val << PICOP_CMD_CMD_CMD_Pos) |
| 240 | #define PICOP_CMD_CMD_CMD_RESET (PICOP_CMD_CMD_CMD_RESET_Val << PICOP_CMD_CMD_CMD_Pos) |
| 241 | #define PICOP_CMD_CMD_CMD_RESTART (PICOP_CMD_CMD_CMD_RESTART_Val << PICOP_CMD_CMD_CMD_Pos) |
| 242 | #define PICOP_CMD_CMD_CMD_ABORT (PICOP_CMD_CMD_CMD_ABORT_Val << PICOP_CMD_CMD_CMD_Pos) |
| 243 | #define PICOP_CMD_CMD_CMD_RUN (PICOP_CMD_CMD_CMD_RUN_Val << PICOP_CMD_CMD_CMD_Pos) |
| 244 | #define PICOP_CMD_CMD_CMD_RUNLOCK (PICOP_CMD_CMD_CMD_RUNLOCK_Val << PICOP_CMD_CMD_CMD_Pos) |
| 245 | #define PICOP_CMD_CMD_CMD_RUNOCD (PICOP_CMD_CMD_CMD_RUNOCD_Val << PICOP_CMD_CMD_CMD_Pos) |
| 246 | #define PICOP_CMD_CMD_CMD_UNLOCK (PICOP_CMD_CMD_CMD_UNLOCK_Val << PICOP_CMD_CMD_CMD_Pos) |
| 247 | #define PICOP_CMD_CMD_CMD_NMI (PICOP_CMD_CMD_CMD_NMI_Val << PICOP_CMD_CMD_CMD_Pos) |
| 248 | #define PICOP_CMD_CMD_CMD_WAKEUP (PICOP_CMD_CMD_CMD_WAKEUP_Val << PICOP_CMD_CMD_CMD_Pos) |
| 249 | #define PICOP_CMD_CMD_UNLOCK_Pos 16 /**< \brief (PICOP_CMD_CMD) Unlock */ |
| 250 | #define PICOP_CMD_CMD_UNLOCK_Msk (0xFFFFul << PICOP_CMD_CMD_UNLOCK_Pos) |
| 251 | #define PICOP_CMD_CMD_UNLOCK(value) (PICOP_CMD_CMD_UNLOCK_Msk & ((value) << PICOP_CMD_CMD_UNLOCK_Pos)) |
| 252 | #define PICOP_CMD_CMD_MASK 0xFFFF000Ful /**< \brief (PICOP_CMD_CMD) MASK Register */ |
| 253 | |
| 254 | // STATUS mode |
| 255 | #define PICOP_CMD_STATUS_CTTSEX_Pos 0 /**< \brief (PICOP_CMD_STATUS) Context Task Switch */ |
| 256 | #define PICOP_CMD_STATUS_CTTSEX (0x1ul << PICOP_CMD_STATUS_CTTSEX_Pos) |
| 257 | #define PICOP_CMD_STATUS_IL0EX_Pos 1 /**< \brief (PICOP_CMD_STATUS) Interrupt Level 0 Exception */ |
| 258 | #define PICOP_CMD_STATUS_IL0EX (0x1ul << PICOP_CMD_STATUS_IL0EX_Pos) |
| 259 | #define PICOP_CMD_STATUS_IL1EX_Pos 2 /**< \brief (PICOP_CMD_STATUS) Interrupt Level 1 Exception */ |
| 260 | #define PICOP_CMD_STATUS_IL1EX (0x1ul << PICOP_CMD_STATUS_IL1EX_Pos) |
| 261 | #define PICOP_CMD_STATUS_IL2EX_Pos 3 /**< \brief (PICOP_CMD_STATUS) Interrupt Level 2 Exception */ |
| 262 | #define PICOP_CMD_STATUS_IL2EX (0x1ul << PICOP_CMD_STATUS_IL2EX_Pos) |
| 263 | #define PICOP_CMD_STATUS_IL3EX_Pos 4 /**< \brief (PICOP_CMD_STATUS) Interrupt Level 3 Exception */ |
| 264 | #define PICOP_CMD_STATUS_IL3EX (0x1ul << PICOP_CMD_STATUS_IL3EX_Pos) |
| 265 | #define PICOP_CMD_STATUS_IL4EX_Pos 5 /**< \brief (PICOP_CMD_STATUS) Interrupt Level 4 Exception */ |
| 266 | #define PICOP_CMD_STATUS_IL4EX (0x1ul << PICOP_CMD_STATUS_IL4EX_Pos) |
| 267 | #define PICOP_CMD_STATUS_NMIEX_Pos 6 /**< \brief (PICOP_CMD_STATUS) NMI Exception */ |
| 268 | #define PICOP_CMD_STATUS_NMIEX (0x1ul << PICOP_CMD_STATUS_NMIEX_Pos) |
| 269 | #define PICOP_CMD_STATUS_EXCEPT_Pos 8 /**< \brief (PICOP_CMD_STATUS) Exception */ |
| 270 | #define PICOP_CMD_STATUS_EXCEPT (0x1ul << PICOP_CMD_STATUS_EXCEPT_Pos) |
| 271 | #define PICOP_CMD_STATUS_AVR16_Pos 9 /**< \brief (PICOP_CMD_STATUS) AVR16 Mode */ |
| 272 | #define PICOP_CMD_STATUS_AVR16 (0x1ul << PICOP_CMD_STATUS_AVR16_Pos) |
| 273 | #define PICOP_CMD_STATUS_OCDCOF_Pos 10 /**< \brief (PICOP_CMD_STATUS) OCD Change of Flow */ |
| 274 | #define PICOP_CMD_STATUS_OCDCOF (0x1ul << PICOP_CMD_STATUS_OCDCOF_Pos) |
| 275 | #define PICOP_CMD_STATUS_UPC_Pos 16 /**< \brief (PICOP_CMD_STATUS) Microcode State */ |
| 276 | #define PICOP_CMD_STATUS_UPC_Msk (0xFFul << PICOP_CMD_STATUS_UPC_Pos) |
| 277 | #define PICOP_CMD_STATUS_UPC(value) (PICOP_CMD_STATUS_UPC_Msk & ((value) << PICOP_CMD_STATUS_UPC_Pos)) |
| 278 | #define PICOP_CMD_STATUS_UPC_EXEC_Val 0x0ul /**< \brief (PICOP_CMD_STATUS) Normal execution (no ucode) */ |
| 279 | #define PICOP_CMD_STATUS_UPC_EXEC_NOBRK_Val 0x1ul /**< \brief (PICOP_CMD_STATUS) Normal execution with break disabled */ |
| 280 | #define PICOP_CMD_STATUS_UPC_EXEC_NOP_Val 0x2ul /**< \brief (PICOP_CMD_STATUS) OCD NOP override execution (break disabled) */ |
| 281 | #define PICOP_CMD_STATUS_UPC_EXEC_IMM_Val 0x3ul /**< \brief (PICOP_CMD_STATUS) OCD IMM override execution (break disabled) */ |
| 282 | #define PICOP_CMD_STATUS_UPC_ICACHE_FLUSH_Val 0x4ul /**< \brief (PICOP_CMD_STATUS) Flush instruction cache */ |
| 283 | #define PICOP_CMD_STATUS_UPC_HALT_Val 0x10ul /**< \brief (PICOP_CMD_STATUS) HALT execution (shutdown) */ |
| 284 | #define PICOP_CMD_STATUS_UPC_HALTED_Val 0x11ul /**< \brief (PICOP_CMD_STATUS) Execution halted (shutdown) */ |
| 285 | #define PICOP_CMD_STATUS_UPC_SLEEP_Val 0x17ul /**< \brief (PICOP_CMD_STATUS) Wait until safe to go to sleeping state */ |
| 286 | #define PICOP_CMD_STATUS_UPC_SLEEPING_Val 0x18ul /**< \brief (PICOP_CMD_STATUS) Sleeping / reset cycle 0 */ |
| 287 | #define PICOP_CMD_STATUS_UPC_WAKEUP_RST1_Val 0x19ul /**< \brief (PICOP_CMD_STATUS) Reset cycle 1 */ |
| 288 | #define PICOP_CMD_STATUS_UPC_WAKEUP_CTR_SP_Val 0x1Aul /**< \brief (PICOP_CMD_STATUS) SLEEP: Context Restore CCR..SP */ |
| 289 | #define PICOP_CMD_STATUS_UPC_WAKEUP_CTR_ZY_Val 0x1Bul /**< \brief (PICOP_CMD_STATUS) SLEEP: Context Restore Z..Y */ |
| 290 | #define PICOP_CMD_STATUS_UPC_OCD_STATE_Val 0x20ul /**< \brief (PICOP_CMD_STATUS) OCD state: No break (sr.upc[1:0] == 2'b00) */ |
| 291 | #define PICOP_CMD_STATUS_UPC_OCD_STATE_NOP_Val 0x21ul /**< \brief (PICOP_CMD_STATUS) OCD state: NOP override (sr.upc[1:0] == 2'b01) */ |
| 292 | #define PICOP_CMD_STATUS_UPC_OCD_STATE_IMM_Val 0x22ul /**< \brief (PICOP_CMD_STATUS) OCD state: IMM override (sr.upc[1:0] == 2'b10) */ |
| 293 | #define PICOP_CMD_STATUS_UPC_OCD_STATE_SLEEP_Val 0x23ul /**< \brief (PICOP_CMD_STATUS) OCD state: SLEEP instruction (sr.upc[1:0] == 2'b11) */ |
| 294 | #define PICOP_CMD_STATUS_UPC_OCD_BREAKPOINT_Val 0x28ul /**< \brief (PICOP_CMD_STATUS) Breakpoint (sr.upc[0] == 1'b0) */ |
| 295 | #define PICOP_CMD_STATUS_UPC_OCD_BREAKI_Val 0x29ul /**< \brief (PICOP_CMD_STATUS) Breakpoint instruction (sr.upc[0] == 1'b1) */ |
| 296 | #define PICOP_CMD_STATUS_UPC_CANCEL_EX_Val 0x2Eul /**< \brief (PICOP_CMD_STATUS) Cancel exception */ |
| 297 | #define PICOP_CMD_STATUS_UPC_IRQ_Val 0x2Ful /**< \brief (PICOP_CMD_STATUS) IRQ: Context Save CCR..SP */ |
| 298 | #define PICOP_CMD_STATUS_UPC_IRQ_CTS_0_Val 0x30ul /**< \brief (PICOP_CMD_STATUS) IRQ: Context Save R{m+0+1}.l */ |
| 299 | #define PICOP_CMD_STATUS_UPC_IRQ_CTS_1_Val 0x31ul /**< \brief (PICOP_CMD_STATUS) IRQ: Context Save R{m+1+1}.l */ |
| 300 | #define PICOP_CMD_STATUS_UPC_IRQ_CTS_2_Val 0x32ul /**< \brief (PICOP_CMD_STATUS) IRQ: Context Save R{m+2+1}.l */ |
| 301 | #define PICOP_CMD_STATUS_UPC_IRQ_CTS_3_Val 0x33ul /**< \brief (PICOP_CMD_STATUS) IRQ: Context Save R{m+3+1}.l */ |
| 302 | #define PICOP_CMD_STATUS_UPC_IRQ_CTS_4_Val 0x34ul /**< \brief (PICOP_CMD_STATUS) IRQ: Context Save R{m+4+1}.l */ |
| 303 | #define PICOP_CMD_STATUS_UPC_IRQ_CTS_5_Val 0x35ul /**< \brief (PICOP_CMD_STATUS) IRQ: Context Save R{m+5+1}.l */ |
| 304 | #define PICOP_CMD_STATUS_UPC_IRQ_CTS_6_Val 0x36ul /**< \brief (PICOP_CMD_STATUS) IRQ: Context Save R{m+6+1}.l */ |
| 305 | #define PICOP_CMD_STATUS_UPC_IRQ_CTS_7_Val 0x37ul /**< \brief (PICOP_CMD_STATUS) IRQ: Context Save R{m+7+1}.l */ |
| 306 | #define PICOP_CMD_STATUS_UPC_IRQ_CTS_PC_Val 0x38ul /**< \brief (PICOP_CMD_STATUS) IRQ: Context Save (SR):PC */ |
| 307 | #define PICOP_CMD_STATUS_UPC_IRQ_ACK_Val 0x39ul /**< \brief (PICOP_CMD_STATUS) IRQ: Acknowledge cycle */ |
| 308 | #define PICOP_CMD_STATUS_UPC_EXCEPT_Val 0x3Aul /**< \brief (PICOP_CMD_STATUS) Internal exceptions */ |
| 309 | #define PICOP_CMD_STATUS_UPC_RETI_SLEEP_Val 0x3Ful /**< \brief (PICOP_CMD_STATUS) RETI: Clear SLEEPMODE (RETI) */ |
| 310 | #define PICOP_CMD_STATUS_UPC_RETI_CTR_R0_Val 0x40ul /**< \brief (PICOP_CMD_STATUS) RETI: Context Restore R3..R0 (RETIS) */ |
| 311 | #define PICOP_CMD_STATUS_UPC_RETI_CTR_R4_Val 0x41ul /**< \brief (PICOP_CMD_STATUS) RETI: Context Restore R7..R4 */ |
| 312 | #define PICOP_CMD_STATUS_UPC_RETI_CTR_R8_Val 0x42ul /**< \brief (PICOP_CMD_STATUS) RETI: Context Restore R11..R8 */ |
| 313 | #define PICOP_CMD_STATUS_UPC_RETI_CTR_R12_Val 0x43ul /**< \brief (PICOP_CMD_STATUS) RETI: Context Restore R15..R12 */ |
| 314 | #define PICOP_CMD_STATUS_UPC_RETI_CTR_R16_Val 0x44ul /**< \brief (PICOP_CMD_STATUS) RETI: Context Restore R19..R16 */ |
| 315 | #define PICOP_CMD_STATUS_UPC_RETI_CTR_R20_Val 0x45ul /**< \brief (PICOP_CMD_STATUS) RETI: Context Restore R23..R20 */ |
| 316 | #define PICOP_CMD_STATUS_UPC_RETI_CTR_R24_Val 0x46ul /**< \brief (PICOP_CMD_STATUS) RETI: Context Restore R27..R24 */ |
| 317 | #define PICOP_CMD_STATUS_UPC_RETI_CTR_R28_Val 0x47ul /**< \brief (PICOP_CMD_STATUS) RETI: Context Restore R31..R28 */ |
| 318 | #define PICOP_CMD_STATUS_UPC_RETI_CTR_SP_Val 0x48ul /**< \brief (PICOP_CMD_STATUS) RETI: Context Restore CCR..SP */ |
| 319 | #define PICOP_CMD_STATUS_UPC_RETI_EXEC_Val 0x49ul /**< \brief (PICOP_CMD_STATUS) RETI: Return to code execution (PC <- LINK) */ |
| 320 | #define PICOP_CMD_STATUS_UPC_EXEC (PICOP_CMD_STATUS_UPC_EXEC_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 321 | #define PICOP_CMD_STATUS_UPC_EXEC_NOBRK (PICOP_CMD_STATUS_UPC_EXEC_NOBRK_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 322 | #define PICOP_CMD_STATUS_UPC_EXEC_NOP (PICOP_CMD_STATUS_UPC_EXEC_NOP_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 323 | #define PICOP_CMD_STATUS_UPC_EXEC_IMM (PICOP_CMD_STATUS_UPC_EXEC_IMM_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 324 | #define PICOP_CMD_STATUS_UPC_ICACHE_FLUSH (PICOP_CMD_STATUS_UPC_ICACHE_FLUSH_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 325 | #define PICOP_CMD_STATUS_UPC_HALT (PICOP_CMD_STATUS_UPC_HALT_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 326 | #define PICOP_CMD_STATUS_UPC_HALTED (PICOP_CMD_STATUS_UPC_HALTED_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 327 | #define PICOP_CMD_STATUS_UPC_SLEEP (PICOP_CMD_STATUS_UPC_SLEEP_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 328 | #define PICOP_CMD_STATUS_UPC_SLEEPING (PICOP_CMD_STATUS_UPC_SLEEPING_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 329 | #define PICOP_CMD_STATUS_UPC_WAKEUP_RST1 (PICOP_CMD_STATUS_UPC_WAKEUP_RST1_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 330 | #define PICOP_CMD_STATUS_UPC_WAKEUP_CTR_SP (PICOP_CMD_STATUS_UPC_WAKEUP_CTR_SP_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 331 | #define PICOP_CMD_STATUS_UPC_WAKEUP_CTR_ZY (PICOP_CMD_STATUS_UPC_WAKEUP_CTR_ZY_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 332 | #define PICOP_CMD_STATUS_UPC_OCD_STATE (PICOP_CMD_STATUS_UPC_OCD_STATE_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 333 | #define PICOP_CMD_STATUS_UPC_OCD_STATE_NOP (PICOP_CMD_STATUS_UPC_OCD_STATE_NOP_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 334 | #define PICOP_CMD_STATUS_UPC_OCD_STATE_IMM (PICOP_CMD_STATUS_UPC_OCD_STATE_IMM_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 335 | #define PICOP_CMD_STATUS_UPC_OCD_STATE_SLEEP (PICOP_CMD_STATUS_UPC_OCD_STATE_SLEEP_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 336 | #define PICOP_CMD_STATUS_UPC_OCD_BREAKPOINT (PICOP_CMD_STATUS_UPC_OCD_BREAKPOINT_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 337 | #define PICOP_CMD_STATUS_UPC_OCD_BREAKI (PICOP_CMD_STATUS_UPC_OCD_BREAKI_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 338 | #define PICOP_CMD_STATUS_UPC_CANCEL_EX (PICOP_CMD_STATUS_UPC_CANCEL_EX_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 339 | #define PICOP_CMD_STATUS_UPC_IRQ (PICOP_CMD_STATUS_UPC_IRQ_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 340 | #define PICOP_CMD_STATUS_UPC_IRQ_CTS_0 (PICOP_CMD_STATUS_UPC_IRQ_CTS_0_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 341 | #define PICOP_CMD_STATUS_UPC_IRQ_CTS_1 (PICOP_CMD_STATUS_UPC_IRQ_CTS_1_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 342 | #define PICOP_CMD_STATUS_UPC_IRQ_CTS_2 (PICOP_CMD_STATUS_UPC_IRQ_CTS_2_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 343 | #define PICOP_CMD_STATUS_UPC_IRQ_CTS_3 (PICOP_CMD_STATUS_UPC_IRQ_CTS_3_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 344 | #define PICOP_CMD_STATUS_UPC_IRQ_CTS_4 (PICOP_CMD_STATUS_UPC_IRQ_CTS_4_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 345 | #define PICOP_CMD_STATUS_UPC_IRQ_CTS_5 (PICOP_CMD_STATUS_UPC_IRQ_CTS_5_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 346 | #define PICOP_CMD_STATUS_UPC_IRQ_CTS_6 (PICOP_CMD_STATUS_UPC_IRQ_CTS_6_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 347 | #define PICOP_CMD_STATUS_UPC_IRQ_CTS_7 (PICOP_CMD_STATUS_UPC_IRQ_CTS_7_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 348 | #define PICOP_CMD_STATUS_UPC_IRQ_CTS_PC (PICOP_CMD_STATUS_UPC_IRQ_CTS_PC_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 349 | #define PICOP_CMD_STATUS_UPC_IRQ_ACK (PICOP_CMD_STATUS_UPC_IRQ_ACK_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 350 | #define PICOP_CMD_STATUS_UPC_EXCEPT (PICOP_CMD_STATUS_UPC_EXCEPT_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 351 | #define PICOP_CMD_STATUS_UPC_RETI_SLEEP (PICOP_CMD_STATUS_UPC_RETI_SLEEP_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 352 | #define PICOP_CMD_STATUS_UPC_RETI_CTR_R0 (PICOP_CMD_STATUS_UPC_RETI_CTR_R0_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 353 | #define PICOP_CMD_STATUS_UPC_RETI_CTR_R4 (PICOP_CMD_STATUS_UPC_RETI_CTR_R4_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 354 | #define PICOP_CMD_STATUS_UPC_RETI_CTR_R8 (PICOP_CMD_STATUS_UPC_RETI_CTR_R8_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 355 | #define PICOP_CMD_STATUS_UPC_RETI_CTR_R12 (PICOP_CMD_STATUS_UPC_RETI_CTR_R12_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 356 | #define PICOP_CMD_STATUS_UPC_RETI_CTR_R16 (PICOP_CMD_STATUS_UPC_RETI_CTR_R16_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 357 | #define PICOP_CMD_STATUS_UPC_RETI_CTR_R20 (PICOP_CMD_STATUS_UPC_RETI_CTR_R20_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 358 | #define PICOP_CMD_STATUS_UPC_RETI_CTR_R24 (PICOP_CMD_STATUS_UPC_RETI_CTR_R24_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 359 | #define PICOP_CMD_STATUS_UPC_RETI_CTR_R28 (PICOP_CMD_STATUS_UPC_RETI_CTR_R28_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 360 | #define PICOP_CMD_STATUS_UPC_RETI_CTR_SP (PICOP_CMD_STATUS_UPC_RETI_CTR_SP_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 361 | #define PICOP_CMD_STATUS_UPC_RETI_EXEC (PICOP_CMD_STATUS_UPC_RETI_EXEC_Val << PICOP_CMD_STATUS_UPC_Pos) |
| 362 | #define PICOP_CMD_STATUS_STATE_Pos 27 /**< \brief (PICOP_CMD_STATUS) System State */ |
| 363 | #define PICOP_CMD_STATUS_STATE_Msk (0x1Ful << PICOP_CMD_STATUS_STATE_Pos) |
| 364 | #define PICOP_CMD_STATUS_STATE(value) (PICOP_CMD_STATUS_STATE_Msk & ((value) << PICOP_CMD_STATUS_STATE_Pos)) |
| 365 | #define PICOP_CMD_STATUS_STATE_RESET_0_Val 0x0ul /**< \brief (PICOP_CMD_STATUS) Reset step 0 */ |
| 366 | #define PICOP_CMD_STATUS_STATE_RESET_1_Val 0x1ul /**< \brief (PICOP_CMD_STATUS) Reset step 1 */ |
| 367 | #define PICOP_CMD_STATUS_STATE_RESET_2_Val 0x2ul /**< \brief (PICOP_CMD_STATUS) Reset step 2 */ |
| 368 | #define PICOP_CMD_STATUS_STATE_RESET_3_Val 0x3ul /**< \brief (PICOP_CMD_STATUS) Reset step 3 */ |
| 369 | #define PICOP_CMD_STATUS_STATE_FUSE_CHECK_Val 0x4ul /**< \brief (PICOP_CMD_STATUS) Fuse check */ |
| 370 | #define PICOP_CMD_STATUS_STATE_INITIALIZED_Val 0x5ul /**< \brief (PICOP_CMD_STATUS) Initialized */ |
| 371 | #define PICOP_CMD_STATUS_STATE_STANDBY_Val 0x6ul /**< \brief (PICOP_CMD_STATUS) Standby */ |
| 372 | #define PICOP_CMD_STATUS_STATE_RUNNING_LOCKED_Val 0x8ul /**< \brief (PICOP_CMD_STATUS) Running locked */ |
| 373 | #define PICOP_CMD_STATUS_STATE_RUNNING_UNLOCK_1_Val 0x9ul /**< \brief (PICOP_CMD_STATUS) Running unlock step 1 */ |
| 374 | #define PICOP_CMD_STATUS_STATE_RUNNING_UNLOCK_2_Val 0xAul /**< \brief (PICOP_CMD_STATUS) Running unlock step 2 */ |
| 375 | #define PICOP_CMD_STATUS_STATE_RUNNING_UNLOCK_3_Val 0xBul /**< \brief (PICOP_CMD_STATUS) Running unlock step 3 */ |
| 376 | #define PICOP_CMD_STATUS_STATE_RUNNING_Val 0xCul /**< \brief (PICOP_CMD_STATUS) Running */ |
| 377 | #define PICOP_CMD_STATUS_STATE_RUNNING_BOOT_Val 0xDul /**< \brief (PICOP_CMD_STATUS) Running boot */ |
| 378 | #define PICOP_CMD_STATUS_STATE_RUNNING_HOSTOCD_Val 0xEul /**< \brief (PICOP_CMD_STATUS) Running hostocd */ |
| 379 | #define PICOP_CMD_STATUS_STATE_RESETTING_Val 0x10ul /**< \brief (PICOP_CMD_STATUS) Resetting */ |
| 380 | #define PICOP_CMD_STATUS_STATE_STOPPING_Val 0x11ul /**< \brief (PICOP_CMD_STATUS) Stopping */ |
| 381 | #define PICOP_CMD_STATUS_STATE_STOPPED_Val 0x12ul /**< \brief (PICOP_CMD_STATUS) Stopped */ |
| 382 | #define PICOP_CMD_STATUS_STATE_RESET_0 (PICOP_CMD_STATUS_STATE_RESET_0_Val << PICOP_CMD_STATUS_STATE_Pos) |
| 383 | #define PICOP_CMD_STATUS_STATE_RESET_1 (PICOP_CMD_STATUS_STATE_RESET_1_Val << PICOP_CMD_STATUS_STATE_Pos) |
| 384 | #define PICOP_CMD_STATUS_STATE_RESET_2 (PICOP_CMD_STATUS_STATE_RESET_2_Val << PICOP_CMD_STATUS_STATE_Pos) |
| 385 | #define PICOP_CMD_STATUS_STATE_RESET_3 (PICOP_CMD_STATUS_STATE_RESET_3_Val << PICOP_CMD_STATUS_STATE_Pos) |
| 386 | #define PICOP_CMD_STATUS_STATE_FUSE_CHECK (PICOP_CMD_STATUS_STATE_FUSE_CHECK_Val << PICOP_CMD_STATUS_STATE_Pos) |
| 387 | #define PICOP_CMD_STATUS_STATE_INITIALIZED (PICOP_CMD_STATUS_STATE_INITIALIZED_Val << PICOP_CMD_STATUS_STATE_Pos) |
| 388 | #define PICOP_CMD_STATUS_STATE_STANDBY (PICOP_CMD_STATUS_STATE_STANDBY_Val << PICOP_CMD_STATUS_STATE_Pos) |
| 389 | #define PICOP_CMD_STATUS_STATE_RUNNING_LOCKED (PICOP_CMD_STATUS_STATE_RUNNING_LOCKED_Val << PICOP_CMD_STATUS_STATE_Pos) |
| 390 | #define PICOP_CMD_STATUS_STATE_RUNNING_UNLOCK_1 (PICOP_CMD_STATUS_STATE_RUNNING_UNLOCK_1_Val << PICOP_CMD_STATUS_STATE_Pos) |
| 391 | #define PICOP_CMD_STATUS_STATE_RUNNING_UNLOCK_2 (PICOP_CMD_STATUS_STATE_RUNNING_UNLOCK_2_Val << PICOP_CMD_STATUS_STATE_Pos) |
| 392 | #define PICOP_CMD_STATUS_STATE_RUNNING_UNLOCK_3 (PICOP_CMD_STATUS_STATE_RUNNING_UNLOCK_3_Val << PICOP_CMD_STATUS_STATE_Pos) |
| 393 | #define PICOP_CMD_STATUS_STATE_RUNNING (PICOP_CMD_STATUS_STATE_RUNNING_Val << PICOP_CMD_STATUS_STATE_Pos) |
| 394 | #define PICOP_CMD_STATUS_STATE_RUNNING_BOOT (PICOP_CMD_STATUS_STATE_RUNNING_BOOT_Val << PICOP_CMD_STATUS_STATE_Pos) |
| 395 | #define PICOP_CMD_STATUS_STATE_RUNNING_HOSTOCD (PICOP_CMD_STATUS_STATE_RUNNING_HOSTOCD_Val << PICOP_CMD_STATUS_STATE_Pos) |
| 396 | #define PICOP_CMD_STATUS_STATE_RESETTING (PICOP_CMD_STATUS_STATE_RESETTING_Val << PICOP_CMD_STATUS_STATE_Pos) |
| 397 | #define PICOP_CMD_STATUS_STATE_STOPPING (PICOP_CMD_STATUS_STATE_STOPPING_Val << PICOP_CMD_STATUS_STATE_Pos) |
| 398 | #define PICOP_CMD_STATUS_STATE_STOPPED (PICOP_CMD_STATUS_STATE_STOPPED_Val << PICOP_CMD_STATUS_STATE_Pos) |
| 399 | #define PICOP_CMD_STATUS_MASK 0xF8FF077Ful /**< \brief (PICOP_CMD_STATUS) MASK Register */ |
| 400 | |
| 401 | /* -------- PICOP_PC : (PICOP Offset: 0x02C) (R/W 32) Program Counter -------- */ |
| 402 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 403 | typedef union { |
| 404 | struct { |
| 405 | uint32_t PC:16; /*!< bit: 0..15 Program Counter */ |
| 406 | uint32_t :16; /*!< bit: 16..31 Reserved */ |
| 407 | } bit; /*!< Structure used for bit access */ |
| 408 | uint32_t reg; /*!< Type used for register access */ |
| 409 | } PICOP_PC_Type; |
| 410 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 411 | |
| 412 | #define PICOP_PC_OFFSET 0x02C /**< \brief (PICOP_PC offset) Program Counter */ |
| 413 | #define PICOP_PC_RESETVALUE 0x00000000ul /**< \brief (PICOP_PC reset_value) Program Counter */ |
| 414 | |
| 415 | #define PICOP_PC_PC_Pos 0 /**< \brief (PICOP_PC) Program Counter */ |
| 416 | #define PICOP_PC_PC_Msk (0xFFFFul << PICOP_PC_PC_Pos) |
| 417 | #define PICOP_PC_PC(value) (PICOP_PC_PC_Msk & ((value) << PICOP_PC_PC_Pos)) |
| 418 | #define PICOP_PC_MASK 0x0000FFFFul /**< \brief (PICOP_PC) MASK Register */ |
| 419 | |
| 420 | /* -------- PICOP_HF : (PICOP Offset: 0x030) (R/W 32) Host Flags -------- */ |
| 421 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 422 | typedef union { |
| 423 | struct { |
| 424 | uint32_t HF:32; /*!< bit: 0..31 Host Flags */ |
| 425 | } bit; /*!< Structure used for bit access */ |
| 426 | uint32_t reg; /*!< Type used for register access */ |
| 427 | } PICOP_HF_Type; |
| 428 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 429 | |
| 430 | #define PICOP_HF_OFFSET 0x030 /**< \brief (PICOP_HF offset) Host Flags */ |
| 431 | #define PICOP_HF_RESETVALUE 0x00000000ul /**< \brief (PICOP_HF reset_value) Host Flags */ |
| 432 | |
| 433 | #define PICOP_HF_HF_Pos 0 /**< \brief (PICOP_HF) Host Flags */ |
| 434 | #define PICOP_HF_HF_Msk (0xFFFFFFFFul << PICOP_HF_HF_Pos) |
| 435 | #define PICOP_HF_HF(value) (PICOP_HF_HF_Msk & ((value) << PICOP_HF_HF_Pos)) |
| 436 | #define PICOP_HF_MASK 0xFFFFFFFFul /**< \brief (PICOP_HF) MASK Register */ |
| 437 | |
| 438 | /* -------- PICOP_HFCTRL : (PICOP Offset: 0x034) (R/W 32) Host Flag Control -------- */ |
| 439 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 440 | typedef union { |
| 441 | struct { |
| 442 | uint32_t :4; /*!< bit: 0.. 3 Reserved */ |
| 443 | uint32_t IRQENCLR:4; /*!< bit: 4.. 7 Host Flags IRQ Enable Clear */ |
| 444 | uint32_t :4; /*!< bit: 8..11 Reserved */ |
| 445 | uint32_t IRQENSET:4; /*!< bit: 12..15 Host Flags IRQ Enable Set */ |
| 446 | uint32_t :16; /*!< bit: 16..31 Reserved */ |
| 447 | } bit; /*!< Structure used for bit access */ |
| 448 | uint32_t reg; /*!< Type used for register access */ |
| 449 | } PICOP_HFCTRL_Type; |
| 450 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 451 | |
| 452 | #define PICOP_HFCTRL_OFFSET 0x034 /**< \brief (PICOP_HFCTRL offset) Host Flag Control */ |
| 453 | #define PICOP_HFCTRL_RESETVALUE 0x00000000ul /**< \brief (PICOP_HFCTRL reset_value) Host Flag Control */ |
| 454 | |
| 455 | #define PICOP_HFCTRL_IRQENCLR_Pos 4 /**< \brief (PICOP_HFCTRL) Host Flags IRQ Enable Clear */ |
| 456 | #define PICOP_HFCTRL_IRQENCLR_Msk (0xFul << PICOP_HFCTRL_IRQENCLR_Pos) |
| 457 | #define PICOP_HFCTRL_IRQENCLR(value) (PICOP_HFCTRL_IRQENCLR_Msk & ((value) << PICOP_HFCTRL_IRQENCLR_Pos)) |
| 458 | #define PICOP_HFCTRL_IRQENSET_Pos 12 /**< \brief (PICOP_HFCTRL) Host Flags IRQ Enable Set */ |
| 459 | #define PICOP_HFCTRL_IRQENSET_Msk (0xFul << PICOP_HFCTRL_IRQENSET_Pos) |
| 460 | #define PICOP_HFCTRL_IRQENSET(value) (PICOP_HFCTRL_IRQENSET_Msk & ((value) << PICOP_HFCTRL_IRQENSET_Pos)) |
| 461 | #define PICOP_HFCTRL_MASK 0x0000F0F0ul /**< \brief (PICOP_HFCTRL) MASK Register */ |
| 462 | |
| 463 | /* -------- PICOP_HFSETCLR0 : (PICOP Offset: 0x038) (R/W 32) Host Flags Set/Clr -------- */ |
| 464 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 465 | typedef union { |
| 466 | struct { |
| 467 | uint32_t HFCLR0:8; /*!< bit: 0.. 7 Host Flags Clear bits 7:0 */ |
| 468 | uint32_t HFSET0:8; /*!< bit: 8..15 Host Flags Set bits 7:0 */ |
| 469 | uint32_t HFCLR1:8; /*!< bit: 16..23 Host Flags Clear bits 15:8 */ |
| 470 | uint32_t HFSET1:8; /*!< bit: 24..31 Host Flags Set bits 15:8 */ |
| 471 | } bit; /*!< Structure used for bit access */ |
| 472 | uint32_t reg; /*!< Type used for register access */ |
| 473 | } PICOP_HFSETCLR0_Type; |
| 474 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 475 | |
| 476 | #define PICOP_HFSETCLR0_OFFSET 0x038 /**< \brief (PICOP_HFSETCLR0 offset) Host Flags Set/Clr */ |
| 477 | #define PICOP_HFSETCLR0_RESETVALUE 0x00000000ul /**< \brief (PICOP_HFSETCLR0 reset_value) Host Flags Set/Clr */ |
| 478 | |
| 479 | #define PICOP_HFSETCLR0_HFCLR0_Pos 0 /**< \brief (PICOP_HFSETCLR0) Host Flags Clear bits 7:0 */ |
| 480 | #define PICOP_HFSETCLR0_HFCLR0_Msk (0xFFul << PICOP_HFSETCLR0_HFCLR0_Pos) |
| 481 | #define PICOP_HFSETCLR0_HFCLR0(value) (PICOP_HFSETCLR0_HFCLR0_Msk & ((value) << PICOP_HFSETCLR0_HFCLR0_Pos)) |
| 482 | #define PICOP_HFSETCLR0_HFSET0_Pos 8 /**< \brief (PICOP_HFSETCLR0) Host Flags Set bits 7:0 */ |
| 483 | #define PICOP_HFSETCLR0_HFSET0_Msk (0xFFul << PICOP_HFSETCLR0_HFSET0_Pos) |
| 484 | #define PICOP_HFSETCLR0_HFSET0(value) (PICOP_HFSETCLR0_HFSET0_Msk & ((value) << PICOP_HFSETCLR0_HFSET0_Pos)) |
| 485 | #define PICOP_HFSETCLR0_HFCLR1_Pos 16 /**< \brief (PICOP_HFSETCLR0) Host Flags Clear bits 15:8 */ |
| 486 | #define PICOP_HFSETCLR0_HFCLR1_Msk (0xFFul << PICOP_HFSETCLR0_HFCLR1_Pos) |
| 487 | #define PICOP_HFSETCLR0_HFCLR1(value) (PICOP_HFSETCLR0_HFCLR1_Msk & ((value) << PICOP_HFSETCLR0_HFCLR1_Pos)) |
| 488 | #define PICOP_HFSETCLR0_HFSET1_Pos 24 /**< \brief (PICOP_HFSETCLR0) Host Flags Set bits 15:8 */ |
| 489 | #define PICOP_HFSETCLR0_HFSET1_Msk (0xFFul << PICOP_HFSETCLR0_HFSET1_Pos) |
| 490 | #define PICOP_HFSETCLR0_HFSET1(value) (PICOP_HFSETCLR0_HFSET1_Msk & ((value) << PICOP_HFSETCLR0_HFSET1_Pos)) |
| 491 | #define PICOP_HFSETCLR0_MASK 0xFFFFFFFFul /**< \brief (PICOP_HFSETCLR0) MASK Register */ |
| 492 | |
| 493 | /* -------- PICOP_HFSETCLR1 : (PICOP Offset: 0x03C) (R/W 32) Host Flags Set/Clr -------- */ |
| 494 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 495 | typedef union { |
| 496 | struct { |
| 497 | uint32_t HFCLR2:8; /*!< bit: 0.. 7 Host Flags Clear bits 23:16 */ |
| 498 | uint32_t HFSET2:8; /*!< bit: 8..15 Host Flags Set bits 23:16 */ |
| 499 | uint32_t HFCLR3:8; /*!< bit: 16..23 Host Flags Clear bits 31:24 */ |
| 500 | uint32_t HFSET3:8; /*!< bit: 24..31 Host Flags Set bits 31:24 */ |
| 501 | } bit; /*!< Structure used for bit access */ |
| 502 | uint32_t reg; /*!< Type used for register access */ |
| 503 | } PICOP_HFSETCLR1_Type; |
| 504 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 505 | |
| 506 | #define PICOP_HFSETCLR1_OFFSET 0x03C /**< \brief (PICOP_HFSETCLR1 offset) Host Flags Set/Clr */ |
| 507 | #define PICOP_HFSETCLR1_RESETVALUE 0x00000000ul /**< \brief (PICOP_HFSETCLR1 reset_value) Host Flags Set/Clr */ |
| 508 | |
| 509 | #define PICOP_HFSETCLR1_HFCLR2_Pos 0 /**< \brief (PICOP_HFSETCLR1) Host Flags Clear bits 23:16 */ |
| 510 | #define PICOP_HFSETCLR1_HFCLR2_Msk (0xFFul << PICOP_HFSETCLR1_HFCLR2_Pos) |
| 511 | #define PICOP_HFSETCLR1_HFCLR2(value) (PICOP_HFSETCLR1_HFCLR2_Msk & ((value) << PICOP_HFSETCLR1_HFCLR2_Pos)) |
| 512 | #define PICOP_HFSETCLR1_HFSET2_Pos 8 /**< \brief (PICOP_HFSETCLR1) Host Flags Set bits 23:16 */ |
| 513 | #define PICOP_HFSETCLR1_HFSET2_Msk (0xFFul << PICOP_HFSETCLR1_HFSET2_Pos) |
| 514 | #define PICOP_HFSETCLR1_HFSET2(value) (PICOP_HFSETCLR1_HFSET2_Msk & ((value) << PICOP_HFSETCLR1_HFSET2_Pos)) |
| 515 | #define PICOP_HFSETCLR1_HFCLR3_Pos 16 /**< \brief (PICOP_HFSETCLR1) Host Flags Clear bits 31:24 */ |
| 516 | #define PICOP_HFSETCLR1_HFCLR3_Msk (0xFFul << PICOP_HFSETCLR1_HFCLR3_Pos) |
| 517 | #define PICOP_HFSETCLR1_HFCLR3(value) (PICOP_HFSETCLR1_HFCLR3_Msk & ((value) << PICOP_HFSETCLR1_HFCLR3_Pos)) |
| 518 | #define PICOP_HFSETCLR1_HFSET3_Pos 24 /**< \brief (PICOP_HFSETCLR1) Host Flags Set bits 31:24 */ |
| 519 | #define PICOP_HFSETCLR1_HFSET3_Msk (0xFFul << PICOP_HFSETCLR1_HFSET3_Pos) |
| 520 | #define PICOP_HFSETCLR1_HFSET3(value) (PICOP_HFSETCLR1_HFSET3_Msk & ((value) << PICOP_HFSETCLR1_HFSET3_Pos)) |
| 521 | #define PICOP_HFSETCLR1_MASK 0xFFFFFFFFul /**< \brief (PICOP_HFSETCLR1) MASK Register */ |
| 522 | |
| 523 | /* -------- PICOP_OCDCONFIG : (PICOP Offset: 0x050) (R/W 32) OCD Configuration -------- */ |
| 524 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 525 | typedef union { |
| 526 | struct { |
| 527 | uint32_t :1; /*!< bit: 0 Reserved */ |
| 528 | uint32_t CCNTEN:1; /*!< bit: 1 Cycle Counter Enable */ |
| 529 | uint32_t :30; /*!< bit: 2..31 Reserved */ |
| 530 | } bit; /*!< Structure used for bit access */ |
| 531 | uint32_t reg; /*!< Type used for register access */ |
| 532 | } PICOP_OCDCONFIG_Type; |
| 533 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 534 | |
| 535 | #define PICOP_OCDCONFIG_OFFSET 0x050 /**< \brief (PICOP_OCDCONFIG offset) OCD Configuration */ |
| 536 | #define PICOP_OCDCONFIG_RESETVALUE 0x00000000ul /**< \brief (PICOP_OCDCONFIG reset_value) OCD Configuration */ |
| 537 | |
| 538 | #define PICOP_OCDCONFIG_CCNTEN_Pos 1 /**< \brief (PICOP_OCDCONFIG) Cycle Counter Enable */ |
| 539 | #define PICOP_OCDCONFIG_CCNTEN (0x1ul << PICOP_OCDCONFIG_CCNTEN_Pos) |
| 540 | #define PICOP_OCDCONFIG_MASK 0x00000002ul /**< \brief (PICOP_OCDCONFIG) MASK Register */ |
| 541 | |
| 542 | /* -------- PICOP_OCDCONTROL : (PICOP Offset: 0x054) (R/W 32) OCD Control -------- */ |
| 543 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 544 | typedef union { |
| 545 | struct { |
| 546 | uint32_t OCDEN:1; /*!< bit: 0 OCD Enable */ |
| 547 | uint32_t :1; /*!< bit: 1 Reserved */ |
| 548 | uint32_t BPSSTEP:1; /*!< bit: 2 Single Step Breakpoint */ |
| 549 | uint32_t BPCOF:1; /*!< bit: 3 Change of Flow Breakpoint */ |
| 550 | uint32_t BPRST:1; /*!< bit: 4 Reset Breakpoint */ |
| 551 | uint32_t BPEXCEPTION:1; /*!< bit: 5 Exception Breakpoint */ |
| 552 | uint32_t BPIRQ:1; /*!< bit: 6 Interrupt Request Breakpoint */ |
| 553 | uint32_t BPSW:1; /*!< bit: 7 Software Breakpoint */ |
| 554 | uint32_t BPSLEEP:1; /*!< bit: 8 Sleep Breakpoint */ |
| 555 | uint32_t BPWDT:1; /*!< bit: 9 Watchdog Timer Breakpoint */ |
| 556 | uint32_t BPISA:1; /*!< bit: 10 ISA Breakpoint */ |
| 557 | uint32_t :1; /*!< bit: 11 Reserved */ |
| 558 | uint32_t BPCOMP:4; /*!< bit: 12..15 Comparator Breakpoint */ |
| 559 | uint32_t BPGENMODE:4; /*!< bit: 16..19 Breakpoint Generator n Mode */ |
| 560 | uint32_t :12; /*!< bit: 20..31 Reserved */ |
| 561 | } bit; /*!< Structure used for bit access */ |
| 562 | uint32_t reg; /*!< Type used for register access */ |
| 563 | } PICOP_OCDCONTROL_Type; |
| 564 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 565 | |
| 566 | #define PICOP_OCDCONTROL_OFFSET 0x054 /**< \brief (PICOP_OCDCONTROL offset) OCD Control */ |
| 567 | #define PICOP_OCDCONTROL_RESETVALUE 0x00000000ul /**< \brief (PICOP_OCDCONTROL reset_value) OCD Control */ |
| 568 | |
| 569 | #define PICOP_OCDCONTROL_OCDEN_Pos 0 /**< \brief (PICOP_OCDCONTROL) OCD Enable */ |
| 570 | #define PICOP_OCDCONTROL_OCDEN (0x1ul << PICOP_OCDCONTROL_OCDEN_Pos) |
| 571 | #define PICOP_OCDCONTROL_BPSSTEP_Pos 2 /**< \brief (PICOP_OCDCONTROL) Single Step Breakpoint */ |
| 572 | #define PICOP_OCDCONTROL_BPSSTEP (0x1ul << PICOP_OCDCONTROL_BPSSTEP_Pos) |
| 573 | #define PICOP_OCDCONTROL_BPCOF_Pos 3 /**< \brief (PICOP_OCDCONTROL) Change of Flow Breakpoint */ |
| 574 | #define PICOP_OCDCONTROL_BPCOF (0x1ul << PICOP_OCDCONTROL_BPCOF_Pos) |
| 575 | #define PICOP_OCDCONTROL_BPRST_Pos 4 /**< \brief (PICOP_OCDCONTROL) Reset Breakpoint */ |
| 576 | #define PICOP_OCDCONTROL_BPRST (0x1ul << PICOP_OCDCONTROL_BPRST_Pos) |
| 577 | #define PICOP_OCDCONTROL_BPEXCEPTION_Pos 5 /**< \brief (PICOP_OCDCONTROL) Exception Breakpoint */ |
| 578 | #define PICOP_OCDCONTROL_BPEXCEPTION (0x1ul << PICOP_OCDCONTROL_BPEXCEPTION_Pos) |
| 579 | #define PICOP_OCDCONTROL_BPIRQ_Pos 6 /**< \brief (PICOP_OCDCONTROL) Interrupt Request Breakpoint */ |
| 580 | #define PICOP_OCDCONTROL_BPIRQ (0x1ul << PICOP_OCDCONTROL_BPIRQ_Pos) |
| 581 | #define PICOP_OCDCONTROL_BPSW_Pos 7 /**< \brief (PICOP_OCDCONTROL) Software Breakpoint */ |
| 582 | #define PICOP_OCDCONTROL_BPSW (0x1ul << PICOP_OCDCONTROL_BPSW_Pos) |
| 583 | #define PICOP_OCDCONTROL_BPSLEEP_Pos 8 /**< \brief (PICOP_OCDCONTROL) Sleep Breakpoint */ |
| 584 | #define PICOP_OCDCONTROL_BPSLEEP (0x1ul << PICOP_OCDCONTROL_BPSLEEP_Pos) |
| 585 | #define PICOP_OCDCONTROL_BPWDT_Pos 9 /**< \brief (PICOP_OCDCONTROL) Watchdog Timer Breakpoint */ |
| 586 | #define PICOP_OCDCONTROL_BPWDT (0x1ul << PICOP_OCDCONTROL_BPWDT_Pos) |
| 587 | #define PICOP_OCDCONTROL_BPISA_Pos 10 /**< \brief (PICOP_OCDCONTROL) ISA Breakpoint */ |
| 588 | #define PICOP_OCDCONTROL_BPISA (0x1ul << PICOP_OCDCONTROL_BPISA_Pos) |
| 589 | #define PICOP_OCDCONTROL_BPCOMP_Pos 12 /**< \brief (PICOP_OCDCONTROL) Comparator Breakpoint */ |
| 590 | #define PICOP_OCDCONTROL_BPCOMP_Msk (0xFul << PICOP_OCDCONTROL_BPCOMP_Pos) |
| 591 | #define PICOP_OCDCONTROL_BPCOMP(value) (PICOP_OCDCONTROL_BPCOMP_Msk & ((value) << PICOP_OCDCONTROL_BPCOMP_Pos)) |
| 592 | #define PICOP_OCDCONTROL_BPGENMODE_Pos 16 /**< \brief (PICOP_OCDCONTROL) Breakpoint Generator n Mode */ |
| 593 | #define PICOP_OCDCONTROL_BPGENMODE_Msk (0xFul << PICOP_OCDCONTROL_BPGENMODE_Pos) |
| 594 | #define PICOP_OCDCONTROL_BPGENMODE(value) (PICOP_OCDCONTROL_BPGENMODE_Msk & ((value) << PICOP_OCDCONTROL_BPGENMODE_Pos)) |
| 595 | #define PICOP_OCDCONTROL_MASK 0x000FF7FDul /**< \brief (PICOP_OCDCONTROL) MASK Register */ |
| 596 | |
| 597 | /* -------- PICOP_OCDSTATUS : (PICOP Offset: 0x058) (R/W 32) OCD Status and Command -------- */ |
| 598 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 599 | typedef union { |
| 600 | struct { // CMD mode |
| 601 | uint32_t INST:16; /*!< bit: 0..15 Instruction Override */ |
| 602 | uint32_t :16; /*!< bit: 16..31 Reserved */ |
| 603 | } CMD; /*!< Structure used for CMD */ |
| 604 | struct { // STATUS mode |
| 605 | uint32_t :1; /*!< bit: 0 Reserved */ |
| 606 | uint32_t BPEXT:1; /*!< bit: 1 External Breakpoint */ |
| 607 | uint32_t BPSSTEP:1; /*!< bit: 2 Single Step Breakpoint */ |
| 608 | uint32_t BPCOF:1; /*!< bit: 3 Change of Flow Breakpoint */ |
| 609 | uint32_t BPRST:1; /*!< bit: 4 Reset Breakpoint */ |
| 610 | uint32_t BPEXCEPTION:1; /*!< bit: 5 Exception Breakpoint */ |
| 611 | uint32_t BPIRQ:1; /*!< bit: 6 Interrupt Request Breakpoint */ |
| 612 | uint32_t BPSW:1; /*!< bit: 7 Software Breakpoint */ |
| 613 | uint32_t BPSLEEP:1; /*!< bit: 8 Sleep Breakpoint */ |
| 614 | uint32_t BPWDT:1; /*!< bit: 9 Watchdog Timer Breakpoint */ |
| 615 | uint32_t BPISA:1; /*!< bit: 10 ISA Breakpoint */ |
| 616 | uint32_t :1; /*!< bit: 11 Reserved */ |
| 617 | uint32_t BPCOMP:4; /*!< bit: 12..15 Comparator Breakpoint */ |
| 618 | uint32_t :16; /*!< bit: 16..31 Reserved */ |
| 619 | } STATUS; /*!< Structure used for STATUS */ |
| 620 | uint32_t reg; /*!< Type used for register access */ |
| 621 | } PICOP_OCDSTATUS_Type; |
| 622 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 623 | |
| 624 | #define PICOP_OCDSTATUS_OFFSET 0x058 /**< \brief (PICOP_OCDSTATUS offset) OCD Status and Command */ |
| 625 | #define PICOP_OCDSTATUS_RESETVALUE 0x00000000ul /**< \brief (PICOP_OCDSTATUS reset_value) OCD Status and Command */ |
| 626 | |
| 627 | // CMD mode |
| 628 | #define PICOP_OCDSTATUS_CMD_INST_Pos 0 /**< \brief (PICOP_OCDSTATUS_CMD) Instruction Override */ |
| 629 | #define PICOP_OCDSTATUS_CMD_INST_Msk (0xFFFFul << PICOP_OCDSTATUS_CMD_INST_Pos) |
| 630 | #define PICOP_OCDSTATUS_CMD_INST(value) (PICOP_OCDSTATUS_CMD_INST_Msk & ((value) << PICOP_OCDSTATUS_CMD_INST_Pos)) |
| 631 | #define PICOP_OCDSTATUS_CMD_MASK 0x0000FFFFul /**< \brief (PICOP_OCDSTATUS_CMD) MASK Register */ |
| 632 | |
| 633 | // STATUS mode |
| 634 | #define PICOP_OCDSTATUS_STATUS_BPEXT_Pos 1 /**< \brief (PICOP_OCDSTATUS_STATUS) External Breakpoint */ |
| 635 | #define PICOP_OCDSTATUS_STATUS_BPEXT (0x1ul << PICOP_OCDSTATUS_STATUS_BPEXT_Pos) |
| 636 | #define PICOP_OCDSTATUS_STATUS_BPSSTEP_Pos 2 /**< \brief (PICOP_OCDSTATUS_STATUS) Single Step Breakpoint */ |
| 637 | #define PICOP_OCDSTATUS_STATUS_BPSSTEP (0x1ul << PICOP_OCDSTATUS_STATUS_BPSSTEP_Pos) |
| 638 | #define PICOP_OCDSTATUS_STATUS_BPCOF_Pos 3 /**< \brief (PICOP_OCDSTATUS_STATUS) Change of Flow Breakpoint */ |
| 639 | #define PICOP_OCDSTATUS_STATUS_BPCOF (0x1ul << PICOP_OCDSTATUS_STATUS_BPCOF_Pos) |
| 640 | #define PICOP_OCDSTATUS_STATUS_BPRST_Pos 4 /**< \brief (PICOP_OCDSTATUS_STATUS) Reset Breakpoint */ |
| 641 | #define PICOP_OCDSTATUS_STATUS_BPRST (0x1ul << PICOP_OCDSTATUS_STATUS_BPRST_Pos) |
| 642 | #define PICOP_OCDSTATUS_STATUS_BPEXCEPTION_Pos 5 /**< \brief (PICOP_OCDSTATUS_STATUS) Exception Breakpoint */ |
| 643 | #define PICOP_OCDSTATUS_STATUS_BPEXCEPTION (0x1ul << PICOP_OCDSTATUS_STATUS_BPEXCEPTION_Pos) |
| 644 | #define PICOP_OCDSTATUS_STATUS_BPIRQ_Pos 6 /**< \brief (PICOP_OCDSTATUS_STATUS) Interrupt Request Breakpoint */ |
| 645 | #define PICOP_OCDSTATUS_STATUS_BPIRQ (0x1ul << PICOP_OCDSTATUS_STATUS_BPIRQ_Pos) |
| 646 | #define PICOP_OCDSTATUS_STATUS_BPSW_Pos 7 /**< \brief (PICOP_OCDSTATUS_STATUS) Software Breakpoint */ |
| 647 | #define PICOP_OCDSTATUS_STATUS_BPSW (0x1ul << PICOP_OCDSTATUS_STATUS_BPSW_Pos) |
| 648 | #define PICOP_OCDSTATUS_STATUS_BPSLEEP_Pos 8 /**< \brief (PICOP_OCDSTATUS_STATUS) Sleep Breakpoint */ |
| 649 | #define PICOP_OCDSTATUS_STATUS_BPSLEEP (0x1ul << PICOP_OCDSTATUS_STATUS_BPSLEEP_Pos) |
| 650 | #define PICOP_OCDSTATUS_STATUS_BPWDT_Pos 9 /**< \brief (PICOP_OCDSTATUS_STATUS) Watchdog Timer Breakpoint */ |
| 651 | #define PICOP_OCDSTATUS_STATUS_BPWDT (0x1ul << PICOP_OCDSTATUS_STATUS_BPWDT_Pos) |
| 652 | #define PICOP_OCDSTATUS_STATUS_BPISA_Pos 10 /**< \brief (PICOP_OCDSTATUS_STATUS) ISA Breakpoint */ |
| 653 | #define PICOP_OCDSTATUS_STATUS_BPISA (0x1ul << PICOP_OCDSTATUS_STATUS_BPISA_Pos) |
| 654 | #define PICOP_OCDSTATUS_STATUS_BPCOMP_Pos 12 /**< \brief (PICOP_OCDSTATUS_STATUS) Comparator Breakpoint */ |
| 655 | #define PICOP_OCDSTATUS_STATUS_BPCOMP_Msk (0xFul << PICOP_OCDSTATUS_STATUS_BPCOMP_Pos) |
| 656 | #define PICOP_OCDSTATUS_STATUS_BPCOMP(value) (PICOP_OCDSTATUS_STATUS_BPCOMP_Msk & ((value) << PICOP_OCDSTATUS_STATUS_BPCOMP_Pos)) |
| 657 | #define PICOP_OCDSTATUS_STATUS_MASK 0x0000F7FEul /**< \brief (PICOP_OCDSTATUS_STATUS) MASK Register */ |
| 658 | |
| 659 | /* -------- PICOP_OCDPC : (PICOP Offset: 0x05C) (R/W 32) ODC Program Counter -------- */ |
| 660 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 661 | typedef union { |
| 662 | struct { |
| 663 | uint32_t PC:16; /*!< bit: 0..15 Program Counter */ |
| 664 | uint32_t :16; /*!< bit: 16..31 Reserved */ |
| 665 | } bit; /*!< Structure used for bit access */ |
| 666 | uint32_t reg; /*!< Type used for register access */ |
| 667 | } PICOP_OCDPC_Type; |
| 668 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 669 | |
| 670 | #define PICOP_OCDPC_OFFSET 0x05C /**< \brief (PICOP_OCDPC offset) ODC Program Counter */ |
| 671 | |
| 672 | #define PICOP_OCDPC_PC_Pos 0 /**< \brief (PICOP_OCDPC) Program Counter */ |
| 673 | #define PICOP_OCDPC_PC_Msk (0xFFFFul << PICOP_OCDPC_PC_Pos) |
| 674 | #define PICOP_OCDPC_PC(value) (PICOP_OCDPC_PC_Msk & ((value) << PICOP_OCDPC_PC_Pos)) |
| 675 | #define PICOP_OCDPC_MASK 0x0000FFFFul /**< \brief (PICOP_OCDPC) MASK Register */ |
| 676 | |
| 677 | /* -------- PICOP_OCDFEAT : (PICOP Offset: 0x060) (R/W 32) OCD Features -------- */ |
| 678 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 679 | typedef union { |
| 680 | struct { |
| 681 | uint32_t CCNT:2; /*!< bit: 0.. 1 Cycle Counter */ |
| 682 | uint32_t BPGEN:2; /*!< bit: 2.. 3 Breakpoint Generators */ |
| 683 | uint32_t :28; /*!< bit: 4..31 Reserved */ |
| 684 | } bit; /*!< Structure used for bit access */ |
| 685 | uint32_t reg; /*!< Type used for register access */ |
| 686 | } PICOP_OCDFEAT_Type; |
| 687 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 688 | |
| 689 | #define PICOP_OCDFEAT_OFFSET 0x060 /**< \brief (PICOP_OCDFEAT offset) OCD Features */ |
| 690 | #define PICOP_OCDFEAT_RESETVALUE 0x00000000ul /**< \brief (PICOP_OCDFEAT reset_value) OCD Features */ |
| 691 | |
| 692 | #define PICOP_OCDFEAT_CCNT_Pos 0 /**< \brief (PICOP_OCDFEAT) Cycle Counter */ |
| 693 | #define PICOP_OCDFEAT_CCNT_Msk (0x3ul << PICOP_OCDFEAT_CCNT_Pos) |
| 694 | #define PICOP_OCDFEAT_CCNT(value) (PICOP_OCDFEAT_CCNT_Msk & ((value) << PICOP_OCDFEAT_CCNT_Pos)) |
| 695 | #define PICOP_OCDFEAT_BPGEN_Pos 2 /**< \brief (PICOP_OCDFEAT) Breakpoint Generators */ |
| 696 | #define PICOP_OCDFEAT_BPGEN_Msk (0x3ul << PICOP_OCDFEAT_BPGEN_Pos) |
| 697 | #define PICOP_OCDFEAT_BPGEN(value) (PICOP_OCDFEAT_BPGEN_Msk & ((value) << PICOP_OCDFEAT_BPGEN_Pos)) |
| 698 | #define PICOP_OCDFEAT_MASK 0x0000000Ful /**< \brief (PICOP_OCDFEAT) MASK Register */ |
| 699 | |
| 700 | /* -------- PICOP_OCDCCNT : (PICOP Offset: 0x068) (R/W 32) OCD Cycle Counter -------- */ |
| 701 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 702 | typedef union { |
| 703 | struct { |
| 704 | uint32_t CCNT:32; /*!< bit: 0..31 Cycle Count */ |
| 705 | } bit; /*!< Structure used for bit access */ |
| 706 | uint32_t reg; /*!< Type used for register access */ |
| 707 | } PICOP_OCDCCNT_Type; |
| 708 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 709 | |
| 710 | #define PICOP_OCDCCNT_OFFSET 0x068 /**< \brief (PICOP_OCDCCNT offset) OCD Cycle Counter */ |
| 711 | #define PICOP_OCDCCNT_RESETVALUE 0x00000000ul /**< \brief (PICOP_OCDCCNT reset_value) OCD Cycle Counter */ |
| 712 | |
| 713 | #define PICOP_OCDCCNT_CCNT_Pos 0 /**< \brief (PICOP_OCDCCNT) Cycle Count */ |
| 714 | #define PICOP_OCDCCNT_CCNT_Msk (0xFFFFFFFFul << PICOP_OCDCCNT_CCNT_Pos) |
| 715 | #define PICOP_OCDCCNT_CCNT(value) (PICOP_OCDCCNT_CCNT_Msk & ((value) << PICOP_OCDCCNT_CCNT_Pos)) |
| 716 | #define PICOP_OCDCCNT_MASK 0xFFFFFFFFul /**< \brief (PICOP_OCDCCNT) MASK Register */ |
| 717 | |
| 718 | /* -------- PICOP_OCDBPGEN : (PICOP Offset: 0x070) (R/W 32) OCD Breakpoint Generator n -------- */ |
| 719 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 720 | typedef union { |
| 721 | struct { |
| 722 | uint32_t BPGEN:16; /*!< bit: 0..15 Breakpoint Generator */ |
| 723 | uint32_t :16; /*!< bit: 16..31 Reserved */ |
| 724 | } bit; /*!< Structure used for bit access */ |
| 725 | uint32_t reg; /*!< Type used for register access */ |
| 726 | } PICOP_OCDBPGEN_Type; |
| 727 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 728 | |
| 729 | #define PICOP_OCDBPGEN_OFFSET 0x070 /**< \brief (PICOP_OCDBPGEN offset) OCD Breakpoint Generator n */ |
| 730 | #define PICOP_OCDBPGEN_RESETVALUE 0x00000000ul /**< \brief (PICOP_OCDBPGEN reset_value) OCD Breakpoint Generator n */ |
| 731 | |
| 732 | #define PICOP_OCDBPGEN_BPGEN_Pos 0 /**< \brief (PICOP_OCDBPGEN) Breakpoint Generator */ |
| 733 | #define PICOP_OCDBPGEN_BPGEN_Msk (0xFFFFul << PICOP_OCDBPGEN_BPGEN_Pos) |
| 734 | #define PICOP_OCDBPGEN_BPGEN(value) (PICOP_OCDBPGEN_BPGEN_Msk & ((value) << PICOP_OCDBPGEN_BPGEN_Pos)) |
| 735 | #define PICOP_OCDBPGEN_MASK 0x0000FFFFul /**< \brief (PICOP_OCDBPGEN) MASK Register */ |
| 736 | |
| 737 | /* -------- PICOP_R3R0 : (PICOP Offset: 0x080) (R/W 32) R3 to 0 -------- */ |
| 738 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 739 | typedef union { |
| 740 | struct { |
| 741 | uint32_t R0:8; /*!< bit: 0.. 7 Register 0 */ |
| 742 | uint32_t R1:8; /*!< bit: 8..15 Register 1 */ |
| 743 | uint32_t R2:8; /*!< bit: 16..23 Register 2 */ |
| 744 | uint32_t R3:8; /*!< bit: 24..31 Register 3 */ |
| 745 | } bit; /*!< Structure used for bit access */ |
| 746 | uint32_t reg; /*!< Type used for register access */ |
| 747 | } PICOP_R3R0_Type; |
| 748 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 749 | |
| 750 | #define PICOP_R3R0_OFFSET 0x080 /**< \brief (PICOP_R3R0 offset) R3 to 0 */ |
| 751 | |
| 752 | #define PICOP_R3R0_R0_Pos 0 /**< \brief (PICOP_R3R0) Register 0 */ |
| 753 | #define PICOP_R3R0_R0_Msk (0xFFul << PICOP_R3R0_R0_Pos) |
| 754 | #define PICOP_R3R0_R0(value) (PICOP_R3R0_R0_Msk & ((value) << PICOP_R3R0_R0_Pos)) |
| 755 | #define PICOP_R3R0_R1_Pos 8 /**< \brief (PICOP_R3R0) Register 1 */ |
| 756 | #define PICOP_R3R0_R1_Msk (0xFFul << PICOP_R3R0_R1_Pos) |
| 757 | #define PICOP_R3R0_R1(value) (PICOP_R3R0_R1_Msk & ((value) << PICOP_R3R0_R1_Pos)) |
| 758 | #define PICOP_R3R0_R2_Pos 16 /**< \brief (PICOP_R3R0) Register 2 */ |
| 759 | #define PICOP_R3R0_R2_Msk (0xFFul << PICOP_R3R0_R2_Pos) |
| 760 | #define PICOP_R3R0_R2(value) (PICOP_R3R0_R2_Msk & ((value) << PICOP_R3R0_R2_Pos)) |
| 761 | #define PICOP_R3R0_R3_Pos 24 /**< \brief (PICOP_R3R0) Register 3 */ |
| 762 | #define PICOP_R3R0_R3_Msk (0xFFul << PICOP_R3R0_R3_Pos) |
| 763 | #define PICOP_R3R0_R3(value) (PICOP_R3R0_R3_Msk & ((value) << PICOP_R3R0_R3_Pos)) |
| 764 | #define PICOP_R3R0_MASK 0xFFFFFFFFul /**< \brief (PICOP_R3R0) MASK Register */ |
| 765 | |
| 766 | /* -------- PICOP_R7R4 : (PICOP Offset: 0x084) (R/W 32) R7 to 4 -------- */ |
| 767 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 768 | typedef union { |
| 769 | struct { |
| 770 | uint32_t R0:8; /*!< bit: 0.. 7 Register 0 */ |
| 771 | uint32_t R1:8; /*!< bit: 8..15 Register 1 */ |
| 772 | uint32_t R2:8; /*!< bit: 16..23 Register 2 */ |
| 773 | uint32_t R3:8; /*!< bit: 24..31 Register 3 */ |
| 774 | } bit; /*!< Structure used for bit access */ |
| 775 | uint32_t reg; /*!< Type used for register access */ |
| 776 | } PICOP_R7R4_Type; |
| 777 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 778 | |
| 779 | #define PICOP_R7R4_OFFSET 0x084 /**< \brief (PICOP_R7R4 offset) R7 to 4 */ |
| 780 | |
| 781 | #define PICOP_R7R4_R0_Pos 0 /**< \brief (PICOP_R7R4) Register 0 */ |
| 782 | #define PICOP_R7R4_R0_Msk (0xFFul << PICOP_R7R4_R0_Pos) |
| 783 | #define PICOP_R7R4_R0(value) (PICOP_R7R4_R0_Msk & ((value) << PICOP_R7R4_R0_Pos)) |
| 784 | #define PICOP_R7R4_R1_Pos 8 /**< \brief (PICOP_R7R4) Register 1 */ |
| 785 | #define PICOP_R7R4_R1_Msk (0xFFul << PICOP_R7R4_R1_Pos) |
| 786 | #define PICOP_R7R4_R1(value) (PICOP_R7R4_R1_Msk & ((value) << PICOP_R7R4_R1_Pos)) |
| 787 | #define PICOP_R7R4_R2_Pos 16 /**< \brief (PICOP_R7R4) Register 2 */ |
| 788 | #define PICOP_R7R4_R2_Msk (0xFFul << PICOP_R7R4_R2_Pos) |
| 789 | #define PICOP_R7R4_R2(value) (PICOP_R7R4_R2_Msk & ((value) << PICOP_R7R4_R2_Pos)) |
| 790 | #define PICOP_R7R4_R3_Pos 24 /**< \brief (PICOP_R7R4) Register 3 */ |
| 791 | #define PICOP_R7R4_R3_Msk (0xFFul << PICOP_R7R4_R3_Pos) |
| 792 | #define PICOP_R7R4_R3(value) (PICOP_R7R4_R3_Msk & ((value) << PICOP_R7R4_R3_Pos)) |
| 793 | #define PICOP_R7R4_MASK 0xFFFFFFFFul /**< \brief (PICOP_R7R4) MASK Register */ |
| 794 | |
| 795 | /* -------- PICOP_R11R8 : (PICOP Offset: 0x088) (R/W 32) R11 to 8 -------- */ |
| 796 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 797 | typedef union { |
| 798 | struct { |
| 799 | uint32_t R0:8; /*!< bit: 0.. 7 Register 0 */ |
| 800 | uint32_t R1:8; /*!< bit: 8..15 Register 1 */ |
| 801 | uint32_t R2:8; /*!< bit: 16..23 Register 2 */ |
| 802 | uint32_t R3:8; /*!< bit: 24..31 Register 3 */ |
| 803 | } bit; /*!< Structure used for bit access */ |
| 804 | uint32_t reg; /*!< Type used for register access */ |
| 805 | } PICOP_R11R8_Type; |
| 806 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 807 | |
| 808 | #define PICOP_R11R8_OFFSET 0x088 /**< \brief (PICOP_R11R8 offset) R11 to 8 */ |
| 809 | |
| 810 | #define PICOP_R11R8_R0_Pos 0 /**< \brief (PICOP_R11R8) Register 0 */ |
| 811 | #define PICOP_R11R8_R0_Msk (0xFFul << PICOP_R11R8_R0_Pos) |
| 812 | #define PICOP_R11R8_R0(value) (PICOP_R11R8_R0_Msk & ((value) << PICOP_R11R8_R0_Pos)) |
| 813 | #define PICOP_R11R8_R1_Pos 8 /**< \brief (PICOP_R11R8) Register 1 */ |
| 814 | #define PICOP_R11R8_R1_Msk (0xFFul << PICOP_R11R8_R1_Pos) |
| 815 | #define PICOP_R11R8_R1(value) (PICOP_R11R8_R1_Msk & ((value) << PICOP_R11R8_R1_Pos)) |
| 816 | #define PICOP_R11R8_R2_Pos 16 /**< \brief (PICOP_R11R8) Register 2 */ |
| 817 | #define PICOP_R11R8_R2_Msk (0xFFul << PICOP_R11R8_R2_Pos) |
| 818 | #define PICOP_R11R8_R2(value) (PICOP_R11R8_R2_Msk & ((value) << PICOP_R11R8_R2_Pos)) |
| 819 | #define PICOP_R11R8_R3_Pos 24 /**< \brief (PICOP_R11R8) Register 3 */ |
| 820 | #define PICOP_R11R8_R3_Msk (0xFFul << PICOP_R11R8_R3_Pos) |
| 821 | #define PICOP_R11R8_R3(value) (PICOP_R11R8_R3_Msk & ((value) << PICOP_R11R8_R3_Pos)) |
| 822 | #define PICOP_R11R8_MASK 0xFFFFFFFFul /**< \brief (PICOP_R11R8) MASK Register */ |
| 823 | |
| 824 | /* -------- PICOP_R15R12 : (PICOP Offset: 0x08C) (R/W 32) R15 to 12 -------- */ |
| 825 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 826 | typedef union { |
| 827 | struct { |
| 828 | uint32_t R0:8; /*!< bit: 0.. 7 Register 0 */ |
| 829 | uint32_t R1:8; /*!< bit: 8..15 Register 1 */ |
| 830 | uint32_t R2:8; /*!< bit: 16..23 Register 2 */ |
| 831 | uint32_t R3:8; /*!< bit: 24..31 Register 3 */ |
| 832 | } bit; /*!< Structure used for bit access */ |
| 833 | uint32_t reg; /*!< Type used for register access */ |
| 834 | } PICOP_R15R12_Type; |
| 835 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 836 | |
| 837 | #define PICOP_R15R12_OFFSET 0x08C /**< \brief (PICOP_R15R12 offset) R15 to 12 */ |
| 838 | |
| 839 | #define PICOP_R15R12_R0_Pos 0 /**< \brief (PICOP_R15R12) Register 0 */ |
| 840 | #define PICOP_R15R12_R0_Msk (0xFFul << PICOP_R15R12_R0_Pos) |
| 841 | #define PICOP_R15R12_R0(value) (PICOP_R15R12_R0_Msk & ((value) << PICOP_R15R12_R0_Pos)) |
| 842 | #define PICOP_R15R12_R1_Pos 8 /**< \brief (PICOP_R15R12) Register 1 */ |
| 843 | #define PICOP_R15R12_R1_Msk (0xFFul << PICOP_R15R12_R1_Pos) |
| 844 | #define PICOP_R15R12_R1(value) (PICOP_R15R12_R1_Msk & ((value) << PICOP_R15R12_R1_Pos)) |
| 845 | #define PICOP_R15R12_R2_Pos 16 /**< \brief (PICOP_R15R12) Register 2 */ |
| 846 | #define PICOP_R15R12_R2_Msk (0xFFul << PICOP_R15R12_R2_Pos) |
| 847 | #define PICOP_R15R12_R2(value) (PICOP_R15R12_R2_Msk & ((value) << PICOP_R15R12_R2_Pos)) |
| 848 | #define PICOP_R15R12_R3_Pos 24 /**< \brief (PICOP_R15R12) Register 3 */ |
| 849 | #define PICOP_R15R12_R3_Msk (0xFFul << PICOP_R15R12_R3_Pos) |
| 850 | #define PICOP_R15R12_R3(value) (PICOP_R15R12_R3_Msk & ((value) << PICOP_R15R12_R3_Pos)) |
| 851 | #define PICOP_R15R12_MASK 0xFFFFFFFFul /**< \brief (PICOP_R15R12) MASK Register */ |
| 852 | |
| 853 | /* -------- PICOP_R19R16 : (PICOP Offset: 0x090) (R/W 32) R19 to 16 -------- */ |
| 854 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 855 | typedef union { |
| 856 | struct { |
| 857 | uint32_t R0:8; /*!< bit: 0.. 7 Register 0 */ |
| 858 | uint32_t R1:8; /*!< bit: 8..15 Register 1 */ |
| 859 | uint32_t R2:8; /*!< bit: 16..23 Register 2 */ |
| 860 | uint32_t R3:8; /*!< bit: 24..31 Register 3 */ |
| 861 | } bit; /*!< Structure used for bit access */ |
| 862 | uint32_t reg; /*!< Type used for register access */ |
| 863 | } PICOP_R19R16_Type; |
| 864 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 865 | |
| 866 | #define PICOP_R19R16_OFFSET 0x090 /**< \brief (PICOP_R19R16 offset) R19 to 16 */ |
| 867 | |
| 868 | #define PICOP_R19R16_R0_Pos 0 /**< \brief (PICOP_R19R16) Register 0 */ |
| 869 | #define PICOP_R19R16_R0_Msk (0xFFul << PICOP_R19R16_R0_Pos) |
| 870 | #define PICOP_R19R16_R0(value) (PICOP_R19R16_R0_Msk & ((value) << PICOP_R19R16_R0_Pos)) |
| 871 | #define PICOP_R19R16_R1_Pos 8 /**< \brief (PICOP_R19R16) Register 1 */ |
| 872 | #define PICOP_R19R16_R1_Msk (0xFFul << PICOP_R19R16_R1_Pos) |
| 873 | #define PICOP_R19R16_R1(value) (PICOP_R19R16_R1_Msk & ((value) << PICOP_R19R16_R1_Pos)) |
| 874 | #define PICOP_R19R16_R2_Pos 16 /**< \brief (PICOP_R19R16) Register 2 */ |
| 875 | #define PICOP_R19R16_R2_Msk (0xFFul << PICOP_R19R16_R2_Pos) |
| 876 | #define PICOP_R19R16_R2(value) (PICOP_R19R16_R2_Msk & ((value) << PICOP_R19R16_R2_Pos)) |
| 877 | #define PICOP_R19R16_R3_Pos 24 /**< \brief (PICOP_R19R16) Register 3 */ |
| 878 | #define PICOP_R19R16_R3_Msk (0xFFul << PICOP_R19R16_R3_Pos) |
| 879 | #define PICOP_R19R16_R3(value) (PICOP_R19R16_R3_Msk & ((value) << PICOP_R19R16_R3_Pos)) |
| 880 | #define PICOP_R19R16_MASK 0xFFFFFFFFul /**< \brief (PICOP_R19R16) MASK Register */ |
| 881 | |
| 882 | /* -------- PICOP_R23R20 : (PICOP Offset: 0x094) (R/W 32) R23 to 20 -------- */ |
| 883 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 884 | typedef union { |
| 885 | struct { |
| 886 | uint32_t R0:8; /*!< bit: 0.. 7 Register 0 */ |
| 887 | uint32_t R1:8; /*!< bit: 8..15 Register 1 */ |
| 888 | uint32_t R2:8; /*!< bit: 16..23 Register 2 */ |
| 889 | uint32_t R3:8; /*!< bit: 24..31 Register 3 */ |
| 890 | } bit; /*!< Structure used for bit access */ |
| 891 | uint32_t reg; /*!< Type used for register access */ |
| 892 | } PICOP_R23R20_Type; |
| 893 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 894 | |
| 895 | #define PICOP_R23R20_OFFSET 0x094 /**< \brief (PICOP_R23R20 offset) R23 to 20 */ |
| 896 | |
| 897 | #define PICOP_R23R20_R0_Pos 0 /**< \brief (PICOP_R23R20) Register 0 */ |
| 898 | #define PICOP_R23R20_R0_Msk (0xFFul << PICOP_R23R20_R0_Pos) |
| 899 | #define PICOP_R23R20_R0(value) (PICOP_R23R20_R0_Msk & ((value) << PICOP_R23R20_R0_Pos)) |
| 900 | #define PICOP_R23R20_R1_Pos 8 /**< \brief (PICOP_R23R20) Register 1 */ |
| 901 | #define PICOP_R23R20_R1_Msk (0xFFul << PICOP_R23R20_R1_Pos) |
| 902 | #define PICOP_R23R20_R1(value) (PICOP_R23R20_R1_Msk & ((value) << PICOP_R23R20_R1_Pos)) |
| 903 | #define PICOP_R23R20_R2_Pos 16 /**< \brief (PICOP_R23R20) Register 2 */ |
| 904 | #define PICOP_R23R20_R2_Msk (0xFFul << PICOP_R23R20_R2_Pos) |
| 905 | #define PICOP_R23R20_R2(value) (PICOP_R23R20_R2_Msk & ((value) << PICOP_R23R20_R2_Pos)) |
| 906 | #define PICOP_R23R20_R3_Pos 24 /**< \brief (PICOP_R23R20) Register 3 */ |
| 907 | #define PICOP_R23R20_R3_Msk (0xFFul << PICOP_R23R20_R3_Pos) |
| 908 | #define PICOP_R23R20_R3(value) (PICOP_R23R20_R3_Msk & ((value) << PICOP_R23R20_R3_Pos)) |
| 909 | #define PICOP_R23R20_MASK 0xFFFFFFFFul /**< \brief (PICOP_R23R20) MASK Register */ |
| 910 | |
| 911 | /* -------- PICOP_R27R24 : (PICOP Offset: 0x098) (R/W 32) R27 to 24: XH, XL, R25, R24 -------- */ |
| 912 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 913 | typedef union { |
| 914 | struct { |
| 915 | uint32_t R0:8; /*!< bit: 0.. 7 Register 0 */ |
| 916 | uint32_t R1:8; /*!< bit: 8..15 Register 1 */ |
| 917 | uint32_t R2:8; /*!< bit: 16..23 Register 2 */ |
| 918 | uint32_t R3:8; /*!< bit: 24..31 Register 3 */ |
| 919 | } bit; /*!< Structure used for bit access */ |
| 920 | uint32_t reg; /*!< Type used for register access */ |
| 921 | } PICOP_R27R24_Type; |
| 922 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 923 | |
| 924 | #define PICOP_R27R24_OFFSET 0x098 /**< \brief (PICOP_R27R24 offset) R27 to 24: XH, XL, R25, R24 */ |
| 925 | |
| 926 | #define PICOP_R27R24_R0_Pos 0 /**< \brief (PICOP_R27R24) Register 0 */ |
| 927 | #define PICOP_R27R24_R0_Msk (0xFFul << PICOP_R27R24_R0_Pos) |
| 928 | #define PICOP_R27R24_R0(value) (PICOP_R27R24_R0_Msk & ((value) << PICOP_R27R24_R0_Pos)) |
| 929 | #define PICOP_R27R24_R1_Pos 8 /**< \brief (PICOP_R27R24) Register 1 */ |
| 930 | #define PICOP_R27R24_R1_Msk (0xFFul << PICOP_R27R24_R1_Pos) |
| 931 | #define PICOP_R27R24_R1(value) (PICOP_R27R24_R1_Msk & ((value) << PICOP_R27R24_R1_Pos)) |
| 932 | #define PICOP_R27R24_R2_Pos 16 /**< \brief (PICOP_R27R24) Register 2 */ |
| 933 | #define PICOP_R27R24_R2_Msk (0xFFul << PICOP_R27R24_R2_Pos) |
| 934 | #define PICOP_R27R24_R2(value) (PICOP_R27R24_R2_Msk & ((value) << PICOP_R27R24_R2_Pos)) |
| 935 | #define PICOP_R27R24_R3_Pos 24 /**< \brief (PICOP_R27R24) Register 3 */ |
| 936 | #define PICOP_R27R24_R3_Msk (0xFFul << PICOP_R27R24_R3_Pos) |
| 937 | #define PICOP_R27R24_R3(value) (PICOP_R27R24_R3_Msk & ((value) << PICOP_R27R24_R3_Pos)) |
| 938 | #define PICOP_R27R24_MASK 0xFFFFFFFFul /**< \brief (PICOP_R27R24) MASK Register */ |
| 939 | |
| 940 | /* -------- PICOP_R31R28 : (PICOP Offset: 0x09C) (R/W 32) R31 to 28: ZH, ZL, YH, YL -------- */ |
| 941 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 942 | typedef union { |
| 943 | struct { |
| 944 | uint32_t R0:8; /*!< bit: 0.. 7 Register 0 */ |
| 945 | uint32_t R1:8; /*!< bit: 8..15 Register 1 */ |
| 946 | uint32_t R2:8; /*!< bit: 16..23 Register 2 */ |
| 947 | uint32_t R3:8; /*!< bit: 24..31 Register 3 */ |
| 948 | } bit; /*!< Structure used for bit access */ |
| 949 | uint32_t reg; /*!< Type used for register access */ |
| 950 | } PICOP_R31R28_Type; |
| 951 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 952 | |
| 953 | #define PICOP_R31R28_OFFSET 0x09C /**< \brief (PICOP_R31R28 offset) R31 to 28: ZH, ZL, YH, YL */ |
| 954 | |
| 955 | #define PICOP_R31R28_R0_Pos 0 /**< \brief (PICOP_R31R28) Register 0 */ |
| 956 | #define PICOP_R31R28_R0_Msk (0xFFul << PICOP_R31R28_R0_Pos) |
| 957 | #define PICOP_R31R28_R0(value) (PICOP_R31R28_R0_Msk & ((value) << PICOP_R31R28_R0_Pos)) |
| 958 | #define PICOP_R31R28_R1_Pos 8 /**< \brief (PICOP_R31R28) Register 1 */ |
| 959 | #define PICOP_R31R28_R1_Msk (0xFFul << PICOP_R31R28_R1_Pos) |
| 960 | #define PICOP_R31R28_R1(value) (PICOP_R31R28_R1_Msk & ((value) << PICOP_R31R28_R1_Pos)) |
| 961 | #define PICOP_R31R28_R2_Pos 16 /**< \brief (PICOP_R31R28) Register 2 */ |
| 962 | #define PICOP_R31R28_R2_Msk (0xFFul << PICOP_R31R28_R2_Pos) |
| 963 | #define PICOP_R31R28_R2(value) (PICOP_R31R28_R2_Msk & ((value) << PICOP_R31R28_R2_Pos)) |
| 964 | #define PICOP_R31R28_R3_Pos 24 /**< \brief (PICOP_R31R28) Register 3 */ |
| 965 | #define PICOP_R31R28_R3_Msk (0xFFul << PICOP_R31R28_R3_Pos) |
| 966 | #define PICOP_R31R28_R3(value) (PICOP_R31R28_R3_Msk & ((value) << PICOP_R31R28_R3_Pos)) |
| 967 | #define PICOP_R31R28_MASK 0xFFFFFFFFul /**< \brief (PICOP_R31R28) MASK Register */ |
| 968 | |
| 969 | /* -------- PICOP_S1S0 : (PICOP Offset: 0x0A0) (R/W 32) System Regs 1 to 0: SR -------- */ |
| 970 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 971 | typedef union { |
| 972 | struct { |
| 973 | uint32_t R0:8; /*!< bit: 0.. 7 Register 0 */ |
| 974 | uint32_t R1:8; /*!< bit: 8..15 Register 1 */ |
| 975 | uint32_t R2:8; /*!< bit: 16..23 Register 2 */ |
| 976 | uint32_t R3:8; /*!< bit: 24..31 Register 3 */ |
| 977 | } bit; /*!< Structure used for bit access */ |
| 978 | uint32_t reg; /*!< Type used for register access */ |
| 979 | } PICOP_S1S0_Type; |
| 980 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 981 | |
| 982 | #define PICOP_S1S0_OFFSET 0x0A0 /**< \brief (PICOP_S1S0 offset) System Regs 1 to 0: SR */ |
| 983 | |
| 984 | #define PICOP_S1S0_R0_Pos 0 /**< \brief (PICOP_S1S0) Register 0 */ |
| 985 | #define PICOP_S1S0_R0_Msk (0xFFul << PICOP_S1S0_R0_Pos) |
| 986 | #define PICOP_S1S0_R0(value) (PICOP_S1S0_R0_Msk & ((value) << PICOP_S1S0_R0_Pos)) |
| 987 | #define PICOP_S1S0_R1_Pos 8 /**< \brief (PICOP_S1S0) Register 1 */ |
| 988 | #define PICOP_S1S0_R1_Msk (0xFFul << PICOP_S1S0_R1_Pos) |
| 989 | #define PICOP_S1S0_R1(value) (PICOP_S1S0_R1_Msk & ((value) << PICOP_S1S0_R1_Pos)) |
| 990 | #define PICOP_S1S0_R2_Pos 16 /**< \brief (PICOP_S1S0) Register 2 */ |
| 991 | #define PICOP_S1S0_R2_Msk (0xFFul << PICOP_S1S0_R2_Pos) |
| 992 | #define PICOP_S1S0_R2(value) (PICOP_S1S0_R2_Msk & ((value) << PICOP_S1S0_R2_Pos)) |
| 993 | #define PICOP_S1S0_R3_Pos 24 /**< \brief (PICOP_S1S0) Register 3 */ |
| 994 | #define PICOP_S1S0_R3_Msk (0xFFul << PICOP_S1S0_R3_Pos) |
| 995 | #define PICOP_S1S0_R3(value) (PICOP_S1S0_R3_Msk & ((value) << PICOP_S1S0_R3_Pos)) |
| 996 | #define PICOP_S1S0_MASK 0xFFFFFFFFul /**< \brief (PICOP_S1S0) MASK Register */ |
| 997 | |
| 998 | /* -------- PICOP_S3S2 : (PICOP Offset: 0x0A4) (R/W 32) System Regs 3 to 2: CTRL -------- */ |
| 999 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 1000 | typedef union { |
| 1001 | struct { |
| 1002 | uint32_t R0:8; /*!< bit: 0.. 7 Register 0 */ |
| 1003 | uint32_t R1:8; /*!< bit: 8..15 Register 1 */ |
| 1004 | uint32_t R2:8; /*!< bit: 16..23 Register 2 */ |
| 1005 | uint32_t R3:8; /*!< bit: 24..31 Register 3 */ |
| 1006 | } bit; /*!< Structure used for bit access */ |
| 1007 | uint32_t reg; /*!< Type used for register access */ |
| 1008 | } PICOP_S3S2_Type; |
| 1009 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 1010 | |
| 1011 | #define PICOP_S3S2_OFFSET 0x0A4 /**< \brief (PICOP_S3S2 offset) System Regs 3 to 2: CTRL */ |
| 1012 | |
| 1013 | #define PICOP_S3S2_R0_Pos 0 /**< \brief (PICOP_S3S2) Register 0 */ |
| 1014 | #define PICOP_S3S2_R0_Msk (0xFFul << PICOP_S3S2_R0_Pos) |
| 1015 | #define PICOP_S3S2_R0(value) (PICOP_S3S2_R0_Msk & ((value) << PICOP_S3S2_R0_Pos)) |
| 1016 | #define PICOP_S3S2_R1_Pos 8 /**< \brief (PICOP_S3S2) Register 1 */ |
| 1017 | #define PICOP_S3S2_R1_Msk (0xFFul << PICOP_S3S2_R1_Pos) |
| 1018 | #define PICOP_S3S2_R1(value) (PICOP_S3S2_R1_Msk & ((value) << PICOP_S3S2_R1_Pos)) |
| 1019 | #define PICOP_S3S2_R2_Pos 16 /**< \brief (PICOP_S3S2) Register 2 */ |
| 1020 | #define PICOP_S3S2_R2_Msk (0xFFul << PICOP_S3S2_R2_Pos) |
| 1021 | #define PICOP_S3S2_R2(value) (PICOP_S3S2_R2_Msk & ((value) << PICOP_S3S2_R2_Pos)) |
| 1022 | #define PICOP_S3S2_R3_Pos 24 /**< \brief (PICOP_S3S2) Register 3 */ |
| 1023 | #define PICOP_S3S2_R3_Msk (0xFFul << PICOP_S3S2_R3_Pos) |
| 1024 | #define PICOP_S3S2_R3(value) (PICOP_S3S2_R3_Msk & ((value) << PICOP_S3S2_R3_Pos)) |
| 1025 | #define PICOP_S3S2_MASK 0xFFFFFFFFul /**< \brief (PICOP_S3S2) MASK Register */ |
| 1026 | |
| 1027 | /* -------- PICOP_S5S4 : (PICOP Offset: 0x0A8) (R/W 32) System Regs 5 to 4: SREG, CCR -------- */ |
| 1028 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 1029 | typedef union { |
| 1030 | struct { |
| 1031 | uint32_t R0:8; /*!< bit: 0.. 7 Register 0 */ |
| 1032 | uint32_t R1:8; /*!< bit: 8..15 Register 1 */ |
| 1033 | uint32_t R2:8; /*!< bit: 16..23 Register 2 */ |
| 1034 | uint32_t R3:8; /*!< bit: 24..31 Register 3 */ |
| 1035 | } bit; /*!< Structure used for bit access */ |
| 1036 | uint32_t reg; /*!< Type used for register access */ |
| 1037 | } PICOP_S5S4_Type; |
| 1038 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 1039 | |
| 1040 | #define PICOP_S5S4_OFFSET 0x0A8 /**< \brief (PICOP_S5S4 offset) System Regs 5 to 4: SREG, CCR */ |
| 1041 | |
| 1042 | #define PICOP_S5S4_R0_Pos 0 /**< \brief (PICOP_S5S4) Register 0 */ |
| 1043 | #define PICOP_S5S4_R0_Msk (0xFFul << PICOP_S5S4_R0_Pos) |
| 1044 | #define PICOP_S5S4_R0(value) (PICOP_S5S4_R0_Msk & ((value) << PICOP_S5S4_R0_Pos)) |
| 1045 | #define PICOP_S5S4_R1_Pos 8 /**< \brief (PICOP_S5S4) Register 1 */ |
| 1046 | #define PICOP_S5S4_R1_Msk (0xFFul << PICOP_S5S4_R1_Pos) |
| 1047 | #define PICOP_S5S4_R1(value) (PICOP_S5S4_R1_Msk & ((value) << PICOP_S5S4_R1_Pos)) |
| 1048 | #define PICOP_S5S4_R2_Pos 16 /**< \brief (PICOP_S5S4) Register 2 */ |
| 1049 | #define PICOP_S5S4_R2_Msk (0xFFul << PICOP_S5S4_R2_Pos) |
| 1050 | #define PICOP_S5S4_R2(value) (PICOP_S5S4_R2_Msk & ((value) << PICOP_S5S4_R2_Pos)) |
| 1051 | #define PICOP_S5S4_R3_Pos 24 /**< \brief (PICOP_S5S4) Register 3 */ |
| 1052 | #define PICOP_S5S4_R3_Msk (0xFFul << PICOP_S5S4_R3_Pos) |
| 1053 | #define PICOP_S5S4_R3(value) (PICOP_S5S4_R3_Msk & ((value) << PICOP_S5S4_R3_Pos)) |
| 1054 | #define PICOP_S5S4_MASK 0xFFFFFFFFul /**< \brief (PICOP_S5S4) MASK Register */ |
| 1055 | |
| 1056 | /* -------- PICOP_S11S10 : (PICOP Offset: 0x0B4) (R/W 32) System Regs 11 to 10: Immediate -------- */ |
| 1057 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 1058 | typedef union { |
| 1059 | struct { |
| 1060 | uint32_t R0:8; /*!< bit: 0.. 7 Register 0 */ |
| 1061 | uint32_t R1:8; /*!< bit: 8..15 Register 1 */ |
| 1062 | uint32_t R2:8; /*!< bit: 16..23 Register 2 */ |
| 1063 | uint32_t R3:8; /*!< bit: 24..31 Register 3 */ |
| 1064 | } bit; /*!< Structure used for bit access */ |
| 1065 | uint32_t reg; /*!< Type used for register access */ |
| 1066 | } PICOP_S11S10_Type; |
| 1067 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 1068 | |
| 1069 | #define PICOP_S11S10_OFFSET 0x0B4 /**< \brief (PICOP_S11S10 offset) System Regs 11 to 10: Immediate */ |
| 1070 | |
| 1071 | #define PICOP_S11S10_R0_Pos 0 /**< \brief (PICOP_S11S10) Register 0 */ |
| 1072 | #define PICOP_S11S10_R0_Msk (0xFFul << PICOP_S11S10_R0_Pos) |
| 1073 | #define PICOP_S11S10_R0(value) (PICOP_S11S10_R0_Msk & ((value) << PICOP_S11S10_R0_Pos)) |
| 1074 | #define PICOP_S11S10_R1_Pos 8 /**< \brief (PICOP_S11S10) Register 1 */ |
| 1075 | #define PICOP_S11S10_R1_Msk (0xFFul << PICOP_S11S10_R1_Pos) |
| 1076 | #define PICOP_S11S10_R1(value) (PICOP_S11S10_R1_Msk & ((value) << PICOP_S11S10_R1_Pos)) |
| 1077 | #define PICOP_S11S10_R2_Pos 16 /**< \brief (PICOP_S11S10) Register 2 */ |
| 1078 | #define PICOP_S11S10_R2_Msk (0xFFul << PICOP_S11S10_R2_Pos) |
| 1079 | #define PICOP_S11S10_R2(value) (PICOP_S11S10_R2_Msk & ((value) << PICOP_S11S10_R2_Pos)) |
| 1080 | #define PICOP_S11S10_R3_Pos 24 /**< \brief (PICOP_S11S10) Register 3 */ |
| 1081 | #define PICOP_S11S10_R3_Msk (0xFFul << PICOP_S11S10_R3_Pos) |
| 1082 | #define PICOP_S11S10_R3(value) (PICOP_S11S10_R3_Msk & ((value) << PICOP_S11S10_R3_Pos)) |
| 1083 | #define PICOP_S11S10_MASK 0xFFFFFFFFul /**< \brief (PICOP_S11S10) MASK Register */ |
| 1084 | |
| 1085 | /* -------- PICOP_LINK : (PICOP Offset: 0x0B8) (R/W 32) Link -------- */ |
| 1086 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 1087 | typedef union { |
| 1088 | uint32_t reg; /*!< Type used for register access */ |
| 1089 | } PICOP_LINK_Type; |
| 1090 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 1091 | |
| 1092 | #define PICOP_LINK_OFFSET 0x0B8 /**< \brief (PICOP_LINK offset) Link */ |
| 1093 | #define PICOP_LINK_MASK 0xFFFFFFFFul /**< \brief (PICOP_LINK) MASK Register */ |
| 1094 | |
| 1095 | /* -------- PICOP_SP : (PICOP Offset: 0x0BC) (R/W 32) Stack Pointer -------- */ |
| 1096 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 1097 | typedef union { |
| 1098 | struct { |
| 1099 | uint32_t R0:8; /*!< bit: 0.. 7 Register 0 */ |
| 1100 | uint32_t R1:8; /*!< bit: 8..15 Register 1 */ |
| 1101 | uint32_t R2:8; /*!< bit: 16..23 Register 2 */ |
| 1102 | uint32_t R3:8; /*!< bit: 24..31 Register 3 */ |
| 1103 | } bit; /*!< Structure used for bit access */ |
| 1104 | uint32_t reg; /*!< Type used for register access */ |
| 1105 | } PICOP_SP_Type; |
| 1106 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 1107 | |
| 1108 | #define PICOP_SP_OFFSET 0x0BC /**< \brief (PICOP_SP offset) Stack Pointer */ |
| 1109 | |
| 1110 | #define PICOP_SP_R0_Pos 0 /**< \brief (PICOP_SP) Register 0 */ |
| 1111 | #define PICOP_SP_R0_Msk (0xFFul << PICOP_SP_R0_Pos) |
| 1112 | #define PICOP_SP_R0(value) (PICOP_SP_R0_Msk & ((value) << PICOP_SP_R0_Pos)) |
| 1113 | #define PICOP_SP_R1_Pos 8 /**< \brief (PICOP_SP) Register 1 */ |
| 1114 | #define PICOP_SP_R1_Msk (0xFFul << PICOP_SP_R1_Pos) |
| 1115 | #define PICOP_SP_R1(value) (PICOP_SP_R1_Msk & ((value) << PICOP_SP_R1_Pos)) |
| 1116 | #define PICOP_SP_R2_Pos 16 /**< \brief (PICOP_SP) Register 2 */ |
| 1117 | #define PICOP_SP_R2_Msk (0xFFul << PICOP_SP_R2_Pos) |
| 1118 | #define PICOP_SP_R2(value) (PICOP_SP_R2_Msk & ((value) << PICOP_SP_R2_Pos)) |
| 1119 | #define PICOP_SP_R3_Pos 24 /**< \brief (PICOP_SP) Register 3 */ |
| 1120 | #define PICOP_SP_R3_Msk (0xFFul << PICOP_SP_R3_Pos) |
| 1121 | #define PICOP_SP_R3(value) (PICOP_SP_R3_Msk & ((value) << PICOP_SP_R3_Pos)) |
| 1122 | #define PICOP_SP_MASK 0xFFFFFFFFul /**< \brief (PICOP_SP) MASK Register */ |
| 1123 | |
| 1124 | /* -------- PICOP_MMUFLASH : (PICOP Offset: 0x100) (R/W 32) MMU mapping for flash -------- */ |
| 1125 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 1126 | typedef union { |
| 1127 | struct { |
| 1128 | uint32_t ADDRESS:4; /*!< bit: 0.. 3 MMU Flash Address */ |
| 1129 | uint32_t :28; /*!< bit: 4..31 Reserved */ |
| 1130 | } bit; /*!< Structure used for bit access */ |
| 1131 | uint32_t reg; /*!< Type used for register access */ |
| 1132 | } PICOP_MMUFLASH_Type; |
| 1133 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 1134 | |
| 1135 | #define PICOP_MMUFLASH_OFFSET 0x100 /**< \brief (PICOP_MMUFLASH offset) MMU mapping for flash */ |
| 1136 | #define PICOP_MMUFLASH_RESETVALUE 0x00000000ul /**< \brief (PICOP_MMUFLASH reset_value) MMU mapping for flash */ |
| 1137 | |
| 1138 | #define PICOP_MMUFLASH_ADDRESS_Pos 0 /**< \brief (PICOP_MMUFLASH) MMU Flash Address */ |
| 1139 | #define PICOP_MMUFLASH_ADDRESS_Msk (0xFul << PICOP_MMUFLASH_ADDRESS_Pos) |
| 1140 | #define PICOP_MMUFLASH_ADDRESS(value) (PICOP_MMUFLASH_ADDRESS_Msk & ((value) << PICOP_MMUFLASH_ADDRESS_Pos)) |
| 1141 | #define PICOP_MMUFLASH_MASK 0x0000000Ful /**< \brief (PICOP_MMUFLASH) MASK Register */ |
| 1142 | |
| 1143 | /* -------- PICOP_MMU0 : (PICOP Offset: 0x118) (R/W 32) MMU mapping user 0 -------- */ |
| 1144 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 1145 | typedef union { |
| 1146 | struct { |
| 1147 | uint32_t ADDRESS:32; /*!< bit: 0..31 MMU User 0 Address */ |
| 1148 | } bit; /*!< Structure used for bit access */ |
| 1149 | uint32_t reg; /*!< Type used for register access */ |
| 1150 | } PICOP_MMU0_Type; |
| 1151 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 1152 | |
| 1153 | #define PICOP_MMU0_OFFSET 0x118 /**< \brief (PICOP_MMU0 offset) MMU mapping user 0 */ |
| 1154 | #define PICOP_MMU0_RESETVALUE 0x00000000ul /**< \brief (PICOP_MMU0 reset_value) MMU mapping user 0 */ |
| 1155 | |
| 1156 | #define PICOP_MMU0_ADDRESS_Pos 0 /**< \brief (PICOP_MMU0) MMU User 0 Address */ |
| 1157 | #define PICOP_MMU0_ADDRESS_Msk (0xFFFFFFFFul << PICOP_MMU0_ADDRESS_Pos) |
| 1158 | #define PICOP_MMU0_ADDRESS(value) (PICOP_MMU0_ADDRESS_Msk & ((value) << PICOP_MMU0_ADDRESS_Pos)) |
| 1159 | #define PICOP_MMU0_MASK 0xFFFFFFFFul /**< \brief (PICOP_MMU0) MASK Register */ |
| 1160 | |
| 1161 | /* -------- PICOP_MMU1 : (PICOP Offset: 0x11C) (R/W 32) MMU mapping user 1 -------- */ |
| 1162 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 1163 | typedef union { |
| 1164 | struct { |
| 1165 | uint32_t ADDRESS:32; /*!< bit: 0..31 MMU User 1 Address */ |
| 1166 | } bit; /*!< Structure used for bit access */ |
| 1167 | uint32_t reg; /*!< Type used for register access */ |
| 1168 | } PICOP_MMU1_Type; |
| 1169 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 1170 | |
| 1171 | #define PICOP_MMU1_OFFSET 0x11C /**< \brief (PICOP_MMU1 offset) MMU mapping user 1 */ |
| 1172 | #define PICOP_MMU1_RESETVALUE 0x00000000ul /**< \brief (PICOP_MMU1 reset_value) MMU mapping user 1 */ |
| 1173 | |
| 1174 | #define PICOP_MMU1_ADDRESS_Pos 0 /**< \brief (PICOP_MMU1) MMU User 1 Address */ |
| 1175 | #define PICOP_MMU1_ADDRESS_Msk (0xFFFFFFFFul << PICOP_MMU1_ADDRESS_Pos) |
| 1176 | #define PICOP_MMU1_ADDRESS(value) (PICOP_MMU1_ADDRESS_Msk & ((value) << PICOP_MMU1_ADDRESS_Pos)) |
| 1177 | #define PICOP_MMU1_MASK 0xFFFFFFFFul /**< \brief (PICOP_MMU1) MASK Register */ |
| 1178 | |
| 1179 | /* -------- PICOP_MMUCTRL : (PICOP Offset: 0x120) (R/W 32) MMU Control -------- */ |
| 1180 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 1181 | typedef union { |
| 1182 | struct { |
| 1183 | uint32_t IODIS:1; /*!< bit: 0 Peripheral MMU Disable */ |
| 1184 | uint32_t MEMDIS:1; /*!< bit: 1 Memory MMU Disable */ |
| 1185 | uint32_t :30; /*!< bit: 2..31 Reserved */ |
| 1186 | } bit; /*!< Structure used for bit access */ |
| 1187 | uint32_t reg; /*!< Type used for register access */ |
| 1188 | } PICOP_MMUCTRL_Type; |
| 1189 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 1190 | |
| 1191 | #define PICOP_MMUCTRL_OFFSET 0x120 /**< \brief (PICOP_MMUCTRL offset) MMU Control */ |
| 1192 | #define PICOP_MMUCTRL_RESETVALUE 0x00000000ul /**< \brief (PICOP_MMUCTRL reset_value) MMU Control */ |
| 1193 | |
| 1194 | #define PICOP_MMUCTRL_IODIS_Pos 0 /**< \brief (PICOP_MMUCTRL) Peripheral MMU Disable */ |
| 1195 | #define PICOP_MMUCTRL_IODIS (0x1ul << PICOP_MMUCTRL_IODIS_Pos) |
| 1196 | #define PICOP_MMUCTRL_MEMDIS_Pos 1 /**< \brief (PICOP_MMUCTRL) Memory MMU Disable */ |
| 1197 | #define PICOP_MMUCTRL_MEMDIS (0x1ul << PICOP_MMUCTRL_MEMDIS_Pos) |
| 1198 | #define PICOP_MMUCTRL_MASK 0x00000003ul /**< \brief (PICOP_MMUCTRL) MASK Register */ |
| 1199 | |
| 1200 | /* -------- PICOP_ICACHE : (PICOP Offset: 0x180) (R/W 32) Instruction Cache Control -------- */ |
| 1201 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 1202 | typedef union { |
| 1203 | struct { |
| 1204 | uint32_t CTRL:2; /*!< bit: 0.. 1 Instruction Cache Control */ |
| 1205 | uint32_t :30; /*!< bit: 2..31 Reserved */ |
| 1206 | } bit; /*!< Structure used for bit access */ |
| 1207 | uint32_t reg; /*!< Type used for register access */ |
| 1208 | } PICOP_ICACHE_Type; |
| 1209 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 1210 | |
| 1211 | #define PICOP_ICACHE_OFFSET 0x180 /**< \brief (PICOP_ICACHE offset) Instruction Cache Control */ |
| 1212 | #define PICOP_ICACHE_RESETVALUE 0x00000000ul /**< \brief (PICOP_ICACHE reset_value) Instruction Cache Control */ |
| 1213 | |
| 1214 | #define PICOP_ICACHE_CTRL_Pos 0 /**< \brief (PICOP_ICACHE) Instruction Cache Control */ |
| 1215 | #define PICOP_ICACHE_CTRL_Msk (0x3ul << PICOP_ICACHE_CTRL_Pos) |
| 1216 | #define PICOP_ICACHE_CTRL(value) (PICOP_ICACHE_CTRL_Msk & ((value) << PICOP_ICACHE_CTRL_Pos)) |
| 1217 | #define PICOP_ICACHE_MASK 0x00000003ul /**< \brief (PICOP_ICACHE) MASK Register */ |
| 1218 | |
| 1219 | /* -------- PICOP_ICACHELRU : (PICOP Offset: 0x184) (R/W 32) Instruction Cache LRU -------- */ |
| 1220 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 1221 | typedef union { |
| 1222 | struct { |
| 1223 | uint32_t LRU0:2; /*!< bit: 0.. 1 Instruction Cache LRU 0 */ |
| 1224 | uint32_t LRU1:2; /*!< bit: 2.. 3 Instruction Cache LRU 1 */ |
| 1225 | uint32_t LRU2:2; /*!< bit: 4.. 5 Instruction Cache LRU 2 */ |
| 1226 | uint32_t LRU3:2; /*!< bit: 6.. 7 Instruction Cache LRU 3 */ |
| 1227 | uint32_t :24; /*!< bit: 8..31 Reserved */ |
| 1228 | } bit; /*!< Structure used for bit access */ |
| 1229 | uint32_t reg; /*!< Type used for register access */ |
| 1230 | } PICOP_ICACHELRU_Type; |
| 1231 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 1232 | |
| 1233 | #define PICOP_ICACHELRU_OFFSET 0x184 /**< \brief (PICOP_ICACHELRU offset) Instruction Cache LRU */ |
| 1234 | #define PICOP_ICACHELRU_RESETVALUE 0x00000000ul /**< \brief (PICOP_ICACHELRU reset_value) Instruction Cache LRU */ |
| 1235 | |
| 1236 | #define PICOP_ICACHELRU_LRU0_Pos 0 /**< \brief (PICOP_ICACHELRU) Instruction Cache LRU 0 */ |
| 1237 | #define PICOP_ICACHELRU_LRU0_Msk (0x3ul << PICOP_ICACHELRU_LRU0_Pos) |
| 1238 | #define PICOP_ICACHELRU_LRU0(value) (PICOP_ICACHELRU_LRU0_Msk & ((value) << PICOP_ICACHELRU_LRU0_Pos)) |
| 1239 | #define PICOP_ICACHELRU_LRU1_Pos 2 /**< \brief (PICOP_ICACHELRU) Instruction Cache LRU 1 */ |
| 1240 | #define PICOP_ICACHELRU_LRU1_Msk (0x3ul << PICOP_ICACHELRU_LRU1_Pos) |
| 1241 | #define PICOP_ICACHELRU_LRU1(value) (PICOP_ICACHELRU_LRU1_Msk & ((value) << PICOP_ICACHELRU_LRU1_Pos)) |
| 1242 | #define PICOP_ICACHELRU_LRU2_Pos 4 /**< \brief (PICOP_ICACHELRU) Instruction Cache LRU 2 */ |
| 1243 | #define PICOP_ICACHELRU_LRU2_Msk (0x3ul << PICOP_ICACHELRU_LRU2_Pos) |
| 1244 | #define PICOP_ICACHELRU_LRU2(value) (PICOP_ICACHELRU_LRU2_Msk & ((value) << PICOP_ICACHELRU_LRU2_Pos)) |
| 1245 | #define PICOP_ICACHELRU_LRU3_Pos 6 /**< \brief (PICOP_ICACHELRU) Instruction Cache LRU 3 */ |
| 1246 | #define PICOP_ICACHELRU_LRU3_Msk (0x3ul << PICOP_ICACHELRU_LRU3_Pos) |
| 1247 | #define PICOP_ICACHELRU_LRU3(value) (PICOP_ICACHELRU_LRU3_Msk & ((value) << PICOP_ICACHELRU_LRU3_Pos)) |
| 1248 | #define PICOP_ICACHELRU_MASK 0x000000FFul /**< \brief (PICOP_ICACHELRU) MASK Register */ |
| 1249 | |
| 1250 | /* -------- PICOP_QOSCTRL : (PICOP Offset: 0x200) (R/W 32) QOS Control -------- */ |
| 1251 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 1252 | typedef union { |
| 1253 | struct { |
| 1254 | uint32_t QOS:2; /*!< bit: 0.. 1 Quality of Service */ |
| 1255 | uint32_t :30; /*!< bit: 2..31 Reserved */ |
| 1256 | } bit; /*!< Structure used for bit access */ |
| 1257 | uint32_t reg; /*!< Type used for register access */ |
| 1258 | } PICOP_QOSCTRL_Type; |
| 1259 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 1260 | |
| 1261 | #define PICOP_QOSCTRL_OFFSET 0x200 /**< \brief (PICOP_QOSCTRL offset) QOS Control */ |
| 1262 | |
| 1263 | #define PICOP_QOSCTRL_QOS_Pos 0 /**< \brief (PICOP_QOSCTRL) Quality of Service */ |
| 1264 | #define PICOP_QOSCTRL_QOS_Msk (0x3ul << PICOP_QOSCTRL_QOS_Pos) |
| 1265 | #define PICOP_QOSCTRL_QOS(value) (PICOP_QOSCTRL_QOS_Msk & ((value) << PICOP_QOSCTRL_QOS_Pos)) |
| 1266 | #define PICOP_QOSCTRL_MASK 0x00000003ul /**< \brief (PICOP_QOSCTRL) MASK Register */ |
| 1267 | |
| 1268 | /** \brief PICOP hardware registers */ |
| 1269 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 1270 | typedef struct { |
| 1271 | __IO PICOP_ID_Type ID[8]; /**< \brief Offset: 0x000 (R/W 32) ID n */ |
| 1272 | __IO PICOP_CONFIG_Type CONFIG; /**< \brief Offset: 0x020 (R/W 32) Configuration */ |
| 1273 | __IO PICOP_CTRL_Type CTRL; /**< \brief Offset: 0x024 (R/W 32) Control */ |
| 1274 | __IO PICOP_CMD_Type CMD; /**< \brief Offset: 0x028 (R/W 32) Command */ |
| 1275 | __IO PICOP_PC_Type PC; /**< \brief Offset: 0x02C (R/W 32) Program Counter */ |
| 1276 | __IO PICOP_HF_Type HF; /**< \brief Offset: 0x030 (R/W 32) Host Flags */ |
| 1277 | __IO PICOP_HFCTRL_Type HFCTRL; /**< \brief Offset: 0x034 (R/W 32) Host Flag Control */ |
| 1278 | __IO PICOP_HFSETCLR0_Type HFSETCLR0; /**< \brief Offset: 0x038 (R/W 32) Host Flags Set/Clr */ |
| 1279 | __IO PICOP_HFSETCLR1_Type HFSETCLR1; /**< \brief Offset: 0x03C (R/W 32) Host Flags Set/Clr */ |
| 1280 | RoReg8 Reserved1[0x10]; |
| 1281 | __IO PICOP_OCDCONFIG_Type OCDCONFIG; /**< \brief Offset: 0x050 (R/W 32) OCD Configuration */ |
| 1282 | __IO PICOP_OCDCONTROL_Type OCDCONTROL; /**< \brief Offset: 0x054 (R/W 32) OCD Control */ |
| 1283 | __IO PICOP_OCDSTATUS_Type OCDSTATUS; /**< \brief Offset: 0x058 (R/W 32) OCD Status and Command */ |
| 1284 | __IO PICOP_OCDPC_Type OCDPC; /**< \brief Offset: 0x05C (R/W 32) ODC Program Counter */ |
| 1285 | __IO PICOP_OCDFEAT_Type OCDFEAT; /**< \brief Offset: 0x060 (R/W 32) OCD Features */ |
| 1286 | RoReg8 Reserved2[0x4]; |
| 1287 | __IO PICOP_OCDCCNT_Type OCDCCNT; /**< \brief Offset: 0x068 (R/W 32) OCD Cycle Counter */ |
| 1288 | RoReg8 Reserved3[0x4]; |
| 1289 | __IO PICOP_OCDBPGEN_Type OCDBPGEN[4]; /**< \brief Offset: 0x070 (R/W 32) OCD Breakpoint Generator n */ |
| 1290 | __IO PICOP_R3R0_Type R3R0; /**< \brief Offset: 0x080 (R/W 32) R3 to 0 */ |
| 1291 | __IO PICOP_R7R4_Type R7R4; /**< \brief Offset: 0x084 (R/W 32) R7 to 4 */ |
| 1292 | __IO PICOP_R11R8_Type R11R8; /**< \brief Offset: 0x088 (R/W 32) R11 to 8 */ |
| 1293 | __IO PICOP_R15R12_Type R15R12; /**< \brief Offset: 0x08C (R/W 32) R15 to 12 */ |
| 1294 | __IO PICOP_R19R16_Type R19R16; /**< \brief Offset: 0x090 (R/W 32) R19 to 16 */ |
| 1295 | __IO PICOP_R23R20_Type R23R20; /**< \brief Offset: 0x094 (R/W 32) R23 to 20 */ |
| 1296 | __IO PICOP_R27R24_Type R27R24; /**< \brief Offset: 0x098 (R/W 32) R27 to 24: XH, XL, R25, R24 */ |
| 1297 | __IO PICOP_R31R28_Type R31R28; /**< \brief Offset: 0x09C (R/W 32) R31 to 28: ZH, ZL, YH, YL */ |
| 1298 | __IO PICOP_S1S0_Type S1S0; /**< \brief Offset: 0x0A0 (R/W 32) System Regs 1 to 0: SR */ |
| 1299 | __IO PICOP_S3S2_Type S3S2; /**< \brief Offset: 0x0A4 (R/W 32) System Regs 3 to 2: CTRL */ |
| 1300 | __IO PICOP_S5S4_Type S5S4; /**< \brief Offset: 0x0A8 (R/W 32) System Regs 5 to 4: SREG, CCR */ |
| 1301 | RoReg8 Reserved4[0x8]; |
| 1302 | __IO PICOP_S11S10_Type S11S10; /**< \brief Offset: 0x0B4 (R/W 32) System Regs 11 to 10: Immediate */ |
| 1303 | __IO PICOP_LINK_Type LINK; /**< \brief Offset: 0x0B8 (R/W 32) Link */ |
| 1304 | __IO PICOP_SP_Type SP; /**< \brief Offset: 0x0BC (R/W 32) Stack Pointer */ |
| 1305 | RoReg8 Reserved5[0x40]; |
| 1306 | __IO PICOP_MMUFLASH_Type MMUFLASH; /**< \brief Offset: 0x100 (R/W 32) MMU mapping for flash */ |
| 1307 | RoReg8 Reserved6[0x14]; |
| 1308 | __IO PICOP_MMU0_Type MMU0; /**< \brief Offset: 0x118 (R/W 32) MMU mapping user 0 */ |
| 1309 | __IO PICOP_MMU1_Type MMU1; /**< \brief Offset: 0x11C (R/W 32) MMU mapping user 1 */ |
| 1310 | __IO PICOP_MMUCTRL_Type MMUCTRL; /**< \brief Offset: 0x120 (R/W 32) MMU Control */ |
| 1311 | RoReg8 Reserved7[0x5C]; |
| 1312 | __IO PICOP_ICACHE_Type ICACHE; /**< \brief Offset: 0x180 (R/W 32) Instruction Cache Control */ |
| 1313 | __IO PICOP_ICACHELRU_Type ICACHELRU; /**< \brief Offset: 0x184 (R/W 32) Instruction Cache LRU */ |
| 1314 | RoReg8 Reserved8[0x78]; |
| 1315 | __IO PICOP_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x200 (R/W 32) QOS Control */ |
| 1316 | } Picop; |
| 1317 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 1318 | |
| 1319 | /*@}*/ |
| 1320 | |
| 1321 | #endif /* _SAME54_PICOP_COMPONENT_ */ |