Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM SDHC |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_SDHC_COMPONENT_ |
| 35 | #ifndef _HRI_SDHC_E54_H_INCLUDED_ |
| 36 | #define _HRI_SDHC_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_SDHC_CRITICAL_SECTIONS) |
| 46 | #define SDHC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define SDHC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define SDHC_CRITICAL_SECTION_ENTER() |
| 50 | #define SDHC_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint16_t hri_sdhc_acesr_reg_t; |
| 54 | typedef uint16_t hri_sdhc_bcr_reg_t; |
| 55 | typedef uint16_t hri_sdhc_bsr_reg_t; |
| 56 | typedef uint16_t hri_sdhc_ccr_reg_t; |
| 57 | typedef uint16_t hri_sdhc_cr_reg_t; |
| 58 | typedef uint16_t hri_sdhc_eisier_reg_t; |
| 59 | typedef uint16_t hri_sdhc_eister_reg_t; |
| 60 | typedef uint16_t hri_sdhc_eistr_reg_t; |
| 61 | typedef uint16_t hri_sdhc_feraces_reg_t; |
| 62 | typedef uint16_t hri_sdhc_fereis_reg_t; |
| 63 | typedef uint16_t hri_sdhc_hc2r_reg_t; |
| 64 | typedef uint16_t hri_sdhc_hcvr_reg_t; |
| 65 | typedef uint16_t hri_sdhc_nisier_reg_t; |
| 66 | typedef uint16_t hri_sdhc_nister_reg_t; |
| 67 | typedef uint16_t hri_sdhc_nistr_reg_t; |
| 68 | typedef uint16_t hri_sdhc_pvr_reg_t; |
| 69 | typedef uint16_t hri_sdhc_sisr_reg_t; |
| 70 | typedef uint16_t hri_sdhc_tmr_reg_t; |
| 71 | typedef uint32_t hri_sdhc_acr_reg_t; |
| 72 | typedef uint32_t hri_sdhc_arg1r_reg_t; |
| 73 | typedef uint32_t hri_sdhc_asar_reg_t; |
| 74 | typedef uint32_t hri_sdhc_bdpr_reg_t; |
| 75 | typedef uint32_t hri_sdhc_ca0r_reg_t; |
| 76 | typedef uint32_t hri_sdhc_ca1r_reg_t; |
| 77 | typedef uint32_t hri_sdhc_cacr_reg_t; |
| 78 | typedef uint32_t hri_sdhc_cc2r_reg_t; |
| 79 | typedef uint32_t hri_sdhc_mccar_reg_t; |
| 80 | typedef uint32_t hri_sdhc_psr_reg_t; |
| 81 | typedef uint32_t hri_sdhc_rr_reg_t; |
| 82 | typedef uint32_t hri_sdhc_ssar_reg_t; |
| 83 | typedef uint8_t hri_sdhc_aesr_reg_t; |
| 84 | typedef uint8_t hri_sdhc_bgcr_reg_t; |
| 85 | typedef uint8_t hri_sdhc_dbgr_reg_t; |
| 86 | typedef uint8_t hri_sdhc_hc1r_reg_t; |
| 87 | typedef uint8_t hri_sdhc_mc1r_reg_t; |
| 88 | typedef uint8_t hri_sdhc_mc2r_reg_t; |
| 89 | typedef uint8_t hri_sdhc_pcr_reg_t; |
| 90 | typedef uint8_t hri_sdhc_srr_reg_t; |
| 91 | typedef uint8_t hri_sdhc_tcr_reg_t; |
| 92 | typedef uint8_t hri_sdhc_wcr_reg_t; |
| 93 | |
| 94 | static inline hri_sdhc_rr_reg_t hri_sdhc_get_RR_CMDRESP_bf(const void *const hw, uint8_t index, hri_sdhc_rr_reg_t mask) |
| 95 | { |
| 96 | return (((Sdhc *)hw)->RR[index].reg & SDHC_RR_CMDRESP(mask)) >> SDHC_RR_CMDRESP_Pos; |
| 97 | } |
| 98 | |
| 99 | static inline hri_sdhc_rr_reg_t hri_sdhc_read_RR_CMDRESP_bf(const void *const hw, uint8_t index) |
| 100 | { |
| 101 | return (((Sdhc *)hw)->RR[index].reg & SDHC_RR_CMDRESP_Msk) >> SDHC_RR_CMDRESP_Pos; |
| 102 | } |
| 103 | |
| 104 | static inline hri_sdhc_rr_reg_t hri_sdhc_get_RR_reg(const void *const hw, uint8_t index, hri_sdhc_rr_reg_t mask) |
| 105 | { |
| 106 | uint32_t tmp; |
| 107 | tmp = ((Sdhc *)hw)->RR[index].reg; |
| 108 | tmp &= mask; |
| 109 | return tmp; |
| 110 | } |
| 111 | |
| 112 | static inline hri_sdhc_rr_reg_t hri_sdhc_read_RR_reg(const void *const hw, uint8_t index) |
| 113 | { |
| 114 | return ((Sdhc *)hw)->RR[index].reg; |
| 115 | } |
| 116 | |
| 117 | static inline bool hri_sdhc_get_PSR_CMDINHC_bit(const void *const hw) |
| 118 | { |
| 119 | return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDINHC) >> SDHC_PSR_CMDINHC_Pos; |
| 120 | } |
| 121 | |
| 122 | static inline bool hri_sdhc_get_PSR_CMDINHD_bit(const void *const hw) |
| 123 | { |
| 124 | return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDINHD) >> SDHC_PSR_CMDINHD_Pos; |
| 125 | } |
| 126 | |
| 127 | static inline bool hri_sdhc_get_PSR_DLACT_bit(const void *const hw) |
| 128 | { |
| 129 | return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DLACT) >> SDHC_PSR_DLACT_Pos; |
| 130 | } |
| 131 | |
| 132 | static inline bool hri_sdhc_get_PSR_RTREQ_bit(const void *const hw) |
| 133 | { |
| 134 | return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_RTREQ) >> SDHC_PSR_RTREQ_Pos; |
| 135 | } |
| 136 | |
| 137 | static inline bool hri_sdhc_get_PSR_WTACT_bit(const void *const hw) |
| 138 | { |
| 139 | return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_WTACT) >> SDHC_PSR_WTACT_Pos; |
| 140 | } |
| 141 | |
| 142 | static inline bool hri_sdhc_get_PSR_RTACT_bit(const void *const hw) |
| 143 | { |
| 144 | return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_RTACT) >> SDHC_PSR_RTACT_Pos; |
| 145 | } |
| 146 | |
| 147 | static inline bool hri_sdhc_get_PSR_BUFWREN_bit(const void *const hw) |
| 148 | { |
| 149 | return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_BUFWREN) >> SDHC_PSR_BUFWREN_Pos; |
| 150 | } |
| 151 | |
| 152 | static inline bool hri_sdhc_get_PSR_BUFRDEN_bit(const void *const hw) |
| 153 | { |
| 154 | return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_BUFRDEN) >> SDHC_PSR_BUFRDEN_Pos; |
| 155 | } |
| 156 | |
| 157 | static inline bool hri_sdhc_get_PSR_CARDINS_bit(const void *const hw) |
| 158 | { |
| 159 | return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDINS) >> SDHC_PSR_CARDINS_Pos; |
| 160 | } |
| 161 | |
| 162 | static inline bool hri_sdhc_get_PSR_CARDSS_bit(const void *const hw) |
| 163 | { |
| 164 | return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDSS) >> SDHC_PSR_CARDSS_Pos; |
| 165 | } |
| 166 | |
| 167 | static inline bool hri_sdhc_get_PSR_CARDDPL_bit(const void *const hw) |
| 168 | { |
| 169 | return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDDPL) >> SDHC_PSR_CARDDPL_Pos; |
| 170 | } |
| 171 | |
| 172 | static inline bool hri_sdhc_get_PSR_WRPPL_bit(const void *const hw) |
| 173 | { |
| 174 | return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_WRPPL) >> SDHC_PSR_WRPPL_Pos; |
| 175 | } |
| 176 | |
| 177 | static inline bool hri_sdhc_get_PSR_CMDLL_bit(const void *const hw) |
| 178 | { |
| 179 | return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDLL) >> SDHC_PSR_CMDLL_Pos; |
| 180 | } |
| 181 | |
| 182 | static inline hri_sdhc_psr_reg_t hri_sdhc_get_PSR_DATLL_bf(const void *const hw, hri_sdhc_psr_reg_t mask) |
| 183 | { |
| 184 | return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DATLL(mask)) >> SDHC_PSR_DATLL_Pos; |
| 185 | } |
| 186 | |
| 187 | static inline hri_sdhc_psr_reg_t hri_sdhc_read_PSR_DATLL_bf(const void *const hw) |
| 188 | { |
| 189 | return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DATLL_Msk) >> SDHC_PSR_DATLL_Pos; |
| 190 | } |
| 191 | |
| 192 | static inline hri_sdhc_psr_reg_t hri_sdhc_get_PSR_reg(const void *const hw, hri_sdhc_psr_reg_t mask) |
| 193 | { |
| 194 | uint32_t tmp; |
| 195 | tmp = ((Sdhc *)hw)->PSR.reg; |
| 196 | tmp &= mask; |
| 197 | return tmp; |
| 198 | } |
| 199 | |
| 200 | static inline hri_sdhc_psr_reg_t hri_sdhc_read_PSR_reg(const void *const hw) |
| 201 | { |
| 202 | return ((Sdhc *)hw)->PSR.reg; |
| 203 | } |
| 204 | |
| 205 | static inline bool hri_sdhc_get_ACESR_ACMD12NE_bit(const void *const hw) |
| 206 | { |
| 207 | return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMD12NE) >> SDHC_ACESR_ACMD12NE_Pos; |
| 208 | } |
| 209 | |
| 210 | static inline bool hri_sdhc_get_ACESR_ACMDTEO_bit(const void *const hw) |
| 211 | { |
| 212 | return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDTEO) >> SDHC_ACESR_ACMDTEO_Pos; |
| 213 | } |
| 214 | |
| 215 | static inline bool hri_sdhc_get_ACESR_ACMDCRC_bit(const void *const hw) |
| 216 | { |
| 217 | return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDCRC) >> SDHC_ACESR_ACMDCRC_Pos; |
| 218 | } |
| 219 | |
| 220 | static inline bool hri_sdhc_get_ACESR_ACMDEND_bit(const void *const hw) |
| 221 | { |
| 222 | return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDEND) >> SDHC_ACESR_ACMDEND_Pos; |
| 223 | } |
| 224 | |
| 225 | static inline bool hri_sdhc_get_ACESR_ACMDIDX_bit(const void *const hw) |
| 226 | { |
| 227 | return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDIDX) >> SDHC_ACESR_ACMDIDX_Pos; |
| 228 | } |
| 229 | |
| 230 | static inline bool hri_sdhc_get_ACESR_CMDNI_bit(const void *const hw) |
| 231 | { |
| 232 | return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_CMDNI) >> SDHC_ACESR_CMDNI_Pos; |
| 233 | } |
| 234 | |
| 235 | static inline hri_sdhc_acesr_reg_t hri_sdhc_get_ACESR_reg(const void *const hw, hri_sdhc_acesr_reg_t mask) |
| 236 | { |
| 237 | uint16_t tmp; |
| 238 | tmp = ((Sdhc *)hw)->ACESR.reg; |
| 239 | tmp &= mask; |
| 240 | return tmp; |
| 241 | } |
| 242 | |
| 243 | static inline hri_sdhc_acesr_reg_t hri_sdhc_read_ACESR_reg(const void *const hw) |
| 244 | { |
| 245 | return ((Sdhc *)hw)->ACESR.reg; |
| 246 | } |
| 247 | |
| 248 | static inline bool hri_sdhc_get_CA0R_TEOCLKU_bit(const void *const hw) |
| 249 | { |
| 250 | return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKU) >> SDHC_CA0R_TEOCLKU_Pos; |
| 251 | } |
| 252 | |
| 253 | static inline bool hri_sdhc_get_CA0R_ED8SUP_bit(const void *const hw) |
| 254 | { |
| 255 | return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ED8SUP) >> SDHC_CA0R_ED8SUP_Pos; |
| 256 | } |
| 257 | |
| 258 | static inline bool hri_sdhc_get_CA0R_ADMA2SUP_bit(const void *const hw) |
| 259 | { |
| 260 | return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ADMA2SUP) >> SDHC_CA0R_ADMA2SUP_Pos; |
| 261 | } |
| 262 | |
| 263 | static inline bool hri_sdhc_get_CA0R_HSSUP_bit(const void *const hw) |
| 264 | { |
| 265 | return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_HSSUP) >> SDHC_CA0R_HSSUP_Pos; |
| 266 | } |
| 267 | |
| 268 | static inline bool hri_sdhc_get_CA0R_SDMASUP_bit(const void *const hw) |
| 269 | { |
| 270 | return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SDMASUP) >> SDHC_CA0R_SDMASUP_Pos; |
| 271 | } |
| 272 | |
| 273 | static inline bool hri_sdhc_get_CA0R_SRSUP_bit(const void *const hw) |
| 274 | { |
| 275 | return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SRSUP) >> SDHC_CA0R_SRSUP_Pos; |
| 276 | } |
| 277 | |
| 278 | static inline bool hri_sdhc_get_CA0R_V33VSUP_bit(const void *const hw) |
| 279 | { |
| 280 | return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V33VSUP) >> SDHC_CA0R_V33VSUP_Pos; |
| 281 | } |
| 282 | |
| 283 | static inline bool hri_sdhc_get_CA0R_V30VSUP_bit(const void *const hw) |
| 284 | { |
| 285 | return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V30VSUP) >> SDHC_CA0R_V30VSUP_Pos; |
| 286 | } |
| 287 | |
| 288 | static inline bool hri_sdhc_get_CA0R_V18VSUP_bit(const void *const hw) |
| 289 | { |
| 290 | return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V18VSUP) >> SDHC_CA0R_V18VSUP_Pos; |
| 291 | } |
| 292 | |
| 293 | static inline bool hri_sdhc_get_CA0R_SB64SUP_bit(const void *const hw) |
| 294 | { |
| 295 | return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SB64SUP) >> SDHC_CA0R_SB64SUP_Pos; |
| 296 | } |
| 297 | |
| 298 | static inline bool hri_sdhc_get_CA0R_ASINTSUP_bit(const void *const hw) |
| 299 | { |
| 300 | return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ASINTSUP) >> SDHC_CA0R_ASINTSUP_Pos; |
| 301 | } |
| 302 | |
| 303 | static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_TEOCLKF_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) |
| 304 | { |
| 305 | return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKF(mask)) >> SDHC_CA0R_TEOCLKF_Pos; |
| 306 | } |
| 307 | |
| 308 | static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_TEOCLKF_bf(const void *const hw) |
| 309 | { |
| 310 | return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKF_Msk) >> SDHC_CA0R_TEOCLKF_Pos; |
| 311 | } |
| 312 | |
| 313 | static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_BASECLKF_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) |
| 314 | { |
| 315 | return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_BASECLKF(mask)) >> SDHC_CA0R_BASECLKF_Pos; |
| 316 | } |
| 317 | |
| 318 | static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_BASECLKF_bf(const void *const hw) |
| 319 | { |
| 320 | return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_BASECLKF_Msk) >> SDHC_CA0R_BASECLKF_Pos; |
| 321 | } |
| 322 | |
| 323 | static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_MAXBLKL_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) |
| 324 | { |
| 325 | return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_MAXBLKL(mask)) >> SDHC_CA0R_MAXBLKL_Pos; |
| 326 | } |
| 327 | |
| 328 | static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_MAXBLKL_bf(const void *const hw) |
| 329 | { |
| 330 | return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_MAXBLKL_Msk) >> SDHC_CA0R_MAXBLKL_Pos; |
| 331 | } |
| 332 | |
| 333 | static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_SLTYPE_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) |
| 334 | { |
| 335 | return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SLTYPE(mask)) >> SDHC_CA0R_SLTYPE_Pos; |
| 336 | } |
| 337 | |
| 338 | static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_SLTYPE_bf(const void *const hw) |
| 339 | { |
| 340 | return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SLTYPE_Msk) >> SDHC_CA0R_SLTYPE_Pos; |
| 341 | } |
| 342 | |
| 343 | static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_reg(const void *const hw, hri_sdhc_ca0r_reg_t mask) |
| 344 | { |
| 345 | uint32_t tmp; |
| 346 | tmp = ((Sdhc *)hw)->CA0R.reg; |
| 347 | tmp &= mask; |
| 348 | return tmp; |
| 349 | } |
| 350 | |
| 351 | static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_reg(const void *const hw) |
| 352 | { |
| 353 | return ((Sdhc *)hw)->CA0R.reg; |
| 354 | } |
| 355 | |
| 356 | static inline bool hri_sdhc_get_CA1R_SDR50SUP_bit(const void *const hw) |
| 357 | { |
| 358 | return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_SDR50SUP) >> SDHC_CA1R_SDR50SUP_Pos; |
| 359 | } |
| 360 | |
| 361 | static inline bool hri_sdhc_get_CA1R_SDR104SUP_bit(const void *const hw) |
| 362 | { |
| 363 | return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_SDR104SUP) >> SDHC_CA1R_SDR104SUP_Pos; |
| 364 | } |
| 365 | |
| 366 | static inline bool hri_sdhc_get_CA1R_DDR50SUP_bit(const void *const hw) |
| 367 | { |
| 368 | return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DDR50SUP) >> SDHC_CA1R_DDR50SUP_Pos; |
| 369 | } |
| 370 | |
| 371 | static inline bool hri_sdhc_get_CA1R_DRVASUP_bit(const void *const hw) |
| 372 | { |
| 373 | return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVASUP) >> SDHC_CA1R_DRVASUP_Pos; |
| 374 | } |
| 375 | |
| 376 | static inline bool hri_sdhc_get_CA1R_DRVCSUP_bit(const void *const hw) |
| 377 | { |
| 378 | return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVCSUP) >> SDHC_CA1R_DRVCSUP_Pos; |
| 379 | } |
| 380 | |
| 381 | static inline bool hri_sdhc_get_CA1R_DRVDSUP_bit(const void *const hw) |
| 382 | { |
| 383 | return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVDSUP) >> SDHC_CA1R_DRVDSUP_Pos; |
| 384 | } |
| 385 | |
| 386 | static inline bool hri_sdhc_get_CA1R_TSDR50_bit(const void *const hw) |
| 387 | { |
| 388 | return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TSDR50) >> SDHC_CA1R_TSDR50_Pos; |
| 389 | } |
| 390 | |
| 391 | static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_TCNTRT_bf(const void *const hw, hri_sdhc_ca1r_reg_t mask) |
| 392 | { |
| 393 | return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TCNTRT(mask)) >> SDHC_CA1R_TCNTRT_Pos; |
| 394 | } |
| 395 | |
| 396 | static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_TCNTRT_bf(const void *const hw) |
| 397 | { |
| 398 | return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TCNTRT_Msk) >> SDHC_CA1R_TCNTRT_Pos; |
| 399 | } |
| 400 | |
| 401 | static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_CLKMULT_bf(const void *const hw, hri_sdhc_ca1r_reg_t mask) |
| 402 | { |
| 403 | return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_CLKMULT(mask)) >> SDHC_CA1R_CLKMULT_Pos; |
| 404 | } |
| 405 | |
| 406 | static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_CLKMULT_bf(const void *const hw) |
| 407 | { |
| 408 | return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_CLKMULT_Msk) >> SDHC_CA1R_CLKMULT_Pos; |
| 409 | } |
| 410 | |
| 411 | static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_reg(const void *const hw, hri_sdhc_ca1r_reg_t mask) |
| 412 | { |
| 413 | uint32_t tmp; |
| 414 | tmp = ((Sdhc *)hw)->CA1R.reg; |
| 415 | tmp &= mask; |
| 416 | return tmp; |
| 417 | } |
| 418 | |
| 419 | static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_reg(const void *const hw) |
| 420 | { |
| 421 | return ((Sdhc *)hw)->CA1R.reg; |
| 422 | } |
| 423 | |
| 424 | static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR33V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask) |
| 425 | { |
| 426 | return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR33V(mask)) >> SDHC_MCCAR_MAXCUR33V_Pos; |
| 427 | } |
| 428 | |
| 429 | static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR33V_bf(const void *const hw) |
| 430 | { |
| 431 | return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR33V_Msk) >> SDHC_MCCAR_MAXCUR33V_Pos; |
| 432 | } |
| 433 | |
| 434 | static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR30V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask) |
| 435 | { |
| 436 | return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR30V(mask)) >> SDHC_MCCAR_MAXCUR30V_Pos; |
| 437 | } |
| 438 | |
| 439 | static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR30V_bf(const void *const hw) |
| 440 | { |
| 441 | return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR30V_Msk) >> SDHC_MCCAR_MAXCUR30V_Pos; |
| 442 | } |
| 443 | |
| 444 | static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR18V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask) |
| 445 | { |
| 446 | return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR18V(mask)) >> SDHC_MCCAR_MAXCUR18V_Pos; |
| 447 | } |
| 448 | |
| 449 | static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR18V_bf(const void *const hw) |
| 450 | { |
| 451 | return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR18V_Msk) >> SDHC_MCCAR_MAXCUR18V_Pos; |
| 452 | } |
| 453 | |
| 454 | static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_reg(const void *const hw, hri_sdhc_mccar_reg_t mask) |
| 455 | { |
| 456 | uint32_t tmp; |
| 457 | tmp = ((Sdhc *)hw)->MCCAR.reg; |
| 458 | tmp &= mask; |
| 459 | return tmp; |
| 460 | } |
| 461 | |
| 462 | static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_reg(const void *const hw) |
| 463 | { |
| 464 | return ((Sdhc *)hw)->MCCAR.reg; |
| 465 | } |
| 466 | |
| 467 | static inline bool hri_sdhc_get_AESR_LMIS_bit(const void *const hw) |
| 468 | { |
| 469 | return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_LMIS) >> SDHC_AESR_LMIS_Pos; |
| 470 | } |
| 471 | |
| 472 | static inline hri_sdhc_aesr_reg_t hri_sdhc_get_AESR_ERRST_bf(const void *const hw, hri_sdhc_aesr_reg_t mask) |
| 473 | { |
| 474 | return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_ERRST(mask)) >> SDHC_AESR_ERRST_Pos; |
| 475 | } |
| 476 | |
| 477 | static inline hri_sdhc_aesr_reg_t hri_sdhc_read_AESR_ERRST_bf(const void *const hw) |
| 478 | { |
| 479 | return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_ERRST_Msk) >> SDHC_AESR_ERRST_Pos; |
| 480 | } |
| 481 | |
| 482 | static inline hri_sdhc_aesr_reg_t hri_sdhc_get_AESR_reg(const void *const hw, hri_sdhc_aesr_reg_t mask) |
| 483 | { |
| 484 | uint8_t tmp; |
| 485 | tmp = ((Sdhc *)hw)->AESR.reg; |
| 486 | tmp &= mask; |
| 487 | return tmp; |
| 488 | } |
| 489 | |
| 490 | static inline hri_sdhc_aesr_reg_t hri_sdhc_read_AESR_reg(const void *const hw) |
| 491 | { |
| 492 | return ((Sdhc *)hw)->AESR.reg; |
| 493 | } |
| 494 | |
| 495 | static inline bool hri_sdhc_get_SISR_INTSSL_bit(const void *const hw) |
| 496 | { |
| 497 | return (((Sdhc *)hw)->SISR.reg & SDHC_SISR_INTSSL_Msk) >> SDHC_SISR_INTSSL_Pos; |
| 498 | } |
| 499 | |
| 500 | static inline hri_sdhc_sisr_reg_t hri_sdhc_get_SISR_reg(const void *const hw, hri_sdhc_sisr_reg_t mask) |
| 501 | { |
| 502 | uint16_t tmp; |
| 503 | tmp = ((Sdhc *)hw)->SISR.reg; |
| 504 | tmp &= mask; |
| 505 | return tmp; |
| 506 | } |
| 507 | |
| 508 | static inline hri_sdhc_sisr_reg_t hri_sdhc_read_SISR_reg(const void *const hw) |
| 509 | { |
| 510 | return ((Sdhc *)hw)->SISR.reg; |
| 511 | } |
| 512 | |
| 513 | static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_SVER_bf(const void *const hw, hri_sdhc_hcvr_reg_t mask) |
| 514 | { |
| 515 | return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_SVER(mask)) >> SDHC_HCVR_SVER_Pos; |
| 516 | } |
| 517 | |
| 518 | static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_SVER_bf(const void *const hw) |
| 519 | { |
| 520 | return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_SVER_Msk) >> SDHC_HCVR_SVER_Pos; |
| 521 | } |
| 522 | |
| 523 | static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_VVER_bf(const void *const hw, hri_sdhc_hcvr_reg_t mask) |
| 524 | { |
| 525 | return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_VVER(mask)) >> SDHC_HCVR_VVER_Pos; |
| 526 | } |
| 527 | |
| 528 | static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_VVER_bf(const void *const hw) |
| 529 | { |
| 530 | return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_VVER_Msk) >> SDHC_HCVR_VVER_Pos; |
| 531 | } |
| 532 | |
| 533 | static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_reg(const void *const hw, hri_sdhc_hcvr_reg_t mask) |
| 534 | { |
| 535 | uint16_t tmp; |
| 536 | tmp = ((Sdhc *)hw)->HCVR.reg; |
| 537 | tmp &= mask; |
| 538 | return tmp; |
| 539 | } |
| 540 | |
| 541 | static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_reg(const void *const hw) |
| 542 | { |
| 543 | return ((Sdhc *)hw)->HCVR.reg; |
| 544 | } |
| 545 | |
| 546 | static inline void hri_sdhc_set_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) |
| 547 | { |
| 548 | SDHC_CRITICAL_SECTION_ENTER(); |
| 549 | ((Sdhc *)hw)->SSAR.reg |= SDHC_SSAR_ADDR(mask); |
| 550 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 551 | } |
| 552 | |
| 553 | static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) |
| 554 | { |
| 555 | uint32_t tmp; |
| 556 | tmp = ((Sdhc *)hw)->SSAR.reg; |
| 557 | tmp = (tmp & SDHC_SSAR_ADDR(mask)) >> SDHC_SSAR_ADDR_Pos; |
| 558 | return tmp; |
| 559 | } |
| 560 | |
| 561 | static inline void hri_sdhc_write_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t data) |
| 562 | { |
| 563 | uint32_t tmp; |
| 564 | SDHC_CRITICAL_SECTION_ENTER(); |
| 565 | tmp = ((Sdhc *)hw)->SSAR.reg; |
| 566 | tmp &= ~SDHC_SSAR_ADDR_Msk; |
| 567 | tmp |= SDHC_SSAR_ADDR(data); |
| 568 | ((Sdhc *)hw)->SSAR.reg = tmp; |
| 569 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 570 | } |
| 571 | |
| 572 | static inline void hri_sdhc_clear_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) |
| 573 | { |
| 574 | SDHC_CRITICAL_SECTION_ENTER(); |
| 575 | ((Sdhc *)hw)->SSAR.reg &= ~SDHC_SSAR_ADDR(mask); |
| 576 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 577 | } |
| 578 | |
| 579 | static inline void hri_sdhc_toggle_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) |
| 580 | { |
| 581 | SDHC_CRITICAL_SECTION_ENTER(); |
| 582 | ((Sdhc *)hw)->SSAR.reg ^= SDHC_SSAR_ADDR(mask); |
| 583 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 584 | } |
| 585 | |
| 586 | static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_ADDR_bf(const void *const hw) |
| 587 | { |
| 588 | uint32_t tmp; |
| 589 | tmp = ((Sdhc *)hw)->SSAR.reg; |
| 590 | tmp = (tmp & SDHC_SSAR_ADDR_Msk) >> SDHC_SSAR_ADDR_Pos; |
| 591 | return tmp; |
| 592 | } |
| 593 | |
| 594 | static inline void hri_sdhc_set_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) |
| 595 | { |
| 596 | SDHC_CRITICAL_SECTION_ENTER(); |
| 597 | ((Sdhc *)hw)->SSAR.reg |= SDHC_SSAR_CMD23_ARG2(mask); |
| 598 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 599 | } |
| 600 | |
| 601 | static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) |
| 602 | { |
| 603 | uint32_t tmp; |
| 604 | tmp = ((Sdhc *)hw)->SSAR.reg; |
| 605 | tmp = (tmp & SDHC_SSAR_CMD23_ARG2(mask)) >> SDHC_SSAR_CMD23_ARG2_Pos; |
| 606 | return tmp; |
| 607 | } |
| 608 | |
| 609 | static inline void hri_sdhc_write_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t data) |
| 610 | { |
| 611 | uint32_t tmp; |
| 612 | SDHC_CRITICAL_SECTION_ENTER(); |
| 613 | tmp = ((Sdhc *)hw)->SSAR.reg; |
| 614 | tmp &= ~SDHC_SSAR_CMD23_ARG2_Msk; |
| 615 | tmp |= SDHC_SSAR_CMD23_ARG2(data); |
| 616 | ((Sdhc *)hw)->SSAR.reg = tmp; |
| 617 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 618 | } |
| 619 | |
| 620 | static inline void hri_sdhc_clear_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) |
| 621 | { |
| 622 | SDHC_CRITICAL_SECTION_ENTER(); |
| 623 | ((Sdhc *)hw)->SSAR.reg &= ~SDHC_SSAR_CMD23_ARG2(mask); |
| 624 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 625 | } |
| 626 | |
| 627 | static inline void hri_sdhc_toggle_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) |
| 628 | { |
| 629 | SDHC_CRITICAL_SECTION_ENTER(); |
| 630 | ((Sdhc *)hw)->SSAR.reg ^= SDHC_SSAR_CMD23_ARG2(mask); |
| 631 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 632 | } |
| 633 | |
| 634 | static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_CMD23_ARG2_bf(const void *const hw) |
| 635 | { |
| 636 | uint32_t tmp; |
| 637 | tmp = ((Sdhc *)hw)->SSAR.reg; |
| 638 | tmp = (tmp & SDHC_SSAR_CMD23_ARG2_Msk) >> SDHC_SSAR_CMD23_ARG2_Pos; |
| 639 | return tmp; |
| 640 | } |
| 641 | |
| 642 | static inline void hri_sdhc_set_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) |
| 643 | { |
| 644 | SDHC_CRITICAL_SECTION_ENTER(); |
| 645 | ((Sdhc *)hw)->SSAR.reg |= mask; |
| 646 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 647 | } |
| 648 | |
| 649 | static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) |
| 650 | { |
| 651 | uint32_t tmp; |
| 652 | tmp = ((Sdhc *)hw)->SSAR.reg; |
| 653 | tmp &= mask; |
| 654 | return tmp; |
| 655 | } |
| 656 | |
| 657 | static inline void hri_sdhc_write_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t data) |
| 658 | { |
| 659 | SDHC_CRITICAL_SECTION_ENTER(); |
| 660 | ((Sdhc *)hw)->SSAR.reg = data; |
| 661 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 662 | } |
| 663 | |
| 664 | static inline void hri_sdhc_clear_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) |
| 665 | { |
| 666 | SDHC_CRITICAL_SECTION_ENTER(); |
| 667 | ((Sdhc *)hw)->SSAR.reg &= ~mask; |
| 668 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 669 | } |
| 670 | |
| 671 | static inline void hri_sdhc_toggle_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) |
| 672 | { |
| 673 | SDHC_CRITICAL_SECTION_ENTER(); |
| 674 | ((Sdhc *)hw)->SSAR.reg ^= mask; |
| 675 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 676 | } |
| 677 | |
| 678 | static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_reg(const void *const hw) |
| 679 | { |
| 680 | return ((Sdhc *)hw)->SSAR.reg; |
| 681 | } |
| 682 | |
| 683 | static inline void hri_sdhc_set_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) |
| 684 | { |
| 685 | SDHC_CRITICAL_SECTION_ENTER(); |
| 686 | ((Sdhc *)hw)->BSR.reg |= SDHC_BSR_BLOCKSIZE(mask); |
| 687 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 688 | } |
| 689 | |
| 690 | static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) |
| 691 | { |
| 692 | uint16_t tmp; |
| 693 | tmp = ((Sdhc *)hw)->BSR.reg; |
| 694 | tmp = (tmp & SDHC_BSR_BLOCKSIZE(mask)) >> SDHC_BSR_BLOCKSIZE_Pos; |
| 695 | return tmp; |
| 696 | } |
| 697 | |
| 698 | static inline void hri_sdhc_write_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t data) |
| 699 | { |
| 700 | uint16_t tmp; |
| 701 | SDHC_CRITICAL_SECTION_ENTER(); |
| 702 | tmp = ((Sdhc *)hw)->BSR.reg; |
| 703 | tmp &= ~SDHC_BSR_BLOCKSIZE_Msk; |
| 704 | tmp |= SDHC_BSR_BLOCKSIZE(data); |
| 705 | ((Sdhc *)hw)->BSR.reg = tmp; |
| 706 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 707 | } |
| 708 | |
| 709 | static inline void hri_sdhc_clear_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) |
| 710 | { |
| 711 | SDHC_CRITICAL_SECTION_ENTER(); |
| 712 | ((Sdhc *)hw)->BSR.reg &= ~SDHC_BSR_BLOCKSIZE(mask); |
| 713 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 714 | } |
| 715 | |
| 716 | static inline void hri_sdhc_toggle_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) |
| 717 | { |
| 718 | SDHC_CRITICAL_SECTION_ENTER(); |
| 719 | ((Sdhc *)hw)->BSR.reg ^= SDHC_BSR_BLOCKSIZE(mask); |
| 720 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 721 | } |
| 722 | |
| 723 | static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_BLOCKSIZE_bf(const void *const hw) |
| 724 | { |
| 725 | uint16_t tmp; |
| 726 | tmp = ((Sdhc *)hw)->BSR.reg; |
| 727 | tmp = (tmp & SDHC_BSR_BLOCKSIZE_Msk) >> SDHC_BSR_BLOCKSIZE_Pos; |
| 728 | return tmp; |
| 729 | } |
| 730 | |
| 731 | static inline void hri_sdhc_set_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) |
| 732 | { |
| 733 | SDHC_CRITICAL_SECTION_ENTER(); |
| 734 | ((Sdhc *)hw)->BSR.reg |= SDHC_BSR_BOUNDARY(mask); |
| 735 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 736 | } |
| 737 | |
| 738 | static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) |
| 739 | { |
| 740 | uint16_t tmp; |
| 741 | tmp = ((Sdhc *)hw)->BSR.reg; |
| 742 | tmp = (tmp & SDHC_BSR_BOUNDARY(mask)) >> SDHC_BSR_BOUNDARY_Pos; |
| 743 | return tmp; |
| 744 | } |
| 745 | |
| 746 | static inline void hri_sdhc_write_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t data) |
| 747 | { |
| 748 | uint16_t tmp; |
| 749 | SDHC_CRITICAL_SECTION_ENTER(); |
| 750 | tmp = ((Sdhc *)hw)->BSR.reg; |
| 751 | tmp &= ~SDHC_BSR_BOUNDARY_Msk; |
| 752 | tmp |= SDHC_BSR_BOUNDARY(data); |
| 753 | ((Sdhc *)hw)->BSR.reg = tmp; |
| 754 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 755 | } |
| 756 | |
| 757 | static inline void hri_sdhc_clear_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) |
| 758 | { |
| 759 | SDHC_CRITICAL_SECTION_ENTER(); |
| 760 | ((Sdhc *)hw)->BSR.reg &= ~SDHC_BSR_BOUNDARY(mask); |
| 761 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 762 | } |
| 763 | |
| 764 | static inline void hri_sdhc_toggle_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) |
| 765 | { |
| 766 | SDHC_CRITICAL_SECTION_ENTER(); |
| 767 | ((Sdhc *)hw)->BSR.reg ^= SDHC_BSR_BOUNDARY(mask); |
| 768 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 769 | } |
| 770 | |
| 771 | static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_BOUNDARY_bf(const void *const hw) |
| 772 | { |
| 773 | uint16_t tmp; |
| 774 | tmp = ((Sdhc *)hw)->BSR.reg; |
| 775 | tmp = (tmp & SDHC_BSR_BOUNDARY_Msk) >> SDHC_BSR_BOUNDARY_Pos; |
| 776 | return tmp; |
| 777 | } |
| 778 | |
| 779 | static inline void hri_sdhc_set_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) |
| 780 | { |
| 781 | SDHC_CRITICAL_SECTION_ENTER(); |
| 782 | ((Sdhc *)hw)->BSR.reg |= mask; |
| 783 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 784 | } |
| 785 | |
| 786 | static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) |
| 787 | { |
| 788 | uint16_t tmp; |
| 789 | tmp = ((Sdhc *)hw)->BSR.reg; |
| 790 | tmp &= mask; |
| 791 | return tmp; |
| 792 | } |
| 793 | |
| 794 | static inline void hri_sdhc_write_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t data) |
| 795 | { |
| 796 | SDHC_CRITICAL_SECTION_ENTER(); |
| 797 | ((Sdhc *)hw)->BSR.reg = data; |
| 798 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 799 | } |
| 800 | |
| 801 | static inline void hri_sdhc_clear_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) |
| 802 | { |
| 803 | SDHC_CRITICAL_SECTION_ENTER(); |
| 804 | ((Sdhc *)hw)->BSR.reg &= ~mask; |
| 805 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 806 | } |
| 807 | |
| 808 | static inline void hri_sdhc_toggle_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) |
| 809 | { |
| 810 | SDHC_CRITICAL_SECTION_ENTER(); |
| 811 | ((Sdhc *)hw)->BSR.reg ^= mask; |
| 812 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 813 | } |
| 814 | |
| 815 | static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_reg(const void *const hw) |
| 816 | { |
| 817 | return ((Sdhc *)hw)->BSR.reg; |
| 818 | } |
| 819 | |
| 820 | static inline void hri_sdhc_set_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) |
| 821 | { |
| 822 | SDHC_CRITICAL_SECTION_ENTER(); |
| 823 | ((Sdhc *)hw)->BCR.reg |= SDHC_BCR_BCNT(mask); |
| 824 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 825 | } |
| 826 | |
| 827 | static inline hri_sdhc_bcr_reg_t hri_sdhc_get_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) |
| 828 | { |
| 829 | uint16_t tmp; |
| 830 | tmp = ((Sdhc *)hw)->BCR.reg; |
| 831 | tmp = (tmp & SDHC_BCR_BCNT(mask)) >> SDHC_BCR_BCNT_Pos; |
| 832 | return tmp; |
| 833 | } |
| 834 | |
| 835 | static inline void hri_sdhc_write_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t data) |
| 836 | { |
| 837 | uint16_t tmp; |
| 838 | SDHC_CRITICAL_SECTION_ENTER(); |
| 839 | tmp = ((Sdhc *)hw)->BCR.reg; |
| 840 | tmp &= ~SDHC_BCR_BCNT_Msk; |
| 841 | tmp |= SDHC_BCR_BCNT(data); |
| 842 | ((Sdhc *)hw)->BCR.reg = tmp; |
| 843 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 844 | } |
| 845 | |
| 846 | static inline void hri_sdhc_clear_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) |
| 847 | { |
| 848 | SDHC_CRITICAL_SECTION_ENTER(); |
| 849 | ((Sdhc *)hw)->BCR.reg &= ~SDHC_BCR_BCNT(mask); |
| 850 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 851 | } |
| 852 | |
| 853 | static inline void hri_sdhc_toggle_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) |
| 854 | { |
| 855 | SDHC_CRITICAL_SECTION_ENTER(); |
| 856 | ((Sdhc *)hw)->BCR.reg ^= SDHC_BCR_BCNT(mask); |
| 857 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 858 | } |
| 859 | |
| 860 | static inline hri_sdhc_bcr_reg_t hri_sdhc_read_BCR_BCNT_bf(const void *const hw) |
| 861 | { |
| 862 | uint16_t tmp; |
| 863 | tmp = ((Sdhc *)hw)->BCR.reg; |
| 864 | tmp = (tmp & SDHC_BCR_BCNT_Msk) >> SDHC_BCR_BCNT_Pos; |
| 865 | return tmp; |
| 866 | } |
| 867 | |
| 868 | static inline void hri_sdhc_set_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) |
| 869 | { |
| 870 | SDHC_CRITICAL_SECTION_ENTER(); |
| 871 | ((Sdhc *)hw)->BCR.reg |= mask; |
| 872 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 873 | } |
| 874 | |
| 875 | static inline hri_sdhc_bcr_reg_t hri_sdhc_get_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) |
| 876 | { |
| 877 | uint16_t tmp; |
| 878 | tmp = ((Sdhc *)hw)->BCR.reg; |
| 879 | tmp &= mask; |
| 880 | return tmp; |
| 881 | } |
| 882 | |
| 883 | static inline void hri_sdhc_write_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t data) |
| 884 | { |
| 885 | SDHC_CRITICAL_SECTION_ENTER(); |
| 886 | ((Sdhc *)hw)->BCR.reg = data; |
| 887 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 888 | } |
| 889 | |
| 890 | static inline void hri_sdhc_clear_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) |
| 891 | { |
| 892 | SDHC_CRITICAL_SECTION_ENTER(); |
| 893 | ((Sdhc *)hw)->BCR.reg &= ~mask; |
| 894 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 895 | } |
| 896 | |
| 897 | static inline void hri_sdhc_toggle_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) |
| 898 | { |
| 899 | SDHC_CRITICAL_SECTION_ENTER(); |
| 900 | ((Sdhc *)hw)->BCR.reg ^= mask; |
| 901 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 902 | } |
| 903 | |
| 904 | static inline hri_sdhc_bcr_reg_t hri_sdhc_read_BCR_reg(const void *const hw) |
| 905 | { |
| 906 | return ((Sdhc *)hw)->BCR.reg; |
| 907 | } |
| 908 | |
| 909 | static inline void hri_sdhc_set_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) |
| 910 | { |
| 911 | SDHC_CRITICAL_SECTION_ENTER(); |
| 912 | ((Sdhc *)hw)->ARG1R.reg |= SDHC_ARG1R_ARG(mask); |
| 913 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 914 | } |
| 915 | |
| 916 | static inline hri_sdhc_arg1r_reg_t hri_sdhc_get_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) |
| 917 | { |
| 918 | uint32_t tmp; |
| 919 | tmp = ((Sdhc *)hw)->ARG1R.reg; |
| 920 | tmp = (tmp & SDHC_ARG1R_ARG(mask)) >> SDHC_ARG1R_ARG_Pos; |
| 921 | return tmp; |
| 922 | } |
| 923 | |
| 924 | static inline void hri_sdhc_write_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t data) |
| 925 | { |
| 926 | uint32_t tmp; |
| 927 | SDHC_CRITICAL_SECTION_ENTER(); |
| 928 | tmp = ((Sdhc *)hw)->ARG1R.reg; |
| 929 | tmp &= ~SDHC_ARG1R_ARG_Msk; |
| 930 | tmp |= SDHC_ARG1R_ARG(data); |
| 931 | ((Sdhc *)hw)->ARG1R.reg = tmp; |
| 932 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 933 | } |
| 934 | |
| 935 | static inline void hri_sdhc_clear_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) |
| 936 | { |
| 937 | SDHC_CRITICAL_SECTION_ENTER(); |
| 938 | ((Sdhc *)hw)->ARG1R.reg &= ~SDHC_ARG1R_ARG(mask); |
| 939 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 940 | } |
| 941 | |
| 942 | static inline void hri_sdhc_toggle_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) |
| 943 | { |
| 944 | SDHC_CRITICAL_SECTION_ENTER(); |
| 945 | ((Sdhc *)hw)->ARG1R.reg ^= SDHC_ARG1R_ARG(mask); |
| 946 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 947 | } |
| 948 | |
| 949 | static inline hri_sdhc_arg1r_reg_t hri_sdhc_read_ARG1R_ARG_bf(const void *const hw) |
| 950 | { |
| 951 | uint32_t tmp; |
| 952 | tmp = ((Sdhc *)hw)->ARG1R.reg; |
| 953 | tmp = (tmp & SDHC_ARG1R_ARG_Msk) >> SDHC_ARG1R_ARG_Pos; |
| 954 | return tmp; |
| 955 | } |
| 956 | |
| 957 | static inline void hri_sdhc_set_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) |
| 958 | { |
| 959 | SDHC_CRITICAL_SECTION_ENTER(); |
| 960 | ((Sdhc *)hw)->ARG1R.reg |= mask; |
| 961 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 962 | } |
| 963 | |
| 964 | static inline hri_sdhc_arg1r_reg_t hri_sdhc_get_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) |
| 965 | { |
| 966 | uint32_t tmp; |
| 967 | tmp = ((Sdhc *)hw)->ARG1R.reg; |
| 968 | tmp &= mask; |
| 969 | return tmp; |
| 970 | } |
| 971 | |
| 972 | static inline void hri_sdhc_write_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t data) |
| 973 | { |
| 974 | SDHC_CRITICAL_SECTION_ENTER(); |
| 975 | ((Sdhc *)hw)->ARG1R.reg = data; |
| 976 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 977 | } |
| 978 | |
| 979 | static inline void hri_sdhc_clear_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) |
| 980 | { |
| 981 | SDHC_CRITICAL_SECTION_ENTER(); |
| 982 | ((Sdhc *)hw)->ARG1R.reg &= ~mask; |
| 983 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 984 | } |
| 985 | |
| 986 | static inline void hri_sdhc_toggle_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) |
| 987 | { |
| 988 | SDHC_CRITICAL_SECTION_ENTER(); |
| 989 | ((Sdhc *)hw)->ARG1R.reg ^= mask; |
| 990 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 991 | } |
| 992 | |
| 993 | static inline hri_sdhc_arg1r_reg_t hri_sdhc_read_ARG1R_reg(const void *const hw) |
| 994 | { |
| 995 | return ((Sdhc *)hw)->ARG1R.reg; |
| 996 | } |
| 997 | |
| 998 | static inline void hri_sdhc_set_TMR_DMAEN_bit(const void *const hw) |
| 999 | { |
| 1000 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1001 | ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_DMAEN; |
| 1002 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1003 | } |
| 1004 | |
| 1005 | static inline bool hri_sdhc_get_TMR_DMAEN_bit(const void *const hw) |
| 1006 | { |
| 1007 | uint16_t tmp; |
| 1008 | tmp = ((Sdhc *)hw)->TMR.reg; |
| 1009 | tmp = (tmp & SDHC_TMR_DMAEN) >> SDHC_TMR_DMAEN_Pos; |
| 1010 | return (bool)tmp; |
| 1011 | } |
| 1012 | |
| 1013 | static inline void hri_sdhc_write_TMR_DMAEN_bit(const void *const hw, bool value) |
| 1014 | { |
| 1015 | uint16_t tmp; |
| 1016 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1017 | tmp = ((Sdhc *)hw)->TMR.reg; |
| 1018 | tmp &= ~SDHC_TMR_DMAEN; |
| 1019 | tmp |= value << SDHC_TMR_DMAEN_Pos; |
| 1020 | ((Sdhc *)hw)->TMR.reg = tmp; |
| 1021 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1022 | } |
| 1023 | |
| 1024 | static inline void hri_sdhc_clear_TMR_DMAEN_bit(const void *const hw) |
| 1025 | { |
| 1026 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1027 | ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_DMAEN; |
| 1028 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1029 | } |
| 1030 | |
| 1031 | static inline void hri_sdhc_toggle_TMR_DMAEN_bit(const void *const hw) |
| 1032 | { |
| 1033 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1034 | ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_DMAEN; |
| 1035 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1036 | } |
| 1037 | |
| 1038 | static inline void hri_sdhc_set_TMR_BCEN_bit(const void *const hw) |
| 1039 | { |
| 1040 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1041 | ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_BCEN; |
| 1042 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1043 | } |
| 1044 | |
| 1045 | static inline bool hri_sdhc_get_TMR_BCEN_bit(const void *const hw) |
| 1046 | { |
| 1047 | uint16_t tmp; |
| 1048 | tmp = ((Sdhc *)hw)->TMR.reg; |
| 1049 | tmp = (tmp & SDHC_TMR_BCEN) >> SDHC_TMR_BCEN_Pos; |
| 1050 | return (bool)tmp; |
| 1051 | } |
| 1052 | |
| 1053 | static inline void hri_sdhc_write_TMR_BCEN_bit(const void *const hw, bool value) |
| 1054 | { |
| 1055 | uint16_t tmp; |
| 1056 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1057 | tmp = ((Sdhc *)hw)->TMR.reg; |
| 1058 | tmp &= ~SDHC_TMR_BCEN; |
| 1059 | tmp |= value << SDHC_TMR_BCEN_Pos; |
| 1060 | ((Sdhc *)hw)->TMR.reg = tmp; |
| 1061 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1062 | } |
| 1063 | |
| 1064 | static inline void hri_sdhc_clear_TMR_BCEN_bit(const void *const hw) |
| 1065 | { |
| 1066 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1067 | ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_BCEN; |
| 1068 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1069 | } |
| 1070 | |
| 1071 | static inline void hri_sdhc_toggle_TMR_BCEN_bit(const void *const hw) |
| 1072 | { |
| 1073 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1074 | ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_BCEN; |
| 1075 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1076 | } |
| 1077 | |
| 1078 | static inline void hri_sdhc_set_TMR_DTDSEL_bit(const void *const hw) |
| 1079 | { |
| 1080 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1081 | ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_DTDSEL; |
| 1082 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1083 | } |
| 1084 | |
| 1085 | static inline bool hri_sdhc_get_TMR_DTDSEL_bit(const void *const hw) |
| 1086 | { |
| 1087 | uint16_t tmp; |
| 1088 | tmp = ((Sdhc *)hw)->TMR.reg; |
| 1089 | tmp = (tmp & SDHC_TMR_DTDSEL) >> SDHC_TMR_DTDSEL_Pos; |
| 1090 | return (bool)tmp; |
| 1091 | } |
| 1092 | |
| 1093 | static inline void hri_sdhc_write_TMR_DTDSEL_bit(const void *const hw, bool value) |
| 1094 | { |
| 1095 | uint16_t tmp; |
| 1096 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1097 | tmp = ((Sdhc *)hw)->TMR.reg; |
| 1098 | tmp &= ~SDHC_TMR_DTDSEL; |
| 1099 | tmp |= value << SDHC_TMR_DTDSEL_Pos; |
| 1100 | ((Sdhc *)hw)->TMR.reg = tmp; |
| 1101 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1102 | } |
| 1103 | |
| 1104 | static inline void hri_sdhc_clear_TMR_DTDSEL_bit(const void *const hw) |
| 1105 | { |
| 1106 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1107 | ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_DTDSEL; |
| 1108 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1109 | } |
| 1110 | |
| 1111 | static inline void hri_sdhc_toggle_TMR_DTDSEL_bit(const void *const hw) |
| 1112 | { |
| 1113 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1114 | ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_DTDSEL; |
| 1115 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1116 | } |
| 1117 | |
| 1118 | static inline void hri_sdhc_set_TMR_MSBSEL_bit(const void *const hw) |
| 1119 | { |
| 1120 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1121 | ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_MSBSEL; |
| 1122 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1123 | } |
| 1124 | |
| 1125 | static inline bool hri_sdhc_get_TMR_MSBSEL_bit(const void *const hw) |
| 1126 | { |
| 1127 | uint16_t tmp; |
| 1128 | tmp = ((Sdhc *)hw)->TMR.reg; |
| 1129 | tmp = (tmp & SDHC_TMR_MSBSEL) >> SDHC_TMR_MSBSEL_Pos; |
| 1130 | return (bool)tmp; |
| 1131 | } |
| 1132 | |
| 1133 | static inline void hri_sdhc_write_TMR_MSBSEL_bit(const void *const hw, bool value) |
| 1134 | { |
| 1135 | uint16_t tmp; |
| 1136 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1137 | tmp = ((Sdhc *)hw)->TMR.reg; |
| 1138 | tmp &= ~SDHC_TMR_MSBSEL; |
| 1139 | tmp |= value << SDHC_TMR_MSBSEL_Pos; |
| 1140 | ((Sdhc *)hw)->TMR.reg = tmp; |
| 1141 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1142 | } |
| 1143 | |
| 1144 | static inline void hri_sdhc_clear_TMR_MSBSEL_bit(const void *const hw) |
| 1145 | { |
| 1146 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1147 | ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_MSBSEL; |
| 1148 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1149 | } |
| 1150 | |
| 1151 | static inline void hri_sdhc_toggle_TMR_MSBSEL_bit(const void *const hw) |
| 1152 | { |
| 1153 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1154 | ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_MSBSEL; |
| 1155 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1156 | } |
| 1157 | |
| 1158 | static inline void hri_sdhc_set_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) |
| 1159 | { |
| 1160 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1161 | ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_ACMDEN(mask); |
| 1162 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1163 | } |
| 1164 | |
| 1165 | static inline hri_sdhc_tmr_reg_t hri_sdhc_get_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) |
| 1166 | { |
| 1167 | uint16_t tmp; |
| 1168 | tmp = ((Sdhc *)hw)->TMR.reg; |
| 1169 | tmp = (tmp & SDHC_TMR_ACMDEN(mask)) >> SDHC_TMR_ACMDEN_Pos; |
| 1170 | return tmp; |
| 1171 | } |
| 1172 | |
| 1173 | static inline void hri_sdhc_write_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t data) |
| 1174 | { |
| 1175 | uint16_t tmp; |
| 1176 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1177 | tmp = ((Sdhc *)hw)->TMR.reg; |
| 1178 | tmp &= ~SDHC_TMR_ACMDEN_Msk; |
| 1179 | tmp |= SDHC_TMR_ACMDEN(data); |
| 1180 | ((Sdhc *)hw)->TMR.reg = tmp; |
| 1181 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1182 | } |
| 1183 | |
| 1184 | static inline void hri_sdhc_clear_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) |
| 1185 | { |
| 1186 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1187 | ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_ACMDEN(mask); |
| 1188 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1189 | } |
| 1190 | |
| 1191 | static inline void hri_sdhc_toggle_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) |
| 1192 | { |
| 1193 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1194 | ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_ACMDEN(mask); |
| 1195 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1196 | } |
| 1197 | |
| 1198 | static inline hri_sdhc_tmr_reg_t hri_sdhc_read_TMR_ACMDEN_bf(const void *const hw) |
| 1199 | { |
| 1200 | uint16_t tmp; |
| 1201 | tmp = ((Sdhc *)hw)->TMR.reg; |
| 1202 | tmp = (tmp & SDHC_TMR_ACMDEN_Msk) >> SDHC_TMR_ACMDEN_Pos; |
| 1203 | return tmp; |
| 1204 | } |
| 1205 | |
| 1206 | static inline void hri_sdhc_set_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) |
| 1207 | { |
| 1208 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1209 | ((Sdhc *)hw)->TMR.reg |= mask; |
| 1210 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1211 | } |
| 1212 | |
| 1213 | static inline hri_sdhc_tmr_reg_t hri_sdhc_get_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) |
| 1214 | { |
| 1215 | uint16_t tmp; |
| 1216 | tmp = ((Sdhc *)hw)->TMR.reg; |
| 1217 | tmp &= mask; |
| 1218 | return tmp; |
| 1219 | } |
| 1220 | |
| 1221 | static inline void hri_sdhc_write_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t data) |
| 1222 | { |
| 1223 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1224 | ((Sdhc *)hw)->TMR.reg = data; |
| 1225 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1226 | } |
| 1227 | |
| 1228 | static inline void hri_sdhc_clear_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) |
| 1229 | { |
| 1230 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1231 | ((Sdhc *)hw)->TMR.reg &= ~mask; |
| 1232 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1233 | } |
| 1234 | |
| 1235 | static inline void hri_sdhc_toggle_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) |
| 1236 | { |
| 1237 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1238 | ((Sdhc *)hw)->TMR.reg ^= mask; |
| 1239 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1240 | } |
| 1241 | |
| 1242 | static inline hri_sdhc_tmr_reg_t hri_sdhc_read_TMR_reg(const void *const hw) |
| 1243 | { |
| 1244 | return ((Sdhc *)hw)->TMR.reg; |
| 1245 | } |
| 1246 | |
| 1247 | static inline void hri_sdhc_set_CR_CMDCCEN_bit(const void *const hw) |
| 1248 | { |
| 1249 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1250 | ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDCCEN; |
| 1251 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1252 | } |
| 1253 | |
| 1254 | static inline bool hri_sdhc_get_CR_CMDCCEN_bit(const void *const hw) |
| 1255 | { |
| 1256 | uint16_t tmp; |
| 1257 | tmp = ((Sdhc *)hw)->CR.reg; |
| 1258 | tmp = (tmp & SDHC_CR_CMDCCEN) >> SDHC_CR_CMDCCEN_Pos; |
| 1259 | return (bool)tmp; |
| 1260 | } |
| 1261 | |
| 1262 | static inline void hri_sdhc_write_CR_CMDCCEN_bit(const void *const hw, bool value) |
| 1263 | { |
| 1264 | uint16_t tmp; |
| 1265 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1266 | tmp = ((Sdhc *)hw)->CR.reg; |
| 1267 | tmp &= ~SDHC_CR_CMDCCEN; |
| 1268 | tmp |= value << SDHC_CR_CMDCCEN_Pos; |
| 1269 | ((Sdhc *)hw)->CR.reg = tmp; |
| 1270 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1271 | } |
| 1272 | |
| 1273 | static inline void hri_sdhc_clear_CR_CMDCCEN_bit(const void *const hw) |
| 1274 | { |
| 1275 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1276 | ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDCCEN; |
| 1277 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1278 | } |
| 1279 | |
| 1280 | static inline void hri_sdhc_toggle_CR_CMDCCEN_bit(const void *const hw) |
| 1281 | { |
| 1282 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1283 | ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDCCEN; |
| 1284 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1285 | } |
| 1286 | |
| 1287 | static inline void hri_sdhc_set_CR_CMDICEN_bit(const void *const hw) |
| 1288 | { |
| 1289 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1290 | ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDICEN; |
| 1291 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1292 | } |
| 1293 | |
| 1294 | static inline bool hri_sdhc_get_CR_CMDICEN_bit(const void *const hw) |
| 1295 | { |
| 1296 | uint16_t tmp; |
| 1297 | tmp = ((Sdhc *)hw)->CR.reg; |
| 1298 | tmp = (tmp & SDHC_CR_CMDICEN) >> SDHC_CR_CMDICEN_Pos; |
| 1299 | return (bool)tmp; |
| 1300 | } |
| 1301 | |
| 1302 | static inline void hri_sdhc_write_CR_CMDICEN_bit(const void *const hw, bool value) |
| 1303 | { |
| 1304 | uint16_t tmp; |
| 1305 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1306 | tmp = ((Sdhc *)hw)->CR.reg; |
| 1307 | tmp &= ~SDHC_CR_CMDICEN; |
| 1308 | tmp |= value << SDHC_CR_CMDICEN_Pos; |
| 1309 | ((Sdhc *)hw)->CR.reg = tmp; |
| 1310 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1311 | } |
| 1312 | |
| 1313 | static inline void hri_sdhc_clear_CR_CMDICEN_bit(const void *const hw) |
| 1314 | { |
| 1315 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1316 | ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDICEN; |
| 1317 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1318 | } |
| 1319 | |
| 1320 | static inline void hri_sdhc_toggle_CR_CMDICEN_bit(const void *const hw) |
| 1321 | { |
| 1322 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1323 | ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDICEN; |
| 1324 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1325 | } |
| 1326 | |
| 1327 | static inline void hri_sdhc_set_CR_DPSEL_bit(const void *const hw) |
| 1328 | { |
| 1329 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1330 | ((Sdhc *)hw)->CR.reg |= SDHC_CR_DPSEL; |
| 1331 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1332 | } |
| 1333 | |
| 1334 | static inline bool hri_sdhc_get_CR_DPSEL_bit(const void *const hw) |
| 1335 | { |
| 1336 | uint16_t tmp; |
| 1337 | tmp = ((Sdhc *)hw)->CR.reg; |
| 1338 | tmp = (tmp & SDHC_CR_DPSEL) >> SDHC_CR_DPSEL_Pos; |
| 1339 | return (bool)tmp; |
| 1340 | } |
| 1341 | |
| 1342 | static inline void hri_sdhc_write_CR_DPSEL_bit(const void *const hw, bool value) |
| 1343 | { |
| 1344 | uint16_t tmp; |
| 1345 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1346 | tmp = ((Sdhc *)hw)->CR.reg; |
| 1347 | tmp &= ~SDHC_CR_DPSEL; |
| 1348 | tmp |= value << SDHC_CR_DPSEL_Pos; |
| 1349 | ((Sdhc *)hw)->CR.reg = tmp; |
| 1350 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1351 | } |
| 1352 | |
| 1353 | static inline void hri_sdhc_clear_CR_DPSEL_bit(const void *const hw) |
| 1354 | { |
| 1355 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1356 | ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_DPSEL; |
| 1357 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1358 | } |
| 1359 | |
| 1360 | static inline void hri_sdhc_toggle_CR_DPSEL_bit(const void *const hw) |
| 1361 | { |
| 1362 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1363 | ((Sdhc *)hw)->CR.reg ^= SDHC_CR_DPSEL; |
| 1364 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1365 | } |
| 1366 | |
| 1367 | static inline void hri_sdhc_set_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) |
| 1368 | { |
| 1369 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1370 | ((Sdhc *)hw)->CR.reg |= SDHC_CR_RESPTYP(mask); |
| 1371 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1372 | } |
| 1373 | |
| 1374 | static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) |
| 1375 | { |
| 1376 | uint16_t tmp; |
| 1377 | tmp = ((Sdhc *)hw)->CR.reg; |
| 1378 | tmp = (tmp & SDHC_CR_RESPTYP(mask)) >> SDHC_CR_RESPTYP_Pos; |
| 1379 | return tmp; |
| 1380 | } |
| 1381 | |
| 1382 | static inline void hri_sdhc_write_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t data) |
| 1383 | { |
| 1384 | uint16_t tmp; |
| 1385 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1386 | tmp = ((Sdhc *)hw)->CR.reg; |
| 1387 | tmp &= ~SDHC_CR_RESPTYP_Msk; |
| 1388 | tmp |= SDHC_CR_RESPTYP(data); |
| 1389 | ((Sdhc *)hw)->CR.reg = tmp; |
| 1390 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1391 | } |
| 1392 | |
| 1393 | static inline void hri_sdhc_clear_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) |
| 1394 | { |
| 1395 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1396 | ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_RESPTYP(mask); |
| 1397 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1398 | } |
| 1399 | |
| 1400 | static inline void hri_sdhc_toggle_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) |
| 1401 | { |
| 1402 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1403 | ((Sdhc *)hw)->CR.reg ^= SDHC_CR_RESPTYP(mask); |
| 1404 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1405 | } |
| 1406 | |
| 1407 | static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_RESPTYP_bf(const void *const hw) |
| 1408 | { |
| 1409 | uint16_t tmp; |
| 1410 | tmp = ((Sdhc *)hw)->CR.reg; |
| 1411 | tmp = (tmp & SDHC_CR_RESPTYP_Msk) >> SDHC_CR_RESPTYP_Pos; |
| 1412 | return tmp; |
| 1413 | } |
| 1414 | |
| 1415 | static inline void hri_sdhc_set_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) |
| 1416 | { |
| 1417 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1418 | ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDTYP(mask); |
| 1419 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1420 | } |
| 1421 | |
| 1422 | static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) |
| 1423 | { |
| 1424 | uint16_t tmp; |
| 1425 | tmp = ((Sdhc *)hw)->CR.reg; |
| 1426 | tmp = (tmp & SDHC_CR_CMDTYP(mask)) >> SDHC_CR_CMDTYP_Pos; |
| 1427 | return tmp; |
| 1428 | } |
| 1429 | |
| 1430 | static inline void hri_sdhc_write_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t data) |
| 1431 | { |
| 1432 | uint16_t tmp; |
| 1433 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1434 | tmp = ((Sdhc *)hw)->CR.reg; |
| 1435 | tmp &= ~SDHC_CR_CMDTYP_Msk; |
| 1436 | tmp |= SDHC_CR_CMDTYP(data); |
| 1437 | ((Sdhc *)hw)->CR.reg = tmp; |
| 1438 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1439 | } |
| 1440 | |
| 1441 | static inline void hri_sdhc_clear_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) |
| 1442 | { |
| 1443 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1444 | ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDTYP(mask); |
| 1445 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1446 | } |
| 1447 | |
| 1448 | static inline void hri_sdhc_toggle_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) |
| 1449 | { |
| 1450 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1451 | ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDTYP(mask); |
| 1452 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1453 | } |
| 1454 | |
| 1455 | static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_CMDTYP_bf(const void *const hw) |
| 1456 | { |
| 1457 | uint16_t tmp; |
| 1458 | tmp = ((Sdhc *)hw)->CR.reg; |
| 1459 | tmp = (tmp & SDHC_CR_CMDTYP_Msk) >> SDHC_CR_CMDTYP_Pos; |
| 1460 | return tmp; |
| 1461 | } |
| 1462 | |
| 1463 | static inline void hri_sdhc_set_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) |
| 1464 | { |
| 1465 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1466 | ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDIDX(mask); |
| 1467 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1468 | } |
| 1469 | |
| 1470 | static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) |
| 1471 | { |
| 1472 | uint16_t tmp; |
| 1473 | tmp = ((Sdhc *)hw)->CR.reg; |
| 1474 | tmp = (tmp & SDHC_CR_CMDIDX(mask)) >> SDHC_CR_CMDIDX_Pos; |
| 1475 | return tmp; |
| 1476 | } |
| 1477 | |
| 1478 | static inline void hri_sdhc_write_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t data) |
| 1479 | { |
| 1480 | uint16_t tmp; |
| 1481 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1482 | tmp = ((Sdhc *)hw)->CR.reg; |
| 1483 | tmp &= ~SDHC_CR_CMDIDX_Msk; |
| 1484 | tmp |= SDHC_CR_CMDIDX(data); |
| 1485 | ((Sdhc *)hw)->CR.reg = tmp; |
| 1486 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1487 | } |
| 1488 | |
| 1489 | static inline void hri_sdhc_clear_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) |
| 1490 | { |
| 1491 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1492 | ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDIDX(mask); |
| 1493 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1494 | } |
| 1495 | |
| 1496 | static inline void hri_sdhc_toggle_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) |
| 1497 | { |
| 1498 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1499 | ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDIDX(mask); |
| 1500 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1501 | } |
| 1502 | |
| 1503 | static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_CMDIDX_bf(const void *const hw) |
| 1504 | { |
| 1505 | uint16_t tmp; |
| 1506 | tmp = ((Sdhc *)hw)->CR.reg; |
| 1507 | tmp = (tmp & SDHC_CR_CMDIDX_Msk) >> SDHC_CR_CMDIDX_Pos; |
| 1508 | return tmp; |
| 1509 | } |
| 1510 | |
| 1511 | static inline void hri_sdhc_set_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) |
| 1512 | { |
| 1513 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1514 | ((Sdhc *)hw)->CR.reg |= mask; |
| 1515 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1516 | } |
| 1517 | |
| 1518 | static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) |
| 1519 | { |
| 1520 | uint16_t tmp; |
| 1521 | tmp = ((Sdhc *)hw)->CR.reg; |
| 1522 | tmp &= mask; |
| 1523 | return tmp; |
| 1524 | } |
| 1525 | |
| 1526 | static inline void hri_sdhc_write_CR_reg(const void *const hw, hri_sdhc_cr_reg_t data) |
| 1527 | { |
| 1528 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1529 | ((Sdhc *)hw)->CR.reg = data; |
| 1530 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1531 | } |
| 1532 | |
| 1533 | static inline void hri_sdhc_clear_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) |
| 1534 | { |
| 1535 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1536 | ((Sdhc *)hw)->CR.reg &= ~mask; |
| 1537 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1538 | } |
| 1539 | |
| 1540 | static inline void hri_sdhc_toggle_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) |
| 1541 | { |
| 1542 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1543 | ((Sdhc *)hw)->CR.reg ^= mask; |
| 1544 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1545 | } |
| 1546 | |
| 1547 | static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_reg(const void *const hw) |
| 1548 | { |
| 1549 | return ((Sdhc *)hw)->CR.reg; |
| 1550 | } |
| 1551 | |
| 1552 | static inline void hri_sdhc_set_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) |
| 1553 | { |
| 1554 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1555 | ((Sdhc *)hw)->BDPR.reg |= SDHC_BDPR_BUFDATA(mask); |
| 1556 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1557 | } |
| 1558 | |
| 1559 | static inline hri_sdhc_bdpr_reg_t hri_sdhc_get_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) |
| 1560 | { |
| 1561 | uint32_t tmp; |
| 1562 | tmp = ((Sdhc *)hw)->BDPR.reg; |
| 1563 | tmp = (tmp & SDHC_BDPR_BUFDATA(mask)) >> SDHC_BDPR_BUFDATA_Pos; |
| 1564 | return tmp; |
| 1565 | } |
| 1566 | |
| 1567 | static inline void hri_sdhc_write_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t data) |
| 1568 | { |
| 1569 | uint32_t tmp; |
| 1570 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1571 | tmp = ((Sdhc *)hw)->BDPR.reg; |
| 1572 | tmp &= ~SDHC_BDPR_BUFDATA_Msk; |
| 1573 | tmp |= SDHC_BDPR_BUFDATA(data); |
| 1574 | ((Sdhc *)hw)->BDPR.reg = tmp; |
| 1575 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1576 | } |
| 1577 | |
| 1578 | static inline void hri_sdhc_clear_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) |
| 1579 | { |
| 1580 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1581 | ((Sdhc *)hw)->BDPR.reg &= ~SDHC_BDPR_BUFDATA(mask); |
| 1582 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1583 | } |
| 1584 | |
| 1585 | static inline void hri_sdhc_toggle_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) |
| 1586 | { |
| 1587 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1588 | ((Sdhc *)hw)->BDPR.reg ^= SDHC_BDPR_BUFDATA(mask); |
| 1589 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1590 | } |
| 1591 | |
| 1592 | static inline hri_sdhc_bdpr_reg_t hri_sdhc_read_BDPR_BUFDATA_bf(const void *const hw) |
| 1593 | { |
| 1594 | uint32_t tmp; |
| 1595 | tmp = ((Sdhc *)hw)->BDPR.reg; |
| 1596 | tmp = (tmp & SDHC_BDPR_BUFDATA_Msk) >> SDHC_BDPR_BUFDATA_Pos; |
| 1597 | return tmp; |
| 1598 | } |
| 1599 | |
| 1600 | static inline void hri_sdhc_set_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) |
| 1601 | { |
| 1602 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1603 | ((Sdhc *)hw)->BDPR.reg |= mask; |
| 1604 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1605 | } |
| 1606 | |
| 1607 | static inline hri_sdhc_bdpr_reg_t hri_sdhc_get_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) |
| 1608 | { |
| 1609 | uint32_t tmp; |
| 1610 | tmp = ((Sdhc *)hw)->BDPR.reg; |
| 1611 | tmp &= mask; |
| 1612 | return tmp; |
| 1613 | } |
| 1614 | |
| 1615 | static inline void hri_sdhc_write_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t data) |
| 1616 | { |
| 1617 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1618 | ((Sdhc *)hw)->BDPR.reg = data; |
| 1619 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1620 | } |
| 1621 | |
| 1622 | static inline void hri_sdhc_clear_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) |
| 1623 | { |
| 1624 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1625 | ((Sdhc *)hw)->BDPR.reg &= ~mask; |
| 1626 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1627 | } |
| 1628 | |
| 1629 | static inline void hri_sdhc_toggle_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) |
| 1630 | { |
| 1631 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1632 | ((Sdhc *)hw)->BDPR.reg ^= mask; |
| 1633 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1634 | } |
| 1635 | |
| 1636 | static inline hri_sdhc_bdpr_reg_t hri_sdhc_read_BDPR_reg(const void *const hw) |
| 1637 | { |
| 1638 | return ((Sdhc *)hw)->BDPR.reg; |
| 1639 | } |
| 1640 | |
| 1641 | static inline void hri_sdhc_set_HC1R_LEDCTRL_bit(const void *const hw) |
| 1642 | { |
| 1643 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1644 | ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_LEDCTRL; |
| 1645 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1646 | } |
| 1647 | |
| 1648 | static inline bool hri_sdhc_get_HC1R_LEDCTRL_bit(const void *const hw) |
| 1649 | { |
| 1650 | uint8_t tmp; |
| 1651 | tmp = ((Sdhc *)hw)->HC1R.reg; |
| 1652 | tmp = (tmp & SDHC_HC1R_LEDCTRL) >> SDHC_HC1R_LEDCTRL_Pos; |
| 1653 | return (bool)tmp; |
| 1654 | } |
| 1655 | |
| 1656 | static inline void hri_sdhc_write_HC1R_LEDCTRL_bit(const void *const hw, bool value) |
| 1657 | { |
| 1658 | uint8_t tmp; |
| 1659 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1660 | tmp = ((Sdhc *)hw)->HC1R.reg; |
| 1661 | tmp &= ~SDHC_HC1R_LEDCTRL; |
| 1662 | tmp |= value << SDHC_HC1R_LEDCTRL_Pos; |
| 1663 | ((Sdhc *)hw)->HC1R.reg = tmp; |
| 1664 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1665 | } |
| 1666 | |
| 1667 | static inline void hri_sdhc_clear_HC1R_LEDCTRL_bit(const void *const hw) |
| 1668 | { |
| 1669 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1670 | ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_LEDCTRL; |
| 1671 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1672 | } |
| 1673 | |
| 1674 | static inline void hri_sdhc_toggle_HC1R_LEDCTRL_bit(const void *const hw) |
| 1675 | { |
| 1676 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1677 | ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_LEDCTRL; |
| 1678 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1679 | } |
| 1680 | |
| 1681 | static inline void hri_sdhc_set_HC1R_DW_bit(const void *const hw) |
| 1682 | { |
| 1683 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1684 | ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_DW; |
| 1685 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1686 | } |
| 1687 | |
| 1688 | static inline bool hri_sdhc_get_HC1R_DW_bit(const void *const hw) |
| 1689 | { |
| 1690 | uint8_t tmp; |
| 1691 | tmp = ((Sdhc *)hw)->HC1R.reg; |
| 1692 | tmp = (tmp & SDHC_HC1R_DW) >> SDHC_HC1R_DW_Pos; |
| 1693 | return (bool)tmp; |
| 1694 | } |
| 1695 | |
| 1696 | static inline void hri_sdhc_write_HC1R_DW_bit(const void *const hw, bool value) |
| 1697 | { |
| 1698 | uint8_t tmp; |
| 1699 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1700 | tmp = ((Sdhc *)hw)->HC1R.reg; |
| 1701 | tmp &= ~SDHC_HC1R_DW; |
| 1702 | tmp |= value << SDHC_HC1R_DW_Pos; |
| 1703 | ((Sdhc *)hw)->HC1R.reg = tmp; |
| 1704 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1705 | } |
| 1706 | |
| 1707 | static inline void hri_sdhc_clear_HC1R_DW_bit(const void *const hw) |
| 1708 | { |
| 1709 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1710 | ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_DW; |
| 1711 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1712 | } |
| 1713 | |
| 1714 | static inline void hri_sdhc_toggle_HC1R_DW_bit(const void *const hw) |
| 1715 | { |
| 1716 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1717 | ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_DW; |
| 1718 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1719 | } |
| 1720 | |
| 1721 | static inline void hri_sdhc_set_HC1R_HSEN_bit(const void *const hw) |
| 1722 | { |
| 1723 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1724 | ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_HSEN; |
| 1725 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1726 | } |
| 1727 | |
| 1728 | static inline bool hri_sdhc_get_HC1R_HSEN_bit(const void *const hw) |
| 1729 | { |
| 1730 | uint8_t tmp; |
| 1731 | tmp = ((Sdhc *)hw)->HC1R.reg; |
| 1732 | tmp = (tmp & SDHC_HC1R_HSEN) >> SDHC_HC1R_HSEN_Pos; |
| 1733 | return (bool)tmp; |
| 1734 | } |
| 1735 | |
| 1736 | static inline void hri_sdhc_write_HC1R_HSEN_bit(const void *const hw, bool value) |
| 1737 | { |
| 1738 | uint8_t tmp; |
| 1739 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1740 | tmp = ((Sdhc *)hw)->HC1R.reg; |
| 1741 | tmp &= ~SDHC_HC1R_HSEN; |
| 1742 | tmp |= value << SDHC_HC1R_HSEN_Pos; |
| 1743 | ((Sdhc *)hw)->HC1R.reg = tmp; |
| 1744 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1745 | } |
| 1746 | |
| 1747 | static inline void hri_sdhc_clear_HC1R_HSEN_bit(const void *const hw) |
| 1748 | { |
| 1749 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1750 | ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_HSEN; |
| 1751 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1752 | } |
| 1753 | |
| 1754 | static inline void hri_sdhc_toggle_HC1R_HSEN_bit(const void *const hw) |
| 1755 | { |
| 1756 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1757 | ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_HSEN; |
| 1758 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1759 | } |
| 1760 | |
| 1761 | static inline void hri_sdhc_set_HC1R_CARDDTL_bit(const void *const hw) |
| 1762 | { |
| 1763 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1764 | ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_CARDDTL; |
| 1765 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1766 | } |
| 1767 | |
| 1768 | static inline bool hri_sdhc_get_HC1R_CARDDTL_bit(const void *const hw) |
| 1769 | { |
| 1770 | uint8_t tmp; |
| 1771 | tmp = ((Sdhc *)hw)->HC1R.reg; |
| 1772 | tmp = (tmp & SDHC_HC1R_CARDDTL) >> SDHC_HC1R_CARDDTL_Pos; |
| 1773 | return (bool)tmp; |
| 1774 | } |
| 1775 | |
| 1776 | static inline void hri_sdhc_write_HC1R_CARDDTL_bit(const void *const hw, bool value) |
| 1777 | { |
| 1778 | uint8_t tmp; |
| 1779 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1780 | tmp = ((Sdhc *)hw)->HC1R.reg; |
| 1781 | tmp &= ~SDHC_HC1R_CARDDTL; |
| 1782 | tmp |= value << SDHC_HC1R_CARDDTL_Pos; |
| 1783 | ((Sdhc *)hw)->HC1R.reg = tmp; |
| 1784 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1785 | } |
| 1786 | |
| 1787 | static inline void hri_sdhc_clear_HC1R_CARDDTL_bit(const void *const hw) |
| 1788 | { |
| 1789 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1790 | ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_CARDDTL; |
| 1791 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1792 | } |
| 1793 | |
| 1794 | static inline void hri_sdhc_toggle_HC1R_CARDDTL_bit(const void *const hw) |
| 1795 | { |
| 1796 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1797 | ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_CARDDTL; |
| 1798 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1799 | } |
| 1800 | |
| 1801 | static inline void hri_sdhc_set_HC1R_CARDDSEL_bit(const void *const hw) |
| 1802 | { |
| 1803 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1804 | ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_CARDDSEL; |
| 1805 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1806 | } |
| 1807 | |
| 1808 | static inline bool hri_sdhc_get_HC1R_CARDDSEL_bit(const void *const hw) |
| 1809 | { |
| 1810 | uint8_t tmp; |
| 1811 | tmp = ((Sdhc *)hw)->HC1R.reg; |
| 1812 | tmp = (tmp & SDHC_HC1R_CARDDSEL) >> SDHC_HC1R_CARDDSEL_Pos; |
| 1813 | return (bool)tmp; |
| 1814 | } |
| 1815 | |
| 1816 | static inline void hri_sdhc_write_HC1R_CARDDSEL_bit(const void *const hw, bool value) |
| 1817 | { |
| 1818 | uint8_t tmp; |
| 1819 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1820 | tmp = ((Sdhc *)hw)->HC1R.reg; |
| 1821 | tmp &= ~SDHC_HC1R_CARDDSEL; |
| 1822 | tmp |= value << SDHC_HC1R_CARDDSEL_Pos; |
| 1823 | ((Sdhc *)hw)->HC1R.reg = tmp; |
| 1824 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1825 | } |
| 1826 | |
| 1827 | static inline void hri_sdhc_clear_HC1R_CARDDSEL_bit(const void *const hw) |
| 1828 | { |
| 1829 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1830 | ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_CARDDSEL; |
| 1831 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1832 | } |
| 1833 | |
| 1834 | static inline void hri_sdhc_toggle_HC1R_CARDDSEL_bit(const void *const hw) |
| 1835 | { |
| 1836 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1837 | ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_CARDDSEL; |
| 1838 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1839 | } |
| 1840 | |
| 1841 | static inline void hri_sdhc_set_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) |
| 1842 | { |
| 1843 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1844 | ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_DMASEL(mask); |
| 1845 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1846 | } |
| 1847 | |
| 1848 | static inline hri_sdhc_hc1r_reg_t hri_sdhc_get_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) |
| 1849 | { |
| 1850 | uint8_t tmp; |
| 1851 | tmp = ((Sdhc *)hw)->HC1R.reg; |
| 1852 | tmp = (tmp & SDHC_HC1R_DMASEL(mask)) >> SDHC_HC1R_DMASEL_Pos; |
| 1853 | return tmp; |
| 1854 | } |
| 1855 | |
| 1856 | static inline void hri_sdhc_write_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t data) |
| 1857 | { |
| 1858 | uint8_t tmp; |
| 1859 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1860 | tmp = ((Sdhc *)hw)->HC1R.reg; |
| 1861 | tmp &= ~SDHC_HC1R_DMASEL_Msk; |
| 1862 | tmp |= SDHC_HC1R_DMASEL(data); |
| 1863 | ((Sdhc *)hw)->HC1R.reg = tmp; |
| 1864 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1865 | } |
| 1866 | |
| 1867 | static inline void hri_sdhc_clear_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) |
| 1868 | { |
| 1869 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1870 | ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_DMASEL(mask); |
| 1871 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1872 | } |
| 1873 | |
| 1874 | static inline void hri_sdhc_toggle_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) |
| 1875 | { |
| 1876 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1877 | ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_DMASEL(mask); |
| 1878 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1879 | } |
| 1880 | |
| 1881 | static inline hri_sdhc_hc1r_reg_t hri_sdhc_read_HC1R_DMASEL_bf(const void *const hw) |
| 1882 | { |
| 1883 | uint8_t tmp; |
| 1884 | tmp = ((Sdhc *)hw)->HC1R.reg; |
| 1885 | tmp = (tmp & SDHC_HC1R_DMASEL_Msk) >> SDHC_HC1R_DMASEL_Pos; |
| 1886 | return tmp; |
| 1887 | } |
| 1888 | |
| 1889 | static inline void hri_sdhc_set_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) |
| 1890 | { |
| 1891 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1892 | ((Sdhc *)hw)->HC1R.reg |= mask; |
| 1893 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1894 | } |
| 1895 | |
| 1896 | static inline hri_sdhc_hc1r_reg_t hri_sdhc_get_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) |
| 1897 | { |
| 1898 | uint8_t tmp; |
| 1899 | tmp = ((Sdhc *)hw)->HC1R.reg; |
| 1900 | tmp &= mask; |
| 1901 | return tmp; |
| 1902 | } |
| 1903 | |
| 1904 | static inline void hri_sdhc_write_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t data) |
| 1905 | { |
| 1906 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1907 | ((Sdhc *)hw)->HC1R.reg = data; |
| 1908 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1909 | } |
| 1910 | |
| 1911 | static inline void hri_sdhc_clear_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) |
| 1912 | { |
| 1913 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1914 | ((Sdhc *)hw)->HC1R.reg &= ~mask; |
| 1915 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1916 | } |
| 1917 | |
| 1918 | static inline void hri_sdhc_toggle_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) |
| 1919 | { |
| 1920 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1921 | ((Sdhc *)hw)->HC1R.reg ^= mask; |
| 1922 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1923 | } |
| 1924 | |
| 1925 | static inline hri_sdhc_hc1r_reg_t hri_sdhc_read_HC1R_reg(const void *const hw) |
| 1926 | { |
| 1927 | return ((Sdhc *)hw)->HC1R.reg; |
| 1928 | } |
| 1929 | |
| 1930 | static inline void hri_sdhc_set_PCR_SDBPWR_bit(const void *const hw) |
| 1931 | { |
| 1932 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1933 | ((Sdhc *)hw)->PCR.reg |= SDHC_PCR_SDBPWR; |
| 1934 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1935 | } |
| 1936 | |
| 1937 | static inline bool hri_sdhc_get_PCR_SDBPWR_bit(const void *const hw) |
| 1938 | { |
| 1939 | uint8_t tmp; |
| 1940 | tmp = ((Sdhc *)hw)->PCR.reg; |
| 1941 | tmp = (tmp & SDHC_PCR_SDBPWR) >> SDHC_PCR_SDBPWR_Pos; |
| 1942 | return (bool)tmp; |
| 1943 | } |
| 1944 | |
| 1945 | static inline void hri_sdhc_write_PCR_SDBPWR_bit(const void *const hw, bool value) |
| 1946 | { |
| 1947 | uint8_t tmp; |
| 1948 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1949 | tmp = ((Sdhc *)hw)->PCR.reg; |
| 1950 | tmp &= ~SDHC_PCR_SDBPWR; |
| 1951 | tmp |= value << SDHC_PCR_SDBPWR_Pos; |
| 1952 | ((Sdhc *)hw)->PCR.reg = tmp; |
| 1953 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1954 | } |
| 1955 | |
| 1956 | static inline void hri_sdhc_clear_PCR_SDBPWR_bit(const void *const hw) |
| 1957 | { |
| 1958 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1959 | ((Sdhc *)hw)->PCR.reg &= ~SDHC_PCR_SDBPWR; |
| 1960 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1961 | } |
| 1962 | |
| 1963 | static inline void hri_sdhc_toggle_PCR_SDBPWR_bit(const void *const hw) |
| 1964 | { |
| 1965 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1966 | ((Sdhc *)hw)->PCR.reg ^= SDHC_PCR_SDBPWR; |
| 1967 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1968 | } |
| 1969 | |
| 1970 | static inline void hri_sdhc_set_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) |
| 1971 | { |
| 1972 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1973 | ((Sdhc *)hw)->PCR.reg |= SDHC_PCR_SDBVSEL(mask); |
| 1974 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1975 | } |
| 1976 | |
| 1977 | static inline hri_sdhc_pcr_reg_t hri_sdhc_get_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) |
| 1978 | { |
| 1979 | uint8_t tmp; |
| 1980 | tmp = ((Sdhc *)hw)->PCR.reg; |
| 1981 | tmp = (tmp & SDHC_PCR_SDBVSEL(mask)) >> SDHC_PCR_SDBVSEL_Pos; |
| 1982 | return tmp; |
| 1983 | } |
| 1984 | |
| 1985 | static inline void hri_sdhc_write_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t data) |
| 1986 | { |
| 1987 | uint8_t tmp; |
| 1988 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1989 | tmp = ((Sdhc *)hw)->PCR.reg; |
| 1990 | tmp &= ~SDHC_PCR_SDBVSEL_Msk; |
| 1991 | tmp |= SDHC_PCR_SDBVSEL(data); |
| 1992 | ((Sdhc *)hw)->PCR.reg = tmp; |
| 1993 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 1994 | } |
| 1995 | |
| 1996 | static inline void hri_sdhc_clear_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) |
| 1997 | { |
| 1998 | SDHC_CRITICAL_SECTION_ENTER(); |
| 1999 | ((Sdhc *)hw)->PCR.reg &= ~SDHC_PCR_SDBVSEL(mask); |
| 2000 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2001 | } |
| 2002 | |
| 2003 | static inline void hri_sdhc_toggle_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) |
| 2004 | { |
| 2005 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2006 | ((Sdhc *)hw)->PCR.reg ^= SDHC_PCR_SDBVSEL(mask); |
| 2007 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2008 | } |
| 2009 | |
| 2010 | static inline hri_sdhc_pcr_reg_t hri_sdhc_read_PCR_SDBVSEL_bf(const void *const hw) |
| 2011 | { |
| 2012 | uint8_t tmp; |
| 2013 | tmp = ((Sdhc *)hw)->PCR.reg; |
| 2014 | tmp = (tmp & SDHC_PCR_SDBVSEL_Msk) >> SDHC_PCR_SDBVSEL_Pos; |
| 2015 | return tmp; |
| 2016 | } |
| 2017 | |
| 2018 | static inline void hri_sdhc_set_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) |
| 2019 | { |
| 2020 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2021 | ((Sdhc *)hw)->PCR.reg |= mask; |
| 2022 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2023 | } |
| 2024 | |
| 2025 | static inline hri_sdhc_pcr_reg_t hri_sdhc_get_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) |
| 2026 | { |
| 2027 | uint8_t tmp; |
| 2028 | tmp = ((Sdhc *)hw)->PCR.reg; |
| 2029 | tmp &= mask; |
| 2030 | return tmp; |
| 2031 | } |
| 2032 | |
| 2033 | static inline void hri_sdhc_write_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t data) |
| 2034 | { |
| 2035 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2036 | ((Sdhc *)hw)->PCR.reg = data; |
| 2037 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2038 | } |
| 2039 | |
| 2040 | static inline void hri_sdhc_clear_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) |
| 2041 | { |
| 2042 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2043 | ((Sdhc *)hw)->PCR.reg &= ~mask; |
| 2044 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2045 | } |
| 2046 | |
| 2047 | static inline void hri_sdhc_toggle_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) |
| 2048 | { |
| 2049 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2050 | ((Sdhc *)hw)->PCR.reg ^= mask; |
| 2051 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2052 | } |
| 2053 | |
| 2054 | static inline hri_sdhc_pcr_reg_t hri_sdhc_read_PCR_reg(const void *const hw) |
| 2055 | { |
| 2056 | return ((Sdhc *)hw)->PCR.reg; |
| 2057 | } |
| 2058 | |
| 2059 | static inline void hri_sdhc_set_BGCR_STPBGR_bit(const void *const hw) |
| 2060 | { |
| 2061 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2062 | ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_STPBGR; |
| 2063 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2064 | } |
| 2065 | |
| 2066 | static inline bool hri_sdhc_get_BGCR_STPBGR_bit(const void *const hw) |
| 2067 | { |
| 2068 | uint8_t tmp; |
| 2069 | tmp = ((Sdhc *)hw)->BGCR.reg; |
| 2070 | tmp = (tmp & SDHC_BGCR_STPBGR) >> SDHC_BGCR_STPBGR_Pos; |
| 2071 | return (bool)tmp; |
| 2072 | } |
| 2073 | |
| 2074 | static inline void hri_sdhc_write_BGCR_STPBGR_bit(const void *const hw, bool value) |
| 2075 | { |
| 2076 | uint8_t tmp; |
| 2077 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2078 | tmp = ((Sdhc *)hw)->BGCR.reg; |
| 2079 | tmp &= ~SDHC_BGCR_STPBGR; |
| 2080 | tmp |= value << SDHC_BGCR_STPBGR_Pos; |
| 2081 | ((Sdhc *)hw)->BGCR.reg = tmp; |
| 2082 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2083 | } |
| 2084 | |
| 2085 | static inline void hri_sdhc_clear_BGCR_STPBGR_bit(const void *const hw) |
| 2086 | { |
| 2087 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2088 | ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_STPBGR; |
| 2089 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2090 | } |
| 2091 | |
| 2092 | static inline void hri_sdhc_toggle_BGCR_STPBGR_bit(const void *const hw) |
| 2093 | { |
| 2094 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2095 | ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_STPBGR; |
| 2096 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2097 | } |
| 2098 | |
| 2099 | static inline void hri_sdhc_set_BGCR_CONTR_bit(const void *const hw) |
| 2100 | { |
| 2101 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2102 | ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_CONTR; |
| 2103 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2104 | } |
| 2105 | |
| 2106 | static inline bool hri_sdhc_get_BGCR_CONTR_bit(const void *const hw) |
| 2107 | { |
| 2108 | uint8_t tmp; |
| 2109 | tmp = ((Sdhc *)hw)->BGCR.reg; |
| 2110 | tmp = (tmp & SDHC_BGCR_CONTR) >> SDHC_BGCR_CONTR_Pos; |
| 2111 | return (bool)tmp; |
| 2112 | } |
| 2113 | |
| 2114 | static inline void hri_sdhc_write_BGCR_CONTR_bit(const void *const hw, bool value) |
| 2115 | { |
| 2116 | uint8_t tmp; |
| 2117 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2118 | tmp = ((Sdhc *)hw)->BGCR.reg; |
| 2119 | tmp &= ~SDHC_BGCR_CONTR; |
| 2120 | tmp |= value << SDHC_BGCR_CONTR_Pos; |
| 2121 | ((Sdhc *)hw)->BGCR.reg = tmp; |
| 2122 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2123 | } |
| 2124 | |
| 2125 | static inline void hri_sdhc_clear_BGCR_CONTR_bit(const void *const hw) |
| 2126 | { |
| 2127 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2128 | ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_CONTR; |
| 2129 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2130 | } |
| 2131 | |
| 2132 | static inline void hri_sdhc_toggle_BGCR_CONTR_bit(const void *const hw) |
| 2133 | { |
| 2134 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2135 | ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_CONTR; |
| 2136 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2137 | } |
| 2138 | |
| 2139 | static inline void hri_sdhc_set_BGCR_RWCTRL_bit(const void *const hw) |
| 2140 | { |
| 2141 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2142 | ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_RWCTRL; |
| 2143 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2144 | } |
| 2145 | |
| 2146 | static inline bool hri_sdhc_get_BGCR_RWCTRL_bit(const void *const hw) |
| 2147 | { |
| 2148 | uint8_t tmp; |
| 2149 | tmp = ((Sdhc *)hw)->BGCR.reg; |
| 2150 | tmp = (tmp & SDHC_BGCR_RWCTRL) >> SDHC_BGCR_RWCTRL_Pos; |
| 2151 | return (bool)tmp; |
| 2152 | } |
| 2153 | |
| 2154 | static inline void hri_sdhc_write_BGCR_RWCTRL_bit(const void *const hw, bool value) |
| 2155 | { |
| 2156 | uint8_t tmp; |
| 2157 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2158 | tmp = ((Sdhc *)hw)->BGCR.reg; |
| 2159 | tmp &= ~SDHC_BGCR_RWCTRL; |
| 2160 | tmp |= value << SDHC_BGCR_RWCTRL_Pos; |
| 2161 | ((Sdhc *)hw)->BGCR.reg = tmp; |
| 2162 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2163 | } |
| 2164 | |
| 2165 | static inline void hri_sdhc_clear_BGCR_RWCTRL_bit(const void *const hw) |
| 2166 | { |
| 2167 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2168 | ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_RWCTRL; |
| 2169 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2170 | } |
| 2171 | |
| 2172 | static inline void hri_sdhc_toggle_BGCR_RWCTRL_bit(const void *const hw) |
| 2173 | { |
| 2174 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2175 | ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_RWCTRL; |
| 2176 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2177 | } |
| 2178 | |
| 2179 | static inline void hri_sdhc_set_BGCR_INTBG_bit(const void *const hw) |
| 2180 | { |
| 2181 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2182 | ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_INTBG; |
| 2183 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2184 | } |
| 2185 | |
| 2186 | static inline bool hri_sdhc_get_BGCR_INTBG_bit(const void *const hw) |
| 2187 | { |
| 2188 | uint8_t tmp; |
| 2189 | tmp = ((Sdhc *)hw)->BGCR.reg; |
| 2190 | tmp = (tmp & SDHC_BGCR_INTBG) >> SDHC_BGCR_INTBG_Pos; |
| 2191 | return (bool)tmp; |
| 2192 | } |
| 2193 | |
| 2194 | static inline void hri_sdhc_write_BGCR_INTBG_bit(const void *const hw, bool value) |
| 2195 | { |
| 2196 | uint8_t tmp; |
| 2197 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2198 | tmp = ((Sdhc *)hw)->BGCR.reg; |
| 2199 | tmp &= ~SDHC_BGCR_INTBG; |
| 2200 | tmp |= value << SDHC_BGCR_INTBG_Pos; |
| 2201 | ((Sdhc *)hw)->BGCR.reg = tmp; |
| 2202 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2203 | } |
| 2204 | |
| 2205 | static inline void hri_sdhc_clear_BGCR_INTBG_bit(const void *const hw) |
| 2206 | { |
| 2207 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2208 | ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_INTBG; |
| 2209 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2210 | } |
| 2211 | |
| 2212 | static inline void hri_sdhc_toggle_BGCR_INTBG_bit(const void *const hw) |
| 2213 | { |
| 2214 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2215 | ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_INTBG; |
| 2216 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2217 | } |
| 2218 | |
| 2219 | static inline void hri_sdhc_set_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) |
| 2220 | { |
| 2221 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2222 | ((Sdhc *)hw)->BGCR.reg |= mask; |
| 2223 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2224 | } |
| 2225 | |
| 2226 | static inline hri_sdhc_bgcr_reg_t hri_sdhc_get_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) |
| 2227 | { |
| 2228 | uint8_t tmp; |
| 2229 | tmp = ((Sdhc *)hw)->BGCR.reg; |
| 2230 | tmp &= mask; |
| 2231 | return tmp; |
| 2232 | } |
| 2233 | |
| 2234 | static inline void hri_sdhc_write_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t data) |
| 2235 | { |
| 2236 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2237 | ((Sdhc *)hw)->BGCR.reg = data; |
| 2238 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2239 | } |
| 2240 | |
| 2241 | static inline void hri_sdhc_clear_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) |
| 2242 | { |
| 2243 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2244 | ((Sdhc *)hw)->BGCR.reg &= ~mask; |
| 2245 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2246 | } |
| 2247 | |
| 2248 | static inline void hri_sdhc_toggle_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) |
| 2249 | { |
| 2250 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2251 | ((Sdhc *)hw)->BGCR.reg ^= mask; |
| 2252 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2253 | } |
| 2254 | |
| 2255 | static inline hri_sdhc_bgcr_reg_t hri_sdhc_read_BGCR_reg(const void *const hw) |
| 2256 | { |
| 2257 | return ((Sdhc *)hw)->BGCR.reg; |
| 2258 | } |
| 2259 | |
| 2260 | static inline void hri_sdhc_set_WCR_WKENCINT_bit(const void *const hw) |
| 2261 | { |
| 2262 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2263 | ((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCINT; |
| 2264 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2265 | } |
| 2266 | |
| 2267 | static inline bool hri_sdhc_get_WCR_WKENCINT_bit(const void *const hw) |
| 2268 | { |
| 2269 | uint8_t tmp; |
| 2270 | tmp = ((Sdhc *)hw)->WCR.reg; |
| 2271 | tmp = (tmp & SDHC_WCR_WKENCINT) >> SDHC_WCR_WKENCINT_Pos; |
| 2272 | return (bool)tmp; |
| 2273 | } |
| 2274 | |
| 2275 | static inline void hri_sdhc_write_WCR_WKENCINT_bit(const void *const hw, bool value) |
| 2276 | { |
| 2277 | uint8_t tmp; |
| 2278 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2279 | tmp = ((Sdhc *)hw)->WCR.reg; |
| 2280 | tmp &= ~SDHC_WCR_WKENCINT; |
| 2281 | tmp |= value << SDHC_WCR_WKENCINT_Pos; |
| 2282 | ((Sdhc *)hw)->WCR.reg = tmp; |
| 2283 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2284 | } |
| 2285 | |
| 2286 | static inline void hri_sdhc_clear_WCR_WKENCINT_bit(const void *const hw) |
| 2287 | { |
| 2288 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2289 | ((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCINT; |
| 2290 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2291 | } |
| 2292 | |
| 2293 | static inline void hri_sdhc_toggle_WCR_WKENCINT_bit(const void *const hw) |
| 2294 | { |
| 2295 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2296 | ((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCINT; |
| 2297 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2298 | } |
| 2299 | |
| 2300 | static inline void hri_sdhc_set_WCR_WKENCINS_bit(const void *const hw) |
| 2301 | { |
| 2302 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2303 | ((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCINS; |
| 2304 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2305 | } |
| 2306 | |
| 2307 | static inline bool hri_sdhc_get_WCR_WKENCINS_bit(const void *const hw) |
| 2308 | { |
| 2309 | uint8_t tmp; |
| 2310 | tmp = ((Sdhc *)hw)->WCR.reg; |
| 2311 | tmp = (tmp & SDHC_WCR_WKENCINS) >> SDHC_WCR_WKENCINS_Pos; |
| 2312 | return (bool)tmp; |
| 2313 | } |
| 2314 | |
| 2315 | static inline void hri_sdhc_write_WCR_WKENCINS_bit(const void *const hw, bool value) |
| 2316 | { |
| 2317 | uint8_t tmp; |
| 2318 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2319 | tmp = ((Sdhc *)hw)->WCR.reg; |
| 2320 | tmp &= ~SDHC_WCR_WKENCINS; |
| 2321 | tmp |= value << SDHC_WCR_WKENCINS_Pos; |
| 2322 | ((Sdhc *)hw)->WCR.reg = tmp; |
| 2323 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2324 | } |
| 2325 | |
| 2326 | static inline void hri_sdhc_clear_WCR_WKENCINS_bit(const void *const hw) |
| 2327 | { |
| 2328 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2329 | ((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCINS; |
| 2330 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2331 | } |
| 2332 | |
| 2333 | static inline void hri_sdhc_toggle_WCR_WKENCINS_bit(const void *const hw) |
| 2334 | { |
| 2335 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2336 | ((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCINS; |
| 2337 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2338 | } |
| 2339 | |
| 2340 | static inline void hri_sdhc_set_WCR_WKENCREM_bit(const void *const hw) |
| 2341 | { |
| 2342 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2343 | ((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCREM; |
| 2344 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2345 | } |
| 2346 | |
| 2347 | static inline bool hri_sdhc_get_WCR_WKENCREM_bit(const void *const hw) |
| 2348 | { |
| 2349 | uint8_t tmp; |
| 2350 | tmp = ((Sdhc *)hw)->WCR.reg; |
| 2351 | tmp = (tmp & SDHC_WCR_WKENCREM) >> SDHC_WCR_WKENCREM_Pos; |
| 2352 | return (bool)tmp; |
| 2353 | } |
| 2354 | |
| 2355 | static inline void hri_sdhc_write_WCR_WKENCREM_bit(const void *const hw, bool value) |
| 2356 | { |
| 2357 | uint8_t tmp; |
| 2358 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2359 | tmp = ((Sdhc *)hw)->WCR.reg; |
| 2360 | tmp &= ~SDHC_WCR_WKENCREM; |
| 2361 | tmp |= value << SDHC_WCR_WKENCREM_Pos; |
| 2362 | ((Sdhc *)hw)->WCR.reg = tmp; |
| 2363 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2364 | } |
| 2365 | |
| 2366 | static inline void hri_sdhc_clear_WCR_WKENCREM_bit(const void *const hw) |
| 2367 | { |
| 2368 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2369 | ((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCREM; |
| 2370 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2371 | } |
| 2372 | |
| 2373 | static inline void hri_sdhc_toggle_WCR_WKENCREM_bit(const void *const hw) |
| 2374 | { |
| 2375 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2376 | ((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCREM; |
| 2377 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2378 | } |
| 2379 | |
| 2380 | static inline void hri_sdhc_set_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) |
| 2381 | { |
| 2382 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2383 | ((Sdhc *)hw)->WCR.reg |= mask; |
| 2384 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2385 | } |
| 2386 | |
| 2387 | static inline hri_sdhc_wcr_reg_t hri_sdhc_get_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) |
| 2388 | { |
| 2389 | uint8_t tmp; |
| 2390 | tmp = ((Sdhc *)hw)->WCR.reg; |
| 2391 | tmp &= mask; |
| 2392 | return tmp; |
| 2393 | } |
| 2394 | |
| 2395 | static inline void hri_sdhc_write_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t data) |
| 2396 | { |
| 2397 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2398 | ((Sdhc *)hw)->WCR.reg = data; |
| 2399 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2400 | } |
| 2401 | |
| 2402 | static inline void hri_sdhc_clear_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) |
| 2403 | { |
| 2404 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2405 | ((Sdhc *)hw)->WCR.reg &= ~mask; |
| 2406 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2407 | } |
| 2408 | |
| 2409 | static inline void hri_sdhc_toggle_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) |
| 2410 | { |
| 2411 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2412 | ((Sdhc *)hw)->WCR.reg ^= mask; |
| 2413 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2414 | } |
| 2415 | |
| 2416 | static inline hri_sdhc_wcr_reg_t hri_sdhc_read_WCR_reg(const void *const hw) |
| 2417 | { |
| 2418 | return ((Sdhc *)hw)->WCR.reg; |
| 2419 | } |
| 2420 | |
| 2421 | static inline void hri_sdhc_set_CCR_INTCLKEN_bit(const void *const hw) |
| 2422 | { |
| 2423 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2424 | ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_INTCLKEN; |
| 2425 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2426 | } |
| 2427 | |
| 2428 | static inline bool hri_sdhc_get_CCR_INTCLKEN_bit(const void *const hw) |
| 2429 | { |
| 2430 | uint16_t tmp; |
| 2431 | tmp = ((Sdhc *)hw)->CCR.reg; |
| 2432 | tmp = (tmp & SDHC_CCR_INTCLKEN) >> SDHC_CCR_INTCLKEN_Pos; |
| 2433 | return (bool)tmp; |
| 2434 | } |
| 2435 | |
| 2436 | static inline void hri_sdhc_write_CCR_INTCLKEN_bit(const void *const hw, bool value) |
| 2437 | { |
| 2438 | uint16_t tmp; |
| 2439 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2440 | tmp = ((Sdhc *)hw)->CCR.reg; |
| 2441 | tmp &= ~SDHC_CCR_INTCLKEN; |
| 2442 | tmp |= value << SDHC_CCR_INTCLKEN_Pos; |
| 2443 | ((Sdhc *)hw)->CCR.reg = tmp; |
| 2444 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2445 | } |
| 2446 | |
| 2447 | static inline void hri_sdhc_clear_CCR_INTCLKEN_bit(const void *const hw) |
| 2448 | { |
| 2449 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2450 | ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_INTCLKEN; |
| 2451 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2452 | } |
| 2453 | |
| 2454 | static inline void hri_sdhc_toggle_CCR_INTCLKEN_bit(const void *const hw) |
| 2455 | { |
| 2456 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2457 | ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_INTCLKEN; |
| 2458 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2459 | } |
| 2460 | |
| 2461 | static inline void hri_sdhc_set_CCR_INTCLKS_bit(const void *const hw) |
| 2462 | { |
| 2463 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2464 | ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_INTCLKS; |
| 2465 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2466 | } |
| 2467 | |
| 2468 | static inline bool hri_sdhc_get_CCR_INTCLKS_bit(const void *const hw) |
| 2469 | { |
| 2470 | uint16_t tmp; |
| 2471 | tmp = ((Sdhc *)hw)->CCR.reg; |
| 2472 | tmp = (tmp & SDHC_CCR_INTCLKS) >> SDHC_CCR_INTCLKS_Pos; |
| 2473 | return (bool)tmp; |
| 2474 | } |
| 2475 | |
| 2476 | static inline void hri_sdhc_write_CCR_INTCLKS_bit(const void *const hw, bool value) |
| 2477 | { |
| 2478 | uint16_t tmp; |
| 2479 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2480 | tmp = ((Sdhc *)hw)->CCR.reg; |
| 2481 | tmp &= ~SDHC_CCR_INTCLKS; |
| 2482 | tmp |= value << SDHC_CCR_INTCLKS_Pos; |
| 2483 | ((Sdhc *)hw)->CCR.reg = tmp; |
| 2484 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2485 | } |
| 2486 | |
| 2487 | static inline void hri_sdhc_clear_CCR_INTCLKS_bit(const void *const hw) |
| 2488 | { |
| 2489 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2490 | ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_INTCLKS; |
| 2491 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2492 | } |
| 2493 | |
| 2494 | static inline void hri_sdhc_toggle_CCR_INTCLKS_bit(const void *const hw) |
| 2495 | { |
| 2496 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2497 | ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_INTCLKS; |
| 2498 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2499 | } |
| 2500 | |
| 2501 | static inline void hri_sdhc_set_CCR_SDCLKEN_bit(const void *const hw) |
| 2502 | { |
| 2503 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2504 | ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_SDCLKEN; |
| 2505 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2506 | } |
| 2507 | |
| 2508 | static inline bool hri_sdhc_get_CCR_SDCLKEN_bit(const void *const hw) |
| 2509 | { |
| 2510 | uint16_t tmp; |
| 2511 | tmp = ((Sdhc *)hw)->CCR.reg; |
| 2512 | tmp = (tmp & SDHC_CCR_SDCLKEN) >> SDHC_CCR_SDCLKEN_Pos; |
| 2513 | return (bool)tmp; |
| 2514 | } |
| 2515 | |
| 2516 | static inline void hri_sdhc_write_CCR_SDCLKEN_bit(const void *const hw, bool value) |
| 2517 | { |
| 2518 | uint16_t tmp; |
| 2519 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2520 | tmp = ((Sdhc *)hw)->CCR.reg; |
| 2521 | tmp &= ~SDHC_CCR_SDCLKEN; |
| 2522 | tmp |= value << SDHC_CCR_SDCLKEN_Pos; |
| 2523 | ((Sdhc *)hw)->CCR.reg = tmp; |
| 2524 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2525 | } |
| 2526 | |
| 2527 | static inline void hri_sdhc_clear_CCR_SDCLKEN_bit(const void *const hw) |
| 2528 | { |
| 2529 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2530 | ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_SDCLKEN; |
| 2531 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2532 | } |
| 2533 | |
| 2534 | static inline void hri_sdhc_toggle_CCR_SDCLKEN_bit(const void *const hw) |
| 2535 | { |
| 2536 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2537 | ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_SDCLKEN; |
| 2538 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2539 | } |
| 2540 | |
| 2541 | static inline void hri_sdhc_set_CCR_CLKGSEL_bit(const void *const hw) |
| 2542 | { |
| 2543 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2544 | ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_CLKGSEL; |
| 2545 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2546 | } |
| 2547 | |
| 2548 | static inline bool hri_sdhc_get_CCR_CLKGSEL_bit(const void *const hw) |
| 2549 | { |
| 2550 | uint16_t tmp; |
| 2551 | tmp = ((Sdhc *)hw)->CCR.reg; |
| 2552 | tmp = (tmp & SDHC_CCR_CLKGSEL) >> SDHC_CCR_CLKGSEL_Pos; |
| 2553 | return (bool)tmp; |
| 2554 | } |
| 2555 | |
| 2556 | static inline void hri_sdhc_write_CCR_CLKGSEL_bit(const void *const hw, bool value) |
| 2557 | { |
| 2558 | uint16_t tmp; |
| 2559 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2560 | tmp = ((Sdhc *)hw)->CCR.reg; |
| 2561 | tmp &= ~SDHC_CCR_CLKGSEL; |
| 2562 | tmp |= value << SDHC_CCR_CLKGSEL_Pos; |
| 2563 | ((Sdhc *)hw)->CCR.reg = tmp; |
| 2564 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2565 | } |
| 2566 | |
| 2567 | static inline void hri_sdhc_clear_CCR_CLKGSEL_bit(const void *const hw) |
| 2568 | { |
| 2569 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2570 | ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_CLKGSEL; |
| 2571 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2572 | } |
| 2573 | |
| 2574 | static inline void hri_sdhc_toggle_CCR_CLKGSEL_bit(const void *const hw) |
| 2575 | { |
| 2576 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2577 | ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_CLKGSEL; |
| 2578 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2579 | } |
| 2580 | |
| 2581 | static inline void hri_sdhc_set_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) |
| 2582 | { |
| 2583 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2584 | ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_USDCLKFSEL(mask); |
| 2585 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2586 | } |
| 2587 | |
| 2588 | static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) |
| 2589 | { |
| 2590 | uint16_t tmp; |
| 2591 | tmp = ((Sdhc *)hw)->CCR.reg; |
| 2592 | tmp = (tmp & SDHC_CCR_USDCLKFSEL(mask)) >> SDHC_CCR_USDCLKFSEL_Pos; |
| 2593 | return tmp; |
| 2594 | } |
| 2595 | |
| 2596 | static inline void hri_sdhc_write_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t data) |
| 2597 | { |
| 2598 | uint16_t tmp; |
| 2599 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2600 | tmp = ((Sdhc *)hw)->CCR.reg; |
| 2601 | tmp &= ~SDHC_CCR_USDCLKFSEL_Msk; |
| 2602 | tmp |= SDHC_CCR_USDCLKFSEL(data); |
| 2603 | ((Sdhc *)hw)->CCR.reg = tmp; |
| 2604 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2605 | } |
| 2606 | |
| 2607 | static inline void hri_sdhc_clear_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) |
| 2608 | { |
| 2609 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2610 | ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_USDCLKFSEL(mask); |
| 2611 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2612 | } |
| 2613 | |
| 2614 | static inline void hri_sdhc_toggle_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) |
| 2615 | { |
| 2616 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2617 | ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_USDCLKFSEL(mask); |
| 2618 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2619 | } |
| 2620 | |
| 2621 | static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_USDCLKFSEL_bf(const void *const hw) |
| 2622 | { |
| 2623 | uint16_t tmp; |
| 2624 | tmp = ((Sdhc *)hw)->CCR.reg; |
| 2625 | tmp = (tmp & SDHC_CCR_USDCLKFSEL_Msk) >> SDHC_CCR_USDCLKFSEL_Pos; |
| 2626 | return tmp; |
| 2627 | } |
| 2628 | |
| 2629 | static inline void hri_sdhc_set_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) |
| 2630 | { |
| 2631 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2632 | ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_SDCLKFSEL(mask); |
| 2633 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2634 | } |
| 2635 | |
| 2636 | static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) |
| 2637 | { |
| 2638 | uint16_t tmp; |
| 2639 | tmp = ((Sdhc *)hw)->CCR.reg; |
| 2640 | tmp = (tmp & SDHC_CCR_SDCLKFSEL(mask)) >> SDHC_CCR_SDCLKFSEL_Pos; |
| 2641 | return tmp; |
| 2642 | } |
| 2643 | |
| 2644 | static inline void hri_sdhc_write_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t data) |
| 2645 | { |
| 2646 | uint16_t tmp; |
| 2647 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2648 | tmp = ((Sdhc *)hw)->CCR.reg; |
| 2649 | tmp &= ~SDHC_CCR_SDCLKFSEL_Msk; |
| 2650 | tmp |= SDHC_CCR_SDCLKFSEL(data); |
| 2651 | ((Sdhc *)hw)->CCR.reg = tmp; |
| 2652 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2653 | } |
| 2654 | |
| 2655 | static inline void hri_sdhc_clear_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) |
| 2656 | { |
| 2657 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2658 | ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_SDCLKFSEL(mask); |
| 2659 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2660 | } |
| 2661 | |
| 2662 | static inline void hri_sdhc_toggle_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) |
| 2663 | { |
| 2664 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2665 | ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_SDCLKFSEL(mask); |
| 2666 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2667 | } |
| 2668 | |
| 2669 | static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_SDCLKFSEL_bf(const void *const hw) |
| 2670 | { |
| 2671 | uint16_t tmp; |
| 2672 | tmp = ((Sdhc *)hw)->CCR.reg; |
| 2673 | tmp = (tmp & SDHC_CCR_SDCLKFSEL_Msk) >> SDHC_CCR_SDCLKFSEL_Pos; |
| 2674 | return tmp; |
| 2675 | } |
| 2676 | |
| 2677 | static inline void hri_sdhc_set_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) |
| 2678 | { |
| 2679 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2680 | ((Sdhc *)hw)->CCR.reg |= mask; |
| 2681 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2682 | } |
| 2683 | |
| 2684 | static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) |
| 2685 | { |
| 2686 | uint16_t tmp; |
| 2687 | tmp = ((Sdhc *)hw)->CCR.reg; |
| 2688 | tmp &= mask; |
| 2689 | return tmp; |
| 2690 | } |
| 2691 | |
| 2692 | static inline void hri_sdhc_write_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t data) |
| 2693 | { |
| 2694 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2695 | ((Sdhc *)hw)->CCR.reg = data; |
| 2696 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2697 | } |
| 2698 | |
| 2699 | static inline void hri_sdhc_clear_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) |
| 2700 | { |
| 2701 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2702 | ((Sdhc *)hw)->CCR.reg &= ~mask; |
| 2703 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2704 | } |
| 2705 | |
| 2706 | static inline void hri_sdhc_toggle_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) |
| 2707 | { |
| 2708 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2709 | ((Sdhc *)hw)->CCR.reg ^= mask; |
| 2710 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2711 | } |
| 2712 | |
| 2713 | static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_reg(const void *const hw) |
| 2714 | { |
| 2715 | return ((Sdhc *)hw)->CCR.reg; |
| 2716 | } |
| 2717 | |
| 2718 | static inline void hri_sdhc_set_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) |
| 2719 | { |
| 2720 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2721 | ((Sdhc *)hw)->TCR.reg |= SDHC_TCR_DTCVAL(mask); |
| 2722 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2723 | } |
| 2724 | |
| 2725 | static inline hri_sdhc_tcr_reg_t hri_sdhc_get_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) |
| 2726 | { |
| 2727 | uint8_t tmp; |
| 2728 | tmp = ((Sdhc *)hw)->TCR.reg; |
| 2729 | tmp = (tmp & SDHC_TCR_DTCVAL(mask)) >> SDHC_TCR_DTCVAL_Pos; |
| 2730 | return tmp; |
| 2731 | } |
| 2732 | |
| 2733 | static inline void hri_sdhc_write_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t data) |
| 2734 | { |
| 2735 | uint8_t tmp; |
| 2736 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2737 | tmp = ((Sdhc *)hw)->TCR.reg; |
| 2738 | tmp &= ~SDHC_TCR_DTCVAL_Msk; |
| 2739 | tmp |= SDHC_TCR_DTCVAL(data); |
| 2740 | ((Sdhc *)hw)->TCR.reg = tmp; |
| 2741 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2742 | } |
| 2743 | |
| 2744 | static inline void hri_sdhc_clear_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) |
| 2745 | { |
| 2746 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2747 | ((Sdhc *)hw)->TCR.reg &= ~SDHC_TCR_DTCVAL(mask); |
| 2748 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2749 | } |
| 2750 | |
| 2751 | static inline void hri_sdhc_toggle_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) |
| 2752 | { |
| 2753 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2754 | ((Sdhc *)hw)->TCR.reg ^= SDHC_TCR_DTCVAL(mask); |
| 2755 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2756 | } |
| 2757 | |
| 2758 | static inline hri_sdhc_tcr_reg_t hri_sdhc_read_TCR_DTCVAL_bf(const void *const hw) |
| 2759 | { |
| 2760 | uint8_t tmp; |
| 2761 | tmp = ((Sdhc *)hw)->TCR.reg; |
| 2762 | tmp = (tmp & SDHC_TCR_DTCVAL_Msk) >> SDHC_TCR_DTCVAL_Pos; |
| 2763 | return tmp; |
| 2764 | } |
| 2765 | |
| 2766 | static inline void hri_sdhc_set_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) |
| 2767 | { |
| 2768 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2769 | ((Sdhc *)hw)->TCR.reg |= mask; |
| 2770 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2771 | } |
| 2772 | |
| 2773 | static inline hri_sdhc_tcr_reg_t hri_sdhc_get_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) |
| 2774 | { |
| 2775 | uint8_t tmp; |
| 2776 | tmp = ((Sdhc *)hw)->TCR.reg; |
| 2777 | tmp &= mask; |
| 2778 | return tmp; |
| 2779 | } |
| 2780 | |
| 2781 | static inline void hri_sdhc_write_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t data) |
| 2782 | { |
| 2783 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2784 | ((Sdhc *)hw)->TCR.reg = data; |
| 2785 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2786 | } |
| 2787 | |
| 2788 | static inline void hri_sdhc_clear_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) |
| 2789 | { |
| 2790 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2791 | ((Sdhc *)hw)->TCR.reg &= ~mask; |
| 2792 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2793 | } |
| 2794 | |
| 2795 | static inline void hri_sdhc_toggle_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) |
| 2796 | { |
| 2797 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2798 | ((Sdhc *)hw)->TCR.reg ^= mask; |
| 2799 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2800 | } |
| 2801 | |
| 2802 | static inline hri_sdhc_tcr_reg_t hri_sdhc_read_TCR_reg(const void *const hw) |
| 2803 | { |
| 2804 | return ((Sdhc *)hw)->TCR.reg; |
| 2805 | } |
| 2806 | |
| 2807 | static inline void hri_sdhc_set_SRR_SWRSTALL_bit(const void *const hw) |
| 2808 | { |
| 2809 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2810 | ((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTALL; |
| 2811 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2812 | } |
| 2813 | |
| 2814 | static inline bool hri_sdhc_get_SRR_SWRSTALL_bit(const void *const hw) |
| 2815 | { |
| 2816 | uint8_t tmp; |
| 2817 | tmp = ((Sdhc *)hw)->SRR.reg; |
| 2818 | tmp = (tmp & SDHC_SRR_SWRSTALL) >> SDHC_SRR_SWRSTALL_Pos; |
| 2819 | return (bool)tmp; |
| 2820 | } |
| 2821 | |
| 2822 | static inline void hri_sdhc_write_SRR_SWRSTALL_bit(const void *const hw, bool value) |
| 2823 | { |
| 2824 | uint8_t tmp; |
| 2825 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2826 | tmp = ((Sdhc *)hw)->SRR.reg; |
| 2827 | tmp &= ~SDHC_SRR_SWRSTALL; |
| 2828 | tmp |= value << SDHC_SRR_SWRSTALL_Pos; |
| 2829 | ((Sdhc *)hw)->SRR.reg = tmp; |
| 2830 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2831 | } |
| 2832 | |
| 2833 | static inline void hri_sdhc_clear_SRR_SWRSTALL_bit(const void *const hw) |
| 2834 | { |
| 2835 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2836 | ((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTALL; |
| 2837 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2838 | } |
| 2839 | |
| 2840 | static inline void hri_sdhc_toggle_SRR_SWRSTALL_bit(const void *const hw) |
| 2841 | { |
| 2842 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2843 | ((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTALL; |
| 2844 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2845 | } |
| 2846 | |
| 2847 | static inline void hri_sdhc_set_SRR_SWRSTCMD_bit(const void *const hw) |
| 2848 | { |
| 2849 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2850 | ((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTCMD; |
| 2851 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2852 | } |
| 2853 | |
| 2854 | static inline bool hri_sdhc_get_SRR_SWRSTCMD_bit(const void *const hw) |
| 2855 | { |
| 2856 | uint8_t tmp; |
| 2857 | tmp = ((Sdhc *)hw)->SRR.reg; |
| 2858 | tmp = (tmp & SDHC_SRR_SWRSTCMD) >> SDHC_SRR_SWRSTCMD_Pos; |
| 2859 | return (bool)tmp; |
| 2860 | } |
| 2861 | |
| 2862 | static inline void hri_sdhc_write_SRR_SWRSTCMD_bit(const void *const hw, bool value) |
| 2863 | { |
| 2864 | uint8_t tmp; |
| 2865 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2866 | tmp = ((Sdhc *)hw)->SRR.reg; |
| 2867 | tmp &= ~SDHC_SRR_SWRSTCMD; |
| 2868 | tmp |= value << SDHC_SRR_SWRSTCMD_Pos; |
| 2869 | ((Sdhc *)hw)->SRR.reg = tmp; |
| 2870 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2871 | } |
| 2872 | |
| 2873 | static inline void hri_sdhc_clear_SRR_SWRSTCMD_bit(const void *const hw) |
| 2874 | { |
| 2875 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2876 | ((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTCMD; |
| 2877 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2878 | } |
| 2879 | |
| 2880 | static inline void hri_sdhc_toggle_SRR_SWRSTCMD_bit(const void *const hw) |
| 2881 | { |
| 2882 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2883 | ((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTCMD; |
| 2884 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2885 | } |
| 2886 | |
| 2887 | static inline void hri_sdhc_set_SRR_SWRSTDAT_bit(const void *const hw) |
| 2888 | { |
| 2889 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2890 | ((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTDAT; |
| 2891 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2892 | } |
| 2893 | |
| 2894 | static inline bool hri_sdhc_get_SRR_SWRSTDAT_bit(const void *const hw) |
| 2895 | { |
| 2896 | uint8_t tmp; |
| 2897 | tmp = ((Sdhc *)hw)->SRR.reg; |
| 2898 | tmp = (tmp & SDHC_SRR_SWRSTDAT) >> SDHC_SRR_SWRSTDAT_Pos; |
| 2899 | return (bool)tmp; |
| 2900 | } |
| 2901 | |
| 2902 | static inline void hri_sdhc_write_SRR_SWRSTDAT_bit(const void *const hw, bool value) |
| 2903 | { |
| 2904 | uint8_t tmp; |
| 2905 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2906 | tmp = ((Sdhc *)hw)->SRR.reg; |
| 2907 | tmp &= ~SDHC_SRR_SWRSTDAT; |
| 2908 | tmp |= value << SDHC_SRR_SWRSTDAT_Pos; |
| 2909 | ((Sdhc *)hw)->SRR.reg = tmp; |
| 2910 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2911 | } |
| 2912 | |
| 2913 | static inline void hri_sdhc_clear_SRR_SWRSTDAT_bit(const void *const hw) |
| 2914 | { |
| 2915 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2916 | ((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTDAT; |
| 2917 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2918 | } |
| 2919 | |
| 2920 | static inline void hri_sdhc_toggle_SRR_SWRSTDAT_bit(const void *const hw) |
| 2921 | { |
| 2922 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2923 | ((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTDAT; |
| 2924 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2925 | } |
| 2926 | |
| 2927 | static inline void hri_sdhc_set_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) |
| 2928 | { |
| 2929 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2930 | ((Sdhc *)hw)->SRR.reg |= mask; |
| 2931 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2932 | } |
| 2933 | |
| 2934 | static inline hri_sdhc_srr_reg_t hri_sdhc_get_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) |
| 2935 | { |
| 2936 | uint8_t tmp; |
| 2937 | tmp = ((Sdhc *)hw)->SRR.reg; |
| 2938 | tmp &= mask; |
| 2939 | return tmp; |
| 2940 | } |
| 2941 | |
| 2942 | static inline void hri_sdhc_write_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t data) |
| 2943 | { |
| 2944 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2945 | ((Sdhc *)hw)->SRR.reg = data; |
| 2946 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2947 | } |
| 2948 | |
| 2949 | static inline void hri_sdhc_clear_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) |
| 2950 | { |
| 2951 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2952 | ((Sdhc *)hw)->SRR.reg &= ~mask; |
| 2953 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2954 | } |
| 2955 | |
| 2956 | static inline void hri_sdhc_toggle_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) |
| 2957 | { |
| 2958 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2959 | ((Sdhc *)hw)->SRR.reg ^= mask; |
| 2960 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2961 | } |
| 2962 | |
| 2963 | static inline hri_sdhc_srr_reg_t hri_sdhc_read_SRR_reg(const void *const hw) |
| 2964 | { |
| 2965 | return ((Sdhc *)hw)->SRR.reg; |
| 2966 | } |
| 2967 | |
| 2968 | static inline void hri_sdhc_set_NISTR_CMDC_bit(const void *const hw) |
| 2969 | { |
| 2970 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2971 | ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CMDC; |
| 2972 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2973 | } |
| 2974 | |
| 2975 | static inline bool hri_sdhc_get_NISTR_CMDC_bit(const void *const hw) |
| 2976 | { |
| 2977 | uint16_t tmp; |
| 2978 | tmp = ((Sdhc *)hw)->NISTR.reg; |
| 2979 | tmp = (tmp & SDHC_NISTR_CMDC) >> SDHC_NISTR_CMDC_Pos; |
| 2980 | return (bool)tmp; |
| 2981 | } |
| 2982 | |
| 2983 | static inline void hri_sdhc_write_NISTR_CMDC_bit(const void *const hw, bool value) |
| 2984 | { |
| 2985 | uint16_t tmp; |
| 2986 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2987 | tmp = ((Sdhc *)hw)->NISTR.reg; |
| 2988 | tmp &= ~SDHC_NISTR_CMDC; |
| 2989 | tmp |= value << SDHC_NISTR_CMDC_Pos; |
| 2990 | ((Sdhc *)hw)->NISTR.reg = tmp; |
| 2991 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2992 | } |
| 2993 | |
| 2994 | static inline void hri_sdhc_clear_NISTR_CMDC_bit(const void *const hw) |
| 2995 | { |
| 2996 | SDHC_CRITICAL_SECTION_ENTER(); |
| 2997 | ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CMDC; |
| 2998 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 2999 | } |
| 3000 | |
| 3001 | static inline void hri_sdhc_toggle_NISTR_CMDC_bit(const void *const hw) |
| 3002 | { |
| 3003 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3004 | ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CMDC; |
| 3005 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3006 | } |
| 3007 | |
| 3008 | static inline void hri_sdhc_set_NISTR_TRFC_bit(const void *const hw) |
| 3009 | { |
| 3010 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3011 | ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_TRFC; |
| 3012 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3013 | } |
| 3014 | |
| 3015 | static inline bool hri_sdhc_get_NISTR_TRFC_bit(const void *const hw) |
| 3016 | { |
| 3017 | uint16_t tmp; |
| 3018 | tmp = ((Sdhc *)hw)->NISTR.reg; |
| 3019 | tmp = (tmp & SDHC_NISTR_TRFC) >> SDHC_NISTR_TRFC_Pos; |
| 3020 | return (bool)tmp; |
| 3021 | } |
| 3022 | |
| 3023 | static inline void hri_sdhc_write_NISTR_TRFC_bit(const void *const hw, bool value) |
| 3024 | { |
| 3025 | uint16_t tmp; |
| 3026 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3027 | tmp = ((Sdhc *)hw)->NISTR.reg; |
| 3028 | tmp &= ~SDHC_NISTR_TRFC; |
| 3029 | tmp |= value << SDHC_NISTR_TRFC_Pos; |
| 3030 | ((Sdhc *)hw)->NISTR.reg = tmp; |
| 3031 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3032 | } |
| 3033 | |
| 3034 | static inline void hri_sdhc_clear_NISTR_TRFC_bit(const void *const hw) |
| 3035 | { |
| 3036 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3037 | ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_TRFC; |
| 3038 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3039 | } |
| 3040 | |
| 3041 | static inline void hri_sdhc_toggle_NISTR_TRFC_bit(const void *const hw) |
| 3042 | { |
| 3043 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3044 | ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_TRFC; |
| 3045 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3046 | } |
| 3047 | |
| 3048 | static inline void hri_sdhc_set_NISTR_BLKGE_bit(const void *const hw) |
| 3049 | { |
| 3050 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3051 | ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BLKGE; |
| 3052 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3053 | } |
| 3054 | |
| 3055 | static inline bool hri_sdhc_get_NISTR_BLKGE_bit(const void *const hw) |
| 3056 | { |
| 3057 | uint16_t tmp; |
| 3058 | tmp = ((Sdhc *)hw)->NISTR.reg; |
| 3059 | tmp = (tmp & SDHC_NISTR_BLKGE) >> SDHC_NISTR_BLKGE_Pos; |
| 3060 | return (bool)tmp; |
| 3061 | } |
| 3062 | |
| 3063 | static inline void hri_sdhc_write_NISTR_BLKGE_bit(const void *const hw, bool value) |
| 3064 | { |
| 3065 | uint16_t tmp; |
| 3066 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3067 | tmp = ((Sdhc *)hw)->NISTR.reg; |
| 3068 | tmp &= ~SDHC_NISTR_BLKGE; |
| 3069 | tmp |= value << SDHC_NISTR_BLKGE_Pos; |
| 3070 | ((Sdhc *)hw)->NISTR.reg = tmp; |
| 3071 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3072 | } |
| 3073 | |
| 3074 | static inline void hri_sdhc_clear_NISTR_BLKGE_bit(const void *const hw) |
| 3075 | { |
| 3076 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3077 | ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BLKGE; |
| 3078 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3079 | } |
| 3080 | |
| 3081 | static inline void hri_sdhc_toggle_NISTR_BLKGE_bit(const void *const hw) |
| 3082 | { |
| 3083 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3084 | ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BLKGE; |
| 3085 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3086 | } |
| 3087 | |
| 3088 | static inline void hri_sdhc_set_NISTR_DMAINT_bit(const void *const hw) |
| 3089 | { |
| 3090 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3091 | ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_DMAINT; |
| 3092 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3093 | } |
| 3094 | |
| 3095 | static inline bool hri_sdhc_get_NISTR_DMAINT_bit(const void *const hw) |
| 3096 | { |
| 3097 | uint16_t tmp; |
| 3098 | tmp = ((Sdhc *)hw)->NISTR.reg; |
| 3099 | tmp = (tmp & SDHC_NISTR_DMAINT) >> SDHC_NISTR_DMAINT_Pos; |
| 3100 | return (bool)tmp; |
| 3101 | } |
| 3102 | |
| 3103 | static inline void hri_sdhc_write_NISTR_DMAINT_bit(const void *const hw, bool value) |
| 3104 | { |
| 3105 | uint16_t tmp; |
| 3106 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3107 | tmp = ((Sdhc *)hw)->NISTR.reg; |
| 3108 | tmp &= ~SDHC_NISTR_DMAINT; |
| 3109 | tmp |= value << SDHC_NISTR_DMAINT_Pos; |
| 3110 | ((Sdhc *)hw)->NISTR.reg = tmp; |
| 3111 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3112 | } |
| 3113 | |
| 3114 | static inline void hri_sdhc_clear_NISTR_DMAINT_bit(const void *const hw) |
| 3115 | { |
| 3116 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3117 | ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_DMAINT; |
| 3118 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3119 | } |
| 3120 | |
| 3121 | static inline void hri_sdhc_toggle_NISTR_DMAINT_bit(const void *const hw) |
| 3122 | { |
| 3123 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3124 | ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_DMAINT; |
| 3125 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3126 | } |
| 3127 | |
| 3128 | static inline void hri_sdhc_set_NISTR_BWRRDY_bit(const void *const hw) |
| 3129 | { |
| 3130 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3131 | ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BWRRDY; |
| 3132 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3133 | } |
| 3134 | |
| 3135 | static inline bool hri_sdhc_get_NISTR_BWRRDY_bit(const void *const hw) |
| 3136 | { |
| 3137 | uint16_t tmp; |
| 3138 | tmp = ((Sdhc *)hw)->NISTR.reg; |
| 3139 | tmp = (tmp & SDHC_NISTR_BWRRDY) >> SDHC_NISTR_BWRRDY_Pos; |
| 3140 | return (bool)tmp; |
| 3141 | } |
| 3142 | |
| 3143 | static inline void hri_sdhc_write_NISTR_BWRRDY_bit(const void *const hw, bool value) |
| 3144 | { |
| 3145 | uint16_t tmp; |
| 3146 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3147 | tmp = ((Sdhc *)hw)->NISTR.reg; |
| 3148 | tmp &= ~SDHC_NISTR_BWRRDY; |
| 3149 | tmp |= value << SDHC_NISTR_BWRRDY_Pos; |
| 3150 | ((Sdhc *)hw)->NISTR.reg = tmp; |
| 3151 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3152 | } |
| 3153 | |
| 3154 | static inline void hri_sdhc_clear_NISTR_BWRRDY_bit(const void *const hw) |
| 3155 | { |
| 3156 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3157 | ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BWRRDY; |
| 3158 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3159 | } |
| 3160 | |
| 3161 | static inline void hri_sdhc_toggle_NISTR_BWRRDY_bit(const void *const hw) |
| 3162 | { |
| 3163 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3164 | ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BWRRDY; |
| 3165 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3166 | } |
| 3167 | |
| 3168 | static inline void hri_sdhc_set_NISTR_BRDRDY_bit(const void *const hw) |
| 3169 | { |
| 3170 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3171 | ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BRDRDY; |
| 3172 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3173 | } |
| 3174 | |
| 3175 | static inline bool hri_sdhc_get_NISTR_BRDRDY_bit(const void *const hw) |
| 3176 | { |
| 3177 | uint16_t tmp; |
| 3178 | tmp = ((Sdhc *)hw)->NISTR.reg; |
| 3179 | tmp = (tmp & SDHC_NISTR_BRDRDY) >> SDHC_NISTR_BRDRDY_Pos; |
| 3180 | return (bool)tmp; |
| 3181 | } |
| 3182 | |
| 3183 | static inline void hri_sdhc_write_NISTR_BRDRDY_bit(const void *const hw, bool value) |
| 3184 | { |
| 3185 | uint16_t tmp; |
| 3186 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3187 | tmp = ((Sdhc *)hw)->NISTR.reg; |
| 3188 | tmp &= ~SDHC_NISTR_BRDRDY; |
| 3189 | tmp |= value << SDHC_NISTR_BRDRDY_Pos; |
| 3190 | ((Sdhc *)hw)->NISTR.reg = tmp; |
| 3191 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3192 | } |
| 3193 | |
| 3194 | static inline void hri_sdhc_clear_NISTR_BRDRDY_bit(const void *const hw) |
| 3195 | { |
| 3196 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3197 | ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BRDRDY; |
| 3198 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3199 | } |
| 3200 | |
| 3201 | static inline void hri_sdhc_toggle_NISTR_BRDRDY_bit(const void *const hw) |
| 3202 | { |
| 3203 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3204 | ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BRDRDY; |
| 3205 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3206 | } |
| 3207 | |
| 3208 | static inline void hri_sdhc_set_NISTR_CINS_bit(const void *const hw) |
| 3209 | { |
| 3210 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3211 | ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CINS; |
| 3212 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3213 | } |
| 3214 | |
| 3215 | static inline bool hri_sdhc_get_NISTR_CINS_bit(const void *const hw) |
| 3216 | { |
| 3217 | uint16_t tmp; |
| 3218 | tmp = ((Sdhc *)hw)->NISTR.reg; |
| 3219 | tmp = (tmp & SDHC_NISTR_CINS) >> SDHC_NISTR_CINS_Pos; |
| 3220 | return (bool)tmp; |
| 3221 | } |
| 3222 | |
| 3223 | static inline void hri_sdhc_write_NISTR_CINS_bit(const void *const hw, bool value) |
| 3224 | { |
| 3225 | uint16_t tmp; |
| 3226 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3227 | tmp = ((Sdhc *)hw)->NISTR.reg; |
| 3228 | tmp &= ~SDHC_NISTR_CINS; |
| 3229 | tmp |= value << SDHC_NISTR_CINS_Pos; |
| 3230 | ((Sdhc *)hw)->NISTR.reg = tmp; |
| 3231 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3232 | } |
| 3233 | |
| 3234 | static inline void hri_sdhc_clear_NISTR_CINS_bit(const void *const hw) |
| 3235 | { |
| 3236 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3237 | ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CINS; |
| 3238 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3239 | } |
| 3240 | |
| 3241 | static inline void hri_sdhc_toggle_NISTR_CINS_bit(const void *const hw) |
| 3242 | { |
| 3243 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3244 | ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CINS; |
| 3245 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3246 | } |
| 3247 | |
| 3248 | static inline void hri_sdhc_set_NISTR_CREM_bit(const void *const hw) |
| 3249 | { |
| 3250 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3251 | ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CREM; |
| 3252 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3253 | } |
| 3254 | |
| 3255 | static inline bool hri_sdhc_get_NISTR_CREM_bit(const void *const hw) |
| 3256 | { |
| 3257 | uint16_t tmp; |
| 3258 | tmp = ((Sdhc *)hw)->NISTR.reg; |
| 3259 | tmp = (tmp & SDHC_NISTR_CREM) >> SDHC_NISTR_CREM_Pos; |
| 3260 | return (bool)tmp; |
| 3261 | } |
| 3262 | |
| 3263 | static inline void hri_sdhc_write_NISTR_CREM_bit(const void *const hw, bool value) |
| 3264 | { |
| 3265 | uint16_t tmp; |
| 3266 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3267 | tmp = ((Sdhc *)hw)->NISTR.reg; |
| 3268 | tmp &= ~SDHC_NISTR_CREM; |
| 3269 | tmp |= value << SDHC_NISTR_CREM_Pos; |
| 3270 | ((Sdhc *)hw)->NISTR.reg = tmp; |
| 3271 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3272 | } |
| 3273 | |
| 3274 | static inline void hri_sdhc_clear_NISTR_CREM_bit(const void *const hw) |
| 3275 | { |
| 3276 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3277 | ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CREM; |
| 3278 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3279 | } |
| 3280 | |
| 3281 | static inline void hri_sdhc_toggle_NISTR_CREM_bit(const void *const hw) |
| 3282 | { |
| 3283 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3284 | ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CREM; |
| 3285 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3286 | } |
| 3287 | |
| 3288 | static inline void hri_sdhc_set_NISTR_CINT_bit(const void *const hw) |
| 3289 | { |
| 3290 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3291 | ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CINT; |
| 3292 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3293 | } |
| 3294 | |
| 3295 | static inline bool hri_sdhc_get_NISTR_CINT_bit(const void *const hw) |
| 3296 | { |
| 3297 | uint16_t tmp; |
| 3298 | tmp = ((Sdhc *)hw)->NISTR.reg; |
| 3299 | tmp = (tmp & SDHC_NISTR_CINT) >> SDHC_NISTR_CINT_Pos; |
| 3300 | return (bool)tmp; |
| 3301 | } |
| 3302 | |
| 3303 | static inline void hri_sdhc_write_NISTR_CINT_bit(const void *const hw, bool value) |
| 3304 | { |
| 3305 | uint16_t tmp; |
| 3306 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3307 | tmp = ((Sdhc *)hw)->NISTR.reg; |
| 3308 | tmp &= ~SDHC_NISTR_CINT; |
| 3309 | tmp |= value << SDHC_NISTR_CINT_Pos; |
| 3310 | ((Sdhc *)hw)->NISTR.reg = tmp; |
| 3311 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3312 | } |
| 3313 | |
| 3314 | static inline void hri_sdhc_clear_NISTR_CINT_bit(const void *const hw) |
| 3315 | { |
| 3316 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3317 | ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CINT; |
| 3318 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3319 | } |
| 3320 | |
| 3321 | static inline void hri_sdhc_toggle_NISTR_CINT_bit(const void *const hw) |
| 3322 | { |
| 3323 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3324 | ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CINT; |
| 3325 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3326 | } |
| 3327 | |
| 3328 | static inline void hri_sdhc_set_NISTR_EMMC_BOOTAR_bit(const void *const hw) |
| 3329 | { |
| 3330 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3331 | ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_EMMC_BOOTAR; |
| 3332 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3333 | } |
| 3334 | |
| 3335 | static inline bool hri_sdhc_get_NISTR_EMMC_BOOTAR_bit(const void *const hw) |
| 3336 | { |
| 3337 | uint16_t tmp; |
| 3338 | tmp = ((Sdhc *)hw)->NISTR.reg; |
| 3339 | tmp = (tmp & SDHC_NISTR_EMMC_BOOTAR) >> SDHC_NISTR_EMMC_BOOTAR_Pos; |
| 3340 | return (bool)tmp; |
| 3341 | } |
| 3342 | |
| 3343 | static inline void hri_sdhc_write_NISTR_EMMC_BOOTAR_bit(const void *const hw, bool value) |
| 3344 | { |
| 3345 | uint16_t tmp; |
| 3346 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3347 | tmp = ((Sdhc *)hw)->NISTR.reg; |
| 3348 | tmp &= ~SDHC_NISTR_EMMC_BOOTAR; |
| 3349 | tmp |= value << SDHC_NISTR_EMMC_BOOTAR_Pos; |
| 3350 | ((Sdhc *)hw)->NISTR.reg = tmp; |
| 3351 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3352 | } |
| 3353 | |
| 3354 | static inline void hri_sdhc_clear_NISTR_EMMC_BOOTAR_bit(const void *const hw) |
| 3355 | { |
| 3356 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3357 | ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_EMMC_BOOTAR; |
| 3358 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3359 | } |
| 3360 | |
| 3361 | static inline void hri_sdhc_toggle_NISTR_EMMC_BOOTAR_bit(const void *const hw) |
| 3362 | { |
| 3363 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3364 | ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_EMMC_BOOTAR; |
| 3365 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3366 | } |
| 3367 | |
| 3368 | static inline void hri_sdhc_set_NISTR_ERRINT_bit(const void *const hw) |
| 3369 | { |
| 3370 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3371 | ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_ERRINT; |
| 3372 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3373 | } |
| 3374 | |
| 3375 | static inline bool hri_sdhc_get_NISTR_ERRINT_bit(const void *const hw) |
| 3376 | { |
| 3377 | uint16_t tmp; |
| 3378 | tmp = ((Sdhc *)hw)->NISTR.reg; |
| 3379 | tmp = (tmp & SDHC_NISTR_ERRINT) >> SDHC_NISTR_ERRINT_Pos; |
| 3380 | return (bool)tmp; |
| 3381 | } |
| 3382 | |
| 3383 | static inline void hri_sdhc_write_NISTR_ERRINT_bit(const void *const hw, bool value) |
| 3384 | { |
| 3385 | uint16_t tmp; |
| 3386 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3387 | tmp = ((Sdhc *)hw)->NISTR.reg; |
| 3388 | tmp &= ~SDHC_NISTR_ERRINT; |
| 3389 | tmp |= value << SDHC_NISTR_ERRINT_Pos; |
| 3390 | ((Sdhc *)hw)->NISTR.reg = tmp; |
| 3391 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3392 | } |
| 3393 | |
| 3394 | static inline void hri_sdhc_clear_NISTR_ERRINT_bit(const void *const hw) |
| 3395 | { |
| 3396 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3397 | ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_ERRINT; |
| 3398 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3399 | } |
| 3400 | |
| 3401 | static inline void hri_sdhc_toggle_NISTR_ERRINT_bit(const void *const hw) |
| 3402 | { |
| 3403 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3404 | ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_ERRINT; |
| 3405 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3406 | } |
| 3407 | |
| 3408 | static inline void hri_sdhc_set_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) |
| 3409 | { |
| 3410 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3411 | ((Sdhc *)hw)->NISTR.reg |= mask; |
| 3412 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3413 | } |
| 3414 | |
| 3415 | static inline hri_sdhc_nistr_reg_t hri_sdhc_get_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) |
| 3416 | { |
| 3417 | uint16_t tmp; |
| 3418 | tmp = ((Sdhc *)hw)->NISTR.reg; |
| 3419 | tmp &= mask; |
| 3420 | return tmp; |
| 3421 | } |
| 3422 | |
| 3423 | static inline void hri_sdhc_write_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t data) |
| 3424 | { |
| 3425 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3426 | ((Sdhc *)hw)->NISTR.reg = data; |
| 3427 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3428 | } |
| 3429 | |
| 3430 | static inline void hri_sdhc_clear_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) |
| 3431 | { |
| 3432 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3433 | ((Sdhc *)hw)->NISTR.reg &= ~mask; |
| 3434 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3435 | } |
| 3436 | |
| 3437 | static inline void hri_sdhc_toggle_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) |
| 3438 | { |
| 3439 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3440 | ((Sdhc *)hw)->NISTR.reg ^= mask; |
| 3441 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3442 | } |
| 3443 | |
| 3444 | static inline hri_sdhc_nistr_reg_t hri_sdhc_read_NISTR_reg(const void *const hw) |
| 3445 | { |
| 3446 | return ((Sdhc *)hw)->NISTR.reg; |
| 3447 | } |
| 3448 | |
| 3449 | static inline void hri_sdhc_set_EISTR_CMDTEO_bit(const void *const hw) |
| 3450 | { |
| 3451 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3452 | ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDTEO; |
| 3453 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3454 | } |
| 3455 | |
| 3456 | static inline bool hri_sdhc_get_EISTR_CMDTEO_bit(const void *const hw) |
| 3457 | { |
| 3458 | uint16_t tmp; |
| 3459 | tmp = ((Sdhc *)hw)->EISTR.reg; |
| 3460 | tmp = (tmp & SDHC_EISTR_CMDTEO) >> SDHC_EISTR_CMDTEO_Pos; |
| 3461 | return (bool)tmp; |
| 3462 | } |
| 3463 | |
| 3464 | static inline void hri_sdhc_write_EISTR_CMDTEO_bit(const void *const hw, bool value) |
| 3465 | { |
| 3466 | uint16_t tmp; |
| 3467 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3468 | tmp = ((Sdhc *)hw)->EISTR.reg; |
| 3469 | tmp &= ~SDHC_EISTR_CMDTEO; |
| 3470 | tmp |= value << SDHC_EISTR_CMDTEO_Pos; |
| 3471 | ((Sdhc *)hw)->EISTR.reg = tmp; |
| 3472 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3473 | } |
| 3474 | |
| 3475 | static inline void hri_sdhc_clear_EISTR_CMDTEO_bit(const void *const hw) |
| 3476 | { |
| 3477 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3478 | ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDTEO; |
| 3479 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3480 | } |
| 3481 | |
| 3482 | static inline void hri_sdhc_toggle_EISTR_CMDTEO_bit(const void *const hw) |
| 3483 | { |
| 3484 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3485 | ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDTEO; |
| 3486 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3487 | } |
| 3488 | |
| 3489 | static inline void hri_sdhc_set_EISTR_CMDCRC_bit(const void *const hw) |
| 3490 | { |
| 3491 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3492 | ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDCRC; |
| 3493 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3494 | } |
| 3495 | |
| 3496 | static inline bool hri_sdhc_get_EISTR_CMDCRC_bit(const void *const hw) |
| 3497 | { |
| 3498 | uint16_t tmp; |
| 3499 | tmp = ((Sdhc *)hw)->EISTR.reg; |
| 3500 | tmp = (tmp & SDHC_EISTR_CMDCRC) >> SDHC_EISTR_CMDCRC_Pos; |
| 3501 | return (bool)tmp; |
| 3502 | } |
| 3503 | |
| 3504 | static inline void hri_sdhc_write_EISTR_CMDCRC_bit(const void *const hw, bool value) |
| 3505 | { |
| 3506 | uint16_t tmp; |
| 3507 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3508 | tmp = ((Sdhc *)hw)->EISTR.reg; |
| 3509 | tmp &= ~SDHC_EISTR_CMDCRC; |
| 3510 | tmp |= value << SDHC_EISTR_CMDCRC_Pos; |
| 3511 | ((Sdhc *)hw)->EISTR.reg = tmp; |
| 3512 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3513 | } |
| 3514 | |
| 3515 | static inline void hri_sdhc_clear_EISTR_CMDCRC_bit(const void *const hw) |
| 3516 | { |
| 3517 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3518 | ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDCRC; |
| 3519 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3520 | } |
| 3521 | |
| 3522 | static inline void hri_sdhc_toggle_EISTR_CMDCRC_bit(const void *const hw) |
| 3523 | { |
| 3524 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3525 | ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDCRC; |
| 3526 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3527 | } |
| 3528 | |
| 3529 | static inline void hri_sdhc_set_EISTR_CMDEND_bit(const void *const hw) |
| 3530 | { |
| 3531 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3532 | ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDEND; |
| 3533 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3534 | } |
| 3535 | |
| 3536 | static inline bool hri_sdhc_get_EISTR_CMDEND_bit(const void *const hw) |
| 3537 | { |
| 3538 | uint16_t tmp; |
| 3539 | tmp = ((Sdhc *)hw)->EISTR.reg; |
| 3540 | tmp = (tmp & SDHC_EISTR_CMDEND) >> SDHC_EISTR_CMDEND_Pos; |
| 3541 | return (bool)tmp; |
| 3542 | } |
| 3543 | |
| 3544 | static inline void hri_sdhc_write_EISTR_CMDEND_bit(const void *const hw, bool value) |
| 3545 | { |
| 3546 | uint16_t tmp; |
| 3547 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3548 | tmp = ((Sdhc *)hw)->EISTR.reg; |
| 3549 | tmp &= ~SDHC_EISTR_CMDEND; |
| 3550 | tmp |= value << SDHC_EISTR_CMDEND_Pos; |
| 3551 | ((Sdhc *)hw)->EISTR.reg = tmp; |
| 3552 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3553 | } |
| 3554 | |
| 3555 | static inline void hri_sdhc_clear_EISTR_CMDEND_bit(const void *const hw) |
| 3556 | { |
| 3557 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3558 | ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDEND; |
| 3559 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3560 | } |
| 3561 | |
| 3562 | static inline void hri_sdhc_toggle_EISTR_CMDEND_bit(const void *const hw) |
| 3563 | { |
| 3564 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3565 | ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDEND; |
| 3566 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3567 | } |
| 3568 | |
| 3569 | static inline void hri_sdhc_set_EISTR_CMDIDX_bit(const void *const hw) |
| 3570 | { |
| 3571 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3572 | ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDIDX; |
| 3573 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3574 | } |
| 3575 | |
| 3576 | static inline bool hri_sdhc_get_EISTR_CMDIDX_bit(const void *const hw) |
| 3577 | { |
| 3578 | uint16_t tmp; |
| 3579 | tmp = ((Sdhc *)hw)->EISTR.reg; |
| 3580 | tmp = (tmp & SDHC_EISTR_CMDIDX) >> SDHC_EISTR_CMDIDX_Pos; |
| 3581 | return (bool)tmp; |
| 3582 | } |
| 3583 | |
| 3584 | static inline void hri_sdhc_write_EISTR_CMDIDX_bit(const void *const hw, bool value) |
| 3585 | { |
| 3586 | uint16_t tmp; |
| 3587 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3588 | tmp = ((Sdhc *)hw)->EISTR.reg; |
| 3589 | tmp &= ~SDHC_EISTR_CMDIDX; |
| 3590 | tmp |= value << SDHC_EISTR_CMDIDX_Pos; |
| 3591 | ((Sdhc *)hw)->EISTR.reg = tmp; |
| 3592 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3593 | } |
| 3594 | |
| 3595 | static inline void hri_sdhc_clear_EISTR_CMDIDX_bit(const void *const hw) |
| 3596 | { |
| 3597 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3598 | ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDIDX; |
| 3599 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3600 | } |
| 3601 | |
| 3602 | static inline void hri_sdhc_toggle_EISTR_CMDIDX_bit(const void *const hw) |
| 3603 | { |
| 3604 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3605 | ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDIDX; |
| 3606 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3607 | } |
| 3608 | |
| 3609 | static inline void hri_sdhc_set_EISTR_DATTEO_bit(const void *const hw) |
| 3610 | { |
| 3611 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3612 | ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATTEO; |
| 3613 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3614 | } |
| 3615 | |
| 3616 | static inline bool hri_sdhc_get_EISTR_DATTEO_bit(const void *const hw) |
| 3617 | { |
| 3618 | uint16_t tmp; |
| 3619 | tmp = ((Sdhc *)hw)->EISTR.reg; |
| 3620 | tmp = (tmp & SDHC_EISTR_DATTEO) >> SDHC_EISTR_DATTEO_Pos; |
| 3621 | return (bool)tmp; |
| 3622 | } |
| 3623 | |
| 3624 | static inline void hri_sdhc_write_EISTR_DATTEO_bit(const void *const hw, bool value) |
| 3625 | { |
| 3626 | uint16_t tmp; |
| 3627 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3628 | tmp = ((Sdhc *)hw)->EISTR.reg; |
| 3629 | tmp &= ~SDHC_EISTR_DATTEO; |
| 3630 | tmp |= value << SDHC_EISTR_DATTEO_Pos; |
| 3631 | ((Sdhc *)hw)->EISTR.reg = tmp; |
| 3632 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3633 | } |
| 3634 | |
| 3635 | static inline void hri_sdhc_clear_EISTR_DATTEO_bit(const void *const hw) |
| 3636 | { |
| 3637 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3638 | ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATTEO; |
| 3639 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3640 | } |
| 3641 | |
| 3642 | static inline void hri_sdhc_toggle_EISTR_DATTEO_bit(const void *const hw) |
| 3643 | { |
| 3644 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3645 | ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATTEO; |
| 3646 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3647 | } |
| 3648 | |
| 3649 | static inline void hri_sdhc_set_EISTR_DATCRC_bit(const void *const hw) |
| 3650 | { |
| 3651 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3652 | ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATCRC; |
| 3653 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3654 | } |
| 3655 | |
| 3656 | static inline bool hri_sdhc_get_EISTR_DATCRC_bit(const void *const hw) |
| 3657 | { |
| 3658 | uint16_t tmp; |
| 3659 | tmp = ((Sdhc *)hw)->EISTR.reg; |
| 3660 | tmp = (tmp & SDHC_EISTR_DATCRC) >> SDHC_EISTR_DATCRC_Pos; |
| 3661 | return (bool)tmp; |
| 3662 | } |
| 3663 | |
| 3664 | static inline void hri_sdhc_write_EISTR_DATCRC_bit(const void *const hw, bool value) |
| 3665 | { |
| 3666 | uint16_t tmp; |
| 3667 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3668 | tmp = ((Sdhc *)hw)->EISTR.reg; |
| 3669 | tmp &= ~SDHC_EISTR_DATCRC; |
| 3670 | tmp |= value << SDHC_EISTR_DATCRC_Pos; |
| 3671 | ((Sdhc *)hw)->EISTR.reg = tmp; |
| 3672 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3673 | } |
| 3674 | |
| 3675 | static inline void hri_sdhc_clear_EISTR_DATCRC_bit(const void *const hw) |
| 3676 | { |
| 3677 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3678 | ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATCRC; |
| 3679 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3680 | } |
| 3681 | |
| 3682 | static inline void hri_sdhc_toggle_EISTR_DATCRC_bit(const void *const hw) |
| 3683 | { |
| 3684 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3685 | ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATCRC; |
| 3686 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3687 | } |
| 3688 | |
| 3689 | static inline void hri_sdhc_set_EISTR_DATEND_bit(const void *const hw) |
| 3690 | { |
| 3691 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3692 | ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATEND; |
| 3693 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3694 | } |
| 3695 | |
| 3696 | static inline bool hri_sdhc_get_EISTR_DATEND_bit(const void *const hw) |
| 3697 | { |
| 3698 | uint16_t tmp; |
| 3699 | tmp = ((Sdhc *)hw)->EISTR.reg; |
| 3700 | tmp = (tmp & SDHC_EISTR_DATEND) >> SDHC_EISTR_DATEND_Pos; |
| 3701 | return (bool)tmp; |
| 3702 | } |
| 3703 | |
| 3704 | static inline void hri_sdhc_write_EISTR_DATEND_bit(const void *const hw, bool value) |
| 3705 | { |
| 3706 | uint16_t tmp; |
| 3707 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3708 | tmp = ((Sdhc *)hw)->EISTR.reg; |
| 3709 | tmp &= ~SDHC_EISTR_DATEND; |
| 3710 | tmp |= value << SDHC_EISTR_DATEND_Pos; |
| 3711 | ((Sdhc *)hw)->EISTR.reg = tmp; |
| 3712 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3713 | } |
| 3714 | |
| 3715 | static inline void hri_sdhc_clear_EISTR_DATEND_bit(const void *const hw) |
| 3716 | { |
| 3717 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3718 | ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATEND; |
| 3719 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3720 | } |
| 3721 | |
| 3722 | static inline void hri_sdhc_toggle_EISTR_DATEND_bit(const void *const hw) |
| 3723 | { |
| 3724 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3725 | ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATEND; |
| 3726 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3727 | } |
| 3728 | |
| 3729 | static inline void hri_sdhc_set_EISTR_CURLIM_bit(const void *const hw) |
| 3730 | { |
| 3731 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3732 | ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CURLIM; |
| 3733 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3734 | } |
| 3735 | |
| 3736 | static inline bool hri_sdhc_get_EISTR_CURLIM_bit(const void *const hw) |
| 3737 | { |
| 3738 | uint16_t tmp; |
| 3739 | tmp = ((Sdhc *)hw)->EISTR.reg; |
| 3740 | tmp = (tmp & SDHC_EISTR_CURLIM) >> SDHC_EISTR_CURLIM_Pos; |
| 3741 | return (bool)tmp; |
| 3742 | } |
| 3743 | |
| 3744 | static inline void hri_sdhc_write_EISTR_CURLIM_bit(const void *const hw, bool value) |
| 3745 | { |
| 3746 | uint16_t tmp; |
| 3747 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3748 | tmp = ((Sdhc *)hw)->EISTR.reg; |
| 3749 | tmp &= ~SDHC_EISTR_CURLIM; |
| 3750 | tmp |= value << SDHC_EISTR_CURLIM_Pos; |
| 3751 | ((Sdhc *)hw)->EISTR.reg = tmp; |
| 3752 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3753 | } |
| 3754 | |
| 3755 | static inline void hri_sdhc_clear_EISTR_CURLIM_bit(const void *const hw) |
| 3756 | { |
| 3757 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3758 | ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CURLIM; |
| 3759 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3760 | } |
| 3761 | |
| 3762 | static inline void hri_sdhc_toggle_EISTR_CURLIM_bit(const void *const hw) |
| 3763 | { |
| 3764 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3765 | ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CURLIM; |
| 3766 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3767 | } |
| 3768 | |
| 3769 | static inline void hri_sdhc_set_EISTR_ACMD_bit(const void *const hw) |
| 3770 | { |
| 3771 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3772 | ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_ACMD; |
| 3773 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3774 | } |
| 3775 | |
| 3776 | static inline bool hri_sdhc_get_EISTR_ACMD_bit(const void *const hw) |
| 3777 | { |
| 3778 | uint16_t tmp; |
| 3779 | tmp = ((Sdhc *)hw)->EISTR.reg; |
| 3780 | tmp = (tmp & SDHC_EISTR_ACMD) >> SDHC_EISTR_ACMD_Pos; |
| 3781 | return (bool)tmp; |
| 3782 | } |
| 3783 | |
| 3784 | static inline void hri_sdhc_write_EISTR_ACMD_bit(const void *const hw, bool value) |
| 3785 | { |
| 3786 | uint16_t tmp; |
| 3787 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3788 | tmp = ((Sdhc *)hw)->EISTR.reg; |
| 3789 | tmp &= ~SDHC_EISTR_ACMD; |
| 3790 | tmp |= value << SDHC_EISTR_ACMD_Pos; |
| 3791 | ((Sdhc *)hw)->EISTR.reg = tmp; |
| 3792 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3793 | } |
| 3794 | |
| 3795 | static inline void hri_sdhc_clear_EISTR_ACMD_bit(const void *const hw) |
| 3796 | { |
| 3797 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3798 | ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_ACMD; |
| 3799 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3800 | } |
| 3801 | |
| 3802 | static inline void hri_sdhc_toggle_EISTR_ACMD_bit(const void *const hw) |
| 3803 | { |
| 3804 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3805 | ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_ACMD; |
| 3806 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3807 | } |
| 3808 | |
| 3809 | static inline void hri_sdhc_set_EISTR_ADMA_bit(const void *const hw) |
| 3810 | { |
| 3811 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3812 | ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_ADMA; |
| 3813 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3814 | } |
| 3815 | |
| 3816 | static inline bool hri_sdhc_get_EISTR_ADMA_bit(const void *const hw) |
| 3817 | { |
| 3818 | uint16_t tmp; |
| 3819 | tmp = ((Sdhc *)hw)->EISTR.reg; |
| 3820 | tmp = (tmp & SDHC_EISTR_ADMA) >> SDHC_EISTR_ADMA_Pos; |
| 3821 | return (bool)tmp; |
| 3822 | } |
| 3823 | |
| 3824 | static inline void hri_sdhc_write_EISTR_ADMA_bit(const void *const hw, bool value) |
| 3825 | { |
| 3826 | uint16_t tmp; |
| 3827 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3828 | tmp = ((Sdhc *)hw)->EISTR.reg; |
| 3829 | tmp &= ~SDHC_EISTR_ADMA; |
| 3830 | tmp |= value << SDHC_EISTR_ADMA_Pos; |
| 3831 | ((Sdhc *)hw)->EISTR.reg = tmp; |
| 3832 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3833 | } |
| 3834 | |
| 3835 | static inline void hri_sdhc_clear_EISTR_ADMA_bit(const void *const hw) |
| 3836 | { |
| 3837 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3838 | ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_ADMA; |
| 3839 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3840 | } |
| 3841 | |
| 3842 | static inline void hri_sdhc_toggle_EISTR_ADMA_bit(const void *const hw) |
| 3843 | { |
| 3844 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3845 | ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_ADMA; |
| 3846 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3847 | } |
| 3848 | |
| 3849 | static inline void hri_sdhc_set_EISTR_EMMC_BOOTAE_bit(const void *const hw) |
| 3850 | { |
| 3851 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3852 | ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_BOOTAE; |
| 3853 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3854 | } |
| 3855 | |
| 3856 | static inline bool hri_sdhc_get_EISTR_EMMC_BOOTAE_bit(const void *const hw) |
| 3857 | { |
| 3858 | uint16_t tmp; |
| 3859 | tmp = ((Sdhc *)hw)->EISTR.reg; |
| 3860 | tmp = (tmp & SDHC_EISTR_EMMC_BOOTAE) >> SDHC_EISTR_EMMC_BOOTAE_Pos; |
| 3861 | return (bool)tmp; |
| 3862 | } |
| 3863 | |
| 3864 | static inline void hri_sdhc_write_EISTR_EMMC_BOOTAE_bit(const void *const hw, bool value) |
| 3865 | { |
| 3866 | uint16_t tmp; |
| 3867 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3868 | tmp = ((Sdhc *)hw)->EISTR.reg; |
| 3869 | tmp &= ~SDHC_EISTR_EMMC_BOOTAE; |
| 3870 | tmp |= value << SDHC_EISTR_EMMC_BOOTAE_Pos; |
| 3871 | ((Sdhc *)hw)->EISTR.reg = tmp; |
| 3872 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3873 | } |
| 3874 | |
| 3875 | static inline void hri_sdhc_clear_EISTR_EMMC_BOOTAE_bit(const void *const hw) |
| 3876 | { |
| 3877 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3878 | ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_BOOTAE; |
| 3879 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3880 | } |
| 3881 | |
| 3882 | static inline void hri_sdhc_toggle_EISTR_EMMC_BOOTAE_bit(const void *const hw) |
| 3883 | { |
| 3884 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3885 | ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_BOOTAE; |
| 3886 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3887 | } |
| 3888 | |
| 3889 | static inline void hri_sdhc_set_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) |
| 3890 | { |
| 3891 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3892 | ((Sdhc *)hw)->EISTR.reg |= mask; |
| 3893 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3894 | } |
| 3895 | |
| 3896 | static inline hri_sdhc_eistr_reg_t hri_sdhc_get_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) |
| 3897 | { |
| 3898 | uint16_t tmp; |
| 3899 | tmp = ((Sdhc *)hw)->EISTR.reg; |
| 3900 | tmp &= mask; |
| 3901 | return tmp; |
| 3902 | } |
| 3903 | |
| 3904 | static inline void hri_sdhc_write_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t data) |
| 3905 | { |
| 3906 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3907 | ((Sdhc *)hw)->EISTR.reg = data; |
| 3908 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3909 | } |
| 3910 | |
| 3911 | static inline void hri_sdhc_clear_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) |
| 3912 | { |
| 3913 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3914 | ((Sdhc *)hw)->EISTR.reg &= ~mask; |
| 3915 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3916 | } |
| 3917 | |
| 3918 | static inline void hri_sdhc_toggle_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) |
| 3919 | { |
| 3920 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3921 | ((Sdhc *)hw)->EISTR.reg ^= mask; |
| 3922 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3923 | } |
| 3924 | |
| 3925 | static inline hri_sdhc_eistr_reg_t hri_sdhc_read_EISTR_reg(const void *const hw) |
| 3926 | { |
| 3927 | return ((Sdhc *)hw)->EISTR.reg; |
| 3928 | } |
| 3929 | |
| 3930 | static inline void hri_sdhc_set_NISTER_CMDC_bit(const void *const hw) |
| 3931 | { |
| 3932 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3933 | ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CMDC; |
| 3934 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3935 | } |
| 3936 | |
| 3937 | static inline bool hri_sdhc_get_NISTER_CMDC_bit(const void *const hw) |
| 3938 | { |
| 3939 | uint16_t tmp; |
| 3940 | tmp = ((Sdhc *)hw)->NISTER.reg; |
| 3941 | tmp = (tmp & SDHC_NISTER_CMDC) >> SDHC_NISTER_CMDC_Pos; |
| 3942 | return (bool)tmp; |
| 3943 | } |
| 3944 | |
| 3945 | static inline void hri_sdhc_write_NISTER_CMDC_bit(const void *const hw, bool value) |
| 3946 | { |
| 3947 | uint16_t tmp; |
| 3948 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3949 | tmp = ((Sdhc *)hw)->NISTER.reg; |
| 3950 | tmp &= ~SDHC_NISTER_CMDC; |
| 3951 | tmp |= value << SDHC_NISTER_CMDC_Pos; |
| 3952 | ((Sdhc *)hw)->NISTER.reg = tmp; |
| 3953 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3954 | } |
| 3955 | |
| 3956 | static inline void hri_sdhc_clear_NISTER_CMDC_bit(const void *const hw) |
| 3957 | { |
| 3958 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3959 | ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CMDC; |
| 3960 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3961 | } |
| 3962 | |
| 3963 | static inline void hri_sdhc_toggle_NISTER_CMDC_bit(const void *const hw) |
| 3964 | { |
| 3965 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3966 | ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CMDC; |
| 3967 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3968 | } |
| 3969 | |
| 3970 | static inline void hri_sdhc_set_NISTER_TRFC_bit(const void *const hw) |
| 3971 | { |
| 3972 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3973 | ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_TRFC; |
| 3974 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3975 | } |
| 3976 | |
| 3977 | static inline bool hri_sdhc_get_NISTER_TRFC_bit(const void *const hw) |
| 3978 | { |
| 3979 | uint16_t tmp; |
| 3980 | tmp = ((Sdhc *)hw)->NISTER.reg; |
| 3981 | tmp = (tmp & SDHC_NISTER_TRFC) >> SDHC_NISTER_TRFC_Pos; |
| 3982 | return (bool)tmp; |
| 3983 | } |
| 3984 | |
| 3985 | static inline void hri_sdhc_write_NISTER_TRFC_bit(const void *const hw, bool value) |
| 3986 | { |
| 3987 | uint16_t tmp; |
| 3988 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3989 | tmp = ((Sdhc *)hw)->NISTER.reg; |
| 3990 | tmp &= ~SDHC_NISTER_TRFC; |
| 3991 | tmp |= value << SDHC_NISTER_TRFC_Pos; |
| 3992 | ((Sdhc *)hw)->NISTER.reg = tmp; |
| 3993 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 3994 | } |
| 3995 | |
| 3996 | static inline void hri_sdhc_clear_NISTER_TRFC_bit(const void *const hw) |
| 3997 | { |
| 3998 | SDHC_CRITICAL_SECTION_ENTER(); |
| 3999 | ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_TRFC; |
| 4000 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4001 | } |
| 4002 | |
| 4003 | static inline void hri_sdhc_toggle_NISTER_TRFC_bit(const void *const hw) |
| 4004 | { |
| 4005 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4006 | ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_TRFC; |
| 4007 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4008 | } |
| 4009 | |
| 4010 | static inline void hri_sdhc_set_NISTER_BLKGE_bit(const void *const hw) |
| 4011 | { |
| 4012 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4013 | ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BLKGE; |
| 4014 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4015 | } |
| 4016 | |
| 4017 | static inline bool hri_sdhc_get_NISTER_BLKGE_bit(const void *const hw) |
| 4018 | { |
| 4019 | uint16_t tmp; |
| 4020 | tmp = ((Sdhc *)hw)->NISTER.reg; |
| 4021 | tmp = (tmp & SDHC_NISTER_BLKGE) >> SDHC_NISTER_BLKGE_Pos; |
| 4022 | return (bool)tmp; |
| 4023 | } |
| 4024 | |
| 4025 | static inline void hri_sdhc_write_NISTER_BLKGE_bit(const void *const hw, bool value) |
| 4026 | { |
| 4027 | uint16_t tmp; |
| 4028 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4029 | tmp = ((Sdhc *)hw)->NISTER.reg; |
| 4030 | tmp &= ~SDHC_NISTER_BLKGE; |
| 4031 | tmp |= value << SDHC_NISTER_BLKGE_Pos; |
| 4032 | ((Sdhc *)hw)->NISTER.reg = tmp; |
| 4033 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4034 | } |
| 4035 | |
| 4036 | static inline void hri_sdhc_clear_NISTER_BLKGE_bit(const void *const hw) |
| 4037 | { |
| 4038 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4039 | ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BLKGE; |
| 4040 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4041 | } |
| 4042 | |
| 4043 | static inline void hri_sdhc_toggle_NISTER_BLKGE_bit(const void *const hw) |
| 4044 | { |
| 4045 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4046 | ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BLKGE; |
| 4047 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4048 | } |
| 4049 | |
| 4050 | static inline void hri_sdhc_set_NISTER_DMAINT_bit(const void *const hw) |
| 4051 | { |
| 4052 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4053 | ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_DMAINT; |
| 4054 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4055 | } |
| 4056 | |
| 4057 | static inline bool hri_sdhc_get_NISTER_DMAINT_bit(const void *const hw) |
| 4058 | { |
| 4059 | uint16_t tmp; |
| 4060 | tmp = ((Sdhc *)hw)->NISTER.reg; |
| 4061 | tmp = (tmp & SDHC_NISTER_DMAINT) >> SDHC_NISTER_DMAINT_Pos; |
| 4062 | return (bool)tmp; |
| 4063 | } |
| 4064 | |
| 4065 | static inline void hri_sdhc_write_NISTER_DMAINT_bit(const void *const hw, bool value) |
| 4066 | { |
| 4067 | uint16_t tmp; |
| 4068 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4069 | tmp = ((Sdhc *)hw)->NISTER.reg; |
| 4070 | tmp &= ~SDHC_NISTER_DMAINT; |
| 4071 | tmp |= value << SDHC_NISTER_DMAINT_Pos; |
| 4072 | ((Sdhc *)hw)->NISTER.reg = tmp; |
| 4073 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4074 | } |
| 4075 | |
| 4076 | static inline void hri_sdhc_clear_NISTER_DMAINT_bit(const void *const hw) |
| 4077 | { |
| 4078 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4079 | ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_DMAINT; |
| 4080 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4081 | } |
| 4082 | |
| 4083 | static inline void hri_sdhc_toggle_NISTER_DMAINT_bit(const void *const hw) |
| 4084 | { |
| 4085 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4086 | ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_DMAINT; |
| 4087 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4088 | } |
| 4089 | |
| 4090 | static inline void hri_sdhc_set_NISTER_BWRRDY_bit(const void *const hw) |
| 4091 | { |
| 4092 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4093 | ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BWRRDY; |
| 4094 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4095 | } |
| 4096 | |
| 4097 | static inline bool hri_sdhc_get_NISTER_BWRRDY_bit(const void *const hw) |
| 4098 | { |
| 4099 | uint16_t tmp; |
| 4100 | tmp = ((Sdhc *)hw)->NISTER.reg; |
| 4101 | tmp = (tmp & SDHC_NISTER_BWRRDY) >> SDHC_NISTER_BWRRDY_Pos; |
| 4102 | return (bool)tmp; |
| 4103 | } |
| 4104 | |
| 4105 | static inline void hri_sdhc_write_NISTER_BWRRDY_bit(const void *const hw, bool value) |
| 4106 | { |
| 4107 | uint16_t tmp; |
| 4108 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4109 | tmp = ((Sdhc *)hw)->NISTER.reg; |
| 4110 | tmp &= ~SDHC_NISTER_BWRRDY; |
| 4111 | tmp |= value << SDHC_NISTER_BWRRDY_Pos; |
| 4112 | ((Sdhc *)hw)->NISTER.reg = tmp; |
| 4113 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4114 | } |
| 4115 | |
| 4116 | static inline void hri_sdhc_clear_NISTER_BWRRDY_bit(const void *const hw) |
| 4117 | { |
| 4118 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4119 | ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BWRRDY; |
| 4120 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4121 | } |
| 4122 | |
| 4123 | static inline void hri_sdhc_toggle_NISTER_BWRRDY_bit(const void *const hw) |
| 4124 | { |
| 4125 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4126 | ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BWRRDY; |
| 4127 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4128 | } |
| 4129 | |
| 4130 | static inline void hri_sdhc_set_NISTER_BRDRDY_bit(const void *const hw) |
| 4131 | { |
| 4132 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4133 | ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BRDRDY; |
| 4134 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4135 | } |
| 4136 | |
| 4137 | static inline bool hri_sdhc_get_NISTER_BRDRDY_bit(const void *const hw) |
| 4138 | { |
| 4139 | uint16_t tmp; |
| 4140 | tmp = ((Sdhc *)hw)->NISTER.reg; |
| 4141 | tmp = (tmp & SDHC_NISTER_BRDRDY) >> SDHC_NISTER_BRDRDY_Pos; |
| 4142 | return (bool)tmp; |
| 4143 | } |
| 4144 | |
| 4145 | static inline void hri_sdhc_write_NISTER_BRDRDY_bit(const void *const hw, bool value) |
| 4146 | { |
| 4147 | uint16_t tmp; |
| 4148 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4149 | tmp = ((Sdhc *)hw)->NISTER.reg; |
| 4150 | tmp &= ~SDHC_NISTER_BRDRDY; |
| 4151 | tmp |= value << SDHC_NISTER_BRDRDY_Pos; |
| 4152 | ((Sdhc *)hw)->NISTER.reg = tmp; |
| 4153 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4154 | } |
| 4155 | |
| 4156 | static inline void hri_sdhc_clear_NISTER_BRDRDY_bit(const void *const hw) |
| 4157 | { |
| 4158 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4159 | ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BRDRDY; |
| 4160 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4161 | } |
| 4162 | |
| 4163 | static inline void hri_sdhc_toggle_NISTER_BRDRDY_bit(const void *const hw) |
| 4164 | { |
| 4165 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4166 | ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BRDRDY; |
| 4167 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4168 | } |
| 4169 | |
| 4170 | static inline void hri_sdhc_set_NISTER_CINS_bit(const void *const hw) |
| 4171 | { |
| 4172 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4173 | ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CINS; |
| 4174 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4175 | } |
| 4176 | |
| 4177 | static inline bool hri_sdhc_get_NISTER_CINS_bit(const void *const hw) |
| 4178 | { |
| 4179 | uint16_t tmp; |
| 4180 | tmp = ((Sdhc *)hw)->NISTER.reg; |
| 4181 | tmp = (tmp & SDHC_NISTER_CINS) >> SDHC_NISTER_CINS_Pos; |
| 4182 | return (bool)tmp; |
| 4183 | } |
| 4184 | |
| 4185 | static inline void hri_sdhc_write_NISTER_CINS_bit(const void *const hw, bool value) |
| 4186 | { |
| 4187 | uint16_t tmp; |
| 4188 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4189 | tmp = ((Sdhc *)hw)->NISTER.reg; |
| 4190 | tmp &= ~SDHC_NISTER_CINS; |
| 4191 | tmp |= value << SDHC_NISTER_CINS_Pos; |
| 4192 | ((Sdhc *)hw)->NISTER.reg = tmp; |
| 4193 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4194 | } |
| 4195 | |
| 4196 | static inline void hri_sdhc_clear_NISTER_CINS_bit(const void *const hw) |
| 4197 | { |
| 4198 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4199 | ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CINS; |
| 4200 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4201 | } |
| 4202 | |
| 4203 | static inline void hri_sdhc_toggle_NISTER_CINS_bit(const void *const hw) |
| 4204 | { |
| 4205 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4206 | ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CINS; |
| 4207 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4208 | } |
| 4209 | |
| 4210 | static inline void hri_sdhc_set_NISTER_CREM_bit(const void *const hw) |
| 4211 | { |
| 4212 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4213 | ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CREM; |
| 4214 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4215 | } |
| 4216 | |
| 4217 | static inline bool hri_sdhc_get_NISTER_CREM_bit(const void *const hw) |
| 4218 | { |
| 4219 | uint16_t tmp; |
| 4220 | tmp = ((Sdhc *)hw)->NISTER.reg; |
| 4221 | tmp = (tmp & SDHC_NISTER_CREM) >> SDHC_NISTER_CREM_Pos; |
| 4222 | return (bool)tmp; |
| 4223 | } |
| 4224 | |
| 4225 | static inline void hri_sdhc_write_NISTER_CREM_bit(const void *const hw, bool value) |
| 4226 | { |
| 4227 | uint16_t tmp; |
| 4228 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4229 | tmp = ((Sdhc *)hw)->NISTER.reg; |
| 4230 | tmp &= ~SDHC_NISTER_CREM; |
| 4231 | tmp |= value << SDHC_NISTER_CREM_Pos; |
| 4232 | ((Sdhc *)hw)->NISTER.reg = tmp; |
| 4233 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4234 | } |
| 4235 | |
| 4236 | static inline void hri_sdhc_clear_NISTER_CREM_bit(const void *const hw) |
| 4237 | { |
| 4238 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4239 | ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CREM; |
| 4240 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4241 | } |
| 4242 | |
| 4243 | static inline void hri_sdhc_toggle_NISTER_CREM_bit(const void *const hw) |
| 4244 | { |
| 4245 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4246 | ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CREM; |
| 4247 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4248 | } |
| 4249 | |
| 4250 | static inline void hri_sdhc_set_NISTER_CINT_bit(const void *const hw) |
| 4251 | { |
| 4252 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4253 | ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CINT; |
| 4254 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4255 | } |
| 4256 | |
| 4257 | static inline bool hri_sdhc_get_NISTER_CINT_bit(const void *const hw) |
| 4258 | { |
| 4259 | uint16_t tmp; |
| 4260 | tmp = ((Sdhc *)hw)->NISTER.reg; |
| 4261 | tmp = (tmp & SDHC_NISTER_CINT) >> SDHC_NISTER_CINT_Pos; |
| 4262 | return (bool)tmp; |
| 4263 | } |
| 4264 | |
| 4265 | static inline void hri_sdhc_write_NISTER_CINT_bit(const void *const hw, bool value) |
| 4266 | { |
| 4267 | uint16_t tmp; |
| 4268 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4269 | tmp = ((Sdhc *)hw)->NISTER.reg; |
| 4270 | tmp &= ~SDHC_NISTER_CINT; |
| 4271 | tmp |= value << SDHC_NISTER_CINT_Pos; |
| 4272 | ((Sdhc *)hw)->NISTER.reg = tmp; |
| 4273 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4274 | } |
| 4275 | |
| 4276 | static inline void hri_sdhc_clear_NISTER_CINT_bit(const void *const hw) |
| 4277 | { |
| 4278 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4279 | ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CINT; |
| 4280 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4281 | } |
| 4282 | |
| 4283 | static inline void hri_sdhc_toggle_NISTER_CINT_bit(const void *const hw) |
| 4284 | { |
| 4285 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4286 | ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CINT; |
| 4287 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4288 | } |
| 4289 | |
| 4290 | static inline void hri_sdhc_set_NISTER_EMMC_BOOTAR_bit(const void *const hw) |
| 4291 | { |
| 4292 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4293 | ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_EMMC_BOOTAR; |
| 4294 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4295 | } |
| 4296 | |
| 4297 | static inline bool hri_sdhc_get_NISTER_EMMC_BOOTAR_bit(const void *const hw) |
| 4298 | { |
| 4299 | uint16_t tmp; |
| 4300 | tmp = ((Sdhc *)hw)->NISTER.reg; |
| 4301 | tmp = (tmp & SDHC_NISTER_EMMC_BOOTAR) >> SDHC_NISTER_EMMC_BOOTAR_Pos; |
| 4302 | return (bool)tmp; |
| 4303 | } |
| 4304 | |
| 4305 | static inline void hri_sdhc_write_NISTER_EMMC_BOOTAR_bit(const void *const hw, bool value) |
| 4306 | { |
| 4307 | uint16_t tmp; |
| 4308 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4309 | tmp = ((Sdhc *)hw)->NISTER.reg; |
| 4310 | tmp &= ~SDHC_NISTER_EMMC_BOOTAR; |
| 4311 | tmp |= value << SDHC_NISTER_EMMC_BOOTAR_Pos; |
| 4312 | ((Sdhc *)hw)->NISTER.reg = tmp; |
| 4313 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4314 | } |
| 4315 | |
| 4316 | static inline void hri_sdhc_clear_NISTER_EMMC_BOOTAR_bit(const void *const hw) |
| 4317 | { |
| 4318 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4319 | ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_EMMC_BOOTAR; |
| 4320 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4321 | } |
| 4322 | |
| 4323 | static inline void hri_sdhc_toggle_NISTER_EMMC_BOOTAR_bit(const void *const hw) |
| 4324 | { |
| 4325 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4326 | ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_EMMC_BOOTAR; |
| 4327 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4328 | } |
| 4329 | |
| 4330 | static inline void hri_sdhc_set_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) |
| 4331 | { |
| 4332 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4333 | ((Sdhc *)hw)->NISTER.reg |= mask; |
| 4334 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4335 | } |
| 4336 | |
| 4337 | static inline hri_sdhc_nister_reg_t hri_sdhc_get_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) |
| 4338 | { |
| 4339 | uint16_t tmp; |
| 4340 | tmp = ((Sdhc *)hw)->NISTER.reg; |
| 4341 | tmp &= mask; |
| 4342 | return tmp; |
| 4343 | } |
| 4344 | |
| 4345 | static inline void hri_sdhc_write_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t data) |
| 4346 | { |
| 4347 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4348 | ((Sdhc *)hw)->NISTER.reg = data; |
| 4349 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4350 | } |
| 4351 | |
| 4352 | static inline void hri_sdhc_clear_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) |
| 4353 | { |
| 4354 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4355 | ((Sdhc *)hw)->NISTER.reg &= ~mask; |
| 4356 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4357 | } |
| 4358 | |
| 4359 | static inline void hri_sdhc_toggle_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) |
| 4360 | { |
| 4361 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4362 | ((Sdhc *)hw)->NISTER.reg ^= mask; |
| 4363 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4364 | } |
| 4365 | |
| 4366 | static inline hri_sdhc_nister_reg_t hri_sdhc_read_NISTER_reg(const void *const hw) |
| 4367 | { |
| 4368 | return ((Sdhc *)hw)->NISTER.reg; |
| 4369 | } |
| 4370 | |
| 4371 | static inline void hri_sdhc_set_EISTER_CMDTEO_bit(const void *const hw) |
| 4372 | { |
| 4373 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4374 | ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDTEO; |
| 4375 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4376 | } |
| 4377 | |
| 4378 | static inline bool hri_sdhc_get_EISTER_CMDTEO_bit(const void *const hw) |
| 4379 | { |
| 4380 | uint16_t tmp; |
| 4381 | tmp = ((Sdhc *)hw)->EISTER.reg; |
| 4382 | tmp = (tmp & SDHC_EISTER_CMDTEO) >> SDHC_EISTER_CMDTEO_Pos; |
| 4383 | return (bool)tmp; |
| 4384 | } |
| 4385 | |
| 4386 | static inline void hri_sdhc_write_EISTER_CMDTEO_bit(const void *const hw, bool value) |
| 4387 | { |
| 4388 | uint16_t tmp; |
| 4389 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4390 | tmp = ((Sdhc *)hw)->EISTER.reg; |
| 4391 | tmp &= ~SDHC_EISTER_CMDTEO; |
| 4392 | tmp |= value << SDHC_EISTER_CMDTEO_Pos; |
| 4393 | ((Sdhc *)hw)->EISTER.reg = tmp; |
| 4394 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4395 | } |
| 4396 | |
| 4397 | static inline void hri_sdhc_clear_EISTER_CMDTEO_bit(const void *const hw) |
| 4398 | { |
| 4399 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4400 | ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDTEO; |
| 4401 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4402 | } |
| 4403 | |
| 4404 | static inline void hri_sdhc_toggle_EISTER_CMDTEO_bit(const void *const hw) |
| 4405 | { |
| 4406 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4407 | ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDTEO; |
| 4408 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4409 | } |
| 4410 | |
| 4411 | static inline void hri_sdhc_set_EISTER_CMDCRC_bit(const void *const hw) |
| 4412 | { |
| 4413 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4414 | ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDCRC; |
| 4415 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4416 | } |
| 4417 | |
| 4418 | static inline bool hri_sdhc_get_EISTER_CMDCRC_bit(const void *const hw) |
| 4419 | { |
| 4420 | uint16_t tmp; |
| 4421 | tmp = ((Sdhc *)hw)->EISTER.reg; |
| 4422 | tmp = (tmp & SDHC_EISTER_CMDCRC) >> SDHC_EISTER_CMDCRC_Pos; |
| 4423 | return (bool)tmp; |
| 4424 | } |
| 4425 | |
| 4426 | static inline void hri_sdhc_write_EISTER_CMDCRC_bit(const void *const hw, bool value) |
| 4427 | { |
| 4428 | uint16_t tmp; |
| 4429 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4430 | tmp = ((Sdhc *)hw)->EISTER.reg; |
| 4431 | tmp &= ~SDHC_EISTER_CMDCRC; |
| 4432 | tmp |= value << SDHC_EISTER_CMDCRC_Pos; |
| 4433 | ((Sdhc *)hw)->EISTER.reg = tmp; |
| 4434 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4435 | } |
| 4436 | |
| 4437 | static inline void hri_sdhc_clear_EISTER_CMDCRC_bit(const void *const hw) |
| 4438 | { |
| 4439 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4440 | ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDCRC; |
| 4441 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4442 | } |
| 4443 | |
| 4444 | static inline void hri_sdhc_toggle_EISTER_CMDCRC_bit(const void *const hw) |
| 4445 | { |
| 4446 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4447 | ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDCRC; |
| 4448 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4449 | } |
| 4450 | |
| 4451 | static inline void hri_sdhc_set_EISTER_CMDEND_bit(const void *const hw) |
| 4452 | { |
| 4453 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4454 | ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDEND; |
| 4455 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4456 | } |
| 4457 | |
| 4458 | static inline bool hri_sdhc_get_EISTER_CMDEND_bit(const void *const hw) |
| 4459 | { |
| 4460 | uint16_t tmp; |
| 4461 | tmp = ((Sdhc *)hw)->EISTER.reg; |
| 4462 | tmp = (tmp & SDHC_EISTER_CMDEND) >> SDHC_EISTER_CMDEND_Pos; |
| 4463 | return (bool)tmp; |
| 4464 | } |
| 4465 | |
| 4466 | static inline void hri_sdhc_write_EISTER_CMDEND_bit(const void *const hw, bool value) |
| 4467 | { |
| 4468 | uint16_t tmp; |
| 4469 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4470 | tmp = ((Sdhc *)hw)->EISTER.reg; |
| 4471 | tmp &= ~SDHC_EISTER_CMDEND; |
| 4472 | tmp |= value << SDHC_EISTER_CMDEND_Pos; |
| 4473 | ((Sdhc *)hw)->EISTER.reg = tmp; |
| 4474 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4475 | } |
| 4476 | |
| 4477 | static inline void hri_sdhc_clear_EISTER_CMDEND_bit(const void *const hw) |
| 4478 | { |
| 4479 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4480 | ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDEND; |
| 4481 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4482 | } |
| 4483 | |
| 4484 | static inline void hri_sdhc_toggle_EISTER_CMDEND_bit(const void *const hw) |
| 4485 | { |
| 4486 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4487 | ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDEND; |
| 4488 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4489 | } |
| 4490 | |
| 4491 | static inline void hri_sdhc_set_EISTER_CMDIDX_bit(const void *const hw) |
| 4492 | { |
| 4493 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4494 | ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDIDX; |
| 4495 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4496 | } |
| 4497 | |
| 4498 | static inline bool hri_sdhc_get_EISTER_CMDIDX_bit(const void *const hw) |
| 4499 | { |
| 4500 | uint16_t tmp; |
| 4501 | tmp = ((Sdhc *)hw)->EISTER.reg; |
| 4502 | tmp = (tmp & SDHC_EISTER_CMDIDX) >> SDHC_EISTER_CMDIDX_Pos; |
| 4503 | return (bool)tmp; |
| 4504 | } |
| 4505 | |
| 4506 | static inline void hri_sdhc_write_EISTER_CMDIDX_bit(const void *const hw, bool value) |
| 4507 | { |
| 4508 | uint16_t tmp; |
| 4509 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4510 | tmp = ((Sdhc *)hw)->EISTER.reg; |
| 4511 | tmp &= ~SDHC_EISTER_CMDIDX; |
| 4512 | tmp |= value << SDHC_EISTER_CMDIDX_Pos; |
| 4513 | ((Sdhc *)hw)->EISTER.reg = tmp; |
| 4514 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4515 | } |
| 4516 | |
| 4517 | static inline void hri_sdhc_clear_EISTER_CMDIDX_bit(const void *const hw) |
| 4518 | { |
| 4519 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4520 | ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDIDX; |
| 4521 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4522 | } |
| 4523 | |
| 4524 | static inline void hri_sdhc_toggle_EISTER_CMDIDX_bit(const void *const hw) |
| 4525 | { |
| 4526 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4527 | ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDIDX; |
| 4528 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4529 | } |
| 4530 | |
| 4531 | static inline void hri_sdhc_set_EISTER_DATTEO_bit(const void *const hw) |
| 4532 | { |
| 4533 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4534 | ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATTEO; |
| 4535 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4536 | } |
| 4537 | |
| 4538 | static inline bool hri_sdhc_get_EISTER_DATTEO_bit(const void *const hw) |
| 4539 | { |
| 4540 | uint16_t tmp; |
| 4541 | tmp = ((Sdhc *)hw)->EISTER.reg; |
| 4542 | tmp = (tmp & SDHC_EISTER_DATTEO) >> SDHC_EISTER_DATTEO_Pos; |
| 4543 | return (bool)tmp; |
| 4544 | } |
| 4545 | |
| 4546 | static inline void hri_sdhc_write_EISTER_DATTEO_bit(const void *const hw, bool value) |
| 4547 | { |
| 4548 | uint16_t tmp; |
| 4549 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4550 | tmp = ((Sdhc *)hw)->EISTER.reg; |
| 4551 | tmp &= ~SDHC_EISTER_DATTEO; |
| 4552 | tmp |= value << SDHC_EISTER_DATTEO_Pos; |
| 4553 | ((Sdhc *)hw)->EISTER.reg = tmp; |
| 4554 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4555 | } |
| 4556 | |
| 4557 | static inline void hri_sdhc_clear_EISTER_DATTEO_bit(const void *const hw) |
| 4558 | { |
| 4559 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4560 | ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATTEO; |
| 4561 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4562 | } |
| 4563 | |
| 4564 | static inline void hri_sdhc_toggle_EISTER_DATTEO_bit(const void *const hw) |
| 4565 | { |
| 4566 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4567 | ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATTEO; |
| 4568 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4569 | } |
| 4570 | |
| 4571 | static inline void hri_sdhc_set_EISTER_DATCRC_bit(const void *const hw) |
| 4572 | { |
| 4573 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4574 | ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATCRC; |
| 4575 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4576 | } |
| 4577 | |
| 4578 | static inline bool hri_sdhc_get_EISTER_DATCRC_bit(const void *const hw) |
| 4579 | { |
| 4580 | uint16_t tmp; |
| 4581 | tmp = ((Sdhc *)hw)->EISTER.reg; |
| 4582 | tmp = (tmp & SDHC_EISTER_DATCRC) >> SDHC_EISTER_DATCRC_Pos; |
| 4583 | return (bool)tmp; |
| 4584 | } |
| 4585 | |
| 4586 | static inline void hri_sdhc_write_EISTER_DATCRC_bit(const void *const hw, bool value) |
| 4587 | { |
| 4588 | uint16_t tmp; |
| 4589 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4590 | tmp = ((Sdhc *)hw)->EISTER.reg; |
| 4591 | tmp &= ~SDHC_EISTER_DATCRC; |
| 4592 | tmp |= value << SDHC_EISTER_DATCRC_Pos; |
| 4593 | ((Sdhc *)hw)->EISTER.reg = tmp; |
| 4594 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4595 | } |
| 4596 | |
| 4597 | static inline void hri_sdhc_clear_EISTER_DATCRC_bit(const void *const hw) |
| 4598 | { |
| 4599 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4600 | ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATCRC; |
| 4601 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4602 | } |
| 4603 | |
| 4604 | static inline void hri_sdhc_toggle_EISTER_DATCRC_bit(const void *const hw) |
| 4605 | { |
| 4606 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4607 | ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATCRC; |
| 4608 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4609 | } |
| 4610 | |
| 4611 | static inline void hri_sdhc_set_EISTER_DATEND_bit(const void *const hw) |
| 4612 | { |
| 4613 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4614 | ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATEND; |
| 4615 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4616 | } |
| 4617 | |
| 4618 | static inline bool hri_sdhc_get_EISTER_DATEND_bit(const void *const hw) |
| 4619 | { |
| 4620 | uint16_t tmp; |
| 4621 | tmp = ((Sdhc *)hw)->EISTER.reg; |
| 4622 | tmp = (tmp & SDHC_EISTER_DATEND) >> SDHC_EISTER_DATEND_Pos; |
| 4623 | return (bool)tmp; |
| 4624 | } |
| 4625 | |
| 4626 | static inline void hri_sdhc_write_EISTER_DATEND_bit(const void *const hw, bool value) |
| 4627 | { |
| 4628 | uint16_t tmp; |
| 4629 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4630 | tmp = ((Sdhc *)hw)->EISTER.reg; |
| 4631 | tmp &= ~SDHC_EISTER_DATEND; |
| 4632 | tmp |= value << SDHC_EISTER_DATEND_Pos; |
| 4633 | ((Sdhc *)hw)->EISTER.reg = tmp; |
| 4634 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4635 | } |
| 4636 | |
| 4637 | static inline void hri_sdhc_clear_EISTER_DATEND_bit(const void *const hw) |
| 4638 | { |
| 4639 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4640 | ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATEND; |
| 4641 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4642 | } |
| 4643 | |
| 4644 | static inline void hri_sdhc_toggle_EISTER_DATEND_bit(const void *const hw) |
| 4645 | { |
| 4646 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4647 | ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATEND; |
| 4648 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4649 | } |
| 4650 | |
| 4651 | static inline void hri_sdhc_set_EISTER_CURLIM_bit(const void *const hw) |
| 4652 | { |
| 4653 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4654 | ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CURLIM; |
| 4655 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4656 | } |
| 4657 | |
| 4658 | static inline bool hri_sdhc_get_EISTER_CURLIM_bit(const void *const hw) |
| 4659 | { |
| 4660 | uint16_t tmp; |
| 4661 | tmp = ((Sdhc *)hw)->EISTER.reg; |
| 4662 | tmp = (tmp & SDHC_EISTER_CURLIM) >> SDHC_EISTER_CURLIM_Pos; |
| 4663 | return (bool)tmp; |
| 4664 | } |
| 4665 | |
| 4666 | static inline void hri_sdhc_write_EISTER_CURLIM_bit(const void *const hw, bool value) |
| 4667 | { |
| 4668 | uint16_t tmp; |
| 4669 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4670 | tmp = ((Sdhc *)hw)->EISTER.reg; |
| 4671 | tmp &= ~SDHC_EISTER_CURLIM; |
| 4672 | tmp |= value << SDHC_EISTER_CURLIM_Pos; |
| 4673 | ((Sdhc *)hw)->EISTER.reg = tmp; |
| 4674 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4675 | } |
| 4676 | |
| 4677 | static inline void hri_sdhc_clear_EISTER_CURLIM_bit(const void *const hw) |
| 4678 | { |
| 4679 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4680 | ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CURLIM; |
| 4681 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4682 | } |
| 4683 | |
| 4684 | static inline void hri_sdhc_toggle_EISTER_CURLIM_bit(const void *const hw) |
| 4685 | { |
| 4686 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4687 | ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CURLIM; |
| 4688 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4689 | } |
| 4690 | |
| 4691 | static inline void hri_sdhc_set_EISTER_ACMD_bit(const void *const hw) |
| 4692 | { |
| 4693 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4694 | ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_ACMD; |
| 4695 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4696 | } |
| 4697 | |
| 4698 | static inline bool hri_sdhc_get_EISTER_ACMD_bit(const void *const hw) |
| 4699 | { |
| 4700 | uint16_t tmp; |
| 4701 | tmp = ((Sdhc *)hw)->EISTER.reg; |
| 4702 | tmp = (tmp & SDHC_EISTER_ACMD) >> SDHC_EISTER_ACMD_Pos; |
| 4703 | return (bool)tmp; |
| 4704 | } |
| 4705 | |
| 4706 | static inline void hri_sdhc_write_EISTER_ACMD_bit(const void *const hw, bool value) |
| 4707 | { |
| 4708 | uint16_t tmp; |
| 4709 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4710 | tmp = ((Sdhc *)hw)->EISTER.reg; |
| 4711 | tmp &= ~SDHC_EISTER_ACMD; |
| 4712 | tmp |= value << SDHC_EISTER_ACMD_Pos; |
| 4713 | ((Sdhc *)hw)->EISTER.reg = tmp; |
| 4714 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4715 | } |
| 4716 | |
| 4717 | static inline void hri_sdhc_clear_EISTER_ACMD_bit(const void *const hw) |
| 4718 | { |
| 4719 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4720 | ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_ACMD; |
| 4721 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4722 | } |
| 4723 | |
| 4724 | static inline void hri_sdhc_toggle_EISTER_ACMD_bit(const void *const hw) |
| 4725 | { |
| 4726 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4727 | ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_ACMD; |
| 4728 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4729 | } |
| 4730 | |
| 4731 | static inline void hri_sdhc_set_EISTER_ADMA_bit(const void *const hw) |
| 4732 | { |
| 4733 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4734 | ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_ADMA; |
| 4735 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4736 | } |
| 4737 | |
| 4738 | static inline bool hri_sdhc_get_EISTER_ADMA_bit(const void *const hw) |
| 4739 | { |
| 4740 | uint16_t tmp; |
| 4741 | tmp = ((Sdhc *)hw)->EISTER.reg; |
| 4742 | tmp = (tmp & SDHC_EISTER_ADMA) >> SDHC_EISTER_ADMA_Pos; |
| 4743 | return (bool)tmp; |
| 4744 | } |
| 4745 | |
| 4746 | static inline void hri_sdhc_write_EISTER_ADMA_bit(const void *const hw, bool value) |
| 4747 | { |
| 4748 | uint16_t tmp; |
| 4749 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4750 | tmp = ((Sdhc *)hw)->EISTER.reg; |
| 4751 | tmp &= ~SDHC_EISTER_ADMA; |
| 4752 | tmp |= value << SDHC_EISTER_ADMA_Pos; |
| 4753 | ((Sdhc *)hw)->EISTER.reg = tmp; |
| 4754 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4755 | } |
| 4756 | |
| 4757 | static inline void hri_sdhc_clear_EISTER_ADMA_bit(const void *const hw) |
| 4758 | { |
| 4759 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4760 | ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_ADMA; |
| 4761 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4762 | } |
| 4763 | |
| 4764 | static inline void hri_sdhc_toggle_EISTER_ADMA_bit(const void *const hw) |
| 4765 | { |
| 4766 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4767 | ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_ADMA; |
| 4768 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4769 | } |
| 4770 | |
| 4771 | static inline void hri_sdhc_set_EISTER_EMMC_BOOTAE_bit(const void *const hw) |
| 4772 | { |
| 4773 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4774 | ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_BOOTAE; |
| 4775 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4776 | } |
| 4777 | |
| 4778 | static inline bool hri_sdhc_get_EISTER_EMMC_BOOTAE_bit(const void *const hw) |
| 4779 | { |
| 4780 | uint16_t tmp; |
| 4781 | tmp = ((Sdhc *)hw)->EISTER.reg; |
| 4782 | tmp = (tmp & SDHC_EISTER_EMMC_BOOTAE) >> SDHC_EISTER_EMMC_BOOTAE_Pos; |
| 4783 | return (bool)tmp; |
| 4784 | } |
| 4785 | |
| 4786 | static inline void hri_sdhc_write_EISTER_EMMC_BOOTAE_bit(const void *const hw, bool value) |
| 4787 | { |
| 4788 | uint16_t tmp; |
| 4789 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4790 | tmp = ((Sdhc *)hw)->EISTER.reg; |
| 4791 | tmp &= ~SDHC_EISTER_EMMC_BOOTAE; |
| 4792 | tmp |= value << SDHC_EISTER_EMMC_BOOTAE_Pos; |
| 4793 | ((Sdhc *)hw)->EISTER.reg = tmp; |
| 4794 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4795 | } |
| 4796 | |
| 4797 | static inline void hri_sdhc_clear_EISTER_EMMC_BOOTAE_bit(const void *const hw) |
| 4798 | { |
| 4799 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4800 | ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_BOOTAE; |
| 4801 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4802 | } |
| 4803 | |
| 4804 | static inline void hri_sdhc_toggle_EISTER_EMMC_BOOTAE_bit(const void *const hw) |
| 4805 | { |
| 4806 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4807 | ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_BOOTAE; |
| 4808 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4809 | } |
| 4810 | |
| 4811 | static inline void hri_sdhc_set_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) |
| 4812 | { |
| 4813 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4814 | ((Sdhc *)hw)->EISTER.reg |= mask; |
| 4815 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4816 | } |
| 4817 | |
| 4818 | static inline hri_sdhc_eister_reg_t hri_sdhc_get_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) |
| 4819 | { |
| 4820 | uint16_t tmp; |
| 4821 | tmp = ((Sdhc *)hw)->EISTER.reg; |
| 4822 | tmp &= mask; |
| 4823 | return tmp; |
| 4824 | } |
| 4825 | |
| 4826 | static inline void hri_sdhc_write_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t data) |
| 4827 | { |
| 4828 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4829 | ((Sdhc *)hw)->EISTER.reg = data; |
| 4830 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4831 | } |
| 4832 | |
| 4833 | static inline void hri_sdhc_clear_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) |
| 4834 | { |
| 4835 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4836 | ((Sdhc *)hw)->EISTER.reg &= ~mask; |
| 4837 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4838 | } |
| 4839 | |
| 4840 | static inline void hri_sdhc_toggle_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) |
| 4841 | { |
| 4842 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4843 | ((Sdhc *)hw)->EISTER.reg ^= mask; |
| 4844 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4845 | } |
| 4846 | |
| 4847 | static inline hri_sdhc_eister_reg_t hri_sdhc_read_EISTER_reg(const void *const hw) |
| 4848 | { |
| 4849 | return ((Sdhc *)hw)->EISTER.reg; |
| 4850 | } |
| 4851 | |
| 4852 | static inline void hri_sdhc_set_NISIER_CMDC_bit(const void *const hw) |
| 4853 | { |
| 4854 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4855 | ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CMDC; |
| 4856 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4857 | } |
| 4858 | |
| 4859 | static inline bool hri_sdhc_get_NISIER_CMDC_bit(const void *const hw) |
| 4860 | { |
| 4861 | uint16_t tmp; |
| 4862 | tmp = ((Sdhc *)hw)->NISIER.reg; |
| 4863 | tmp = (tmp & SDHC_NISIER_CMDC) >> SDHC_NISIER_CMDC_Pos; |
| 4864 | return (bool)tmp; |
| 4865 | } |
| 4866 | |
| 4867 | static inline void hri_sdhc_write_NISIER_CMDC_bit(const void *const hw, bool value) |
| 4868 | { |
| 4869 | uint16_t tmp; |
| 4870 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4871 | tmp = ((Sdhc *)hw)->NISIER.reg; |
| 4872 | tmp &= ~SDHC_NISIER_CMDC; |
| 4873 | tmp |= value << SDHC_NISIER_CMDC_Pos; |
| 4874 | ((Sdhc *)hw)->NISIER.reg = tmp; |
| 4875 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4876 | } |
| 4877 | |
| 4878 | static inline void hri_sdhc_clear_NISIER_CMDC_bit(const void *const hw) |
| 4879 | { |
| 4880 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4881 | ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CMDC; |
| 4882 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4883 | } |
| 4884 | |
| 4885 | static inline void hri_sdhc_toggle_NISIER_CMDC_bit(const void *const hw) |
| 4886 | { |
| 4887 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4888 | ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CMDC; |
| 4889 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4890 | } |
| 4891 | |
| 4892 | static inline void hri_sdhc_set_NISIER_TRFC_bit(const void *const hw) |
| 4893 | { |
| 4894 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4895 | ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_TRFC; |
| 4896 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4897 | } |
| 4898 | |
| 4899 | static inline bool hri_sdhc_get_NISIER_TRFC_bit(const void *const hw) |
| 4900 | { |
| 4901 | uint16_t tmp; |
| 4902 | tmp = ((Sdhc *)hw)->NISIER.reg; |
| 4903 | tmp = (tmp & SDHC_NISIER_TRFC) >> SDHC_NISIER_TRFC_Pos; |
| 4904 | return (bool)tmp; |
| 4905 | } |
| 4906 | |
| 4907 | static inline void hri_sdhc_write_NISIER_TRFC_bit(const void *const hw, bool value) |
| 4908 | { |
| 4909 | uint16_t tmp; |
| 4910 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4911 | tmp = ((Sdhc *)hw)->NISIER.reg; |
| 4912 | tmp &= ~SDHC_NISIER_TRFC; |
| 4913 | tmp |= value << SDHC_NISIER_TRFC_Pos; |
| 4914 | ((Sdhc *)hw)->NISIER.reg = tmp; |
| 4915 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4916 | } |
| 4917 | |
| 4918 | static inline void hri_sdhc_clear_NISIER_TRFC_bit(const void *const hw) |
| 4919 | { |
| 4920 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4921 | ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_TRFC; |
| 4922 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4923 | } |
| 4924 | |
| 4925 | static inline void hri_sdhc_toggle_NISIER_TRFC_bit(const void *const hw) |
| 4926 | { |
| 4927 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4928 | ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_TRFC; |
| 4929 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4930 | } |
| 4931 | |
| 4932 | static inline void hri_sdhc_set_NISIER_BLKGE_bit(const void *const hw) |
| 4933 | { |
| 4934 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4935 | ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BLKGE; |
| 4936 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4937 | } |
| 4938 | |
| 4939 | static inline bool hri_sdhc_get_NISIER_BLKGE_bit(const void *const hw) |
| 4940 | { |
| 4941 | uint16_t tmp; |
| 4942 | tmp = ((Sdhc *)hw)->NISIER.reg; |
| 4943 | tmp = (tmp & SDHC_NISIER_BLKGE) >> SDHC_NISIER_BLKGE_Pos; |
| 4944 | return (bool)tmp; |
| 4945 | } |
| 4946 | |
| 4947 | static inline void hri_sdhc_write_NISIER_BLKGE_bit(const void *const hw, bool value) |
| 4948 | { |
| 4949 | uint16_t tmp; |
| 4950 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4951 | tmp = ((Sdhc *)hw)->NISIER.reg; |
| 4952 | tmp &= ~SDHC_NISIER_BLKGE; |
| 4953 | tmp |= value << SDHC_NISIER_BLKGE_Pos; |
| 4954 | ((Sdhc *)hw)->NISIER.reg = tmp; |
| 4955 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4956 | } |
| 4957 | |
| 4958 | static inline void hri_sdhc_clear_NISIER_BLKGE_bit(const void *const hw) |
| 4959 | { |
| 4960 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4961 | ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BLKGE; |
| 4962 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4963 | } |
| 4964 | |
| 4965 | static inline void hri_sdhc_toggle_NISIER_BLKGE_bit(const void *const hw) |
| 4966 | { |
| 4967 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4968 | ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BLKGE; |
| 4969 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4970 | } |
| 4971 | |
| 4972 | static inline void hri_sdhc_set_NISIER_DMAINT_bit(const void *const hw) |
| 4973 | { |
| 4974 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4975 | ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_DMAINT; |
| 4976 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4977 | } |
| 4978 | |
| 4979 | static inline bool hri_sdhc_get_NISIER_DMAINT_bit(const void *const hw) |
| 4980 | { |
| 4981 | uint16_t tmp; |
| 4982 | tmp = ((Sdhc *)hw)->NISIER.reg; |
| 4983 | tmp = (tmp & SDHC_NISIER_DMAINT) >> SDHC_NISIER_DMAINT_Pos; |
| 4984 | return (bool)tmp; |
| 4985 | } |
| 4986 | |
| 4987 | static inline void hri_sdhc_write_NISIER_DMAINT_bit(const void *const hw, bool value) |
| 4988 | { |
| 4989 | uint16_t tmp; |
| 4990 | SDHC_CRITICAL_SECTION_ENTER(); |
| 4991 | tmp = ((Sdhc *)hw)->NISIER.reg; |
| 4992 | tmp &= ~SDHC_NISIER_DMAINT; |
| 4993 | tmp |= value << SDHC_NISIER_DMAINT_Pos; |
| 4994 | ((Sdhc *)hw)->NISIER.reg = tmp; |
| 4995 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 4996 | } |
| 4997 | |
| 4998 | static inline void hri_sdhc_clear_NISIER_DMAINT_bit(const void *const hw) |
| 4999 | { |
| 5000 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5001 | ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_DMAINT; |
| 5002 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5003 | } |
| 5004 | |
| 5005 | static inline void hri_sdhc_toggle_NISIER_DMAINT_bit(const void *const hw) |
| 5006 | { |
| 5007 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5008 | ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_DMAINT; |
| 5009 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5010 | } |
| 5011 | |
| 5012 | static inline void hri_sdhc_set_NISIER_BWRRDY_bit(const void *const hw) |
| 5013 | { |
| 5014 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5015 | ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BWRRDY; |
| 5016 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5017 | } |
| 5018 | |
| 5019 | static inline bool hri_sdhc_get_NISIER_BWRRDY_bit(const void *const hw) |
| 5020 | { |
| 5021 | uint16_t tmp; |
| 5022 | tmp = ((Sdhc *)hw)->NISIER.reg; |
| 5023 | tmp = (tmp & SDHC_NISIER_BWRRDY) >> SDHC_NISIER_BWRRDY_Pos; |
| 5024 | return (bool)tmp; |
| 5025 | } |
| 5026 | |
| 5027 | static inline void hri_sdhc_write_NISIER_BWRRDY_bit(const void *const hw, bool value) |
| 5028 | { |
| 5029 | uint16_t tmp; |
| 5030 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5031 | tmp = ((Sdhc *)hw)->NISIER.reg; |
| 5032 | tmp &= ~SDHC_NISIER_BWRRDY; |
| 5033 | tmp |= value << SDHC_NISIER_BWRRDY_Pos; |
| 5034 | ((Sdhc *)hw)->NISIER.reg = tmp; |
| 5035 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5036 | } |
| 5037 | |
| 5038 | static inline void hri_sdhc_clear_NISIER_BWRRDY_bit(const void *const hw) |
| 5039 | { |
| 5040 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5041 | ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BWRRDY; |
| 5042 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5043 | } |
| 5044 | |
| 5045 | static inline void hri_sdhc_toggle_NISIER_BWRRDY_bit(const void *const hw) |
| 5046 | { |
| 5047 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5048 | ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BWRRDY; |
| 5049 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5050 | } |
| 5051 | |
| 5052 | static inline void hri_sdhc_set_NISIER_BRDRDY_bit(const void *const hw) |
| 5053 | { |
| 5054 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5055 | ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BRDRDY; |
| 5056 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5057 | } |
| 5058 | |
| 5059 | static inline bool hri_sdhc_get_NISIER_BRDRDY_bit(const void *const hw) |
| 5060 | { |
| 5061 | uint16_t tmp; |
| 5062 | tmp = ((Sdhc *)hw)->NISIER.reg; |
| 5063 | tmp = (tmp & SDHC_NISIER_BRDRDY) >> SDHC_NISIER_BRDRDY_Pos; |
| 5064 | return (bool)tmp; |
| 5065 | } |
| 5066 | |
| 5067 | static inline void hri_sdhc_write_NISIER_BRDRDY_bit(const void *const hw, bool value) |
| 5068 | { |
| 5069 | uint16_t tmp; |
| 5070 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5071 | tmp = ((Sdhc *)hw)->NISIER.reg; |
| 5072 | tmp &= ~SDHC_NISIER_BRDRDY; |
| 5073 | tmp |= value << SDHC_NISIER_BRDRDY_Pos; |
| 5074 | ((Sdhc *)hw)->NISIER.reg = tmp; |
| 5075 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5076 | } |
| 5077 | |
| 5078 | static inline void hri_sdhc_clear_NISIER_BRDRDY_bit(const void *const hw) |
| 5079 | { |
| 5080 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5081 | ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BRDRDY; |
| 5082 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5083 | } |
| 5084 | |
| 5085 | static inline void hri_sdhc_toggle_NISIER_BRDRDY_bit(const void *const hw) |
| 5086 | { |
| 5087 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5088 | ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BRDRDY; |
| 5089 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5090 | } |
| 5091 | |
| 5092 | static inline void hri_sdhc_set_NISIER_CINS_bit(const void *const hw) |
| 5093 | { |
| 5094 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5095 | ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CINS; |
| 5096 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5097 | } |
| 5098 | |
| 5099 | static inline bool hri_sdhc_get_NISIER_CINS_bit(const void *const hw) |
| 5100 | { |
| 5101 | uint16_t tmp; |
| 5102 | tmp = ((Sdhc *)hw)->NISIER.reg; |
| 5103 | tmp = (tmp & SDHC_NISIER_CINS) >> SDHC_NISIER_CINS_Pos; |
| 5104 | return (bool)tmp; |
| 5105 | } |
| 5106 | |
| 5107 | static inline void hri_sdhc_write_NISIER_CINS_bit(const void *const hw, bool value) |
| 5108 | { |
| 5109 | uint16_t tmp; |
| 5110 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5111 | tmp = ((Sdhc *)hw)->NISIER.reg; |
| 5112 | tmp &= ~SDHC_NISIER_CINS; |
| 5113 | tmp |= value << SDHC_NISIER_CINS_Pos; |
| 5114 | ((Sdhc *)hw)->NISIER.reg = tmp; |
| 5115 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5116 | } |
| 5117 | |
| 5118 | static inline void hri_sdhc_clear_NISIER_CINS_bit(const void *const hw) |
| 5119 | { |
| 5120 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5121 | ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CINS; |
| 5122 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5123 | } |
| 5124 | |
| 5125 | static inline void hri_sdhc_toggle_NISIER_CINS_bit(const void *const hw) |
| 5126 | { |
| 5127 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5128 | ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CINS; |
| 5129 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5130 | } |
| 5131 | |
| 5132 | static inline void hri_sdhc_set_NISIER_CREM_bit(const void *const hw) |
| 5133 | { |
| 5134 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5135 | ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CREM; |
| 5136 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5137 | } |
| 5138 | |
| 5139 | static inline bool hri_sdhc_get_NISIER_CREM_bit(const void *const hw) |
| 5140 | { |
| 5141 | uint16_t tmp; |
| 5142 | tmp = ((Sdhc *)hw)->NISIER.reg; |
| 5143 | tmp = (tmp & SDHC_NISIER_CREM) >> SDHC_NISIER_CREM_Pos; |
| 5144 | return (bool)tmp; |
| 5145 | } |
| 5146 | |
| 5147 | static inline void hri_sdhc_write_NISIER_CREM_bit(const void *const hw, bool value) |
| 5148 | { |
| 5149 | uint16_t tmp; |
| 5150 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5151 | tmp = ((Sdhc *)hw)->NISIER.reg; |
| 5152 | tmp &= ~SDHC_NISIER_CREM; |
| 5153 | tmp |= value << SDHC_NISIER_CREM_Pos; |
| 5154 | ((Sdhc *)hw)->NISIER.reg = tmp; |
| 5155 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5156 | } |
| 5157 | |
| 5158 | static inline void hri_sdhc_clear_NISIER_CREM_bit(const void *const hw) |
| 5159 | { |
| 5160 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5161 | ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CREM; |
| 5162 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5163 | } |
| 5164 | |
| 5165 | static inline void hri_sdhc_toggle_NISIER_CREM_bit(const void *const hw) |
| 5166 | { |
| 5167 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5168 | ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CREM; |
| 5169 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5170 | } |
| 5171 | |
| 5172 | static inline void hri_sdhc_set_NISIER_CINT_bit(const void *const hw) |
| 5173 | { |
| 5174 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5175 | ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CINT; |
| 5176 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5177 | } |
| 5178 | |
| 5179 | static inline bool hri_sdhc_get_NISIER_CINT_bit(const void *const hw) |
| 5180 | { |
| 5181 | uint16_t tmp; |
| 5182 | tmp = ((Sdhc *)hw)->NISIER.reg; |
| 5183 | tmp = (tmp & SDHC_NISIER_CINT) >> SDHC_NISIER_CINT_Pos; |
| 5184 | return (bool)tmp; |
| 5185 | } |
| 5186 | |
| 5187 | static inline void hri_sdhc_write_NISIER_CINT_bit(const void *const hw, bool value) |
| 5188 | { |
| 5189 | uint16_t tmp; |
| 5190 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5191 | tmp = ((Sdhc *)hw)->NISIER.reg; |
| 5192 | tmp &= ~SDHC_NISIER_CINT; |
| 5193 | tmp |= value << SDHC_NISIER_CINT_Pos; |
| 5194 | ((Sdhc *)hw)->NISIER.reg = tmp; |
| 5195 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5196 | } |
| 5197 | |
| 5198 | static inline void hri_sdhc_clear_NISIER_CINT_bit(const void *const hw) |
| 5199 | { |
| 5200 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5201 | ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CINT; |
| 5202 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5203 | } |
| 5204 | |
| 5205 | static inline void hri_sdhc_toggle_NISIER_CINT_bit(const void *const hw) |
| 5206 | { |
| 5207 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5208 | ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CINT; |
| 5209 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5210 | } |
| 5211 | |
| 5212 | static inline void hri_sdhc_set_NISIER_EMMC_BOOTAR_bit(const void *const hw) |
| 5213 | { |
| 5214 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5215 | ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_EMMC_BOOTAR; |
| 5216 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5217 | } |
| 5218 | |
| 5219 | static inline bool hri_sdhc_get_NISIER_EMMC_BOOTAR_bit(const void *const hw) |
| 5220 | { |
| 5221 | uint16_t tmp; |
| 5222 | tmp = ((Sdhc *)hw)->NISIER.reg; |
| 5223 | tmp = (tmp & SDHC_NISIER_EMMC_BOOTAR) >> SDHC_NISIER_EMMC_BOOTAR_Pos; |
| 5224 | return (bool)tmp; |
| 5225 | } |
| 5226 | |
| 5227 | static inline void hri_sdhc_write_NISIER_EMMC_BOOTAR_bit(const void *const hw, bool value) |
| 5228 | { |
| 5229 | uint16_t tmp; |
| 5230 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5231 | tmp = ((Sdhc *)hw)->NISIER.reg; |
| 5232 | tmp &= ~SDHC_NISIER_EMMC_BOOTAR; |
| 5233 | tmp |= value << SDHC_NISIER_EMMC_BOOTAR_Pos; |
| 5234 | ((Sdhc *)hw)->NISIER.reg = tmp; |
| 5235 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5236 | } |
| 5237 | |
| 5238 | static inline void hri_sdhc_clear_NISIER_EMMC_BOOTAR_bit(const void *const hw) |
| 5239 | { |
| 5240 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5241 | ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_EMMC_BOOTAR; |
| 5242 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5243 | } |
| 5244 | |
| 5245 | static inline void hri_sdhc_toggle_NISIER_EMMC_BOOTAR_bit(const void *const hw) |
| 5246 | { |
| 5247 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5248 | ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_EMMC_BOOTAR; |
| 5249 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5250 | } |
| 5251 | |
| 5252 | static inline void hri_sdhc_set_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) |
| 5253 | { |
| 5254 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5255 | ((Sdhc *)hw)->NISIER.reg |= mask; |
| 5256 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5257 | } |
| 5258 | |
| 5259 | static inline hri_sdhc_nisier_reg_t hri_sdhc_get_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) |
| 5260 | { |
| 5261 | uint16_t tmp; |
| 5262 | tmp = ((Sdhc *)hw)->NISIER.reg; |
| 5263 | tmp &= mask; |
| 5264 | return tmp; |
| 5265 | } |
| 5266 | |
| 5267 | static inline void hri_sdhc_write_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t data) |
| 5268 | { |
| 5269 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5270 | ((Sdhc *)hw)->NISIER.reg = data; |
| 5271 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5272 | } |
| 5273 | |
| 5274 | static inline void hri_sdhc_clear_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) |
| 5275 | { |
| 5276 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5277 | ((Sdhc *)hw)->NISIER.reg &= ~mask; |
| 5278 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5279 | } |
| 5280 | |
| 5281 | static inline void hri_sdhc_toggle_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) |
| 5282 | { |
| 5283 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5284 | ((Sdhc *)hw)->NISIER.reg ^= mask; |
| 5285 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5286 | } |
| 5287 | |
| 5288 | static inline hri_sdhc_nisier_reg_t hri_sdhc_read_NISIER_reg(const void *const hw) |
| 5289 | { |
| 5290 | return ((Sdhc *)hw)->NISIER.reg; |
| 5291 | } |
| 5292 | |
| 5293 | static inline void hri_sdhc_set_EISIER_CMDTEO_bit(const void *const hw) |
| 5294 | { |
| 5295 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5296 | ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDTEO; |
| 5297 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5298 | } |
| 5299 | |
| 5300 | static inline bool hri_sdhc_get_EISIER_CMDTEO_bit(const void *const hw) |
| 5301 | { |
| 5302 | uint16_t tmp; |
| 5303 | tmp = ((Sdhc *)hw)->EISIER.reg; |
| 5304 | tmp = (tmp & SDHC_EISIER_CMDTEO) >> SDHC_EISIER_CMDTEO_Pos; |
| 5305 | return (bool)tmp; |
| 5306 | } |
| 5307 | |
| 5308 | static inline void hri_sdhc_write_EISIER_CMDTEO_bit(const void *const hw, bool value) |
| 5309 | { |
| 5310 | uint16_t tmp; |
| 5311 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5312 | tmp = ((Sdhc *)hw)->EISIER.reg; |
| 5313 | tmp &= ~SDHC_EISIER_CMDTEO; |
| 5314 | tmp |= value << SDHC_EISIER_CMDTEO_Pos; |
| 5315 | ((Sdhc *)hw)->EISIER.reg = tmp; |
| 5316 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5317 | } |
| 5318 | |
| 5319 | static inline void hri_sdhc_clear_EISIER_CMDTEO_bit(const void *const hw) |
| 5320 | { |
| 5321 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5322 | ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDTEO; |
| 5323 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5324 | } |
| 5325 | |
| 5326 | static inline void hri_sdhc_toggle_EISIER_CMDTEO_bit(const void *const hw) |
| 5327 | { |
| 5328 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5329 | ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDTEO; |
| 5330 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5331 | } |
| 5332 | |
| 5333 | static inline void hri_sdhc_set_EISIER_CMDCRC_bit(const void *const hw) |
| 5334 | { |
| 5335 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5336 | ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDCRC; |
| 5337 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5338 | } |
| 5339 | |
| 5340 | static inline bool hri_sdhc_get_EISIER_CMDCRC_bit(const void *const hw) |
| 5341 | { |
| 5342 | uint16_t tmp; |
| 5343 | tmp = ((Sdhc *)hw)->EISIER.reg; |
| 5344 | tmp = (tmp & SDHC_EISIER_CMDCRC) >> SDHC_EISIER_CMDCRC_Pos; |
| 5345 | return (bool)tmp; |
| 5346 | } |
| 5347 | |
| 5348 | static inline void hri_sdhc_write_EISIER_CMDCRC_bit(const void *const hw, bool value) |
| 5349 | { |
| 5350 | uint16_t tmp; |
| 5351 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5352 | tmp = ((Sdhc *)hw)->EISIER.reg; |
| 5353 | tmp &= ~SDHC_EISIER_CMDCRC; |
| 5354 | tmp |= value << SDHC_EISIER_CMDCRC_Pos; |
| 5355 | ((Sdhc *)hw)->EISIER.reg = tmp; |
| 5356 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5357 | } |
| 5358 | |
| 5359 | static inline void hri_sdhc_clear_EISIER_CMDCRC_bit(const void *const hw) |
| 5360 | { |
| 5361 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5362 | ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDCRC; |
| 5363 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5364 | } |
| 5365 | |
| 5366 | static inline void hri_sdhc_toggle_EISIER_CMDCRC_bit(const void *const hw) |
| 5367 | { |
| 5368 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5369 | ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDCRC; |
| 5370 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5371 | } |
| 5372 | |
| 5373 | static inline void hri_sdhc_set_EISIER_CMDEND_bit(const void *const hw) |
| 5374 | { |
| 5375 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5376 | ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDEND; |
| 5377 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5378 | } |
| 5379 | |
| 5380 | static inline bool hri_sdhc_get_EISIER_CMDEND_bit(const void *const hw) |
| 5381 | { |
| 5382 | uint16_t tmp; |
| 5383 | tmp = ((Sdhc *)hw)->EISIER.reg; |
| 5384 | tmp = (tmp & SDHC_EISIER_CMDEND) >> SDHC_EISIER_CMDEND_Pos; |
| 5385 | return (bool)tmp; |
| 5386 | } |
| 5387 | |
| 5388 | static inline void hri_sdhc_write_EISIER_CMDEND_bit(const void *const hw, bool value) |
| 5389 | { |
| 5390 | uint16_t tmp; |
| 5391 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5392 | tmp = ((Sdhc *)hw)->EISIER.reg; |
| 5393 | tmp &= ~SDHC_EISIER_CMDEND; |
| 5394 | tmp |= value << SDHC_EISIER_CMDEND_Pos; |
| 5395 | ((Sdhc *)hw)->EISIER.reg = tmp; |
| 5396 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5397 | } |
| 5398 | |
| 5399 | static inline void hri_sdhc_clear_EISIER_CMDEND_bit(const void *const hw) |
| 5400 | { |
| 5401 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5402 | ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDEND; |
| 5403 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5404 | } |
| 5405 | |
| 5406 | static inline void hri_sdhc_toggle_EISIER_CMDEND_bit(const void *const hw) |
| 5407 | { |
| 5408 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5409 | ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDEND; |
| 5410 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5411 | } |
| 5412 | |
| 5413 | static inline void hri_sdhc_set_EISIER_CMDIDX_bit(const void *const hw) |
| 5414 | { |
| 5415 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5416 | ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDIDX; |
| 5417 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5418 | } |
| 5419 | |
| 5420 | static inline bool hri_sdhc_get_EISIER_CMDIDX_bit(const void *const hw) |
| 5421 | { |
| 5422 | uint16_t tmp; |
| 5423 | tmp = ((Sdhc *)hw)->EISIER.reg; |
| 5424 | tmp = (tmp & SDHC_EISIER_CMDIDX) >> SDHC_EISIER_CMDIDX_Pos; |
| 5425 | return (bool)tmp; |
| 5426 | } |
| 5427 | |
| 5428 | static inline void hri_sdhc_write_EISIER_CMDIDX_bit(const void *const hw, bool value) |
| 5429 | { |
| 5430 | uint16_t tmp; |
| 5431 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5432 | tmp = ((Sdhc *)hw)->EISIER.reg; |
| 5433 | tmp &= ~SDHC_EISIER_CMDIDX; |
| 5434 | tmp |= value << SDHC_EISIER_CMDIDX_Pos; |
| 5435 | ((Sdhc *)hw)->EISIER.reg = tmp; |
| 5436 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5437 | } |
| 5438 | |
| 5439 | static inline void hri_sdhc_clear_EISIER_CMDIDX_bit(const void *const hw) |
| 5440 | { |
| 5441 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5442 | ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDIDX; |
| 5443 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5444 | } |
| 5445 | |
| 5446 | static inline void hri_sdhc_toggle_EISIER_CMDIDX_bit(const void *const hw) |
| 5447 | { |
| 5448 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5449 | ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDIDX; |
| 5450 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5451 | } |
| 5452 | |
| 5453 | static inline void hri_sdhc_set_EISIER_DATTEO_bit(const void *const hw) |
| 5454 | { |
| 5455 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5456 | ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATTEO; |
| 5457 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5458 | } |
| 5459 | |
| 5460 | static inline bool hri_sdhc_get_EISIER_DATTEO_bit(const void *const hw) |
| 5461 | { |
| 5462 | uint16_t tmp; |
| 5463 | tmp = ((Sdhc *)hw)->EISIER.reg; |
| 5464 | tmp = (tmp & SDHC_EISIER_DATTEO) >> SDHC_EISIER_DATTEO_Pos; |
| 5465 | return (bool)tmp; |
| 5466 | } |
| 5467 | |
| 5468 | static inline void hri_sdhc_write_EISIER_DATTEO_bit(const void *const hw, bool value) |
| 5469 | { |
| 5470 | uint16_t tmp; |
| 5471 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5472 | tmp = ((Sdhc *)hw)->EISIER.reg; |
| 5473 | tmp &= ~SDHC_EISIER_DATTEO; |
| 5474 | tmp |= value << SDHC_EISIER_DATTEO_Pos; |
| 5475 | ((Sdhc *)hw)->EISIER.reg = tmp; |
| 5476 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5477 | } |
| 5478 | |
| 5479 | static inline void hri_sdhc_clear_EISIER_DATTEO_bit(const void *const hw) |
| 5480 | { |
| 5481 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5482 | ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATTEO; |
| 5483 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5484 | } |
| 5485 | |
| 5486 | static inline void hri_sdhc_toggle_EISIER_DATTEO_bit(const void *const hw) |
| 5487 | { |
| 5488 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5489 | ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATTEO; |
| 5490 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5491 | } |
| 5492 | |
| 5493 | static inline void hri_sdhc_set_EISIER_DATCRC_bit(const void *const hw) |
| 5494 | { |
| 5495 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5496 | ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATCRC; |
| 5497 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5498 | } |
| 5499 | |
| 5500 | static inline bool hri_sdhc_get_EISIER_DATCRC_bit(const void *const hw) |
| 5501 | { |
| 5502 | uint16_t tmp; |
| 5503 | tmp = ((Sdhc *)hw)->EISIER.reg; |
| 5504 | tmp = (tmp & SDHC_EISIER_DATCRC) >> SDHC_EISIER_DATCRC_Pos; |
| 5505 | return (bool)tmp; |
| 5506 | } |
| 5507 | |
| 5508 | static inline void hri_sdhc_write_EISIER_DATCRC_bit(const void *const hw, bool value) |
| 5509 | { |
| 5510 | uint16_t tmp; |
| 5511 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5512 | tmp = ((Sdhc *)hw)->EISIER.reg; |
| 5513 | tmp &= ~SDHC_EISIER_DATCRC; |
| 5514 | tmp |= value << SDHC_EISIER_DATCRC_Pos; |
| 5515 | ((Sdhc *)hw)->EISIER.reg = tmp; |
| 5516 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5517 | } |
| 5518 | |
| 5519 | static inline void hri_sdhc_clear_EISIER_DATCRC_bit(const void *const hw) |
| 5520 | { |
| 5521 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5522 | ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATCRC; |
| 5523 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5524 | } |
| 5525 | |
| 5526 | static inline void hri_sdhc_toggle_EISIER_DATCRC_bit(const void *const hw) |
| 5527 | { |
| 5528 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5529 | ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATCRC; |
| 5530 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5531 | } |
| 5532 | |
| 5533 | static inline void hri_sdhc_set_EISIER_DATEND_bit(const void *const hw) |
| 5534 | { |
| 5535 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5536 | ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATEND; |
| 5537 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5538 | } |
| 5539 | |
| 5540 | static inline bool hri_sdhc_get_EISIER_DATEND_bit(const void *const hw) |
| 5541 | { |
| 5542 | uint16_t tmp; |
| 5543 | tmp = ((Sdhc *)hw)->EISIER.reg; |
| 5544 | tmp = (tmp & SDHC_EISIER_DATEND) >> SDHC_EISIER_DATEND_Pos; |
| 5545 | return (bool)tmp; |
| 5546 | } |
| 5547 | |
| 5548 | static inline void hri_sdhc_write_EISIER_DATEND_bit(const void *const hw, bool value) |
| 5549 | { |
| 5550 | uint16_t tmp; |
| 5551 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5552 | tmp = ((Sdhc *)hw)->EISIER.reg; |
| 5553 | tmp &= ~SDHC_EISIER_DATEND; |
| 5554 | tmp |= value << SDHC_EISIER_DATEND_Pos; |
| 5555 | ((Sdhc *)hw)->EISIER.reg = tmp; |
| 5556 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5557 | } |
| 5558 | |
| 5559 | static inline void hri_sdhc_clear_EISIER_DATEND_bit(const void *const hw) |
| 5560 | { |
| 5561 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5562 | ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATEND; |
| 5563 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5564 | } |
| 5565 | |
| 5566 | static inline void hri_sdhc_toggle_EISIER_DATEND_bit(const void *const hw) |
| 5567 | { |
| 5568 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5569 | ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATEND; |
| 5570 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5571 | } |
| 5572 | |
| 5573 | static inline void hri_sdhc_set_EISIER_CURLIM_bit(const void *const hw) |
| 5574 | { |
| 5575 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5576 | ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CURLIM; |
| 5577 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5578 | } |
| 5579 | |
| 5580 | static inline bool hri_sdhc_get_EISIER_CURLIM_bit(const void *const hw) |
| 5581 | { |
| 5582 | uint16_t tmp; |
| 5583 | tmp = ((Sdhc *)hw)->EISIER.reg; |
| 5584 | tmp = (tmp & SDHC_EISIER_CURLIM) >> SDHC_EISIER_CURLIM_Pos; |
| 5585 | return (bool)tmp; |
| 5586 | } |
| 5587 | |
| 5588 | static inline void hri_sdhc_write_EISIER_CURLIM_bit(const void *const hw, bool value) |
| 5589 | { |
| 5590 | uint16_t tmp; |
| 5591 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5592 | tmp = ((Sdhc *)hw)->EISIER.reg; |
| 5593 | tmp &= ~SDHC_EISIER_CURLIM; |
| 5594 | tmp |= value << SDHC_EISIER_CURLIM_Pos; |
| 5595 | ((Sdhc *)hw)->EISIER.reg = tmp; |
| 5596 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5597 | } |
| 5598 | |
| 5599 | static inline void hri_sdhc_clear_EISIER_CURLIM_bit(const void *const hw) |
| 5600 | { |
| 5601 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5602 | ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CURLIM; |
| 5603 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5604 | } |
| 5605 | |
| 5606 | static inline void hri_sdhc_toggle_EISIER_CURLIM_bit(const void *const hw) |
| 5607 | { |
| 5608 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5609 | ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CURLIM; |
| 5610 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5611 | } |
| 5612 | |
| 5613 | static inline void hri_sdhc_set_EISIER_ACMD_bit(const void *const hw) |
| 5614 | { |
| 5615 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5616 | ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_ACMD; |
| 5617 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5618 | } |
| 5619 | |
| 5620 | static inline bool hri_sdhc_get_EISIER_ACMD_bit(const void *const hw) |
| 5621 | { |
| 5622 | uint16_t tmp; |
| 5623 | tmp = ((Sdhc *)hw)->EISIER.reg; |
| 5624 | tmp = (tmp & SDHC_EISIER_ACMD) >> SDHC_EISIER_ACMD_Pos; |
| 5625 | return (bool)tmp; |
| 5626 | } |
| 5627 | |
| 5628 | static inline void hri_sdhc_write_EISIER_ACMD_bit(const void *const hw, bool value) |
| 5629 | { |
| 5630 | uint16_t tmp; |
| 5631 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5632 | tmp = ((Sdhc *)hw)->EISIER.reg; |
| 5633 | tmp &= ~SDHC_EISIER_ACMD; |
| 5634 | tmp |= value << SDHC_EISIER_ACMD_Pos; |
| 5635 | ((Sdhc *)hw)->EISIER.reg = tmp; |
| 5636 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5637 | } |
| 5638 | |
| 5639 | static inline void hri_sdhc_clear_EISIER_ACMD_bit(const void *const hw) |
| 5640 | { |
| 5641 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5642 | ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_ACMD; |
| 5643 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5644 | } |
| 5645 | |
| 5646 | static inline void hri_sdhc_toggle_EISIER_ACMD_bit(const void *const hw) |
| 5647 | { |
| 5648 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5649 | ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_ACMD; |
| 5650 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5651 | } |
| 5652 | |
| 5653 | static inline void hri_sdhc_set_EISIER_ADMA_bit(const void *const hw) |
| 5654 | { |
| 5655 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5656 | ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_ADMA; |
| 5657 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5658 | } |
| 5659 | |
| 5660 | static inline bool hri_sdhc_get_EISIER_ADMA_bit(const void *const hw) |
| 5661 | { |
| 5662 | uint16_t tmp; |
| 5663 | tmp = ((Sdhc *)hw)->EISIER.reg; |
| 5664 | tmp = (tmp & SDHC_EISIER_ADMA) >> SDHC_EISIER_ADMA_Pos; |
| 5665 | return (bool)tmp; |
| 5666 | } |
| 5667 | |
| 5668 | static inline void hri_sdhc_write_EISIER_ADMA_bit(const void *const hw, bool value) |
| 5669 | { |
| 5670 | uint16_t tmp; |
| 5671 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5672 | tmp = ((Sdhc *)hw)->EISIER.reg; |
| 5673 | tmp &= ~SDHC_EISIER_ADMA; |
| 5674 | tmp |= value << SDHC_EISIER_ADMA_Pos; |
| 5675 | ((Sdhc *)hw)->EISIER.reg = tmp; |
| 5676 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5677 | } |
| 5678 | |
| 5679 | static inline void hri_sdhc_clear_EISIER_ADMA_bit(const void *const hw) |
| 5680 | { |
| 5681 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5682 | ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_ADMA; |
| 5683 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5684 | } |
| 5685 | |
| 5686 | static inline void hri_sdhc_toggle_EISIER_ADMA_bit(const void *const hw) |
| 5687 | { |
| 5688 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5689 | ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_ADMA; |
| 5690 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5691 | } |
| 5692 | |
| 5693 | static inline void hri_sdhc_set_EISIER_EMMC_BOOTAE_bit(const void *const hw) |
| 5694 | { |
| 5695 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5696 | ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_BOOTAE; |
| 5697 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5698 | } |
| 5699 | |
| 5700 | static inline bool hri_sdhc_get_EISIER_EMMC_BOOTAE_bit(const void *const hw) |
| 5701 | { |
| 5702 | uint16_t tmp; |
| 5703 | tmp = ((Sdhc *)hw)->EISIER.reg; |
| 5704 | tmp = (tmp & SDHC_EISIER_EMMC_BOOTAE) >> SDHC_EISIER_EMMC_BOOTAE_Pos; |
| 5705 | return (bool)tmp; |
| 5706 | } |
| 5707 | |
| 5708 | static inline void hri_sdhc_write_EISIER_EMMC_BOOTAE_bit(const void *const hw, bool value) |
| 5709 | { |
| 5710 | uint16_t tmp; |
| 5711 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5712 | tmp = ((Sdhc *)hw)->EISIER.reg; |
| 5713 | tmp &= ~SDHC_EISIER_EMMC_BOOTAE; |
| 5714 | tmp |= value << SDHC_EISIER_EMMC_BOOTAE_Pos; |
| 5715 | ((Sdhc *)hw)->EISIER.reg = tmp; |
| 5716 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5717 | } |
| 5718 | |
| 5719 | static inline void hri_sdhc_clear_EISIER_EMMC_BOOTAE_bit(const void *const hw) |
| 5720 | { |
| 5721 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5722 | ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_BOOTAE; |
| 5723 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5724 | } |
| 5725 | |
| 5726 | static inline void hri_sdhc_toggle_EISIER_EMMC_BOOTAE_bit(const void *const hw) |
| 5727 | { |
| 5728 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5729 | ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_BOOTAE; |
| 5730 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5731 | } |
| 5732 | |
| 5733 | static inline void hri_sdhc_set_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) |
| 5734 | { |
| 5735 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5736 | ((Sdhc *)hw)->EISIER.reg |= mask; |
| 5737 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5738 | } |
| 5739 | |
| 5740 | static inline hri_sdhc_eisier_reg_t hri_sdhc_get_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) |
| 5741 | { |
| 5742 | uint16_t tmp; |
| 5743 | tmp = ((Sdhc *)hw)->EISIER.reg; |
| 5744 | tmp &= mask; |
| 5745 | return tmp; |
| 5746 | } |
| 5747 | |
| 5748 | static inline void hri_sdhc_write_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t data) |
| 5749 | { |
| 5750 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5751 | ((Sdhc *)hw)->EISIER.reg = data; |
| 5752 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5753 | } |
| 5754 | |
| 5755 | static inline void hri_sdhc_clear_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) |
| 5756 | { |
| 5757 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5758 | ((Sdhc *)hw)->EISIER.reg &= ~mask; |
| 5759 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5760 | } |
| 5761 | |
| 5762 | static inline void hri_sdhc_toggle_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) |
| 5763 | { |
| 5764 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5765 | ((Sdhc *)hw)->EISIER.reg ^= mask; |
| 5766 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5767 | } |
| 5768 | |
| 5769 | static inline hri_sdhc_eisier_reg_t hri_sdhc_read_EISIER_reg(const void *const hw) |
| 5770 | { |
| 5771 | return ((Sdhc *)hw)->EISIER.reg; |
| 5772 | } |
| 5773 | |
| 5774 | static inline void hri_sdhc_set_HC2R_VS18EN_bit(const void *const hw) |
| 5775 | { |
| 5776 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5777 | ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_VS18EN; |
| 5778 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5779 | } |
| 5780 | |
| 5781 | static inline bool hri_sdhc_get_HC2R_VS18EN_bit(const void *const hw) |
| 5782 | { |
| 5783 | uint16_t tmp; |
| 5784 | tmp = ((Sdhc *)hw)->HC2R.reg; |
| 5785 | tmp = (tmp & SDHC_HC2R_VS18EN) >> SDHC_HC2R_VS18EN_Pos; |
| 5786 | return (bool)tmp; |
| 5787 | } |
| 5788 | |
| 5789 | static inline void hri_sdhc_write_HC2R_VS18EN_bit(const void *const hw, bool value) |
| 5790 | { |
| 5791 | uint16_t tmp; |
| 5792 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5793 | tmp = ((Sdhc *)hw)->HC2R.reg; |
| 5794 | tmp &= ~SDHC_HC2R_VS18EN; |
| 5795 | tmp |= value << SDHC_HC2R_VS18EN_Pos; |
| 5796 | ((Sdhc *)hw)->HC2R.reg = tmp; |
| 5797 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5798 | } |
| 5799 | |
| 5800 | static inline void hri_sdhc_clear_HC2R_VS18EN_bit(const void *const hw) |
| 5801 | { |
| 5802 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5803 | ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_VS18EN; |
| 5804 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5805 | } |
| 5806 | |
| 5807 | static inline void hri_sdhc_toggle_HC2R_VS18EN_bit(const void *const hw) |
| 5808 | { |
| 5809 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5810 | ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_VS18EN; |
| 5811 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5812 | } |
| 5813 | |
| 5814 | static inline void hri_sdhc_set_HC2R_EXTUN_bit(const void *const hw) |
| 5815 | { |
| 5816 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5817 | ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EXTUN; |
| 5818 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5819 | } |
| 5820 | |
| 5821 | static inline bool hri_sdhc_get_HC2R_EXTUN_bit(const void *const hw) |
| 5822 | { |
| 5823 | uint16_t tmp; |
| 5824 | tmp = ((Sdhc *)hw)->HC2R.reg; |
| 5825 | tmp = (tmp & SDHC_HC2R_EXTUN) >> SDHC_HC2R_EXTUN_Pos; |
| 5826 | return (bool)tmp; |
| 5827 | } |
| 5828 | |
| 5829 | static inline void hri_sdhc_write_HC2R_EXTUN_bit(const void *const hw, bool value) |
| 5830 | { |
| 5831 | uint16_t tmp; |
| 5832 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5833 | tmp = ((Sdhc *)hw)->HC2R.reg; |
| 5834 | tmp &= ~SDHC_HC2R_EXTUN; |
| 5835 | tmp |= value << SDHC_HC2R_EXTUN_Pos; |
| 5836 | ((Sdhc *)hw)->HC2R.reg = tmp; |
| 5837 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5838 | } |
| 5839 | |
| 5840 | static inline void hri_sdhc_clear_HC2R_EXTUN_bit(const void *const hw) |
| 5841 | { |
| 5842 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5843 | ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EXTUN; |
| 5844 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5845 | } |
| 5846 | |
| 5847 | static inline void hri_sdhc_toggle_HC2R_EXTUN_bit(const void *const hw) |
| 5848 | { |
| 5849 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5850 | ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EXTUN; |
| 5851 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5852 | } |
| 5853 | |
| 5854 | static inline void hri_sdhc_set_HC2R_SLCKSEL_bit(const void *const hw) |
| 5855 | { |
| 5856 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5857 | ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_SLCKSEL; |
| 5858 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5859 | } |
| 5860 | |
| 5861 | static inline bool hri_sdhc_get_HC2R_SLCKSEL_bit(const void *const hw) |
| 5862 | { |
| 5863 | uint16_t tmp; |
| 5864 | tmp = ((Sdhc *)hw)->HC2R.reg; |
| 5865 | tmp = (tmp & SDHC_HC2R_SLCKSEL) >> SDHC_HC2R_SLCKSEL_Pos; |
| 5866 | return (bool)tmp; |
| 5867 | } |
| 5868 | |
| 5869 | static inline void hri_sdhc_write_HC2R_SLCKSEL_bit(const void *const hw, bool value) |
| 5870 | { |
| 5871 | uint16_t tmp; |
| 5872 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5873 | tmp = ((Sdhc *)hw)->HC2R.reg; |
| 5874 | tmp &= ~SDHC_HC2R_SLCKSEL; |
| 5875 | tmp |= value << SDHC_HC2R_SLCKSEL_Pos; |
| 5876 | ((Sdhc *)hw)->HC2R.reg = tmp; |
| 5877 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5878 | } |
| 5879 | |
| 5880 | static inline void hri_sdhc_clear_HC2R_SLCKSEL_bit(const void *const hw) |
| 5881 | { |
| 5882 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5883 | ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_SLCKSEL; |
| 5884 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5885 | } |
| 5886 | |
| 5887 | static inline void hri_sdhc_toggle_HC2R_SLCKSEL_bit(const void *const hw) |
| 5888 | { |
| 5889 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5890 | ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_SLCKSEL; |
| 5891 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5892 | } |
| 5893 | |
| 5894 | static inline void hri_sdhc_set_HC2R_ASINTEN_bit(const void *const hw) |
| 5895 | { |
| 5896 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5897 | ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_ASINTEN; |
| 5898 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5899 | } |
| 5900 | |
| 5901 | static inline bool hri_sdhc_get_HC2R_ASINTEN_bit(const void *const hw) |
| 5902 | { |
| 5903 | uint16_t tmp; |
| 5904 | tmp = ((Sdhc *)hw)->HC2R.reg; |
| 5905 | tmp = (tmp & SDHC_HC2R_ASINTEN) >> SDHC_HC2R_ASINTEN_Pos; |
| 5906 | return (bool)tmp; |
| 5907 | } |
| 5908 | |
| 5909 | static inline void hri_sdhc_write_HC2R_ASINTEN_bit(const void *const hw, bool value) |
| 5910 | { |
| 5911 | uint16_t tmp; |
| 5912 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5913 | tmp = ((Sdhc *)hw)->HC2R.reg; |
| 5914 | tmp &= ~SDHC_HC2R_ASINTEN; |
| 5915 | tmp |= value << SDHC_HC2R_ASINTEN_Pos; |
| 5916 | ((Sdhc *)hw)->HC2R.reg = tmp; |
| 5917 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5918 | } |
| 5919 | |
| 5920 | static inline void hri_sdhc_clear_HC2R_ASINTEN_bit(const void *const hw) |
| 5921 | { |
| 5922 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5923 | ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_ASINTEN; |
| 5924 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5925 | } |
| 5926 | |
| 5927 | static inline void hri_sdhc_toggle_HC2R_ASINTEN_bit(const void *const hw) |
| 5928 | { |
| 5929 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5930 | ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_ASINTEN; |
| 5931 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5932 | } |
| 5933 | |
| 5934 | static inline void hri_sdhc_set_HC2R_PVALEN_bit(const void *const hw) |
| 5935 | { |
| 5936 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5937 | ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_PVALEN; |
| 5938 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5939 | } |
| 5940 | |
| 5941 | static inline bool hri_sdhc_get_HC2R_PVALEN_bit(const void *const hw) |
| 5942 | { |
| 5943 | uint16_t tmp; |
| 5944 | tmp = ((Sdhc *)hw)->HC2R.reg; |
| 5945 | tmp = (tmp & SDHC_HC2R_PVALEN) >> SDHC_HC2R_PVALEN_Pos; |
| 5946 | return (bool)tmp; |
| 5947 | } |
| 5948 | |
| 5949 | static inline void hri_sdhc_write_HC2R_PVALEN_bit(const void *const hw, bool value) |
| 5950 | { |
| 5951 | uint16_t tmp; |
| 5952 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5953 | tmp = ((Sdhc *)hw)->HC2R.reg; |
| 5954 | tmp &= ~SDHC_HC2R_PVALEN; |
| 5955 | tmp |= value << SDHC_HC2R_PVALEN_Pos; |
| 5956 | ((Sdhc *)hw)->HC2R.reg = tmp; |
| 5957 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5958 | } |
| 5959 | |
| 5960 | static inline void hri_sdhc_clear_HC2R_PVALEN_bit(const void *const hw) |
| 5961 | { |
| 5962 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5963 | ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_PVALEN; |
| 5964 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5965 | } |
| 5966 | |
| 5967 | static inline void hri_sdhc_toggle_HC2R_PVALEN_bit(const void *const hw) |
| 5968 | { |
| 5969 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5970 | ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_PVALEN; |
| 5971 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5972 | } |
| 5973 | |
| 5974 | static inline void hri_sdhc_set_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) |
| 5975 | { |
| 5976 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5977 | ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_UHSMS(mask); |
| 5978 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5979 | } |
| 5980 | |
| 5981 | static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) |
| 5982 | { |
| 5983 | uint16_t tmp; |
| 5984 | tmp = ((Sdhc *)hw)->HC2R.reg; |
| 5985 | tmp = (tmp & SDHC_HC2R_UHSMS(mask)) >> SDHC_HC2R_UHSMS_Pos; |
| 5986 | return tmp; |
| 5987 | } |
| 5988 | |
| 5989 | static inline void hri_sdhc_write_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) |
| 5990 | { |
| 5991 | uint16_t tmp; |
| 5992 | SDHC_CRITICAL_SECTION_ENTER(); |
| 5993 | tmp = ((Sdhc *)hw)->HC2R.reg; |
| 5994 | tmp &= ~SDHC_HC2R_UHSMS_Msk; |
| 5995 | tmp |= SDHC_HC2R_UHSMS(data); |
| 5996 | ((Sdhc *)hw)->HC2R.reg = tmp; |
| 5997 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 5998 | } |
| 5999 | |
| 6000 | static inline void hri_sdhc_clear_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) |
| 6001 | { |
| 6002 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6003 | ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_UHSMS(mask); |
| 6004 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6005 | } |
| 6006 | |
| 6007 | static inline void hri_sdhc_toggle_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) |
| 6008 | { |
| 6009 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6010 | ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_UHSMS(mask); |
| 6011 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6012 | } |
| 6013 | |
| 6014 | static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_UHSMS_bf(const void *const hw) |
| 6015 | { |
| 6016 | uint16_t tmp; |
| 6017 | tmp = ((Sdhc *)hw)->HC2R.reg; |
| 6018 | tmp = (tmp & SDHC_HC2R_UHSMS_Msk) >> SDHC_HC2R_UHSMS_Pos; |
| 6019 | return tmp; |
| 6020 | } |
| 6021 | |
| 6022 | static inline void hri_sdhc_set_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) |
| 6023 | { |
| 6024 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6025 | ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EMMC_HS200EN(mask); |
| 6026 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6027 | } |
| 6028 | |
| 6029 | static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) |
| 6030 | { |
| 6031 | uint16_t tmp; |
| 6032 | tmp = ((Sdhc *)hw)->HC2R.reg; |
| 6033 | tmp = (tmp & SDHC_HC2R_EMMC_HS200EN(mask)) >> SDHC_HC2R_EMMC_HS200EN_Pos; |
| 6034 | return tmp; |
| 6035 | } |
| 6036 | |
| 6037 | static inline void hri_sdhc_write_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) |
| 6038 | { |
| 6039 | uint16_t tmp; |
| 6040 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6041 | tmp = ((Sdhc *)hw)->HC2R.reg; |
| 6042 | tmp &= ~SDHC_HC2R_EMMC_HS200EN_Msk; |
| 6043 | tmp |= SDHC_HC2R_EMMC_HS200EN(data); |
| 6044 | ((Sdhc *)hw)->HC2R.reg = tmp; |
| 6045 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6046 | } |
| 6047 | |
| 6048 | static inline void hri_sdhc_clear_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) |
| 6049 | { |
| 6050 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6051 | ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EMMC_HS200EN(mask); |
| 6052 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6053 | } |
| 6054 | |
| 6055 | static inline void hri_sdhc_toggle_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) |
| 6056 | { |
| 6057 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6058 | ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EMMC_HS200EN(mask); |
| 6059 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6060 | } |
| 6061 | |
| 6062 | static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_EMMC_HS200EN_bf(const void *const hw) |
| 6063 | { |
| 6064 | uint16_t tmp; |
| 6065 | tmp = ((Sdhc *)hw)->HC2R.reg; |
| 6066 | tmp = (tmp & SDHC_HC2R_EMMC_HS200EN_Msk) >> SDHC_HC2R_EMMC_HS200EN_Pos; |
| 6067 | return tmp; |
| 6068 | } |
| 6069 | |
| 6070 | static inline void hri_sdhc_set_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) |
| 6071 | { |
| 6072 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6073 | ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_DRVSEL(mask); |
| 6074 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6075 | } |
| 6076 | |
| 6077 | static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) |
| 6078 | { |
| 6079 | uint16_t tmp; |
| 6080 | tmp = ((Sdhc *)hw)->HC2R.reg; |
| 6081 | tmp = (tmp & SDHC_HC2R_DRVSEL(mask)) >> SDHC_HC2R_DRVSEL_Pos; |
| 6082 | return tmp; |
| 6083 | } |
| 6084 | |
| 6085 | static inline void hri_sdhc_write_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) |
| 6086 | { |
| 6087 | uint16_t tmp; |
| 6088 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6089 | tmp = ((Sdhc *)hw)->HC2R.reg; |
| 6090 | tmp &= ~SDHC_HC2R_DRVSEL_Msk; |
| 6091 | tmp |= SDHC_HC2R_DRVSEL(data); |
| 6092 | ((Sdhc *)hw)->HC2R.reg = tmp; |
| 6093 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6094 | } |
| 6095 | |
| 6096 | static inline void hri_sdhc_clear_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) |
| 6097 | { |
| 6098 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6099 | ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_DRVSEL(mask); |
| 6100 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6101 | } |
| 6102 | |
| 6103 | static inline void hri_sdhc_toggle_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) |
| 6104 | { |
| 6105 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6106 | ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_DRVSEL(mask); |
| 6107 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6108 | } |
| 6109 | |
| 6110 | static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_DRVSEL_bf(const void *const hw) |
| 6111 | { |
| 6112 | uint16_t tmp; |
| 6113 | tmp = ((Sdhc *)hw)->HC2R.reg; |
| 6114 | tmp = (tmp & SDHC_HC2R_DRVSEL_Msk) >> SDHC_HC2R_DRVSEL_Pos; |
| 6115 | return tmp; |
| 6116 | } |
| 6117 | |
| 6118 | static inline void hri_sdhc_set_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) |
| 6119 | { |
| 6120 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6121 | ((Sdhc *)hw)->HC2R.reg |= mask; |
| 6122 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6123 | } |
| 6124 | |
| 6125 | static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) |
| 6126 | { |
| 6127 | uint16_t tmp; |
| 6128 | tmp = ((Sdhc *)hw)->HC2R.reg; |
| 6129 | tmp &= mask; |
| 6130 | return tmp; |
| 6131 | } |
| 6132 | |
| 6133 | static inline void hri_sdhc_write_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t data) |
| 6134 | { |
| 6135 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6136 | ((Sdhc *)hw)->HC2R.reg = data; |
| 6137 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6138 | } |
| 6139 | |
| 6140 | static inline void hri_sdhc_clear_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) |
| 6141 | { |
| 6142 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6143 | ((Sdhc *)hw)->HC2R.reg &= ~mask; |
| 6144 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6145 | } |
| 6146 | |
| 6147 | static inline void hri_sdhc_toggle_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) |
| 6148 | { |
| 6149 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6150 | ((Sdhc *)hw)->HC2R.reg ^= mask; |
| 6151 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6152 | } |
| 6153 | |
| 6154 | static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_reg(const void *const hw) |
| 6155 | { |
| 6156 | return ((Sdhc *)hw)->HC2R.reg; |
| 6157 | } |
| 6158 | |
| 6159 | static inline void hri_sdhc_set_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) |
| 6160 | { |
| 6161 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6162 | ((Sdhc *)hw)->ASAR[index].reg |= SDHC_ASAR_ADMASA(mask); |
| 6163 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6164 | } |
| 6165 | |
| 6166 | static inline hri_sdhc_asar_reg_t hri_sdhc_get_ASAR_ADMASA_bf(const void *const hw, uint8_t index, |
| 6167 | hri_sdhc_asar_reg_t mask) |
| 6168 | { |
| 6169 | uint32_t tmp; |
| 6170 | tmp = ((Sdhc *)hw)->ASAR[index].reg; |
| 6171 | tmp = (tmp & SDHC_ASAR_ADMASA(mask)) >> SDHC_ASAR_ADMASA_Pos; |
| 6172 | return tmp; |
| 6173 | } |
| 6174 | |
| 6175 | static inline void hri_sdhc_write_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t data) |
| 6176 | { |
| 6177 | uint32_t tmp; |
| 6178 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6179 | tmp = ((Sdhc *)hw)->ASAR[index].reg; |
| 6180 | tmp &= ~SDHC_ASAR_ADMASA_Msk; |
| 6181 | tmp |= SDHC_ASAR_ADMASA(data); |
| 6182 | ((Sdhc *)hw)->ASAR[index].reg = tmp; |
| 6183 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6184 | } |
| 6185 | |
| 6186 | static inline void hri_sdhc_clear_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) |
| 6187 | { |
| 6188 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6189 | ((Sdhc *)hw)->ASAR[index].reg &= ~SDHC_ASAR_ADMASA(mask); |
| 6190 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6191 | } |
| 6192 | |
| 6193 | static inline void hri_sdhc_toggle_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) |
| 6194 | { |
| 6195 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6196 | ((Sdhc *)hw)->ASAR[index].reg ^= SDHC_ASAR_ADMASA(mask); |
| 6197 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6198 | } |
| 6199 | |
| 6200 | static inline hri_sdhc_asar_reg_t hri_sdhc_read_ASAR_ADMASA_bf(const void *const hw, uint8_t index) |
| 6201 | { |
| 6202 | uint32_t tmp; |
| 6203 | tmp = ((Sdhc *)hw)->ASAR[index].reg; |
| 6204 | tmp = (tmp & SDHC_ASAR_ADMASA_Msk) >> SDHC_ASAR_ADMASA_Pos; |
| 6205 | return tmp; |
| 6206 | } |
| 6207 | |
| 6208 | static inline void hri_sdhc_set_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) |
| 6209 | { |
| 6210 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6211 | ((Sdhc *)hw)->ASAR[index].reg |= mask; |
| 6212 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6213 | } |
| 6214 | |
| 6215 | static inline hri_sdhc_asar_reg_t hri_sdhc_get_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) |
| 6216 | { |
| 6217 | uint32_t tmp; |
| 6218 | tmp = ((Sdhc *)hw)->ASAR[index].reg; |
| 6219 | tmp &= mask; |
| 6220 | return tmp; |
| 6221 | } |
| 6222 | |
| 6223 | static inline void hri_sdhc_write_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t data) |
| 6224 | { |
| 6225 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6226 | ((Sdhc *)hw)->ASAR[index].reg = data; |
| 6227 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6228 | } |
| 6229 | |
| 6230 | static inline void hri_sdhc_clear_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) |
| 6231 | { |
| 6232 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6233 | ((Sdhc *)hw)->ASAR[index].reg &= ~mask; |
| 6234 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6235 | } |
| 6236 | |
| 6237 | static inline void hri_sdhc_toggle_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) |
| 6238 | { |
| 6239 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6240 | ((Sdhc *)hw)->ASAR[index].reg ^= mask; |
| 6241 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6242 | } |
| 6243 | |
| 6244 | static inline hri_sdhc_asar_reg_t hri_sdhc_read_ASAR_reg(const void *const hw, uint8_t index) |
| 6245 | { |
| 6246 | return ((Sdhc *)hw)->ASAR[index].reg; |
| 6247 | } |
| 6248 | |
| 6249 | static inline void hri_sdhc_set_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) |
| 6250 | { |
| 6251 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6252 | ((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_CLKGSEL; |
| 6253 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6254 | } |
| 6255 | |
| 6256 | static inline bool hri_sdhc_get_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) |
| 6257 | { |
| 6258 | uint16_t tmp; |
| 6259 | tmp = ((Sdhc *)hw)->PVR[index].reg; |
| 6260 | tmp = (tmp & SDHC_PVR_CLKGSEL) >> SDHC_PVR_CLKGSEL_Pos; |
| 6261 | return (bool)tmp; |
| 6262 | } |
| 6263 | |
| 6264 | static inline void hri_sdhc_write_PVR_CLKGSEL_bit(const void *const hw, uint8_t index, bool value) |
| 6265 | { |
| 6266 | uint16_t tmp; |
| 6267 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6268 | tmp = ((Sdhc *)hw)->PVR[index].reg; |
| 6269 | tmp &= ~SDHC_PVR_CLKGSEL; |
| 6270 | tmp |= value << SDHC_PVR_CLKGSEL_Pos; |
| 6271 | ((Sdhc *)hw)->PVR[index].reg = tmp; |
| 6272 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6273 | } |
| 6274 | |
| 6275 | static inline void hri_sdhc_clear_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) |
| 6276 | { |
| 6277 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6278 | ((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_CLKGSEL; |
| 6279 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6280 | } |
| 6281 | |
| 6282 | static inline void hri_sdhc_toggle_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) |
| 6283 | { |
| 6284 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6285 | ((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_CLKGSEL; |
| 6286 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6287 | } |
| 6288 | |
| 6289 | static inline void hri_sdhc_set_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) |
| 6290 | { |
| 6291 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6292 | ((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_SDCLKFSEL(mask); |
| 6293 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6294 | } |
| 6295 | |
| 6296 | static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, |
| 6297 | hri_sdhc_pvr_reg_t mask) |
| 6298 | { |
| 6299 | uint16_t tmp; |
| 6300 | tmp = ((Sdhc *)hw)->PVR[index].reg; |
| 6301 | tmp = (tmp & SDHC_PVR_SDCLKFSEL(mask)) >> SDHC_PVR_SDCLKFSEL_Pos; |
| 6302 | return tmp; |
| 6303 | } |
| 6304 | |
| 6305 | static inline void hri_sdhc_write_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data) |
| 6306 | { |
| 6307 | uint16_t tmp; |
| 6308 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6309 | tmp = ((Sdhc *)hw)->PVR[index].reg; |
| 6310 | tmp &= ~SDHC_PVR_SDCLKFSEL_Msk; |
| 6311 | tmp |= SDHC_PVR_SDCLKFSEL(data); |
| 6312 | ((Sdhc *)hw)->PVR[index].reg = tmp; |
| 6313 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6314 | } |
| 6315 | |
| 6316 | static inline void hri_sdhc_clear_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) |
| 6317 | { |
| 6318 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6319 | ((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_SDCLKFSEL(mask); |
| 6320 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6321 | } |
| 6322 | |
| 6323 | static inline void hri_sdhc_toggle_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) |
| 6324 | { |
| 6325 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6326 | ((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_SDCLKFSEL(mask); |
| 6327 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6328 | } |
| 6329 | |
| 6330 | static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index) |
| 6331 | { |
| 6332 | uint16_t tmp; |
| 6333 | tmp = ((Sdhc *)hw)->PVR[index].reg; |
| 6334 | tmp = (tmp & SDHC_PVR_SDCLKFSEL_Msk) >> SDHC_PVR_SDCLKFSEL_Pos; |
| 6335 | return tmp; |
| 6336 | } |
| 6337 | |
| 6338 | static inline void hri_sdhc_set_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) |
| 6339 | { |
| 6340 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6341 | ((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_DRVSEL(mask); |
| 6342 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6343 | } |
| 6344 | |
| 6345 | static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_DRVSEL_bf(const void *const hw, uint8_t index, |
| 6346 | hri_sdhc_pvr_reg_t mask) |
| 6347 | { |
| 6348 | uint16_t tmp; |
| 6349 | tmp = ((Sdhc *)hw)->PVR[index].reg; |
| 6350 | tmp = (tmp & SDHC_PVR_DRVSEL(mask)) >> SDHC_PVR_DRVSEL_Pos; |
| 6351 | return tmp; |
| 6352 | } |
| 6353 | |
| 6354 | static inline void hri_sdhc_write_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data) |
| 6355 | { |
| 6356 | uint16_t tmp; |
| 6357 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6358 | tmp = ((Sdhc *)hw)->PVR[index].reg; |
| 6359 | tmp &= ~SDHC_PVR_DRVSEL_Msk; |
| 6360 | tmp |= SDHC_PVR_DRVSEL(data); |
| 6361 | ((Sdhc *)hw)->PVR[index].reg = tmp; |
| 6362 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6363 | } |
| 6364 | |
| 6365 | static inline void hri_sdhc_clear_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) |
| 6366 | { |
| 6367 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6368 | ((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_DRVSEL(mask); |
| 6369 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6370 | } |
| 6371 | |
| 6372 | static inline void hri_sdhc_toggle_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) |
| 6373 | { |
| 6374 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6375 | ((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_DRVSEL(mask); |
| 6376 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6377 | } |
| 6378 | |
| 6379 | static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_DRVSEL_bf(const void *const hw, uint8_t index) |
| 6380 | { |
| 6381 | uint16_t tmp; |
| 6382 | tmp = ((Sdhc *)hw)->PVR[index].reg; |
| 6383 | tmp = (tmp & SDHC_PVR_DRVSEL_Msk) >> SDHC_PVR_DRVSEL_Pos; |
| 6384 | return tmp; |
| 6385 | } |
| 6386 | |
| 6387 | static inline void hri_sdhc_set_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) |
| 6388 | { |
| 6389 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6390 | ((Sdhc *)hw)->PVR[index].reg |= mask; |
| 6391 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6392 | } |
| 6393 | |
| 6394 | static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) |
| 6395 | { |
| 6396 | uint16_t tmp; |
| 6397 | tmp = ((Sdhc *)hw)->PVR[index].reg; |
| 6398 | tmp &= mask; |
| 6399 | return tmp; |
| 6400 | } |
| 6401 | |
| 6402 | static inline void hri_sdhc_write_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data) |
| 6403 | { |
| 6404 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6405 | ((Sdhc *)hw)->PVR[index].reg = data; |
| 6406 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6407 | } |
| 6408 | |
| 6409 | static inline void hri_sdhc_clear_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) |
| 6410 | { |
| 6411 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6412 | ((Sdhc *)hw)->PVR[index].reg &= ~mask; |
| 6413 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6414 | } |
| 6415 | |
| 6416 | static inline void hri_sdhc_toggle_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) |
| 6417 | { |
| 6418 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6419 | ((Sdhc *)hw)->PVR[index].reg ^= mask; |
| 6420 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6421 | } |
| 6422 | |
| 6423 | static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_reg(const void *const hw, uint8_t index) |
| 6424 | { |
| 6425 | return ((Sdhc *)hw)->PVR[index].reg; |
| 6426 | } |
| 6427 | |
| 6428 | static inline void hri_sdhc_set_MC1R_DDR_bit(const void *const hw) |
| 6429 | { |
| 6430 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6431 | ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_DDR; |
| 6432 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6433 | } |
| 6434 | |
| 6435 | static inline bool hri_sdhc_get_MC1R_DDR_bit(const void *const hw) |
| 6436 | { |
| 6437 | uint8_t tmp; |
| 6438 | tmp = ((Sdhc *)hw)->MC1R.reg; |
| 6439 | tmp = (tmp & SDHC_MC1R_DDR) >> SDHC_MC1R_DDR_Pos; |
| 6440 | return (bool)tmp; |
| 6441 | } |
| 6442 | |
| 6443 | static inline void hri_sdhc_write_MC1R_DDR_bit(const void *const hw, bool value) |
| 6444 | { |
| 6445 | uint8_t tmp; |
| 6446 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6447 | tmp = ((Sdhc *)hw)->MC1R.reg; |
| 6448 | tmp &= ~SDHC_MC1R_DDR; |
| 6449 | tmp |= value << SDHC_MC1R_DDR_Pos; |
| 6450 | ((Sdhc *)hw)->MC1R.reg = tmp; |
| 6451 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6452 | } |
| 6453 | |
| 6454 | static inline void hri_sdhc_clear_MC1R_DDR_bit(const void *const hw) |
| 6455 | { |
| 6456 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6457 | ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_DDR; |
| 6458 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6459 | } |
| 6460 | |
| 6461 | static inline void hri_sdhc_toggle_MC1R_DDR_bit(const void *const hw) |
| 6462 | { |
| 6463 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6464 | ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_DDR; |
| 6465 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6466 | } |
| 6467 | |
| 6468 | static inline void hri_sdhc_set_MC1R_OPD_bit(const void *const hw) |
| 6469 | { |
| 6470 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6471 | ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_OPD; |
| 6472 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6473 | } |
| 6474 | |
| 6475 | static inline bool hri_sdhc_get_MC1R_OPD_bit(const void *const hw) |
| 6476 | { |
| 6477 | uint8_t tmp; |
| 6478 | tmp = ((Sdhc *)hw)->MC1R.reg; |
| 6479 | tmp = (tmp & SDHC_MC1R_OPD) >> SDHC_MC1R_OPD_Pos; |
| 6480 | return (bool)tmp; |
| 6481 | } |
| 6482 | |
| 6483 | static inline void hri_sdhc_write_MC1R_OPD_bit(const void *const hw, bool value) |
| 6484 | { |
| 6485 | uint8_t tmp; |
| 6486 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6487 | tmp = ((Sdhc *)hw)->MC1R.reg; |
| 6488 | tmp &= ~SDHC_MC1R_OPD; |
| 6489 | tmp |= value << SDHC_MC1R_OPD_Pos; |
| 6490 | ((Sdhc *)hw)->MC1R.reg = tmp; |
| 6491 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6492 | } |
| 6493 | |
| 6494 | static inline void hri_sdhc_clear_MC1R_OPD_bit(const void *const hw) |
| 6495 | { |
| 6496 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6497 | ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_OPD; |
| 6498 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6499 | } |
| 6500 | |
| 6501 | static inline void hri_sdhc_toggle_MC1R_OPD_bit(const void *const hw) |
| 6502 | { |
| 6503 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6504 | ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_OPD; |
| 6505 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6506 | } |
| 6507 | |
| 6508 | static inline void hri_sdhc_set_MC1R_BOOTA_bit(const void *const hw) |
| 6509 | { |
| 6510 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6511 | ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_BOOTA; |
| 6512 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6513 | } |
| 6514 | |
| 6515 | static inline bool hri_sdhc_get_MC1R_BOOTA_bit(const void *const hw) |
| 6516 | { |
| 6517 | uint8_t tmp; |
| 6518 | tmp = ((Sdhc *)hw)->MC1R.reg; |
| 6519 | tmp = (tmp & SDHC_MC1R_BOOTA) >> SDHC_MC1R_BOOTA_Pos; |
| 6520 | return (bool)tmp; |
| 6521 | } |
| 6522 | |
| 6523 | static inline void hri_sdhc_write_MC1R_BOOTA_bit(const void *const hw, bool value) |
| 6524 | { |
| 6525 | uint8_t tmp; |
| 6526 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6527 | tmp = ((Sdhc *)hw)->MC1R.reg; |
| 6528 | tmp &= ~SDHC_MC1R_BOOTA; |
| 6529 | tmp |= value << SDHC_MC1R_BOOTA_Pos; |
| 6530 | ((Sdhc *)hw)->MC1R.reg = tmp; |
| 6531 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6532 | } |
| 6533 | |
| 6534 | static inline void hri_sdhc_clear_MC1R_BOOTA_bit(const void *const hw) |
| 6535 | { |
| 6536 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6537 | ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_BOOTA; |
| 6538 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6539 | } |
| 6540 | |
| 6541 | static inline void hri_sdhc_toggle_MC1R_BOOTA_bit(const void *const hw) |
| 6542 | { |
| 6543 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6544 | ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_BOOTA; |
| 6545 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6546 | } |
| 6547 | |
| 6548 | static inline void hri_sdhc_set_MC1R_RSTN_bit(const void *const hw) |
| 6549 | { |
| 6550 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6551 | ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_RSTN; |
| 6552 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6553 | } |
| 6554 | |
| 6555 | static inline bool hri_sdhc_get_MC1R_RSTN_bit(const void *const hw) |
| 6556 | { |
| 6557 | uint8_t tmp; |
| 6558 | tmp = ((Sdhc *)hw)->MC1R.reg; |
| 6559 | tmp = (tmp & SDHC_MC1R_RSTN) >> SDHC_MC1R_RSTN_Pos; |
| 6560 | return (bool)tmp; |
| 6561 | } |
| 6562 | |
| 6563 | static inline void hri_sdhc_write_MC1R_RSTN_bit(const void *const hw, bool value) |
| 6564 | { |
| 6565 | uint8_t tmp; |
| 6566 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6567 | tmp = ((Sdhc *)hw)->MC1R.reg; |
| 6568 | tmp &= ~SDHC_MC1R_RSTN; |
| 6569 | tmp |= value << SDHC_MC1R_RSTN_Pos; |
| 6570 | ((Sdhc *)hw)->MC1R.reg = tmp; |
| 6571 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6572 | } |
| 6573 | |
| 6574 | static inline void hri_sdhc_clear_MC1R_RSTN_bit(const void *const hw) |
| 6575 | { |
| 6576 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6577 | ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_RSTN; |
| 6578 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6579 | } |
| 6580 | |
| 6581 | static inline void hri_sdhc_toggle_MC1R_RSTN_bit(const void *const hw) |
| 6582 | { |
| 6583 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6584 | ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_RSTN; |
| 6585 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6586 | } |
| 6587 | |
| 6588 | static inline void hri_sdhc_set_MC1R_FCD_bit(const void *const hw) |
| 6589 | { |
| 6590 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6591 | ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_FCD; |
| 6592 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6593 | } |
| 6594 | |
| 6595 | static inline bool hri_sdhc_get_MC1R_FCD_bit(const void *const hw) |
| 6596 | { |
| 6597 | uint8_t tmp; |
| 6598 | tmp = ((Sdhc *)hw)->MC1R.reg; |
| 6599 | tmp = (tmp & SDHC_MC1R_FCD) >> SDHC_MC1R_FCD_Pos; |
| 6600 | return (bool)tmp; |
| 6601 | } |
| 6602 | |
| 6603 | static inline void hri_sdhc_write_MC1R_FCD_bit(const void *const hw, bool value) |
| 6604 | { |
| 6605 | uint8_t tmp; |
| 6606 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6607 | tmp = ((Sdhc *)hw)->MC1R.reg; |
| 6608 | tmp &= ~SDHC_MC1R_FCD; |
| 6609 | tmp |= value << SDHC_MC1R_FCD_Pos; |
| 6610 | ((Sdhc *)hw)->MC1R.reg = tmp; |
| 6611 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6612 | } |
| 6613 | |
| 6614 | static inline void hri_sdhc_clear_MC1R_FCD_bit(const void *const hw) |
| 6615 | { |
| 6616 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6617 | ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_FCD; |
| 6618 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6619 | } |
| 6620 | |
| 6621 | static inline void hri_sdhc_toggle_MC1R_FCD_bit(const void *const hw) |
| 6622 | { |
| 6623 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6624 | ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_FCD; |
| 6625 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6626 | } |
| 6627 | |
| 6628 | static inline void hri_sdhc_set_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) |
| 6629 | { |
| 6630 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6631 | ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_CMDTYP(mask); |
| 6632 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6633 | } |
| 6634 | |
| 6635 | static inline hri_sdhc_mc1r_reg_t hri_sdhc_get_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) |
| 6636 | { |
| 6637 | uint8_t tmp; |
| 6638 | tmp = ((Sdhc *)hw)->MC1R.reg; |
| 6639 | tmp = (tmp & SDHC_MC1R_CMDTYP(mask)) >> SDHC_MC1R_CMDTYP_Pos; |
| 6640 | return tmp; |
| 6641 | } |
| 6642 | |
| 6643 | static inline void hri_sdhc_write_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t data) |
| 6644 | { |
| 6645 | uint8_t tmp; |
| 6646 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6647 | tmp = ((Sdhc *)hw)->MC1R.reg; |
| 6648 | tmp &= ~SDHC_MC1R_CMDTYP_Msk; |
| 6649 | tmp |= SDHC_MC1R_CMDTYP(data); |
| 6650 | ((Sdhc *)hw)->MC1R.reg = tmp; |
| 6651 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6652 | } |
| 6653 | |
| 6654 | static inline void hri_sdhc_clear_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) |
| 6655 | { |
| 6656 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6657 | ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_CMDTYP(mask); |
| 6658 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6659 | } |
| 6660 | |
| 6661 | static inline void hri_sdhc_toggle_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) |
| 6662 | { |
| 6663 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6664 | ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_CMDTYP(mask); |
| 6665 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6666 | } |
| 6667 | |
| 6668 | static inline hri_sdhc_mc1r_reg_t hri_sdhc_read_MC1R_CMDTYP_bf(const void *const hw) |
| 6669 | { |
| 6670 | uint8_t tmp; |
| 6671 | tmp = ((Sdhc *)hw)->MC1R.reg; |
| 6672 | tmp = (tmp & SDHC_MC1R_CMDTYP_Msk) >> SDHC_MC1R_CMDTYP_Pos; |
| 6673 | return tmp; |
| 6674 | } |
| 6675 | |
| 6676 | static inline void hri_sdhc_set_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) |
| 6677 | { |
| 6678 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6679 | ((Sdhc *)hw)->MC1R.reg |= mask; |
| 6680 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6681 | } |
| 6682 | |
| 6683 | static inline hri_sdhc_mc1r_reg_t hri_sdhc_get_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) |
| 6684 | { |
| 6685 | uint8_t tmp; |
| 6686 | tmp = ((Sdhc *)hw)->MC1R.reg; |
| 6687 | tmp &= mask; |
| 6688 | return tmp; |
| 6689 | } |
| 6690 | |
| 6691 | static inline void hri_sdhc_write_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t data) |
| 6692 | { |
| 6693 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6694 | ((Sdhc *)hw)->MC1R.reg = data; |
| 6695 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6696 | } |
| 6697 | |
| 6698 | static inline void hri_sdhc_clear_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) |
| 6699 | { |
| 6700 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6701 | ((Sdhc *)hw)->MC1R.reg &= ~mask; |
| 6702 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6703 | } |
| 6704 | |
| 6705 | static inline void hri_sdhc_toggle_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) |
| 6706 | { |
| 6707 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6708 | ((Sdhc *)hw)->MC1R.reg ^= mask; |
| 6709 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6710 | } |
| 6711 | |
| 6712 | static inline hri_sdhc_mc1r_reg_t hri_sdhc_read_MC1R_reg(const void *const hw) |
| 6713 | { |
| 6714 | return ((Sdhc *)hw)->MC1R.reg; |
| 6715 | } |
| 6716 | |
| 6717 | static inline void hri_sdhc_set_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) |
| 6718 | { |
| 6719 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6720 | ((Sdhc *)hw)->ACR.reg |= SDHC_ACR_BMAX(mask); |
| 6721 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6722 | } |
| 6723 | |
| 6724 | static inline hri_sdhc_acr_reg_t hri_sdhc_get_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) |
| 6725 | { |
| 6726 | uint32_t tmp; |
| 6727 | tmp = ((Sdhc *)hw)->ACR.reg; |
| 6728 | tmp = (tmp & SDHC_ACR_BMAX(mask)) >> SDHC_ACR_BMAX_Pos; |
| 6729 | return tmp; |
| 6730 | } |
| 6731 | |
| 6732 | static inline void hri_sdhc_write_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t data) |
| 6733 | { |
| 6734 | uint32_t tmp; |
| 6735 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6736 | tmp = ((Sdhc *)hw)->ACR.reg; |
| 6737 | tmp &= ~SDHC_ACR_BMAX_Msk; |
| 6738 | tmp |= SDHC_ACR_BMAX(data); |
| 6739 | ((Sdhc *)hw)->ACR.reg = tmp; |
| 6740 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6741 | } |
| 6742 | |
| 6743 | static inline void hri_sdhc_clear_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) |
| 6744 | { |
| 6745 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6746 | ((Sdhc *)hw)->ACR.reg &= ~SDHC_ACR_BMAX(mask); |
| 6747 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6748 | } |
| 6749 | |
| 6750 | static inline void hri_sdhc_toggle_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) |
| 6751 | { |
| 6752 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6753 | ((Sdhc *)hw)->ACR.reg ^= SDHC_ACR_BMAX(mask); |
| 6754 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6755 | } |
| 6756 | |
| 6757 | static inline hri_sdhc_acr_reg_t hri_sdhc_read_ACR_BMAX_bf(const void *const hw) |
| 6758 | { |
| 6759 | uint32_t tmp; |
| 6760 | tmp = ((Sdhc *)hw)->ACR.reg; |
| 6761 | tmp = (tmp & SDHC_ACR_BMAX_Msk) >> SDHC_ACR_BMAX_Pos; |
| 6762 | return tmp; |
| 6763 | } |
| 6764 | |
| 6765 | static inline void hri_sdhc_set_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) |
| 6766 | { |
| 6767 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6768 | ((Sdhc *)hw)->ACR.reg |= mask; |
| 6769 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6770 | } |
| 6771 | |
| 6772 | static inline hri_sdhc_acr_reg_t hri_sdhc_get_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) |
| 6773 | { |
| 6774 | uint32_t tmp; |
| 6775 | tmp = ((Sdhc *)hw)->ACR.reg; |
| 6776 | tmp &= mask; |
| 6777 | return tmp; |
| 6778 | } |
| 6779 | |
| 6780 | static inline void hri_sdhc_write_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t data) |
| 6781 | { |
| 6782 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6783 | ((Sdhc *)hw)->ACR.reg = data; |
| 6784 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6785 | } |
| 6786 | |
| 6787 | static inline void hri_sdhc_clear_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) |
| 6788 | { |
| 6789 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6790 | ((Sdhc *)hw)->ACR.reg &= ~mask; |
| 6791 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6792 | } |
| 6793 | |
| 6794 | static inline void hri_sdhc_toggle_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) |
| 6795 | { |
| 6796 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6797 | ((Sdhc *)hw)->ACR.reg ^= mask; |
| 6798 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6799 | } |
| 6800 | |
| 6801 | static inline hri_sdhc_acr_reg_t hri_sdhc_read_ACR_reg(const void *const hw) |
| 6802 | { |
| 6803 | return ((Sdhc *)hw)->ACR.reg; |
| 6804 | } |
| 6805 | |
| 6806 | static inline void hri_sdhc_set_CC2R_FSDCLKD_bit(const void *const hw) |
| 6807 | { |
| 6808 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6809 | ((Sdhc *)hw)->CC2R.reg |= SDHC_CC2R_FSDCLKD; |
| 6810 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6811 | } |
| 6812 | |
| 6813 | static inline bool hri_sdhc_get_CC2R_FSDCLKD_bit(const void *const hw) |
| 6814 | { |
| 6815 | uint32_t tmp; |
| 6816 | tmp = ((Sdhc *)hw)->CC2R.reg; |
| 6817 | tmp = (tmp & SDHC_CC2R_FSDCLKD) >> SDHC_CC2R_FSDCLKD_Pos; |
| 6818 | return (bool)tmp; |
| 6819 | } |
| 6820 | |
| 6821 | static inline void hri_sdhc_write_CC2R_FSDCLKD_bit(const void *const hw, bool value) |
| 6822 | { |
| 6823 | uint32_t tmp; |
| 6824 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6825 | tmp = ((Sdhc *)hw)->CC2R.reg; |
| 6826 | tmp &= ~SDHC_CC2R_FSDCLKD; |
| 6827 | tmp |= value << SDHC_CC2R_FSDCLKD_Pos; |
| 6828 | ((Sdhc *)hw)->CC2R.reg = tmp; |
| 6829 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6830 | } |
| 6831 | |
| 6832 | static inline void hri_sdhc_clear_CC2R_FSDCLKD_bit(const void *const hw) |
| 6833 | { |
| 6834 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6835 | ((Sdhc *)hw)->CC2R.reg &= ~SDHC_CC2R_FSDCLKD; |
| 6836 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6837 | } |
| 6838 | |
| 6839 | static inline void hri_sdhc_toggle_CC2R_FSDCLKD_bit(const void *const hw) |
| 6840 | { |
| 6841 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6842 | ((Sdhc *)hw)->CC2R.reg ^= SDHC_CC2R_FSDCLKD; |
| 6843 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6844 | } |
| 6845 | |
| 6846 | static inline void hri_sdhc_set_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) |
| 6847 | { |
| 6848 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6849 | ((Sdhc *)hw)->CC2R.reg |= mask; |
| 6850 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6851 | } |
| 6852 | |
| 6853 | static inline hri_sdhc_cc2r_reg_t hri_sdhc_get_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) |
| 6854 | { |
| 6855 | uint32_t tmp; |
| 6856 | tmp = ((Sdhc *)hw)->CC2R.reg; |
| 6857 | tmp &= mask; |
| 6858 | return tmp; |
| 6859 | } |
| 6860 | |
| 6861 | static inline void hri_sdhc_write_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t data) |
| 6862 | { |
| 6863 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6864 | ((Sdhc *)hw)->CC2R.reg = data; |
| 6865 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6866 | } |
| 6867 | |
| 6868 | static inline void hri_sdhc_clear_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) |
| 6869 | { |
| 6870 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6871 | ((Sdhc *)hw)->CC2R.reg &= ~mask; |
| 6872 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6873 | } |
| 6874 | |
| 6875 | static inline void hri_sdhc_toggle_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) |
| 6876 | { |
| 6877 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6878 | ((Sdhc *)hw)->CC2R.reg ^= mask; |
| 6879 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6880 | } |
| 6881 | |
| 6882 | static inline hri_sdhc_cc2r_reg_t hri_sdhc_read_CC2R_reg(const void *const hw) |
| 6883 | { |
| 6884 | return ((Sdhc *)hw)->CC2R.reg; |
| 6885 | } |
| 6886 | |
| 6887 | static inline void hri_sdhc_set_CACR_CAPWREN_bit(const void *const hw) |
| 6888 | { |
| 6889 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6890 | ((Sdhc *)hw)->CACR.reg |= SDHC_CACR_CAPWREN; |
| 6891 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6892 | } |
| 6893 | |
| 6894 | static inline bool hri_sdhc_get_CACR_CAPWREN_bit(const void *const hw) |
| 6895 | { |
| 6896 | uint32_t tmp; |
| 6897 | tmp = ((Sdhc *)hw)->CACR.reg; |
| 6898 | tmp = (tmp & SDHC_CACR_CAPWREN) >> SDHC_CACR_CAPWREN_Pos; |
| 6899 | return (bool)tmp; |
| 6900 | } |
| 6901 | |
| 6902 | static inline void hri_sdhc_write_CACR_CAPWREN_bit(const void *const hw, bool value) |
| 6903 | { |
| 6904 | uint32_t tmp; |
| 6905 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6906 | tmp = ((Sdhc *)hw)->CACR.reg; |
| 6907 | tmp &= ~SDHC_CACR_CAPWREN; |
| 6908 | tmp |= value << SDHC_CACR_CAPWREN_Pos; |
| 6909 | ((Sdhc *)hw)->CACR.reg = tmp; |
| 6910 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6911 | } |
| 6912 | |
| 6913 | static inline void hri_sdhc_clear_CACR_CAPWREN_bit(const void *const hw) |
| 6914 | { |
| 6915 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6916 | ((Sdhc *)hw)->CACR.reg &= ~SDHC_CACR_CAPWREN; |
| 6917 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6918 | } |
| 6919 | |
| 6920 | static inline void hri_sdhc_toggle_CACR_CAPWREN_bit(const void *const hw) |
| 6921 | { |
| 6922 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6923 | ((Sdhc *)hw)->CACR.reg ^= SDHC_CACR_CAPWREN; |
| 6924 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6925 | } |
| 6926 | |
| 6927 | static inline void hri_sdhc_set_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) |
| 6928 | { |
| 6929 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6930 | ((Sdhc *)hw)->CACR.reg |= SDHC_CACR_KEY(mask); |
| 6931 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6932 | } |
| 6933 | |
| 6934 | static inline hri_sdhc_cacr_reg_t hri_sdhc_get_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) |
| 6935 | { |
| 6936 | uint32_t tmp; |
| 6937 | tmp = ((Sdhc *)hw)->CACR.reg; |
| 6938 | tmp = (tmp & SDHC_CACR_KEY(mask)) >> SDHC_CACR_KEY_Pos; |
| 6939 | return tmp; |
| 6940 | } |
| 6941 | |
| 6942 | static inline void hri_sdhc_write_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t data) |
| 6943 | { |
| 6944 | uint32_t tmp; |
| 6945 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6946 | tmp = ((Sdhc *)hw)->CACR.reg; |
| 6947 | tmp &= ~SDHC_CACR_KEY_Msk; |
| 6948 | tmp |= SDHC_CACR_KEY(data); |
| 6949 | ((Sdhc *)hw)->CACR.reg = tmp; |
| 6950 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6951 | } |
| 6952 | |
| 6953 | static inline void hri_sdhc_clear_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) |
| 6954 | { |
| 6955 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6956 | ((Sdhc *)hw)->CACR.reg &= ~SDHC_CACR_KEY(mask); |
| 6957 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6958 | } |
| 6959 | |
| 6960 | static inline void hri_sdhc_toggle_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) |
| 6961 | { |
| 6962 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6963 | ((Sdhc *)hw)->CACR.reg ^= SDHC_CACR_KEY(mask); |
| 6964 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6965 | } |
| 6966 | |
| 6967 | static inline hri_sdhc_cacr_reg_t hri_sdhc_read_CACR_KEY_bf(const void *const hw) |
| 6968 | { |
| 6969 | uint32_t tmp; |
| 6970 | tmp = ((Sdhc *)hw)->CACR.reg; |
| 6971 | tmp = (tmp & SDHC_CACR_KEY_Msk) >> SDHC_CACR_KEY_Pos; |
| 6972 | return tmp; |
| 6973 | } |
| 6974 | |
| 6975 | static inline void hri_sdhc_set_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) |
| 6976 | { |
| 6977 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6978 | ((Sdhc *)hw)->CACR.reg |= mask; |
| 6979 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6980 | } |
| 6981 | |
| 6982 | static inline hri_sdhc_cacr_reg_t hri_sdhc_get_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) |
| 6983 | { |
| 6984 | uint32_t tmp; |
| 6985 | tmp = ((Sdhc *)hw)->CACR.reg; |
| 6986 | tmp &= mask; |
| 6987 | return tmp; |
| 6988 | } |
| 6989 | |
| 6990 | static inline void hri_sdhc_write_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t data) |
| 6991 | { |
| 6992 | SDHC_CRITICAL_SECTION_ENTER(); |
| 6993 | ((Sdhc *)hw)->CACR.reg = data; |
| 6994 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 6995 | } |
| 6996 | |
| 6997 | static inline void hri_sdhc_clear_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) |
| 6998 | { |
| 6999 | SDHC_CRITICAL_SECTION_ENTER(); |
| 7000 | ((Sdhc *)hw)->CACR.reg &= ~mask; |
| 7001 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 7002 | } |
| 7003 | |
| 7004 | static inline void hri_sdhc_toggle_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) |
| 7005 | { |
| 7006 | SDHC_CRITICAL_SECTION_ENTER(); |
| 7007 | ((Sdhc *)hw)->CACR.reg ^= mask; |
| 7008 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 7009 | } |
| 7010 | |
| 7011 | static inline hri_sdhc_cacr_reg_t hri_sdhc_read_CACR_reg(const void *const hw) |
| 7012 | { |
| 7013 | return ((Sdhc *)hw)->CACR.reg; |
| 7014 | } |
| 7015 | |
| 7016 | static inline void hri_sdhc_set_DBGR_NIDBG_bit(const void *const hw) |
| 7017 | { |
| 7018 | SDHC_CRITICAL_SECTION_ENTER(); |
| 7019 | ((Sdhc *)hw)->DBGR.reg |= SDHC_DBGR_NIDBG; |
| 7020 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 7021 | } |
| 7022 | |
| 7023 | static inline bool hri_sdhc_get_DBGR_NIDBG_bit(const void *const hw) |
| 7024 | { |
| 7025 | uint8_t tmp; |
| 7026 | tmp = ((Sdhc *)hw)->DBGR.reg; |
| 7027 | tmp = (tmp & SDHC_DBGR_NIDBG) >> SDHC_DBGR_NIDBG_Pos; |
| 7028 | return (bool)tmp; |
| 7029 | } |
| 7030 | |
| 7031 | static inline void hri_sdhc_write_DBGR_NIDBG_bit(const void *const hw, bool value) |
| 7032 | { |
| 7033 | uint8_t tmp; |
| 7034 | SDHC_CRITICAL_SECTION_ENTER(); |
| 7035 | tmp = ((Sdhc *)hw)->DBGR.reg; |
| 7036 | tmp &= ~SDHC_DBGR_NIDBG; |
| 7037 | tmp |= value << SDHC_DBGR_NIDBG_Pos; |
| 7038 | ((Sdhc *)hw)->DBGR.reg = tmp; |
| 7039 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 7040 | } |
| 7041 | |
| 7042 | static inline void hri_sdhc_clear_DBGR_NIDBG_bit(const void *const hw) |
| 7043 | { |
| 7044 | SDHC_CRITICAL_SECTION_ENTER(); |
| 7045 | ((Sdhc *)hw)->DBGR.reg &= ~SDHC_DBGR_NIDBG; |
| 7046 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 7047 | } |
| 7048 | |
| 7049 | static inline void hri_sdhc_toggle_DBGR_NIDBG_bit(const void *const hw) |
| 7050 | { |
| 7051 | SDHC_CRITICAL_SECTION_ENTER(); |
| 7052 | ((Sdhc *)hw)->DBGR.reg ^= SDHC_DBGR_NIDBG; |
| 7053 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 7054 | } |
| 7055 | |
| 7056 | static inline void hri_sdhc_set_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) |
| 7057 | { |
| 7058 | SDHC_CRITICAL_SECTION_ENTER(); |
| 7059 | ((Sdhc *)hw)->DBGR.reg |= mask; |
| 7060 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 7061 | } |
| 7062 | |
| 7063 | static inline hri_sdhc_dbgr_reg_t hri_sdhc_get_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) |
| 7064 | { |
| 7065 | uint8_t tmp; |
| 7066 | tmp = ((Sdhc *)hw)->DBGR.reg; |
| 7067 | tmp &= mask; |
| 7068 | return tmp; |
| 7069 | } |
| 7070 | |
| 7071 | static inline void hri_sdhc_write_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t data) |
| 7072 | { |
| 7073 | SDHC_CRITICAL_SECTION_ENTER(); |
| 7074 | ((Sdhc *)hw)->DBGR.reg = data; |
| 7075 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 7076 | } |
| 7077 | |
| 7078 | static inline void hri_sdhc_clear_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) |
| 7079 | { |
| 7080 | SDHC_CRITICAL_SECTION_ENTER(); |
| 7081 | ((Sdhc *)hw)->DBGR.reg &= ~mask; |
| 7082 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 7083 | } |
| 7084 | |
| 7085 | static inline void hri_sdhc_toggle_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) |
| 7086 | { |
| 7087 | SDHC_CRITICAL_SECTION_ENTER(); |
| 7088 | ((Sdhc *)hw)->DBGR.reg ^= mask; |
| 7089 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 7090 | } |
| 7091 | |
| 7092 | static inline hri_sdhc_dbgr_reg_t hri_sdhc_read_DBGR_reg(const void *const hw) |
| 7093 | { |
| 7094 | return ((Sdhc *)hw)->DBGR.reg; |
| 7095 | } |
| 7096 | |
| 7097 | static inline void hri_sdhc_write_FERACES_reg(const void *const hw, hri_sdhc_feraces_reg_t data) |
| 7098 | { |
| 7099 | SDHC_CRITICAL_SECTION_ENTER(); |
| 7100 | ((Sdhc *)hw)->FERACES.reg = data; |
| 7101 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 7102 | } |
| 7103 | |
| 7104 | static inline void hri_sdhc_write_FEREIS_reg(const void *const hw, hri_sdhc_fereis_reg_t data) |
| 7105 | { |
| 7106 | SDHC_CRITICAL_SECTION_ENTER(); |
| 7107 | ((Sdhc *)hw)->FEREIS.reg = data; |
| 7108 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 7109 | } |
| 7110 | |
| 7111 | static inline void hri_sdhc_write_MC2R_reg(const void *const hw, hri_sdhc_mc2r_reg_t data) |
| 7112 | { |
| 7113 | SDHC_CRITICAL_SECTION_ENTER(); |
| 7114 | ((Sdhc *)hw)->MC2R.reg = data; |
| 7115 | SDHC_CRITICAL_SECTION_LEAVE(); |
| 7116 | } |
| 7117 | |
| 7118 | /* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ |
| 7119 | #define hri_sdhc_set_SSAR_CMD23_reg(a, b) hri_sdhc_set_SSAR_reg(a, b) |
| 7120 | #define hri_sdhc_get_SSAR_CMD23_reg(a, b) hri_sdhc_get_SSAR_reg(a, b) |
| 7121 | #define hri_sdhc_write_SSAR_CMD23_reg(a, b) hri_sdhc_write_SSAR_reg(a, b) |
| 7122 | #define hri_sdhc_clear_SSAR_CMD23_reg(a, b) hri_sdhc_clear_SSAR_reg(a, b) |
| 7123 | #define hri_sdhc_toggle_SSAR_CMD23_reg(a, b) hri_sdhc_toggle_SSAR_reg(a, b) |
| 7124 | #define hri_sdhc_read_SSAR_CMD23_reg(a) hri_sdhc_read_SSAR_reg(a) |
| 7125 | #define hri_sdhc_set_HC1R_EMMC_DW_bit(a) hri_sdhc_set_HC1R_DW_bit(a) |
| 7126 | #define hri_sdhc_get_HC1R_EMMC_DW_bit(a) hri_sdhc_get_HC1R_DW_bit(a) |
| 7127 | #define hri_sdhc_write_HC1R_EMMC_DW_bit(a, b) hri_sdhc_write_HC1R_DW_bit(a, b) |
| 7128 | #define hri_sdhc_clear_HC1R_EMMC_DW_bit(a) hri_sdhc_clear_HC1R_DW_bit(a) |
| 7129 | #define hri_sdhc_toggle_HC1R_EMMC_DW_bit(a) hri_sdhc_toggle_HC1R_DW_bit(a) |
| 7130 | #define hri_sdhc_set_HC1R_EMMC_HSEN_bit(a) hri_sdhc_set_HC1R_HSEN_bit(a) |
| 7131 | #define hri_sdhc_get_HC1R_EMMC_HSEN_bit(a) hri_sdhc_get_HC1R_HSEN_bit(a) |
| 7132 | #define hri_sdhc_write_HC1R_EMMC_HSEN_bit(a, b) hri_sdhc_write_HC1R_HSEN_bit(a, b) |
| 7133 | #define hri_sdhc_clear_HC1R_EMMC_HSEN_bit(a) hri_sdhc_clear_HC1R_HSEN_bit(a) |
| 7134 | #define hri_sdhc_toggle_HC1R_EMMC_HSEN_bit(a) hri_sdhc_toggle_HC1R_HSEN_bit(a) |
| 7135 | #define hri_sdhc_set_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_set_HC1R_DMASEL_bf(a, b) |
| 7136 | #define hri_sdhc_get_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_get_HC1R_DMASEL_bf(a, b) |
| 7137 | #define hri_sdhc_write_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_write_HC1R_DMASEL_bf(a, b) |
| 7138 | #define hri_sdhc_clear_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_clear_HC1R_DMASEL_bf(a, b) |
| 7139 | #define hri_sdhc_toggle_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_toggle_HC1R_DMASEL_bf(a, b) |
| 7140 | #define hri_sdhc_read_HC1R_EMMC_DMASEL_bf(a) hri_sdhc_read_HC1R_DMASEL_bf(a) |
| 7141 | #define hri_sdhc_set_HC1R_EMMC_reg(a, b) hri_sdhc_set_HC1R_reg(a, b) |
| 7142 | #define hri_sdhc_get_HC1R_EMMC_reg(a, b) hri_sdhc_get_HC1R_reg(a, b) |
| 7143 | #define hri_sdhc_write_HC1R_EMMC_reg(a, b) hri_sdhc_write_HC1R_reg(a, b) |
| 7144 | #define hri_sdhc_clear_HC1R_EMMC_reg(a, b) hri_sdhc_clear_HC1R_reg(a, b) |
| 7145 | #define hri_sdhc_toggle_HC1R_EMMC_reg(a, b) hri_sdhc_toggle_HC1R_reg(a, b) |
| 7146 | #define hri_sdhc_read_HC1R_EMMC_reg(a) hri_sdhc_read_HC1R_reg(a) |
| 7147 | #define hri_sdhc_set_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_set_BGCR_STPBGR_bit(a) |
| 7148 | #define hri_sdhc_get_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_get_BGCR_STPBGR_bit(a) |
| 7149 | #define hri_sdhc_write_BGCR_EMMC_STPBGR_bit(a, b) hri_sdhc_write_BGCR_STPBGR_bit(a, b) |
| 7150 | #define hri_sdhc_clear_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_clear_BGCR_STPBGR_bit(a) |
| 7151 | #define hri_sdhc_toggle_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_toggle_BGCR_STPBGR_bit(a) |
| 7152 | #define hri_sdhc_set_BGCR_EMMC_CONTR_bit(a) hri_sdhc_set_BGCR_CONTR_bit(a) |
| 7153 | #define hri_sdhc_get_BGCR_EMMC_CONTR_bit(a) hri_sdhc_get_BGCR_CONTR_bit(a) |
| 7154 | #define hri_sdhc_write_BGCR_EMMC_CONTR_bit(a, b) hri_sdhc_write_BGCR_CONTR_bit(a, b) |
| 7155 | #define hri_sdhc_clear_BGCR_EMMC_CONTR_bit(a) hri_sdhc_clear_BGCR_CONTR_bit(a) |
| 7156 | #define hri_sdhc_toggle_BGCR_EMMC_CONTR_bit(a) hri_sdhc_toggle_BGCR_CONTR_bit(a) |
| 7157 | #define hri_sdhc_set_BGCR_EMMC_reg(a, b) hri_sdhc_set_BGCR_reg(a, b) |
| 7158 | #define hri_sdhc_get_BGCR_EMMC_reg(a, b) hri_sdhc_get_BGCR_reg(a, b) |
| 7159 | #define hri_sdhc_write_BGCR_EMMC_reg(a, b) hri_sdhc_write_BGCR_reg(a, b) |
| 7160 | #define hri_sdhc_clear_BGCR_EMMC_reg(a, b) hri_sdhc_clear_BGCR_reg(a, b) |
| 7161 | #define hri_sdhc_toggle_BGCR_EMMC_reg(a, b) hri_sdhc_toggle_BGCR_reg(a, b) |
| 7162 | #define hri_sdhc_read_BGCR_EMMC_reg(a) hri_sdhc_read_BGCR_reg(a) |
| 7163 | #define hri_sdhc_set_NISTR_EMMC_CMDC_bit(a) hri_sdhc_set_NISTR_CMDC_bit(a) |
| 7164 | #define hri_sdhc_get_NISTR_EMMC_CMDC_bit(a) hri_sdhc_get_NISTR_CMDC_bit(a) |
| 7165 | #define hri_sdhc_write_NISTR_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISTR_CMDC_bit(a, b) |
| 7166 | #define hri_sdhc_clear_NISTR_EMMC_CMDC_bit(a) hri_sdhc_clear_NISTR_CMDC_bit(a) |
| 7167 | #define hri_sdhc_toggle_NISTR_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISTR_CMDC_bit(a) |
| 7168 | #define hri_sdhc_set_NISTR_EMMC_TRFC_bit(a) hri_sdhc_set_NISTR_TRFC_bit(a) |
| 7169 | #define hri_sdhc_get_NISTR_EMMC_TRFC_bit(a) hri_sdhc_get_NISTR_TRFC_bit(a) |
| 7170 | #define hri_sdhc_write_NISTR_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISTR_TRFC_bit(a, b) |
| 7171 | #define hri_sdhc_clear_NISTR_EMMC_TRFC_bit(a) hri_sdhc_clear_NISTR_TRFC_bit(a) |
| 7172 | #define hri_sdhc_toggle_NISTR_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISTR_TRFC_bit(a) |
| 7173 | #define hri_sdhc_set_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_set_NISTR_BLKGE_bit(a) |
| 7174 | #define hri_sdhc_get_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_get_NISTR_BLKGE_bit(a) |
| 7175 | #define hri_sdhc_write_NISTR_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISTR_BLKGE_bit(a, b) |
| 7176 | #define hri_sdhc_clear_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISTR_BLKGE_bit(a) |
| 7177 | #define hri_sdhc_toggle_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISTR_BLKGE_bit(a) |
| 7178 | #define hri_sdhc_set_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_set_NISTR_DMAINT_bit(a) |
| 7179 | #define hri_sdhc_get_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_get_NISTR_DMAINT_bit(a) |
| 7180 | #define hri_sdhc_write_NISTR_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISTR_DMAINT_bit(a, b) |
| 7181 | #define hri_sdhc_clear_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISTR_DMAINT_bit(a) |
| 7182 | #define hri_sdhc_toggle_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISTR_DMAINT_bit(a) |
| 7183 | #define hri_sdhc_set_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISTR_BWRRDY_bit(a) |
| 7184 | #define hri_sdhc_get_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISTR_BWRRDY_bit(a) |
| 7185 | #define hri_sdhc_write_NISTR_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISTR_BWRRDY_bit(a, b) |
| 7186 | #define hri_sdhc_clear_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISTR_BWRRDY_bit(a) |
| 7187 | #define hri_sdhc_toggle_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISTR_BWRRDY_bit(a) |
| 7188 | #define hri_sdhc_set_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISTR_BRDRDY_bit(a) |
| 7189 | #define hri_sdhc_get_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISTR_BRDRDY_bit(a) |
| 7190 | #define hri_sdhc_write_NISTR_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISTR_BRDRDY_bit(a, b) |
| 7191 | #define hri_sdhc_clear_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISTR_BRDRDY_bit(a) |
| 7192 | #define hri_sdhc_toggle_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISTR_BRDRDY_bit(a) |
| 7193 | #define hri_sdhc_set_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_set_NISTR_ERRINT_bit(a) |
| 7194 | #define hri_sdhc_get_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_get_NISTR_ERRINT_bit(a) |
| 7195 | #define hri_sdhc_write_NISTR_EMMC_ERRINT_bit(a, b) hri_sdhc_write_NISTR_ERRINT_bit(a, b) |
| 7196 | #define hri_sdhc_clear_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_clear_NISTR_ERRINT_bit(a) |
| 7197 | #define hri_sdhc_toggle_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_toggle_NISTR_ERRINT_bit(a) |
| 7198 | #define hri_sdhc_set_NISTR_EMMC_reg(a, b) hri_sdhc_set_NISTR_reg(a, b) |
| 7199 | #define hri_sdhc_get_NISTR_EMMC_reg(a, b) hri_sdhc_get_NISTR_reg(a, b) |
| 7200 | #define hri_sdhc_write_NISTR_EMMC_reg(a, b) hri_sdhc_write_NISTR_reg(a, b) |
| 7201 | #define hri_sdhc_clear_NISTR_EMMC_reg(a, b) hri_sdhc_clear_NISTR_reg(a, b) |
| 7202 | #define hri_sdhc_toggle_NISTR_EMMC_reg(a, b) hri_sdhc_toggle_NISTR_reg(a, b) |
| 7203 | #define hri_sdhc_read_NISTR_EMMC_reg(a) hri_sdhc_read_NISTR_reg(a) |
| 7204 | #define hri_sdhc_set_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISTR_CMDTEO_bit(a) |
| 7205 | #define hri_sdhc_get_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISTR_CMDTEO_bit(a) |
| 7206 | #define hri_sdhc_write_EISTR_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISTR_CMDTEO_bit(a, b) |
| 7207 | #define hri_sdhc_clear_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISTR_CMDTEO_bit(a) |
| 7208 | #define hri_sdhc_toggle_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISTR_CMDTEO_bit(a) |
| 7209 | #define hri_sdhc_set_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISTR_CMDCRC_bit(a) |
| 7210 | #define hri_sdhc_get_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISTR_CMDCRC_bit(a) |
| 7211 | #define hri_sdhc_write_EISTR_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISTR_CMDCRC_bit(a, b) |
| 7212 | #define hri_sdhc_clear_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISTR_CMDCRC_bit(a) |
| 7213 | #define hri_sdhc_toggle_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISTR_CMDCRC_bit(a) |
| 7214 | #define hri_sdhc_set_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_set_EISTR_CMDEND_bit(a) |
| 7215 | #define hri_sdhc_get_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_get_EISTR_CMDEND_bit(a) |
| 7216 | #define hri_sdhc_write_EISTR_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISTR_CMDEND_bit(a, b) |
| 7217 | #define hri_sdhc_clear_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISTR_CMDEND_bit(a) |
| 7218 | #define hri_sdhc_toggle_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISTR_CMDEND_bit(a) |
| 7219 | #define hri_sdhc_set_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISTR_CMDIDX_bit(a) |
| 7220 | #define hri_sdhc_get_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISTR_CMDIDX_bit(a) |
| 7221 | #define hri_sdhc_write_EISTR_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISTR_CMDIDX_bit(a, b) |
| 7222 | #define hri_sdhc_clear_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISTR_CMDIDX_bit(a) |
| 7223 | #define hri_sdhc_toggle_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISTR_CMDIDX_bit(a) |
| 7224 | #define hri_sdhc_set_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_set_EISTR_DATTEO_bit(a) |
| 7225 | #define hri_sdhc_get_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_get_EISTR_DATTEO_bit(a) |
| 7226 | #define hri_sdhc_write_EISTR_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISTR_DATTEO_bit(a, b) |
| 7227 | #define hri_sdhc_clear_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISTR_DATTEO_bit(a) |
| 7228 | #define hri_sdhc_toggle_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISTR_DATTEO_bit(a) |
| 7229 | #define hri_sdhc_set_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_set_EISTR_DATCRC_bit(a) |
| 7230 | #define hri_sdhc_get_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_get_EISTR_DATCRC_bit(a) |
| 7231 | #define hri_sdhc_write_EISTR_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISTR_DATCRC_bit(a, b) |
| 7232 | #define hri_sdhc_clear_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISTR_DATCRC_bit(a) |
| 7233 | #define hri_sdhc_toggle_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISTR_DATCRC_bit(a) |
| 7234 | #define hri_sdhc_set_EISTR_EMMC_DATEND_bit(a) hri_sdhc_set_EISTR_DATEND_bit(a) |
| 7235 | #define hri_sdhc_get_EISTR_EMMC_DATEND_bit(a) hri_sdhc_get_EISTR_DATEND_bit(a) |
| 7236 | #define hri_sdhc_write_EISTR_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISTR_DATEND_bit(a, b) |
| 7237 | #define hri_sdhc_clear_EISTR_EMMC_DATEND_bit(a) hri_sdhc_clear_EISTR_DATEND_bit(a) |
| 7238 | #define hri_sdhc_toggle_EISTR_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISTR_DATEND_bit(a) |
| 7239 | #define hri_sdhc_set_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_set_EISTR_CURLIM_bit(a) |
| 7240 | #define hri_sdhc_get_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_get_EISTR_CURLIM_bit(a) |
| 7241 | #define hri_sdhc_write_EISTR_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISTR_CURLIM_bit(a, b) |
| 7242 | #define hri_sdhc_clear_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISTR_CURLIM_bit(a) |
| 7243 | #define hri_sdhc_toggle_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISTR_CURLIM_bit(a) |
| 7244 | #define hri_sdhc_set_EISTR_EMMC_ACMD_bit(a) hri_sdhc_set_EISTR_ACMD_bit(a) |
| 7245 | #define hri_sdhc_get_EISTR_EMMC_ACMD_bit(a) hri_sdhc_get_EISTR_ACMD_bit(a) |
| 7246 | #define hri_sdhc_write_EISTR_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISTR_ACMD_bit(a, b) |
| 7247 | #define hri_sdhc_clear_EISTR_EMMC_ACMD_bit(a) hri_sdhc_clear_EISTR_ACMD_bit(a) |
| 7248 | #define hri_sdhc_toggle_EISTR_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISTR_ACMD_bit(a) |
| 7249 | #define hri_sdhc_set_EISTR_EMMC_ADMA_bit(a) hri_sdhc_set_EISTR_ADMA_bit(a) |
| 7250 | #define hri_sdhc_get_EISTR_EMMC_ADMA_bit(a) hri_sdhc_get_EISTR_ADMA_bit(a) |
| 7251 | #define hri_sdhc_write_EISTR_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISTR_ADMA_bit(a, b) |
| 7252 | #define hri_sdhc_clear_EISTR_EMMC_ADMA_bit(a) hri_sdhc_clear_EISTR_ADMA_bit(a) |
| 7253 | #define hri_sdhc_toggle_EISTR_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISTR_ADMA_bit(a) |
| 7254 | #define hri_sdhc_set_EISTR_EMMC_reg(a, b) hri_sdhc_set_EISTR_reg(a, b) |
| 7255 | #define hri_sdhc_get_EISTR_EMMC_reg(a, b) hri_sdhc_get_EISTR_reg(a, b) |
| 7256 | #define hri_sdhc_write_EISTR_EMMC_reg(a, b) hri_sdhc_write_EISTR_reg(a, b) |
| 7257 | #define hri_sdhc_clear_EISTR_EMMC_reg(a, b) hri_sdhc_clear_EISTR_reg(a, b) |
| 7258 | #define hri_sdhc_toggle_EISTR_EMMC_reg(a, b) hri_sdhc_toggle_EISTR_reg(a, b) |
| 7259 | #define hri_sdhc_read_EISTR_EMMC_reg(a) hri_sdhc_read_EISTR_reg(a) |
| 7260 | #define hri_sdhc_set_NISTER_EMMC_CMDC_bit(a) hri_sdhc_set_NISTER_CMDC_bit(a) |
| 7261 | #define hri_sdhc_get_NISTER_EMMC_CMDC_bit(a) hri_sdhc_get_NISTER_CMDC_bit(a) |
| 7262 | #define hri_sdhc_write_NISTER_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISTER_CMDC_bit(a, b) |
| 7263 | #define hri_sdhc_clear_NISTER_EMMC_CMDC_bit(a) hri_sdhc_clear_NISTER_CMDC_bit(a) |
| 7264 | #define hri_sdhc_toggle_NISTER_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISTER_CMDC_bit(a) |
| 7265 | #define hri_sdhc_set_NISTER_EMMC_TRFC_bit(a) hri_sdhc_set_NISTER_TRFC_bit(a) |
| 7266 | #define hri_sdhc_get_NISTER_EMMC_TRFC_bit(a) hri_sdhc_get_NISTER_TRFC_bit(a) |
| 7267 | #define hri_sdhc_write_NISTER_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISTER_TRFC_bit(a, b) |
| 7268 | #define hri_sdhc_clear_NISTER_EMMC_TRFC_bit(a) hri_sdhc_clear_NISTER_TRFC_bit(a) |
| 7269 | #define hri_sdhc_toggle_NISTER_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISTER_TRFC_bit(a) |
| 7270 | #define hri_sdhc_set_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_set_NISTER_BLKGE_bit(a) |
| 7271 | #define hri_sdhc_get_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_get_NISTER_BLKGE_bit(a) |
| 7272 | #define hri_sdhc_write_NISTER_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISTER_BLKGE_bit(a, b) |
| 7273 | #define hri_sdhc_clear_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISTER_BLKGE_bit(a) |
| 7274 | #define hri_sdhc_toggle_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISTER_BLKGE_bit(a) |
| 7275 | #define hri_sdhc_set_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_set_NISTER_DMAINT_bit(a) |
| 7276 | #define hri_sdhc_get_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_get_NISTER_DMAINT_bit(a) |
| 7277 | #define hri_sdhc_write_NISTER_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISTER_DMAINT_bit(a, b) |
| 7278 | #define hri_sdhc_clear_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISTER_DMAINT_bit(a) |
| 7279 | #define hri_sdhc_toggle_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISTER_DMAINT_bit(a) |
| 7280 | #define hri_sdhc_set_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISTER_BWRRDY_bit(a) |
| 7281 | #define hri_sdhc_get_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISTER_BWRRDY_bit(a) |
| 7282 | #define hri_sdhc_write_NISTER_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISTER_BWRRDY_bit(a, b) |
| 7283 | #define hri_sdhc_clear_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISTER_BWRRDY_bit(a) |
| 7284 | #define hri_sdhc_toggle_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISTER_BWRRDY_bit(a) |
| 7285 | #define hri_sdhc_set_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISTER_BRDRDY_bit(a) |
| 7286 | #define hri_sdhc_get_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISTER_BRDRDY_bit(a) |
| 7287 | #define hri_sdhc_write_NISTER_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISTER_BRDRDY_bit(a, b) |
| 7288 | #define hri_sdhc_clear_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISTER_BRDRDY_bit(a) |
| 7289 | #define hri_sdhc_toggle_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISTER_BRDRDY_bit(a) |
| 7290 | #define hri_sdhc_set_NISTER_EMMC_reg(a, b) hri_sdhc_set_NISTER_reg(a, b) |
| 7291 | #define hri_sdhc_get_NISTER_EMMC_reg(a, b) hri_sdhc_get_NISTER_reg(a, b) |
| 7292 | #define hri_sdhc_write_NISTER_EMMC_reg(a, b) hri_sdhc_write_NISTER_reg(a, b) |
| 7293 | #define hri_sdhc_clear_NISTER_EMMC_reg(a, b) hri_sdhc_clear_NISTER_reg(a, b) |
| 7294 | #define hri_sdhc_toggle_NISTER_EMMC_reg(a, b) hri_sdhc_toggle_NISTER_reg(a, b) |
| 7295 | #define hri_sdhc_read_NISTER_EMMC_reg(a) hri_sdhc_read_NISTER_reg(a) |
| 7296 | #define hri_sdhc_set_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISTER_CMDTEO_bit(a) |
| 7297 | #define hri_sdhc_get_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISTER_CMDTEO_bit(a) |
| 7298 | #define hri_sdhc_write_EISTER_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISTER_CMDTEO_bit(a, b) |
| 7299 | #define hri_sdhc_clear_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISTER_CMDTEO_bit(a) |
| 7300 | #define hri_sdhc_toggle_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISTER_CMDTEO_bit(a) |
| 7301 | #define hri_sdhc_set_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISTER_CMDCRC_bit(a) |
| 7302 | #define hri_sdhc_get_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISTER_CMDCRC_bit(a) |
| 7303 | #define hri_sdhc_write_EISTER_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISTER_CMDCRC_bit(a, b) |
| 7304 | #define hri_sdhc_clear_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISTER_CMDCRC_bit(a) |
| 7305 | #define hri_sdhc_toggle_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISTER_CMDCRC_bit(a) |
| 7306 | #define hri_sdhc_set_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_set_EISTER_CMDEND_bit(a) |
| 7307 | #define hri_sdhc_get_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_get_EISTER_CMDEND_bit(a) |
| 7308 | #define hri_sdhc_write_EISTER_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISTER_CMDEND_bit(a, b) |
| 7309 | #define hri_sdhc_clear_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISTER_CMDEND_bit(a) |
| 7310 | #define hri_sdhc_toggle_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISTER_CMDEND_bit(a) |
| 7311 | #define hri_sdhc_set_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISTER_CMDIDX_bit(a) |
| 7312 | #define hri_sdhc_get_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISTER_CMDIDX_bit(a) |
| 7313 | #define hri_sdhc_write_EISTER_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISTER_CMDIDX_bit(a, b) |
| 7314 | #define hri_sdhc_clear_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISTER_CMDIDX_bit(a) |
| 7315 | #define hri_sdhc_toggle_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISTER_CMDIDX_bit(a) |
| 7316 | #define hri_sdhc_set_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_set_EISTER_DATTEO_bit(a) |
| 7317 | #define hri_sdhc_get_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_get_EISTER_DATTEO_bit(a) |
| 7318 | #define hri_sdhc_write_EISTER_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISTER_DATTEO_bit(a, b) |
| 7319 | #define hri_sdhc_clear_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISTER_DATTEO_bit(a) |
| 7320 | #define hri_sdhc_toggle_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISTER_DATTEO_bit(a) |
| 7321 | #define hri_sdhc_set_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_set_EISTER_DATCRC_bit(a) |
| 7322 | #define hri_sdhc_get_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_get_EISTER_DATCRC_bit(a) |
| 7323 | #define hri_sdhc_write_EISTER_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISTER_DATCRC_bit(a, b) |
| 7324 | #define hri_sdhc_clear_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISTER_DATCRC_bit(a) |
| 7325 | #define hri_sdhc_toggle_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISTER_DATCRC_bit(a) |
| 7326 | #define hri_sdhc_set_EISTER_EMMC_DATEND_bit(a) hri_sdhc_set_EISTER_DATEND_bit(a) |
| 7327 | #define hri_sdhc_get_EISTER_EMMC_DATEND_bit(a) hri_sdhc_get_EISTER_DATEND_bit(a) |
| 7328 | #define hri_sdhc_write_EISTER_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISTER_DATEND_bit(a, b) |
| 7329 | #define hri_sdhc_clear_EISTER_EMMC_DATEND_bit(a) hri_sdhc_clear_EISTER_DATEND_bit(a) |
| 7330 | #define hri_sdhc_toggle_EISTER_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISTER_DATEND_bit(a) |
| 7331 | #define hri_sdhc_set_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_set_EISTER_CURLIM_bit(a) |
| 7332 | #define hri_sdhc_get_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_get_EISTER_CURLIM_bit(a) |
| 7333 | #define hri_sdhc_write_EISTER_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISTER_CURLIM_bit(a, b) |
| 7334 | #define hri_sdhc_clear_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISTER_CURLIM_bit(a) |
| 7335 | #define hri_sdhc_toggle_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISTER_CURLIM_bit(a) |
| 7336 | #define hri_sdhc_set_EISTER_EMMC_ACMD_bit(a) hri_sdhc_set_EISTER_ACMD_bit(a) |
| 7337 | #define hri_sdhc_get_EISTER_EMMC_ACMD_bit(a) hri_sdhc_get_EISTER_ACMD_bit(a) |
| 7338 | #define hri_sdhc_write_EISTER_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISTER_ACMD_bit(a, b) |
| 7339 | #define hri_sdhc_clear_EISTER_EMMC_ACMD_bit(a) hri_sdhc_clear_EISTER_ACMD_bit(a) |
| 7340 | #define hri_sdhc_toggle_EISTER_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISTER_ACMD_bit(a) |
| 7341 | #define hri_sdhc_set_EISTER_EMMC_ADMA_bit(a) hri_sdhc_set_EISTER_ADMA_bit(a) |
| 7342 | #define hri_sdhc_get_EISTER_EMMC_ADMA_bit(a) hri_sdhc_get_EISTER_ADMA_bit(a) |
| 7343 | #define hri_sdhc_write_EISTER_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISTER_ADMA_bit(a, b) |
| 7344 | #define hri_sdhc_clear_EISTER_EMMC_ADMA_bit(a) hri_sdhc_clear_EISTER_ADMA_bit(a) |
| 7345 | #define hri_sdhc_toggle_EISTER_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISTER_ADMA_bit(a) |
| 7346 | #define hri_sdhc_set_EISTER_EMMC_reg(a, b) hri_sdhc_set_EISTER_reg(a, b) |
| 7347 | #define hri_sdhc_get_EISTER_EMMC_reg(a, b) hri_sdhc_get_EISTER_reg(a, b) |
| 7348 | #define hri_sdhc_write_EISTER_EMMC_reg(a, b) hri_sdhc_write_EISTER_reg(a, b) |
| 7349 | #define hri_sdhc_clear_EISTER_EMMC_reg(a, b) hri_sdhc_clear_EISTER_reg(a, b) |
| 7350 | #define hri_sdhc_toggle_EISTER_EMMC_reg(a, b) hri_sdhc_toggle_EISTER_reg(a, b) |
| 7351 | #define hri_sdhc_read_EISTER_EMMC_reg(a) hri_sdhc_read_EISTER_reg(a) |
| 7352 | #define hri_sdhc_set_NISIER_EMMC_CMDC_bit(a) hri_sdhc_set_NISIER_CMDC_bit(a) |
| 7353 | #define hri_sdhc_get_NISIER_EMMC_CMDC_bit(a) hri_sdhc_get_NISIER_CMDC_bit(a) |
| 7354 | #define hri_sdhc_write_NISIER_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISIER_CMDC_bit(a, b) |
| 7355 | #define hri_sdhc_clear_NISIER_EMMC_CMDC_bit(a) hri_sdhc_clear_NISIER_CMDC_bit(a) |
| 7356 | #define hri_sdhc_toggle_NISIER_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISIER_CMDC_bit(a) |
| 7357 | #define hri_sdhc_set_NISIER_EMMC_TRFC_bit(a) hri_sdhc_set_NISIER_TRFC_bit(a) |
| 7358 | #define hri_sdhc_get_NISIER_EMMC_TRFC_bit(a) hri_sdhc_get_NISIER_TRFC_bit(a) |
| 7359 | #define hri_sdhc_write_NISIER_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISIER_TRFC_bit(a, b) |
| 7360 | #define hri_sdhc_clear_NISIER_EMMC_TRFC_bit(a) hri_sdhc_clear_NISIER_TRFC_bit(a) |
| 7361 | #define hri_sdhc_toggle_NISIER_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISIER_TRFC_bit(a) |
| 7362 | #define hri_sdhc_set_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_set_NISIER_BLKGE_bit(a) |
| 7363 | #define hri_sdhc_get_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_get_NISIER_BLKGE_bit(a) |
| 7364 | #define hri_sdhc_write_NISIER_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISIER_BLKGE_bit(a, b) |
| 7365 | #define hri_sdhc_clear_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISIER_BLKGE_bit(a) |
| 7366 | #define hri_sdhc_toggle_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISIER_BLKGE_bit(a) |
| 7367 | #define hri_sdhc_set_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_set_NISIER_DMAINT_bit(a) |
| 7368 | #define hri_sdhc_get_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_get_NISIER_DMAINT_bit(a) |
| 7369 | #define hri_sdhc_write_NISIER_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISIER_DMAINT_bit(a, b) |
| 7370 | #define hri_sdhc_clear_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISIER_DMAINT_bit(a) |
| 7371 | #define hri_sdhc_toggle_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISIER_DMAINT_bit(a) |
| 7372 | #define hri_sdhc_set_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISIER_BWRRDY_bit(a) |
| 7373 | #define hri_sdhc_get_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISIER_BWRRDY_bit(a) |
| 7374 | #define hri_sdhc_write_NISIER_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISIER_BWRRDY_bit(a, b) |
| 7375 | #define hri_sdhc_clear_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISIER_BWRRDY_bit(a) |
| 7376 | #define hri_sdhc_toggle_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISIER_BWRRDY_bit(a) |
| 7377 | #define hri_sdhc_set_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISIER_BRDRDY_bit(a) |
| 7378 | #define hri_sdhc_get_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISIER_BRDRDY_bit(a) |
| 7379 | #define hri_sdhc_write_NISIER_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISIER_BRDRDY_bit(a, b) |
| 7380 | #define hri_sdhc_clear_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISIER_BRDRDY_bit(a) |
| 7381 | #define hri_sdhc_toggle_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISIER_BRDRDY_bit(a) |
| 7382 | #define hri_sdhc_set_NISIER_EMMC_reg(a, b) hri_sdhc_set_NISIER_reg(a, b) |
| 7383 | #define hri_sdhc_get_NISIER_EMMC_reg(a, b) hri_sdhc_get_NISIER_reg(a, b) |
| 7384 | #define hri_sdhc_write_NISIER_EMMC_reg(a, b) hri_sdhc_write_NISIER_reg(a, b) |
| 7385 | #define hri_sdhc_clear_NISIER_EMMC_reg(a, b) hri_sdhc_clear_NISIER_reg(a, b) |
| 7386 | #define hri_sdhc_toggle_NISIER_EMMC_reg(a, b) hri_sdhc_toggle_NISIER_reg(a, b) |
| 7387 | #define hri_sdhc_read_NISIER_EMMC_reg(a) hri_sdhc_read_NISIER_reg(a) |
| 7388 | #define hri_sdhc_set_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISIER_CMDTEO_bit(a) |
| 7389 | #define hri_sdhc_get_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISIER_CMDTEO_bit(a) |
| 7390 | #define hri_sdhc_write_EISIER_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISIER_CMDTEO_bit(a, b) |
| 7391 | #define hri_sdhc_clear_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISIER_CMDTEO_bit(a) |
| 7392 | #define hri_sdhc_toggle_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISIER_CMDTEO_bit(a) |
| 7393 | #define hri_sdhc_set_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISIER_CMDCRC_bit(a) |
| 7394 | #define hri_sdhc_get_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISIER_CMDCRC_bit(a) |
| 7395 | #define hri_sdhc_write_EISIER_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISIER_CMDCRC_bit(a, b) |
| 7396 | #define hri_sdhc_clear_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISIER_CMDCRC_bit(a) |
| 7397 | #define hri_sdhc_toggle_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISIER_CMDCRC_bit(a) |
| 7398 | #define hri_sdhc_set_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_set_EISIER_CMDEND_bit(a) |
| 7399 | #define hri_sdhc_get_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_get_EISIER_CMDEND_bit(a) |
| 7400 | #define hri_sdhc_write_EISIER_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISIER_CMDEND_bit(a, b) |
| 7401 | #define hri_sdhc_clear_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISIER_CMDEND_bit(a) |
| 7402 | #define hri_sdhc_toggle_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISIER_CMDEND_bit(a) |
| 7403 | #define hri_sdhc_set_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISIER_CMDIDX_bit(a) |
| 7404 | #define hri_sdhc_get_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISIER_CMDIDX_bit(a) |
| 7405 | #define hri_sdhc_write_EISIER_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISIER_CMDIDX_bit(a, b) |
| 7406 | #define hri_sdhc_clear_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISIER_CMDIDX_bit(a) |
| 7407 | #define hri_sdhc_toggle_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISIER_CMDIDX_bit(a) |
| 7408 | #define hri_sdhc_set_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_set_EISIER_DATTEO_bit(a) |
| 7409 | #define hri_sdhc_get_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_get_EISIER_DATTEO_bit(a) |
| 7410 | #define hri_sdhc_write_EISIER_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISIER_DATTEO_bit(a, b) |
| 7411 | #define hri_sdhc_clear_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISIER_DATTEO_bit(a) |
| 7412 | #define hri_sdhc_toggle_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISIER_DATTEO_bit(a) |
| 7413 | #define hri_sdhc_set_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_set_EISIER_DATCRC_bit(a) |
| 7414 | #define hri_sdhc_get_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_get_EISIER_DATCRC_bit(a) |
| 7415 | #define hri_sdhc_write_EISIER_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISIER_DATCRC_bit(a, b) |
| 7416 | #define hri_sdhc_clear_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISIER_DATCRC_bit(a) |
| 7417 | #define hri_sdhc_toggle_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISIER_DATCRC_bit(a) |
| 7418 | #define hri_sdhc_set_EISIER_EMMC_DATEND_bit(a) hri_sdhc_set_EISIER_DATEND_bit(a) |
| 7419 | #define hri_sdhc_get_EISIER_EMMC_DATEND_bit(a) hri_sdhc_get_EISIER_DATEND_bit(a) |
| 7420 | #define hri_sdhc_write_EISIER_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISIER_DATEND_bit(a, b) |
| 7421 | #define hri_sdhc_clear_EISIER_EMMC_DATEND_bit(a) hri_sdhc_clear_EISIER_DATEND_bit(a) |
| 7422 | #define hri_sdhc_toggle_EISIER_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISIER_DATEND_bit(a) |
| 7423 | #define hri_sdhc_set_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_set_EISIER_CURLIM_bit(a) |
| 7424 | #define hri_sdhc_get_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_get_EISIER_CURLIM_bit(a) |
| 7425 | #define hri_sdhc_write_EISIER_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISIER_CURLIM_bit(a, b) |
| 7426 | #define hri_sdhc_clear_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISIER_CURLIM_bit(a) |
| 7427 | #define hri_sdhc_toggle_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISIER_CURLIM_bit(a) |
| 7428 | #define hri_sdhc_set_EISIER_EMMC_ACMD_bit(a) hri_sdhc_set_EISIER_ACMD_bit(a) |
| 7429 | #define hri_sdhc_get_EISIER_EMMC_ACMD_bit(a) hri_sdhc_get_EISIER_ACMD_bit(a) |
| 7430 | #define hri_sdhc_write_EISIER_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISIER_ACMD_bit(a, b) |
| 7431 | #define hri_sdhc_clear_EISIER_EMMC_ACMD_bit(a) hri_sdhc_clear_EISIER_ACMD_bit(a) |
| 7432 | #define hri_sdhc_toggle_EISIER_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISIER_ACMD_bit(a) |
| 7433 | #define hri_sdhc_set_EISIER_EMMC_ADMA_bit(a) hri_sdhc_set_EISIER_ADMA_bit(a) |
| 7434 | #define hri_sdhc_get_EISIER_EMMC_ADMA_bit(a) hri_sdhc_get_EISIER_ADMA_bit(a) |
| 7435 | #define hri_sdhc_write_EISIER_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISIER_ADMA_bit(a, b) |
| 7436 | #define hri_sdhc_clear_EISIER_EMMC_ADMA_bit(a) hri_sdhc_clear_EISIER_ADMA_bit(a) |
| 7437 | #define hri_sdhc_toggle_EISIER_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISIER_ADMA_bit(a) |
| 7438 | #define hri_sdhc_set_EISIER_EMMC_reg(a, b) hri_sdhc_set_EISIER_reg(a, b) |
| 7439 | #define hri_sdhc_get_EISIER_EMMC_reg(a, b) hri_sdhc_get_EISIER_reg(a, b) |
| 7440 | #define hri_sdhc_write_EISIER_EMMC_reg(a, b) hri_sdhc_write_EISIER_reg(a, b) |
| 7441 | #define hri_sdhc_clear_EISIER_EMMC_reg(a, b) hri_sdhc_clear_EISIER_reg(a, b) |
| 7442 | #define hri_sdhc_toggle_EISIER_EMMC_reg(a, b) hri_sdhc_toggle_EISIER_reg(a, b) |
| 7443 | #define hri_sdhc_read_EISIER_EMMC_reg(a) hri_sdhc_read_EISIER_reg(a) |
| 7444 | #define hri_sdhc_set_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_set_HC2R_EXTUN_bit(a) |
| 7445 | #define hri_sdhc_get_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_get_HC2R_EXTUN_bit(a) |
| 7446 | #define hri_sdhc_write_HC2R_EMMC_EXTUN_bit(a, b) hri_sdhc_write_HC2R_EXTUN_bit(a, b) |
| 7447 | #define hri_sdhc_clear_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_clear_HC2R_EXTUN_bit(a) |
| 7448 | #define hri_sdhc_toggle_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_toggle_HC2R_EXTUN_bit(a) |
| 7449 | #define hri_sdhc_set_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_set_HC2R_SLCKSEL_bit(a) |
| 7450 | #define hri_sdhc_get_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_get_HC2R_SLCKSEL_bit(a) |
| 7451 | #define hri_sdhc_write_HC2R_EMMC_SLCKSEL_bit(a, b) hri_sdhc_write_HC2R_SLCKSEL_bit(a, b) |
| 7452 | #define hri_sdhc_clear_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_clear_HC2R_SLCKSEL_bit(a) |
| 7453 | #define hri_sdhc_toggle_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_toggle_HC2R_SLCKSEL_bit(a) |
| 7454 | #define hri_sdhc_set_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_set_HC2R_PVALEN_bit(a) |
| 7455 | #define hri_sdhc_get_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_get_HC2R_PVALEN_bit(a) |
| 7456 | #define hri_sdhc_write_HC2R_EMMC_PVALEN_bit(a, b) hri_sdhc_write_HC2R_PVALEN_bit(a, b) |
| 7457 | #define hri_sdhc_clear_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_clear_HC2R_PVALEN_bit(a) |
| 7458 | #define hri_sdhc_toggle_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_toggle_HC2R_PVALEN_bit(a) |
| 7459 | #define hri_sdhc_set_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_set_HC2R_DRVSEL_bf(a, b) |
| 7460 | #define hri_sdhc_get_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_get_HC2R_DRVSEL_bf(a, b) |
| 7461 | #define hri_sdhc_write_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_write_HC2R_DRVSEL_bf(a, b) |
| 7462 | #define hri_sdhc_clear_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_clear_HC2R_DRVSEL_bf(a, b) |
| 7463 | #define hri_sdhc_toggle_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_toggle_HC2R_DRVSEL_bf(a, b) |
| 7464 | #define hri_sdhc_read_HC2R_EMMC_DRVSEL_bf(a) hri_sdhc_read_HC2R_DRVSEL_bf(a) |
| 7465 | #define hri_sdhc_set_HC2R_EMMC_reg(a, b) hri_sdhc_set_HC2R_reg(a, b) |
| 7466 | #define hri_sdhc_get_HC2R_EMMC_reg(a, b) hri_sdhc_get_HC2R_reg(a, b) |
| 7467 | #define hri_sdhc_write_HC2R_EMMC_reg(a, b) hri_sdhc_write_HC2R_reg(a, b) |
| 7468 | #define hri_sdhc_clear_HC2R_EMMC_reg(a, b) hri_sdhc_clear_HC2R_reg(a, b) |
| 7469 | #define hri_sdhc_toggle_HC2R_EMMC_reg(a, b) hri_sdhc_toggle_HC2R_reg(a, b) |
| 7470 | #define hri_sdhc_read_HC2R_EMMC_reg(a) hri_sdhc_read_HC2R_reg(a) |
| 7471 | |
| 7472 | #ifdef __cplusplus |
| 7473 | } |
| 7474 | #endif |
| 7475 | |
| 7476 | #endif /* _HRI_SDHC_E54_H_INCLUDED */ |
| 7477 | #endif /* _SAME54_SDHC_COMPONENT_ */ |