Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM DSU |
| 5 | * |
Harald Welte | 9bb8bfe | 2019-05-17 16:10:00 +0200 | [diff] [blame] | 6 | * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_DSU_COMPONENT_ |
| 35 | #ifndef _HRI_DSU_E54_H_INCLUDED_ |
| 36 | #define _HRI_DSU_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_DSU_CRITICAL_SECTIONS) |
| 46 | #define DSU_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define DSU_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define DSU_CRITICAL_SECTION_ENTER() |
| 50 | #define DSU_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint32_t hri_dsu_addr_reg_t; |
| 54 | typedef uint32_t hri_dsu_cfg_reg_t; |
| 55 | typedef uint32_t hri_dsu_cid0_reg_t; |
| 56 | typedef uint32_t hri_dsu_cid1_reg_t; |
| 57 | typedef uint32_t hri_dsu_cid2_reg_t; |
| 58 | typedef uint32_t hri_dsu_cid3_reg_t; |
| 59 | typedef uint32_t hri_dsu_data_reg_t; |
| 60 | typedef uint32_t hri_dsu_dcc_reg_t; |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 61 | typedef uint32_t hri_dsu_did_reg_t; |
| 62 | typedef uint32_t hri_dsu_end_reg_t; |
| 63 | typedef uint32_t hri_dsu_entry0_reg_t; |
| 64 | typedef uint32_t hri_dsu_entry1_reg_t; |
| 65 | typedef uint32_t hri_dsu_length_reg_t; |
| 66 | typedef uint32_t hri_dsu_memtype_reg_t; |
| 67 | typedef uint32_t hri_dsu_pid0_reg_t; |
| 68 | typedef uint32_t hri_dsu_pid1_reg_t; |
| 69 | typedef uint32_t hri_dsu_pid2_reg_t; |
| 70 | typedef uint32_t hri_dsu_pid3_reg_t; |
| 71 | typedef uint32_t hri_dsu_pid4_reg_t; |
| 72 | typedef uint32_t hri_dsu_pid5_reg_t; |
| 73 | typedef uint32_t hri_dsu_pid6_reg_t; |
| 74 | typedef uint32_t hri_dsu_pid7_reg_t; |
| 75 | typedef uint8_t hri_dsu_ctrl_reg_t; |
| 76 | typedef uint8_t hri_dsu_statusa_reg_t; |
| 77 | typedef uint8_t hri_dsu_statusb_reg_t; |
| 78 | |
| 79 | static inline bool hri_dsu_get_STATUSB_PROT_bit(const void *const hw) |
| 80 | { |
| 81 | return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_PROT) >> DSU_STATUSB_PROT_Pos; |
| 82 | } |
| 83 | |
| 84 | static inline bool hri_dsu_get_STATUSB_DBGPRES_bit(const void *const hw) |
| 85 | { |
| 86 | return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DBGPRES) >> DSU_STATUSB_DBGPRES_Pos; |
| 87 | } |
| 88 | |
| 89 | static inline bool hri_dsu_get_STATUSB_DCCD0_bit(const void *const hw) |
| 90 | { |
| 91 | return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD0) >> DSU_STATUSB_DCCD0_Pos; |
| 92 | } |
| 93 | |
| 94 | static inline bool hri_dsu_get_STATUSB_DCCD1_bit(const void *const hw) |
| 95 | { |
| 96 | return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD1) >> DSU_STATUSB_DCCD1_Pos; |
| 97 | } |
| 98 | |
| 99 | static inline bool hri_dsu_get_STATUSB_HPE_bit(const void *const hw) |
| 100 | { |
| 101 | return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_HPE) >> DSU_STATUSB_HPE_Pos; |
| 102 | } |
| 103 | |
| 104 | static inline bool hri_dsu_get_STATUSB_CELCK_bit(const void *const hw) |
| 105 | { |
| 106 | return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_CELCK) >> DSU_STATUSB_CELCK_Pos; |
| 107 | } |
| 108 | |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 109 | static inline hri_dsu_statusb_reg_t hri_dsu_get_STATUSB_reg(const void *const hw, hri_dsu_statusb_reg_t mask) |
| 110 | { |
| 111 | uint8_t tmp; |
| 112 | tmp = ((Dsu *)hw)->STATUSB.reg; |
| 113 | tmp &= mask; |
| 114 | return tmp; |
| 115 | } |
| 116 | |
| 117 | static inline hri_dsu_statusb_reg_t hri_dsu_read_STATUSB_reg(const void *const hw) |
| 118 | { |
| 119 | return ((Dsu *)hw)->STATUSB.reg; |
| 120 | } |
| 121 | |
| 122 | static inline hri_dsu_did_reg_t hri_dsu_get_DID_DEVSEL_bf(const void *const hw, hri_dsu_did_reg_t mask) |
| 123 | { |
| 124 | return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL(mask)) >> DSU_DID_DEVSEL_Pos; |
| 125 | } |
| 126 | |
| 127 | static inline hri_dsu_did_reg_t hri_dsu_read_DID_DEVSEL_bf(const void *const hw) |
| 128 | { |
| 129 | return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL_Msk) >> DSU_DID_DEVSEL_Pos; |
| 130 | } |
| 131 | |
| 132 | static inline hri_dsu_did_reg_t hri_dsu_get_DID_REVISION_bf(const void *const hw, hri_dsu_did_reg_t mask) |
| 133 | { |
| 134 | return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION(mask)) >> DSU_DID_REVISION_Pos; |
| 135 | } |
| 136 | |
| 137 | static inline hri_dsu_did_reg_t hri_dsu_read_DID_REVISION_bf(const void *const hw) |
| 138 | { |
| 139 | return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION_Msk) >> DSU_DID_REVISION_Pos; |
| 140 | } |
| 141 | |
| 142 | static inline hri_dsu_did_reg_t hri_dsu_get_DID_DIE_bf(const void *const hw, hri_dsu_did_reg_t mask) |
| 143 | { |
| 144 | return (((Dsu *)hw)->DID.reg & DSU_DID_DIE(mask)) >> DSU_DID_DIE_Pos; |
| 145 | } |
| 146 | |
| 147 | static inline hri_dsu_did_reg_t hri_dsu_read_DID_DIE_bf(const void *const hw) |
| 148 | { |
| 149 | return (((Dsu *)hw)->DID.reg & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos; |
| 150 | } |
| 151 | |
| 152 | static inline hri_dsu_did_reg_t hri_dsu_get_DID_SERIES_bf(const void *const hw, hri_dsu_did_reg_t mask) |
| 153 | { |
| 154 | return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES(mask)) >> DSU_DID_SERIES_Pos; |
| 155 | } |
| 156 | |
| 157 | static inline hri_dsu_did_reg_t hri_dsu_read_DID_SERIES_bf(const void *const hw) |
| 158 | { |
| 159 | return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES_Msk) >> DSU_DID_SERIES_Pos; |
| 160 | } |
| 161 | |
| 162 | static inline hri_dsu_did_reg_t hri_dsu_get_DID_FAMILY_bf(const void *const hw, hri_dsu_did_reg_t mask) |
| 163 | { |
| 164 | return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY(mask)) >> DSU_DID_FAMILY_Pos; |
| 165 | } |
| 166 | |
| 167 | static inline hri_dsu_did_reg_t hri_dsu_read_DID_FAMILY_bf(const void *const hw) |
| 168 | { |
| 169 | return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY_Msk) >> DSU_DID_FAMILY_Pos; |
| 170 | } |
| 171 | |
| 172 | static inline hri_dsu_did_reg_t hri_dsu_get_DID_PROCESSOR_bf(const void *const hw, hri_dsu_did_reg_t mask) |
| 173 | { |
| 174 | return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR(mask)) >> DSU_DID_PROCESSOR_Pos; |
| 175 | } |
| 176 | |
| 177 | static inline hri_dsu_did_reg_t hri_dsu_read_DID_PROCESSOR_bf(const void *const hw) |
| 178 | { |
| 179 | return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR_Msk) >> DSU_DID_PROCESSOR_Pos; |
| 180 | } |
| 181 | |
| 182 | static inline hri_dsu_did_reg_t hri_dsu_get_DID_reg(const void *const hw, hri_dsu_did_reg_t mask) |
| 183 | { |
| 184 | uint32_t tmp; |
| 185 | tmp = ((Dsu *)hw)->DID.reg; |
| 186 | tmp &= mask; |
| 187 | return tmp; |
| 188 | } |
| 189 | |
| 190 | static inline hri_dsu_did_reg_t hri_dsu_read_DID_reg(const void *const hw) |
| 191 | { |
| 192 | return ((Dsu *)hw)->DID.reg; |
| 193 | } |
| 194 | |
| 195 | static inline bool hri_dsu_get_ENTRY0_EPRES_bit(const void *const hw) |
| 196 | { |
| 197 | return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_EPRES) >> DSU_ENTRY0_EPRES_Pos; |
| 198 | } |
| 199 | |
| 200 | static inline bool hri_dsu_get_ENTRY0_FMT_bit(const void *const hw) |
| 201 | { |
| 202 | return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_FMT) >> DSU_ENTRY0_FMT_Pos; |
| 203 | } |
| 204 | |
| 205 | static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_ADDOFF_bf(const void *const hw, hri_dsu_entry0_reg_t mask) |
| 206 | { |
| 207 | return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF(mask)) >> DSU_ENTRY0_ADDOFF_Pos; |
| 208 | } |
| 209 | |
| 210 | static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_ADDOFF_bf(const void *const hw) |
| 211 | { |
| 212 | return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF_Msk) >> DSU_ENTRY0_ADDOFF_Pos; |
| 213 | } |
| 214 | |
| 215 | static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_reg(const void *const hw, hri_dsu_entry0_reg_t mask) |
| 216 | { |
| 217 | uint32_t tmp; |
| 218 | tmp = ((Dsu *)hw)->ENTRY0.reg; |
| 219 | tmp &= mask; |
| 220 | return tmp; |
| 221 | } |
| 222 | |
| 223 | static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_reg(const void *const hw) |
| 224 | { |
| 225 | return ((Dsu *)hw)->ENTRY0.reg; |
| 226 | } |
| 227 | |
| 228 | static inline hri_dsu_entry1_reg_t hri_dsu_get_ENTRY1_reg(const void *const hw, hri_dsu_entry1_reg_t mask) |
| 229 | { |
| 230 | uint32_t tmp; |
| 231 | tmp = ((Dsu *)hw)->ENTRY1.reg; |
| 232 | tmp &= mask; |
| 233 | return tmp; |
| 234 | } |
| 235 | |
| 236 | static inline hri_dsu_entry1_reg_t hri_dsu_read_ENTRY1_reg(const void *const hw) |
| 237 | { |
| 238 | return ((Dsu *)hw)->ENTRY1.reg; |
| 239 | } |
| 240 | |
| 241 | static inline hri_dsu_end_reg_t hri_dsu_get_END_END_bf(const void *const hw, hri_dsu_end_reg_t mask) |
| 242 | { |
| 243 | return (((Dsu *)hw)->END.reg & DSU_END_END(mask)) >> DSU_END_END_Pos; |
| 244 | } |
| 245 | |
| 246 | static inline hri_dsu_end_reg_t hri_dsu_read_END_END_bf(const void *const hw) |
| 247 | { |
| 248 | return (((Dsu *)hw)->END.reg & DSU_END_END_Msk) >> DSU_END_END_Pos; |
| 249 | } |
| 250 | |
| 251 | static inline hri_dsu_end_reg_t hri_dsu_get_END_reg(const void *const hw, hri_dsu_end_reg_t mask) |
| 252 | { |
| 253 | uint32_t tmp; |
| 254 | tmp = ((Dsu *)hw)->END.reg; |
| 255 | tmp &= mask; |
| 256 | return tmp; |
| 257 | } |
| 258 | |
| 259 | static inline hri_dsu_end_reg_t hri_dsu_read_END_reg(const void *const hw) |
| 260 | { |
| 261 | return ((Dsu *)hw)->END.reg; |
| 262 | } |
| 263 | |
| 264 | static inline bool hri_dsu_get_MEMTYPE_SMEMP_bit(const void *const hw) |
| 265 | { |
| 266 | return (((Dsu *)hw)->MEMTYPE.reg & DSU_MEMTYPE_SMEMP) >> DSU_MEMTYPE_SMEMP_Pos; |
| 267 | } |
| 268 | |
| 269 | static inline hri_dsu_memtype_reg_t hri_dsu_get_MEMTYPE_reg(const void *const hw, hri_dsu_memtype_reg_t mask) |
| 270 | { |
| 271 | uint32_t tmp; |
| 272 | tmp = ((Dsu *)hw)->MEMTYPE.reg; |
| 273 | tmp &= mask; |
| 274 | return tmp; |
| 275 | } |
| 276 | |
| 277 | static inline hri_dsu_memtype_reg_t hri_dsu_read_MEMTYPE_reg(const void *const hw) |
| 278 | { |
| 279 | return ((Dsu *)hw)->MEMTYPE.reg; |
| 280 | } |
| 281 | |
| 282 | static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_JEPCC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) |
| 283 | { |
| 284 | return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC(mask)) >> DSU_PID4_JEPCC_Pos; |
| 285 | } |
| 286 | |
| 287 | static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_JEPCC_bf(const void *const hw) |
| 288 | { |
| 289 | return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC_Msk) >> DSU_PID4_JEPCC_Pos; |
| 290 | } |
| 291 | |
| 292 | static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_FKBC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) |
| 293 | { |
| 294 | return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC(mask)) >> DSU_PID4_FKBC_Pos; |
| 295 | } |
| 296 | |
| 297 | static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_FKBC_bf(const void *const hw) |
| 298 | { |
| 299 | return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC_Msk) >> DSU_PID4_FKBC_Pos; |
| 300 | } |
| 301 | |
| 302 | static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_reg(const void *const hw, hri_dsu_pid4_reg_t mask) |
| 303 | { |
| 304 | uint32_t tmp; |
| 305 | tmp = ((Dsu *)hw)->PID4.reg; |
| 306 | tmp &= mask; |
| 307 | return tmp; |
| 308 | } |
| 309 | |
| 310 | static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_reg(const void *const hw) |
| 311 | { |
| 312 | return ((Dsu *)hw)->PID4.reg; |
| 313 | } |
| 314 | |
| 315 | static inline hri_dsu_pid5_reg_t hri_dsu_get_PID5_reg(const void *const hw, hri_dsu_pid5_reg_t mask) |
| 316 | { |
| 317 | uint32_t tmp; |
| 318 | tmp = ((Dsu *)hw)->PID5.reg; |
| 319 | tmp &= mask; |
| 320 | return tmp; |
| 321 | } |
| 322 | |
| 323 | static inline hri_dsu_pid5_reg_t hri_dsu_read_PID5_reg(const void *const hw) |
| 324 | { |
| 325 | return ((Dsu *)hw)->PID5.reg; |
| 326 | } |
| 327 | |
| 328 | static inline hri_dsu_pid6_reg_t hri_dsu_get_PID6_reg(const void *const hw, hri_dsu_pid6_reg_t mask) |
| 329 | { |
| 330 | uint32_t tmp; |
| 331 | tmp = ((Dsu *)hw)->PID6.reg; |
| 332 | tmp &= mask; |
| 333 | return tmp; |
| 334 | } |
| 335 | |
| 336 | static inline hri_dsu_pid6_reg_t hri_dsu_read_PID6_reg(const void *const hw) |
| 337 | { |
| 338 | return ((Dsu *)hw)->PID6.reg; |
| 339 | } |
| 340 | |
| 341 | static inline hri_dsu_pid7_reg_t hri_dsu_get_PID7_reg(const void *const hw, hri_dsu_pid7_reg_t mask) |
| 342 | { |
| 343 | uint32_t tmp; |
| 344 | tmp = ((Dsu *)hw)->PID7.reg; |
| 345 | tmp &= mask; |
| 346 | return tmp; |
| 347 | } |
| 348 | |
| 349 | static inline hri_dsu_pid7_reg_t hri_dsu_read_PID7_reg(const void *const hw) |
| 350 | { |
| 351 | return ((Dsu *)hw)->PID7.reg; |
| 352 | } |
| 353 | |
| 354 | static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_PARTNBL_bf(const void *const hw, hri_dsu_pid0_reg_t mask) |
| 355 | { |
| 356 | return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL(mask)) >> DSU_PID0_PARTNBL_Pos; |
| 357 | } |
| 358 | |
| 359 | static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_PARTNBL_bf(const void *const hw) |
| 360 | { |
| 361 | return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL_Msk) >> DSU_PID0_PARTNBL_Pos; |
| 362 | } |
| 363 | |
| 364 | static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_reg(const void *const hw, hri_dsu_pid0_reg_t mask) |
| 365 | { |
| 366 | uint32_t tmp; |
| 367 | tmp = ((Dsu *)hw)->PID0.reg; |
| 368 | tmp &= mask; |
| 369 | return tmp; |
| 370 | } |
| 371 | |
| 372 | static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_reg(const void *const hw) |
| 373 | { |
| 374 | return ((Dsu *)hw)->PID0.reg; |
| 375 | } |
| 376 | |
| 377 | static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_PARTNBH_bf(const void *const hw, hri_dsu_pid1_reg_t mask) |
| 378 | { |
| 379 | return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH(mask)) >> DSU_PID1_PARTNBH_Pos; |
| 380 | } |
| 381 | |
| 382 | static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_PARTNBH_bf(const void *const hw) |
| 383 | { |
| 384 | return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH_Msk) >> DSU_PID1_PARTNBH_Pos; |
| 385 | } |
| 386 | |
| 387 | static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_JEPIDCL_bf(const void *const hw, hri_dsu_pid1_reg_t mask) |
| 388 | { |
| 389 | return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL(mask)) >> DSU_PID1_JEPIDCL_Pos; |
| 390 | } |
| 391 | |
| 392 | static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_JEPIDCL_bf(const void *const hw) |
| 393 | { |
| 394 | return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL_Msk) >> DSU_PID1_JEPIDCL_Pos; |
| 395 | } |
| 396 | |
| 397 | static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_reg(const void *const hw, hri_dsu_pid1_reg_t mask) |
| 398 | { |
| 399 | uint32_t tmp; |
| 400 | tmp = ((Dsu *)hw)->PID1.reg; |
| 401 | tmp &= mask; |
| 402 | return tmp; |
| 403 | } |
| 404 | |
| 405 | static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_reg(const void *const hw) |
| 406 | { |
| 407 | return ((Dsu *)hw)->PID1.reg; |
| 408 | } |
| 409 | |
| 410 | static inline bool hri_dsu_get_PID2_JEPU_bit(const void *const hw) |
| 411 | { |
| 412 | return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPU) >> DSU_PID2_JEPU_Pos; |
| 413 | } |
| 414 | |
| 415 | static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_JEPIDCH_bf(const void *const hw, hri_dsu_pid2_reg_t mask) |
| 416 | { |
| 417 | return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH(mask)) >> DSU_PID2_JEPIDCH_Pos; |
| 418 | } |
| 419 | |
| 420 | static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_JEPIDCH_bf(const void *const hw) |
| 421 | { |
| 422 | return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH_Msk) >> DSU_PID2_JEPIDCH_Pos; |
| 423 | } |
| 424 | |
| 425 | static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_REVISION_bf(const void *const hw, hri_dsu_pid2_reg_t mask) |
| 426 | { |
| 427 | return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION(mask)) >> DSU_PID2_REVISION_Pos; |
| 428 | } |
| 429 | |
| 430 | static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_REVISION_bf(const void *const hw) |
| 431 | { |
| 432 | return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION_Msk) >> DSU_PID2_REVISION_Pos; |
| 433 | } |
| 434 | |
| 435 | static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_reg(const void *const hw, hri_dsu_pid2_reg_t mask) |
| 436 | { |
| 437 | uint32_t tmp; |
| 438 | tmp = ((Dsu *)hw)->PID2.reg; |
| 439 | tmp &= mask; |
| 440 | return tmp; |
| 441 | } |
| 442 | |
| 443 | static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_reg(const void *const hw) |
| 444 | { |
| 445 | return ((Dsu *)hw)->PID2.reg; |
| 446 | } |
| 447 | |
| 448 | static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_CUSMOD_bf(const void *const hw, hri_dsu_pid3_reg_t mask) |
| 449 | { |
| 450 | return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD(mask)) >> DSU_PID3_CUSMOD_Pos; |
| 451 | } |
| 452 | |
| 453 | static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_CUSMOD_bf(const void *const hw) |
| 454 | { |
| 455 | return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD_Msk) >> DSU_PID3_CUSMOD_Pos; |
| 456 | } |
| 457 | |
| 458 | static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_REVAND_bf(const void *const hw, hri_dsu_pid3_reg_t mask) |
| 459 | { |
| 460 | return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND(mask)) >> DSU_PID3_REVAND_Pos; |
| 461 | } |
| 462 | |
| 463 | static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_REVAND_bf(const void *const hw) |
| 464 | { |
| 465 | return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND_Msk) >> DSU_PID3_REVAND_Pos; |
| 466 | } |
| 467 | |
| 468 | static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_reg(const void *const hw, hri_dsu_pid3_reg_t mask) |
| 469 | { |
| 470 | uint32_t tmp; |
| 471 | tmp = ((Dsu *)hw)->PID3.reg; |
| 472 | tmp &= mask; |
| 473 | return tmp; |
| 474 | } |
| 475 | |
| 476 | static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_reg(const void *const hw) |
| 477 | { |
| 478 | return ((Dsu *)hw)->PID3.reg; |
| 479 | } |
| 480 | |
| 481 | static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_PREAMBLEB0_bf(const void *const hw, hri_dsu_cid0_reg_t mask) |
| 482 | { |
| 483 | return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0(mask)) >> DSU_CID0_PREAMBLEB0_Pos; |
| 484 | } |
| 485 | |
| 486 | static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_PREAMBLEB0_bf(const void *const hw) |
| 487 | { |
| 488 | return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0_Msk) >> DSU_CID0_PREAMBLEB0_Pos; |
| 489 | } |
| 490 | |
| 491 | static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_reg(const void *const hw, hri_dsu_cid0_reg_t mask) |
| 492 | { |
| 493 | uint32_t tmp; |
| 494 | tmp = ((Dsu *)hw)->CID0.reg; |
| 495 | tmp &= mask; |
| 496 | return tmp; |
| 497 | } |
| 498 | |
| 499 | static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_reg(const void *const hw) |
| 500 | { |
| 501 | return ((Dsu *)hw)->CID0.reg; |
| 502 | } |
| 503 | |
| 504 | static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_PREAMBLE_bf(const void *const hw, hri_dsu_cid1_reg_t mask) |
| 505 | { |
| 506 | return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE(mask)) >> DSU_CID1_PREAMBLE_Pos; |
| 507 | } |
| 508 | |
| 509 | static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_PREAMBLE_bf(const void *const hw) |
| 510 | { |
| 511 | return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE_Msk) >> DSU_CID1_PREAMBLE_Pos; |
| 512 | } |
| 513 | |
| 514 | static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_CCLASS_bf(const void *const hw, hri_dsu_cid1_reg_t mask) |
| 515 | { |
| 516 | return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS(mask)) >> DSU_CID1_CCLASS_Pos; |
| 517 | } |
| 518 | |
| 519 | static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_CCLASS_bf(const void *const hw) |
| 520 | { |
| 521 | return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS_Msk) >> DSU_CID1_CCLASS_Pos; |
| 522 | } |
| 523 | |
| 524 | static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_reg(const void *const hw, hri_dsu_cid1_reg_t mask) |
| 525 | { |
| 526 | uint32_t tmp; |
| 527 | tmp = ((Dsu *)hw)->CID1.reg; |
| 528 | tmp &= mask; |
| 529 | return tmp; |
| 530 | } |
| 531 | |
| 532 | static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_reg(const void *const hw) |
| 533 | { |
| 534 | return ((Dsu *)hw)->CID1.reg; |
| 535 | } |
| 536 | |
| 537 | static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_PREAMBLEB2_bf(const void *const hw, hri_dsu_cid2_reg_t mask) |
| 538 | { |
| 539 | return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2(mask)) >> DSU_CID2_PREAMBLEB2_Pos; |
| 540 | } |
| 541 | |
| 542 | static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_PREAMBLEB2_bf(const void *const hw) |
| 543 | { |
| 544 | return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2_Msk) >> DSU_CID2_PREAMBLEB2_Pos; |
| 545 | } |
| 546 | |
| 547 | static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_reg(const void *const hw, hri_dsu_cid2_reg_t mask) |
| 548 | { |
| 549 | uint32_t tmp; |
| 550 | tmp = ((Dsu *)hw)->CID2.reg; |
| 551 | tmp &= mask; |
| 552 | return tmp; |
| 553 | } |
| 554 | |
| 555 | static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_reg(const void *const hw) |
| 556 | { |
| 557 | return ((Dsu *)hw)->CID2.reg; |
| 558 | } |
| 559 | |
| 560 | static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_PREAMBLEB3_bf(const void *const hw, hri_dsu_cid3_reg_t mask) |
| 561 | { |
| 562 | return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3(mask)) >> DSU_CID3_PREAMBLEB3_Pos; |
| 563 | } |
| 564 | |
| 565 | static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_PREAMBLEB3_bf(const void *const hw) |
| 566 | { |
| 567 | return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3_Msk) >> DSU_CID3_PREAMBLEB3_Pos; |
| 568 | } |
| 569 | |
| 570 | static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_reg(const void *const hw, hri_dsu_cid3_reg_t mask) |
| 571 | { |
| 572 | uint32_t tmp; |
| 573 | tmp = ((Dsu *)hw)->CID3.reg; |
| 574 | tmp &= mask; |
| 575 | return tmp; |
| 576 | } |
| 577 | |
| 578 | static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_reg(const void *const hw) |
| 579 | { |
| 580 | return ((Dsu *)hw)->CID3.reg; |
| 581 | } |
| 582 | |
| 583 | static inline void hri_dsu_set_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) |
| 584 | { |
| 585 | DSU_CRITICAL_SECTION_ENTER(); |
| 586 | ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_AMOD(mask); |
| 587 | DSU_CRITICAL_SECTION_LEAVE(); |
| 588 | } |
| 589 | |
| 590 | static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) |
| 591 | { |
| 592 | uint32_t tmp; |
| 593 | tmp = ((Dsu *)hw)->ADDR.reg; |
| 594 | tmp = (tmp & DSU_ADDR_AMOD(mask)) >> DSU_ADDR_AMOD_Pos; |
| 595 | return tmp; |
| 596 | } |
| 597 | |
| 598 | static inline void hri_dsu_write_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t data) |
| 599 | { |
| 600 | uint32_t tmp; |
| 601 | DSU_CRITICAL_SECTION_ENTER(); |
| 602 | tmp = ((Dsu *)hw)->ADDR.reg; |
| 603 | tmp &= ~DSU_ADDR_AMOD_Msk; |
| 604 | tmp |= DSU_ADDR_AMOD(data); |
| 605 | ((Dsu *)hw)->ADDR.reg = tmp; |
| 606 | DSU_CRITICAL_SECTION_LEAVE(); |
| 607 | } |
| 608 | |
| 609 | static inline void hri_dsu_clear_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) |
| 610 | { |
| 611 | DSU_CRITICAL_SECTION_ENTER(); |
| 612 | ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_AMOD(mask); |
| 613 | DSU_CRITICAL_SECTION_LEAVE(); |
| 614 | } |
| 615 | |
| 616 | static inline void hri_dsu_toggle_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) |
| 617 | { |
| 618 | DSU_CRITICAL_SECTION_ENTER(); |
| 619 | ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_AMOD(mask); |
| 620 | DSU_CRITICAL_SECTION_LEAVE(); |
| 621 | } |
| 622 | |
| 623 | static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_AMOD_bf(const void *const hw) |
| 624 | { |
| 625 | uint32_t tmp; |
| 626 | tmp = ((Dsu *)hw)->ADDR.reg; |
| 627 | tmp = (tmp & DSU_ADDR_AMOD_Msk) >> DSU_ADDR_AMOD_Pos; |
| 628 | return tmp; |
| 629 | } |
| 630 | |
| 631 | static inline void hri_dsu_set_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) |
| 632 | { |
| 633 | DSU_CRITICAL_SECTION_ENTER(); |
| 634 | ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_ADDR(mask); |
| 635 | DSU_CRITICAL_SECTION_LEAVE(); |
| 636 | } |
| 637 | |
| 638 | static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) |
| 639 | { |
| 640 | uint32_t tmp; |
| 641 | tmp = ((Dsu *)hw)->ADDR.reg; |
| 642 | tmp = (tmp & DSU_ADDR_ADDR(mask)) >> DSU_ADDR_ADDR_Pos; |
| 643 | return tmp; |
| 644 | } |
| 645 | |
| 646 | static inline void hri_dsu_write_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t data) |
| 647 | { |
| 648 | uint32_t tmp; |
| 649 | DSU_CRITICAL_SECTION_ENTER(); |
| 650 | tmp = ((Dsu *)hw)->ADDR.reg; |
| 651 | tmp &= ~DSU_ADDR_ADDR_Msk; |
| 652 | tmp |= DSU_ADDR_ADDR(data); |
| 653 | ((Dsu *)hw)->ADDR.reg = tmp; |
| 654 | DSU_CRITICAL_SECTION_LEAVE(); |
| 655 | } |
| 656 | |
| 657 | static inline void hri_dsu_clear_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) |
| 658 | { |
| 659 | DSU_CRITICAL_SECTION_ENTER(); |
| 660 | ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_ADDR(mask); |
| 661 | DSU_CRITICAL_SECTION_LEAVE(); |
| 662 | } |
| 663 | |
| 664 | static inline void hri_dsu_toggle_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) |
| 665 | { |
| 666 | DSU_CRITICAL_SECTION_ENTER(); |
| 667 | ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_ADDR(mask); |
| 668 | DSU_CRITICAL_SECTION_LEAVE(); |
| 669 | } |
| 670 | |
| 671 | static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_ADDR_bf(const void *const hw) |
| 672 | { |
| 673 | uint32_t tmp; |
| 674 | tmp = ((Dsu *)hw)->ADDR.reg; |
| 675 | tmp = (tmp & DSU_ADDR_ADDR_Msk) >> DSU_ADDR_ADDR_Pos; |
| 676 | return tmp; |
| 677 | } |
| 678 | |
| 679 | static inline void hri_dsu_set_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) |
| 680 | { |
| 681 | DSU_CRITICAL_SECTION_ENTER(); |
| 682 | ((Dsu *)hw)->ADDR.reg |= mask; |
| 683 | DSU_CRITICAL_SECTION_LEAVE(); |
| 684 | } |
| 685 | |
| 686 | static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) |
| 687 | { |
| 688 | uint32_t tmp; |
| 689 | tmp = ((Dsu *)hw)->ADDR.reg; |
| 690 | tmp &= mask; |
| 691 | return tmp; |
| 692 | } |
| 693 | |
| 694 | static inline void hri_dsu_write_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t data) |
| 695 | { |
| 696 | DSU_CRITICAL_SECTION_ENTER(); |
| 697 | ((Dsu *)hw)->ADDR.reg = data; |
| 698 | DSU_CRITICAL_SECTION_LEAVE(); |
| 699 | } |
| 700 | |
| 701 | static inline void hri_dsu_clear_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) |
| 702 | { |
| 703 | DSU_CRITICAL_SECTION_ENTER(); |
| 704 | ((Dsu *)hw)->ADDR.reg &= ~mask; |
| 705 | DSU_CRITICAL_SECTION_LEAVE(); |
| 706 | } |
| 707 | |
| 708 | static inline void hri_dsu_toggle_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) |
| 709 | { |
| 710 | DSU_CRITICAL_SECTION_ENTER(); |
| 711 | ((Dsu *)hw)->ADDR.reg ^= mask; |
| 712 | DSU_CRITICAL_SECTION_LEAVE(); |
| 713 | } |
| 714 | |
| 715 | static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_reg(const void *const hw) |
| 716 | { |
| 717 | return ((Dsu *)hw)->ADDR.reg; |
| 718 | } |
| 719 | |
| 720 | static inline void hri_dsu_set_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) |
| 721 | { |
| 722 | DSU_CRITICAL_SECTION_ENTER(); |
| 723 | ((Dsu *)hw)->LENGTH.reg |= DSU_LENGTH_LENGTH(mask); |
| 724 | DSU_CRITICAL_SECTION_LEAVE(); |
| 725 | } |
| 726 | |
| 727 | static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) |
| 728 | { |
| 729 | uint32_t tmp; |
| 730 | tmp = ((Dsu *)hw)->LENGTH.reg; |
| 731 | tmp = (tmp & DSU_LENGTH_LENGTH(mask)) >> DSU_LENGTH_LENGTH_Pos; |
| 732 | return tmp; |
| 733 | } |
| 734 | |
| 735 | static inline void hri_dsu_write_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t data) |
| 736 | { |
| 737 | uint32_t tmp; |
| 738 | DSU_CRITICAL_SECTION_ENTER(); |
| 739 | tmp = ((Dsu *)hw)->LENGTH.reg; |
| 740 | tmp &= ~DSU_LENGTH_LENGTH_Msk; |
| 741 | tmp |= DSU_LENGTH_LENGTH(data); |
| 742 | ((Dsu *)hw)->LENGTH.reg = tmp; |
| 743 | DSU_CRITICAL_SECTION_LEAVE(); |
| 744 | } |
| 745 | |
| 746 | static inline void hri_dsu_clear_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) |
| 747 | { |
| 748 | DSU_CRITICAL_SECTION_ENTER(); |
| 749 | ((Dsu *)hw)->LENGTH.reg &= ~DSU_LENGTH_LENGTH(mask); |
| 750 | DSU_CRITICAL_SECTION_LEAVE(); |
| 751 | } |
| 752 | |
| 753 | static inline void hri_dsu_toggle_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) |
| 754 | { |
| 755 | DSU_CRITICAL_SECTION_ENTER(); |
| 756 | ((Dsu *)hw)->LENGTH.reg ^= DSU_LENGTH_LENGTH(mask); |
| 757 | DSU_CRITICAL_SECTION_LEAVE(); |
| 758 | } |
| 759 | |
| 760 | static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_LENGTH_bf(const void *const hw) |
| 761 | { |
| 762 | uint32_t tmp; |
| 763 | tmp = ((Dsu *)hw)->LENGTH.reg; |
| 764 | tmp = (tmp & DSU_LENGTH_LENGTH_Msk) >> DSU_LENGTH_LENGTH_Pos; |
| 765 | return tmp; |
| 766 | } |
| 767 | |
| 768 | static inline void hri_dsu_set_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) |
| 769 | { |
| 770 | DSU_CRITICAL_SECTION_ENTER(); |
| 771 | ((Dsu *)hw)->LENGTH.reg |= mask; |
| 772 | DSU_CRITICAL_SECTION_LEAVE(); |
| 773 | } |
| 774 | |
| 775 | static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) |
| 776 | { |
| 777 | uint32_t tmp; |
| 778 | tmp = ((Dsu *)hw)->LENGTH.reg; |
| 779 | tmp &= mask; |
| 780 | return tmp; |
| 781 | } |
| 782 | |
| 783 | static inline void hri_dsu_write_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t data) |
| 784 | { |
| 785 | DSU_CRITICAL_SECTION_ENTER(); |
| 786 | ((Dsu *)hw)->LENGTH.reg = data; |
| 787 | DSU_CRITICAL_SECTION_LEAVE(); |
| 788 | } |
| 789 | |
| 790 | static inline void hri_dsu_clear_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) |
| 791 | { |
| 792 | DSU_CRITICAL_SECTION_ENTER(); |
| 793 | ((Dsu *)hw)->LENGTH.reg &= ~mask; |
| 794 | DSU_CRITICAL_SECTION_LEAVE(); |
| 795 | } |
| 796 | |
| 797 | static inline void hri_dsu_toggle_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) |
| 798 | { |
| 799 | DSU_CRITICAL_SECTION_ENTER(); |
| 800 | ((Dsu *)hw)->LENGTH.reg ^= mask; |
| 801 | DSU_CRITICAL_SECTION_LEAVE(); |
| 802 | } |
| 803 | |
| 804 | static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_reg(const void *const hw) |
| 805 | { |
| 806 | return ((Dsu *)hw)->LENGTH.reg; |
| 807 | } |
| 808 | |
| 809 | static inline void hri_dsu_set_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) |
| 810 | { |
| 811 | DSU_CRITICAL_SECTION_ENTER(); |
| 812 | ((Dsu *)hw)->DATA.reg |= DSU_DATA_DATA(mask); |
| 813 | DSU_CRITICAL_SECTION_LEAVE(); |
| 814 | } |
| 815 | |
| 816 | static inline hri_dsu_data_reg_t hri_dsu_get_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) |
| 817 | { |
| 818 | uint32_t tmp; |
| 819 | tmp = ((Dsu *)hw)->DATA.reg; |
| 820 | tmp = (tmp & DSU_DATA_DATA(mask)) >> DSU_DATA_DATA_Pos; |
| 821 | return tmp; |
| 822 | } |
| 823 | |
| 824 | static inline void hri_dsu_write_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t data) |
| 825 | { |
| 826 | uint32_t tmp; |
| 827 | DSU_CRITICAL_SECTION_ENTER(); |
| 828 | tmp = ((Dsu *)hw)->DATA.reg; |
| 829 | tmp &= ~DSU_DATA_DATA_Msk; |
| 830 | tmp |= DSU_DATA_DATA(data); |
| 831 | ((Dsu *)hw)->DATA.reg = tmp; |
| 832 | DSU_CRITICAL_SECTION_LEAVE(); |
| 833 | } |
| 834 | |
| 835 | static inline void hri_dsu_clear_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) |
| 836 | { |
| 837 | DSU_CRITICAL_SECTION_ENTER(); |
| 838 | ((Dsu *)hw)->DATA.reg &= ~DSU_DATA_DATA(mask); |
| 839 | DSU_CRITICAL_SECTION_LEAVE(); |
| 840 | } |
| 841 | |
| 842 | static inline void hri_dsu_toggle_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) |
| 843 | { |
| 844 | DSU_CRITICAL_SECTION_ENTER(); |
| 845 | ((Dsu *)hw)->DATA.reg ^= DSU_DATA_DATA(mask); |
| 846 | DSU_CRITICAL_SECTION_LEAVE(); |
| 847 | } |
| 848 | |
| 849 | static inline hri_dsu_data_reg_t hri_dsu_read_DATA_DATA_bf(const void *const hw) |
| 850 | { |
| 851 | uint32_t tmp; |
| 852 | tmp = ((Dsu *)hw)->DATA.reg; |
| 853 | tmp = (tmp & DSU_DATA_DATA_Msk) >> DSU_DATA_DATA_Pos; |
| 854 | return tmp; |
| 855 | } |
| 856 | |
| 857 | static inline void hri_dsu_set_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) |
| 858 | { |
| 859 | DSU_CRITICAL_SECTION_ENTER(); |
| 860 | ((Dsu *)hw)->DATA.reg |= mask; |
| 861 | DSU_CRITICAL_SECTION_LEAVE(); |
| 862 | } |
| 863 | |
| 864 | static inline hri_dsu_data_reg_t hri_dsu_get_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) |
| 865 | { |
| 866 | uint32_t tmp; |
| 867 | tmp = ((Dsu *)hw)->DATA.reg; |
| 868 | tmp &= mask; |
| 869 | return tmp; |
| 870 | } |
| 871 | |
| 872 | static inline void hri_dsu_write_DATA_reg(const void *const hw, hri_dsu_data_reg_t data) |
| 873 | { |
| 874 | DSU_CRITICAL_SECTION_ENTER(); |
| 875 | ((Dsu *)hw)->DATA.reg = data; |
| 876 | DSU_CRITICAL_SECTION_LEAVE(); |
| 877 | } |
| 878 | |
| 879 | static inline void hri_dsu_clear_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) |
| 880 | { |
| 881 | DSU_CRITICAL_SECTION_ENTER(); |
| 882 | ((Dsu *)hw)->DATA.reg &= ~mask; |
| 883 | DSU_CRITICAL_SECTION_LEAVE(); |
| 884 | } |
| 885 | |
| 886 | static inline void hri_dsu_toggle_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) |
| 887 | { |
| 888 | DSU_CRITICAL_SECTION_ENTER(); |
| 889 | ((Dsu *)hw)->DATA.reg ^= mask; |
| 890 | DSU_CRITICAL_SECTION_LEAVE(); |
| 891 | } |
| 892 | |
| 893 | static inline hri_dsu_data_reg_t hri_dsu_read_DATA_reg(const void *const hw) |
| 894 | { |
| 895 | return ((Dsu *)hw)->DATA.reg; |
| 896 | } |
| 897 | |
| 898 | static inline void hri_dsu_set_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) |
| 899 | { |
| 900 | DSU_CRITICAL_SECTION_ENTER(); |
| 901 | ((Dsu *)hw)->DCC[index].reg |= DSU_DCC_DATA(mask); |
| 902 | DSU_CRITICAL_SECTION_LEAVE(); |
| 903 | } |
| 904 | |
| 905 | static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) |
| 906 | { |
| 907 | uint32_t tmp; |
| 908 | tmp = ((Dsu *)hw)->DCC[index].reg; |
| 909 | tmp = (tmp & DSU_DCC_DATA(mask)) >> DSU_DCC_DATA_Pos; |
| 910 | return tmp; |
| 911 | } |
| 912 | |
| 913 | static inline void hri_dsu_write_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) |
| 914 | { |
| 915 | uint32_t tmp; |
| 916 | DSU_CRITICAL_SECTION_ENTER(); |
| 917 | tmp = ((Dsu *)hw)->DCC[index].reg; |
| 918 | tmp &= ~DSU_DCC_DATA_Msk; |
| 919 | tmp |= DSU_DCC_DATA(data); |
| 920 | ((Dsu *)hw)->DCC[index].reg = tmp; |
| 921 | DSU_CRITICAL_SECTION_LEAVE(); |
| 922 | } |
| 923 | |
| 924 | static inline void hri_dsu_clear_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) |
| 925 | { |
| 926 | DSU_CRITICAL_SECTION_ENTER(); |
| 927 | ((Dsu *)hw)->DCC[index].reg &= ~DSU_DCC_DATA(mask); |
| 928 | DSU_CRITICAL_SECTION_LEAVE(); |
| 929 | } |
| 930 | |
| 931 | static inline void hri_dsu_toggle_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) |
| 932 | { |
| 933 | DSU_CRITICAL_SECTION_ENTER(); |
| 934 | ((Dsu *)hw)->DCC[index].reg ^= DSU_DCC_DATA(mask); |
| 935 | DSU_CRITICAL_SECTION_LEAVE(); |
| 936 | } |
| 937 | |
| 938 | static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_DATA_bf(const void *const hw, uint8_t index) |
| 939 | { |
| 940 | uint32_t tmp; |
| 941 | tmp = ((Dsu *)hw)->DCC[index].reg; |
| 942 | tmp = (tmp & DSU_DCC_DATA_Msk) >> DSU_DCC_DATA_Pos; |
| 943 | return tmp; |
| 944 | } |
| 945 | |
| 946 | static inline void hri_dsu_set_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) |
| 947 | { |
| 948 | DSU_CRITICAL_SECTION_ENTER(); |
| 949 | ((Dsu *)hw)->DCC[index].reg |= mask; |
| 950 | DSU_CRITICAL_SECTION_LEAVE(); |
| 951 | } |
| 952 | |
| 953 | static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) |
| 954 | { |
| 955 | uint32_t tmp; |
| 956 | tmp = ((Dsu *)hw)->DCC[index].reg; |
| 957 | tmp &= mask; |
| 958 | return tmp; |
| 959 | } |
| 960 | |
| 961 | static inline void hri_dsu_write_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) |
| 962 | { |
| 963 | DSU_CRITICAL_SECTION_ENTER(); |
| 964 | ((Dsu *)hw)->DCC[index].reg = data; |
| 965 | DSU_CRITICAL_SECTION_LEAVE(); |
| 966 | } |
| 967 | |
| 968 | static inline void hri_dsu_clear_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) |
| 969 | { |
| 970 | DSU_CRITICAL_SECTION_ENTER(); |
| 971 | ((Dsu *)hw)->DCC[index].reg &= ~mask; |
| 972 | DSU_CRITICAL_SECTION_LEAVE(); |
| 973 | } |
| 974 | |
| 975 | static inline void hri_dsu_toggle_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) |
| 976 | { |
| 977 | DSU_CRITICAL_SECTION_ENTER(); |
| 978 | ((Dsu *)hw)->DCC[index].reg ^= mask; |
| 979 | DSU_CRITICAL_SECTION_LEAVE(); |
| 980 | } |
| 981 | |
| 982 | static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_reg(const void *const hw, uint8_t index) |
| 983 | { |
| 984 | return ((Dsu *)hw)->DCC[index].reg; |
| 985 | } |
| 986 | |
| 987 | static inline void hri_dsu_set_CFG_ETBRAMEN_bit(const void *const hw) |
| 988 | { |
| 989 | DSU_CRITICAL_SECTION_ENTER(); |
| 990 | ((Dsu *)hw)->CFG.reg |= DSU_CFG_ETBRAMEN; |
| 991 | DSU_CRITICAL_SECTION_LEAVE(); |
| 992 | } |
| 993 | |
| 994 | static inline bool hri_dsu_get_CFG_ETBRAMEN_bit(const void *const hw) |
| 995 | { |
| 996 | uint32_t tmp; |
| 997 | tmp = ((Dsu *)hw)->CFG.reg; |
| 998 | tmp = (tmp & DSU_CFG_ETBRAMEN) >> DSU_CFG_ETBRAMEN_Pos; |
| 999 | return (bool)tmp; |
| 1000 | } |
| 1001 | |
| 1002 | static inline void hri_dsu_write_CFG_ETBRAMEN_bit(const void *const hw, bool value) |
| 1003 | { |
| 1004 | uint32_t tmp; |
| 1005 | DSU_CRITICAL_SECTION_ENTER(); |
| 1006 | tmp = ((Dsu *)hw)->CFG.reg; |
| 1007 | tmp &= ~DSU_CFG_ETBRAMEN; |
| 1008 | tmp |= value << DSU_CFG_ETBRAMEN_Pos; |
| 1009 | ((Dsu *)hw)->CFG.reg = tmp; |
| 1010 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1011 | } |
| 1012 | |
| 1013 | static inline void hri_dsu_clear_CFG_ETBRAMEN_bit(const void *const hw) |
| 1014 | { |
| 1015 | DSU_CRITICAL_SECTION_ENTER(); |
| 1016 | ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_ETBRAMEN; |
| 1017 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1018 | } |
| 1019 | |
| 1020 | static inline void hri_dsu_toggle_CFG_ETBRAMEN_bit(const void *const hw) |
| 1021 | { |
| 1022 | DSU_CRITICAL_SECTION_ENTER(); |
| 1023 | ((Dsu *)hw)->CFG.reg ^= DSU_CFG_ETBRAMEN; |
| 1024 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1025 | } |
| 1026 | |
| 1027 | static inline void hri_dsu_set_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) |
| 1028 | { |
| 1029 | DSU_CRITICAL_SECTION_ENTER(); |
| 1030 | ((Dsu *)hw)->CFG.reg |= DSU_CFG_LQOS(mask); |
| 1031 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1032 | } |
| 1033 | |
| 1034 | static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) |
| 1035 | { |
| 1036 | uint32_t tmp; |
| 1037 | tmp = ((Dsu *)hw)->CFG.reg; |
| 1038 | tmp = (tmp & DSU_CFG_LQOS(mask)) >> DSU_CFG_LQOS_Pos; |
| 1039 | return tmp; |
| 1040 | } |
| 1041 | |
| 1042 | static inline void hri_dsu_write_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t data) |
| 1043 | { |
| 1044 | uint32_t tmp; |
| 1045 | DSU_CRITICAL_SECTION_ENTER(); |
| 1046 | tmp = ((Dsu *)hw)->CFG.reg; |
| 1047 | tmp &= ~DSU_CFG_LQOS_Msk; |
| 1048 | tmp |= DSU_CFG_LQOS(data); |
| 1049 | ((Dsu *)hw)->CFG.reg = tmp; |
| 1050 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1051 | } |
| 1052 | |
| 1053 | static inline void hri_dsu_clear_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) |
| 1054 | { |
| 1055 | DSU_CRITICAL_SECTION_ENTER(); |
| 1056 | ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_LQOS(mask); |
| 1057 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1058 | } |
| 1059 | |
| 1060 | static inline void hri_dsu_toggle_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) |
| 1061 | { |
| 1062 | DSU_CRITICAL_SECTION_ENTER(); |
| 1063 | ((Dsu *)hw)->CFG.reg ^= DSU_CFG_LQOS(mask); |
| 1064 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1065 | } |
| 1066 | |
| 1067 | static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_LQOS_bf(const void *const hw) |
| 1068 | { |
| 1069 | uint32_t tmp; |
| 1070 | tmp = ((Dsu *)hw)->CFG.reg; |
| 1071 | tmp = (tmp & DSU_CFG_LQOS_Msk) >> DSU_CFG_LQOS_Pos; |
| 1072 | return tmp; |
| 1073 | } |
| 1074 | |
| 1075 | static inline void hri_dsu_set_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) |
| 1076 | { |
| 1077 | DSU_CRITICAL_SECTION_ENTER(); |
| 1078 | ((Dsu *)hw)->CFG.reg |= DSU_CFG_DCCDMALEVEL(mask); |
| 1079 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1080 | } |
| 1081 | |
| 1082 | static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) |
| 1083 | { |
| 1084 | uint32_t tmp; |
| 1085 | tmp = ((Dsu *)hw)->CFG.reg; |
| 1086 | tmp = (tmp & DSU_CFG_DCCDMALEVEL(mask)) >> DSU_CFG_DCCDMALEVEL_Pos; |
| 1087 | return tmp; |
| 1088 | } |
| 1089 | |
| 1090 | static inline void hri_dsu_write_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t data) |
| 1091 | { |
| 1092 | uint32_t tmp; |
| 1093 | DSU_CRITICAL_SECTION_ENTER(); |
| 1094 | tmp = ((Dsu *)hw)->CFG.reg; |
| 1095 | tmp &= ~DSU_CFG_DCCDMALEVEL_Msk; |
| 1096 | tmp |= DSU_CFG_DCCDMALEVEL(data); |
| 1097 | ((Dsu *)hw)->CFG.reg = tmp; |
| 1098 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1099 | } |
| 1100 | |
| 1101 | static inline void hri_dsu_clear_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) |
| 1102 | { |
| 1103 | DSU_CRITICAL_SECTION_ENTER(); |
| 1104 | ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_DCCDMALEVEL(mask); |
| 1105 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1106 | } |
| 1107 | |
| 1108 | static inline void hri_dsu_toggle_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) |
| 1109 | { |
| 1110 | DSU_CRITICAL_SECTION_ENTER(); |
| 1111 | ((Dsu *)hw)->CFG.reg ^= DSU_CFG_DCCDMALEVEL(mask); |
| 1112 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1113 | } |
| 1114 | |
| 1115 | static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_DCCDMALEVEL_bf(const void *const hw) |
| 1116 | { |
| 1117 | uint32_t tmp; |
| 1118 | tmp = ((Dsu *)hw)->CFG.reg; |
| 1119 | tmp = (tmp & DSU_CFG_DCCDMALEVEL_Msk) >> DSU_CFG_DCCDMALEVEL_Pos; |
| 1120 | return tmp; |
| 1121 | } |
| 1122 | |
| 1123 | static inline void hri_dsu_set_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) |
| 1124 | { |
| 1125 | DSU_CRITICAL_SECTION_ENTER(); |
| 1126 | ((Dsu *)hw)->CFG.reg |= mask; |
| 1127 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1128 | } |
| 1129 | |
| 1130 | static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) |
| 1131 | { |
| 1132 | uint32_t tmp; |
| 1133 | tmp = ((Dsu *)hw)->CFG.reg; |
| 1134 | tmp &= mask; |
| 1135 | return tmp; |
| 1136 | } |
| 1137 | |
| 1138 | static inline void hri_dsu_write_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t data) |
| 1139 | { |
| 1140 | DSU_CRITICAL_SECTION_ENTER(); |
| 1141 | ((Dsu *)hw)->CFG.reg = data; |
| 1142 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1143 | } |
| 1144 | |
| 1145 | static inline void hri_dsu_clear_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) |
| 1146 | { |
| 1147 | DSU_CRITICAL_SECTION_ENTER(); |
| 1148 | ((Dsu *)hw)->CFG.reg &= ~mask; |
| 1149 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1150 | } |
| 1151 | |
| 1152 | static inline void hri_dsu_toggle_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) |
| 1153 | { |
| 1154 | DSU_CRITICAL_SECTION_ENTER(); |
| 1155 | ((Dsu *)hw)->CFG.reg ^= mask; |
| 1156 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1157 | } |
| 1158 | |
| 1159 | static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_reg(const void *const hw) |
| 1160 | { |
| 1161 | return ((Dsu *)hw)->CFG.reg; |
| 1162 | } |
| 1163 | |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1164 | static inline bool hri_dsu_get_STATUSA_DONE_bit(const void *const hw) |
| 1165 | { |
| 1166 | return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_DONE) >> DSU_STATUSA_DONE_Pos; |
| 1167 | } |
| 1168 | |
| 1169 | static inline void hri_dsu_clear_STATUSA_DONE_bit(const void *const hw) |
| 1170 | { |
| 1171 | DSU_CRITICAL_SECTION_ENTER(); |
| 1172 | ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_DONE; |
| 1173 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1174 | } |
| 1175 | |
| 1176 | static inline bool hri_dsu_get_STATUSA_CRSTEXT_bit(const void *const hw) |
| 1177 | { |
| 1178 | return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_CRSTEXT) >> DSU_STATUSA_CRSTEXT_Pos; |
| 1179 | } |
| 1180 | |
| 1181 | static inline void hri_dsu_clear_STATUSA_CRSTEXT_bit(const void *const hw) |
| 1182 | { |
| 1183 | DSU_CRITICAL_SECTION_ENTER(); |
| 1184 | ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_CRSTEXT; |
| 1185 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1186 | } |
| 1187 | |
| 1188 | static inline bool hri_dsu_get_STATUSA_BERR_bit(const void *const hw) |
| 1189 | { |
| 1190 | return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_BERR) >> DSU_STATUSA_BERR_Pos; |
| 1191 | } |
| 1192 | |
| 1193 | static inline void hri_dsu_clear_STATUSA_BERR_bit(const void *const hw) |
| 1194 | { |
| 1195 | DSU_CRITICAL_SECTION_ENTER(); |
| 1196 | ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_BERR; |
| 1197 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1198 | } |
| 1199 | |
| 1200 | static inline bool hri_dsu_get_STATUSA_FAIL_bit(const void *const hw) |
| 1201 | { |
| 1202 | return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_FAIL) >> DSU_STATUSA_FAIL_Pos; |
| 1203 | } |
| 1204 | |
| 1205 | static inline void hri_dsu_clear_STATUSA_FAIL_bit(const void *const hw) |
| 1206 | { |
| 1207 | DSU_CRITICAL_SECTION_ENTER(); |
| 1208 | ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_FAIL; |
| 1209 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1210 | } |
| 1211 | |
| 1212 | static inline bool hri_dsu_get_STATUSA_PERR_bit(const void *const hw) |
| 1213 | { |
| 1214 | return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_PERR) >> DSU_STATUSA_PERR_Pos; |
| 1215 | } |
| 1216 | |
| 1217 | static inline void hri_dsu_clear_STATUSA_PERR_bit(const void *const hw) |
| 1218 | { |
| 1219 | DSU_CRITICAL_SECTION_ENTER(); |
| 1220 | ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_PERR; |
| 1221 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1222 | } |
| 1223 | |
| 1224 | static inline hri_dsu_statusa_reg_t hri_dsu_get_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) |
| 1225 | { |
| 1226 | uint8_t tmp; |
| 1227 | tmp = ((Dsu *)hw)->STATUSA.reg; |
| 1228 | tmp &= mask; |
| 1229 | return tmp; |
| 1230 | } |
| 1231 | |
| 1232 | static inline void hri_dsu_clear_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) |
| 1233 | { |
| 1234 | DSU_CRITICAL_SECTION_ENTER(); |
| 1235 | ((Dsu *)hw)->STATUSA.reg = mask; |
| 1236 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1237 | } |
| 1238 | |
| 1239 | static inline hri_dsu_statusa_reg_t hri_dsu_read_STATUSA_reg(const void *const hw) |
| 1240 | { |
| 1241 | return ((Dsu *)hw)->STATUSA.reg; |
| 1242 | } |
| 1243 | |
| 1244 | static inline void hri_dsu_write_CTRL_reg(const void *const hw, hri_dsu_ctrl_reg_t data) |
| 1245 | { |
| 1246 | DSU_CRITICAL_SECTION_ENTER(); |
| 1247 | ((Dsu *)hw)->CTRL.reg = data; |
| 1248 | DSU_CRITICAL_SECTION_LEAVE(); |
| 1249 | } |
| 1250 | |
| 1251 | #ifdef __cplusplus |
| 1252 | } |
| 1253 | #endif |
| 1254 | |
| 1255 | #endif /* _HRI_DSU_E54_H_INCLUDED */ |
| 1256 | #endif /* _SAME54_DSU_COMPONENT_ */ |