Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM SERCOM |
| 5 | * |
Kévin Redon | a6c44f1 | 2019-06-06 16:41:21 +0200 | [diff] [blame] | 6 | * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries. |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_SERCOM_COMPONENT_ |
| 35 | #ifndef _HRI_SERCOM_E54_H_INCLUDED_ |
| 36 | #define _HRI_SERCOM_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_SERCOM_CRITICAL_SECTIONS) |
| 46 | #define SERCOM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define SERCOM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define SERCOM_CRITICAL_SECTION_ENTER() |
| 50 | #define SERCOM_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint16_t hri_sercomi2cm_status_reg_t; |
| 54 | typedef uint16_t hri_sercomi2cs_length_reg_t; |
| 55 | typedef uint16_t hri_sercomi2cs_status_reg_t; |
| 56 | typedef uint16_t hri_sercomspi_length_reg_t; |
| 57 | typedef uint16_t hri_sercomspi_status_reg_t; |
| 58 | typedef uint16_t hri_sercomusart_baud_reg_t; |
| 59 | typedef uint16_t hri_sercomusart_length_reg_t; |
| 60 | typedef uint16_t hri_sercomusart_status_reg_t; |
| 61 | typedef uint32_t hri_sercomi2cm_addr_reg_t; |
| 62 | typedef uint32_t hri_sercomi2cm_baud_reg_t; |
| 63 | typedef uint32_t hri_sercomi2cm_ctrla_reg_t; |
| 64 | typedef uint32_t hri_sercomi2cm_ctrlb_reg_t; |
| 65 | typedef uint32_t hri_sercomi2cm_ctrlc_reg_t; |
| 66 | typedef uint32_t hri_sercomi2cm_data_reg_t; |
| 67 | typedef uint32_t hri_sercomi2cm_syncbusy_reg_t; |
| 68 | typedef uint32_t hri_sercomi2cs_addr_reg_t; |
| 69 | typedef uint32_t hri_sercomi2cs_ctrla_reg_t; |
| 70 | typedef uint32_t hri_sercomi2cs_ctrlb_reg_t; |
| 71 | typedef uint32_t hri_sercomi2cs_ctrlc_reg_t; |
| 72 | typedef uint32_t hri_sercomi2cs_data_reg_t; |
| 73 | typedef uint32_t hri_sercomi2cs_syncbusy_reg_t; |
| 74 | typedef uint32_t hri_sercomspi_addr_reg_t; |
| 75 | typedef uint32_t hri_sercomspi_ctrla_reg_t; |
| 76 | typedef uint32_t hri_sercomspi_ctrlb_reg_t; |
| 77 | typedef uint32_t hri_sercomspi_ctrlc_reg_t; |
| 78 | typedef uint32_t hri_sercomspi_data_reg_t; |
| 79 | typedef uint32_t hri_sercomspi_syncbusy_reg_t; |
| 80 | typedef uint32_t hri_sercomusart_ctrla_reg_t; |
| 81 | typedef uint32_t hri_sercomusart_ctrlb_reg_t; |
| 82 | typedef uint32_t hri_sercomusart_ctrlc_reg_t; |
| 83 | typedef uint32_t hri_sercomusart_data_reg_t; |
| 84 | typedef uint32_t hri_sercomusart_syncbusy_reg_t; |
| 85 | typedef uint8_t hri_sercomi2cm_dbgctrl_reg_t; |
| 86 | typedef uint8_t hri_sercomi2cm_intenset_reg_t; |
| 87 | typedef uint8_t hri_sercomi2cm_intflag_reg_t; |
| 88 | typedef uint8_t hri_sercomi2cs_intenset_reg_t; |
| 89 | typedef uint8_t hri_sercomi2cs_intflag_reg_t; |
| 90 | typedef uint8_t hri_sercomspi_baud_reg_t; |
| 91 | typedef uint8_t hri_sercomspi_dbgctrl_reg_t; |
| 92 | typedef uint8_t hri_sercomspi_intenset_reg_t; |
| 93 | typedef uint8_t hri_sercomspi_intflag_reg_t; |
| 94 | typedef uint8_t hri_sercomusart_dbgctrl_reg_t; |
| 95 | typedef uint8_t hri_sercomusart_intenset_reg_t; |
| 96 | typedef uint8_t hri_sercomusart_intflag_reg_t; |
| 97 | typedef uint8_t hri_sercomusart_rxerrcnt_reg_t; |
| 98 | typedef uint8_t hri_sercomusart_rxpl_reg_t; |
| 99 | |
| 100 | static inline void hri_sercomi2cm_wait_for_sync(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) |
| 101 | { |
| 102 | while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) { |
| 103 | }; |
| 104 | } |
| 105 | |
| 106 | static inline bool hri_sercomi2cm_is_syncing(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) |
| 107 | { |
| 108 | return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg; |
| 109 | } |
| 110 | |
| 111 | static inline void hri_sercomi2cs_wait_for_sync(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) |
| 112 | { |
| 113 | while (((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg) { |
| 114 | }; |
| 115 | } |
| 116 | |
| 117 | static inline bool hri_sercomi2cs_is_syncing(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) |
| 118 | { |
| 119 | return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg; |
| 120 | } |
| 121 | |
| 122 | static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) |
| 123 | { |
| 124 | while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) { |
| 125 | }; |
| 126 | } |
| 127 | |
| 128 | static inline bool hri_sercomspi_is_syncing(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) |
| 129 | { |
| 130 | return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg; |
| 131 | } |
| 132 | |
| 133 | static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) |
| 134 | { |
| 135 | while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) { |
| 136 | }; |
| 137 | } |
| 138 | |
| 139 | static inline bool hri_sercomusart_is_syncing(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) |
| 140 | { |
| 141 | return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg; |
| 142 | } |
| 143 | |
| 144 | static inline bool hri_sercomi2cm_get_INTFLAG_MB_bit(const void *const hw) |
| 145 | { |
| 146 | return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; |
| 147 | } |
| 148 | |
| 149 | static inline void hri_sercomi2cm_clear_INTFLAG_MB_bit(const void *const hw) |
| 150 | { |
| 151 | ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; |
| 152 | } |
| 153 | |
| 154 | static inline bool hri_sercomi2cm_get_INTFLAG_SB_bit(const void *const hw) |
| 155 | { |
| 156 | return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; |
| 157 | } |
| 158 | |
| 159 | static inline void hri_sercomi2cm_clear_INTFLAG_SB_bit(const void *const hw) |
| 160 | { |
| 161 | ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; |
| 162 | } |
| 163 | |
| 164 | static inline bool hri_sercomi2cm_get_INTFLAG_ERROR_bit(const void *const hw) |
| 165 | { |
| 166 | return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; |
| 167 | } |
| 168 | |
| 169 | static inline void hri_sercomi2cm_clear_INTFLAG_ERROR_bit(const void *const hw) |
| 170 | { |
| 171 | ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; |
| 172 | } |
| 173 | |
| 174 | static inline bool hri_sercomi2cm_get_interrupt_MB_bit(const void *const hw) |
| 175 | { |
| 176 | return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; |
| 177 | } |
| 178 | |
| 179 | static inline void hri_sercomi2cm_clear_interrupt_MB_bit(const void *const hw) |
| 180 | { |
| 181 | ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; |
| 182 | } |
| 183 | |
| 184 | static inline bool hri_sercomi2cm_get_interrupt_SB_bit(const void *const hw) |
| 185 | { |
| 186 | return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; |
| 187 | } |
| 188 | |
| 189 | static inline void hri_sercomi2cm_clear_interrupt_SB_bit(const void *const hw) |
| 190 | { |
| 191 | ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; |
| 192 | } |
| 193 | |
| 194 | static inline bool hri_sercomi2cm_get_interrupt_ERROR_bit(const void *const hw) |
| 195 | { |
| 196 | return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; |
| 197 | } |
| 198 | |
| 199 | static inline void hri_sercomi2cm_clear_interrupt_ERROR_bit(const void *const hw) |
| 200 | { |
| 201 | ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; |
| 202 | } |
| 203 | |
| 204 | static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_get_INTFLAG_reg(const void *const hw, |
| 205 | hri_sercomi2cm_intflag_reg_t mask) |
| 206 | { |
| 207 | uint8_t tmp; |
| 208 | tmp = ((Sercom *)hw)->I2CM.INTFLAG.reg; |
| 209 | tmp &= mask; |
| 210 | return tmp; |
| 211 | } |
| 212 | |
| 213 | static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_read_INTFLAG_reg(const void *const hw) |
| 214 | { |
| 215 | return ((Sercom *)hw)->I2CM.INTFLAG.reg; |
| 216 | } |
| 217 | |
| 218 | static inline void hri_sercomi2cm_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cm_intflag_reg_t mask) |
| 219 | { |
| 220 | ((Sercom *)hw)->I2CM.INTFLAG.reg = mask; |
| 221 | } |
| 222 | |
| 223 | static inline bool hri_sercomi2cs_get_INTFLAG_PREC_bit(const void *const hw) |
| 224 | { |
| 225 | return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; |
| 226 | } |
| 227 | |
| 228 | static inline void hri_sercomi2cs_clear_INTFLAG_PREC_bit(const void *const hw) |
| 229 | { |
| 230 | ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; |
| 231 | } |
| 232 | |
| 233 | static inline bool hri_sercomi2cs_get_INTFLAG_AMATCH_bit(const void *const hw) |
| 234 | { |
| 235 | return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; |
| 236 | } |
| 237 | |
| 238 | static inline void hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(const void *const hw) |
| 239 | { |
| 240 | ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; |
| 241 | } |
| 242 | |
| 243 | static inline bool hri_sercomi2cs_get_INTFLAG_DRDY_bit(const void *const hw) |
| 244 | { |
| 245 | return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; |
| 246 | } |
| 247 | |
| 248 | static inline void hri_sercomi2cs_clear_INTFLAG_DRDY_bit(const void *const hw) |
| 249 | { |
| 250 | ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; |
| 251 | } |
| 252 | |
| 253 | static inline bool hri_sercomi2cs_get_INTFLAG_ERROR_bit(const void *const hw) |
| 254 | { |
| 255 | return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; |
| 256 | } |
| 257 | |
| 258 | static inline void hri_sercomi2cs_clear_INTFLAG_ERROR_bit(const void *const hw) |
| 259 | { |
| 260 | ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; |
| 261 | } |
| 262 | |
| 263 | static inline bool hri_sercomi2cs_get_interrupt_PREC_bit(const void *const hw) |
| 264 | { |
| 265 | return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; |
| 266 | } |
| 267 | |
| 268 | static inline void hri_sercomi2cs_clear_interrupt_PREC_bit(const void *const hw) |
| 269 | { |
| 270 | ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; |
| 271 | } |
| 272 | |
| 273 | static inline bool hri_sercomi2cs_get_interrupt_AMATCH_bit(const void *const hw) |
| 274 | { |
| 275 | return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; |
| 276 | } |
| 277 | |
| 278 | static inline void hri_sercomi2cs_clear_interrupt_AMATCH_bit(const void *const hw) |
| 279 | { |
| 280 | ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; |
| 281 | } |
| 282 | |
| 283 | static inline bool hri_sercomi2cs_get_interrupt_DRDY_bit(const void *const hw) |
| 284 | { |
| 285 | return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; |
| 286 | } |
| 287 | |
| 288 | static inline void hri_sercomi2cs_clear_interrupt_DRDY_bit(const void *const hw) |
| 289 | { |
| 290 | ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; |
| 291 | } |
| 292 | |
| 293 | static inline bool hri_sercomi2cs_get_interrupt_ERROR_bit(const void *const hw) |
| 294 | { |
| 295 | return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; |
| 296 | } |
| 297 | |
| 298 | static inline void hri_sercomi2cs_clear_interrupt_ERROR_bit(const void *const hw) |
| 299 | { |
| 300 | ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; |
| 301 | } |
| 302 | |
| 303 | static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_get_INTFLAG_reg(const void *const hw, |
| 304 | hri_sercomi2cs_intflag_reg_t mask) |
| 305 | { |
| 306 | uint8_t tmp; |
| 307 | tmp = ((Sercom *)hw)->I2CS.INTFLAG.reg; |
| 308 | tmp &= mask; |
| 309 | return tmp; |
| 310 | } |
| 311 | |
| 312 | static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_read_INTFLAG_reg(const void *const hw) |
| 313 | { |
| 314 | return ((Sercom *)hw)->I2CS.INTFLAG.reg; |
| 315 | } |
| 316 | |
| 317 | static inline void hri_sercomi2cs_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cs_intflag_reg_t mask) |
| 318 | { |
| 319 | ((Sercom *)hw)->I2CS.INTFLAG.reg = mask; |
| 320 | } |
| 321 | |
| 322 | static inline bool hri_sercomspi_get_INTFLAG_DRE_bit(const void *const hw) |
| 323 | { |
| 324 | return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; |
| 325 | } |
| 326 | |
| 327 | static inline void hri_sercomspi_clear_INTFLAG_DRE_bit(const void *const hw) |
| 328 | { |
| 329 | ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; |
| 330 | } |
| 331 | |
| 332 | static inline bool hri_sercomspi_get_INTFLAG_TXC_bit(const void *const hw) |
| 333 | { |
| 334 | return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; |
| 335 | } |
| 336 | |
| 337 | static inline void hri_sercomspi_clear_INTFLAG_TXC_bit(const void *const hw) |
| 338 | { |
| 339 | ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; |
| 340 | } |
| 341 | |
| 342 | static inline bool hri_sercomspi_get_INTFLAG_RXC_bit(const void *const hw) |
| 343 | { |
| 344 | return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; |
| 345 | } |
| 346 | |
| 347 | static inline void hri_sercomspi_clear_INTFLAG_RXC_bit(const void *const hw) |
| 348 | { |
| 349 | ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; |
| 350 | } |
| 351 | |
| 352 | static inline bool hri_sercomspi_get_INTFLAG_SSL_bit(const void *const hw) |
| 353 | { |
| 354 | return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; |
| 355 | } |
| 356 | |
| 357 | static inline void hri_sercomspi_clear_INTFLAG_SSL_bit(const void *const hw) |
| 358 | { |
| 359 | ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; |
| 360 | } |
| 361 | |
| 362 | static inline bool hri_sercomspi_get_INTFLAG_ERROR_bit(const void *const hw) |
| 363 | { |
| 364 | return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; |
| 365 | } |
| 366 | |
| 367 | static inline void hri_sercomspi_clear_INTFLAG_ERROR_bit(const void *const hw) |
| 368 | { |
| 369 | ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; |
| 370 | } |
| 371 | |
| 372 | static inline bool hri_sercomspi_get_interrupt_DRE_bit(const void *const hw) |
| 373 | { |
| 374 | return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; |
| 375 | } |
| 376 | |
| 377 | static inline void hri_sercomspi_clear_interrupt_DRE_bit(const void *const hw) |
| 378 | { |
| 379 | ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; |
| 380 | } |
| 381 | |
| 382 | static inline bool hri_sercomspi_get_interrupt_TXC_bit(const void *const hw) |
| 383 | { |
| 384 | return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; |
| 385 | } |
| 386 | |
| 387 | static inline void hri_sercomspi_clear_interrupt_TXC_bit(const void *const hw) |
| 388 | { |
| 389 | ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; |
| 390 | } |
| 391 | |
| 392 | static inline bool hri_sercomspi_get_interrupt_RXC_bit(const void *const hw) |
| 393 | { |
| 394 | return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; |
| 395 | } |
| 396 | |
| 397 | static inline void hri_sercomspi_clear_interrupt_RXC_bit(const void *const hw) |
| 398 | { |
| 399 | ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; |
| 400 | } |
| 401 | |
| 402 | static inline bool hri_sercomspi_get_interrupt_SSL_bit(const void *const hw) |
| 403 | { |
| 404 | return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; |
| 405 | } |
| 406 | |
| 407 | static inline void hri_sercomspi_clear_interrupt_SSL_bit(const void *const hw) |
| 408 | { |
| 409 | ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; |
| 410 | } |
| 411 | |
| 412 | static inline bool hri_sercomspi_get_interrupt_ERROR_bit(const void *const hw) |
| 413 | { |
| 414 | return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; |
| 415 | } |
| 416 | |
| 417 | static inline void hri_sercomspi_clear_interrupt_ERROR_bit(const void *const hw) |
| 418 | { |
| 419 | ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; |
| 420 | } |
| 421 | |
| 422 | static inline hri_sercomspi_intflag_reg_t hri_sercomspi_get_INTFLAG_reg(const void *const hw, |
| 423 | hri_sercomspi_intflag_reg_t mask) |
| 424 | { |
| 425 | uint8_t tmp; |
| 426 | tmp = ((Sercom *)hw)->SPI.INTFLAG.reg; |
| 427 | tmp &= mask; |
| 428 | return tmp; |
| 429 | } |
| 430 | |
| 431 | static inline hri_sercomspi_intflag_reg_t hri_sercomspi_read_INTFLAG_reg(const void *const hw) |
| 432 | { |
| 433 | return ((Sercom *)hw)->SPI.INTFLAG.reg; |
| 434 | } |
| 435 | |
| 436 | static inline void hri_sercomspi_clear_INTFLAG_reg(const void *const hw, hri_sercomspi_intflag_reg_t mask) |
| 437 | { |
| 438 | ((Sercom *)hw)->SPI.INTFLAG.reg = mask; |
| 439 | } |
| 440 | |
| 441 | static inline bool hri_sercomusart_get_INTFLAG_DRE_bit(const void *const hw) |
| 442 | { |
| 443 | return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; |
| 444 | } |
| 445 | |
| 446 | static inline void hri_sercomusart_clear_INTFLAG_DRE_bit(const void *const hw) |
| 447 | { |
| 448 | ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; |
| 449 | } |
| 450 | |
| 451 | static inline bool hri_sercomusart_get_INTFLAG_TXC_bit(const void *const hw) |
| 452 | { |
| 453 | return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; |
| 454 | } |
| 455 | |
| 456 | static inline void hri_sercomusart_clear_INTFLAG_TXC_bit(const void *const hw) |
| 457 | { |
| 458 | ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; |
| 459 | } |
| 460 | |
| 461 | static inline bool hri_sercomusart_get_INTFLAG_RXC_bit(const void *const hw) |
| 462 | { |
| 463 | return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; |
| 464 | } |
| 465 | |
| 466 | static inline void hri_sercomusart_clear_INTFLAG_RXC_bit(const void *const hw) |
| 467 | { |
| 468 | ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; |
| 469 | } |
| 470 | |
| 471 | static inline bool hri_sercomusart_get_INTFLAG_RXS_bit(const void *const hw) |
| 472 | { |
| 473 | return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; |
| 474 | } |
| 475 | |
| 476 | static inline void hri_sercomusart_clear_INTFLAG_RXS_bit(const void *const hw) |
| 477 | { |
| 478 | ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; |
| 479 | } |
| 480 | |
| 481 | static inline bool hri_sercomusart_get_INTFLAG_CTSIC_bit(const void *const hw) |
| 482 | { |
| 483 | return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; |
| 484 | } |
| 485 | |
| 486 | static inline void hri_sercomusart_clear_INTFLAG_CTSIC_bit(const void *const hw) |
| 487 | { |
| 488 | ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; |
| 489 | } |
| 490 | |
| 491 | static inline bool hri_sercomusart_get_INTFLAG_RXBRK_bit(const void *const hw) |
| 492 | { |
| 493 | return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; |
| 494 | } |
| 495 | |
| 496 | static inline void hri_sercomusart_clear_INTFLAG_RXBRK_bit(const void *const hw) |
| 497 | { |
| 498 | ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; |
| 499 | } |
| 500 | |
| 501 | static inline bool hri_sercomusart_get_INTFLAG_ERROR_bit(const void *const hw) |
| 502 | { |
| 503 | return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; |
| 504 | } |
| 505 | |
| 506 | static inline void hri_sercomusart_clear_INTFLAG_ERROR_bit(const void *const hw) |
| 507 | { |
| 508 | ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; |
| 509 | } |
| 510 | |
| 511 | static inline bool hri_sercomusart_get_interrupt_DRE_bit(const void *const hw) |
| 512 | { |
| 513 | return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; |
| 514 | } |
| 515 | |
| 516 | static inline void hri_sercomusart_clear_interrupt_DRE_bit(const void *const hw) |
| 517 | { |
| 518 | ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; |
| 519 | } |
| 520 | |
| 521 | static inline bool hri_sercomusart_get_interrupt_TXC_bit(const void *const hw) |
| 522 | { |
| 523 | return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; |
| 524 | } |
| 525 | |
| 526 | static inline void hri_sercomusart_clear_interrupt_TXC_bit(const void *const hw) |
| 527 | { |
| 528 | ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; |
| 529 | } |
| 530 | |
| 531 | static inline bool hri_sercomusart_get_interrupt_RXC_bit(const void *const hw) |
| 532 | { |
| 533 | return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; |
| 534 | } |
| 535 | |
| 536 | static inline void hri_sercomusart_clear_interrupt_RXC_bit(const void *const hw) |
| 537 | { |
| 538 | ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; |
| 539 | } |
| 540 | |
| 541 | static inline bool hri_sercomusart_get_interrupt_RXS_bit(const void *const hw) |
| 542 | { |
| 543 | return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; |
| 544 | } |
| 545 | |
| 546 | static inline void hri_sercomusart_clear_interrupt_RXS_bit(const void *const hw) |
| 547 | { |
| 548 | ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; |
| 549 | } |
| 550 | |
| 551 | static inline bool hri_sercomusart_get_interrupt_CTSIC_bit(const void *const hw) |
| 552 | { |
| 553 | return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; |
| 554 | } |
| 555 | |
| 556 | static inline void hri_sercomusart_clear_interrupt_CTSIC_bit(const void *const hw) |
| 557 | { |
| 558 | ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; |
| 559 | } |
| 560 | |
| 561 | static inline bool hri_sercomusart_get_interrupt_RXBRK_bit(const void *const hw) |
| 562 | { |
| 563 | return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; |
| 564 | } |
| 565 | |
| 566 | static inline void hri_sercomusart_clear_interrupt_RXBRK_bit(const void *const hw) |
| 567 | { |
| 568 | ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; |
| 569 | } |
| 570 | |
| 571 | static inline bool hri_sercomusart_get_interrupt_ERROR_bit(const void *const hw) |
| 572 | { |
| 573 | return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; |
| 574 | } |
| 575 | |
| 576 | static inline void hri_sercomusart_clear_interrupt_ERROR_bit(const void *const hw) |
| 577 | { |
| 578 | ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; |
| 579 | } |
| 580 | |
| 581 | static inline hri_sercomusart_intflag_reg_t hri_sercomusart_get_INTFLAG_reg(const void *const hw, |
| 582 | hri_sercomusart_intflag_reg_t mask) |
| 583 | { |
| 584 | uint8_t tmp; |
| 585 | tmp = ((Sercom *)hw)->USART.INTFLAG.reg; |
| 586 | tmp &= mask; |
| 587 | return tmp; |
| 588 | } |
| 589 | |
| 590 | static inline hri_sercomusart_intflag_reg_t hri_sercomusart_read_INTFLAG_reg(const void *const hw) |
| 591 | { |
| 592 | return ((Sercom *)hw)->USART.INTFLAG.reg; |
| 593 | } |
| 594 | |
| 595 | static inline void hri_sercomusart_clear_INTFLAG_reg(const void *const hw, hri_sercomusart_intflag_reg_t mask) |
| 596 | { |
| 597 | ((Sercom *)hw)->USART.INTFLAG.reg = mask; |
| 598 | } |
| 599 | |
| 600 | static inline void hri_sercomi2cm_set_INTEN_MB_bit(const void *const hw) |
| 601 | { |
| 602 | ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; |
| 603 | } |
| 604 | |
| 605 | static inline bool hri_sercomi2cm_get_INTEN_MB_bit(const void *const hw) |
| 606 | { |
| 607 | return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_MB) >> SERCOM_I2CM_INTENSET_MB_Pos; |
| 608 | } |
| 609 | |
| 610 | static inline void hri_sercomi2cm_write_INTEN_MB_bit(const void *const hw, bool value) |
| 611 | { |
| 612 | if (value == 0x0) { |
| 613 | ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; |
| 614 | } else { |
| 615 | ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; |
| 616 | } |
| 617 | } |
| 618 | |
| 619 | static inline void hri_sercomi2cm_clear_INTEN_MB_bit(const void *const hw) |
| 620 | { |
| 621 | ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; |
| 622 | } |
| 623 | |
| 624 | static inline void hri_sercomi2cm_set_INTEN_SB_bit(const void *const hw) |
| 625 | { |
| 626 | ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; |
| 627 | } |
| 628 | |
| 629 | static inline bool hri_sercomi2cm_get_INTEN_SB_bit(const void *const hw) |
| 630 | { |
| 631 | return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_SB) >> SERCOM_I2CM_INTENSET_SB_Pos; |
| 632 | } |
| 633 | |
| 634 | static inline void hri_sercomi2cm_write_INTEN_SB_bit(const void *const hw, bool value) |
| 635 | { |
| 636 | if (value == 0x0) { |
| 637 | ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; |
| 638 | } else { |
| 639 | ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; |
| 640 | } |
| 641 | } |
| 642 | |
| 643 | static inline void hri_sercomi2cm_clear_INTEN_SB_bit(const void *const hw) |
| 644 | { |
| 645 | ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; |
| 646 | } |
| 647 | |
| 648 | static inline void hri_sercomi2cm_set_INTEN_ERROR_bit(const void *const hw) |
| 649 | { |
| 650 | ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; |
| 651 | } |
| 652 | |
| 653 | static inline bool hri_sercomi2cm_get_INTEN_ERROR_bit(const void *const hw) |
| 654 | { |
| 655 | return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_ERROR) >> SERCOM_I2CM_INTENSET_ERROR_Pos; |
| 656 | } |
| 657 | |
| 658 | static inline void hri_sercomi2cm_write_INTEN_ERROR_bit(const void *const hw, bool value) |
| 659 | { |
| 660 | if (value == 0x0) { |
| 661 | ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; |
| 662 | } else { |
| 663 | ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; |
| 664 | } |
| 665 | } |
| 666 | |
| 667 | static inline void hri_sercomi2cm_clear_INTEN_ERROR_bit(const void *const hw) |
| 668 | { |
| 669 | ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; |
| 670 | } |
| 671 | |
| 672 | static inline void hri_sercomi2cm_set_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) |
| 673 | { |
| 674 | ((Sercom *)hw)->I2CM.INTENSET.reg = mask; |
| 675 | } |
| 676 | |
| 677 | static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_get_INTEN_reg(const void *const hw, |
| 678 | hri_sercomi2cm_intenset_reg_t mask) |
| 679 | { |
| 680 | uint8_t tmp; |
| 681 | tmp = ((Sercom *)hw)->I2CM.INTENSET.reg; |
| 682 | tmp &= mask; |
| 683 | return tmp; |
| 684 | } |
| 685 | |
| 686 | static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_read_INTEN_reg(const void *const hw) |
| 687 | { |
| 688 | return ((Sercom *)hw)->I2CM.INTENSET.reg; |
| 689 | } |
| 690 | |
| 691 | static inline void hri_sercomi2cm_write_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t data) |
| 692 | { |
| 693 | ((Sercom *)hw)->I2CM.INTENSET.reg = data; |
| 694 | ((Sercom *)hw)->I2CM.INTENCLR.reg = ~data; |
| 695 | } |
| 696 | |
| 697 | static inline void hri_sercomi2cm_clear_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) |
| 698 | { |
| 699 | ((Sercom *)hw)->I2CM.INTENCLR.reg = mask; |
| 700 | } |
| 701 | |
| 702 | static inline void hri_sercomi2cs_set_INTEN_PREC_bit(const void *const hw) |
| 703 | { |
| 704 | ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; |
| 705 | } |
| 706 | |
| 707 | static inline bool hri_sercomi2cs_get_INTEN_PREC_bit(const void *const hw) |
| 708 | { |
| 709 | return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_PREC) >> SERCOM_I2CS_INTENSET_PREC_Pos; |
| 710 | } |
| 711 | |
| 712 | static inline void hri_sercomi2cs_write_INTEN_PREC_bit(const void *const hw, bool value) |
| 713 | { |
| 714 | if (value == 0x0) { |
| 715 | ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; |
| 716 | } else { |
| 717 | ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; |
| 718 | } |
| 719 | } |
| 720 | |
| 721 | static inline void hri_sercomi2cs_clear_INTEN_PREC_bit(const void *const hw) |
| 722 | { |
| 723 | ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; |
| 724 | } |
| 725 | |
| 726 | static inline void hri_sercomi2cs_set_INTEN_AMATCH_bit(const void *const hw) |
| 727 | { |
| 728 | ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; |
| 729 | } |
| 730 | |
| 731 | static inline bool hri_sercomi2cs_get_INTEN_AMATCH_bit(const void *const hw) |
| 732 | { |
| 733 | return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_AMATCH) >> SERCOM_I2CS_INTENSET_AMATCH_Pos; |
| 734 | } |
| 735 | |
| 736 | static inline void hri_sercomi2cs_write_INTEN_AMATCH_bit(const void *const hw, bool value) |
| 737 | { |
| 738 | if (value == 0x0) { |
| 739 | ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; |
| 740 | } else { |
| 741 | ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; |
| 742 | } |
| 743 | } |
| 744 | |
| 745 | static inline void hri_sercomi2cs_clear_INTEN_AMATCH_bit(const void *const hw) |
| 746 | { |
| 747 | ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; |
| 748 | } |
| 749 | |
| 750 | static inline void hri_sercomi2cs_set_INTEN_DRDY_bit(const void *const hw) |
| 751 | { |
| 752 | ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; |
| 753 | } |
| 754 | |
| 755 | static inline bool hri_sercomi2cs_get_INTEN_DRDY_bit(const void *const hw) |
| 756 | { |
| 757 | return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_DRDY) >> SERCOM_I2CS_INTENSET_DRDY_Pos; |
| 758 | } |
| 759 | |
| 760 | static inline void hri_sercomi2cs_write_INTEN_DRDY_bit(const void *const hw, bool value) |
| 761 | { |
| 762 | if (value == 0x0) { |
| 763 | ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; |
| 764 | } else { |
| 765 | ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; |
| 766 | } |
| 767 | } |
| 768 | |
| 769 | static inline void hri_sercomi2cs_clear_INTEN_DRDY_bit(const void *const hw) |
| 770 | { |
| 771 | ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; |
| 772 | } |
| 773 | |
| 774 | static inline void hri_sercomi2cs_set_INTEN_ERROR_bit(const void *const hw) |
| 775 | { |
| 776 | ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; |
| 777 | } |
| 778 | |
| 779 | static inline bool hri_sercomi2cs_get_INTEN_ERROR_bit(const void *const hw) |
| 780 | { |
| 781 | return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_ERROR) >> SERCOM_I2CS_INTENSET_ERROR_Pos; |
| 782 | } |
| 783 | |
| 784 | static inline void hri_sercomi2cs_write_INTEN_ERROR_bit(const void *const hw, bool value) |
| 785 | { |
| 786 | if (value == 0x0) { |
| 787 | ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; |
| 788 | } else { |
| 789 | ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; |
| 790 | } |
| 791 | } |
| 792 | |
| 793 | static inline void hri_sercomi2cs_clear_INTEN_ERROR_bit(const void *const hw) |
| 794 | { |
| 795 | ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; |
| 796 | } |
| 797 | |
| 798 | static inline void hri_sercomi2cs_set_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) |
| 799 | { |
| 800 | ((Sercom *)hw)->I2CS.INTENSET.reg = mask; |
| 801 | } |
| 802 | |
| 803 | static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_get_INTEN_reg(const void *const hw, |
| 804 | hri_sercomi2cs_intenset_reg_t mask) |
| 805 | { |
| 806 | uint8_t tmp; |
| 807 | tmp = ((Sercom *)hw)->I2CS.INTENSET.reg; |
| 808 | tmp &= mask; |
| 809 | return tmp; |
| 810 | } |
| 811 | |
| 812 | static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_read_INTEN_reg(const void *const hw) |
| 813 | { |
| 814 | return ((Sercom *)hw)->I2CS.INTENSET.reg; |
| 815 | } |
| 816 | |
| 817 | static inline void hri_sercomi2cs_write_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t data) |
| 818 | { |
| 819 | ((Sercom *)hw)->I2CS.INTENSET.reg = data; |
| 820 | ((Sercom *)hw)->I2CS.INTENCLR.reg = ~data; |
| 821 | } |
| 822 | |
| 823 | static inline void hri_sercomi2cs_clear_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) |
| 824 | { |
| 825 | ((Sercom *)hw)->I2CS.INTENCLR.reg = mask; |
| 826 | } |
| 827 | |
| 828 | static inline void hri_sercomspi_set_INTEN_DRE_bit(const void *const hw) |
| 829 | { |
| 830 | ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; |
| 831 | } |
| 832 | |
| 833 | static inline bool hri_sercomspi_get_INTEN_DRE_bit(const void *const hw) |
| 834 | { |
| 835 | return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_DRE) >> SERCOM_SPI_INTENSET_DRE_Pos; |
| 836 | } |
| 837 | |
| 838 | static inline void hri_sercomspi_write_INTEN_DRE_bit(const void *const hw, bool value) |
| 839 | { |
| 840 | if (value == 0x0) { |
| 841 | ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; |
| 842 | } else { |
| 843 | ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; |
| 844 | } |
| 845 | } |
| 846 | |
| 847 | static inline void hri_sercomspi_clear_INTEN_DRE_bit(const void *const hw) |
| 848 | { |
| 849 | ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; |
| 850 | } |
| 851 | |
| 852 | static inline void hri_sercomspi_set_INTEN_TXC_bit(const void *const hw) |
| 853 | { |
| 854 | ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; |
| 855 | } |
| 856 | |
| 857 | static inline bool hri_sercomspi_get_INTEN_TXC_bit(const void *const hw) |
| 858 | { |
| 859 | return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_TXC) >> SERCOM_SPI_INTENSET_TXC_Pos; |
| 860 | } |
| 861 | |
| 862 | static inline void hri_sercomspi_write_INTEN_TXC_bit(const void *const hw, bool value) |
| 863 | { |
| 864 | if (value == 0x0) { |
| 865 | ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; |
| 866 | } else { |
| 867 | ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; |
| 868 | } |
| 869 | } |
| 870 | |
| 871 | static inline void hri_sercomspi_clear_INTEN_TXC_bit(const void *const hw) |
| 872 | { |
| 873 | ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; |
| 874 | } |
| 875 | |
| 876 | static inline void hri_sercomspi_set_INTEN_RXC_bit(const void *const hw) |
| 877 | { |
| 878 | ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; |
| 879 | } |
| 880 | |
| 881 | static inline bool hri_sercomspi_get_INTEN_RXC_bit(const void *const hw) |
| 882 | { |
| 883 | return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_RXC) >> SERCOM_SPI_INTENSET_RXC_Pos; |
| 884 | } |
| 885 | |
| 886 | static inline void hri_sercomspi_write_INTEN_RXC_bit(const void *const hw, bool value) |
| 887 | { |
| 888 | if (value == 0x0) { |
| 889 | ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; |
| 890 | } else { |
| 891 | ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; |
| 892 | } |
| 893 | } |
| 894 | |
| 895 | static inline void hri_sercomspi_clear_INTEN_RXC_bit(const void *const hw) |
| 896 | { |
| 897 | ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; |
| 898 | } |
| 899 | |
| 900 | static inline void hri_sercomspi_set_INTEN_SSL_bit(const void *const hw) |
| 901 | { |
| 902 | ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; |
| 903 | } |
| 904 | |
| 905 | static inline bool hri_sercomspi_get_INTEN_SSL_bit(const void *const hw) |
| 906 | { |
| 907 | return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_SSL) >> SERCOM_SPI_INTENSET_SSL_Pos; |
| 908 | } |
| 909 | |
| 910 | static inline void hri_sercomspi_write_INTEN_SSL_bit(const void *const hw, bool value) |
| 911 | { |
| 912 | if (value == 0x0) { |
| 913 | ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; |
| 914 | } else { |
| 915 | ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; |
| 916 | } |
| 917 | } |
| 918 | |
| 919 | static inline void hri_sercomspi_clear_INTEN_SSL_bit(const void *const hw) |
| 920 | { |
| 921 | ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; |
| 922 | } |
| 923 | |
| 924 | static inline void hri_sercomspi_set_INTEN_ERROR_bit(const void *const hw) |
| 925 | { |
| 926 | ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; |
| 927 | } |
| 928 | |
| 929 | static inline bool hri_sercomspi_get_INTEN_ERROR_bit(const void *const hw) |
| 930 | { |
| 931 | return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_ERROR) >> SERCOM_SPI_INTENSET_ERROR_Pos; |
| 932 | } |
| 933 | |
| 934 | static inline void hri_sercomspi_write_INTEN_ERROR_bit(const void *const hw, bool value) |
| 935 | { |
| 936 | if (value == 0x0) { |
| 937 | ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; |
| 938 | } else { |
| 939 | ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; |
| 940 | } |
| 941 | } |
| 942 | |
| 943 | static inline void hri_sercomspi_clear_INTEN_ERROR_bit(const void *const hw) |
| 944 | { |
| 945 | ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; |
| 946 | } |
| 947 | |
| 948 | static inline void hri_sercomspi_set_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) |
| 949 | { |
| 950 | ((Sercom *)hw)->SPI.INTENSET.reg = mask; |
| 951 | } |
| 952 | |
| 953 | static inline hri_sercomspi_intenset_reg_t hri_sercomspi_get_INTEN_reg(const void *const hw, |
| 954 | hri_sercomspi_intenset_reg_t mask) |
| 955 | { |
| 956 | uint8_t tmp; |
| 957 | tmp = ((Sercom *)hw)->SPI.INTENSET.reg; |
| 958 | tmp &= mask; |
| 959 | return tmp; |
| 960 | } |
| 961 | |
| 962 | static inline hri_sercomspi_intenset_reg_t hri_sercomspi_read_INTEN_reg(const void *const hw) |
| 963 | { |
| 964 | return ((Sercom *)hw)->SPI.INTENSET.reg; |
| 965 | } |
| 966 | |
| 967 | static inline void hri_sercomspi_write_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t data) |
| 968 | { |
| 969 | ((Sercom *)hw)->SPI.INTENSET.reg = data; |
| 970 | ((Sercom *)hw)->SPI.INTENCLR.reg = ~data; |
| 971 | } |
| 972 | |
| 973 | static inline void hri_sercomspi_clear_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) |
| 974 | { |
| 975 | ((Sercom *)hw)->SPI.INTENCLR.reg = mask; |
| 976 | } |
| 977 | |
| 978 | static inline void hri_sercomusart_set_INTEN_DRE_bit(const void *const hw) |
| 979 | { |
| 980 | ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; |
| 981 | } |
| 982 | |
| 983 | static inline bool hri_sercomusart_get_INTEN_DRE_bit(const void *const hw) |
| 984 | { |
| 985 | return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_DRE) >> SERCOM_USART_INTENSET_DRE_Pos; |
| 986 | } |
| 987 | |
| 988 | static inline void hri_sercomusart_write_INTEN_DRE_bit(const void *const hw, bool value) |
| 989 | { |
| 990 | if (value == 0x0) { |
| 991 | ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; |
| 992 | } else { |
| 993 | ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; |
| 994 | } |
| 995 | } |
| 996 | |
| 997 | static inline void hri_sercomusart_clear_INTEN_DRE_bit(const void *const hw) |
| 998 | { |
| 999 | ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; |
| 1000 | } |
| 1001 | |
| 1002 | static inline void hri_sercomusart_set_INTEN_TXC_bit(const void *const hw) |
| 1003 | { |
| 1004 | ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; |
| 1005 | } |
| 1006 | |
| 1007 | static inline bool hri_sercomusart_get_INTEN_TXC_bit(const void *const hw) |
| 1008 | { |
| 1009 | return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_TXC) >> SERCOM_USART_INTENSET_TXC_Pos; |
| 1010 | } |
| 1011 | |
| 1012 | static inline void hri_sercomusart_write_INTEN_TXC_bit(const void *const hw, bool value) |
| 1013 | { |
| 1014 | if (value == 0x0) { |
| 1015 | ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; |
| 1016 | } else { |
| 1017 | ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; |
| 1018 | } |
| 1019 | } |
| 1020 | |
| 1021 | static inline void hri_sercomusart_clear_INTEN_TXC_bit(const void *const hw) |
| 1022 | { |
| 1023 | ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; |
| 1024 | } |
| 1025 | |
| 1026 | static inline void hri_sercomusart_set_INTEN_RXC_bit(const void *const hw) |
| 1027 | { |
| 1028 | ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; |
| 1029 | } |
| 1030 | |
| 1031 | static inline bool hri_sercomusart_get_INTEN_RXC_bit(const void *const hw) |
| 1032 | { |
| 1033 | return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXC) >> SERCOM_USART_INTENSET_RXC_Pos; |
| 1034 | } |
| 1035 | |
| 1036 | static inline void hri_sercomusart_write_INTEN_RXC_bit(const void *const hw, bool value) |
| 1037 | { |
| 1038 | if (value == 0x0) { |
| 1039 | ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; |
| 1040 | } else { |
| 1041 | ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; |
| 1042 | } |
| 1043 | } |
| 1044 | |
| 1045 | static inline void hri_sercomusart_clear_INTEN_RXC_bit(const void *const hw) |
| 1046 | { |
| 1047 | ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; |
| 1048 | } |
| 1049 | |
| 1050 | static inline void hri_sercomusart_set_INTEN_RXS_bit(const void *const hw) |
| 1051 | { |
| 1052 | ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; |
| 1053 | } |
| 1054 | |
| 1055 | static inline bool hri_sercomusart_get_INTEN_RXS_bit(const void *const hw) |
| 1056 | { |
| 1057 | return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXS) >> SERCOM_USART_INTENSET_RXS_Pos; |
| 1058 | } |
| 1059 | |
| 1060 | static inline void hri_sercomusart_write_INTEN_RXS_bit(const void *const hw, bool value) |
| 1061 | { |
| 1062 | if (value == 0x0) { |
| 1063 | ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; |
| 1064 | } else { |
| 1065 | ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; |
| 1066 | } |
| 1067 | } |
| 1068 | |
| 1069 | static inline void hri_sercomusart_clear_INTEN_RXS_bit(const void *const hw) |
| 1070 | { |
| 1071 | ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; |
| 1072 | } |
| 1073 | |
| 1074 | static inline void hri_sercomusart_set_INTEN_CTSIC_bit(const void *const hw) |
| 1075 | { |
| 1076 | ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; |
| 1077 | } |
| 1078 | |
| 1079 | static inline bool hri_sercomusart_get_INTEN_CTSIC_bit(const void *const hw) |
| 1080 | { |
| 1081 | return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_CTSIC) >> SERCOM_USART_INTENSET_CTSIC_Pos; |
| 1082 | } |
| 1083 | |
| 1084 | static inline void hri_sercomusart_write_INTEN_CTSIC_bit(const void *const hw, bool value) |
| 1085 | { |
| 1086 | if (value == 0x0) { |
| 1087 | ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; |
| 1088 | } else { |
| 1089 | ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; |
| 1090 | } |
| 1091 | } |
| 1092 | |
| 1093 | static inline void hri_sercomusart_clear_INTEN_CTSIC_bit(const void *const hw) |
| 1094 | { |
| 1095 | ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; |
| 1096 | } |
| 1097 | |
| 1098 | static inline void hri_sercomusart_set_INTEN_RXBRK_bit(const void *const hw) |
| 1099 | { |
| 1100 | ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; |
| 1101 | } |
| 1102 | |
| 1103 | static inline bool hri_sercomusart_get_INTEN_RXBRK_bit(const void *const hw) |
| 1104 | { |
| 1105 | return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXBRK) >> SERCOM_USART_INTENSET_RXBRK_Pos; |
| 1106 | } |
| 1107 | |
| 1108 | static inline void hri_sercomusart_write_INTEN_RXBRK_bit(const void *const hw, bool value) |
| 1109 | { |
| 1110 | if (value == 0x0) { |
| 1111 | ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; |
| 1112 | } else { |
| 1113 | ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; |
| 1114 | } |
| 1115 | } |
| 1116 | |
| 1117 | static inline void hri_sercomusart_clear_INTEN_RXBRK_bit(const void *const hw) |
| 1118 | { |
| 1119 | ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; |
| 1120 | } |
| 1121 | |
| 1122 | static inline void hri_sercomusart_set_INTEN_ERROR_bit(const void *const hw) |
| 1123 | { |
| 1124 | ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; |
| 1125 | } |
| 1126 | |
| 1127 | static inline bool hri_sercomusart_get_INTEN_ERROR_bit(const void *const hw) |
| 1128 | { |
| 1129 | return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_ERROR) >> SERCOM_USART_INTENSET_ERROR_Pos; |
| 1130 | } |
| 1131 | |
| 1132 | static inline void hri_sercomusart_write_INTEN_ERROR_bit(const void *const hw, bool value) |
| 1133 | { |
| 1134 | if (value == 0x0) { |
| 1135 | ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; |
| 1136 | } else { |
| 1137 | ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; |
| 1138 | } |
| 1139 | } |
| 1140 | |
| 1141 | static inline void hri_sercomusart_clear_INTEN_ERROR_bit(const void *const hw) |
| 1142 | { |
| 1143 | ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; |
| 1144 | } |
| 1145 | |
| 1146 | static inline void hri_sercomusart_set_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) |
| 1147 | { |
| 1148 | ((Sercom *)hw)->USART.INTENSET.reg = mask; |
| 1149 | } |
| 1150 | |
| 1151 | static inline hri_sercomusart_intenset_reg_t hri_sercomusart_get_INTEN_reg(const void *const hw, |
| 1152 | hri_sercomusart_intenset_reg_t mask) |
| 1153 | { |
| 1154 | uint8_t tmp; |
| 1155 | tmp = ((Sercom *)hw)->USART.INTENSET.reg; |
| 1156 | tmp &= mask; |
| 1157 | return tmp; |
| 1158 | } |
| 1159 | |
| 1160 | static inline hri_sercomusart_intenset_reg_t hri_sercomusart_read_INTEN_reg(const void *const hw) |
| 1161 | { |
| 1162 | return ((Sercom *)hw)->USART.INTENSET.reg; |
| 1163 | } |
| 1164 | |
| 1165 | static inline void hri_sercomusart_write_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t data) |
| 1166 | { |
| 1167 | ((Sercom *)hw)->USART.INTENSET.reg = data; |
| 1168 | ((Sercom *)hw)->USART.INTENCLR.reg = ~data; |
| 1169 | } |
| 1170 | |
| 1171 | static inline void hri_sercomusart_clear_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) |
| 1172 | { |
| 1173 | ((Sercom *)hw)->USART.INTENCLR.reg = mask; |
| 1174 | } |
| 1175 | |
| 1176 | static inline bool hri_sercomi2cm_get_SYNCBUSY_SWRST_bit(const void *const hw) |
| 1177 | { |
| 1178 | return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SWRST) >> SERCOM_I2CM_SYNCBUSY_SWRST_Pos; |
| 1179 | } |
| 1180 | |
| 1181 | static inline bool hri_sercomi2cm_get_SYNCBUSY_ENABLE_bit(const void *const hw) |
| 1182 | { |
| 1183 | return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_ENABLE) >> SERCOM_I2CM_SYNCBUSY_ENABLE_Pos; |
| 1184 | } |
| 1185 | |
| 1186 | static inline bool hri_sercomi2cm_get_SYNCBUSY_SYSOP_bit(const void *const hw) |
| 1187 | { |
| 1188 | return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SYSOP) >> SERCOM_I2CM_SYNCBUSY_SYSOP_Pos; |
| 1189 | } |
| 1190 | |
| 1191 | static inline bool hri_sercomi2cm_get_SYNCBUSY_LENGTH_bit(const void *const hw) |
| 1192 | { |
| 1193 | return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_LENGTH) >> SERCOM_I2CM_SYNCBUSY_LENGTH_Pos; |
| 1194 | } |
| 1195 | |
| 1196 | static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_get_SYNCBUSY_reg(const void *const hw, |
| 1197 | hri_sercomi2cm_syncbusy_reg_t mask) |
| 1198 | { |
| 1199 | uint32_t tmp; |
| 1200 | tmp = ((Sercom *)hw)->I2CM.SYNCBUSY.reg; |
| 1201 | tmp &= mask; |
| 1202 | return tmp; |
| 1203 | } |
| 1204 | |
| 1205 | static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_read_SYNCBUSY_reg(const void *const hw) |
| 1206 | { |
| 1207 | return ((Sercom *)hw)->I2CM.SYNCBUSY.reg; |
| 1208 | } |
| 1209 | |
| 1210 | static inline bool hri_sercomi2cs_get_SYNCBUSY_SWRST_bit(const void *const hw) |
| 1211 | { |
| 1212 | return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_SWRST) >> SERCOM_I2CS_SYNCBUSY_SWRST_Pos; |
| 1213 | } |
| 1214 | |
| 1215 | static inline bool hri_sercomi2cs_get_SYNCBUSY_ENABLE_bit(const void *const hw) |
| 1216 | { |
| 1217 | return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_ENABLE) >> SERCOM_I2CS_SYNCBUSY_ENABLE_Pos; |
| 1218 | } |
| 1219 | |
| 1220 | static inline bool hri_sercomi2cs_get_SYNCBUSY_LENGTH_bit(const void *const hw) |
| 1221 | { |
| 1222 | return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_LENGTH) >> SERCOM_I2CS_SYNCBUSY_LENGTH_Pos; |
| 1223 | } |
| 1224 | |
| 1225 | static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_get_SYNCBUSY_reg(const void *const hw, |
| 1226 | hri_sercomi2cs_syncbusy_reg_t mask) |
| 1227 | { |
| 1228 | uint32_t tmp; |
| 1229 | tmp = ((Sercom *)hw)->I2CS.SYNCBUSY.reg; |
| 1230 | tmp &= mask; |
| 1231 | return tmp; |
| 1232 | } |
| 1233 | |
| 1234 | static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_read_SYNCBUSY_reg(const void *const hw) |
| 1235 | { |
| 1236 | return ((Sercom *)hw)->I2CS.SYNCBUSY.reg; |
| 1237 | } |
| 1238 | |
| 1239 | static inline bool hri_sercomspi_get_SYNCBUSY_SWRST_bit(const void *const hw) |
| 1240 | { |
| 1241 | return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_SWRST) >> SERCOM_SPI_SYNCBUSY_SWRST_Pos; |
| 1242 | } |
| 1243 | |
| 1244 | static inline bool hri_sercomspi_get_SYNCBUSY_ENABLE_bit(const void *const hw) |
| 1245 | { |
| 1246 | return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_ENABLE) >> SERCOM_SPI_SYNCBUSY_ENABLE_Pos; |
| 1247 | } |
| 1248 | |
| 1249 | static inline bool hri_sercomspi_get_SYNCBUSY_CTRLB_bit(const void *const hw) |
| 1250 | { |
| 1251 | return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_CTRLB) >> SERCOM_SPI_SYNCBUSY_CTRLB_Pos; |
| 1252 | } |
| 1253 | |
| 1254 | static inline bool hri_sercomspi_get_SYNCBUSY_LENGTH_bit(const void *const hw) |
| 1255 | { |
| 1256 | return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_LENGTH) >> SERCOM_SPI_SYNCBUSY_LENGTH_Pos; |
| 1257 | } |
| 1258 | |
| 1259 | static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_get_SYNCBUSY_reg(const void *const hw, |
| 1260 | hri_sercomspi_syncbusy_reg_t mask) |
| 1261 | { |
| 1262 | uint32_t tmp; |
| 1263 | tmp = ((Sercom *)hw)->SPI.SYNCBUSY.reg; |
| 1264 | tmp &= mask; |
| 1265 | return tmp; |
| 1266 | } |
| 1267 | |
| 1268 | static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_read_SYNCBUSY_reg(const void *const hw) |
| 1269 | { |
| 1270 | return ((Sercom *)hw)->SPI.SYNCBUSY.reg; |
| 1271 | } |
| 1272 | |
| 1273 | static inline bool hri_sercomusart_get_SYNCBUSY_SWRST_bit(const void *const hw) |
| 1274 | { |
| 1275 | return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) >> SERCOM_USART_SYNCBUSY_SWRST_Pos; |
| 1276 | } |
| 1277 | |
| 1278 | static inline bool hri_sercomusart_get_SYNCBUSY_ENABLE_bit(const void *const hw) |
| 1279 | { |
| 1280 | return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_ENABLE) >> SERCOM_USART_SYNCBUSY_ENABLE_Pos; |
| 1281 | } |
| 1282 | |
| 1283 | static inline bool hri_sercomusart_get_SYNCBUSY_CTRLB_bit(const void *const hw) |
| 1284 | { |
| 1285 | return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) >> SERCOM_USART_SYNCBUSY_CTRLB_Pos; |
| 1286 | } |
| 1287 | |
| 1288 | static inline bool hri_sercomusart_get_SYNCBUSY_RXERRCNT_bit(const void *const hw) |
| 1289 | { |
| 1290 | return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_RXERRCNT) >> SERCOM_USART_SYNCBUSY_RXERRCNT_Pos; |
| 1291 | } |
| 1292 | |
| 1293 | static inline bool hri_sercomusart_get_SYNCBUSY_LENGTH_bit(const void *const hw) |
| 1294 | { |
| 1295 | return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_LENGTH) >> SERCOM_USART_SYNCBUSY_LENGTH_Pos; |
| 1296 | } |
| 1297 | |
| 1298 | static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_get_SYNCBUSY_reg(const void *const hw, |
| 1299 | hri_sercomusart_syncbusy_reg_t mask) |
| 1300 | { |
| 1301 | uint32_t tmp; |
| 1302 | tmp = ((Sercom *)hw)->USART.SYNCBUSY.reg; |
| 1303 | tmp &= mask; |
| 1304 | return tmp; |
| 1305 | } |
| 1306 | |
| 1307 | static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_read_SYNCBUSY_reg(const void *const hw) |
| 1308 | { |
| 1309 | return ((Sercom *)hw)->USART.SYNCBUSY.reg; |
| 1310 | } |
| 1311 | |
| 1312 | static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_get_RXERRCNT_reg(const void *const hw, |
| 1313 | hri_sercomusart_rxerrcnt_reg_t mask) |
| 1314 | { |
| 1315 | uint8_t tmp; |
| 1316 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 1317 | tmp = ((Sercom *)hw)->USART.RXERRCNT.reg; |
| 1318 | tmp &= mask; |
| 1319 | return tmp; |
| 1320 | } |
| 1321 | |
| 1322 | static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_read_RXERRCNT_reg(const void *const hw) |
| 1323 | { |
| 1324 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 1325 | return ((Sercom *)hw)->USART.RXERRCNT.reg; |
| 1326 | } |
| 1327 | |
| 1328 | static inline void hri_sercomi2cm_set_CTRLA_SWRST_bit(const void *const hw) |
| 1329 | { |
| 1330 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1331 | ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SWRST; |
| 1332 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); |
| 1333 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1334 | } |
| 1335 | |
| 1336 | static inline bool hri_sercomi2cm_get_CTRLA_SWRST_bit(const void *const hw) |
| 1337 | { |
| 1338 | uint32_t tmp; |
| 1339 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); |
| 1340 | tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1341 | tmp = (tmp & SERCOM_I2CM_CTRLA_SWRST) >> SERCOM_I2CM_CTRLA_SWRST_Pos; |
| 1342 | return (bool)tmp; |
| 1343 | } |
| 1344 | |
| 1345 | static inline void hri_sercomi2cm_set_CTRLA_ENABLE_bit(const void *const hw) |
| 1346 | { |
| 1347 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1348 | ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE; |
| 1349 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); |
| 1350 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1351 | } |
| 1352 | |
| 1353 | static inline bool hri_sercomi2cm_get_CTRLA_ENABLE_bit(const void *const hw) |
| 1354 | { |
| 1355 | uint32_t tmp; |
| 1356 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); |
| 1357 | tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1358 | tmp = (tmp & SERCOM_I2CM_CTRLA_ENABLE) >> SERCOM_I2CM_CTRLA_ENABLE_Pos; |
| 1359 | return (bool)tmp; |
| 1360 | } |
| 1361 | |
| 1362 | static inline void hri_sercomi2cm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) |
| 1363 | { |
| 1364 | uint32_t tmp; |
| 1365 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1366 | tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1367 | tmp &= ~SERCOM_I2CM_CTRLA_ENABLE; |
| 1368 | tmp |= value << SERCOM_I2CM_CTRLA_ENABLE_Pos; |
| 1369 | ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; |
| 1370 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); |
| 1371 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1372 | } |
| 1373 | |
| 1374 | static inline void hri_sercomi2cm_clear_CTRLA_ENABLE_bit(const void *const hw) |
| 1375 | { |
| 1376 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1377 | ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE; |
| 1378 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); |
| 1379 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1380 | } |
| 1381 | |
| 1382 | static inline void hri_sercomi2cm_toggle_CTRLA_ENABLE_bit(const void *const hw) |
| 1383 | { |
| 1384 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1385 | ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_ENABLE; |
| 1386 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); |
| 1387 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1388 | } |
| 1389 | |
| 1390 | static inline void hri_sercomi2cm_set_CTRLA_RUNSTDBY_bit(const void *const hw) |
| 1391 | { |
| 1392 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1393 | ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_RUNSTDBY; |
| 1394 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1395 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1396 | } |
| 1397 | |
| 1398 | static inline bool hri_sercomi2cm_get_CTRLA_RUNSTDBY_bit(const void *const hw) |
| 1399 | { |
| 1400 | uint32_t tmp; |
| 1401 | tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1402 | tmp = (tmp & SERCOM_I2CM_CTRLA_RUNSTDBY) >> SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; |
| 1403 | return (bool)tmp; |
| 1404 | } |
| 1405 | |
| 1406 | static inline void hri_sercomi2cm_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) |
| 1407 | { |
| 1408 | uint32_t tmp; |
| 1409 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1410 | tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1411 | tmp &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; |
| 1412 | tmp |= value << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; |
| 1413 | ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; |
| 1414 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1415 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1416 | } |
| 1417 | |
| 1418 | static inline void hri_sercomi2cm_clear_CTRLA_RUNSTDBY_bit(const void *const hw) |
| 1419 | { |
| 1420 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1421 | ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; |
| 1422 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1423 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1424 | } |
| 1425 | |
| 1426 | static inline void hri_sercomi2cm_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) |
| 1427 | { |
| 1428 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1429 | ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_RUNSTDBY; |
| 1430 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1431 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1432 | } |
| 1433 | |
| 1434 | static inline void hri_sercomi2cm_set_CTRLA_PINOUT_bit(const void *const hw) |
| 1435 | { |
| 1436 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1437 | ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_PINOUT; |
| 1438 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1439 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1440 | } |
| 1441 | |
| 1442 | static inline bool hri_sercomi2cm_get_CTRLA_PINOUT_bit(const void *const hw) |
| 1443 | { |
| 1444 | uint32_t tmp; |
| 1445 | tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1446 | tmp = (tmp & SERCOM_I2CM_CTRLA_PINOUT) >> SERCOM_I2CM_CTRLA_PINOUT_Pos; |
| 1447 | return (bool)tmp; |
| 1448 | } |
| 1449 | |
| 1450 | static inline void hri_sercomi2cm_write_CTRLA_PINOUT_bit(const void *const hw, bool value) |
| 1451 | { |
| 1452 | uint32_t tmp; |
| 1453 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1454 | tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1455 | tmp &= ~SERCOM_I2CM_CTRLA_PINOUT; |
| 1456 | tmp |= value << SERCOM_I2CM_CTRLA_PINOUT_Pos; |
| 1457 | ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; |
| 1458 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1459 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1460 | } |
| 1461 | |
| 1462 | static inline void hri_sercomi2cm_clear_CTRLA_PINOUT_bit(const void *const hw) |
| 1463 | { |
| 1464 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1465 | ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_PINOUT; |
| 1466 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1467 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1468 | } |
| 1469 | |
| 1470 | static inline void hri_sercomi2cm_toggle_CTRLA_PINOUT_bit(const void *const hw) |
| 1471 | { |
| 1472 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1473 | ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_PINOUT; |
| 1474 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1475 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1476 | } |
| 1477 | |
| 1478 | static inline void hri_sercomi2cm_set_CTRLA_MEXTTOEN_bit(const void *const hw) |
| 1479 | { |
| 1480 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1481 | ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MEXTTOEN; |
| 1482 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1483 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1484 | } |
| 1485 | |
| 1486 | static inline bool hri_sercomi2cm_get_CTRLA_MEXTTOEN_bit(const void *const hw) |
| 1487 | { |
| 1488 | uint32_t tmp; |
| 1489 | tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1490 | tmp = (tmp & SERCOM_I2CM_CTRLA_MEXTTOEN) >> SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; |
| 1491 | return (bool)tmp; |
| 1492 | } |
| 1493 | |
| 1494 | static inline void hri_sercomi2cm_write_CTRLA_MEXTTOEN_bit(const void *const hw, bool value) |
| 1495 | { |
| 1496 | uint32_t tmp; |
| 1497 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1498 | tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1499 | tmp &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; |
| 1500 | tmp |= value << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; |
| 1501 | ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; |
| 1502 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1503 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1504 | } |
| 1505 | |
| 1506 | static inline void hri_sercomi2cm_clear_CTRLA_MEXTTOEN_bit(const void *const hw) |
| 1507 | { |
| 1508 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1509 | ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; |
| 1510 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1511 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1512 | } |
| 1513 | |
| 1514 | static inline void hri_sercomi2cm_toggle_CTRLA_MEXTTOEN_bit(const void *const hw) |
| 1515 | { |
| 1516 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1517 | ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MEXTTOEN; |
| 1518 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1519 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1520 | } |
| 1521 | |
| 1522 | static inline void hri_sercomi2cm_set_CTRLA_SEXTTOEN_bit(const void *const hw) |
| 1523 | { |
| 1524 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1525 | ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SEXTTOEN; |
| 1526 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1527 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1528 | } |
| 1529 | |
| 1530 | static inline bool hri_sercomi2cm_get_CTRLA_SEXTTOEN_bit(const void *const hw) |
| 1531 | { |
| 1532 | uint32_t tmp; |
| 1533 | tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1534 | tmp = (tmp & SERCOM_I2CM_CTRLA_SEXTTOEN) >> SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; |
| 1535 | return (bool)tmp; |
| 1536 | } |
| 1537 | |
| 1538 | static inline void hri_sercomi2cm_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) |
| 1539 | { |
| 1540 | uint32_t tmp; |
| 1541 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1542 | tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1543 | tmp &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; |
| 1544 | tmp |= value << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; |
| 1545 | ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; |
| 1546 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1547 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1548 | } |
| 1549 | |
| 1550 | static inline void hri_sercomi2cm_clear_CTRLA_SEXTTOEN_bit(const void *const hw) |
| 1551 | { |
| 1552 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1553 | ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; |
| 1554 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1555 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1556 | } |
| 1557 | |
| 1558 | static inline void hri_sercomi2cm_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) |
| 1559 | { |
| 1560 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1561 | ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SEXTTOEN; |
| 1562 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1563 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1564 | } |
| 1565 | |
| 1566 | static inline void hri_sercomi2cm_set_CTRLA_SCLSM_bit(const void *const hw) |
| 1567 | { |
| 1568 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1569 | ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SCLSM; |
| 1570 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1571 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1572 | } |
| 1573 | |
| 1574 | static inline bool hri_sercomi2cm_get_CTRLA_SCLSM_bit(const void *const hw) |
| 1575 | { |
| 1576 | uint32_t tmp; |
| 1577 | tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1578 | tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos; |
| 1579 | return (bool)tmp; |
| 1580 | } |
| 1581 | |
| 1582 | static inline void hri_sercomi2cm_write_CTRLA_SCLSM_bit(const void *const hw, bool value) |
| 1583 | { |
| 1584 | uint32_t tmp; |
| 1585 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1586 | tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1587 | tmp &= ~SERCOM_I2CM_CTRLA_SCLSM; |
| 1588 | tmp |= value << SERCOM_I2CM_CTRLA_SCLSM_Pos; |
| 1589 | ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; |
| 1590 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1591 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1592 | } |
| 1593 | |
| 1594 | static inline void hri_sercomi2cm_clear_CTRLA_SCLSM_bit(const void *const hw) |
| 1595 | { |
| 1596 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1597 | ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SCLSM; |
| 1598 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1599 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1600 | } |
| 1601 | |
| 1602 | static inline void hri_sercomi2cm_toggle_CTRLA_SCLSM_bit(const void *const hw) |
| 1603 | { |
| 1604 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1605 | ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SCLSM; |
| 1606 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1607 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1608 | } |
| 1609 | |
| 1610 | static inline void hri_sercomi2cm_set_CTRLA_LOWTOUTEN_bit(const void *const hw) |
| 1611 | { |
| 1612 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1613 | ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_LOWTOUTEN; |
| 1614 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1615 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1616 | } |
| 1617 | |
| 1618 | static inline bool hri_sercomi2cm_get_CTRLA_LOWTOUTEN_bit(const void *const hw) |
| 1619 | { |
| 1620 | uint32_t tmp; |
| 1621 | tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1622 | tmp = (tmp & SERCOM_I2CM_CTRLA_LOWTOUTEN) >> SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; |
| 1623 | return (bool)tmp; |
| 1624 | } |
| 1625 | |
| 1626 | static inline void hri_sercomi2cm_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) |
| 1627 | { |
| 1628 | uint32_t tmp; |
| 1629 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1630 | tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1631 | tmp &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; |
| 1632 | tmp |= value << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; |
| 1633 | ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; |
| 1634 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1635 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1636 | } |
| 1637 | |
| 1638 | static inline void hri_sercomi2cm_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) |
| 1639 | { |
| 1640 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1641 | ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; |
| 1642 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1643 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1644 | } |
| 1645 | |
| 1646 | static inline void hri_sercomi2cm_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) |
| 1647 | { |
| 1648 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1649 | ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_LOWTOUTEN; |
| 1650 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1651 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1652 | } |
| 1653 | |
| 1654 | static inline void hri_sercomi2cm_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) |
| 1655 | { |
| 1656 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1657 | ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MODE(mask); |
| 1658 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1659 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1660 | } |
| 1661 | |
| 1662 | static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_MODE_bf(const void *const hw, |
| 1663 | hri_sercomi2cm_ctrla_reg_t mask) |
| 1664 | { |
| 1665 | uint32_t tmp; |
| 1666 | tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1667 | tmp = (tmp & SERCOM_I2CM_CTRLA_MODE(mask)) >> SERCOM_I2CM_CTRLA_MODE_Pos; |
| 1668 | return tmp; |
| 1669 | } |
| 1670 | |
| 1671 | static inline void hri_sercomi2cm_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) |
| 1672 | { |
| 1673 | uint32_t tmp; |
| 1674 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1675 | tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1676 | tmp &= ~SERCOM_I2CM_CTRLA_MODE_Msk; |
| 1677 | tmp |= SERCOM_I2CM_CTRLA_MODE(data); |
| 1678 | ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; |
| 1679 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1680 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1681 | } |
| 1682 | |
| 1683 | static inline void hri_sercomi2cm_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) |
| 1684 | { |
| 1685 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1686 | ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MODE(mask); |
| 1687 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1688 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1689 | } |
| 1690 | |
| 1691 | static inline void hri_sercomi2cm_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) |
| 1692 | { |
| 1693 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1694 | ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MODE(mask); |
| 1695 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1696 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1697 | } |
| 1698 | |
| 1699 | static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_MODE_bf(const void *const hw) |
| 1700 | { |
| 1701 | uint32_t tmp; |
| 1702 | tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1703 | tmp = (tmp & SERCOM_I2CM_CTRLA_MODE_Msk) >> SERCOM_I2CM_CTRLA_MODE_Pos; |
| 1704 | return tmp; |
| 1705 | } |
| 1706 | |
| 1707 | static inline void hri_sercomi2cm_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) |
| 1708 | { |
| 1709 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1710 | ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SDAHOLD(mask); |
| 1711 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1712 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1713 | } |
| 1714 | |
| 1715 | static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SDAHOLD_bf(const void *const hw, |
| 1716 | hri_sercomi2cm_ctrla_reg_t mask) |
| 1717 | { |
| 1718 | uint32_t tmp; |
| 1719 | tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1720 | tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; |
| 1721 | return tmp; |
| 1722 | } |
| 1723 | |
| 1724 | static inline void hri_sercomi2cm_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) |
| 1725 | { |
| 1726 | uint32_t tmp; |
| 1727 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1728 | tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1729 | tmp &= ~SERCOM_I2CM_CTRLA_SDAHOLD_Msk; |
| 1730 | tmp |= SERCOM_I2CM_CTRLA_SDAHOLD(data); |
| 1731 | ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; |
| 1732 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1733 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1734 | } |
| 1735 | |
| 1736 | static inline void hri_sercomi2cm_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) |
| 1737 | { |
| 1738 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1739 | ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SDAHOLD(mask); |
| 1740 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1741 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1742 | } |
| 1743 | |
| 1744 | static inline void hri_sercomi2cm_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) |
| 1745 | { |
| 1746 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1747 | ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SDAHOLD(mask); |
| 1748 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1749 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1750 | } |
| 1751 | |
| 1752 | static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SDAHOLD_bf(const void *const hw) |
| 1753 | { |
| 1754 | uint32_t tmp; |
| 1755 | tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1756 | tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; |
| 1757 | return tmp; |
| 1758 | } |
| 1759 | |
| 1760 | static inline void hri_sercomi2cm_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) |
| 1761 | { |
| 1762 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1763 | ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SPEED(mask); |
| 1764 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1765 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1766 | } |
| 1767 | |
| 1768 | static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SPEED_bf(const void *const hw, |
| 1769 | hri_sercomi2cm_ctrla_reg_t mask) |
| 1770 | { |
| 1771 | uint32_t tmp; |
| 1772 | tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1773 | tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED(mask)) >> SERCOM_I2CM_CTRLA_SPEED_Pos; |
| 1774 | return tmp; |
| 1775 | } |
| 1776 | |
| 1777 | static inline void hri_sercomi2cm_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) |
| 1778 | { |
| 1779 | uint32_t tmp; |
| 1780 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1781 | tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1782 | tmp &= ~SERCOM_I2CM_CTRLA_SPEED_Msk; |
| 1783 | tmp |= SERCOM_I2CM_CTRLA_SPEED(data); |
| 1784 | ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; |
| 1785 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1786 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1787 | } |
| 1788 | |
| 1789 | static inline void hri_sercomi2cm_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) |
| 1790 | { |
| 1791 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1792 | ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SPEED(mask); |
| 1793 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1794 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1795 | } |
| 1796 | |
| 1797 | static inline void hri_sercomi2cm_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) |
| 1798 | { |
| 1799 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1800 | ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SPEED(mask); |
| 1801 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1802 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1803 | } |
| 1804 | |
| 1805 | static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SPEED_bf(const void *const hw) |
| 1806 | { |
| 1807 | uint32_t tmp; |
| 1808 | tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1809 | tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; |
| 1810 | return tmp; |
| 1811 | } |
| 1812 | |
| 1813 | static inline void hri_sercomi2cm_set_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) |
| 1814 | { |
| 1815 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1816 | ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_INACTOUT(mask); |
| 1817 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1818 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1819 | } |
| 1820 | |
| 1821 | static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_INACTOUT_bf(const void *const hw, |
| 1822 | hri_sercomi2cm_ctrla_reg_t mask) |
| 1823 | { |
| 1824 | uint32_t tmp; |
| 1825 | tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1826 | tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT(mask)) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; |
| 1827 | return tmp; |
| 1828 | } |
| 1829 | |
| 1830 | static inline void hri_sercomi2cm_write_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) |
| 1831 | { |
| 1832 | uint32_t tmp; |
| 1833 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1834 | tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1835 | tmp &= ~SERCOM_I2CM_CTRLA_INACTOUT_Msk; |
| 1836 | tmp |= SERCOM_I2CM_CTRLA_INACTOUT(data); |
| 1837 | ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; |
| 1838 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1839 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1840 | } |
| 1841 | |
| 1842 | static inline void hri_sercomi2cm_clear_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) |
| 1843 | { |
| 1844 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1845 | ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_INACTOUT(mask); |
| 1846 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1847 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1848 | } |
| 1849 | |
| 1850 | static inline void hri_sercomi2cm_toggle_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) |
| 1851 | { |
| 1852 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1853 | ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_INACTOUT(mask); |
| 1854 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); |
| 1855 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1856 | } |
| 1857 | |
| 1858 | static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_INACTOUT_bf(const void *const hw) |
| 1859 | { |
| 1860 | uint32_t tmp; |
| 1861 | tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1862 | tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT_Msk) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; |
| 1863 | return tmp; |
| 1864 | } |
| 1865 | |
| 1866 | static inline void hri_sercomi2cm_set_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) |
| 1867 | { |
| 1868 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1869 | ((Sercom *)hw)->I2CM.CTRLA.reg |= mask; |
| 1870 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); |
| 1871 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1872 | } |
| 1873 | |
| 1874 | static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_reg(const void *const hw, |
| 1875 | hri_sercomi2cm_ctrla_reg_t mask) |
| 1876 | { |
| 1877 | uint32_t tmp; |
| 1878 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); |
| 1879 | tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1880 | tmp &= mask; |
| 1881 | return tmp; |
| 1882 | } |
| 1883 | |
| 1884 | static inline void hri_sercomi2cm_write_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) |
| 1885 | { |
| 1886 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1887 | ((Sercom *)hw)->I2CM.CTRLA.reg = data; |
| 1888 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); |
| 1889 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1890 | } |
| 1891 | |
| 1892 | static inline void hri_sercomi2cm_clear_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) |
| 1893 | { |
| 1894 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1895 | ((Sercom *)hw)->I2CM.CTRLA.reg &= ~mask; |
| 1896 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); |
| 1897 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1898 | } |
| 1899 | |
| 1900 | static inline void hri_sercomi2cm_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) |
| 1901 | { |
| 1902 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1903 | ((Sercom *)hw)->I2CM.CTRLA.reg ^= mask; |
| 1904 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); |
| 1905 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1906 | } |
| 1907 | |
| 1908 | static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_reg(const void *const hw) |
| 1909 | { |
| 1910 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); |
| 1911 | return ((Sercom *)hw)->I2CM.CTRLA.reg; |
| 1912 | } |
| 1913 | |
| 1914 | static inline void hri_sercomi2cs_set_CTRLA_SWRST_bit(const void *const hw) |
| 1915 | { |
| 1916 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1917 | ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SWRST; |
| 1918 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); |
| 1919 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1920 | } |
| 1921 | |
| 1922 | static inline bool hri_sercomi2cs_get_CTRLA_SWRST_bit(const void *const hw) |
| 1923 | { |
| 1924 | uint32_t tmp; |
| 1925 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); |
| 1926 | tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; |
| 1927 | tmp = (tmp & SERCOM_I2CS_CTRLA_SWRST) >> SERCOM_I2CS_CTRLA_SWRST_Pos; |
| 1928 | return (bool)tmp; |
| 1929 | } |
| 1930 | |
| 1931 | static inline void hri_sercomi2cs_set_CTRLA_ENABLE_bit(const void *const hw) |
| 1932 | { |
| 1933 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1934 | ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE; |
| 1935 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); |
| 1936 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1937 | } |
| 1938 | |
| 1939 | static inline bool hri_sercomi2cs_get_CTRLA_ENABLE_bit(const void *const hw) |
| 1940 | { |
| 1941 | uint32_t tmp; |
| 1942 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); |
| 1943 | tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; |
| 1944 | tmp = (tmp & SERCOM_I2CS_CTRLA_ENABLE) >> SERCOM_I2CS_CTRLA_ENABLE_Pos; |
| 1945 | return (bool)tmp; |
| 1946 | } |
| 1947 | |
| 1948 | static inline void hri_sercomi2cs_write_CTRLA_ENABLE_bit(const void *const hw, bool value) |
| 1949 | { |
| 1950 | uint32_t tmp; |
| 1951 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1952 | tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; |
| 1953 | tmp &= ~SERCOM_I2CS_CTRLA_ENABLE; |
| 1954 | tmp |= value << SERCOM_I2CS_CTRLA_ENABLE_Pos; |
| 1955 | ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; |
| 1956 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); |
| 1957 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1958 | } |
| 1959 | |
| 1960 | static inline void hri_sercomi2cs_clear_CTRLA_ENABLE_bit(const void *const hw) |
| 1961 | { |
| 1962 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1963 | ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE; |
| 1964 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); |
| 1965 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1966 | } |
| 1967 | |
| 1968 | static inline void hri_sercomi2cs_toggle_CTRLA_ENABLE_bit(const void *const hw) |
| 1969 | { |
| 1970 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1971 | ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_ENABLE; |
| 1972 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); |
| 1973 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1974 | } |
| 1975 | |
| 1976 | static inline void hri_sercomi2cs_set_CTRLA_RUNSTDBY_bit(const void *const hw) |
| 1977 | { |
| 1978 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1979 | ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_RUNSTDBY; |
| 1980 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 1981 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 1982 | } |
| 1983 | |
| 1984 | static inline bool hri_sercomi2cs_get_CTRLA_RUNSTDBY_bit(const void *const hw) |
| 1985 | { |
| 1986 | uint32_t tmp; |
| 1987 | tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; |
| 1988 | tmp = (tmp & SERCOM_I2CS_CTRLA_RUNSTDBY) >> SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; |
| 1989 | return (bool)tmp; |
| 1990 | } |
| 1991 | |
| 1992 | static inline void hri_sercomi2cs_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) |
| 1993 | { |
| 1994 | uint32_t tmp; |
| 1995 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 1996 | tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; |
| 1997 | tmp &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; |
| 1998 | tmp |= value << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; |
| 1999 | ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; |
| 2000 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2001 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2002 | } |
| 2003 | |
| 2004 | static inline void hri_sercomi2cs_clear_CTRLA_RUNSTDBY_bit(const void *const hw) |
| 2005 | { |
| 2006 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2007 | ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; |
| 2008 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2009 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2010 | } |
| 2011 | |
| 2012 | static inline void hri_sercomi2cs_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) |
| 2013 | { |
| 2014 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2015 | ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_RUNSTDBY; |
| 2016 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2017 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2018 | } |
| 2019 | |
| 2020 | static inline void hri_sercomi2cs_set_CTRLA_PINOUT_bit(const void *const hw) |
| 2021 | { |
| 2022 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2023 | ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_PINOUT; |
| 2024 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2025 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2026 | } |
| 2027 | |
| 2028 | static inline bool hri_sercomi2cs_get_CTRLA_PINOUT_bit(const void *const hw) |
| 2029 | { |
| 2030 | uint32_t tmp; |
| 2031 | tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; |
| 2032 | tmp = (tmp & SERCOM_I2CS_CTRLA_PINOUT) >> SERCOM_I2CS_CTRLA_PINOUT_Pos; |
| 2033 | return (bool)tmp; |
| 2034 | } |
| 2035 | |
| 2036 | static inline void hri_sercomi2cs_write_CTRLA_PINOUT_bit(const void *const hw, bool value) |
| 2037 | { |
| 2038 | uint32_t tmp; |
| 2039 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2040 | tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; |
| 2041 | tmp &= ~SERCOM_I2CS_CTRLA_PINOUT; |
| 2042 | tmp |= value << SERCOM_I2CS_CTRLA_PINOUT_Pos; |
| 2043 | ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; |
| 2044 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2045 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2046 | } |
| 2047 | |
| 2048 | static inline void hri_sercomi2cs_clear_CTRLA_PINOUT_bit(const void *const hw) |
| 2049 | { |
| 2050 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2051 | ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_PINOUT; |
| 2052 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2053 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2054 | } |
| 2055 | |
| 2056 | static inline void hri_sercomi2cs_toggle_CTRLA_PINOUT_bit(const void *const hw) |
| 2057 | { |
| 2058 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2059 | ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_PINOUT; |
| 2060 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2061 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2062 | } |
| 2063 | |
| 2064 | static inline void hri_sercomi2cs_set_CTRLA_SEXTTOEN_bit(const void *const hw) |
| 2065 | { |
| 2066 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2067 | ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SEXTTOEN; |
| 2068 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2069 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2070 | } |
| 2071 | |
| 2072 | static inline bool hri_sercomi2cs_get_CTRLA_SEXTTOEN_bit(const void *const hw) |
| 2073 | { |
| 2074 | uint32_t tmp; |
| 2075 | tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; |
| 2076 | tmp = (tmp & SERCOM_I2CS_CTRLA_SEXTTOEN) >> SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; |
| 2077 | return (bool)tmp; |
| 2078 | } |
| 2079 | |
| 2080 | static inline void hri_sercomi2cs_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) |
| 2081 | { |
| 2082 | uint32_t tmp; |
| 2083 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2084 | tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; |
| 2085 | tmp &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; |
| 2086 | tmp |= value << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; |
| 2087 | ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; |
| 2088 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2089 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2090 | } |
| 2091 | |
| 2092 | static inline void hri_sercomi2cs_clear_CTRLA_SEXTTOEN_bit(const void *const hw) |
| 2093 | { |
| 2094 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2095 | ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; |
| 2096 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2097 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2098 | } |
| 2099 | |
| 2100 | static inline void hri_sercomi2cs_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) |
| 2101 | { |
| 2102 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2103 | ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SEXTTOEN; |
| 2104 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2105 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2106 | } |
| 2107 | |
| 2108 | static inline void hri_sercomi2cs_set_CTRLA_SCLSM_bit(const void *const hw) |
| 2109 | { |
| 2110 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2111 | ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SCLSM; |
| 2112 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2113 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2114 | } |
| 2115 | |
| 2116 | static inline bool hri_sercomi2cs_get_CTRLA_SCLSM_bit(const void *const hw) |
| 2117 | { |
| 2118 | uint32_t tmp; |
| 2119 | tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; |
| 2120 | tmp = (tmp & SERCOM_I2CS_CTRLA_SCLSM) >> SERCOM_I2CS_CTRLA_SCLSM_Pos; |
| 2121 | return (bool)tmp; |
| 2122 | } |
| 2123 | |
| 2124 | static inline void hri_sercomi2cs_write_CTRLA_SCLSM_bit(const void *const hw, bool value) |
| 2125 | { |
| 2126 | uint32_t tmp; |
| 2127 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2128 | tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; |
| 2129 | tmp &= ~SERCOM_I2CS_CTRLA_SCLSM; |
| 2130 | tmp |= value << SERCOM_I2CS_CTRLA_SCLSM_Pos; |
| 2131 | ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; |
| 2132 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2133 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2134 | } |
| 2135 | |
| 2136 | static inline void hri_sercomi2cs_clear_CTRLA_SCLSM_bit(const void *const hw) |
| 2137 | { |
| 2138 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2139 | ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SCLSM; |
| 2140 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2141 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2142 | } |
| 2143 | |
| 2144 | static inline void hri_sercomi2cs_toggle_CTRLA_SCLSM_bit(const void *const hw) |
| 2145 | { |
| 2146 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2147 | ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SCLSM; |
| 2148 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2149 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2150 | } |
| 2151 | |
| 2152 | static inline void hri_sercomi2cs_set_CTRLA_LOWTOUTEN_bit(const void *const hw) |
| 2153 | { |
| 2154 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2155 | ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_LOWTOUTEN; |
| 2156 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2157 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2158 | } |
| 2159 | |
| 2160 | static inline bool hri_sercomi2cs_get_CTRLA_LOWTOUTEN_bit(const void *const hw) |
| 2161 | { |
| 2162 | uint32_t tmp; |
| 2163 | tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; |
| 2164 | tmp = (tmp & SERCOM_I2CS_CTRLA_LOWTOUTEN) >> SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; |
| 2165 | return (bool)tmp; |
| 2166 | } |
| 2167 | |
| 2168 | static inline void hri_sercomi2cs_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) |
| 2169 | { |
| 2170 | uint32_t tmp; |
| 2171 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2172 | tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; |
| 2173 | tmp &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; |
| 2174 | tmp |= value << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; |
| 2175 | ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; |
| 2176 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2177 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2178 | } |
| 2179 | |
| 2180 | static inline void hri_sercomi2cs_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) |
| 2181 | { |
| 2182 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2183 | ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; |
| 2184 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2185 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2186 | } |
| 2187 | |
| 2188 | static inline void hri_sercomi2cs_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) |
| 2189 | { |
| 2190 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2191 | ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_LOWTOUTEN; |
| 2192 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2193 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2194 | } |
| 2195 | |
| 2196 | static inline void hri_sercomi2cs_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) |
| 2197 | { |
| 2198 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2199 | ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_MODE(mask); |
| 2200 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2201 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2202 | } |
| 2203 | |
| 2204 | static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_MODE_bf(const void *const hw, |
| 2205 | hri_sercomi2cs_ctrla_reg_t mask) |
| 2206 | { |
| 2207 | uint32_t tmp; |
| 2208 | tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; |
| 2209 | tmp = (tmp & SERCOM_I2CS_CTRLA_MODE(mask)) >> SERCOM_I2CS_CTRLA_MODE_Pos; |
| 2210 | return tmp; |
| 2211 | } |
| 2212 | |
| 2213 | static inline void hri_sercomi2cs_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) |
| 2214 | { |
| 2215 | uint32_t tmp; |
| 2216 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2217 | tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; |
| 2218 | tmp &= ~SERCOM_I2CS_CTRLA_MODE_Msk; |
| 2219 | tmp |= SERCOM_I2CS_CTRLA_MODE(data); |
| 2220 | ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; |
| 2221 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2222 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2223 | } |
| 2224 | |
| 2225 | static inline void hri_sercomi2cs_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) |
| 2226 | { |
| 2227 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2228 | ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_MODE(mask); |
| 2229 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2230 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2231 | } |
| 2232 | |
| 2233 | static inline void hri_sercomi2cs_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) |
| 2234 | { |
| 2235 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2236 | ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_MODE(mask); |
| 2237 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2238 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2239 | } |
| 2240 | |
| 2241 | static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_MODE_bf(const void *const hw) |
| 2242 | { |
| 2243 | uint32_t tmp; |
| 2244 | tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; |
| 2245 | tmp = (tmp & SERCOM_I2CS_CTRLA_MODE_Msk) >> SERCOM_I2CS_CTRLA_MODE_Pos; |
| 2246 | return tmp; |
| 2247 | } |
| 2248 | |
| 2249 | static inline void hri_sercomi2cs_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) |
| 2250 | { |
| 2251 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2252 | ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SDAHOLD(mask); |
| 2253 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2254 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2255 | } |
| 2256 | |
| 2257 | static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SDAHOLD_bf(const void *const hw, |
| 2258 | hri_sercomi2cs_ctrla_reg_t mask) |
| 2259 | { |
| 2260 | uint32_t tmp; |
| 2261 | tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; |
| 2262 | tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; |
| 2263 | return tmp; |
| 2264 | } |
| 2265 | |
| 2266 | static inline void hri_sercomi2cs_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) |
| 2267 | { |
| 2268 | uint32_t tmp; |
| 2269 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2270 | tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; |
| 2271 | tmp &= ~SERCOM_I2CS_CTRLA_SDAHOLD_Msk; |
| 2272 | tmp |= SERCOM_I2CS_CTRLA_SDAHOLD(data); |
| 2273 | ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; |
| 2274 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2275 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2276 | } |
| 2277 | |
| 2278 | static inline void hri_sercomi2cs_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) |
| 2279 | { |
| 2280 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2281 | ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SDAHOLD(mask); |
| 2282 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2283 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2284 | } |
| 2285 | |
| 2286 | static inline void hri_sercomi2cs_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) |
| 2287 | { |
| 2288 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2289 | ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SDAHOLD(mask); |
| 2290 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2291 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2292 | } |
| 2293 | |
| 2294 | static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SDAHOLD_bf(const void *const hw) |
| 2295 | { |
| 2296 | uint32_t tmp; |
| 2297 | tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; |
| 2298 | tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; |
| 2299 | return tmp; |
| 2300 | } |
| 2301 | |
| 2302 | static inline void hri_sercomi2cs_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) |
| 2303 | { |
| 2304 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2305 | ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SPEED(mask); |
| 2306 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2307 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2308 | } |
| 2309 | |
| 2310 | static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SPEED_bf(const void *const hw, |
| 2311 | hri_sercomi2cs_ctrla_reg_t mask) |
| 2312 | { |
| 2313 | uint32_t tmp; |
| 2314 | tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; |
| 2315 | tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED(mask)) >> SERCOM_I2CS_CTRLA_SPEED_Pos; |
| 2316 | return tmp; |
| 2317 | } |
| 2318 | |
| 2319 | static inline void hri_sercomi2cs_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) |
| 2320 | { |
| 2321 | uint32_t tmp; |
| 2322 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2323 | tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; |
| 2324 | tmp &= ~SERCOM_I2CS_CTRLA_SPEED_Msk; |
| 2325 | tmp |= SERCOM_I2CS_CTRLA_SPEED(data); |
| 2326 | ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; |
| 2327 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2328 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2329 | } |
| 2330 | |
| 2331 | static inline void hri_sercomi2cs_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) |
| 2332 | { |
| 2333 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2334 | ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SPEED(mask); |
| 2335 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2336 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2337 | } |
| 2338 | |
| 2339 | static inline void hri_sercomi2cs_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) |
| 2340 | { |
| 2341 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2342 | ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SPEED(mask); |
| 2343 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 2344 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2345 | } |
| 2346 | |
| 2347 | static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SPEED_bf(const void *const hw) |
| 2348 | { |
| 2349 | uint32_t tmp; |
| 2350 | tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; |
| 2351 | tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED_Msk) >> SERCOM_I2CS_CTRLA_SPEED_Pos; |
| 2352 | return tmp; |
| 2353 | } |
| 2354 | |
| 2355 | static inline void hri_sercomi2cs_set_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) |
| 2356 | { |
| 2357 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2358 | ((Sercom *)hw)->I2CS.CTRLA.reg |= mask; |
| 2359 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); |
| 2360 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2361 | } |
| 2362 | |
| 2363 | static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_reg(const void *const hw, |
| 2364 | hri_sercomi2cs_ctrla_reg_t mask) |
| 2365 | { |
| 2366 | uint32_t tmp; |
| 2367 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); |
| 2368 | tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; |
| 2369 | tmp &= mask; |
| 2370 | return tmp; |
| 2371 | } |
| 2372 | |
| 2373 | static inline void hri_sercomi2cs_write_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) |
| 2374 | { |
| 2375 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2376 | ((Sercom *)hw)->I2CS.CTRLA.reg = data; |
| 2377 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); |
| 2378 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2379 | } |
| 2380 | |
| 2381 | static inline void hri_sercomi2cs_clear_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) |
| 2382 | { |
| 2383 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2384 | ((Sercom *)hw)->I2CS.CTRLA.reg &= ~mask; |
| 2385 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); |
| 2386 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2387 | } |
| 2388 | |
| 2389 | static inline void hri_sercomi2cs_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) |
| 2390 | { |
| 2391 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2392 | ((Sercom *)hw)->I2CS.CTRLA.reg ^= mask; |
| 2393 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); |
| 2394 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2395 | } |
| 2396 | |
| 2397 | static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_reg(const void *const hw) |
| 2398 | { |
| 2399 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); |
| 2400 | return ((Sercom *)hw)->I2CS.CTRLA.reg; |
| 2401 | } |
| 2402 | |
| 2403 | static inline void hri_sercomspi_set_CTRLA_SWRST_bit(const void *const hw) |
| 2404 | { |
| 2405 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2406 | ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST; |
| 2407 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); |
| 2408 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2409 | } |
| 2410 | |
| 2411 | static inline bool hri_sercomspi_get_CTRLA_SWRST_bit(const void *const hw) |
| 2412 | { |
| 2413 | uint32_t tmp; |
| 2414 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); |
| 2415 | tmp = ((Sercom *)hw)->SPI.CTRLA.reg; |
| 2416 | tmp = (tmp & SERCOM_SPI_CTRLA_SWRST) >> SERCOM_SPI_CTRLA_SWRST_Pos; |
| 2417 | return (bool)tmp; |
| 2418 | } |
| 2419 | |
| 2420 | static inline void hri_sercomspi_set_CTRLA_ENABLE_bit(const void *const hw) |
| 2421 | { |
| 2422 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2423 | ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE; |
| 2424 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); |
| 2425 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2426 | } |
| 2427 | |
| 2428 | static inline bool hri_sercomspi_get_CTRLA_ENABLE_bit(const void *const hw) |
| 2429 | { |
| 2430 | uint32_t tmp; |
| 2431 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); |
| 2432 | tmp = ((Sercom *)hw)->SPI.CTRLA.reg; |
| 2433 | tmp = (tmp & SERCOM_SPI_CTRLA_ENABLE) >> SERCOM_SPI_CTRLA_ENABLE_Pos; |
| 2434 | return (bool)tmp; |
| 2435 | } |
| 2436 | |
| 2437 | static inline void hri_sercomspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value) |
| 2438 | { |
| 2439 | uint32_t tmp; |
| 2440 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2441 | tmp = ((Sercom *)hw)->SPI.CTRLA.reg; |
| 2442 | tmp &= ~SERCOM_SPI_CTRLA_ENABLE; |
| 2443 | tmp |= value << SERCOM_SPI_CTRLA_ENABLE_Pos; |
| 2444 | ((Sercom *)hw)->SPI.CTRLA.reg = tmp; |
| 2445 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); |
| 2446 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2447 | } |
| 2448 | |
| 2449 | static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw) |
| 2450 | { |
| 2451 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2452 | ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE; |
| 2453 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); |
| 2454 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2455 | } |
| 2456 | |
| 2457 | static inline void hri_sercomspi_toggle_CTRLA_ENABLE_bit(const void *const hw) |
| 2458 | { |
| 2459 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2460 | ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_ENABLE; |
| 2461 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); |
| 2462 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2463 | } |
| 2464 | |
| 2465 | static inline void hri_sercomspi_set_CTRLA_RUNSTDBY_bit(const void *const hw) |
| 2466 | { |
| 2467 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2468 | ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_RUNSTDBY; |
| 2469 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2470 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2471 | } |
| 2472 | |
| 2473 | static inline bool hri_sercomspi_get_CTRLA_RUNSTDBY_bit(const void *const hw) |
| 2474 | { |
| 2475 | uint32_t tmp; |
| 2476 | tmp = ((Sercom *)hw)->SPI.CTRLA.reg; |
| 2477 | tmp = (tmp & SERCOM_SPI_CTRLA_RUNSTDBY) >> SERCOM_SPI_CTRLA_RUNSTDBY_Pos; |
| 2478 | return (bool)tmp; |
| 2479 | } |
| 2480 | |
| 2481 | static inline void hri_sercomspi_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) |
| 2482 | { |
| 2483 | uint32_t tmp; |
| 2484 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2485 | tmp = ((Sercom *)hw)->SPI.CTRLA.reg; |
| 2486 | tmp &= ~SERCOM_SPI_CTRLA_RUNSTDBY; |
| 2487 | tmp |= value << SERCOM_SPI_CTRLA_RUNSTDBY_Pos; |
| 2488 | ((Sercom *)hw)->SPI.CTRLA.reg = tmp; |
| 2489 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2490 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2491 | } |
| 2492 | |
| 2493 | static inline void hri_sercomspi_clear_CTRLA_RUNSTDBY_bit(const void *const hw) |
| 2494 | { |
| 2495 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2496 | ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_RUNSTDBY; |
| 2497 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2498 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2499 | } |
| 2500 | |
| 2501 | static inline void hri_sercomspi_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) |
| 2502 | { |
| 2503 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2504 | ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_RUNSTDBY; |
| 2505 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2506 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2507 | } |
| 2508 | |
| 2509 | static inline void hri_sercomspi_set_CTRLA_IBON_bit(const void *const hw) |
| 2510 | { |
| 2511 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2512 | ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_IBON; |
| 2513 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2514 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2515 | } |
| 2516 | |
| 2517 | static inline bool hri_sercomspi_get_CTRLA_IBON_bit(const void *const hw) |
| 2518 | { |
| 2519 | uint32_t tmp; |
| 2520 | tmp = ((Sercom *)hw)->SPI.CTRLA.reg; |
| 2521 | tmp = (tmp & SERCOM_SPI_CTRLA_IBON) >> SERCOM_SPI_CTRLA_IBON_Pos; |
| 2522 | return (bool)tmp; |
| 2523 | } |
| 2524 | |
| 2525 | static inline void hri_sercomspi_write_CTRLA_IBON_bit(const void *const hw, bool value) |
| 2526 | { |
| 2527 | uint32_t tmp; |
| 2528 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2529 | tmp = ((Sercom *)hw)->SPI.CTRLA.reg; |
| 2530 | tmp &= ~SERCOM_SPI_CTRLA_IBON; |
| 2531 | tmp |= value << SERCOM_SPI_CTRLA_IBON_Pos; |
| 2532 | ((Sercom *)hw)->SPI.CTRLA.reg = tmp; |
| 2533 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2534 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2535 | } |
| 2536 | |
| 2537 | static inline void hri_sercomspi_clear_CTRLA_IBON_bit(const void *const hw) |
| 2538 | { |
| 2539 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2540 | ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_IBON; |
| 2541 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2542 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2543 | } |
| 2544 | |
| 2545 | static inline void hri_sercomspi_toggle_CTRLA_IBON_bit(const void *const hw) |
| 2546 | { |
| 2547 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2548 | ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_IBON; |
| 2549 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2550 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2551 | } |
| 2552 | |
| 2553 | static inline void hri_sercomspi_set_CTRLA_CPHA_bit(const void *const hw) |
| 2554 | { |
| 2555 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2556 | ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPHA; |
| 2557 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2558 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2559 | } |
| 2560 | |
| 2561 | static inline bool hri_sercomspi_get_CTRLA_CPHA_bit(const void *const hw) |
| 2562 | { |
| 2563 | uint32_t tmp; |
| 2564 | tmp = ((Sercom *)hw)->SPI.CTRLA.reg; |
| 2565 | tmp = (tmp & SERCOM_SPI_CTRLA_CPHA) >> SERCOM_SPI_CTRLA_CPHA_Pos; |
| 2566 | return (bool)tmp; |
| 2567 | } |
| 2568 | |
| 2569 | static inline void hri_sercomspi_write_CTRLA_CPHA_bit(const void *const hw, bool value) |
| 2570 | { |
| 2571 | uint32_t tmp; |
| 2572 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2573 | tmp = ((Sercom *)hw)->SPI.CTRLA.reg; |
| 2574 | tmp &= ~SERCOM_SPI_CTRLA_CPHA; |
| 2575 | tmp |= value << SERCOM_SPI_CTRLA_CPHA_Pos; |
| 2576 | ((Sercom *)hw)->SPI.CTRLA.reg = tmp; |
| 2577 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2578 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2579 | } |
| 2580 | |
| 2581 | static inline void hri_sercomspi_clear_CTRLA_CPHA_bit(const void *const hw) |
| 2582 | { |
| 2583 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2584 | ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPHA; |
| 2585 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2586 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2587 | } |
| 2588 | |
| 2589 | static inline void hri_sercomspi_toggle_CTRLA_CPHA_bit(const void *const hw) |
| 2590 | { |
| 2591 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2592 | ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPHA; |
| 2593 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2594 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2595 | } |
| 2596 | |
| 2597 | static inline void hri_sercomspi_set_CTRLA_CPOL_bit(const void *const hw) |
| 2598 | { |
| 2599 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2600 | ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPOL; |
| 2601 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2602 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2603 | } |
| 2604 | |
| 2605 | static inline bool hri_sercomspi_get_CTRLA_CPOL_bit(const void *const hw) |
| 2606 | { |
| 2607 | uint32_t tmp; |
| 2608 | tmp = ((Sercom *)hw)->SPI.CTRLA.reg; |
| 2609 | tmp = (tmp & SERCOM_SPI_CTRLA_CPOL) >> SERCOM_SPI_CTRLA_CPOL_Pos; |
| 2610 | return (bool)tmp; |
| 2611 | } |
| 2612 | |
| 2613 | static inline void hri_sercomspi_write_CTRLA_CPOL_bit(const void *const hw, bool value) |
| 2614 | { |
| 2615 | uint32_t tmp; |
| 2616 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2617 | tmp = ((Sercom *)hw)->SPI.CTRLA.reg; |
| 2618 | tmp &= ~SERCOM_SPI_CTRLA_CPOL; |
| 2619 | tmp |= value << SERCOM_SPI_CTRLA_CPOL_Pos; |
| 2620 | ((Sercom *)hw)->SPI.CTRLA.reg = tmp; |
| 2621 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2622 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2623 | } |
| 2624 | |
| 2625 | static inline void hri_sercomspi_clear_CTRLA_CPOL_bit(const void *const hw) |
| 2626 | { |
| 2627 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2628 | ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPOL; |
| 2629 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2630 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2631 | } |
| 2632 | |
| 2633 | static inline void hri_sercomspi_toggle_CTRLA_CPOL_bit(const void *const hw) |
| 2634 | { |
| 2635 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2636 | ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPOL; |
| 2637 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2638 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2639 | } |
| 2640 | |
| 2641 | static inline void hri_sercomspi_set_CTRLA_DORD_bit(const void *const hw) |
| 2642 | { |
| 2643 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2644 | ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DORD; |
| 2645 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2646 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2647 | } |
| 2648 | |
| 2649 | static inline bool hri_sercomspi_get_CTRLA_DORD_bit(const void *const hw) |
| 2650 | { |
| 2651 | uint32_t tmp; |
| 2652 | tmp = ((Sercom *)hw)->SPI.CTRLA.reg; |
| 2653 | tmp = (tmp & SERCOM_SPI_CTRLA_DORD) >> SERCOM_SPI_CTRLA_DORD_Pos; |
| 2654 | return (bool)tmp; |
| 2655 | } |
| 2656 | |
| 2657 | static inline void hri_sercomspi_write_CTRLA_DORD_bit(const void *const hw, bool value) |
| 2658 | { |
| 2659 | uint32_t tmp; |
| 2660 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2661 | tmp = ((Sercom *)hw)->SPI.CTRLA.reg; |
| 2662 | tmp &= ~SERCOM_SPI_CTRLA_DORD; |
| 2663 | tmp |= value << SERCOM_SPI_CTRLA_DORD_Pos; |
| 2664 | ((Sercom *)hw)->SPI.CTRLA.reg = tmp; |
| 2665 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2666 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2667 | } |
| 2668 | |
| 2669 | static inline void hri_sercomspi_clear_CTRLA_DORD_bit(const void *const hw) |
| 2670 | { |
| 2671 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2672 | ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DORD; |
| 2673 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2674 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2675 | } |
| 2676 | |
| 2677 | static inline void hri_sercomspi_toggle_CTRLA_DORD_bit(const void *const hw) |
| 2678 | { |
| 2679 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2680 | ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DORD; |
| 2681 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2682 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2683 | } |
| 2684 | |
| 2685 | static inline void hri_sercomspi_set_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) |
| 2686 | { |
| 2687 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2688 | ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(mask); |
| 2689 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2690 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2691 | } |
| 2692 | |
| 2693 | static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_MODE_bf(const void *const hw, |
| 2694 | hri_sercomspi_ctrla_reg_t mask) |
| 2695 | { |
| 2696 | uint32_t tmp; |
| 2697 | tmp = ((Sercom *)hw)->SPI.CTRLA.reg; |
| 2698 | tmp = (tmp & SERCOM_SPI_CTRLA_MODE(mask)) >> SERCOM_SPI_CTRLA_MODE_Pos; |
| 2699 | return tmp; |
| 2700 | } |
| 2701 | |
| 2702 | static inline void hri_sercomspi_write_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) |
| 2703 | { |
| 2704 | uint32_t tmp; |
| 2705 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2706 | tmp = ((Sercom *)hw)->SPI.CTRLA.reg; |
| 2707 | tmp &= ~SERCOM_SPI_CTRLA_MODE_Msk; |
| 2708 | tmp |= SERCOM_SPI_CTRLA_MODE(data); |
| 2709 | ((Sercom *)hw)->SPI.CTRLA.reg = tmp; |
| 2710 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2711 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2712 | } |
| 2713 | |
| 2714 | static inline void hri_sercomspi_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) |
| 2715 | { |
| 2716 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2717 | ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_MODE(mask); |
| 2718 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2719 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2720 | } |
| 2721 | |
| 2722 | static inline void hri_sercomspi_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) |
| 2723 | { |
| 2724 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2725 | ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_MODE(mask); |
| 2726 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2727 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2728 | } |
| 2729 | |
| 2730 | static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_MODE_bf(const void *const hw) |
| 2731 | { |
| 2732 | uint32_t tmp; |
| 2733 | tmp = ((Sercom *)hw)->SPI.CTRLA.reg; |
| 2734 | tmp = (tmp & SERCOM_SPI_CTRLA_MODE_Msk) >> SERCOM_SPI_CTRLA_MODE_Pos; |
| 2735 | return tmp; |
| 2736 | } |
| 2737 | |
| 2738 | static inline void hri_sercomspi_set_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) |
| 2739 | { |
| 2740 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2741 | ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DOPO(mask); |
| 2742 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2743 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2744 | } |
| 2745 | |
| 2746 | static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DOPO_bf(const void *const hw, |
| 2747 | hri_sercomspi_ctrla_reg_t mask) |
| 2748 | { |
| 2749 | uint32_t tmp; |
| 2750 | tmp = ((Sercom *)hw)->SPI.CTRLA.reg; |
| 2751 | tmp = (tmp & SERCOM_SPI_CTRLA_DOPO(mask)) >> SERCOM_SPI_CTRLA_DOPO_Pos; |
| 2752 | return tmp; |
| 2753 | } |
| 2754 | |
| 2755 | static inline void hri_sercomspi_write_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) |
| 2756 | { |
| 2757 | uint32_t tmp; |
| 2758 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2759 | tmp = ((Sercom *)hw)->SPI.CTRLA.reg; |
| 2760 | tmp &= ~SERCOM_SPI_CTRLA_DOPO_Msk; |
| 2761 | tmp |= SERCOM_SPI_CTRLA_DOPO(data); |
| 2762 | ((Sercom *)hw)->SPI.CTRLA.reg = tmp; |
| 2763 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2764 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2765 | } |
| 2766 | |
| 2767 | static inline void hri_sercomspi_clear_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) |
| 2768 | { |
| 2769 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2770 | ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DOPO(mask); |
| 2771 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2772 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2773 | } |
| 2774 | |
| 2775 | static inline void hri_sercomspi_toggle_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) |
| 2776 | { |
| 2777 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2778 | ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DOPO(mask); |
| 2779 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2780 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2781 | } |
| 2782 | |
| 2783 | static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DOPO_bf(const void *const hw) |
| 2784 | { |
| 2785 | uint32_t tmp; |
| 2786 | tmp = ((Sercom *)hw)->SPI.CTRLA.reg; |
| 2787 | tmp = (tmp & SERCOM_SPI_CTRLA_DOPO_Msk) >> SERCOM_SPI_CTRLA_DOPO_Pos; |
| 2788 | return tmp; |
| 2789 | } |
| 2790 | |
| 2791 | static inline void hri_sercomspi_set_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) |
| 2792 | { |
| 2793 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2794 | ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DIPO(mask); |
| 2795 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2796 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2797 | } |
| 2798 | |
| 2799 | static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DIPO_bf(const void *const hw, |
| 2800 | hri_sercomspi_ctrla_reg_t mask) |
| 2801 | { |
| 2802 | uint32_t tmp; |
| 2803 | tmp = ((Sercom *)hw)->SPI.CTRLA.reg; |
| 2804 | tmp = (tmp & SERCOM_SPI_CTRLA_DIPO(mask)) >> SERCOM_SPI_CTRLA_DIPO_Pos; |
| 2805 | return tmp; |
| 2806 | } |
| 2807 | |
| 2808 | static inline void hri_sercomspi_write_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) |
| 2809 | { |
| 2810 | uint32_t tmp; |
| 2811 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2812 | tmp = ((Sercom *)hw)->SPI.CTRLA.reg; |
| 2813 | tmp &= ~SERCOM_SPI_CTRLA_DIPO_Msk; |
| 2814 | tmp |= SERCOM_SPI_CTRLA_DIPO(data); |
| 2815 | ((Sercom *)hw)->SPI.CTRLA.reg = tmp; |
| 2816 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2817 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2818 | } |
| 2819 | |
| 2820 | static inline void hri_sercomspi_clear_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) |
| 2821 | { |
| 2822 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2823 | ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DIPO(mask); |
| 2824 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2825 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2826 | } |
| 2827 | |
| 2828 | static inline void hri_sercomspi_toggle_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) |
| 2829 | { |
| 2830 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2831 | ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DIPO(mask); |
| 2832 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2833 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2834 | } |
| 2835 | |
| 2836 | static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DIPO_bf(const void *const hw) |
| 2837 | { |
| 2838 | uint32_t tmp; |
| 2839 | tmp = ((Sercom *)hw)->SPI.CTRLA.reg; |
| 2840 | tmp = (tmp & SERCOM_SPI_CTRLA_DIPO_Msk) >> SERCOM_SPI_CTRLA_DIPO_Pos; |
| 2841 | return tmp; |
| 2842 | } |
| 2843 | |
| 2844 | static inline void hri_sercomspi_set_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) |
| 2845 | { |
| 2846 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2847 | ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_FORM(mask); |
| 2848 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2849 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2850 | } |
| 2851 | |
| 2852 | static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_FORM_bf(const void *const hw, |
| 2853 | hri_sercomspi_ctrla_reg_t mask) |
| 2854 | { |
| 2855 | uint32_t tmp; |
| 2856 | tmp = ((Sercom *)hw)->SPI.CTRLA.reg; |
| 2857 | tmp = (tmp & SERCOM_SPI_CTRLA_FORM(mask)) >> SERCOM_SPI_CTRLA_FORM_Pos; |
| 2858 | return tmp; |
| 2859 | } |
| 2860 | |
| 2861 | static inline void hri_sercomspi_write_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) |
| 2862 | { |
| 2863 | uint32_t tmp; |
| 2864 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2865 | tmp = ((Sercom *)hw)->SPI.CTRLA.reg; |
| 2866 | tmp &= ~SERCOM_SPI_CTRLA_FORM_Msk; |
| 2867 | tmp |= SERCOM_SPI_CTRLA_FORM(data); |
| 2868 | ((Sercom *)hw)->SPI.CTRLA.reg = tmp; |
| 2869 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2870 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2871 | } |
| 2872 | |
| 2873 | static inline void hri_sercomspi_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) |
| 2874 | { |
| 2875 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2876 | ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_FORM(mask); |
| 2877 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2878 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2879 | } |
| 2880 | |
| 2881 | static inline void hri_sercomspi_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) |
| 2882 | { |
| 2883 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2884 | ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_FORM(mask); |
| 2885 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 2886 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2887 | } |
| 2888 | |
| 2889 | static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_FORM_bf(const void *const hw) |
| 2890 | { |
| 2891 | uint32_t tmp; |
| 2892 | tmp = ((Sercom *)hw)->SPI.CTRLA.reg; |
| 2893 | tmp = (tmp & SERCOM_SPI_CTRLA_FORM_Msk) >> SERCOM_SPI_CTRLA_FORM_Pos; |
| 2894 | return tmp; |
| 2895 | } |
| 2896 | |
| 2897 | static inline void hri_sercomspi_set_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) |
| 2898 | { |
| 2899 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2900 | ((Sercom *)hw)->SPI.CTRLA.reg |= mask; |
| 2901 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); |
| 2902 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2903 | } |
| 2904 | |
| 2905 | static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_reg(const void *const hw, |
| 2906 | hri_sercomspi_ctrla_reg_t mask) |
| 2907 | { |
| 2908 | uint32_t tmp; |
| 2909 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); |
| 2910 | tmp = ((Sercom *)hw)->SPI.CTRLA.reg; |
| 2911 | tmp &= mask; |
| 2912 | return tmp; |
| 2913 | } |
| 2914 | |
| 2915 | static inline void hri_sercomspi_write_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t data) |
| 2916 | { |
| 2917 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2918 | ((Sercom *)hw)->SPI.CTRLA.reg = data; |
| 2919 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); |
| 2920 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2921 | } |
| 2922 | |
| 2923 | static inline void hri_sercomspi_clear_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) |
| 2924 | { |
| 2925 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2926 | ((Sercom *)hw)->SPI.CTRLA.reg &= ~mask; |
| 2927 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); |
| 2928 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2929 | } |
| 2930 | |
| 2931 | static inline void hri_sercomspi_toggle_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) |
| 2932 | { |
| 2933 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2934 | ((Sercom *)hw)->SPI.CTRLA.reg ^= mask; |
| 2935 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); |
| 2936 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2937 | } |
| 2938 | |
| 2939 | static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_reg(const void *const hw) |
| 2940 | { |
| 2941 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); |
| 2942 | return ((Sercom *)hw)->SPI.CTRLA.reg; |
| 2943 | } |
| 2944 | |
| 2945 | static inline void hri_sercomusart_set_CTRLA_SWRST_bit(const void *const hw) |
| 2946 | { |
| 2947 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2948 | ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SWRST; |
| 2949 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); |
| 2950 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2951 | } |
| 2952 | |
| 2953 | static inline bool hri_sercomusart_get_CTRLA_SWRST_bit(const void *const hw) |
| 2954 | { |
| 2955 | uint32_t tmp; |
| 2956 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); |
| 2957 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 2958 | tmp = (tmp & SERCOM_USART_CTRLA_SWRST) >> SERCOM_USART_CTRLA_SWRST_Pos; |
| 2959 | return (bool)tmp; |
| 2960 | } |
| 2961 | |
| 2962 | static inline void hri_sercomusart_set_CTRLA_ENABLE_bit(const void *const hw) |
| 2963 | { |
| 2964 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2965 | ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; |
| 2966 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); |
| 2967 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2968 | } |
| 2969 | |
| 2970 | static inline bool hri_sercomusart_get_CTRLA_ENABLE_bit(const void *const hw) |
| 2971 | { |
| 2972 | uint32_t tmp; |
| 2973 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); |
| 2974 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 2975 | tmp = (tmp & SERCOM_USART_CTRLA_ENABLE) >> SERCOM_USART_CTRLA_ENABLE_Pos; |
| 2976 | return (bool)tmp; |
| 2977 | } |
| 2978 | |
| 2979 | static inline void hri_sercomusart_write_CTRLA_ENABLE_bit(const void *const hw, bool value) |
| 2980 | { |
| 2981 | uint32_t tmp; |
| 2982 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2983 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 2984 | tmp &= ~SERCOM_USART_CTRLA_ENABLE; |
| 2985 | tmp |= value << SERCOM_USART_CTRLA_ENABLE_Pos; |
| 2986 | ((Sercom *)hw)->USART.CTRLA.reg = tmp; |
| 2987 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); |
| 2988 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2989 | } |
| 2990 | |
| 2991 | static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw) |
| 2992 | { |
| 2993 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 2994 | ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE; |
| 2995 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); |
| 2996 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 2997 | } |
| 2998 | |
| 2999 | static inline void hri_sercomusart_toggle_CTRLA_ENABLE_bit(const void *const hw) |
| 3000 | { |
| 3001 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3002 | ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_ENABLE; |
| 3003 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); |
| 3004 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3005 | } |
| 3006 | |
| 3007 | static inline void hri_sercomusart_set_CTRLA_RUNSTDBY_bit(const void *const hw) |
| 3008 | { |
| 3009 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3010 | ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RUNSTDBY; |
| 3011 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3012 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3013 | } |
| 3014 | |
| 3015 | static inline bool hri_sercomusart_get_CTRLA_RUNSTDBY_bit(const void *const hw) |
| 3016 | { |
| 3017 | uint32_t tmp; |
| 3018 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3019 | tmp = (tmp & SERCOM_USART_CTRLA_RUNSTDBY) >> SERCOM_USART_CTRLA_RUNSTDBY_Pos; |
| 3020 | return (bool)tmp; |
| 3021 | } |
| 3022 | |
| 3023 | static inline void hri_sercomusart_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) |
| 3024 | { |
| 3025 | uint32_t tmp; |
| 3026 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3027 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3028 | tmp &= ~SERCOM_USART_CTRLA_RUNSTDBY; |
| 3029 | tmp |= value << SERCOM_USART_CTRLA_RUNSTDBY_Pos; |
| 3030 | ((Sercom *)hw)->USART.CTRLA.reg = tmp; |
| 3031 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3032 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3033 | } |
| 3034 | |
| 3035 | static inline void hri_sercomusart_clear_CTRLA_RUNSTDBY_bit(const void *const hw) |
| 3036 | { |
| 3037 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3038 | ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RUNSTDBY; |
| 3039 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3040 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3041 | } |
| 3042 | |
| 3043 | static inline void hri_sercomusart_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) |
| 3044 | { |
| 3045 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3046 | ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RUNSTDBY; |
| 3047 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3048 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3049 | } |
| 3050 | |
| 3051 | static inline void hri_sercomusart_set_CTRLA_IBON_bit(const void *const hw) |
| 3052 | { |
| 3053 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3054 | ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_IBON; |
| 3055 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3056 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3057 | } |
| 3058 | |
| 3059 | static inline bool hri_sercomusart_get_CTRLA_IBON_bit(const void *const hw) |
| 3060 | { |
| 3061 | uint32_t tmp; |
| 3062 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3063 | tmp = (tmp & SERCOM_USART_CTRLA_IBON) >> SERCOM_USART_CTRLA_IBON_Pos; |
| 3064 | return (bool)tmp; |
| 3065 | } |
| 3066 | |
| 3067 | static inline void hri_sercomusart_write_CTRLA_IBON_bit(const void *const hw, bool value) |
| 3068 | { |
| 3069 | uint32_t tmp; |
| 3070 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3071 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3072 | tmp &= ~SERCOM_USART_CTRLA_IBON; |
| 3073 | tmp |= value << SERCOM_USART_CTRLA_IBON_Pos; |
| 3074 | ((Sercom *)hw)->USART.CTRLA.reg = tmp; |
| 3075 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3076 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3077 | } |
| 3078 | |
| 3079 | static inline void hri_sercomusart_clear_CTRLA_IBON_bit(const void *const hw) |
| 3080 | { |
| 3081 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3082 | ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_IBON; |
| 3083 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3084 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3085 | } |
| 3086 | |
| 3087 | static inline void hri_sercomusart_toggle_CTRLA_IBON_bit(const void *const hw) |
| 3088 | { |
| 3089 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3090 | ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_IBON; |
| 3091 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3092 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3093 | } |
| 3094 | |
| 3095 | static inline void hri_sercomusart_set_CTRLA_TXINV_bit(const void *const hw) |
| 3096 | { |
| 3097 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3098 | ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXINV; |
| 3099 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3100 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3101 | } |
| 3102 | |
| 3103 | static inline bool hri_sercomusart_get_CTRLA_TXINV_bit(const void *const hw) |
| 3104 | { |
| 3105 | uint32_t tmp; |
| 3106 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3107 | tmp = (tmp & SERCOM_USART_CTRLA_TXINV) >> SERCOM_USART_CTRLA_TXINV_Pos; |
| 3108 | return (bool)tmp; |
| 3109 | } |
| 3110 | |
| 3111 | static inline void hri_sercomusart_write_CTRLA_TXINV_bit(const void *const hw, bool value) |
| 3112 | { |
| 3113 | uint32_t tmp; |
| 3114 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3115 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3116 | tmp &= ~SERCOM_USART_CTRLA_TXINV; |
| 3117 | tmp |= value << SERCOM_USART_CTRLA_TXINV_Pos; |
| 3118 | ((Sercom *)hw)->USART.CTRLA.reg = tmp; |
| 3119 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3120 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3121 | } |
| 3122 | |
| 3123 | static inline void hri_sercomusart_clear_CTRLA_TXINV_bit(const void *const hw) |
| 3124 | { |
| 3125 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3126 | ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXINV; |
| 3127 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3128 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3129 | } |
| 3130 | |
| 3131 | static inline void hri_sercomusart_toggle_CTRLA_TXINV_bit(const void *const hw) |
| 3132 | { |
| 3133 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3134 | ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXINV; |
| 3135 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3136 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3137 | } |
| 3138 | |
| 3139 | static inline void hri_sercomusart_set_CTRLA_RXINV_bit(const void *const hw) |
| 3140 | { |
| 3141 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3142 | ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXINV; |
| 3143 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3144 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3145 | } |
| 3146 | |
| 3147 | static inline bool hri_sercomusart_get_CTRLA_RXINV_bit(const void *const hw) |
| 3148 | { |
| 3149 | uint32_t tmp; |
| 3150 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3151 | tmp = (tmp & SERCOM_USART_CTRLA_RXINV) >> SERCOM_USART_CTRLA_RXINV_Pos; |
| 3152 | return (bool)tmp; |
| 3153 | } |
| 3154 | |
| 3155 | static inline void hri_sercomusart_write_CTRLA_RXINV_bit(const void *const hw, bool value) |
| 3156 | { |
| 3157 | uint32_t tmp; |
| 3158 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3159 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3160 | tmp &= ~SERCOM_USART_CTRLA_RXINV; |
| 3161 | tmp |= value << SERCOM_USART_CTRLA_RXINV_Pos; |
| 3162 | ((Sercom *)hw)->USART.CTRLA.reg = tmp; |
| 3163 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3164 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3165 | } |
| 3166 | |
| 3167 | static inline void hri_sercomusart_clear_CTRLA_RXINV_bit(const void *const hw) |
| 3168 | { |
| 3169 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3170 | ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXINV; |
| 3171 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3172 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3173 | } |
| 3174 | |
| 3175 | static inline void hri_sercomusart_toggle_CTRLA_RXINV_bit(const void *const hw) |
| 3176 | { |
| 3177 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3178 | ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXINV; |
| 3179 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3180 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3181 | } |
| 3182 | |
| 3183 | static inline void hri_sercomusart_set_CTRLA_CMODE_bit(const void *const hw) |
| 3184 | { |
| 3185 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3186 | ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CMODE; |
| 3187 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3188 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3189 | } |
| 3190 | |
| 3191 | static inline bool hri_sercomusart_get_CTRLA_CMODE_bit(const void *const hw) |
| 3192 | { |
| 3193 | uint32_t tmp; |
| 3194 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3195 | tmp = (tmp & SERCOM_USART_CTRLA_CMODE) >> SERCOM_USART_CTRLA_CMODE_Pos; |
| 3196 | return (bool)tmp; |
| 3197 | } |
| 3198 | |
| 3199 | static inline void hri_sercomusart_write_CTRLA_CMODE_bit(const void *const hw, bool value) |
| 3200 | { |
| 3201 | uint32_t tmp; |
| 3202 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3203 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3204 | tmp &= ~SERCOM_USART_CTRLA_CMODE; |
| 3205 | tmp |= value << SERCOM_USART_CTRLA_CMODE_Pos; |
| 3206 | ((Sercom *)hw)->USART.CTRLA.reg = tmp; |
| 3207 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3208 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3209 | } |
| 3210 | |
| 3211 | static inline void hri_sercomusart_clear_CTRLA_CMODE_bit(const void *const hw) |
| 3212 | { |
| 3213 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3214 | ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CMODE; |
| 3215 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3216 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3217 | } |
| 3218 | |
| 3219 | static inline void hri_sercomusart_toggle_CTRLA_CMODE_bit(const void *const hw) |
| 3220 | { |
| 3221 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3222 | ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CMODE; |
| 3223 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3224 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3225 | } |
| 3226 | |
| 3227 | static inline void hri_sercomusart_set_CTRLA_CPOL_bit(const void *const hw) |
| 3228 | { |
| 3229 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3230 | ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CPOL; |
| 3231 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3232 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3233 | } |
| 3234 | |
| 3235 | static inline bool hri_sercomusart_get_CTRLA_CPOL_bit(const void *const hw) |
| 3236 | { |
| 3237 | uint32_t tmp; |
| 3238 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3239 | tmp = (tmp & SERCOM_USART_CTRLA_CPOL) >> SERCOM_USART_CTRLA_CPOL_Pos; |
| 3240 | return (bool)tmp; |
| 3241 | } |
| 3242 | |
| 3243 | static inline void hri_sercomusart_write_CTRLA_CPOL_bit(const void *const hw, bool value) |
| 3244 | { |
| 3245 | uint32_t tmp; |
| 3246 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3247 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3248 | tmp &= ~SERCOM_USART_CTRLA_CPOL; |
| 3249 | tmp |= value << SERCOM_USART_CTRLA_CPOL_Pos; |
| 3250 | ((Sercom *)hw)->USART.CTRLA.reg = tmp; |
| 3251 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3252 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3253 | } |
| 3254 | |
| 3255 | static inline void hri_sercomusart_clear_CTRLA_CPOL_bit(const void *const hw) |
| 3256 | { |
| 3257 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3258 | ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CPOL; |
| 3259 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3260 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3261 | } |
| 3262 | |
| 3263 | static inline void hri_sercomusart_toggle_CTRLA_CPOL_bit(const void *const hw) |
| 3264 | { |
| 3265 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3266 | ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CPOL; |
| 3267 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3268 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3269 | } |
| 3270 | |
| 3271 | static inline void hri_sercomusart_set_CTRLA_DORD_bit(const void *const hw) |
| 3272 | { |
| 3273 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3274 | ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_DORD; |
| 3275 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3276 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3277 | } |
| 3278 | |
| 3279 | static inline bool hri_sercomusart_get_CTRLA_DORD_bit(const void *const hw) |
| 3280 | { |
| 3281 | uint32_t tmp; |
| 3282 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3283 | tmp = (tmp & SERCOM_USART_CTRLA_DORD) >> SERCOM_USART_CTRLA_DORD_Pos; |
| 3284 | return (bool)tmp; |
| 3285 | } |
| 3286 | |
| 3287 | static inline void hri_sercomusart_write_CTRLA_DORD_bit(const void *const hw, bool value) |
| 3288 | { |
| 3289 | uint32_t tmp; |
| 3290 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3291 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3292 | tmp &= ~SERCOM_USART_CTRLA_DORD; |
| 3293 | tmp |= value << SERCOM_USART_CTRLA_DORD_Pos; |
| 3294 | ((Sercom *)hw)->USART.CTRLA.reg = tmp; |
| 3295 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3296 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3297 | } |
| 3298 | |
| 3299 | static inline void hri_sercomusart_clear_CTRLA_DORD_bit(const void *const hw) |
| 3300 | { |
| 3301 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3302 | ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_DORD; |
| 3303 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3304 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3305 | } |
| 3306 | |
| 3307 | static inline void hri_sercomusart_toggle_CTRLA_DORD_bit(const void *const hw) |
| 3308 | { |
| 3309 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3310 | ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_DORD; |
| 3311 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3312 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3313 | } |
| 3314 | |
| 3315 | static inline void hri_sercomusart_set_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) |
| 3316 | { |
| 3317 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3318 | ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_MODE(mask); |
| 3319 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3320 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3321 | } |
| 3322 | |
| 3323 | static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_MODE_bf(const void *const hw, |
| 3324 | hri_sercomusart_ctrla_reg_t mask) |
| 3325 | { |
| 3326 | uint32_t tmp; |
| 3327 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3328 | tmp = (tmp & SERCOM_USART_CTRLA_MODE(mask)) >> SERCOM_USART_CTRLA_MODE_Pos; |
| 3329 | return tmp; |
| 3330 | } |
| 3331 | |
| 3332 | static inline void hri_sercomusart_write_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) |
| 3333 | { |
| 3334 | uint32_t tmp; |
| 3335 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3336 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3337 | tmp &= ~SERCOM_USART_CTRLA_MODE_Msk; |
| 3338 | tmp |= SERCOM_USART_CTRLA_MODE(data); |
| 3339 | ((Sercom *)hw)->USART.CTRLA.reg = tmp; |
| 3340 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3341 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3342 | } |
| 3343 | |
| 3344 | static inline void hri_sercomusart_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) |
| 3345 | { |
| 3346 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3347 | ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_MODE(mask); |
| 3348 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3349 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3350 | } |
| 3351 | |
| 3352 | static inline void hri_sercomusart_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) |
| 3353 | { |
| 3354 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3355 | ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_MODE(mask); |
| 3356 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3357 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3358 | } |
| 3359 | |
| 3360 | static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_MODE_bf(const void *const hw) |
| 3361 | { |
| 3362 | uint32_t tmp; |
| 3363 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3364 | tmp = (tmp & SERCOM_USART_CTRLA_MODE_Msk) >> SERCOM_USART_CTRLA_MODE_Pos; |
| 3365 | return tmp; |
| 3366 | } |
| 3367 | |
| 3368 | static inline void hri_sercomusart_set_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) |
| 3369 | { |
| 3370 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3371 | ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPR(mask); |
| 3372 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3373 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3374 | } |
| 3375 | |
| 3376 | static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPR_bf(const void *const hw, |
| 3377 | hri_sercomusart_ctrla_reg_t mask) |
| 3378 | { |
| 3379 | uint32_t tmp; |
| 3380 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3381 | tmp = (tmp & SERCOM_USART_CTRLA_SAMPR(mask)) >> SERCOM_USART_CTRLA_SAMPR_Pos; |
| 3382 | return tmp; |
| 3383 | } |
| 3384 | |
| 3385 | static inline void hri_sercomusart_write_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) |
| 3386 | { |
| 3387 | uint32_t tmp; |
| 3388 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3389 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3390 | tmp &= ~SERCOM_USART_CTRLA_SAMPR_Msk; |
| 3391 | tmp |= SERCOM_USART_CTRLA_SAMPR(data); |
| 3392 | ((Sercom *)hw)->USART.CTRLA.reg = tmp; |
| 3393 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3394 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3395 | } |
| 3396 | |
| 3397 | static inline void hri_sercomusart_clear_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) |
| 3398 | { |
| 3399 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3400 | ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPR(mask); |
| 3401 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3402 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3403 | } |
| 3404 | |
| 3405 | static inline void hri_sercomusart_toggle_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) |
| 3406 | { |
| 3407 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3408 | ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPR(mask); |
| 3409 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3410 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3411 | } |
| 3412 | |
| 3413 | static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPR_bf(const void *const hw) |
| 3414 | { |
| 3415 | uint32_t tmp; |
| 3416 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3417 | tmp = (tmp & SERCOM_USART_CTRLA_SAMPR_Msk) >> SERCOM_USART_CTRLA_SAMPR_Pos; |
| 3418 | return tmp; |
| 3419 | } |
| 3420 | |
| 3421 | static inline void hri_sercomusart_set_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) |
| 3422 | { |
| 3423 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3424 | ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(mask); |
| 3425 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3426 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3427 | } |
| 3428 | |
| 3429 | static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_TXPO_bf(const void *const hw, |
| 3430 | hri_sercomusart_ctrla_reg_t mask) |
| 3431 | { |
| 3432 | uint32_t tmp; |
| 3433 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3434 | tmp = (tmp & SERCOM_USART_CTRLA_TXPO(mask)) >> SERCOM_USART_CTRLA_TXPO_Pos; |
| 3435 | return tmp; |
| 3436 | } |
| 3437 | |
| 3438 | static inline void hri_sercomusart_write_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) |
| 3439 | { |
| 3440 | uint32_t tmp; |
| 3441 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3442 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3443 | tmp &= ~SERCOM_USART_CTRLA_TXPO_Msk; |
| 3444 | tmp |= SERCOM_USART_CTRLA_TXPO(data); |
| 3445 | ((Sercom *)hw)->USART.CTRLA.reg = tmp; |
| 3446 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3447 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3448 | } |
| 3449 | |
| 3450 | static inline void hri_sercomusart_clear_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) |
| 3451 | { |
| 3452 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3453 | ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXPO(mask); |
| 3454 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3455 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3456 | } |
| 3457 | |
| 3458 | static inline void hri_sercomusart_toggle_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) |
| 3459 | { |
| 3460 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3461 | ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXPO(mask); |
| 3462 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3463 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3464 | } |
| 3465 | |
| 3466 | static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_TXPO_bf(const void *const hw) |
| 3467 | { |
| 3468 | uint32_t tmp; |
| 3469 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3470 | tmp = (tmp & SERCOM_USART_CTRLA_TXPO_Msk) >> SERCOM_USART_CTRLA_TXPO_Pos; |
| 3471 | return tmp; |
| 3472 | } |
| 3473 | |
| 3474 | static inline void hri_sercomusart_set_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) |
| 3475 | { |
| 3476 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3477 | ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXPO(mask); |
| 3478 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3479 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3480 | } |
| 3481 | |
| 3482 | static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_RXPO_bf(const void *const hw, |
| 3483 | hri_sercomusart_ctrla_reg_t mask) |
| 3484 | { |
| 3485 | uint32_t tmp; |
| 3486 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3487 | tmp = (tmp & SERCOM_USART_CTRLA_RXPO(mask)) >> SERCOM_USART_CTRLA_RXPO_Pos; |
| 3488 | return tmp; |
| 3489 | } |
| 3490 | |
| 3491 | static inline void hri_sercomusart_write_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) |
| 3492 | { |
| 3493 | uint32_t tmp; |
| 3494 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3495 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3496 | tmp &= ~SERCOM_USART_CTRLA_RXPO_Msk; |
| 3497 | tmp |= SERCOM_USART_CTRLA_RXPO(data); |
| 3498 | ((Sercom *)hw)->USART.CTRLA.reg = tmp; |
| 3499 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3500 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3501 | } |
| 3502 | |
| 3503 | static inline void hri_sercomusart_clear_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) |
| 3504 | { |
| 3505 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3506 | ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXPO(mask); |
| 3507 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3508 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3509 | } |
| 3510 | |
| 3511 | static inline void hri_sercomusart_toggle_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) |
| 3512 | { |
| 3513 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3514 | ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXPO(mask); |
| 3515 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3516 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3517 | } |
| 3518 | |
| 3519 | static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_RXPO_bf(const void *const hw) |
| 3520 | { |
| 3521 | uint32_t tmp; |
| 3522 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3523 | tmp = (tmp & SERCOM_USART_CTRLA_RXPO_Msk) >> SERCOM_USART_CTRLA_RXPO_Pos; |
| 3524 | return tmp; |
| 3525 | } |
| 3526 | |
| 3527 | static inline void hri_sercomusart_set_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) |
| 3528 | { |
| 3529 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3530 | ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPA(mask); |
| 3531 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3532 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3533 | } |
| 3534 | |
| 3535 | static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPA_bf(const void *const hw, |
| 3536 | hri_sercomusart_ctrla_reg_t mask) |
| 3537 | { |
| 3538 | uint32_t tmp; |
| 3539 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3540 | tmp = (tmp & SERCOM_USART_CTRLA_SAMPA(mask)) >> SERCOM_USART_CTRLA_SAMPA_Pos; |
| 3541 | return tmp; |
| 3542 | } |
| 3543 | |
| 3544 | static inline void hri_sercomusart_write_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) |
| 3545 | { |
| 3546 | uint32_t tmp; |
| 3547 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3548 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3549 | tmp &= ~SERCOM_USART_CTRLA_SAMPA_Msk; |
| 3550 | tmp |= SERCOM_USART_CTRLA_SAMPA(data); |
| 3551 | ((Sercom *)hw)->USART.CTRLA.reg = tmp; |
| 3552 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3553 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3554 | } |
| 3555 | |
| 3556 | static inline void hri_sercomusart_clear_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) |
| 3557 | { |
| 3558 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3559 | ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPA(mask); |
| 3560 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3561 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3562 | } |
| 3563 | |
| 3564 | static inline void hri_sercomusart_toggle_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) |
| 3565 | { |
| 3566 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3567 | ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPA(mask); |
| 3568 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3569 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3570 | } |
| 3571 | |
| 3572 | static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPA_bf(const void *const hw) |
| 3573 | { |
| 3574 | uint32_t tmp; |
| 3575 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3576 | tmp = (tmp & SERCOM_USART_CTRLA_SAMPA_Msk) >> SERCOM_USART_CTRLA_SAMPA_Pos; |
| 3577 | return tmp; |
| 3578 | } |
| 3579 | |
| 3580 | static inline void hri_sercomusart_set_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) |
| 3581 | { |
| 3582 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3583 | ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM(mask); |
| 3584 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3585 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3586 | } |
| 3587 | |
| 3588 | static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_FORM_bf(const void *const hw, |
| 3589 | hri_sercomusart_ctrla_reg_t mask) |
| 3590 | { |
| 3591 | uint32_t tmp; |
| 3592 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3593 | tmp = (tmp & SERCOM_USART_CTRLA_FORM(mask)) >> SERCOM_USART_CTRLA_FORM_Pos; |
| 3594 | return tmp; |
| 3595 | } |
| 3596 | |
| 3597 | static inline void hri_sercomusart_write_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) |
| 3598 | { |
| 3599 | uint32_t tmp; |
| 3600 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3601 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3602 | tmp &= ~SERCOM_USART_CTRLA_FORM_Msk; |
| 3603 | tmp |= SERCOM_USART_CTRLA_FORM(data); |
| 3604 | ((Sercom *)hw)->USART.CTRLA.reg = tmp; |
| 3605 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3606 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3607 | } |
| 3608 | |
| 3609 | static inline void hri_sercomusart_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) |
| 3610 | { |
| 3611 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3612 | ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_FORM(mask); |
| 3613 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3614 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3615 | } |
| 3616 | |
| 3617 | static inline void hri_sercomusart_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) |
| 3618 | { |
| 3619 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3620 | ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_FORM(mask); |
| 3621 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 3622 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3623 | } |
| 3624 | |
| 3625 | static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_FORM_bf(const void *const hw) |
| 3626 | { |
| 3627 | uint32_t tmp; |
| 3628 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3629 | tmp = (tmp & SERCOM_USART_CTRLA_FORM_Msk) >> SERCOM_USART_CTRLA_FORM_Pos; |
| 3630 | return tmp; |
| 3631 | } |
| 3632 | |
| 3633 | static inline void hri_sercomusart_set_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) |
| 3634 | { |
| 3635 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3636 | ((Sercom *)hw)->USART.CTRLA.reg |= mask; |
| 3637 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); |
| 3638 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3639 | } |
| 3640 | |
| 3641 | static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const hw, |
| 3642 | hri_sercomusart_ctrla_reg_t mask) |
| 3643 | { |
| 3644 | uint32_t tmp; |
| 3645 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); |
| 3646 | tmp = ((Sercom *)hw)->USART.CTRLA.reg; |
| 3647 | tmp &= mask; |
| 3648 | return tmp; |
| 3649 | } |
| 3650 | |
| 3651 | static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data) |
| 3652 | { |
| 3653 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3654 | ((Sercom *)hw)->USART.CTRLA.reg = data; |
| 3655 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); |
| 3656 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3657 | } |
| 3658 | |
| 3659 | static inline void hri_sercomusart_clear_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) |
| 3660 | { |
| 3661 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3662 | ((Sercom *)hw)->USART.CTRLA.reg &= ~mask; |
| 3663 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); |
| 3664 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3665 | } |
| 3666 | |
| 3667 | static inline void hri_sercomusart_toggle_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) |
| 3668 | { |
| 3669 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3670 | ((Sercom *)hw)->USART.CTRLA.reg ^= mask; |
| 3671 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); |
| 3672 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3673 | } |
| 3674 | |
| 3675 | static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_reg(const void *const hw) |
| 3676 | { |
| 3677 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); |
| 3678 | return ((Sercom *)hw)->USART.CTRLA.reg; |
| 3679 | } |
| 3680 | |
| 3681 | static inline void hri_sercomi2cm_set_CTRLB_SMEN_bit(const void *const hw) |
| 3682 | { |
| 3683 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3684 | ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_SMEN; |
Kévin Redon | a6c44f1 | 2019-06-06 16:41:21 +0200 | [diff] [blame] | 3685 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 3686 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3687 | } |
| 3688 | |
| 3689 | static inline bool hri_sercomi2cm_get_CTRLB_SMEN_bit(const void *const hw) |
| 3690 | { |
| 3691 | uint32_t tmp; |
| 3692 | tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; |
| 3693 | tmp = (tmp & SERCOM_I2CM_CTRLB_SMEN) >> SERCOM_I2CM_CTRLB_SMEN_Pos; |
| 3694 | return (bool)tmp; |
| 3695 | } |
| 3696 | |
| 3697 | static inline void hri_sercomi2cm_write_CTRLB_SMEN_bit(const void *const hw, bool value) |
| 3698 | { |
| 3699 | uint32_t tmp; |
| 3700 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3701 | tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; |
| 3702 | tmp &= ~SERCOM_I2CM_CTRLB_SMEN; |
| 3703 | tmp |= value << SERCOM_I2CM_CTRLB_SMEN_Pos; |
| 3704 | ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; |
Kévin Redon | a6c44f1 | 2019-06-06 16:41:21 +0200 | [diff] [blame] | 3705 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 3706 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3707 | } |
| 3708 | |
| 3709 | static inline void hri_sercomi2cm_clear_CTRLB_SMEN_bit(const void *const hw) |
| 3710 | { |
| 3711 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3712 | ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN; |
Kévin Redon | a6c44f1 | 2019-06-06 16:41:21 +0200 | [diff] [blame] | 3713 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 3714 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3715 | } |
| 3716 | |
| 3717 | static inline void hri_sercomi2cm_toggle_CTRLB_SMEN_bit(const void *const hw) |
| 3718 | { |
| 3719 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3720 | ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_SMEN; |
Kévin Redon | a6c44f1 | 2019-06-06 16:41:21 +0200 | [diff] [blame] | 3721 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 3722 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3723 | } |
| 3724 | |
| 3725 | static inline void hri_sercomi2cm_set_CTRLB_QCEN_bit(const void *const hw) |
| 3726 | { |
| 3727 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3728 | ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_QCEN; |
Kévin Redon | a6c44f1 | 2019-06-06 16:41:21 +0200 | [diff] [blame] | 3729 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 3730 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3731 | } |
| 3732 | |
| 3733 | static inline bool hri_sercomi2cm_get_CTRLB_QCEN_bit(const void *const hw) |
| 3734 | { |
| 3735 | uint32_t tmp; |
| 3736 | tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; |
| 3737 | tmp = (tmp & SERCOM_I2CM_CTRLB_QCEN) >> SERCOM_I2CM_CTRLB_QCEN_Pos; |
| 3738 | return (bool)tmp; |
| 3739 | } |
| 3740 | |
| 3741 | static inline void hri_sercomi2cm_write_CTRLB_QCEN_bit(const void *const hw, bool value) |
| 3742 | { |
| 3743 | uint32_t tmp; |
| 3744 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3745 | tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; |
| 3746 | tmp &= ~SERCOM_I2CM_CTRLB_QCEN; |
| 3747 | tmp |= value << SERCOM_I2CM_CTRLB_QCEN_Pos; |
| 3748 | ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; |
Kévin Redon | a6c44f1 | 2019-06-06 16:41:21 +0200 | [diff] [blame] | 3749 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 3750 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3751 | } |
| 3752 | |
| 3753 | static inline void hri_sercomi2cm_clear_CTRLB_QCEN_bit(const void *const hw) |
| 3754 | { |
| 3755 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3756 | ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_QCEN; |
Kévin Redon | a6c44f1 | 2019-06-06 16:41:21 +0200 | [diff] [blame] | 3757 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 3758 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3759 | } |
| 3760 | |
| 3761 | static inline void hri_sercomi2cm_toggle_CTRLB_QCEN_bit(const void *const hw) |
| 3762 | { |
| 3763 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3764 | ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_QCEN; |
Kévin Redon | a6c44f1 | 2019-06-06 16:41:21 +0200 | [diff] [blame] | 3765 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 3766 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3767 | } |
| 3768 | |
| 3769 | static inline void hri_sercomi2cm_set_CTRLB_ACKACT_bit(const void *const hw) |
| 3770 | { |
| 3771 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3772 | ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; |
Kévin Redon | a6c44f1 | 2019-06-06 16:41:21 +0200 | [diff] [blame] | 3773 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 3774 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3775 | } |
| 3776 | |
| 3777 | static inline bool hri_sercomi2cm_get_CTRLB_ACKACT_bit(const void *const hw) |
| 3778 | { |
| 3779 | uint32_t tmp; |
| 3780 | tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; |
| 3781 | tmp = (tmp & SERCOM_I2CM_CTRLB_ACKACT) >> SERCOM_I2CM_CTRLB_ACKACT_Pos; |
| 3782 | return (bool)tmp; |
| 3783 | } |
| 3784 | |
| 3785 | static inline void hri_sercomi2cm_write_CTRLB_ACKACT_bit(const void *const hw, bool value) |
| 3786 | { |
| 3787 | uint32_t tmp; |
| 3788 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3789 | tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; |
| 3790 | tmp &= ~SERCOM_I2CM_CTRLB_ACKACT; |
| 3791 | tmp |= value << SERCOM_I2CM_CTRLB_ACKACT_Pos; |
| 3792 | ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; |
Kévin Redon | a6c44f1 | 2019-06-06 16:41:21 +0200 | [diff] [blame] | 3793 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 3794 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3795 | } |
| 3796 | |
| 3797 | static inline void hri_sercomi2cm_clear_CTRLB_ACKACT_bit(const void *const hw) |
| 3798 | { |
| 3799 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3800 | ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; |
Kévin Redon | a6c44f1 | 2019-06-06 16:41:21 +0200 | [diff] [blame] | 3801 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 3802 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3803 | } |
| 3804 | |
| 3805 | static inline void hri_sercomi2cm_toggle_CTRLB_ACKACT_bit(const void *const hw) |
| 3806 | { |
| 3807 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3808 | ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_ACKACT; |
Kévin Redon | a6c44f1 | 2019-06-06 16:41:21 +0200 | [diff] [blame] | 3809 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 3810 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3811 | } |
| 3812 | |
| 3813 | static inline void hri_sercomi2cm_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) |
| 3814 | { |
| 3815 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3816 | ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask); |
| 3817 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 3818 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3819 | } |
| 3820 | |
| 3821 | static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_CMD_bf(const void *const hw, |
| 3822 | hri_sercomi2cm_ctrlb_reg_t mask) |
| 3823 | { |
| 3824 | uint32_t tmp; |
| 3825 | tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; |
| 3826 | tmp = (tmp & SERCOM_I2CM_CTRLB_CMD(mask)) >> SERCOM_I2CM_CTRLB_CMD_Pos; |
| 3827 | return tmp; |
| 3828 | } |
| 3829 | |
| 3830 | static inline void hri_sercomi2cm_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) |
| 3831 | { |
| 3832 | uint32_t tmp; |
| 3833 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3834 | tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; |
| 3835 | tmp &= ~SERCOM_I2CM_CTRLB_CMD_Msk; |
| 3836 | tmp |= SERCOM_I2CM_CTRLB_CMD(data); |
| 3837 | ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; |
| 3838 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 3839 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3840 | } |
| 3841 | |
| 3842 | static inline void hri_sercomi2cm_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) |
| 3843 | { |
| 3844 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3845 | ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_CMD(mask); |
| 3846 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 3847 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3848 | } |
| 3849 | |
| 3850 | static inline void hri_sercomi2cm_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) |
| 3851 | { |
| 3852 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3853 | ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_CMD(mask); |
| 3854 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 3855 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3856 | } |
| 3857 | |
| 3858 | static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_CMD_bf(const void *const hw) |
| 3859 | { |
| 3860 | uint32_t tmp; |
| 3861 | tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; |
| 3862 | tmp = (tmp & SERCOM_I2CM_CTRLB_CMD_Msk) >> SERCOM_I2CM_CTRLB_CMD_Pos; |
| 3863 | return tmp; |
| 3864 | } |
| 3865 | |
| 3866 | static inline void hri_sercomi2cm_set_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) |
| 3867 | { |
| 3868 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3869 | ((Sercom *)hw)->I2CM.CTRLB.reg |= mask; |
Kévin Redon | a6c44f1 | 2019-06-06 16:41:21 +0200 | [diff] [blame] | 3870 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 3871 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3872 | } |
| 3873 | |
| 3874 | static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_reg(const void *const hw, |
| 3875 | hri_sercomi2cm_ctrlb_reg_t mask) |
| 3876 | { |
| 3877 | uint32_t tmp; |
Kévin Redon | a6c44f1 | 2019-06-06 16:41:21 +0200 | [diff] [blame] | 3878 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 3879 | tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; |
| 3880 | tmp &= mask; |
| 3881 | return tmp; |
| 3882 | } |
| 3883 | |
| 3884 | static inline void hri_sercomi2cm_write_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) |
| 3885 | { |
| 3886 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3887 | ((Sercom *)hw)->I2CM.CTRLB.reg = data; |
Kévin Redon | a6c44f1 | 2019-06-06 16:41:21 +0200 | [diff] [blame] | 3888 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 3889 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3890 | } |
| 3891 | |
| 3892 | static inline void hri_sercomi2cm_clear_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) |
| 3893 | { |
| 3894 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3895 | ((Sercom *)hw)->I2CM.CTRLB.reg &= ~mask; |
Kévin Redon | a6c44f1 | 2019-06-06 16:41:21 +0200 | [diff] [blame] | 3896 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 3897 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3898 | } |
| 3899 | |
| 3900 | static inline void hri_sercomi2cm_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) |
| 3901 | { |
| 3902 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3903 | ((Sercom *)hw)->I2CM.CTRLB.reg ^= mask; |
Kévin Redon | a6c44f1 | 2019-06-06 16:41:21 +0200 | [diff] [blame] | 3904 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 3905 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3906 | } |
| 3907 | |
| 3908 | static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_reg(const void *const hw) |
| 3909 | { |
Kévin Redon | a6c44f1 | 2019-06-06 16:41:21 +0200 | [diff] [blame] | 3910 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 3911 | return ((Sercom *)hw)->I2CM.CTRLB.reg; |
| 3912 | } |
| 3913 | |
| 3914 | static inline void hri_sercomi2cs_set_CTRLB_SMEN_bit(const void *const hw) |
| 3915 | { |
| 3916 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3917 | ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_SMEN; |
| 3918 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3919 | } |
| 3920 | |
| 3921 | static inline bool hri_sercomi2cs_get_CTRLB_SMEN_bit(const void *const hw) |
| 3922 | { |
| 3923 | uint32_t tmp; |
| 3924 | tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; |
| 3925 | tmp = (tmp & SERCOM_I2CS_CTRLB_SMEN) >> SERCOM_I2CS_CTRLB_SMEN_Pos; |
| 3926 | return (bool)tmp; |
| 3927 | } |
| 3928 | |
| 3929 | static inline void hri_sercomi2cs_write_CTRLB_SMEN_bit(const void *const hw, bool value) |
| 3930 | { |
| 3931 | uint32_t tmp; |
| 3932 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3933 | tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; |
| 3934 | tmp &= ~SERCOM_I2CS_CTRLB_SMEN; |
| 3935 | tmp |= value << SERCOM_I2CS_CTRLB_SMEN_Pos; |
| 3936 | ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; |
| 3937 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3938 | } |
| 3939 | |
| 3940 | static inline void hri_sercomi2cs_clear_CTRLB_SMEN_bit(const void *const hw) |
| 3941 | { |
| 3942 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3943 | ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_SMEN; |
| 3944 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3945 | } |
| 3946 | |
| 3947 | static inline void hri_sercomi2cs_toggle_CTRLB_SMEN_bit(const void *const hw) |
| 3948 | { |
| 3949 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3950 | ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_SMEN; |
| 3951 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3952 | } |
| 3953 | |
| 3954 | static inline void hri_sercomi2cs_set_CTRLB_GCMD_bit(const void *const hw) |
| 3955 | { |
| 3956 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3957 | ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_GCMD; |
| 3958 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3959 | } |
| 3960 | |
| 3961 | static inline bool hri_sercomi2cs_get_CTRLB_GCMD_bit(const void *const hw) |
| 3962 | { |
| 3963 | uint32_t tmp; |
| 3964 | tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; |
| 3965 | tmp = (tmp & SERCOM_I2CS_CTRLB_GCMD) >> SERCOM_I2CS_CTRLB_GCMD_Pos; |
| 3966 | return (bool)tmp; |
| 3967 | } |
| 3968 | |
| 3969 | static inline void hri_sercomi2cs_write_CTRLB_GCMD_bit(const void *const hw, bool value) |
| 3970 | { |
| 3971 | uint32_t tmp; |
| 3972 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3973 | tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; |
| 3974 | tmp &= ~SERCOM_I2CS_CTRLB_GCMD; |
| 3975 | tmp |= value << SERCOM_I2CS_CTRLB_GCMD_Pos; |
| 3976 | ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; |
| 3977 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3978 | } |
| 3979 | |
| 3980 | static inline void hri_sercomi2cs_clear_CTRLB_GCMD_bit(const void *const hw) |
| 3981 | { |
| 3982 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3983 | ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_GCMD; |
| 3984 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3985 | } |
| 3986 | |
| 3987 | static inline void hri_sercomi2cs_toggle_CTRLB_GCMD_bit(const void *const hw) |
| 3988 | { |
| 3989 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3990 | ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_GCMD; |
| 3991 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3992 | } |
| 3993 | |
| 3994 | static inline void hri_sercomi2cs_set_CTRLB_AACKEN_bit(const void *const hw) |
| 3995 | { |
| 3996 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 3997 | ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AACKEN; |
| 3998 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 3999 | } |
| 4000 | |
| 4001 | static inline bool hri_sercomi2cs_get_CTRLB_AACKEN_bit(const void *const hw) |
| 4002 | { |
| 4003 | uint32_t tmp; |
| 4004 | tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; |
| 4005 | tmp = (tmp & SERCOM_I2CS_CTRLB_AACKEN) >> SERCOM_I2CS_CTRLB_AACKEN_Pos; |
| 4006 | return (bool)tmp; |
| 4007 | } |
| 4008 | |
| 4009 | static inline void hri_sercomi2cs_write_CTRLB_AACKEN_bit(const void *const hw, bool value) |
| 4010 | { |
| 4011 | uint32_t tmp; |
| 4012 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4013 | tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; |
| 4014 | tmp &= ~SERCOM_I2CS_CTRLB_AACKEN; |
| 4015 | tmp |= value << SERCOM_I2CS_CTRLB_AACKEN_Pos; |
| 4016 | ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; |
| 4017 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4018 | } |
| 4019 | |
| 4020 | static inline void hri_sercomi2cs_clear_CTRLB_AACKEN_bit(const void *const hw) |
| 4021 | { |
| 4022 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4023 | ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AACKEN; |
| 4024 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4025 | } |
| 4026 | |
| 4027 | static inline void hri_sercomi2cs_toggle_CTRLB_AACKEN_bit(const void *const hw) |
| 4028 | { |
| 4029 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4030 | ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AACKEN; |
| 4031 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4032 | } |
| 4033 | |
| 4034 | static inline void hri_sercomi2cs_set_CTRLB_ACKACT_bit(const void *const hw) |
| 4035 | { |
| 4036 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4037 | ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; |
| 4038 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4039 | } |
| 4040 | |
| 4041 | static inline bool hri_sercomi2cs_get_CTRLB_ACKACT_bit(const void *const hw) |
| 4042 | { |
| 4043 | uint32_t tmp; |
| 4044 | tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; |
| 4045 | tmp = (tmp & SERCOM_I2CS_CTRLB_ACKACT) >> SERCOM_I2CS_CTRLB_ACKACT_Pos; |
| 4046 | return (bool)tmp; |
| 4047 | } |
| 4048 | |
| 4049 | static inline void hri_sercomi2cs_write_CTRLB_ACKACT_bit(const void *const hw, bool value) |
| 4050 | { |
| 4051 | uint32_t tmp; |
| 4052 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4053 | tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; |
| 4054 | tmp &= ~SERCOM_I2CS_CTRLB_ACKACT; |
| 4055 | tmp |= value << SERCOM_I2CS_CTRLB_ACKACT_Pos; |
| 4056 | ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; |
| 4057 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4058 | } |
| 4059 | |
| 4060 | static inline void hri_sercomi2cs_clear_CTRLB_ACKACT_bit(const void *const hw) |
| 4061 | { |
| 4062 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4063 | ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; |
| 4064 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4065 | } |
| 4066 | |
| 4067 | static inline void hri_sercomi2cs_toggle_CTRLB_ACKACT_bit(const void *const hw) |
| 4068 | { |
| 4069 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4070 | ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_ACKACT; |
| 4071 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4072 | } |
| 4073 | |
| 4074 | static inline void hri_sercomi2cs_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) |
| 4075 | { |
| 4076 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4077 | ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AMODE(mask); |
| 4078 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4079 | } |
| 4080 | |
| 4081 | static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_AMODE_bf(const void *const hw, |
| 4082 | hri_sercomi2cs_ctrlb_reg_t mask) |
| 4083 | { |
| 4084 | uint32_t tmp; |
| 4085 | tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; |
| 4086 | tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE(mask)) >> SERCOM_I2CS_CTRLB_AMODE_Pos; |
| 4087 | return tmp; |
| 4088 | } |
| 4089 | |
| 4090 | static inline void hri_sercomi2cs_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) |
| 4091 | { |
| 4092 | uint32_t tmp; |
| 4093 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4094 | tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; |
| 4095 | tmp &= ~SERCOM_I2CS_CTRLB_AMODE_Msk; |
| 4096 | tmp |= SERCOM_I2CS_CTRLB_AMODE(data); |
| 4097 | ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; |
| 4098 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4099 | } |
| 4100 | |
| 4101 | static inline void hri_sercomi2cs_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) |
| 4102 | { |
| 4103 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4104 | ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AMODE(mask); |
| 4105 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4106 | } |
| 4107 | |
| 4108 | static inline void hri_sercomi2cs_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) |
| 4109 | { |
| 4110 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4111 | ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AMODE(mask); |
| 4112 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4113 | } |
| 4114 | |
| 4115 | static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_AMODE_bf(const void *const hw) |
| 4116 | { |
| 4117 | uint32_t tmp; |
| 4118 | tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; |
| 4119 | tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE_Msk) >> SERCOM_I2CS_CTRLB_AMODE_Pos; |
| 4120 | return tmp; |
| 4121 | } |
| 4122 | |
| 4123 | static inline void hri_sercomi2cs_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) |
| 4124 | { |
| 4125 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4126 | ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(mask); |
| 4127 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4128 | } |
| 4129 | |
| 4130 | static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_CMD_bf(const void *const hw, |
| 4131 | hri_sercomi2cs_ctrlb_reg_t mask) |
| 4132 | { |
| 4133 | uint32_t tmp; |
| 4134 | tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; |
| 4135 | tmp = (tmp & SERCOM_I2CS_CTRLB_CMD(mask)) >> SERCOM_I2CS_CTRLB_CMD_Pos; |
| 4136 | return tmp; |
| 4137 | } |
| 4138 | |
| 4139 | static inline void hri_sercomi2cs_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) |
| 4140 | { |
| 4141 | uint32_t tmp; |
| 4142 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4143 | tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; |
| 4144 | tmp &= ~SERCOM_I2CS_CTRLB_CMD_Msk; |
| 4145 | tmp |= SERCOM_I2CS_CTRLB_CMD(data); |
| 4146 | ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; |
| 4147 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4148 | } |
| 4149 | |
| 4150 | static inline void hri_sercomi2cs_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) |
| 4151 | { |
| 4152 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4153 | ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_CMD(mask); |
| 4154 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4155 | } |
| 4156 | |
| 4157 | static inline void hri_sercomi2cs_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) |
| 4158 | { |
| 4159 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4160 | ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_CMD(mask); |
| 4161 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4162 | } |
| 4163 | |
| 4164 | static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_CMD_bf(const void *const hw) |
| 4165 | { |
| 4166 | uint32_t tmp; |
| 4167 | tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; |
| 4168 | tmp = (tmp & SERCOM_I2CS_CTRLB_CMD_Msk) >> SERCOM_I2CS_CTRLB_CMD_Pos; |
| 4169 | return tmp; |
| 4170 | } |
| 4171 | |
| 4172 | static inline void hri_sercomi2cs_set_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) |
| 4173 | { |
| 4174 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4175 | ((Sercom *)hw)->I2CS.CTRLB.reg |= mask; |
| 4176 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4177 | } |
| 4178 | |
| 4179 | static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_reg(const void *const hw, |
| 4180 | hri_sercomi2cs_ctrlb_reg_t mask) |
| 4181 | { |
| 4182 | uint32_t tmp; |
| 4183 | tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; |
| 4184 | tmp &= mask; |
| 4185 | return tmp; |
| 4186 | } |
| 4187 | |
| 4188 | static inline void hri_sercomi2cs_write_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) |
| 4189 | { |
| 4190 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4191 | ((Sercom *)hw)->I2CS.CTRLB.reg = data; |
| 4192 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4193 | } |
| 4194 | |
| 4195 | static inline void hri_sercomi2cs_clear_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) |
| 4196 | { |
| 4197 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4198 | ((Sercom *)hw)->I2CS.CTRLB.reg &= ~mask; |
| 4199 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4200 | } |
| 4201 | |
| 4202 | static inline void hri_sercomi2cs_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) |
| 4203 | { |
| 4204 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4205 | ((Sercom *)hw)->I2CS.CTRLB.reg ^= mask; |
| 4206 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4207 | } |
| 4208 | |
| 4209 | static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_reg(const void *const hw) |
| 4210 | { |
| 4211 | return ((Sercom *)hw)->I2CS.CTRLB.reg; |
| 4212 | } |
| 4213 | |
| 4214 | static inline void hri_sercomspi_set_CTRLB_PLOADEN_bit(const void *const hw) |
| 4215 | { |
| 4216 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4217 | ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_PLOADEN; |
| 4218 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4219 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4220 | } |
| 4221 | |
| 4222 | static inline bool hri_sercomspi_get_CTRLB_PLOADEN_bit(const void *const hw) |
| 4223 | { |
| 4224 | uint32_t tmp; |
| 4225 | tmp = ((Sercom *)hw)->SPI.CTRLB.reg; |
| 4226 | tmp = (tmp & SERCOM_SPI_CTRLB_PLOADEN) >> SERCOM_SPI_CTRLB_PLOADEN_Pos; |
| 4227 | return (bool)tmp; |
| 4228 | } |
| 4229 | |
| 4230 | static inline void hri_sercomspi_write_CTRLB_PLOADEN_bit(const void *const hw, bool value) |
| 4231 | { |
| 4232 | uint32_t tmp; |
| 4233 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4234 | tmp = ((Sercom *)hw)->SPI.CTRLB.reg; |
| 4235 | tmp &= ~SERCOM_SPI_CTRLB_PLOADEN; |
| 4236 | tmp |= value << SERCOM_SPI_CTRLB_PLOADEN_Pos; |
| 4237 | ((Sercom *)hw)->SPI.CTRLB.reg = tmp; |
| 4238 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4239 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4240 | } |
| 4241 | |
| 4242 | static inline void hri_sercomspi_clear_CTRLB_PLOADEN_bit(const void *const hw) |
| 4243 | { |
| 4244 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4245 | ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_PLOADEN; |
| 4246 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4247 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4248 | } |
| 4249 | |
| 4250 | static inline void hri_sercomspi_toggle_CTRLB_PLOADEN_bit(const void *const hw) |
| 4251 | { |
| 4252 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4253 | ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_PLOADEN; |
| 4254 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4255 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4256 | } |
| 4257 | |
| 4258 | static inline void hri_sercomspi_set_CTRLB_SSDE_bit(const void *const hw) |
| 4259 | { |
| 4260 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4261 | ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_SSDE; |
| 4262 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4263 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4264 | } |
| 4265 | |
| 4266 | static inline bool hri_sercomspi_get_CTRLB_SSDE_bit(const void *const hw) |
| 4267 | { |
| 4268 | uint32_t tmp; |
| 4269 | tmp = ((Sercom *)hw)->SPI.CTRLB.reg; |
| 4270 | tmp = (tmp & SERCOM_SPI_CTRLB_SSDE) >> SERCOM_SPI_CTRLB_SSDE_Pos; |
| 4271 | return (bool)tmp; |
| 4272 | } |
| 4273 | |
| 4274 | static inline void hri_sercomspi_write_CTRLB_SSDE_bit(const void *const hw, bool value) |
| 4275 | { |
| 4276 | uint32_t tmp; |
| 4277 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4278 | tmp = ((Sercom *)hw)->SPI.CTRLB.reg; |
| 4279 | tmp &= ~SERCOM_SPI_CTRLB_SSDE; |
| 4280 | tmp |= value << SERCOM_SPI_CTRLB_SSDE_Pos; |
| 4281 | ((Sercom *)hw)->SPI.CTRLB.reg = tmp; |
| 4282 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4283 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4284 | } |
| 4285 | |
| 4286 | static inline void hri_sercomspi_clear_CTRLB_SSDE_bit(const void *const hw) |
| 4287 | { |
| 4288 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4289 | ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_SSDE; |
| 4290 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4291 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4292 | } |
| 4293 | |
| 4294 | static inline void hri_sercomspi_toggle_CTRLB_SSDE_bit(const void *const hw) |
| 4295 | { |
| 4296 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4297 | ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_SSDE; |
| 4298 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4299 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4300 | } |
| 4301 | |
| 4302 | static inline void hri_sercomspi_set_CTRLB_MSSEN_bit(const void *const hw) |
| 4303 | { |
| 4304 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4305 | ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_MSSEN; |
| 4306 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4307 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4308 | } |
| 4309 | |
| 4310 | static inline bool hri_sercomspi_get_CTRLB_MSSEN_bit(const void *const hw) |
| 4311 | { |
| 4312 | uint32_t tmp; |
| 4313 | tmp = ((Sercom *)hw)->SPI.CTRLB.reg; |
| 4314 | tmp = (tmp & SERCOM_SPI_CTRLB_MSSEN) >> SERCOM_SPI_CTRLB_MSSEN_Pos; |
| 4315 | return (bool)tmp; |
| 4316 | } |
| 4317 | |
| 4318 | static inline void hri_sercomspi_write_CTRLB_MSSEN_bit(const void *const hw, bool value) |
| 4319 | { |
| 4320 | uint32_t tmp; |
| 4321 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4322 | tmp = ((Sercom *)hw)->SPI.CTRLB.reg; |
| 4323 | tmp &= ~SERCOM_SPI_CTRLB_MSSEN; |
| 4324 | tmp |= value << SERCOM_SPI_CTRLB_MSSEN_Pos; |
| 4325 | ((Sercom *)hw)->SPI.CTRLB.reg = tmp; |
| 4326 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4327 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4328 | } |
| 4329 | |
| 4330 | static inline void hri_sercomspi_clear_CTRLB_MSSEN_bit(const void *const hw) |
| 4331 | { |
| 4332 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4333 | ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_MSSEN; |
| 4334 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4335 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4336 | } |
| 4337 | |
| 4338 | static inline void hri_sercomspi_toggle_CTRLB_MSSEN_bit(const void *const hw) |
| 4339 | { |
| 4340 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4341 | ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_MSSEN; |
| 4342 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4343 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4344 | } |
| 4345 | |
| 4346 | static inline void hri_sercomspi_set_CTRLB_RXEN_bit(const void *const hw) |
| 4347 | { |
| 4348 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4349 | ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_RXEN; |
| 4350 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4351 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4352 | } |
| 4353 | |
| 4354 | static inline bool hri_sercomspi_get_CTRLB_RXEN_bit(const void *const hw) |
| 4355 | { |
| 4356 | uint32_t tmp; |
| 4357 | tmp = ((Sercom *)hw)->SPI.CTRLB.reg; |
| 4358 | tmp = (tmp & SERCOM_SPI_CTRLB_RXEN) >> SERCOM_SPI_CTRLB_RXEN_Pos; |
| 4359 | return (bool)tmp; |
| 4360 | } |
| 4361 | |
| 4362 | static inline void hri_sercomspi_write_CTRLB_RXEN_bit(const void *const hw, bool value) |
| 4363 | { |
| 4364 | uint32_t tmp; |
| 4365 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4366 | tmp = ((Sercom *)hw)->SPI.CTRLB.reg; |
| 4367 | tmp &= ~SERCOM_SPI_CTRLB_RXEN; |
| 4368 | tmp |= value << SERCOM_SPI_CTRLB_RXEN_Pos; |
| 4369 | ((Sercom *)hw)->SPI.CTRLB.reg = tmp; |
| 4370 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4371 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4372 | } |
| 4373 | |
| 4374 | static inline void hri_sercomspi_clear_CTRLB_RXEN_bit(const void *const hw) |
| 4375 | { |
| 4376 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4377 | ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_RXEN; |
| 4378 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4379 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4380 | } |
| 4381 | |
| 4382 | static inline void hri_sercomspi_toggle_CTRLB_RXEN_bit(const void *const hw) |
| 4383 | { |
| 4384 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4385 | ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_RXEN; |
| 4386 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4387 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4388 | } |
| 4389 | |
| 4390 | static inline void hri_sercomspi_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) |
| 4391 | { |
| 4392 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4393 | ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_CHSIZE(mask); |
| 4394 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4395 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4396 | } |
| 4397 | |
| 4398 | static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_CHSIZE_bf(const void *const hw, |
| 4399 | hri_sercomspi_ctrlb_reg_t mask) |
| 4400 | { |
| 4401 | uint32_t tmp; |
| 4402 | tmp = ((Sercom *)hw)->SPI.CTRLB.reg; |
| 4403 | tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE(mask)) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; |
| 4404 | return tmp; |
| 4405 | } |
| 4406 | |
| 4407 | static inline void hri_sercomspi_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) |
| 4408 | { |
| 4409 | uint32_t tmp; |
| 4410 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4411 | tmp = ((Sercom *)hw)->SPI.CTRLB.reg; |
| 4412 | tmp &= ~SERCOM_SPI_CTRLB_CHSIZE_Msk; |
| 4413 | tmp |= SERCOM_SPI_CTRLB_CHSIZE(data); |
| 4414 | ((Sercom *)hw)->SPI.CTRLB.reg = tmp; |
| 4415 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4416 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4417 | } |
| 4418 | |
| 4419 | static inline void hri_sercomspi_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) |
| 4420 | { |
| 4421 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4422 | ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_CHSIZE(mask); |
| 4423 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4424 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4425 | } |
| 4426 | |
| 4427 | static inline void hri_sercomspi_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) |
| 4428 | { |
| 4429 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4430 | ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_CHSIZE(mask); |
| 4431 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4432 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4433 | } |
| 4434 | |
| 4435 | static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_CHSIZE_bf(const void *const hw) |
| 4436 | { |
| 4437 | uint32_t tmp; |
| 4438 | tmp = ((Sercom *)hw)->SPI.CTRLB.reg; |
| 4439 | tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE_Msk) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; |
| 4440 | return tmp; |
| 4441 | } |
| 4442 | |
| 4443 | static inline void hri_sercomspi_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) |
| 4444 | { |
| 4445 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4446 | ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_AMODE(mask); |
| 4447 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4448 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4449 | } |
| 4450 | |
| 4451 | static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_AMODE_bf(const void *const hw, |
| 4452 | hri_sercomspi_ctrlb_reg_t mask) |
| 4453 | { |
| 4454 | uint32_t tmp; |
| 4455 | tmp = ((Sercom *)hw)->SPI.CTRLB.reg; |
| 4456 | tmp = (tmp & SERCOM_SPI_CTRLB_AMODE(mask)) >> SERCOM_SPI_CTRLB_AMODE_Pos; |
| 4457 | return tmp; |
| 4458 | } |
| 4459 | |
| 4460 | static inline void hri_sercomspi_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) |
| 4461 | { |
| 4462 | uint32_t tmp; |
| 4463 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4464 | tmp = ((Sercom *)hw)->SPI.CTRLB.reg; |
| 4465 | tmp &= ~SERCOM_SPI_CTRLB_AMODE_Msk; |
| 4466 | tmp |= SERCOM_SPI_CTRLB_AMODE(data); |
| 4467 | ((Sercom *)hw)->SPI.CTRLB.reg = tmp; |
| 4468 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4469 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4470 | } |
| 4471 | |
| 4472 | static inline void hri_sercomspi_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) |
| 4473 | { |
| 4474 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4475 | ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_AMODE(mask); |
| 4476 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4477 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4478 | } |
| 4479 | |
| 4480 | static inline void hri_sercomspi_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) |
| 4481 | { |
| 4482 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4483 | ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_AMODE(mask); |
| 4484 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4485 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4486 | } |
| 4487 | |
| 4488 | static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_AMODE_bf(const void *const hw) |
| 4489 | { |
| 4490 | uint32_t tmp; |
| 4491 | tmp = ((Sercom *)hw)->SPI.CTRLB.reg; |
| 4492 | tmp = (tmp & SERCOM_SPI_CTRLB_AMODE_Msk) >> SERCOM_SPI_CTRLB_AMODE_Pos; |
| 4493 | return tmp; |
| 4494 | } |
| 4495 | |
| 4496 | static inline void hri_sercomspi_set_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) |
| 4497 | { |
| 4498 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4499 | ((Sercom *)hw)->SPI.CTRLB.reg |= mask; |
| 4500 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4501 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4502 | } |
| 4503 | |
| 4504 | static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_reg(const void *const hw, |
| 4505 | hri_sercomspi_ctrlb_reg_t mask) |
| 4506 | { |
| 4507 | uint32_t tmp; |
| 4508 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4509 | tmp = ((Sercom *)hw)->SPI.CTRLB.reg; |
| 4510 | tmp &= mask; |
| 4511 | return tmp; |
| 4512 | } |
| 4513 | |
| 4514 | static inline void hri_sercomspi_write_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t data) |
| 4515 | { |
| 4516 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4517 | ((Sercom *)hw)->SPI.CTRLB.reg = data; |
| 4518 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4519 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4520 | } |
| 4521 | |
| 4522 | static inline void hri_sercomspi_clear_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) |
| 4523 | { |
| 4524 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4525 | ((Sercom *)hw)->SPI.CTRLB.reg &= ~mask; |
| 4526 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4527 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4528 | } |
| 4529 | |
| 4530 | static inline void hri_sercomspi_toggle_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) |
| 4531 | { |
| 4532 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4533 | ((Sercom *)hw)->SPI.CTRLB.reg ^= mask; |
| 4534 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4535 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4536 | } |
| 4537 | |
| 4538 | static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_reg(const void *const hw) |
| 4539 | { |
| 4540 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 4541 | return ((Sercom *)hw)->SPI.CTRLB.reg; |
| 4542 | } |
| 4543 | |
| 4544 | static inline void hri_sercomusart_set_CTRLB_SBMODE_bit(const void *const hw) |
| 4545 | { |
| 4546 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4547 | ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SBMODE; |
| 4548 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4549 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4550 | } |
| 4551 | |
| 4552 | static inline bool hri_sercomusart_get_CTRLB_SBMODE_bit(const void *const hw) |
| 4553 | { |
| 4554 | uint32_t tmp; |
| 4555 | tmp = ((Sercom *)hw)->USART.CTRLB.reg; |
| 4556 | tmp = (tmp & SERCOM_USART_CTRLB_SBMODE) >> SERCOM_USART_CTRLB_SBMODE_Pos; |
| 4557 | return (bool)tmp; |
| 4558 | } |
| 4559 | |
| 4560 | static inline void hri_sercomusart_write_CTRLB_SBMODE_bit(const void *const hw, bool value) |
| 4561 | { |
| 4562 | uint32_t tmp; |
| 4563 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4564 | tmp = ((Sercom *)hw)->USART.CTRLB.reg; |
| 4565 | tmp &= ~SERCOM_USART_CTRLB_SBMODE; |
| 4566 | tmp |= value << SERCOM_USART_CTRLB_SBMODE_Pos; |
| 4567 | ((Sercom *)hw)->USART.CTRLB.reg = tmp; |
| 4568 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4569 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4570 | } |
| 4571 | |
| 4572 | static inline void hri_sercomusart_clear_CTRLB_SBMODE_bit(const void *const hw) |
| 4573 | { |
| 4574 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4575 | ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SBMODE; |
| 4576 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4577 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4578 | } |
| 4579 | |
| 4580 | static inline void hri_sercomusart_toggle_CTRLB_SBMODE_bit(const void *const hw) |
| 4581 | { |
| 4582 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4583 | ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SBMODE; |
| 4584 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4585 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4586 | } |
| 4587 | |
| 4588 | static inline void hri_sercomusart_set_CTRLB_COLDEN_bit(const void *const hw) |
| 4589 | { |
| 4590 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4591 | ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_COLDEN; |
| 4592 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4593 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4594 | } |
| 4595 | |
| 4596 | static inline bool hri_sercomusart_get_CTRLB_COLDEN_bit(const void *const hw) |
| 4597 | { |
| 4598 | uint32_t tmp; |
| 4599 | tmp = ((Sercom *)hw)->USART.CTRLB.reg; |
| 4600 | tmp = (tmp & SERCOM_USART_CTRLB_COLDEN) >> SERCOM_USART_CTRLB_COLDEN_Pos; |
| 4601 | return (bool)tmp; |
| 4602 | } |
| 4603 | |
| 4604 | static inline void hri_sercomusart_write_CTRLB_COLDEN_bit(const void *const hw, bool value) |
| 4605 | { |
| 4606 | uint32_t tmp; |
| 4607 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4608 | tmp = ((Sercom *)hw)->USART.CTRLB.reg; |
| 4609 | tmp &= ~SERCOM_USART_CTRLB_COLDEN; |
| 4610 | tmp |= value << SERCOM_USART_CTRLB_COLDEN_Pos; |
| 4611 | ((Sercom *)hw)->USART.CTRLB.reg = tmp; |
| 4612 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4613 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4614 | } |
| 4615 | |
| 4616 | static inline void hri_sercomusart_clear_CTRLB_COLDEN_bit(const void *const hw) |
| 4617 | { |
| 4618 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4619 | ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_COLDEN; |
| 4620 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4621 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4622 | } |
| 4623 | |
| 4624 | static inline void hri_sercomusart_toggle_CTRLB_COLDEN_bit(const void *const hw) |
| 4625 | { |
| 4626 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4627 | ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_COLDEN; |
| 4628 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4629 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4630 | } |
| 4631 | |
| 4632 | static inline void hri_sercomusart_set_CTRLB_SFDE_bit(const void *const hw) |
| 4633 | { |
| 4634 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4635 | ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SFDE; |
| 4636 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4637 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4638 | } |
| 4639 | |
| 4640 | static inline bool hri_sercomusart_get_CTRLB_SFDE_bit(const void *const hw) |
| 4641 | { |
| 4642 | uint32_t tmp; |
| 4643 | tmp = ((Sercom *)hw)->USART.CTRLB.reg; |
| 4644 | tmp = (tmp & SERCOM_USART_CTRLB_SFDE) >> SERCOM_USART_CTRLB_SFDE_Pos; |
| 4645 | return (bool)tmp; |
| 4646 | } |
| 4647 | |
| 4648 | static inline void hri_sercomusart_write_CTRLB_SFDE_bit(const void *const hw, bool value) |
| 4649 | { |
| 4650 | uint32_t tmp; |
| 4651 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4652 | tmp = ((Sercom *)hw)->USART.CTRLB.reg; |
| 4653 | tmp &= ~SERCOM_USART_CTRLB_SFDE; |
| 4654 | tmp |= value << SERCOM_USART_CTRLB_SFDE_Pos; |
| 4655 | ((Sercom *)hw)->USART.CTRLB.reg = tmp; |
| 4656 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4657 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4658 | } |
| 4659 | |
| 4660 | static inline void hri_sercomusart_clear_CTRLB_SFDE_bit(const void *const hw) |
| 4661 | { |
| 4662 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4663 | ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SFDE; |
| 4664 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4665 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4666 | } |
| 4667 | |
| 4668 | static inline void hri_sercomusart_toggle_CTRLB_SFDE_bit(const void *const hw) |
| 4669 | { |
| 4670 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4671 | ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SFDE; |
| 4672 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4673 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4674 | } |
| 4675 | |
| 4676 | static inline void hri_sercomusart_set_CTRLB_ENC_bit(const void *const hw) |
| 4677 | { |
| 4678 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4679 | ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_ENC; |
| 4680 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4681 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4682 | } |
| 4683 | |
| 4684 | static inline bool hri_sercomusart_get_CTRLB_ENC_bit(const void *const hw) |
| 4685 | { |
| 4686 | uint32_t tmp; |
| 4687 | tmp = ((Sercom *)hw)->USART.CTRLB.reg; |
| 4688 | tmp = (tmp & SERCOM_USART_CTRLB_ENC) >> SERCOM_USART_CTRLB_ENC_Pos; |
| 4689 | return (bool)tmp; |
| 4690 | } |
| 4691 | |
| 4692 | static inline void hri_sercomusart_write_CTRLB_ENC_bit(const void *const hw, bool value) |
| 4693 | { |
| 4694 | uint32_t tmp; |
| 4695 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4696 | tmp = ((Sercom *)hw)->USART.CTRLB.reg; |
| 4697 | tmp &= ~SERCOM_USART_CTRLB_ENC; |
| 4698 | tmp |= value << SERCOM_USART_CTRLB_ENC_Pos; |
| 4699 | ((Sercom *)hw)->USART.CTRLB.reg = tmp; |
| 4700 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4701 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4702 | } |
| 4703 | |
| 4704 | static inline void hri_sercomusart_clear_CTRLB_ENC_bit(const void *const hw) |
| 4705 | { |
| 4706 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4707 | ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_ENC; |
| 4708 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4709 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4710 | } |
| 4711 | |
| 4712 | static inline void hri_sercomusart_toggle_CTRLB_ENC_bit(const void *const hw) |
| 4713 | { |
| 4714 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4715 | ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_ENC; |
| 4716 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4717 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4718 | } |
| 4719 | |
| 4720 | static inline void hri_sercomusart_set_CTRLB_PMODE_bit(const void *const hw) |
| 4721 | { |
| 4722 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4723 | ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_PMODE; |
| 4724 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4725 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4726 | } |
| 4727 | |
| 4728 | static inline bool hri_sercomusart_get_CTRLB_PMODE_bit(const void *const hw) |
| 4729 | { |
| 4730 | uint32_t tmp; |
| 4731 | tmp = ((Sercom *)hw)->USART.CTRLB.reg; |
| 4732 | tmp = (tmp & SERCOM_USART_CTRLB_PMODE) >> SERCOM_USART_CTRLB_PMODE_Pos; |
| 4733 | return (bool)tmp; |
| 4734 | } |
| 4735 | |
| 4736 | static inline void hri_sercomusart_write_CTRLB_PMODE_bit(const void *const hw, bool value) |
| 4737 | { |
| 4738 | uint32_t tmp; |
| 4739 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4740 | tmp = ((Sercom *)hw)->USART.CTRLB.reg; |
| 4741 | tmp &= ~SERCOM_USART_CTRLB_PMODE; |
| 4742 | tmp |= value << SERCOM_USART_CTRLB_PMODE_Pos; |
| 4743 | ((Sercom *)hw)->USART.CTRLB.reg = tmp; |
| 4744 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4745 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4746 | } |
| 4747 | |
| 4748 | static inline void hri_sercomusart_clear_CTRLB_PMODE_bit(const void *const hw) |
| 4749 | { |
| 4750 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4751 | ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_PMODE; |
| 4752 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4753 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4754 | } |
| 4755 | |
| 4756 | static inline void hri_sercomusart_toggle_CTRLB_PMODE_bit(const void *const hw) |
| 4757 | { |
| 4758 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4759 | ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_PMODE; |
| 4760 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4761 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4762 | } |
| 4763 | |
| 4764 | static inline void hri_sercomusart_set_CTRLB_TXEN_bit(const void *const hw) |
| 4765 | { |
| 4766 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4767 | ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN; |
| 4768 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4769 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4770 | } |
| 4771 | |
| 4772 | static inline bool hri_sercomusart_get_CTRLB_TXEN_bit(const void *const hw) |
| 4773 | { |
| 4774 | uint32_t tmp; |
| 4775 | tmp = ((Sercom *)hw)->USART.CTRLB.reg; |
| 4776 | tmp = (tmp & SERCOM_USART_CTRLB_TXEN) >> SERCOM_USART_CTRLB_TXEN_Pos; |
| 4777 | return (bool)tmp; |
| 4778 | } |
| 4779 | |
| 4780 | static inline void hri_sercomusart_write_CTRLB_TXEN_bit(const void *const hw, bool value) |
| 4781 | { |
| 4782 | uint32_t tmp; |
| 4783 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4784 | tmp = ((Sercom *)hw)->USART.CTRLB.reg; |
| 4785 | tmp &= ~SERCOM_USART_CTRLB_TXEN; |
| 4786 | tmp |= value << SERCOM_USART_CTRLB_TXEN_Pos; |
| 4787 | ((Sercom *)hw)->USART.CTRLB.reg = tmp; |
| 4788 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4789 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4790 | } |
| 4791 | |
| 4792 | static inline void hri_sercomusart_clear_CTRLB_TXEN_bit(const void *const hw) |
| 4793 | { |
| 4794 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4795 | ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN; |
| 4796 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4797 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4798 | } |
| 4799 | |
| 4800 | static inline void hri_sercomusart_toggle_CTRLB_TXEN_bit(const void *const hw) |
| 4801 | { |
| 4802 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4803 | ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_TXEN; |
| 4804 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4805 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4806 | } |
| 4807 | |
| 4808 | static inline void hri_sercomusart_set_CTRLB_RXEN_bit(const void *const hw) |
| 4809 | { |
| 4810 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4811 | ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_RXEN; |
| 4812 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4813 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4814 | } |
| 4815 | |
| 4816 | static inline bool hri_sercomusart_get_CTRLB_RXEN_bit(const void *const hw) |
| 4817 | { |
| 4818 | uint32_t tmp; |
| 4819 | tmp = ((Sercom *)hw)->USART.CTRLB.reg; |
| 4820 | tmp = (tmp & SERCOM_USART_CTRLB_RXEN) >> SERCOM_USART_CTRLB_RXEN_Pos; |
| 4821 | return (bool)tmp; |
| 4822 | } |
| 4823 | |
| 4824 | static inline void hri_sercomusart_write_CTRLB_RXEN_bit(const void *const hw, bool value) |
| 4825 | { |
| 4826 | uint32_t tmp; |
| 4827 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4828 | tmp = ((Sercom *)hw)->USART.CTRLB.reg; |
| 4829 | tmp &= ~SERCOM_USART_CTRLB_RXEN; |
| 4830 | tmp |= value << SERCOM_USART_CTRLB_RXEN_Pos; |
| 4831 | ((Sercom *)hw)->USART.CTRLB.reg = tmp; |
| 4832 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4833 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4834 | } |
| 4835 | |
| 4836 | static inline void hri_sercomusart_clear_CTRLB_RXEN_bit(const void *const hw) |
| 4837 | { |
| 4838 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4839 | ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN; |
| 4840 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4841 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4842 | } |
| 4843 | |
| 4844 | static inline void hri_sercomusart_toggle_CTRLB_RXEN_bit(const void *const hw) |
| 4845 | { |
| 4846 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4847 | ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_RXEN; |
| 4848 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4849 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4850 | } |
| 4851 | |
| 4852 | static inline void hri_sercomusart_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) |
| 4853 | { |
| 4854 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4855 | ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(mask); |
| 4856 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4857 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4858 | } |
| 4859 | |
| 4860 | static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_CHSIZE_bf(const void *const hw, |
| 4861 | hri_sercomusart_ctrlb_reg_t mask) |
| 4862 | { |
| 4863 | uint32_t tmp; |
| 4864 | tmp = ((Sercom *)hw)->USART.CTRLB.reg; |
| 4865 | tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE(mask)) >> SERCOM_USART_CTRLB_CHSIZE_Pos; |
| 4866 | return tmp; |
| 4867 | } |
| 4868 | |
| 4869 | static inline void hri_sercomusart_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data) |
| 4870 | { |
| 4871 | uint32_t tmp; |
| 4872 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4873 | tmp = ((Sercom *)hw)->USART.CTRLB.reg; |
| 4874 | tmp &= ~SERCOM_USART_CTRLB_CHSIZE_Msk; |
| 4875 | tmp |= SERCOM_USART_CTRLB_CHSIZE(data); |
| 4876 | ((Sercom *)hw)->USART.CTRLB.reg = tmp; |
| 4877 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4878 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4879 | } |
| 4880 | |
| 4881 | static inline void hri_sercomusart_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) |
| 4882 | { |
| 4883 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4884 | ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_CHSIZE(mask); |
| 4885 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4886 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4887 | } |
| 4888 | |
| 4889 | static inline void hri_sercomusart_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) |
| 4890 | { |
| 4891 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4892 | ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_CHSIZE(mask); |
| 4893 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4894 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4895 | } |
| 4896 | |
| 4897 | static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_CHSIZE_bf(const void *const hw) |
| 4898 | { |
| 4899 | uint32_t tmp; |
| 4900 | tmp = ((Sercom *)hw)->USART.CTRLB.reg; |
| 4901 | tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE_Msk) >> SERCOM_USART_CTRLB_CHSIZE_Pos; |
| 4902 | return tmp; |
| 4903 | } |
| 4904 | |
| 4905 | static inline void hri_sercomusart_set_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) |
| 4906 | { |
| 4907 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4908 | ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_LINCMD(mask); |
| 4909 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4910 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4911 | } |
| 4912 | |
| 4913 | static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_LINCMD_bf(const void *const hw, |
| 4914 | hri_sercomusart_ctrlb_reg_t mask) |
| 4915 | { |
| 4916 | uint32_t tmp; |
| 4917 | tmp = ((Sercom *)hw)->USART.CTRLB.reg; |
| 4918 | tmp = (tmp & SERCOM_USART_CTRLB_LINCMD(mask)) >> SERCOM_USART_CTRLB_LINCMD_Pos; |
| 4919 | return tmp; |
| 4920 | } |
| 4921 | |
| 4922 | static inline void hri_sercomusart_write_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data) |
| 4923 | { |
| 4924 | uint32_t tmp; |
| 4925 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4926 | tmp = ((Sercom *)hw)->USART.CTRLB.reg; |
| 4927 | tmp &= ~SERCOM_USART_CTRLB_LINCMD_Msk; |
| 4928 | tmp |= SERCOM_USART_CTRLB_LINCMD(data); |
| 4929 | ((Sercom *)hw)->USART.CTRLB.reg = tmp; |
| 4930 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4931 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4932 | } |
| 4933 | |
| 4934 | static inline void hri_sercomusart_clear_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) |
| 4935 | { |
| 4936 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4937 | ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_LINCMD(mask); |
| 4938 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4939 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4940 | } |
| 4941 | |
| 4942 | static inline void hri_sercomusart_toggle_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) |
| 4943 | { |
| 4944 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4945 | ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_LINCMD(mask); |
| 4946 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4947 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4948 | } |
| 4949 | |
| 4950 | static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_LINCMD_bf(const void *const hw) |
| 4951 | { |
| 4952 | uint32_t tmp; |
| 4953 | tmp = ((Sercom *)hw)->USART.CTRLB.reg; |
| 4954 | tmp = (tmp & SERCOM_USART_CTRLB_LINCMD_Msk) >> SERCOM_USART_CTRLB_LINCMD_Pos; |
| 4955 | return tmp; |
| 4956 | } |
| 4957 | |
| 4958 | static inline void hri_sercomusart_set_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) |
| 4959 | { |
| 4960 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4961 | ((Sercom *)hw)->USART.CTRLB.reg |= mask; |
| 4962 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4963 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4964 | } |
| 4965 | |
| 4966 | static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_reg(const void *const hw, |
| 4967 | hri_sercomusart_ctrlb_reg_t mask) |
| 4968 | { |
| 4969 | uint32_t tmp; |
| 4970 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4971 | tmp = ((Sercom *)hw)->USART.CTRLB.reg; |
| 4972 | tmp &= mask; |
| 4973 | return tmp; |
| 4974 | } |
| 4975 | |
| 4976 | static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data) |
| 4977 | { |
| 4978 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4979 | ((Sercom *)hw)->USART.CTRLB.reg = data; |
| 4980 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4981 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4982 | } |
| 4983 | |
| 4984 | static inline void hri_sercomusart_clear_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) |
| 4985 | { |
| 4986 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4987 | ((Sercom *)hw)->USART.CTRLB.reg &= ~mask; |
| 4988 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4989 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4990 | } |
| 4991 | |
| 4992 | static inline void hri_sercomusart_toggle_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) |
| 4993 | { |
| 4994 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 4995 | ((Sercom *)hw)->USART.CTRLB.reg ^= mask; |
| 4996 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 4997 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 4998 | } |
| 4999 | |
| 5000 | static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_reg(const void *const hw) |
| 5001 | { |
| 5002 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 5003 | return ((Sercom *)hw)->USART.CTRLB.reg; |
| 5004 | } |
| 5005 | |
| 5006 | static inline void hri_sercomi2cm_set_CTRLC_DATA32B_bit(const void *const hw) |
| 5007 | { |
| 5008 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5009 | ((Sercom *)hw)->I2CM.CTRLC.reg |= SERCOM_I2CM_CTRLC_DATA32B; |
| 5010 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5011 | } |
| 5012 | |
| 5013 | static inline bool hri_sercomi2cm_get_CTRLC_DATA32B_bit(const void *const hw) |
| 5014 | { |
| 5015 | uint32_t tmp; |
| 5016 | tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; |
| 5017 | tmp = (tmp & SERCOM_I2CM_CTRLC_DATA32B) >> SERCOM_I2CM_CTRLC_DATA32B_Pos; |
| 5018 | return (bool)tmp; |
| 5019 | } |
| 5020 | |
| 5021 | static inline void hri_sercomi2cm_write_CTRLC_DATA32B_bit(const void *const hw, bool value) |
| 5022 | { |
| 5023 | uint32_t tmp; |
| 5024 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5025 | tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; |
| 5026 | tmp &= ~SERCOM_I2CM_CTRLC_DATA32B; |
| 5027 | tmp |= value << SERCOM_I2CM_CTRLC_DATA32B_Pos; |
| 5028 | ((Sercom *)hw)->I2CM.CTRLC.reg = tmp; |
| 5029 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5030 | } |
| 5031 | |
| 5032 | static inline void hri_sercomi2cm_clear_CTRLC_DATA32B_bit(const void *const hw) |
| 5033 | { |
| 5034 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5035 | ((Sercom *)hw)->I2CM.CTRLC.reg &= ~SERCOM_I2CM_CTRLC_DATA32B; |
| 5036 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5037 | } |
| 5038 | |
| 5039 | static inline void hri_sercomi2cm_toggle_CTRLC_DATA32B_bit(const void *const hw) |
| 5040 | { |
| 5041 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5042 | ((Sercom *)hw)->I2CM.CTRLC.reg ^= SERCOM_I2CM_CTRLC_DATA32B; |
| 5043 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5044 | } |
| 5045 | |
| 5046 | static inline void hri_sercomi2cm_set_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask) |
| 5047 | { |
| 5048 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5049 | ((Sercom *)hw)->I2CM.CTRLC.reg |= mask; |
| 5050 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5051 | } |
| 5052 | |
| 5053 | static inline hri_sercomi2cm_ctrlc_reg_t hri_sercomi2cm_get_CTRLC_reg(const void *const hw, |
| 5054 | hri_sercomi2cm_ctrlc_reg_t mask) |
| 5055 | { |
| 5056 | uint32_t tmp; |
| 5057 | tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; |
| 5058 | tmp &= mask; |
| 5059 | return tmp; |
| 5060 | } |
| 5061 | |
| 5062 | static inline void hri_sercomi2cm_write_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t data) |
| 5063 | { |
| 5064 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5065 | ((Sercom *)hw)->I2CM.CTRLC.reg = data; |
| 5066 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5067 | } |
| 5068 | |
| 5069 | static inline void hri_sercomi2cm_clear_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask) |
| 5070 | { |
| 5071 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5072 | ((Sercom *)hw)->I2CM.CTRLC.reg &= ~mask; |
| 5073 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5074 | } |
| 5075 | |
| 5076 | static inline void hri_sercomi2cm_toggle_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask) |
| 5077 | { |
| 5078 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5079 | ((Sercom *)hw)->I2CM.CTRLC.reg ^= mask; |
| 5080 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5081 | } |
| 5082 | |
| 5083 | static inline hri_sercomi2cm_ctrlc_reg_t hri_sercomi2cm_read_CTRLC_reg(const void *const hw) |
| 5084 | { |
| 5085 | return ((Sercom *)hw)->I2CM.CTRLC.reg; |
| 5086 | } |
| 5087 | |
| 5088 | static inline void hri_sercomi2cs_set_CTRLC_DATA32B_bit(const void *const hw) |
| 5089 | { |
| 5090 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5091 | ((Sercom *)hw)->I2CS.CTRLC.reg |= SERCOM_I2CS_CTRLC_DATA32B; |
| 5092 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5093 | } |
| 5094 | |
| 5095 | static inline bool hri_sercomi2cs_get_CTRLC_DATA32B_bit(const void *const hw) |
| 5096 | { |
| 5097 | uint32_t tmp; |
| 5098 | tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; |
| 5099 | tmp = (tmp & SERCOM_I2CS_CTRLC_DATA32B) >> SERCOM_I2CS_CTRLC_DATA32B_Pos; |
| 5100 | return (bool)tmp; |
| 5101 | } |
| 5102 | |
| 5103 | static inline void hri_sercomi2cs_write_CTRLC_DATA32B_bit(const void *const hw, bool value) |
| 5104 | { |
| 5105 | uint32_t tmp; |
| 5106 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5107 | tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; |
| 5108 | tmp &= ~SERCOM_I2CS_CTRLC_DATA32B; |
| 5109 | tmp |= value << SERCOM_I2CS_CTRLC_DATA32B_Pos; |
| 5110 | ((Sercom *)hw)->I2CS.CTRLC.reg = tmp; |
| 5111 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5112 | } |
| 5113 | |
| 5114 | static inline void hri_sercomi2cs_clear_CTRLC_DATA32B_bit(const void *const hw) |
| 5115 | { |
| 5116 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5117 | ((Sercom *)hw)->I2CS.CTRLC.reg &= ~SERCOM_I2CS_CTRLC_DATA32B; |
| 5118 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5119 | } |
| 5120 | |
| 5121 | static inline void hri_sercomi2cs_toggle_CTRLC_DATA32B_bit(const void *const hw) |
| 5122 | { |
| 5123 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5124 | ((Sercom *)hw)->I2CS.CTRLC.reg ^= SERCOM_I2CS_CTRLC_DATA32B; |
| 5125 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5126 | } |
| 5127 | |
| 5128 | static inline void hri_sercomi2cs_set_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) |
| 5129 | { |
| 5130 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5131 | ((Sercom *)hw)->I2CS.CTRLC.reg |= SERCOM_I2CS_CTRLC_SDASETUP(mask); |
| 5132 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5133 | } |
| 5134 | |
| 5135 | static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_get_CTRLC_SDASETUP_bf(const void *const hw, |
| 5136 | hri_sercomi2cs_ctrlc_reg_t mask) |
| 5137 | { |
| 5138 | uint32_t tmp; |
| 5139 | tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; |
| 5140 | tmp = (tmp & SERCOM_I2CS_CTRLC_SDASETUP(mask)) >> SERCOM_I2CS_CTRLC_SDASETUP_Pos; |
| 5141 | return tmp; |
| 5142 | } |
| 5143 | |
| 5144 | static inline void hri_sercomi2cs_write_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t data) |
| 5145 | { |
| 5146 | uint32_t tmp; |
| 5147 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5148 | tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; |
| 5149 | tmp &= ~SERCOM_I2CS_CTRLC_SDASETUP_Msk; |
| 5150 | tmp |= SERCOM_I2CS_CTRLC_SDASETUP(data); |
| 5151 | ((Sercom *)hw)->I2CS.CTRLC.reg = tmp; |
| 5152 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5153 | } |
| 5154 | |
| 5155 | static inline void hri_sercomi2cs_clear_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) |
| 5156 | { |
| 5157 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5158 | ((Sercom *)hw)->I2CS.CTRLC.reg &= ~SERCOM_I2CS_CTRLC_SDASETUP(mask); |
| 5159 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5160 | } |
| 5161 | |
| 5162 | static inline void hri_sercomi2cs_toggle_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) |
| 5163 | { |
| 5164 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5165 | ((Sercom *)hw)->I2CS.CTRLC.reg ^= SERCOM_I2CS_CTRLC_SDASETUP(mask); |
| 5166 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5167 | } |
| 5168 | |
| 5169 | static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_read_CTRLC_SDASETUP_bf(const void *const hw) |
| 5170 | { |
| 5171 | uint32_t tmp; |
| 5172 | tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; |
| 5173 | tmp = (tmp & SERCOM_I2CS_CTRLC_SDASETUP_Msk) >> SERCOM_I2CS_CTRLC_SDASETUP_Pos; |
| 5174 | return tmp; |
| 5175 | } |
| 5176 | |
| 5177 | static inline void hri_sercomi2cs_set_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) |
| 5178 | { |
| 5179 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5180 | ((Sercom *)hw)->I2CS.CTRLC.reg |= mask; |
| 5181 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5182 | } |
| 5183 | |
| 5184 | static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_get_CTRLC_reg(const void *const hw, |
| 5185 | hri_sercomi2cs_ctrlc_reg_t mask) |
| 5186 | { |
| 5187 | uint32_t tmp; |
| 5188 | tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; |
| 5189 | tmp &= mask; |
| 5190 | return tmp; |
| 5191 | } |
| 5192 | |
| 5193 | static inline void hri_sercomi2cs_write_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t data) |
| 5194 | { |
| 5195 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5196 | ((Sercom *)hw)->I2CS.CTRLC.reg = data; |
| 5197 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5198 | } |
| 5199 | |
| 5200 | static inline void hri_sercomi2cs_clear_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) |
| 5201 | { |
| 5202 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5203 | ((Sercom *)hw)->I2CS.CTRLC.reg &= ~mask; |
| 5204 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5205 | } |
| 5206 | |
| 5207 | static inline void hri_sercomi2cs_toggle_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) |
| 5208 | { |
| 5209 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5210 | ((Sercom *)hw)->I2CS.CTRLC.reg ^= mask; |
| 5211 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5212 | } |
| 5213 | |
| 5214 | static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_read_CTRLC_reg(const void *const hw) |
| 5215 | { |
| 5216 | return ((Sercom *)hw)->I2CS.CTRLC.reg; |
| 5217 | } |
| 5218 | |
| 5219 | static inline void hri_sercomspi_set_CTRLC_DATA32B_bit(const void *const hw) |
| 5220 | { |
| 5221 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5222 | ((Sercom *)hw)->SPI.CTRLC.reg |= SERCOM_SPI_CTRLC_DATA32B; |
| 5223 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5224 | } |
| 5225 | |
| 5226 | static inline bool hri_sercomspi_get_CTRLC_DATA32B_bit(const void *const hw) |
| 5227 | { |
| 5228 | uint32_t tmp; |
| 5229 | tmp = ((Sercom *)hw)->SPI.CTRLC.reg; |
| 5230 | tmp = (tmp & SERCOM_SPI_CTRLC_DATA32B) >> SERCOM_SPI_CTRLC_DATA32B_Pos; |
| 5231 | return (bool)tmp; |
| 5232 | } |
| 5233 | |
| 5234 | static inline void hri_sercomspi_write_CTRLC_DATA32B_bit(const void *const hw, bool value) |
| 5235 | { |
| 5236 | uint32_t tmp; |
| 5237 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5238 | tmp = ((Sercom *)hw)->SPI.CTRLC.reg; |
| 5239 | tmp &= ~SERCOM_SPI_CTRLC_DATA32B; |
| 5240 | tmp |= value << SERCOM_SPI_CTRLC_DATA32B_Pos; |
| 5241 | ((Sercom *)hw)->SPI.CTRLC.reg = tmp; |
| 5242 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5243 | } |
| 5244 | |
| 5245 | static inline void hri_sercomspi_clear_CTRLC_DATA32B_bit(const void *const hw) |
| 5246 | { |
| 5247 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5248 | ((Sercom *)hw)->SPI.CTRLC.reg &= ~SERCOM_SPI_CTRLC_DATA32B; |
| 5249 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5250 | } |
| 5251 | |
| 5252 | static inline void hri_sercomspi_toggle_CTRLC_DATA32B_bit(const void *const hw) |
| 5253 | { |
| 5254 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5255 | ((Sercom *)hw)->SPI.CTRLC.reg ^= SERCOM_SPI_CTRLC_DATA32B; |
| 5256 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5257 | } |
| 5258 | |
| 5259 | static inline void hri_sercomspi_set_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) |
| 5260 | { |
| 5261 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5262 | ((Sercom *)hw)->SPI.CTRLC.reg |= SERCOM_SPI_CTRLC_ICSPACE(mask); |
| 5263 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5264 | } |
| 5265 | |
| 5266 | static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_get_CTRLC_ICSPACE_bf(const void *const hw, |
| 5267 | hri_sercomspi_ctrlc_reg_t mask) |
| 5268 | { |
| 5269 | uint32_t tmp; |
| 5270 | tmp = ((Sercom *)hw)->SPI.CTRLC.reg; |
| 5271 | tmp = (tmp & SERCOM_SPI_CTRLC_ICSPACE(mask)) >> SERCOM_SPI_CTRLC_ICSPACE_Pos; |
| 5272 | return tmp; |
| 5273 | } |
| 5274 | |
| 5275 | static inline void hri_sercomspi_write_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t data) |
| 5276 | { |
| 5277 | uint32_t tmp; |
| 5278 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5279 | tmp = ((Sercom *)hw)->SPI.CTRLC.reg; |
| 5280 | tmp &= ~SERCOM_SPI_CTRLC_ICSPACE_Msk; |
| 5281 | tmp |= SERCOM_SPI_CTRLC_ICSPACE(data); |
| 5282 | ((Sercom *)hw)->SPI.CTRLC.reg = tmp; |
| 5283 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5284 | } |
| 5285 | |
| 5286 | static inline void hri_sercomspi_clear_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) |
| 5287 | { |
| 5288 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5289 | ((Sercom *)hw)->SPI.CTRLC.reg &= ~SERCOM_SPI_CTRLC_ICSPACE(mask); |
| 5290 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5291 | } |
| 5292 | |
| 5293 | static inline void hri_sercomspi_toggle_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) |
| 5294 | { |
| 5295 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5296 | ((Sercom *)hw)->SPI.CTRLC.reg ^= SERCOM_SPI_CTRLC_ICSPACE(mask); |
| 5297 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5298 | } |
| 5299 | |
| 5300 | static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_read_CTRLC_ICSPACE_bf(const void *const hw) |
| 5301 | { |
| 5302 | uint32_t tmp; |
| 5303 | tmp = ((Sercom *)hw)->SPI.CTRLC.reg; |
| 5304 | tmp = (tmp & SERCOM_SPI_CTRLC_ICSPACE_Msk) >> SERCOM_SPI_CTRLC_ICSPACE_Pos; |
| 5305 | return tmp; |
| 5306 | } |
| 5307 | |
| 5308 | static inline void hri_sercomspi_set_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) |
| 5309 | { |
| 5310 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5311 | ((Sercom *)hw)->SPI.CTRLC.reg |= mask; |
| 5312 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5313 | } |
| 5314 | |
| 5315 | static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_get_CTRLC_reg(const void *const hw, |
| 5316 | hri_sercomspi_ctrlc_reg_t mask) |
| 5317 | { |
| 5318 | uint32_t tmp; |
| 5319 | tmp = ((Sercom *)hw)->SPI.CTRLC.reg; |
| 5320 | tmp &= mask; |
| 5321 | return tmp; |
| 5322 | } |
| 5323 | |
| 5324 | static inline void hri_sercomspi_write_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t data) |
| 5325 | { |
| 5326 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5327 | ((Sercom *)hw)->SPI.CTRLC.reg = data; |
| 5328 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5329 | } |
| 5330 | |
| 5331 | static inline void hri_sercomspi_clear_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) |
| 5332 | { |
| 5333 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5334 | ((Sercom *)hw)->SPI.CTRLC.reg &= ~mask; |
| 5335 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5336 | } |
| 5337 | |
| 5338 | static inline void hri_sercomspi_toggle_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) |
| 5339 | { |
| 5340 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5341 | ((Sercom *)hw)->SPI.CTRLC.reg ^= mask; |
| 5342 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5343 | } |
| 5344 | |
| 5345 | static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_read_CTRLC_reg(const void *const hw) |
| 5346 | { |
| 5347 | return ((Sercom *)hw)->SPI.CTRLC.reg; |
| 5348 | } |
| 5349 | |
| 5350 | static inline void hri_sercomusart_set_CTRLC_INACK_bit(const void *const hw) |
| 5351 | { |
| 5352 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5353 | ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_INACK; |
| 5354 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5355 | } |
| 5356 | |
| 5357 | static inline bool hri_sercomusart_get_CTRLC_INACK_bit(const void *const hw) |
| 5358 | { |
| 5359 | uint32_t tmp; |
| 5360 | tmp = ((Sercom *)hw)->USART.CTRLC.reg; |
| 5361 | tmp = (tmp & SERCOM_USART_CTRLC_INACK) >> SERCOM_USART_CTRLC_INACK_Pos; |
| 5362 | return (bool)tmp; |
| 5363 | } |
| 5364 | |
| 5365 | static inline void hri_sercomusart_write_CTRLC_INACK_bit(const void *const hw, bool value) |
| 5366 | { |
| 5367 | uint32_t tmp; |
| 5368 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5369 | tmp = ((Sercom *)hw)->USART.CTRLC.reg; |
| 5370 | tmp &= ~SERCOM_USART_CTRLC_INACK; |
| 5371 | tmp |= value << SERCOM_USART_CTRLC_INACK_Pos; |
| 5372 | ((Sercom *)hw)->USART.CTRLC.reg = tmp; |
| 5373 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5374 | } |
| 5375 | |
| 5376 | static inline void hri_sercomusart_clear_CTRLC_INACK_bit(const void *const hw) |
| 5377 | { |
| 5378 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5379 | ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_INACK; |
| 5380 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5381 | } |
| 5382 | |
| 5383 | static inline void hri_sercomusart_toggle_CTRLC_INACK_bit(const void *const hw) |
| 5384 | { |
| 5385 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5386 | ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_INACK; |
| 5387 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5388 | } |
| 5389 | |
| 5390 | static inline void hri_sercomusart_set_CTRLC_DSNACK_bit(const void *const hw) |
| 5391 | { |
| 5392 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5393 | ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_DSNACK; |
| 5394 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5395 | } |
| 5396 | |
| 5397 | static inline bool hri_sercomusart_get_CTRLC_DSNACK_bit(const void *const hw) |
| 5398 | { |
| 5399 | uint32_t tmp; |
| 5400 | tmp = ((Sercom *)hw)->USART.CTRLC.reg; |
| 5401 | tmp = (tmp & SERCOM_USART_CTRLC_DSNACK) >> SERCOM_USART_CTRLC_DSNACK_Pos; |
| 5402 | return (bool)tmp; |
| 5403 | } |
| 5404 | |
| 5405 | static inline void hri_sercomusart_write_CTRLC_DSNACK_bit(const void *const hw, bool value) |
| 5406 | { |
| 5407 | uint32_t tmp; |
| 5408 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5409 | tmp = ((Sercom *)hw)->USART.CTRLC.reg; |
| 5410 | tmp &= ~SERCOM_USART_CTRLC_DSNACK; |
| 5411 | tmp |= value << SERCOM_USART_CTRLC_DSNACK_Pos; |
| 5412 | ((Sercom *)hw)->USART.CTRLC.reg = tmp; |
| 5413 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5414 | } |
| 5415 | |
| 5416 | static inline void hri_sercomusart_clear_CTRLC_DSNACK_bit(const void *const hw) |
| 5417 | { |
| 5418 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5419 | ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_DSNACK; |
| 5420 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5421 | } |
| 5422 | |
| 5423 | static inline void hri_sercomusart_toggle_CTRLC_DSNACK_bit(const void *const hw) |
| 5424 | { |
| 5425 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5426 | ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_DSNACK; |
| 5427 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5428 | } |
| 5429 | |
| 5430 | static inline void hri_sercomusart_set_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) |
| 5431 | { |
| 5432 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5433 | ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(mask); |
| 5434 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5435 | } |
| 5436 | |
| 5437 | static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_GTIME_bf(const void *const hw, |
| 5438 | hri_sercomusart_ctrlc_reg_t mask) |
| 5439 | { |
| 5440 | uint32_t tmp; |
| 5441 | tmp = ((Sercom *)hw)->USART.CTRLC.reg; |
| 5442 | tmp = (tmp & SERCOM_USART_CTRLC_GTIME(mask)) >> SERCOM_USART_CTRLC_GTIME_Pos; |
| 5443 | return tmp; |
| 5444 | } |
| 5445 | |
| 5446 | static inline void hri_sercomusart_write_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) |
| 5447 | { |
| 5448 | uint32_t tmp; |
| 5449 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5450 | tmp = ((Sercom *)hw)->USART.CTRLC.reg; |
| 5451 | tmp &= ~SERCOM_USART_CTRLC_GTIME_Msk; |
| 5452 | tmp |= SERCOM_USART_CTRLC_GTIME(data); |
| 5453 | ((Sercom *)hw)->USART.CTRLC.reg = tmp; |
| 5454 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5455 | } |
| 5456 | |
| 5457 | static inline void hri_sercomusart_clear_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) |
| 5458 | { |
| 5459 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5460 | ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_GTIME(mask); |
| 5461 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5462 | } |
| 5463 | |
| 5464 | static inline void hri_sercomusart_toggle_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) |
| 5465 | { |
| 5466 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5467 | ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_GTIME(mask); |
| 5468 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5469 | } |
| 5470 | |
| 5471 | static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_GTIME_bf(const void *const hw) |
| 5472 | { |
| 5473 | uint32_t tmp; |
| 5474 | tmp = ((Sercom *)hw)->USART.CTRLC.reg; |
| 5475 | tmp = (tmp & SERCOM_USART_CTRLC_GTIME_Msk) >> SERCOM_USART_CTRLC_GTIME_Pos; |
| 5476 | return tmp; |
| 5477 | } |
| 5478 | |
| 5479 | static inline void hri_sercomusart_set_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) |
| 5480 | { |
| 5481 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5482 | ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_BRKLEN(mask); |
| 5483 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5484 | } |
| 5485 | |
| 5486 | static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_BRKLEN_bf(const void *const hw, |
| 5487 | hri_sercomusart_ctrlc_reg_t mask) |
| 5488 | { |
| 5489 | uint32_t tmp; |
| 5490 | tmp = ((Sercom *)hw)->USART.CTRLC.reg; |
| 5491 | tmp = (tmp & SERCOM_USART_CTRLC_BRKLEN(mask)) >> SERCOM_USART_CTRLC_BRKLEN_Pos; |
| 5492 | return tmp; |
| 5493 | } |
| 5494 | |
| 5495 | static inline void hri_sercomusart_write_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) |
| 5496 | { |
| 5497 | uint32_t tmp; |
| 5498 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5499 | tmp = ((Sercom *)hw)->USART.CTRLC.reg; |
| 5500 | tmp &= ~SERCOM_USART_CTRLC_BRKLEN_Msk; |
| 5501 | tmp |= SERCOM_USART_CTRLC_BRKLEN(data); |
| 5502 | ((Sercom *)hw)->USART.CTRLC.reg = tmp; |
| 5503 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5504 | } |
| 5505 | |
| 5506 | static inline void hri_sercomusart_clear_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) |
| 5507 | { |
| 5508 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5509 | ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_BRKLEN(mask); |
| 5510 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5511 | } |
| 5512 | |
| 5513 | static inline void hri_sercomusart_toggle_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) |
| 5514 | { |
| 5515 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5516 | ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_BRKLEN(mask); |
| 5517 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5518 | } |
| 5519 | |
| 5520 | static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_BRKLEN_bf(const void *const hw) |
| 5521 | { |
| 5522 | uint32_t tmp; |
| 5523 | tmp = ((Sercom *)hw)->USART.CTRLC.reg; |
| 5524 | tmp = (tmp & SERCOM_USART_CTRLC_BRKLEN_Msk) >> SERCOM_USART_CTRLC_BRKLEN_Pos; |
| 5525 | return tmp; |
| 5526 | } |
| 5527 | |
| 5528 | static inline void hri_sercomusart_set_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) |
| 5529 | { |
| 5530 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5531 | ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_HDRDLY(mask); |
| 5532 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5533 | } |
| 5534 | |
| 5535 | static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_HDRDLY_bf(const void *const hw, |
| 5536 | hri_sercomusart_ctrlc_reg_t mask) |
| 5537 | { |
| 5538 | uint32_t tmp; |
| 5539 | tmp = ((Sercom *)hw)->USART.CTRLC.reg; |
| 5540 | tmp = (tmp & SERCOM_USART_CTRLC_HDRDLY(mask)) >> SERCOM_USART_CTRLC_HDRDLY_Pos; |
| 5541 | return tmp; |
| 5542 | } |
| 5543 | |
| 5544 | static inline void hri_sercomusart_write_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) |
| 5545 | { |
| 5546 | uint32_t tmp; |
| 5547 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5548 | tmp = ((Sercom *)hw)->USART.CTRLC.reg; |
| 5549 | tmp &= ~SERCOM_USART_CTRLC_HDRDLY_Msk; |
| 5550 | tmp |= SERCOM_USART_CTRLC_HDRDLY(data); |
| 5551 | ((Sercom *)hw)->USART.CTRLC.reg = tmp; |
| 5552 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5553 | } |
| 5554 | |
| 5555 | static inline void hri_sercomusart_clear_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) |
| 5556 | { |
| 5557 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5558 | ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_HDRDLY(mask); |
| 5559 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5560 | } |
| 5561 | |
| 5562 | static inline void hri_sercomusart_toggle_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) |
| 5563 | { |
| 5564 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5565 | ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_HDRDLY(mask); |
| 5566 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5567 | } |
| 5568 | |
| 5569 | static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_HDRDLY_bf(const void *const hw) |
| 5570 | { |
| 5571 | uint32_t tmp; |
| 5572 | tmp = ((Sercom *)hw)->USART.CTRLC.reg; |
| 5573 | tmp = (tmp & SERCOM_USART_CTRLC_HDRDLY_Msk) >> SERCOM_USART_CTRLC_HDRDLY_Pos; |
| 5574 | return tmp; |
| 5575 | } |
| 5576 | |
| 5577 | static inline void hri_sercomusart_set_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) |
| 5578 | { |
| 5579 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5580 | ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_MAXITER(mask); |
| 5581 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5582 | } |
| 5583 | |
| 5584 | static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_MAXITER_bf(const void *const hw, |
| 5585 | hri_sercomusart_ctrlc_reg_t mask) |
| 5586 | { |
| 5587 | uint32_t tmp; |
| 5588 | tmp = ((Sercom *)hw)->USART.CTRLC.reg; |
| 5589 | tmp = (tmp & SERCOM_USART_CTRLC_MAXITER(mask)) >> SERCOM_USART_CTRLC_MAXITER_Pos; |
| 5590 | return tmp; |
| 5591 | } |
| 5592 | |
| 5593 | static inline void hri_sercomusart_write_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) |
| 5594 | { |
| 5595 | uint32_t tmp; |
| 5596 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5597 | tmp = ((Sercom *)hw)->USART.CTRLC.reg; |
| 5598 | tmp &= ~SERCOM_USART_CTRLC_MAXITER_Msk; |
| 5599 | tmp |= SERCOM_USART_CTRLC_MAXITER(data); |
| 5600 | ((Sercom *)hw)->USART.CTRLC.reg = tmp; |
| 5601 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5602 | } |
| 5603 | |
| 5604 | static inline void hri_sercomusart_clear_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) |
| 5605 | { |
| 5606 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5607 | ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_MAXITER(mask); |
| 5608 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5609 | } |
| 5610 | |
| 5611 | static inline void hri_sercomusart_toggle_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) |
| 5612 | { |
| 5613 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5614 | ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_MAXITER(mask); |
| 5615 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5616 | } |
| 5617 | |
| 5618 | static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_MAXITER_bf(const void *const hw) |
| 5619 | { |
| 5620 | uint32_t tmp; |
| 5621 | tmp = ((Sercom *)hw)->USART.CTRLC.reg; |
| 5622 | tmp = (tmp & SERCOM_USART_CTRLC_MAXITER_Msk) >> SERCOM_USART_CTRLC_MAXITER_Pos; |
| 5623 | return tmp; |
| 5624 | } |
| 5625 | |
| 5626 | static inline void hri_sercomusart_set_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) |
| 5627 | { |
| 5628 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5629 | ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_DATA32B(mask); |
| 5630 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5631 | } |
| 5632 | |
| 5633 | static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_DATA32B_bf(const void *const hw, |
| 5634 | hri_sercomusart_ctrlc_reg_t mask) |
| 5635 | { |
| 5636 | uint32_t tmp; |
| 5637 | tmp = ((Sercom *)hw)->USART.CTRLC.reg; |
| 5638 | tmp = (tmp & SERCOM_USART_CTRLC_DATA32B(mask)) >> SERCOM_USART_CTRLC_DATA32B_Pos; |
| 5639 | return tmp; |
| 5640 | } |
| 5641 | |
| 5642 | static inline void hri_sercomusart_write_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) |
| 5643 | { |
| 5644 | uint32_t tmp; |
| 5645 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5646 | tmp = ((Sercom *)hw)->USART.CTRLC.reg; |
| 5647 | tmp &= ~SERCOM_USART_CTRLC_DATA32B_Msk; |
| 5648 | tmp |= SERCOM_USART_CTRLC_DATA32B(data); |
| 5649 | ((Sercom *)hw)->USART.CTRLC.reg = tmp; |
| 5650 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5651 | } |
| 5652 | |
| 5653 | static inline void hri_sercomusart_clear_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) |
| 5654 | { |
| 5655 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5656 | ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_DATA32B(mask); |
| 5657 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5658 | } |
| 5659 | |
| 5660 | static inline void hri_sercomusart_toggle_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) |
| 5661 | { |
| 5662 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5663 | ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_DATA32B(mask); |
| 5664 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5665 | } |
| 5666 | |
| 5667 | static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_DATA32B_bf(const void *const hw) |
| 5668 | { |
| 5669 | uint32_t tmp; |
| 5670 | tmp = ((Sercom *)hw)->USART.CTRLC.reg; |
| 5671 | tmp = (tmp & SERCOM_USART_CTRLC_DATA32B_Msk) >> SERCOM_USART_CTRLC_DATA32B_Pos; |
| 5672 | return tmp; |
| 5673 | } |
| 5674 | |
| 5675 | static inline void hri_sercomusart_set_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) |
| 5676 | { |
| 5677 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5678 | ((Sercom *)hw)->USART.CTRLC.reg |= mask; |
| 5679 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5680 | } |
| 5681 | |
| 5682 | static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_reg(const void *const hw, |
| 5683 | hri_sercomusart_ctrlc_reg_t mask) |
| 5684 | { |
| 5685 | uint32_t tmp; |
| 5686 | tmp = ((Sercom *)hw)->USART.CTRLC.reg; |
| 5687 | tmp &= mask; |
| 5688 | return tmp; |
| 5689 | } |
| 5690 | |
| 5691 | static inline void hri_sercomusart_write_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t data) |
| 5692 | { |
| 5693 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5694 | ((Sercom *)hw)->USART.CTRLC.reg = data; |
| 5695 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5696 | } |
| 5697 | |
| 5698 | static inline void hri_sercomusart_clear_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) |
| 5699 | { |
| 5700 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5701 | ((Sercom *)hw)->USART.CTRLC.reg &= ~mask; |
| 5702 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5703 | } |
| 5704 | |
| 5705 | static inline void hri_sercomusart_toggle_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) |
| 5706 | { |
| 5707 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5708 | ((Sercom *)hw)->USART.CTRLC.reg ^= mask; |
| 5709 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5710 | } |
| 5711 | |
| 5712 | static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_reg(const void *const hw) |
| 5713 | { |
| 5714 | return ((Sercom *)hw)->USART.CTRLC.reg; |
| 5715 | } |
| 5716 | |
| 5717 | static inline void hri_sercomi2cm_set_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) |
| 5718 | { |
| 5719 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5720 | ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUD(mask); |
| 5721 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5722 | } |
| 5723 | |
| 5724 | static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUD_bf(const void *const hw, |
| 5725 | hri_sercomi2cm_baud_reg_t mask) |
| 5726 | { |
| 5727 | uint32_t tmp; |
| 5728 | tmp = ((Sercom *)hw)->I2CM.BAUD.reg; |
| 5729 | tmp = (tmp & SERCOM_I2CM_BAUD_BAUD(mask)) >> SERCOM_I2CM_BAUD_BAUD_Pos; |
| 5730 | return tmp; |
| 5731 | } |
| 5732 | |
| 5733 | static inline void hri_sercomi2cm_write_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) |
| 5734 | { |
| 5735 | uint32_t tmp; |
| 5736 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5737 | tmp = ((Sercom *)hw)->I2CM.BAUD.reg; |
| 5738 | tmp &= ~SERCOM_I2CM_BAUD_BAUD_Msk; |
| 5739 | tmp |= SERCOM_I2CM_BAUD_BAUD(data); |
| 5740 | ((Sercom *)hw)->I2CM.BAUD.reg = tmp; |
| 5741 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5742 | } |
| 5743 | |
| 5744 | static inline void hri_sercomi2cm_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) |
| 5745 | { |
| 5746 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5747 | ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUD(mask); |
| 5748 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5749 | } |
| 5750 | |
| 5751 | static inline void hri_sercomi2cm_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) |
| 5752 | { |
| 5753 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5754 | ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUD(mask); |
| 5755 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5756 | } |
| 5757 | |
| 5758 | static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUD_bf(const void *const hw) |
| 5759 | { |
| 5760 | uint32_t tmp; |
| 5761 | tmp = ((Sercom *)hw)->I2CM.BAUD.reg; |
| 5762 | tmp = (tmp & SERCOM_I2CM_BAUD_BAUD_Msk) >> SERCOM_I2CM_BAUD_BAUD_Pos; |
| 5763 | return tmp; |
| 5764 | } |
| 5765 | |
| 5766 | static inline void hri_sercomi2cm_set_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) |
| 5767 | { |
| 5768 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5769 | ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUDLOW(mask); |
| 5770 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5771 | } |
| 5772 | |
| 5773 | static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUDLOW_bf(const void *const hw, |
| 5774 | hri_sercomi2cm_baud_reg_t mask) |
| 5775 | { |
| 5776 | uint32_t tmp; |
| 5777 | tmp = ((Sercom *)hw)->I2CM.BAUD.reg; |
| 5778 | tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW(mask)) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; |
| 5779 | return tmp; |
| 5780 | } |
| 5781 | |
| 5782 | static inline void hri_sercomi2cm_write_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) |
| 5783 | { |
| 5784 | uint32_t tmp; |
| 5785 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5786 | tmp = ((Sercom *)hw)->I2CM.BAUD.reg; |
| 5787 | tmp &= ~SERCOM_I2CM_BAUD_BAUDLOW_Msk; |
| 5788 | tmp |= SERCOM_I2CM_BAUD_BAUDLOW(data); |
| 5789 | ((Sercom *)hw)->I2CM.BAUD.reg = tmp; |
| 5790 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5791 | } |
| 5792 | |
| 5793 | static inline void hri_sercomi2cm_clear_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) |
| 5794 | { |
| 5795 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5796 | ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUDLOW(mask); |
| 5797 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5798 | } |
| 5799 | |
| 5800 | static inline void hri_sercomi2cm_toggle_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) |
| 5801 | { |
| 5802 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5803 | ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUDLOW(mask); |
| 5804 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5805 | } |
| 5806 | |
| 5807 | static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUDLOW_bf(const void *const hw) |
| 5808 | { |
| 5809 | uint32_t tmp; |
| 5810 | tmp = ((Sercom *)hw)->I2CM.BAUD.reg; |
| 5811 | tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW_Msk) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; |
| 5812 | return tmp; |
| 5813 | } |
| 5814 | |
| 5815 | static inline void hri_sercomi2cm_set_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) |
| 5816 | { |
| 5817 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5818 | ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUD(mask); |
| 5819 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5820 | } |
| 5821 | |
| 5822 | static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUD_bf(const void *const hw, |
| 5823 | hri_sercomi2cm_baud_reg_t mask) |
| 5824 | { |
| 5825 | uint32_t tmp; |
| 5826 | tmp = ((Sercom *)hw)->I2CM.BAUD.reg; |
| 5827 | tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD(mask)) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; |
| 5828 | return tmp; |
| 5829 | } |
| 5830 | |
| 5831 | static inline void hri_sercomi2cm_write_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) |
| 5832 | { |
| 5833 | uint32_t tmp; |
| 5834 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5835 | tmp = ((Sercom *)hw)->I2CM.BAUD.reg; |
| 5836 | tmp &= ~SERCOM_I2CM_BAUD_HSBAUD_Msk; |
| 5837 | tmp |= SERCOM_I2CM_BAUD_HSBAUD(data); |
| 5838 | ((Sercom *)hw)->I2CM.BAUD.reg = tmp; |
| 5839 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5840 | } |
| 5841 | |
| 5842 | static inline void hri_sercomi2cm_clear_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) |
| 5843 | { |
| 5844 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5845 | ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUD(mask); |
| 5846 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5847 | } |
| 5848 | |
| 5849 | static inline void hri_sercomi2cm_toggle_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) |
| 5850 | { |
| 5851 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5852 | ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUD(mask); |
| 5853 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5854 | } |
| 5855 | |
| 5856 | static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUD_bf(const void *const hw) |
| 5857 | { |
| 5858 | uint32_t tmp; |
| 5859 | tmp = ((Sercom *)hw)->I2CM.BAUD.reg; |
| 5860 | tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD_Msk) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; |
| 5861 | return tmp; |
| 5862 | } |
| 5863 | |
| 5864 | static inline void hri_sercomi2cm_set_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) |
| 5865 | { |
| 5866 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5867 | ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); |
| 5868 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5869 | } |
| 5870 | |
| 5871 | static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUDLOW_bf(const void *const hw, |
| 5872 | hri_sercomi2cm_baud_reg_t mask) |
| 5873 | { |
| 5874 | uint32_t tmp; |
| 5875 | tmp = ((Sercom *)hw)->I2CM.BAUD.reg; |
| 5876 | tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW(mask)) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; |
| 5877 | return tmp; |
| 5878 | } |
| 5879 | |
| 5880 | static inline void hri_sercomi2cm_write_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) |
| 5881 | { |
| 5882 | uint32_t tmp; |
| 5883 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5884 | tmp = ((Sercom *)hw)->I2CM.BAUD.reg; |
| 5885 | tmp &= ~SERCOM_I2CM_BAUD_HSBAUDLOW_Msk; |
| 5886 | tmp |= SERCOM_I2CM_BAUD_HSBAUDLOW(data); |
| 5887 | ((Sercom *)hw)->I2CM.BAUD.reg = tmp; |
| 5888 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5889 | } |
| 5890 | |
| 5891 | static inline void hri_sercomi2cm_clear_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) |
| 5892 | { |
| 5893 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5894 | ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUDLOW(mask); |
| 5895 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5896 | } |
| 5897 | |
| 5898 | static inline void hri_sercomi2cm_toggle_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) |
| 5899 | { |
| 5900 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5901 | ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); |
| 5902 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5903 | } |
| 5904 | |
| 5905 | static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUDLOW_bf(const void *const hw) |
| 5906 | { |
| 5907 | uint32_t tmp; |
| 5908 | tmp = ((Sercom *)hw)->I2CM.BAUD.reg; |
| 5909 | tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW_Msk) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; |
| 5910 | return tmp; |
| 5911 | } |
| 5912 | |
| 5913 | static inline void hri_sercomi2cm_set_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) |
| 5914 | { |
| 5915 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5916 | ((Sercom *)hw)->I2CM.BAUD.reg |= mask; |
| 5917 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5918 | } |
| 5919 | |
| 5920 | static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_reg(const void *const hw, |
| 5921 | hri_sercomi2cm_baud_reg_t mask) |
| 5922 | { |
| 5923 | uint32_t tmp; |
| 5924 | tmp = ((Sercom *)hw)->I2CM.BAUD.reg; |
| 5925 | tmp &= mask; |
| 5926 | return tmp; |
| 5927 | } |
| 5928 | |
| 5929 | static inline void hri_sercomi2cm_write_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t data) |
| 5930 | { |
| 5931 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5932 | ((Sercom *)hw)->I2CM.BAUD.reg = data; |
| 5933 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5934 | } |
| 5935 | |
| 5936 | static inline void hri_sercomi2cm_clear_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) |
| 5937 | { |
| 5938 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5939 | ((Sercom *)hw)->I2CM.BAUD.reg &= ~mask; |
| 5940 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5941 | } |
| 5942 | |
| 5943 | static inline void hri_sercomi2cm_toggle_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) |
| 5944 | { |
| 5945 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5946 | ((Sercom *)hw)->I2CM.BAUD.reg ^= mask; |
| 5947 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5948 | } |
| 5949 | |
| 5950 | static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_reg(const void *const hw) |
| 5951 | { |
| 5952 | return ((Sercom *)hw)->I2CM.BAUD.reg; |
| 5953 | } |
| 5954 | |
| 5955 | static inline void hri_sercomspi_set_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) |
| 5956 | { |
| 5957 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5958 | ((Sercom *)hw)->SPI.BAUD.reg |= SERCOM_SPI_BAUD_BAUD(mask); |
| 5959 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5960 | } |
| 5961 | |
| 5962 | static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_BAUD_bf(const void *const hw, |
| 5963 | hri_sercomspi_baud_reg_t mask) |
| 5964 | { |
| 5965 | uint8_t tmp; |
| 5966 | tmp = ((Sercom *)hw)->SPI.BAUD.reg; |
| 5967 | tmp = (tmp & SERCOM_SPI_BAUD_BAUD(mask)) >> SERCOM_SPI_BAUD_BAUD_Pos; |
| 5968 | return tmp; |
| 5969 | } |
| 5970 | |
| 5971 | static inline void hri_sercomspi_write_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t data) |
| 5972 | { |
| 5973 | uint8_t tmp; |
| 5974 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5975 | tmp = ((Sercom *)hw)->SPI.BAUD.reg; |
| 5976 | tmp &= ~SERCOM_SPI_BAUD_BAUD_Msk; |
| 5977 | tmp |= SERCOM_SPI_BAUD_BAUD(data); |
| 5978 | ((Sercom *)hw)->SPI.BAUD.reg = tmp; |
| 5979 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5980 | } |
| 5981 | |
| 5982 | static inline void hri_sercomspi_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) |
| 5983 | { |
| 5984 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5985 | ((Sercom *)hw)->SPI.BAUD.reg &= ~SERCOM_SPI_BAUD_BAUD(mask); |
| 5986 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5987 | } |
| 5988 | |
| 5989 | static inline void hri_sercomspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) |
| 5990 | { |
| 5991 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 5992 | ((Sercom *)hw)->SPI.BAUD.reg ^= SERCOM_SPI_BAUD_BAUD(mask); |
| 5993 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 5994 | } |
| 5995 | |
| 5996 | static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_BAUD_bf(const void *const hw) |
| 5997 | { |
| 5998 | uint8_t tmp; |
| 5999 | tmp = ((Sercom *)hw)->SPI.BAUD.reg; |
| 6000 | tmp = (tmp & SERCOM_SPI_BAUD_BAUD_Msk) >> SERCOM_SPI_BAUD_BAUD_Pos; |
| 6001 | return tmp; |
| 6002 | } |
| 6003 | |
| 6004 | static inline void hri_sercomspi_set_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) |
| 6005 | { |
| 6006 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6007 | ((Sercom *)hw)->SPI.BAUD.reg |= mask; |
| 6008 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6009 | } |
| 6010 | |
| 6011 | static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) |
| 6012 | { |
| 6013 | uint8_t tmp; |
| 6014 | tmp = ((Sercom *)hw)->SPI.BAUD.reg; |
| 6015 | tmp &= mask; |
| 6016 | return tmp; |
| 6017 | } |
| 6018 | |
| 6019 | static inline void hri_sercomspi_write_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t data) |
| 6020 | { |
| 6021 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6022 | ((Sercom *)hw)->SPI.BAUD.reg = data; |
| 6023 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6024 | } |
| 6025 | |
| 6026 | static inline void hri_sercomspi_clear_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) |
| 6027 | { |
| 6028 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6029 | ((Sercom *)hw)->SPI.BAUD.reg &= ~mask; |
| 6030 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6031 | } |
| 6032 | |
| 6033 | static inline void hri_sercomspi_toggle_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) |
| 6034 | { |
| 6035 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6036 | ((Sercom *)hw)->SPI.BAUD.reg ^= mask; |
| 6037 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6038 | } |
| 6039 | |
| 6040 | static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_reg(const void *const hw) |
| 6041 | { |
| 6042 | return ((Sercom *)hw)->SPI.BAUD.reg; |
| 6043 | } |
| 6044 | |
| 6045 | static inline void hri_sercomusart_set_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) |
| 6046 | { |
| 6047 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6048 | ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); |
| 6049 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6050 | } |
| 6051 | |
| 6052 | static inline void hri_sercomusart_set_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) |
| 6053 | { |
| 6054 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6055 | ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); |
| 6056 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6057 | } |
| 6058 | |
| 6059 | static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_BAUD_bf(const void *const hw, |
| 6060 | hri_sercomusart_baud_reg_t mask) |
| 6061 | { |
| 6062 | uint16_t tmp; |
| 6063 | tmp = ((Sercom *)hw)->USART.BAUD.reg; |
| 6064 | tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; |
| 6065 | return tmp; |
| 6066 | } |
| 6067 | |
| 6068 | static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_BAUD_bf(const void *const hw, |
| 6069 | hri_sercomusart_baud_reg_t mask) |
| 6070 | { |
| 6071 | uint16_t tmp; |
| 6072 | tmp = ((Sercom *)hw)->USART.BAUD.reg; |
| 6073 | tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; |
| 6074 | return tmp; |
| 6075 | } |
| 6076 | |
| 6077 | static inline void hri_sercomusart_write_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) |
| 6078 | { |
| 6079 | uint16_t tmp; |
| 6080 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6081 | tmp = ((Sercom *)hw)->USART.BAUD.reg; |
| 6082 | tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; |
| 6083 | tmp |= SERCOM_USART_BAUD_BAUD(data); |
| 6084 | ((Sercom *)hw)->USART.BAUD.reg = tmp; |
| 6085 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6086 | } |
| 6087 | |
| 6088 | static inline void hri_sercomusart_write_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) |
| 6089 | { |
| 6090 | uint16_t tmp; |
| 6091 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6092 | tmp = ((Sercom *)hw)->USART.BAUD.reg; |
| 6093 | tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; |
| 6094 | tmp |= SERCOM_USART_BAUD_BAUD(data); |
| 6095 | ((Sercom *)hw)->USART.BAUD.reg = tmp; |
| 6096 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6097 | } |
| 6098 | |
| 6099 | static inline void hri_sercomusart_clear_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) |
| 6100 | { |
| 6101 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6102 | ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); |
| 6103 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6104 | } |
| 6105 | |
| 6106 | static inline void hri_sercomusart_clear_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) |
| 6107 | { |
| 6108 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6109 | ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); |
| 6110 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6111 | } |
| 6112 | |
| 6113 | static inline void hri_sercomusart_toggle_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) |
| 6114 | { |
| 6115 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6116 | ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); |
| 6117 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6118 | } |
| 6119 | |
| 6120 | static inline void hri_sercomusart_toggle_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) |
| 6121 | { |
| 6122 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6123 | ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); |
| 6124 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6125 | } |
| 6126 | |
| 6127 | static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_BAUD_bf(const void *const hw) |
| 6128 | { |
| 6129 | uint16_t tmp; |
| 6130 | tmp = ((Sercom *)hw)->USART.BAUD.reg; |
| 6131 | tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; |
| 6132 | return tmp; |
| 6133 | } |
| 6134 | |
| 6135 | static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_BAUD_bf(const void *const hw) |
| 6136 | { |
| 6137 | uint16_t tmp; |
| 6138 | tmp = ((Sercom *)hw)->USART.BAUD.reg; |
| 6139 | tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; |
| 6140 | return tmp; |
| 6141 | } |
| 6142 | |
| 6143 | static inline void hri_sercomusart_set_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) |
| 6144 | { |
| 6145 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6146 | ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_FP(mask); |
| 6147 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6148 | } |
| 6149 | |
| 6150 | static inline void hri_sercomusart_set_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) |
| 6151 | { |
| 6152 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6153 | ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_FP(mask); |
| 6154 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6155 | } |
| 6156 | |
| 6157 | static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_FP_bf(const void *const hw, |
| 6158 | hri_sercomusart_baud_reg_t mask) |
| 6159 | { |
| 6160 | uint16_t tmp; |
| 6161 | tmp = ((Sercom *)hw)->USART.BAUD.reg; |
| 6162 | tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP(mask)) >> SERCOM_USART_BAUD_FRAC_FP_Pos; |
| 6163 | return tmp; |
| 6164 | } |
| 6165 | |
| 6166 | static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_FP_bf(const void *const hw, |
| 6167 | hri_sercomusart_baud_reg_t mask) |
| 6168 | { |
| 6169 | uint16_t tmp; |
| 6170 | tmp = ((Sercom *)hw)->USART.BAUD.reg; |
| 6171 | tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP(mask)) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; |
| 6172 | return tmp; |
| 6173 | } |
| 6174 | |
| 6175 | static inline void hri_sercomusart_write_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) |
| 6176 | { |
| 6177 | uint16_t tmp; |
| 6178 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6179 | tmp = ((Sercom *)hw)->USART.BAUD.reg; |
| 6180 | tmp &= ~SERCOM_USART_BAUD_FRAC_FP_Msk; |
| 6181 | tmp |= SERCOM_USART_BAUD_FRAC_FP(data); |
| 6182 | ((Sercom *)hw)->USART.BAUD.reg = tmp; |
| 6183 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6184 | } |
| 6185 | |
| 6186 | static inline void hri_sercomusart_write_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) |
| 6187 | { |
| 6188 | uint16_t tmp; |
| 6189 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6190 | tmp = ((Sercom *)hw)->USART.BAUD.reg; |
| 6191 | tmp &= ~SERCOM_USART_BAUD_FRACFP_FP_Msk; |
| 6192 | tmp |= SERCOM_USART_BAUD_FRACFP_FP(data); |
| 6193 | ((Sercom *)hw)->USART.BAUD.reg = tmp; |
| 6194 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6195 | } |
| 6196 | |
| 6197 | static inline void hri_sercomusart_clear_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) |
| 6198 | { |
| 6199 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6200 | ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_FP(mask); |
| 6201 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6202 | } |
| 6203 | |
| 6204 | static inline void hri_sercomusart_clear_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) |
| 6205 | { |
| 6206 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6207 | ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_FP(mask); |
| 6208 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6209 | } |
| 6210 | |
| 6211 | static inline void hri_sercomusart_toggle_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) |
| 6212 | { |
| 6213 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6214 | ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_FP(mask); |
| 6215 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6216 | } |
| 6217 | |
| 6218 | static inline void hri_sercomusart_toggle_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) |
| 6219 | { |
| 6220 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6221 | ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_FP(mask); |
| 6222 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6223 | } |
| 6224 | |
| 6225 | static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_FP_bf(const void *const hw) |
| 6226 | { |
| 6227 | uint16_t tmp; |
| 6228 | tmp = ((Sercom *)hw)->USART.BAUD.reg; |
| 6229 | tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP_Msk) >> SERCOM_USART_BAUD_FRAC_FP_Pos; |
| 6230 | return tmp; |
| 6231 | } |
| 6232 | |
| 6233 | static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_FP_bf(const void *const hw) |
| 6234 | { |
| 6235 | uint16_t tmp; |
| 6236 | tmp = ((Sercom *)hw)->USART.BAUD.reg; |
| 6237 | tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP_Msk) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; |
| 6238 | return tmp; |
| 6239 | } |
| 6240 | |
| 6241 | static inline void hri_sercomusart_set_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) |
| 6242 | { |
| 6243 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6244 | ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); |
| 6245 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6246 | } |
| 6247 | |
| 6248 | static inline void hri_sercomusart_set_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) |
| 6249 | { |
| 6250 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6251 | ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); |
| 6252 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6253 | } |
| 6254 | |
| 6255 | static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_BAUD_bf(const void *const hw, |
| 6256 | hri_sercomusart_baud_reg_t mask) |
| 6257 | { |
| 6258 | uint16_t tmp; |
| 6259 | tmp = ((Sercom *)hw)->USART.BAUD.reg; |
| 6260 | tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; |
| 6261 | return tmp; |
| 6262 | } |
| 6263 | |
| 6264 | static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_BAUD_bf(const void *const hw, |
| 6265 | hri_sercomusart_baud_reg_t mask) |
| 6266 | { |
| 6267 | uint16_t tmp; |
| 6268 | tmp = ((Sercom *)hw)->USART.BAUD.reg; |
| 6269 | tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; |
| 6270 | return tmp; |
| 6271 | } |
| 6272 | |
| 6273 | static inline void hri_sercomusart_write_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) |
| 6274 | { |
| 6275 | uint16_t tmp; |
| 6276 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6277 | tmp = ((Sercom *)hw)->USART.BAUD.reg; |
| 6278 | tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; |
| 6279 | tmp |= SERCOM_USART_BAUD_BAUD(data); |
| 6280 | ((Sercom *)hw)->USART.BAUD.reg = tmp; |
| 6281 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6282 | } |
| 6283 | |
| 6284 | static inline void hri_sercomusart_write_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) |
| 6285 | { |
| 6286 | uint16_t tmp; |
| 6287 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6288 | tmp = ((Sercom *)hw)->USART.BAUD.reg; |
| 6289 | tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; |
| 6290 | tmp |= SERCOM_USART_BAUD_BAUD(data); |
| 6291 | ((Sercom *)hw)->USART.BAUD.reg = tmp; |
| 6292 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6293 | } |
| 6294 | |
| 6295 | static inline void hri_sercomusart_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) |
| 6296 | { |
| 6297 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6298 | ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); |
| 6299 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6300 | } |
| 6301 | |
| 6302 | static inline void hri_sercomusart_clear_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) |
| 6303 | { |
| 6304 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6305 | ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); |
| 6306 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6307 | } |
| 6308 | |
| 6309 | static inline void hri_sercomusart_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) |
| 6310 | { |
| 6311 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6312 | ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); |
| 6313 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6314 | } |
| 6315 | |
| 6316 | static inline void hri_sercomusart_toggle_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) |
| 6317 | { |
| 6318 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6319 | ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); |
| 6320 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6321 | } |
| 6322 | |
| 6323 | static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_BAUD_bf(const void *const hw) |
| 6324 | { |
| 6325 | uint16_t tmp; |
| 6326 | tmp = ((Sercom *)hw)->USART.BAUD.reg; |
| 6327 | tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; |
| 6328 | return tmp; |
| 6329 | } |
| 6330 | |
| 6331 | static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_BAUD_bf(const void *const hw) |
| 6332 | { |
| 6333 | uint16_t tmp; |
| 6334 | tmp = ((Sercom *)hw)->USART.BAUD.reg; |
| 6335 | tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; |
| 6336 | return tmp; |
| 6337 | } |
| 6338 | |
| 6339 | static inline void hri_sercomusart_set_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) |
| 6340 | { |
| 6341 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6342 | ((Sercom *)hw)->USART.BAUD.reg |= mask; |
| 6343 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6344 | } |
| 6345 | |
| 6346 | static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_reg(const void *const hw, |
| 6347 | hri_sercomusart_baud_reg_t mask) |
| 6348 | { |
| 6349 | uint16_t tmp; |
| 6350 | tmp = ((Sercom *)hw)->USART.BAUD.reg; |
| 6351 | tmp &= mask; |
| 6352 | return tmp; |
| 6353 | } |
| 6354 | |
| 6355 | static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data) |
| 6356 | { |
| 6357 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6358 | ((Sercom *)hw)->USART.BAUD.reg = data; |
| 6359 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6360 | } |
| 6361 | |
| 6362 | static inline void hri_sercomusart_clear_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) |
| 6363 | { |
| 6364 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6365 | ((Sercom *)hw)->USART.BAUD.reg &= ~mask; |
| 6366 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6367 | } |
| 6368 | |
| 6369 | static inline void hri_sercomusart_toggle_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) |
| 6370 | { |
| 6371 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6372 | ((Sercom *)hw)->USART.BAUD.reg ^= mask; |
| 6373 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6374 | } |
| 6375 | |
| 6376 | static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_reg(const void *const hw) |
| 6377 | { |
| 6378 | return ((Sercom *)hw)->USART.BAUD.reg; |
| 6379 | } |
| 6380 | |
| 6381 | static inline void hri_sercomusart_set_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) |
| 6382 | { |
| 6383 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6384 | ((Sercom *)hw)->USART.RXPL.reg |= SERCOM_USART_RXPL_RXPL(mask); |
| 6385 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6386 | } |
| 6387 | |
| 6388 | static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_RXPL_bf(const void *const hw, |
| 6389 | hri_sercomusart_rxpl_reg_t mask) |
| 6390 | { |
| 6391 | uint8_t tmp; |
| 6392 | tmp = ((Sercom *)hw)->USART.RXPL.reg; |
| 6393 | tmp = (tmp & SERCOM_USART_RXPL_RXPL(mask)) >> SERCOM_USART_RXPL_RXPL_Pos; |
| 6394 | return tmp; |
| 6395 | } |
| 6396 | |
| 6397 | static inline void hri_sercomusart_write_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t data) |
| 6398 | { |
| 6399 | uint8_t tmp; |
| 6400 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6401 | tmp = ((Sercom *)hw)->USART.RXPL.reg; |
| 6402 | tmp &= ~SERCOM_USART_RXPL_RXPL_Msk; |
| 6403 | tmp |= SERCOM_USART_RXPL_RXPL(data); |
| 6404 | ((Sercom *)hw)->USART.RXPL.reg = tmp; |
| 6405 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6406 | } |
| 6407 | |
| 6408 | static inline void hri_sercomusart_clear_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) |
| 6409 | { |
| 6410 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6411 | ((Sercom *)hw)->USART.RXPL.reg &= ~SERCOM_USART_RXPL_RXPL(mask); |
| 6412 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6413 | } |
| 6414 | |
| 6415 | static inline void hri_sercomusart_toggle_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) |
| 6416 | { |
| 6417 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6418 | ((Sercom *)hw)->USART.RXPL.reg ^= SERCOM_USART_RXPL_RXPL(mask); |
| 6419 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6420 | } |
| 6421 | |
| 6422 | static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_RXPL_bf(const void *const hw) |
| 6423 | { |
| 6424 | uint8_t tmp; |
| 6425 | tmp = ((Sercom *)hw)->USART.RXPL.reg; |
| 6426 | tmp = (tmp & SERCOM_USART_RXPL_RXPL_Msk) >> SERCOM_USART_RXPL_RXPL_Pos; |
| 6427 | return tmp; |
| 6428 | } |
| 6429 | |
| 6430 | static inline void hri_sercomusart_set_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) |
| 6431 | { |
| 6432 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6433 | ((Sercom *)hw)->USART.RXPL.reg |= mask; |
| 6434 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6435 | } |
| 6436 | |
| 6437 | static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_reg(const void *const hw, |
| 6438 | hri_sercomusart_rxpl_reg_t mask) |
| 6439 | { |
| 6440 | uint8_t tmp; |
| 6441 | tmp = ((Sercom *)hw)->USART.RXPL.reg; |
| 6442 | tmp &= mask; |
| 6443 | return tmp; |
| 6444 | } |
| 6445 | |
| 6446 | static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data) |
| 6447 | { |
| 6448 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6449 | ((Sercom *)hw)->USART.RXPL.reg = data; |
| 6450 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6451 | } |
| 6452 | |
| 6453 | static inline void hri_sercomusart_clear_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) |
| 6454 | { |
| 6455 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6456 | ((Sercom *)hw)->USART.RXPL.reg &= ~mask; |
| 6457 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6458 | } |
| 6459 | |
| 6460 | static inline void hri_sercomusart_toggle_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) |
| 6461 | { |
| 6462 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6463 | ((Sercom *)hw)->USART.RXPL.reg ^= mask; |
| 6464 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6465 | } |
| 6466 | |
| 6467 | static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_reg(const void *const hw) |
| 6468 | { |
| 6469 | return ((Sercom *)hw)->USART.RXPL.reg; |
| 6470 | } |
| 6471 | |
| 6472 | static inline void hri_sercomi2cs_set_LENGTH_LENEN_bit(const void *const hw) |
| 6473 | { |
| 6474 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6475 | ((Sercom *)hw)->I2CS.LENGTH.reg |= SERCOM_I2CS_LENGTH_LENEN; |
| 6476 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 6477 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6478 | } |
| 6479 | |
| 6480 | static inline bool hri_sercomi2cs_get_LENGTH_LENEN_bit(const void *const hw) |
| 6481 | { |
| 6482 | uint16_t tmp; |
| 6483 | tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; |
| 6484 | tmp = (tmp & SERCOM_I2CS_LENGTH_LENEN) >> SERCOM_I2CS_LENGTH_LENEN_Pos; |
| 6485 | return (bool)tmp; |
| 6486 | } |
| 6487 | |
| 6488 | static inline void hri_sercomi2cs_write_LENGTH_LENEN_bit(const void *const hw, bool value) |
| 6489 | { |
| 6490 | uint16_t tmp; |
| 6491 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6492 | tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; |
| 6493 | tmp &= ~SERCOM_I2CS_LENGTH_LENEN; |
| 6494 | tmp |= value << SERCOM_I2CS_LENGTH_LENEN_Pos; |
| 6495 | ((Sercom *)hw)->I2CS.LENGTH.reg = tmp; |
| 6496 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 6497 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6498 | } |
| 6499 | |
| 6500 | static inline void hri_sercomi2cs_clear_LENGTH_LENEN_bit(const void *const hw) |
| 6501 | { |
| 6502 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6503 | ((Sercom *)hw)->I2CS.LENGTH.reg &= ~SERCOM_I2CS_LENGTH_LENEN; |
| 6504 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 6505 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6506 | } |
| 6507 | |
| 6508 | static inline void hri_sercomi2cs_toggle_LENGTH_LENEN_bit(const void *const hw) |
| 6509 | { |
| 6510 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6511 | ((Sercom *)hw)->I2CS.LENGTH.reg ^= SERCOM_I2CS_LENGTH_LENEN; |
| 6512 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 6513 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6514 | } |
| 6515 | |
| 6516 | static inline void hri_sercomi2cs_set_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask) |
| 6517 | { |
| 6518 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6519 | ((Sercom *)hw)->I2CS.LENGTH.reg |= SERCOM_I2CS_LENGTH_LEN(mask); |
| 6520 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 6521 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6522 | } |
| 6523 | |
| 6524 | static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_get_LENGTH_LEN_bf(const void *const hw, |
| 6525 | hri_sercomi2cs_length_reg_t mask) |
| 6526 | { |
| 6527 | uint16_t tmp; |
| 6528 | tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; |
| 6529 | tmp = (tmp & SERCOM_I2CS_LENGTH_LEN(mask)) >> SERCOM_I2CS_LENGTH_LEN_Pos; |
| 6530 | return tmp; |
| 6531 | } |
| 6532 | |
| 6533 | static inline void hri_sercomi2cs_write_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t data) |
| 6534 | { |
| 6535 | uint16_t tmp; |
| 6536 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6537 | tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; |
| 6538 | tmp &= ~SERCOM_I2CS_LENGTH_LEN_Msk; |
| 6539 | tmp |= SERCOM_I2CS_LENGTH_LEN(data); |
| 6540 | ((Sercom *)hw)->I2CS.LENGTH.reg = tmp; |
| 6541 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 6542 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6543 | } |
| 6544 | |
| 6545 | static inline void hri_sercomi2cs_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask) |
| 6546 | { |
| 6547 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6548 | ((Sercom *)hw)->I2CS.LENGTH.reg &= ~SERCOM_I2CS_LENGTH_LEN(mask); |
| 6549 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 6550 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6551 | } |
| 6552 | |
| 6553 | static inline void hri_sercomi2cs_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask) |
| 6554 | { |
| 6555 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6556 | ((Sercom *)hw)->I2CS.LENGTH.reg ^= SERCOM_I2CS_LENGTH_LEN(mask); |
| 6557 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 6558 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6559 | } |
| 6560 | |
| 6561 | static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_read_LENGTH_LEN_bf(const void *const hw) |
| 6562 | { |
| 6563 | uint16_t tmp; |
| 6564 | tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; |
| 6565 | tmp = (tmp & SERCOM_I2CS_LENGTH_LEN_Msk) >> SERCOM_I2CS_LENGTH_LEN_Pos; |
| 6566 | return tmp; |
| 6567 | } |
| 6568 | |
| 6569 | static inline void hri_sercomi2cs_set_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask) |
| 6570 | { |
| 6571 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6572 | ((Sercom *)hw)->I2CS.LENGTH.reg |= mask; |
| 6573 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 6574 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6575 | } |
| 6576 | |
| 6577 | static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_get_LENGTH_reg(const void *const hw, |
| 6578 | hri_sercomi2cs_length_reg_t mask) |
| 6579 | { |
| 6580 | uint16_t tmp; |
| 6581 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 6582 | tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; |
| 6583 | tmp &= mask; |
| 6584 | return tmp; |
| 6585 | } |
| 6586 | |
| 6587 | static inline void hri_sercomi2cs_write_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t data) |
| 6588 | { |
| 6589 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6590 | ((Sercom *)hw)->I2CS.LENGTH.reg = data; |
| 6591 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 6592 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6593 | } |
| 6594 | |
| 6595 | static inline void hri_sercomi2cs_clear_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask) |
| 6596 | { |
| 6597 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6598 | ((Sercom *)hw)->I2CS.LENGTH.reg &= ~mask; |
| 6599 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 6600 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6601 | } |
| 6602 | |
| 6603 | static inline void hri_sercomi2cs_toggle_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask) |
| 6604 | { |
| 6605 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6606 | ((Sercom *)hw)->I2CS.LENGTH.reg ^= mask; |
| 6607 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 6608 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6609 | } |
| 6610 | |
| 6611 | static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_read_LENGTH_reg(const void *const hw) |
| 6612 | { |
| 6613 | hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); |
| 6614 | return ((Sercom *)hw)->I2CS.LENGTH.reg; |
| 6615 | } |
| 6616 | |
| 6617 | static inline void hri_sercomspi_set_LENGTH_LENEN_bit(const void *const hw) |
| 6618 | { |
| 6619 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6620 | ((Sercom *)hw)->SPI.LENGTH.reg |= SERCOM_SPI_LENGTH_LENEN; |
| 6621 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 6622 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6623 | } |
| 6624 | |
| 6625 | static inline bool hri_sercomspi_get_LENGTH_LENEN_bit(const void *const hw) |
| 6626 | { |
| 6627 | uint16_t tmp; |
| 6628 | tmp = ((Sercom *)hw)->SPI.LENGTH.reg; |
| 6629 | tmp = (tmp & SERCOM_SPI_LENGTH_LENEN) >> SERCOM_SPI_LENGTH_LENEN_Pos; |
| 6630 | return (bool)tmp; |
| 6631 | } |
| 6632 | |
| 6633 | static inline void hri_sercomspi_write_LENGTH_LENEN_bit(const void *const hw, bool value) |
| 6634 | { |
| 6635 | uint16_t tmp; |
| 6636 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6637 | tmp = ((Sercom *)hw)->SPI.LENGTH.reg; |
| 6638 | tmp &= ~SERCOM_SPI_LENGTH_LENEN; |
| 6639 | tmp |= value << SERCOM_SPI_LENGTH_LENEN_Pos; |
| 6640 | ((Sercom *)hw)->SPI.LENGTH.reg = tmp; |
| 6641 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 6642 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6643 | } |
| 6644 | |
| 6645 | static inline void hri_sercomspi_clear_LENGTH_LENEN_bit(const void *const hw) |
| 6646 | { |
| 6647 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6648 | ((Sercom *)hw)->SPI.LENGTH.reg &= ~SERCOM_SPI_LENGTH_LENEN; |
| 6649 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 6650 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6651 | } |
| 6652 | |
| 6653 | static inline void hri_sercomspi_toggle_LENGTH_LENEN_bit(const void *const hw) |
| 6654 | { |
| 6655 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6656 | ((Sercom *)hw)->SPI.LENGTH.reg ^= SERCOM_SPI_LENGTH_LENEN; |
| 6657 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 6658 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6659 | } |
| 6660 | |
| 6661 | static inline void hri_sercomspi_set_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask) |
| 6662 | { |
| 6663 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6664 | ((Sercom *)hw)->SPI.LENGTH.reg |= SERCOM_SPI_LENGTH_LEN(mask); |
| 6665 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 6666 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6667 | } |
| 6668 | |
| 6669 | static inline hri_sercomspi_length_reg_t hri_sercomspi_get_LENGTH_LEN_bf(const void *const hw, |
| 6670 | hri_sercomspi_length_reg_t mask) |
| 6671 | { |
| 6672 | uint16_t tmp; |
| 6673 | tmp = ((Sercom *)hw)->SPI.LENGTH.reg; |
| 6674 | tmp = (tmp & SERCOM_SPI_LENGTH_LEN(mask)) >> SERCOM_SPI_LENGTH_LEN_Pos; |
| 6675 | return tmp; |
| 6676 | } |
| 6677 | |
| 6678 | static inline void hri_sercomspi_write_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t data) |
| 6679 | { |
| 6680 | uint16_t tmp; |
| 6681 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6682 | tmp = ((Sercom *)hw)->SPI.LENGTH.reg; |
| 6683 | tmp &= ~SERCOM_SPI_LENGTH_LEN_Msk; |
| 6684 | tmp |= SERCOM_SPI_LENGTH_LEN(data); |
| 6685 | ((Sercom *)hw)->SPI.LENGTH.reg = tmp; |
| 6686 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 6687 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6688 | } |
| 6689 | |
| 6690 | static inline void hri_sercomspi_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask) |
| 6691 | { |
| 6692 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6693 | ((Sercom *)hw)->SPI.LENGTH.reg &= ~SERCOM_SPI_LENGTH_LEN(mask); |
| 6694 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 6695 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6696 | } |
| 6697 | |
| 6698 | static inline void hri_sercomspi_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask) |
| 6699 | { |
| 6700 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6701 | ((Sercom *)hw)->SPI.LENGTH.reg ^= SERCOM_SPI_LENGTH_LEN(mask); |
| 6702 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 6703 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6704 | } |
| 6705 | |
| 6706 | static inline hri_sercomspi_length_reg_t hri_sercomspi_read_LENGTH_LEN_bf(const void *const hw) |
| 6707 | { |
| 6708 | uint16_t tmp; |
| 6709 | tmp = ((Sercom *)hw)->SPI.LENGTH.reg; |
| 6710 | tmp = (tmp & SERCOM_SPI_LENGTH_LEN_Msk) >> SERCOM_SPI_LENGTH_LEN_Pos; |
| 6711 | return tmp; |
| 6712 | } |
| 6713 | |
| 6714 | static inline void hri_sercomspi_set_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask) |
| 6715 | { |
| 6716 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6717 | ((Sercom *)hw)->SPI.LENGTH.reg |= mask; |
| 6718 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 6719 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6720 | } |
| 6721 | |
| 6722 | static inline hri_sercomspi_length_reg_t hri_sercomspi_get_LENGTH_reg(const void *const hw, |
| 6723 | hri_sercomspi_length_reg_t mask) |
| 6724 | { |
| 6725 | uint16_t tmp; |
| 6726 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 6727 | tmp = ((Sercom *)hw)->SPI.LENGTH.reg; |
| 6728 | tmp &= mask; |
| 6729 | return tmp; |
| 6730 | } |
| 6731 | |
| 6732 | static inline void hri_sercomspi_write_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t data) |
| 6733 | { |
| 6734 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6735 | ((Sercom *)hw)->SPI.LENGTH.reg = data; |
| 6736 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 6737 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6738 | } |
| 6739 | |
| 6740 | static inline void hri_sercomspi_clear_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask) |
| 6741 | { |
| 6742 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6743 | ((Sercom *)hw)->SPI.LENGTH.reg &= ~mask; |
| 6744 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 6745 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6746 | } |
| 6747 | |
| 6748 | static inline void hri_sercomspi_toggle_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask) |
| 6749 | { |
| 6750 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6751 | ((Sercom *)hw)->SPI.LENGTH.reg ^= mask; |
| 6752 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 6753 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6754 | } |
| 6755 | |
| 6756 | static inline hri_sercomspi_length_reg_t hri_sercomspi_read_LENGTH_reg(const void *const hw) |
| 6757 | { |
| 6758 | hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); |
| 6759 | return ((Sercom *)hw)->SPI.LENGTH.reg; |
| 6760 | } |
| 6761 | |
| 6762 | static inline void hri_sercomusart_set_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) |
| 6763 | { |
| 6764 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6765 | ((Sercom *)hw)->USART.LENGTH.reg |= SERCOM_USART_LENGTH_LEN(mask); |
| 6766 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 6767 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6768 | } |
| 6769 | |
| 6770 | static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_LEN_bf(const void *const hw, |
| 6771 | hri_sercomusart_length_reg_t mask) |
| 6772 | { |
| 6773 | uint16_t tmp; |
| 6774 | tmp = ((Sercom *)hw)->USART.LENGTH.reg; |
| 6775 | tmp = (tmp & SERCOM_USART_LENGTH_LEN(mask)) >> SERCOM_USART_LENGTH_LEN_Pos; |
| 6776 | return tmp; |
| 6777 | } |
| 6778 | |
| 6779 | static inline void hri_sercomusart_write_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t data) |
| 6780 | { |
| 6781 | uint16_t tmp; |
| 6782 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6783 | tmp = ((Sercom *)hw)->USART.LENGTH.reg; |
| 6784 | tmp &= ~SERCOM_USART_LENGTH_LEN_Msk; |
| 6785 | tmp |= SERCOM_USART_LENGTH_LEN(data); |
| 6786 | ((Sercom *)hw)->USART.LENGTH.reg = tmp; |
| 6787 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 6788 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6789 | } |
| 6790 | |
| 6791 | static inline void hri_sercomusart_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) |
| 6792 | { |
| 6793 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6794 | ((Sercom *)hw)->USART.LENGTH.reg &= ~SERCOM_USART_LENGTH_LEN(mask); |
| 6795 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 6796 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6797 | } |
| 6798 | |
| 6799 | static inline void hri_sercomusart_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) |
| 6800 | { |
| 6801 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6802 | ((Sercom *)hw)->USART.LENGTH.reg ^= SERCOM_USART_LENGTH_LEN(mask); |
| 6803 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 6804 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6805 | } |
| 6806 | |
| 6807 | static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_LEN_bf(const void *const hw) |
| 6808 | { |
| 6809 | uint16_t tmp; |
| 6810 | tmp = ((Sercom *)hw)->USART.LENGTH.reg; |
| 6811 | tmp = (tmp & SERCOM_USART_LENGTH_LEN_Msk) >> SERCOM_USART_LENGTH_LEN_Pos; |
| 6812 | return tmp; |
| 6813 | } |
| 6814 | |
| 6815 | static inline void hri_sercomusart_set_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) |
| 6816 | { |
| 6817 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6818 | ((Sercom *)hw)->USART.LENGTH.reg |= SERCOM_USART_LENGTH_LENEN(mask); |
| 6819 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 6820 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6821 | } |
| 6822 | |
| 6823 | static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_LENEN_bf(const void *const hw, |
| 6824 | hri_sercomusart_length_reg_t mask) |
| 6825 | { |
| 6826 | uint16_t tmp; |
| 6827 | tmp = ((Sercom *)hw)->USART.LENGTH.reg; |
| 6828 | tmp = (tmp & SERCOM_USART_LENGTH_LENEN(mask)) >> SERCOM_USART_LENGTH_LENEN_Pos; |
| 6829 | return tmp; |
| 6830 | } |
| 6831 | |
| 6832 | static inline void hri_sercomusart_write_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t data) |
| 6833 | { |
| 6834 | uint16_t tmp; |
| 6835 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6836 | tmp = ((Sercom *)hw)->USART.LENGTH.reg; |
| 6837 | tmp &= ~SERCOM_USART_LENGTH_LENEN_Msk; |
| 6838 | tmp |= SERCOM_USART_LENGTH_LENEN(data); |
| 6839 | ((Sercom *)hw)->USART.LENGTH.reg = tmp; |
| 6840 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 6841 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6842 | } |
| 6843 | |
| 6844 | static inline void hri_sercomusart_clear_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) |
| 6845 | { |
| 6846 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6847 | ((Sercom *)hw)->USART.LENGTH.reg &= ~SERCOM_USART_LENGTH_LENEN(mask); |
| 6848 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 6849 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6850 | } |
| 6851 | |
| 6852 | static inline void hri_sercomusart_toggle_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) |
| 6853 | { |
| 6854 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6855 | ((Sercom *)hw)->USART.LENGTH.reg ^= SERCOM_USART_LENGTH_LENEN(mask); |
| 6856 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 6857 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6858 | } |
| 6859 | |
| 6860 | static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_LENEN_bf(const void *const hw) |
| 6861 | { |
| 6862 | uint16_t tmp; |
| 6863 | tmp = ((Sercom *)hw)->USART.LENGTH.reg; |
| 6864 | tmp = (tmp & SERCOM_USART_LENGTH_LENEN_Msk) >> SERCOM_USART_LENGTH_LENEN_Pos; |
| 6865 | return tmp; |
| 6866 | } |
| 6867 | |
| 6868 | static inline void hri_sercomusart_set_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask) |
| 6869 | { |
| 6870 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6871 | ((Sercom *)hw)->USART.LENGTH.reg |= mask; |
| 6872 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 6873 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6874 | } |
| 6875 | |
| 6876 | static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_reg(const void *const hw, |
| 6877 | hri_sercomusart_length_reg_t mask) |
| 6878 | { |
| 6879 | uint16_t tmp; |
| 6880 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 6881 | tmp = ((Sercom *)hw)->USART.LENGTH.reg; |
| 6882 | tmp &= mask; |
| 6883 | return tmp; |
| 6884 | } |
| 6885 | |
| 6886 | static inline void hri_sercomusart_write_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t data) |
| 6887 | { |
| 6888 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6889 | ((Sercom *)hw)->USART.LENGTH.reg = data; |
| 6890 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 6891 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6892 | } |
| 6893 | |
| 6894 | static inline void hri_sercomusart_clear_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask) |
| 6895 | { |
| 6896 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6897 | ((Sercom *)hw)->USART.LENGTH.reg &= ~mask; |
| 6898 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 6899 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6900 | } |
| 6901 | |
| 6902 | static inline void hri_sercomusart_toggle_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask) |
| 6903 | { |
| 6904 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6905 | ((Sercom *)hw)->USART.LENGTH.reg ^= mask; |
| 6906 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 6907 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6908 | } |
| 6909 | |
| 6910 | static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_reg(const void *const hw) |
| 6911 | { |
| 6912 | hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); |
| 6913 | return ((Sercom *)hw)->USART.LENGTH.reg; |
| 6914 | } |
| 6915 | |
| 6916 | static inline void hri_sercomi2cm_set_ADDR_LENEN_bit(const void *const hw) |
| 6917 | { |
| 6918 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6919 | ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LENEN; |
| 6920 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 6921 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6922 | } |
| 6923 | |
| 6924 | static inline bool hri_sercomi2cm_get_ADDR_LENEN_bit(const void *const hw) |
| 6925 | { |
| 6926 | uint32_t tmp; |
| 6927 | tmp = ((Sercom *)hw)->I2CM.ADDR.reg; |
| 6928 | tmp = (tmp & SERCOM_I2CM_ADDR_LENEN) >> SERCOM_I2CM_ADDR_LENEN_Pos; |
| 6929 | return (bool)tmp; |
| 6930 | } |
| 6931 | |
| 6932 | static inline void hri_sercomi2cm_write_ADDR_LENEN_bit(const void *const hw, bool value) |
| 6933 | { |
| 6934 | uint32_t tmp; |
| 6935 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6936 | tmp = ((Sercom *)hw)->I2CM.ADDR.reg; |
| 6937 | tmp &= ~SERCOM_I2CM_ADDR_LENEN; |
| 6938 | tmp |= value << SERCOM_I2CM_ADDR_LENEN_Pos; |
| 6939 | ((Sercom *)hw)->I2CM.ADDR.reg = tmp; |
| 6940 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 6941 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6942 | } |
| 6943 | |
| 6944 | static inline void hri_sercomi2cm_clear_ADDR_LENEN_bit(const void *const hw) |
| 6945 | { |
| 6946 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6947 | ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LENEN; |
| 6948 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 6949 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6950 | } |
| 6951 | |
| 6952 | static inline void hri_sercomi2cm_toggle_ADDR_LENEN_bit(const void *const hw) |
| 6953 | { |
| 6954 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6955 | ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LENEN; |
| 6956 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 6957 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6958 | } |
| 6959 | |
| 6960 | static inline void hri_sercomi2cm_set_ADDR_HS_bit(const void *const hw) |
| 6961 | { |
| 6962 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6963 | ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_HS; |
| 6964 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 6965 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6966 | } |
| 6967 | |
| 6968 | static inline bool hri_sercomi2cm_get_ADDR_HS_bit(const void *const hw) |
| 6969 | { |
| 6970 | uint32_t tmp; |
| 6971 | tmp = ((Sercom *)hw)->I2CM.ADDR.reg; |
| 6972 | tmp = (tmp & SERCOM_I2CM_ADDR_HS) >> SERCOM_I2CM_ADDR_HS_Pos; |
| 6973 | return (bool)tmp; |
| 6974 | } |
| 6975 | |
| 6976 | static inline void hri_sercomi2cm_write_ADDR_HS_bit(const void *const hw, bool value) |
| 6977 | { |
| 6978 | uint32_t tmp; |
| 6979 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6980 | tmp = ((Sercom *)hw)->I2CM.ADDR.reg; |
| 6981 | tmp &= ~SERCOM_I2CM_ADDR_HS; |
| 6982 | tmp |= value << SERCOM_I2CM_ADDR_HS_Pos; |
| 6983 | ((Sercom *)hw)->I2CM.ADDR.reg = tmp; |
| 6984 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 6985 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6986 | } |
| 6987 | |
| 6988 | static inline void hri_sercomi2cm_clear_ADDR_HS_bit(const void *const hw) |
| 6989 | { |
| 6990 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6991 | ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_HS; |
| 6992 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 6993 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 6994 | } |
| 6995 | |
| 6996 | static inline void hri_sercomi2cm_toggle_ADDR_HS_bit(const void *const hw) |
| 6997 | { |
| 6998 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 6999 | ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_HS; |
| 7000 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7001 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7002 | } |
| 7003 | |
| 7004 | static inline void hri_sercomi2cm_set_ADDR_TENBITEN_bit(const void *const hw) |
| 7005 | { |
| 7006 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7007 | ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_TENBITEN; |
| 7008 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7009 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7010 | } |
| 7011 | |
| 7012 | static inline bool hri_sercomi2cm_get_ADDR_TENBITEN_bit(const void *const hw) |
| 7013 | { |
| 7014 | uint32_t tmp; |
| 7015 | tmp = ((Sercom *)hw)->I2CM.ADDR.reg; |
| 7016 | tmp = (tmp & SERCOM_I2CM_ADDR_TENBITEN) >> SERCOM_I2CM_ADDR_TENBITEN_Pos; |
| 7017 | return (bool)tmp; |
| 7018 | } |
| 7019 | |
| 7020 | static inline void hri_sercomi2cm_write_ADDR_TENBITEN_bit(const void *const hw, bool value) |
| 7021 | { |
| 7022 | uint32_t tmp; |
| 7023 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7024 | tmp = ((Sercom *)hw)->I2CM.ADDR.reg; |
| 7025 | tmp &= ~SERCOM_I2CM_ADDR_TENBITEN; |
| 7026 | tmp |= value << SERCOM_I2CM_ADDR_TENBITEN_Pos; |
| 7027 | ((Sercom *)hw)->I2CM.ADDR.reg = tmp; |
| 7028 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7029 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7030 | } |
| 7031 | |
| 7032 | static inline void hri_sercomi2cm_clear_ADDR_TENBITEN_bit(const void *const hw) |
| 7033 | { |
| 7034 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7035 | ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_TENBITEN; |
| 7036 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7037 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7038 | } |
| 7039 | |
| 7040 | static inline void hri_sercomi2cm_toggle_ADDR_TENBITEN_bit(const void *const hw) |
| 7041 | { |
| 7042 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7043 | ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_TENBITEN; |
| 7044 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7045 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7046 | } |
| 7047 | |
| 7048 | static inline void hri_sercomi2cm_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) |
| 7049 | { |
| 7050 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7051 | ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_ADDR(mask); |
| 7052 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7053 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7054 | } |
| 7055 | |
| 7056 | static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_ADDR_bf(const void *const hw, |
| 7057 | hri_sercomi2cm_addr_reg_t mask) |
| 7058 | { |
| 7059 | uint32_t tmp; |
| 7060 | tmp = ((Sercom *)hw)->I2CM.ADDR.reg; |
| 7061 | tmp = (tmp & SERCOM_I2CM_ADDR_ADDR(mask)) >> SERCOM_I2CM_ADDR_ADDR_Pos; |
| 7062 | return tmp; |
| 7063 | } |
| 7064 | |
| 7065 | static inline void hri_sercomi2cm_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) |
| 7066 | { |
| 7067 | uint32_t tmp; |
| 7068 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7069 | tmp = ((Sercom *)hw)->I2CM.ADDR.reg; |
| 7070 | tmp &= ~SERCOM_I2CM_ADDR_ADDR_Msk; |
| 7071 | tmp |= SERCOM_I2CM_ADDR_ADDR(data); |
| 7072 | ((Sercom *)hw)->I2CM.ADDR.reg = tmp; |
| 7073 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7074 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7075 | } |
| 7076 | |
| 7077 | static inline void hri_sercomi2cm_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) |
| 7078 | { |
| 7079 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7080 | ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_ADDR(mask); |
| 7081 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7082 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7083 | } |
| 7084 | |
| 7085 | static inline void hri_sercomi2cm_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) |
| 7086 | { |
| 7087 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7088 | ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_ADDR(mask); |
| 7089 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7090 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7091 | } |
| 7092 | |
| 7093 | static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_ADDR_bf(const void *const hw) |
| 7094 | { |
| 7095 | uint32_t tmp; |
| 7096 | tmp = ((Sercom *)hw)->I2CM.ADDR.reg; |
| 7097 | tmp = (tmp & SERCOM_I2CM_ADDR_ADDR_Msk) >> SERCOM_I2CM_ADDR_ADDR_Pos; |
| 7098 | return tmp; |
| 7099 | } |
| 7100 | |
| 7101 | static inline void hri_sercomi2cm_set_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) |
| 7102 | { |
| 7103 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7104 | ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LEN(mask); |
| 7105 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7106 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7107 | } |
| 7108 | |
| 7109 | static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_LEN_bf(const void *const hw, |
| 7110 | hri_sercomi2cm_addr_reg_t mask) |
| 7111 | { |
| 7112 | uint32_t tmp; |
| 7113 | tmp = ((Sercom *)hw)->I2CM.ADDR.reg; |
| 7114 | tmp = (tmp & SERCOM_I2CM_ADDR_LEN(mask)) >> SERCOM_I2CM_ADDR_LEN_Pos; |
| 7115 | return tmp; |
| 7116 | } |
| 7117 | |
| 7118 | static inline void hri_sercomi2cm_write_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) |
| 7119 | { |
| 7120 | uint32_t tmp; |
| 7121 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7122 | tmp = ((Sercom *)hw)->I2CM.ADDR.reg; |
| 7123 | tmp &= ~SERCOM_I2CM_ADDR_LEN_Msk; |
| 7124 | tmp |= SERCOM_I2CM_ADDR_LEN(data); |
| 7125 | ((Sercom *)hw)->I2CM.ADDR.reg = tmp; |
| 7126 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7127 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7128 | } |
| 7129 | |
| 7130 | static inline void hri_sercomi2cm_clear_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) |
| 7131 | { |
| 7132 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7133 | ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LEN(mask); |
| 7134 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7135 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7136 | } |
| 7137 | |
| 7138 | static inline void hri_sercomi2cm_toggle_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) |
| 7139 | { |
| 7140 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7141 | ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LEN(mask); |
| 7142 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7143 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7144 | } |
| 7145 | |
| 7146 | static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_LEN_bf(const void *const hw) |
| 7147 | { |
| 7148 | uint32_t tmp; |
| 7149 | tmp = ((Sercom *)hw)->I2CM.ADDR.reg; |
| 7150 | tmp = (tmp & SERCOM_I2CM_ADDR_LEN_Msk) >> SERCOM_I2CM_ADDR_LEN_Pos; |
| 7151 | return tmp; |
| 7152 | } |
| 7153 | |
| 7154 | static inline void hri_sercomi2cm_set_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) |
| 7155 | { |
| 7156 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7157 | ((Sercom *)hw)->I2CM.ADDR.reg |= mask; |
| 7158 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7159 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7160 | } |
| 7161 | |
| 7162 | static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_reg(const void *const hw, |
| 7163 | hri_sercomi2cm_addr_reg_t mask) |
| 7164 | { |
| 7165 | uint32_t tmp; |
| 7166 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7167 | tmp = ((Sercom *)hw)->I2CM.ADDR.reg; |
| 7168 | tmp &= mask; |
| 7169 | return tmp; |
| 7170 | } |
| 7171 | |
| 7172 | static inline void hri_sercomi2cm_write_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t data) |
| 7173 | { |
| 7174 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7175 | ((Sercom *)hw)->I2CM.ADDR.reg = data; |
| 7176 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7177 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7178 | } |
| 7179 | |
| 7180 | static inline void hri_sercomi2cm_clear_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) |
| 7181 | { |
| 7182 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7183 | ((Sercom *)hw)->I2CM.ADDR.reg &= ~mask; |
| 7184 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7185 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7186 | } |
| 7187 | |
| 7188 | static inline void hri_sercomi2cm_toggle_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) |
| 7189 | { |
| 7190 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7191 | ((Sercom *)hw)->I2CM.ADDR.reg ^= mask; |
| 7192 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7193 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7194 | } |
| 7195 | |
| 7196 | static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_reg(const void *const hw) |
| 7197 | { |
| 7198 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7199 | return ((Sercom *)hw)->I2CM.ADDR.reg; |
| 7200 | } |
| 7201 | |
| 7202 | static inline void hri_sercomi2cs_set_ADDR_GENCEN_bit(const void *const hw) |
| 7203 | { |
| 7204 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7205 | ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_GENCEN; |
| 7206 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7207 | } |
| 7208 | |
| 7209 | static inline bool hri_sercomi2cs_get_ADDR_GENCEN_bit(const void *const hw) |
| 7210 | { |
| 7211 | uint32_t tmp; |
| 7212 | tmp = ((Sercom *)hw)->I2CS.ADDR.reg; |
| 7213 | tmp = (tmp & SERCOM_I2CS_ADDR_GENCEN) >> SERCOM_I2CS_ADDR_GENCEN_Pos; |
| 7214 | return (bool)tmp; |
| 7215 | } |
| 7216 | |
| 7217 | static inline void hri_sercomi2cs_write_ADDR_GENCEN_bit(const void *const hw, bool value) |
| 7218 | { |
| 7219 | uint32_t tmp; |
| 7220 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7221 | tmp = ((Sercom *)hw)->I2CS.ADDR.reg; |
| 7222 | tmp &= ~SERCOM_I2CS_ADDR_GENCEN; |
| 7223 | tmp |= value << SERCOM_I2CS_ADDR_GENCEN_Pos; |
| 7224 | ((Sercom *)hw)->I2CS.ADDR.reg = tmp; |
| 7225 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7226 | } |
| 7227 | |
| 7228 | static inline void hri_sercomi2cs_clear_ADDR_GENCEN_bit(const void *const hw) |
| 7229 | { |
| 7230 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7231 | ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_GENCEN; |
| 7232 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7233 | } |
| 7234 | |
| 7235 | static inline void hri_sercomi2cs_toggle_ADDR_GENCEN_bit(const void *const hw) |
| 7236 | { |
| 7237 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7238 | ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_GENCEN; |
| 7239 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7240 | } |
| 7241 | |
| 7242 | static inline void hri_sercomi2cs_set_ADDR_TENBITEN_bit(const void *const hw) |
| 7243 | { |
| 7244 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7245 | ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_TENBITEN; |
| 7246 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7247 | } |
| 7248 | |
| 7249 | static inline bool hri_sercomi2cs_get_ADDR_TENBITEN_bit(const void *const hw) |
| 7250 | { |
| 7251 | uint32_t tmp; |
| 7252 | tmp = ((Sercom *)hw)->I2CS.ADDR.reg; |
| 7253 | tmp = (tmp & SERCOM_I2CS_ADDR_TENBITEN) >> SERCOM_I2CS_ADDR_TENBITEN_Pos; |
| 7254 | return (bool)tmp; |
| 7255 | } |
| 7256 | |
| 7257 | static inline void hri_sercomi2cs_write_ADDR_TENBITEN_bit(const void *const hw, bool value) |
| 7258 | { |
| 7259 | uint32_t tmp; |
| 7260 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7261 | tmp = ((Sercom *)hw)->I2CS.ADDR.reg; |
| 7262 | tmp &= ~SERCOM_I2CS_ADDR_TENBITEN; |
| 7263 | tmp |= value << SERCOM_I2CS_ADDR_TENBITEN_Pos; |
| 7264 | ((Sercom *)hw)->I2CS.ADDR.reg = tmp; |
| 7265 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7266 | } |
| 7267 | |
| 7268 | static inline void hri_sercomi2cs_clear_ADDR_TENBITEN_bit(const void *const hw) |
| 7269 | { |
| 7270 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7271 | ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_TENBITEN; |
| 7272 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7273 | } |
| 7274 | |
| 7275 | static inline void hri_sercomi2cs_toggle_ADDR_TENBITEN_bit(const void *const hw) |
| 7276 | { |
| 7277 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7278 | ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_TENBITEN; |
| 7279 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7280 | } |
| 7281 | |
| 7282 | static inline void hri_sercomi2cs_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) |
| 7283 | { |
| 7284 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7285 | ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDR(mask); |
| 7286 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7287 | } |
| 7288 | |
| 7289 | static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDR_bf(const void *const hw, |
| 7290 | hri_sercomi2cs_addr_reg_t mask) |
| 7291 | { |
| 7292 | uint32_t tmp; |
| 7293 | tmp = ((Sercom *)hw)->I2CS.ADDR.reg; |
| 7294 | tmp = (tmp & SERCOM_I2CS_ADDR_ADDR(mask)) >> SERCOM_I2CS_ADDR_ADDR_Pos; |
| 7295 | return tmp; |
| 7296 | } |
| 7297 | |
| 7298 | static inline void hri_sercomi2cs_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) |
| 7299 | { |
| 7300 | uint32_t tmp; |
| 7301 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7302 | tmp = ((Sercom *)hw)->I2CS.ADDR.reg; |
| 7303 | tmp &= ~SERCOM_I2CS_ADDR_ADDR_Msk; |
| 7304 | tmp |= SERCOM_I2CS_ADDR_ADDR(data); |
| 7305 | ((Sercom *)hw)->I2CS.ADDR.reg = tmp; |
| 7306 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7307 | } |
| 7308 | |
| 7309 | static inline void hri_sercomi2cs_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) |
| 7310 | { |
| 7311 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7312 | ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDR(mask); |
| 7313 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7314 | } |
| 7315 | |
| 7316 | static inline void hri_sercomi2cs_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) |
| 7317 | { |
| 7318 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7319 | ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDR(mask); |
| 7320 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7321 | } |
| 7322 | |
| 7323 | static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDR_bf(const void *const hw) |
| 7324 | { |
| 7325 | uint32_t tmp; |
| 7326 | tmp = ((Sercom *)hw)->I2CS.ADDR.reg; |
| 7327 | tmp = (tmp & SERCOM_I2CS_ADDR_ADDR_Msk) >> SERCOM_I2CS_ADDR_ADDR_Pos; |
| 7328 | return tmp; |
| 7329 | } |
| 7330 | |
| 7331 | static inline void hri_sercomi2cs_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) |
| 7332 | { |
| 7333 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7334 | ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDRMASK(mask); |
| 7335 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7336 | } |
| 7337 | |
| 7338 | static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDRMASK_bf(const void *const hw, |
| 7339 | hri_sercomi2cs_addr_reg_t mask) |
| 7340 | { |
| 7341 | uint32_t tmp; |
| 7342 | tmp = ((Sercom *)hw)->I2CS.ADDR.reg; |
| 7343 | tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK(mask)) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; |
| 7344 | return tmp; |
| 7345 | } |
| 7346 | |
| 7347 | static inline void hri_sercomi2cs_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) |
| 7348 | { |
| 7349 | uint32_t tmp; |
| 7350 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7351 | tmp = ((Sercom *)hw)->I2CS.ADDR.reg; |
| 7352 | tmp &= ~SERCOM_I2CS_ADDR_ADDRMASK_Msk; |
| 7353 | tmp |= SERCOM_I2CS_ADDR_ADDRMASK(data); |
| 7354 | ((Sercom *)hw)->I2CS.ADDR.reg = tmp; |
| 7355 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7356 | } |
| 7357 | |
| 7358 | static inline void hri_sercomi2cs_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) |
| 7359 | { |
| 7360 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7361 | ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDRMASK(mask); |
| 7362 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7363 | } |
| 7364 | |
| 7365 | static inline void hri_sercomi2cs_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) |
| 7366 | { |
| 7367 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7368 | ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDRMASK(mask); |
| 7369 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7370 | } |
| 7371 | |
| 7372 | static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDRMASK_bf(const void *const hw) |
| 7373 | { |
| 7374 | uint32_t tmp; |
| 7375 | tmp = ((Sercom *)hw)->I2CS.ADDR.reg; |
| 7376 | tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK_Msk) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; |
| 7377 | return tmp; |
| 7378 | } |
| 7379 | |
| 7380 | static inline void hri_sercomi2cs_set_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) |
| 7381 | { |
| 7382 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7383 | ((Sercom *)hw)->I2CS.ADDR.reg |= mask; |
| 7384 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7385 | } |
| 7386 | |
| 7387 | static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_reg(const void *const hw, |
| 7388 | hri_sercomi2cs_addr_reg_t mask) |
| 7389 | { |
| 7390 | uint32_t tmp; |
| 7391 | tmp = ((Sercom *)hw)->I2CS.ADDR.reg; |
| 7392 | tmp &= mask; |
| 7393 | return tmp; |
| 7394 | } |
| 7395 | |
| 7396 | static inline void hri_sercomi2cs_write_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t data) |
| 7397 | { |
| 7398 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7399 | ((Sercom *)hw)->I2CS.ADDR.reg = data; |
| 7400 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7401 | } |
| 7402 | |
| 7403 | static inline void hri_sercomi2cs_clear_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) |
| 7404 | { |
| 7405 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7406 | ((Sercom *)hw)->I2CS.ADDR.reg &= ~mask; |
| 7407 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7408 | } |
| 7409 | |
| 7410 | static inline void hri_sercomi2cs_toggle_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) |
| 7411 | { |
| 7412 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7413 | ((Sercom *)hw)->I2CS.ADDR.reg ^= mask; |
| 7414 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7415 | } |
| 7416 | |
| 7417 | static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_reg(const void *const hw) |
| 7418 | { |
| 7419 | return ((Sercom *)hw)->I2CS.ADDR.reg; |
| 7420 | } |
| 7421 | |
| 7422 | static inline void hri_sercomspi_set_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) |
| 7423 | { |
| 7424 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7425 | ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDR(mask); |
| 7426 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7427 | } |
| 7428 | |
| 7429 | static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDR_bf(const void *const hw, |
| 7430 | hri_sercomspi_addr_reg_t mask) |
| 7431 | { |
| 7432 | uint32_t tmp; |
| 7433 | tmp = ((Sercom *)hw)->SPI.ADDR.reg; |
| 7434 | tmp = (tmp & SERCOM_SPI_ADDR_ADDR(mask)) >> SERCOM_SPI_ADDR_ADDR_Pos; |
| 7435 | return tmp; |
| 7436 | } |
| 7437 | |
| 7438 | static inline void hri_sercomspi_write_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t data) |
| 7439 | { |
| 7440 | uint32_t tmp; |
| 7441 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7442 | tmp = ((Sercom *)hw)->SPI.ADDR.reg; |
| 7443 | tmp &= ~SERCOM_SPI_ADDR_ADDR_Msk; |
| 7444 | tmp |= SERCOM_SPI_ADDR_ADDR(data); |
| 7445 | ((Sercom *)hw)->SPI.ADDR.reg = tmp; |
| 7446 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7447 | } |
| 7448 | |
| 7449 | static inline void hri_sercomspi_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) |
| 7450 | { |
| 7451 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7452 | ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDR(mask); |
| 7453 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7454 | } |
| 7455 | |
| 7456 | static inline void hri_sercomspi_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) |
| 7457 | { |
| 7458 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7459 | ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDR(mask); |
| 7460 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7461 | } |
| 7462 | |
| 7463 | static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDR_bf(const void *const hw) |
| 7464 | { |
| 7465 | uint32_t tmp; |
| 7466 | tmp = ((Sercom *)hw)->SPI.ADDR.reg; |
| 7467 | tmp = (tmp & SERCOM_SPI_ADDR_ADDR_Msk) >> SERCOM_SPI_ADDR_ADDR_Pos; |
| 7468 | return tmp; |
| 7469 | } |
| 7470 | |
| 7471 | static inline void hri_sercomspi_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) |
| 7472 | { |
| 7473 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7474 | ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDRMASK(mask); |
| 7475 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7476 | } |
| 7477 | |
| 7478 | static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDRMASK_bf(const void *const hw, |
| 7479 | hri_sercomspi_addr_reg_t mask) |
| 7480 | { |
| 7481 | uint32_t tmp; |
| 7482 | tmp = ((Sercom *)hw)->SPI.ADDR.reg; |
| 7483 | tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK(mask)) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; |
| 7484 | return tmp; |
| 7485 | } |
| 7486 | |
| 7487 | static inline void hri_sercomspi_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t data) |
| 7488 | { |
| 7489 | uint32_t tmp; |
| 7490 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7491 | tmp = ((Sercom *)hw)->SPI.ADDR.reg; |
| 7492 | tmp &= ~SERCOM_SPI_ADDR_ADDRMASK_Msk; |
| 7493 | tmp |= SERCOM_SPI_ADDR_ADDRMASK(data); |
| 7494 | ((Sercom *)hw)->SPI.ADDR.reg = tmp; |
| 7495 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7496 | } |
| 7497 | |
| 7498 | static inline void hri_sercomspi_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) |
| 7499 | { |
| 7500 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7501 | ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDRMASK(mask); |
| 7502 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7503 | } |
| 7504 | |
| 7505 | static inline void hri_sercomspi_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) |
| 7506 | { |
| 7507 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7508 | ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDRMASK(mask); |
| 7509 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7510 | } |
| 7511 | |
| 7512 | static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDRMASK_bf(const void *const hw) |
| 7513 | { |
| 7514 | uint32_t tmp; |
| 7515 | tmp = ((Sercom *)hw)->SPI.ADDR.reg; |
| 7516 | tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK_Msk) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; |
| 7517 | return tmp; |
| 7518 | } |
| 7519 | |
| 7520 | static inline void hri_sercomspi_set_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) |
| 7521 | { |
| 7522 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7523 | ((Sercom *)hw)->SPI.ADDR.reg |= mask; |
| 7524 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7525 | } |
| 7526 | |
| 7527 | static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) |
| 7528 | { |
| 7529 | uint32_t tmp; |
| 7530 | tmp = ((Sercom *)hw)->SPI.ADDR.reg; |
| 7531 | tmp &= mask; |
| 7532 | return tmp; |
| 7533 | } |
| 7534 | |
| 7535 | static inline void hri_sercomspi_write_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t data) |
| 7536 | { |
| 7537 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7538 | ((Sercom *)hw)->SPI.ADDR.reg = data; |
| 7539 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7540 | } |
| 7541 | |
| 7542 | static inline void hri_sercomspi_clear_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) |
| 7543 | { |
| 7544 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7545 | ((Sercom *)hw)->SPI.ADDR.reg &= ~mask; |
| 7546 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7547 | } |
| 7548 | |
| 7549 | static inline void hri_sercomspi_toggle_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) |
| 7550 | { |
| 7551 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7552 | ((Sercom *)hw)->SPI.ADDR.reg ^= mask; |
| 7553 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7554 | } |
| 7555 | |
| 7556 | static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_reg(const void *const hw) |
| 7557 | { |
| 7558 | return ((Sercom *)hw)->SPI.ADDR.reg; |
| 7559 | } |
| 7560 | |
| 7561 | static inline void hri_sercomi2cm_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) |
| 7562 | { |
| 7563 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7564 | ((Sercom *)hw)->I2CM.DATA.reg |= SERCOM_I2CM_DATA_DATA(mask); |
| 7565 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7566 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7567 | } |
| 7568 | |
| 7569 | static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_DATA_bf(const void *const hw, |
| 7570 | hri_sercomi2cm_data_reg_t mask) |
| 7571 | { |
| 7572 | uint32_t tmp; |
| 7573 | tmp = ((Sercom *)hw)->I2CM.DATA.reg; |
| 7574 | tmp = (tmp & SERCOM_I2CM_DATA_DATA(mask)) >> SERCOM_I2CM_DATA_DATA_Pos; |
| 7575 | return tmp; |
| 7576 | } |
| 7577 | |
| 7578 | static inline void hri_sercomi2cm_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t data) |
| 7579 | { |
| 7580 | uint32_t tmp; |
| 7581 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7582 | tmp = ((Sercom *)hw)->I2CM.DATA.reg; |
| 7583 | tmp &= ~SERCOM_I2CM_DATA_DATA_Msk; |
| 7584 | tmp |= SERCOM_I2CM_DATA_DATA(data); |
| 7585 | ((Sercom *)hw)->I2CM.DATA.reg = tmp; |
| 7586 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7587 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7588 | } |
| 7589 | |
| 7590 | static inline void hri_sercomi2cm_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) |
| 7591 | { |
| 7592 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7593 | ((Sercom *)hw)->I2CM.DATA.reg &= ~SERCOM_I2CM_DATA_DATA(mask); |
| 7594 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7595 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7596 | } |
| 7597 | |
| 7598 | static inline void hri_sercomi2cm_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) |
| 7599 | { |
| 7600 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7601 | ((Sercom *)hw)->I2CM.DATA.reg ^= SERCOM_I2CM_DATA_DATA(mask); |
| 7602 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7603 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7604 | } |
| 7605 | |
| 7606 | static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_DATA_bf(const void *const hw) |
| 7607 | { |
| 7608 | uint32_t tmp; |
| 7609 | tmp = ((Sercom *)hw)->I2CM.DATA.reg; |
| 7610 | tmp = (tmp & SERCOM_I2CM_DATA_DATA_Msk) >> SERCOM_I2CM_DATA_DATA_Pos; |
| 7611 | return tmp; |
| 7612 | } |
| 7613 | |
| 7614 | static inline void hri_sercomi2cm_set_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) |
| 7615 | { |
| 7616 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7617 | ((Sercom *)hw)->I2CM.DATA.reg |= mask; |
| 7618 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7619 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7620 | } |
| 7621 | |
| 7622 | static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_reg(const void *const hw, |
| 7623 | hri_sercomi2cm_data_reg_t mask) |
| 7624 | { |
| 7625 | uint32_t tmp; |
| 7626 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7627 | tmp = ((Sercom *)hw)->I2CM.DATA.reg; |
| 7628 | tmp &= mask; |
| 7629 | return tmp; |
| 7630 | } |
| 7631 | |
| 7632 | static inline void hri_sercomi2cm_write_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t data) |
| 7633 | { |
| 7634 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7635 | ((Sercom *)hw)->I2CM.DATA.reg = data; |
| 7636 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7637 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7638 | } |
| 7639 | |
| 7640 | static inline void hri_sercomi2cm_clear_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) |
| 7641 | { |
| 7642 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7643 | ((Sercom *)hw)->I2CM.DATA.reg &= ~mask; |
| 7644 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7645 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7646 | } |
| 7647 | |
| 7648 | static inline void hri_sercomi2cm_toggle_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) |
| 7649 | { |
| 7650 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7651 | ((Sercom *)hw)->I2CM.DATA.reg ^= mask; |
| 7652 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7653 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7654 | } |
| 7655 | |
| 7656 | static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_reg(const void *const hw) |
| 7657 | { |
| 7658 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 7659 | return ((Sercom *)hw)->I2CM.DATA.reg; |
| 7660 | } |
| 7661 | |
| 7662 | static inline void hri_sercomi2cs_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) |
| 7663 | { |
| 7664 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7665 | ((Sercom *)hw)->I2CS.DATA.reg |= SERCOM_I2CS_DATA_DATA(mask); |
| 7666 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7667 | } |
| 7668 | |
| 7669 | static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_DATA_bf(const void *const hw, |
| 7670 | hri_sercomi2cs_data_reg_t mask) |
| 7671 | { |
| 7672 | uint32_t tmp; |
| 7673 | tmp = ((Sercom *)hw)->I2CS.DATA.reg; |
| 7674 | tmp = (tmp & SERCOM_I2CS_DATA_DATA(mask)) >> SERCOM_I2CS_DATA_DATA_Pos; |
| 7675 | return tmp; |
| 7676 | } |
| 7677 | |
| 7678 | static inline void hri_sercomi2cs_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t data) |
| 7679 | { |
| 7680 | uint32_t tmp; |
| 7681 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7682 | tmp = ((Sercom *)hw)->I2CS.DATA.reg; |
| 7683 | tmp &= ~SERCOM_I2CS_DATA_DATA_Msk; |
| 7684 | tmp |= SERCOM_I2CS_DATA_DATA(data); |
| 7685 | ((Sercom *)hw)->I2CS.DATA.reg = tmp; |
| 7686 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7687 | } |
| 7688 | |
| 7689 | static inline void hri_sercomi2cs_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) |
| 7690 | { |
| 7691 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7692 | ((Sercom *)hw)->I2CS.DATA.reg &= ~SERCOM_I2CS_DATA_DATA(mask); |
| 7693 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7694 | } |
| 7695 | |
| 7696 | static inline void hri_sercomi2cs_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) |
| 7697 | { |
| 7698 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7699 | ((Sercom *)hw)->I2CS.DATA.reg ^= SERCOM_I2CS_DATA_DATA(mask); |
| 7700 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7701 | } |
| 7702 | |
| 7703 | static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_DATA_bf(const void *const hw) |
| 7704 | { |
| 7705 | uint32_t tmp; |
| 7706 | tmp = ((Sercom *)hw)->I2CS.DATA.reg; |
| 7707 | tmp = (tmp & SERCOM_I2CS_DATA_DATA_Msk) >> SERCOM_I2CS_DATA_DATA_Pos; |
| 7708 | return tmp; |
| 7709 | } |
| 7710 | |
| 7711 | static inline void hri_sercomi2cs_set_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) |
| 7712 | { |
| 7713 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7714 | ((Sercom *)hw)->I2CS.DATA.reg |= mask; |
| 7715 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7716 | } |
| 7717 | |
| 7718 | static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_reg(const void *const hw, |
| 7719 | hri_sercomi2cs_data_reg_t mask) |
| 7720 | { |
| 7721 | uint32_t tmp; |
| 7722 | tmp = ((Sercom *)hw)->I2CS.DATA.reg; |
| 7723 | tmp &= mask; |
| 7724 | return tmp; |
| 7725 | } |
| 7726 | |
| 7727 | static inline void hri_sercomi2cs_write_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t data) |
| 7728 | { |
| 7729 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7730 | ((Sercom *)hw)->I2CS.DATA.reg = data; |
| 7731 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7732 | } |
| 7733 | |
| 7734 | static inline void hri_sercomi2cs_clear_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) |
| 7735 | { |
| 7736 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7737 | ((Sercom *)hw)->I2CS.DATA.reg &= ~mask; |
| 7738 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7739 | } |
| 7740 | |
| 7741 | static inline void hri_sercomi2cs_toggle_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) |
| 7742 | { |
| 7743 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7744 | ((Sercom *)hw)->I2CS.DATA.reg ^= mask; |
| 7745 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7746 | } |
| 7747 | |
| 7748 | static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_reg(const void *const hw) |
| 7749 | { |
| 7750 | return ((Sercom *)hw)->I2CS.DATA.reg; |
| 7751 | } |
| 7752 | |
| 7753 | static inline void hri_sercomspi_set_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) |
| 7754 | { |
| 7755 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7756 | ((Sercom *)hw)->SPI.DATA.reg |= SERCOM_SPI_DATA_DATA(mask); |
| 7757 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7758 | } |
| 7759 | |
| 7760 | static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_DATA_bf(const void *const hw, |
| 7761 | hri_sercomspi_data_reg_t mask) |
| 7762 | { |
| 7763 | uint32_t tmp; |
| 7764 | tmp = ((Sercom *)hw)->SPI.DATA.reg; |
| 7765 | tmp = (tmp & SERCOM_SPI_DATA_DATA(mask)) >> SERCOM_SPI_DATA_DATA_Pos; |
| 7766 | return tmp; |
| 7767 | } |
| 7768 | |
| 7769 | static inline void hri_sercomspi_write_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t data) |
| 7770 | { |
| 7771 | uint32_t tmp; |
| 7772 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7773 | tmp = ((Sercom *)hw)->SPI.DATA.reg; |
| 7774 | tmp &= ~SERCOM_SPI_DATA_DATA_Msk; |
| 7775 | tmp |= SERCOM_SPI_DATA_DATA(data); |
| 7776 | ((Sercom *)hw)->SPI.DATA.reg = tmp; |
| 7777 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7778 | } |
| 7779 | |
| 7780 | static inline void hri_sercomspi_clear_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) |
| 7781 | { |
| 7782 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7783 | ((Sercom *)hw)->SPI.DATA.reg &= ~SERCOM_SPI_DATA_DATA(mask); |
| 7784 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7785 | } |
| 7786 | |
| 7787 | static inline void hri_sercomspi_toggle_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) |
| 7788 | { |
| 7789 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7790 | ((Sercom *)hw)->SPI.DATA.reg ^= SERCOM_SPI_DATA_DATA(mask); |
| 7791 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7792 | } |
| 7793 | |
| 7794 | static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_DATA_bf(const void *const hw) |
| 7795 | { |
| 7796 | uint32_t tmp; |
| 7797 | tmp = ((Sercom *)hw)->SPI.DATA.reg; |
| 7798 | tmp = (tmp & SERCOM_SPI_DATA_DATA_Msk) >> SERCOM_SPI_DATA_DATA_Pos; |
| 7799 | return tmp; |
| 7800 | } |
| 7801 | |
| 7802 | static inline void hri_sercomspi_set_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) |
| 7803 | { |
| 7804 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7805 | ((Sercom *)hw)->SPI.DATA.reg |= mask; |
| 7806 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7807 | } |
| 7808 | |
| 7809 | static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) |
| 7810 | { |
| 7811 | uint32_t tmp; |
| 7812 | tmp = ((Sercom *)hw)->SPI.DATA.reg; |
| 7813 | tmp &= mask; |
| 7814 | return tmp; |
| 7815 | } |
| 7816 | |
| 7817 | static inline void hri_sercomspi_write_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t data) |
| 7818 | { |
| 7819 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7820 | ((Sercom *)hw)->SPI.DATA.reg = data; |
| 7821 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7822 | } |
| 7823 | |
| 7824 | static inline void hri_sercomspi_clear_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) |
| 7825 | { |
| 7826 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7827 | ((Sercom *)hw)->SPI.DATA.reg &= ~mask; |
| 7828 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7829 | } |
| 7830 | |
| 7831 | static inline void hri_sercomspi_toggle_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) |
| 7832 | { |
| 7833 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7834 | ((Sercom *)hw)->SPI.DATA.reg ^= mask; |
| 7835 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7836 | } |
| 7837 | |
| 7838 | static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_reg(const void *const hw) |
| 7839 | { |
| 7840 | return ((Sercom *)hw)->SPI.DATA.reg; |
| 7841 | } |
| 7842 | |
| 7843 | static inline void hri_sercomusart_set_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) |
| 7844 | { |
| 7845 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7846 | ((Sercom *)hw)->USART.DATA.reg |= SERCOM_USART_DATA_DATA(mask); |
| 7847 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7848 | } |
| 7849 | |
| 7850 | static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_DATA_bf(const void *const hw, |
| 7851 | hri_sercomusart_data_reg_t mask) |
| 7852 | { |
| 7853 | uint32_t tmp; |
| 7854 | tmp = ((Sercom *)hw)->USART.DATA.reg; |
| 7855 | tmp = (tmp & SERCOM_USART_DATA_DATA(mask)) >> SERCOM_USART_DATA_DATA_Pos; |
| 7856 | return tmp; |
| 7857 | } |
| 7858 | |
| 7859 | static inline void hri_sercomusart_write_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t data) |
| 7860 | { |
| 7861 | uint32_t tmp; |
| 7862 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7863 | tmp = ((Sercom *)hw)->USART.DATA.reg; |
| 7864 | tmp &= ~SERCOM_USART_DATA_DATA_Msk; |
| 7865 | tmp |= SERCOM_USART_DATA_DATA(data); |
| 7866 | ((Sercom *)hw)->USART.DATA.reg = tmp; |
| 7867 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7868 | } |
| 7869 | |
| 7870 | static inline void hri_sercomusart_clear_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) |
| 7871 | { |
| 7872 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7873 | ((Sercom *)hw)->USART.DATA.reg &= ~SERCOM_USART_DATA_DATA(mask); |
| 7874 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7875 | } |
| 7876 | |
| 7877 | static inline void hri_sercomusart_toggle_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) |
| 7878 | { |
| 7879 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7880 | ((Sercom *)hw)->USART.DATA.reg ^= SERCOM_USART_DATA_DATA(mask); |
| 7881 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7882 | } |
| 7883 | |
| 7884 | static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_DATA_bf(const void *const hw) |
| 7885 | { |
| 7886 | uint32_t tmp; |
| 7887 | tmp = ((Sercom *)hw)->USART.DATA.reg; |
| 7888 | tmp = (tmp & SERCOM_USART_DATA_DATA_Msk) >> SERCOM_USART_DATA_DATA_Pos; |
| 7889 | return tmp; |
| 7890 | } |
| 7891 | |
| 7892 | static inline void hri_sercomusart_set_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) |
| 7893 | { |
| 7894 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7895 | ((Sercom *)hw)->USART.DATA.reg |= mask; |
| 7896 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7897 | } |
| 7898 | |
| 7899 | static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_reg(const void *const hw, |
| 7900 | hri_sercomusart_data_reg_t mask) |
| 7901 | { |
| 7902 | uint32_t tmp; |
| 7903 | tmp = ((Sercom *)hw)->USART.DATA.reg; |
| 7904 | tmp &= mask; |
| 7905 | return tmp; |
| 7906 | } |
| 7907 | |
| 7908 | static inline void hri_sercomusart_write_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t data) |
| 7909 | { |
| 7910 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7911 | ((Sercom *)hw)->USART.DATA.reg = data; |
| 7912 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7913 | } |
| 7914 | |
| 7915 | static inline void hri_sercomusart_clear_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) |
| 7916 | { |
| 7917 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7918 | ((Sercom *)hw)->USART.DATA.reg &= ~mask; |
| 7919 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7920 | } |
| 7921 | |
| 7922 | static inline void hri_sercomusart_toggle_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) |
| 7923 | { |
| 7924 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7925 | ((Sercom *)hw)->USART.DATA.reg ^= mask; |
| 7926 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7927 | } |
| 7928 | |
| 7929 | static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_reg(const void *const hw) |
| 7930 | { |
| 7931 | return ((Sercom *)hw)->USART.DATA.reg; |
| 7932 | } |
| 7933 | |
| 7934 | static inline void hri_sercomi2cm_set_DBGCTRL_DBGSTOP_bit(const void *const hw) |
| 7935 | { |
| 7936 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7937 | ((Sercom *)hw)->I2CM.DBGCTRL.reg |= SERCOM_I2CM_DBGCTRL_DBGSTOP; |
| 7938 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7939 | } |
| 7940 | |
| 7941 | static inline bool hri_sercomi2cm_get_DBGCTRL_DBGSTOP_bit(const void *const hw) |
| 7942 | { |
| 7943 | uint8_t tmp; |
| 7944 | tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; |
| 7945 | tmp = (tmp & SERCOM_I2CM_DBGCTRL_DBGSTOP) >> SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; |
| 7946 | return (bool)tmp; |
| 7947 | } |
| 7948 | |
| 7949 | static inline void hri_sercomi2cm_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) |
| 7950 | { |
| 7951 | uint8_t tmp; |
| 7952 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7953 | tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; |
| 7954 | tmp &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; |
| 7955 | tmp |= value << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; |
| 7956 | ((Sercom *)hw)->I2CM.DBGCTRL.reg = tmp; |
| 7957 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7958 | } |
| 7959 | |
| 7960 | static inline void hri_sercomi2cm_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) |
| 7961 | { |
| 7962 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7963 | ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; |
| 7964 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7965 | } |
| 7966 | |
| 7967 | static inline void hri_sercomi2cm_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) |
| 7968 | { |
| 7969 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7970 | ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= SERCOM_I2CM_DBGCTRL_DBGSTOP; |
| 7971 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7972 | } |
| 7973 | |
| 7974 | static inline void hri_sercomi2cm_set_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) |
| 7975 | { |
| 7976 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7977 | ((Sercom *)hw)->I2CM.DBGCTRL.reg |= mask; |
| 7978 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7979 | } |
| 7980 | |
| 7981 | static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_get_DBGCTRL_reg(const void *const hw, |
| 7982 | hri_sercomi2cm_dbgctrl_reg_t mask) |
| 7983 | { |
| 7984 | uint8_t tmp; |
| 7985 | tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; |
| 7986 | tmp &= mask; |
| 7987 | return tmp; |
| 7988 | } |
| 7989 | |
| 7990 | static inline void hri_sercomi2cm_write_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t data) |
| 7991 | { |
| 7992 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 7993 | ((Sercom *)hw)->I2CM.DBGCTRL.reg = data; |
| 7994 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 7995 | } |
| 7996 | |
| 7997 | static inline void hri_sercomi2cm_clear_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) |
| 7998 | { |
| 7999 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8000 | ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~mask; |
| 8001 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8002 | } |
| 8003 | |
| 8004 | static inline void hri_sercomi2cm_toggle_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) |
| 8005 | { |
| 8006 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8007 | ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= mask; |
| 8008 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8009 | } |
| 8010 | |
| 8011 | static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_read_DBGCTRL_reg(const void *const hw) |
| 8012 | { |
| 8013 | return ((Sercom *)hw)->I2CM.DBGCTRL.reg; |
| 8014 | } |
| 8015 | |
| 8016 | static inline void hri_sercomspi_set_DBGCTRL_DBGSTOP_bit(const void *const hw) |
| 8017 | { |
| 8018 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8019 | ((Sercom *)hw)->SPI.DBGCTRL.reg |= SERCOM_SPI_DBGCTRL_DBGSTOP; |
| 8020 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8021 | } |
| 8022 | |
| 8023 | static inline bool hri_sercomspi_get_DBGCTRL_DBGSTOP_bit(const void *const hw) |
| 8024 | { |
| 8025 | uint8_t tmp; |
| 8026 | tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; |
| 8027 | tmp = (tmp & SERCOM_SPI_DBGCTRL_DBGSTOP) >> SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; |
| 8028 | return (bool)tmp; |
| 8029 | } |
| 8030 | |
| 8031 | static inline void hri_sercomspi_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) |
| 8032 | { |
| 8033 | uint8_t tmp; |
| 8034 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8035 | tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; |
| 8036 | tmp &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; |
| 8037 | tmp |= value << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; |
| 8038 | ((Sercom *)hw)->SPI.DBGCTRL.reg = tmp; |
| 8039 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8040 | } |
| 8041 | |
| 8042 | static inline void hri_sercomspi_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) |
| 8043 | { |
| 8044 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8045 | ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; |
| 8046 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8047 | } |
| 8048 | |
| 8049 | static inline void hri_sercomspi_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) |
| 8050 | { |
| 8051 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8052 | ((Sercom *)hw)->SPI.DBGCTRL.reg ^= SERCOM_SPI_DBGCTRL_DBGSTOP; |
| 8053 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8054 | } |
| 8055 | |
| 8056 | static inline void hri_sercomspi_set_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) |
| 8057 | { |
| 8058 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8059 | ((Sercom *)hw)->SPI.DBGCTRL.reg |= mask; |
| 8060 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8061 | } |
| 8062 | |
| 8063 | static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_get_DBGCTRL_reg(const void *const hw, |
| 8064 | hri_sercomspi_dbgctrl_reg_t mask) |
| 8065 | { |
| 8066 | uint8_t tmp; |
| 8067 | tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; |
| 8068 | tmp &= mask; |
| 8069 | return tmp; |
| 8070 | } |
| 8071 | |
| 8072 | static inline void hri_sercomspi_write_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t data) |
| 8073 | { |
| 8074 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8075 | ((Sercom *)hw)->SPI.DBGCTRL.reg = data; |
| 8076 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8077 | } |
| 8078 | |
| 8079 | static inline void hri_sercomspi_clear_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) |
| 8080 | { |
| 8081 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8082 | ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~mask; |
| 8083 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8084 | } |
| 8085 | |
| 8086 | static inline void hri_sercomspi_toggle_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) |
| 8087 | { |
| 8088 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8089 | ((Sercom *)hw)->SPI.DBGCTRL.reg ^= mask; |
| 8090 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8091 | } |
| 8092 | |
| 8093 | static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_read_DBGCTRL_reg(const void *const hw) |
| 8094 | { |
| 8095 | return ((Sercom *)hw)->SPI.DBGCTRL.reg; |
| 8096 | } |
| 8097 | |
| 8098 | static inline void hri_sercomusart_set_DBGCTRL_DBGSTOP_bit(const void *const hw) |
| 8099 | { |
| 8100 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8101 | ((Sercom *)hw)->USART.DBGCTRL.reg |= SERCOM_USART_DBGCTRL_DBGSTOP; |
| 8102 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8103 | } |
| 8104 | |
| 8105 | static inline bool hri_sercomusart_get_DBGCTRL_DBGSTOP_bit(const void *const hw) |
| 8106 | { |
| 8107 | uint8_t tmp; |
| 8108 | tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; |
| 8109 | tmp = (tmp & SERCOM_USART_DBGCTRL_DBGSTOP) >> SERCOM_USART_DBGCTRL_DBGSTOP_Pos; |
| 8110 | return (bool)tmp; |
| 8111 | } |
| 8112 | |
| 8113 | static inline void hri_sercomusart_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) |
| 8114 | { |
| 8115 | uint8_t tmp; |
| 8116 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8117 | tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; |
| 8118 | tmp &= ~SERCOM_USART_DBGCTRL_DBGSTOP; |
| 8119 | tmp |= value << SERCOM_USART_DBGCTRL_DBGSTOP_Pos; |
| 8120 | ((Sercom *)hw)->USART.DBGCTRL.reg = tmp; |
| 8121 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8122 | } |
| 8123 | |
| 8124 | static inline void hri_sercomusart_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) |
| 8125 | { |
| 8126 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8127 | ((Sercom *)hw)->USART.DBGCTRL.reg &= ~SERCOM_USART_DBGCTRL_DBGSTOP; |
| 8128 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8129 | } |
| 8130 | |
| 8131 | static inline void hri_sercomusart_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) |
| 8132 | { |
| 8133 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8134 | ((Sercom *)hw)->USART.DBGCTRL.reg ^= SERCOM_USART_DBGCTRL_DBGSTOP; |
| 8135 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8136 | } |
| 8137 | |
| 8138 | static inline void hri_sercomusart_set_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) |
| 8139 | { |
| 8140 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8141 | ((Sercom *)hw)->USART.DBGCTRL.reg |= mask; |
| 8142 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8143 | } |
| 8144 | |
| 8145 | static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_get_DBGCTRL_reg(const void *const hw, |
| 8146 | hri_sercomusart_dbgctrl_reg_t mask) |
| 8147 | { |
| 8148 | uint8_t tmp; |
| 8149 | tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; |
| 8150 | tmp &= mask; |
| 8151 | return tmp; |
| 8152 | } |
| 8153 | |
| 8154 | static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data) |
| 8155 | { |
| 8156 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8157 | ((Sercom *)hw)->USART.DBGCTRL.reg = data; |
| 8158 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8159 | } |
| 8160 | |
| 8161 | static inline void hri_sercomusart_clear_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) |
| 8162 | { |
| 8163 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8164 | ((Sercom *)hw)->USART.DBGCTRL.reg &= ~mask; |
| 8165 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8166 | } |
| 8167 | |
| 8168 | static inline void hri_sercomusart_toggle_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) |
| 8169 | { |
| 8170 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8171 | ((Sercom *)hw)->USART.DBGCTRL.reg ^= mask; |
| 8172 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8173 | } |
| 8174 | |
| 8175 | static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_read_DBGCTRL_reg(const void *const hw) |
| 8176 | { |
| 8177 | return ((Sercom *)hw)->USART.DBGCTRL.reg; |
| 8178 | } |
| 8179 | |
| 8180 | static inline bool hri_sercomi2cs_get_STATUS_BUSERR_bit(const void *const hw) |
| 8181 | { |
| 8182 | return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_BUSERR) >> SERCOM_I2CS_STATUS_BUSERR_Pos; |
| 8183 | } |
| 8184 | |
| 8185 | static inline void hri_sercomi2cs_clear_STATUS_BUSERR_bit(const void *const hw) |
| 8186 | { |
| 8187 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8188 | ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_BUSERR; |
| 8189 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8190 | } |
| 8191 | |
| 8192 | static inline bool hri_sercomi2cs_get_STATUS_COLL_bit(const void *const hw) |
| 8193 | { |
| 8194 | return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_COLL) >> SERCOM_I2CS_STATUS_COLL_Pos; |
| 8195 | } |
| 8196 | |
| 8197 | static inline void hri_sercomi2cs_clear_STATUS_COLL_bit(const void *const hw) |
| 8198 | { |
| 8199 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8200 | ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_COLL; |
| 8201 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8202 | } |
| 8203 | |
| 8204 | static inline bool hri_sercomi2cs_get_STATUS_RXNACK_bit(const void *const hw) |
| 8205 | { |
| 8206 | return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_RXNACK) >> SERCOM_I2CS_STATUS_RXNACK_Pos; |
| 8207 | } |
| 8208 | |
| 8209 | static inline void hri_sercomi2cs_clear_STATUS_RXNACK_bit(const void *const hw) |
| 8210 | { |
| 8211 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8212 | ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_RXNACK; |
| 8213 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8214 | } |
| 8215 | |
| 8216 | static inline bool hri_sercomi2cs_get_STATUS_DIR_bit(const void *const hw) |
| 8217 | { |
| 8218 | return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_DIR) >> SERCOM_I2CS_STATUS_DIR_Pos; |
| 8219 | } |
| 8220 | |
| 8221 | static inline void hri_sercomi2cs_clear_STATUS_DIR_bit(const void *const hw) |
| 8222 | { |
| 8223 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8224 | ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_DIR; |
| 8225 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8226 | } |
| 8227 | |
| 8228 | static inline bool hri_sercomi2cs_get_STATUS_SR_bit(const void *const hw) |
| 8229 | { |
| 8230 | return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SR) >> SERCOM_I2CS_STATUS_SR_Pos; |
| 8231 | } |
| 8232 | |
| 8233 | static inline void hri_sercomi2cs_clear_STATUS_SR_bit(const void *const hw) |
| 8234 | { |
| 8235 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8236 | ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SR; |
| 8237 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8238 | } |
| 8239 | |
| 8240 | static inline bool hri_sercomi2cs_get_STATUS_LOWTOUT_bit(const void *const hw) |
| 8241 | { |
| 8242 | return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LOWTOUT) >> SERCOM_I2CS_STATUS_LOWTOUT_Pos; |
| 8243 | } |
| 8244 | |
| 8245 | static inline void hri_sercomi2cs_clear_STATUS_LOWTOUT_bit(const void *const hw) |
| 8246 | { |
| 8247 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8248 | ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT; |
| 8249 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8250 | } |
| 8251 | |
| 8252 | static inline bool hri_sercomi2cs_get_STATUS_CLKHOLD_bit(const void *const hw) |
| 8253 | { |
| 8254 | return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_CLKHOLD) >> SERCOM_I2CS_STATUS_CLKHOLD_Pos; |
| 8255 | } |
| 8256 | |
| 8257 | static inline void hri_sercomi2cs_clear_STATUS_CLKHOLD_bit(const void *const hw) |
| 8258 | { |
| 8259 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8260 | ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_CLKHOLD; |
| 8261 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8262 | } |
| 8263 | |
| 8264 | static inline bool hri_sercomi2cs_get_STATUS_SEXTTOUT_bit(const void *const hw) |
| 8265 | { |
| 8266 | return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SEXTTOUT) >> SERCOM_I2CS_STATUS_SEXTTOUT_Pos; |
| 8267 | } |
| 8268 | |
| 8269 | static inline void hri_sercomi2cs_clear_STATUS_SEXTTOUT_bit(const void *const hw) |
| 8270 | { |
| 8271 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8272 | ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SEXTTOUT; |
| 8273 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8274 | } |
| 8275 | |
| 8276 | static inline bool hri_sercomi2cs_get_STATUS_HS_bit(const void *const hw) |
| 8277 | { |
| 8278 | return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_HS) >> SERCOM_I2CS_STATUS_HS_Pos; |
| 8279 | } |
| 8280 | |
| 8281 | static inline void hri_sercomi2cs_clear_STATUS_HS_bit(const void *const hw) |
| 8282 | { |
| 8283 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8284 | ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_HS; |
| 8285 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8286 | } |
| 8287 | |
| 8288 | static inline bool hri_sercomi2cs_get_STATUS_LENERR_bit(const void *const hw) |
| 8289 | { |
| 8290 | return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LENERR) >> SERCOM_I2CS_STATUS_LENERR_Pos; |
| 8291 | } |
| 8292 | |
| 8293 | static inline void hri_sercomi2cs_clear_STATUS_LENERR_bit(const void *const hw) |
| 8294 | { |
| 8295 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8296 | ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LENERR; |
| 8297 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8298 | } |
| 8299 | |
| 8300 | static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_get_STATUS_reg(const void *const hw, |
| 8301 | hri_sercomi2cs_status_reg_t mask) |
| 8302 | { |
| 8303 | uint16_t tmp; |
| 8304 | tmp = ((Sercom *)hw)->I2CS.STATUS.reg; |
| 8305 | tmp &= mask; |
| 8306 | return tmp; |
| 8307 | } |
| 8308 | |
| 8309 | static inline void hri_sercomi2cs_clear_STATUS_reg(const void *const hw, hri_sercomi2cs_status_reg_t mask) |
| 8310 | { |
| 8311 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8312 | ((Sercom *)hw)->I2CS.STATUS.reg = mask; |
| 8313 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8314 | } |
| 8315 | |
| 8316 | static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_read_STATUS_reg(const void *const hw) |
| 8317 | { |
| 8318 | return ((Sercom *)hw)->I2CS.STATUS.reg; |
| 8319 | } |
| 8320 | |
| 8321 | static inline bool hri_sercomspi_get_STATUS_BUFOVF_bit(const void *const hw) |
| 8322 | { |
| 8323 | return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) >> SERCOM_SPI_STATUS_BUFOVF_Pos; |
| 8324 | } |
| 8325 | |
| 8326 | static inline void hri_sercomspi_clear_STATUS_BUFOVF_bit(const void *const hw) |
| 8327 | { |
| 8328 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8329 | ((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_BUFOVF; |
| 8330 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8331 | } |
| 8332 | |
| 8333 | static inline bool hri_sercomspi_get_STATUS_LENERR_bit(const void *const hw) |
| 8334 | { |
| 8335 | return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_LENERR) >> SERCOM_SPI_STATUS_LENERR_Pos; |
| 8336 | } |
| 8337 | |
| 8338 | static inline void hri_sercomspi_clear_STATUS_LENERR_bit(const void *const hw) |
| 8339 | { |
| 8340 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8341 | ((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_LENERR; |
| 8342 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8343 | } |
| 8344 | |
| 8345 | static inline hri_sercomspi_status_reg_t hri_sercomspi_get_STATUS_reg(const void *const hw, |
| 8346 | hri_sercomspi_status_reg_t mask) |
| 8347 | { |
| 8348 | uint16_t tmp; |
| 8349 | tmp = ((Sercom *)hw)->SPI.STATUS.reg; |
| 8350 | tmp &= mask; |
| 8351 | return tmp; |
| 8352 | } |
| 8353 | |
| 8354 | static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask) |
| 8355 | { |
| 8356 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8357 | ((Sercom *)hw)->SPI.STATUS.reg = mask; |
| 8358 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8359 | } |
| 8360 | |
| 8361 | static inline hri_sercomspi_status_reg_t hri_sercomspi_read_STATUS_reg(const void *const hw) |
| 8362 | { |
| 8363 | return ((Sercom *)hw)->SPI.STATUS.reg; |
| 8364 | } |
| 8365 | |
| 8366 | static inline bool hri_sercomusart_get_STATUS_PERR_bit(const void *const hw) |
| 8367 | { |
| 8368 | return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_PERR) >> SERCOM_USART_STATUS_PERR_Pos; |
| 8369 | } |
| 8370 | |
| 8371 | static inline void hri_sercomusart_clear_STATUS_PERR_bit(const void *const hw) |
| 8372 | { |
| 8373 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8374 | ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_PERR; |
| 8375 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8376 | } |
| 8377 | |
| 8378 | static inline bool hri_sercomusart_get_STATUS_FERR_bit(const void *const hw) |
| 8379 | { |
| 8380 | return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_FERR) >> SERCOM_USART_STATUS_FERR_Pos; |
| 8381 | } |
| 8382 | |
| 8383 | static inline void hri_sercomusart_clear_STATUS_FERR_bit(const void *const hw) |
| 8384 | { |
| 8385 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8386 | ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_FERR; |
| 8387 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8388 | } |
| 8389 | |
| 8390 | static inline bool hri_sercomusart_get_STATUS_BUFOVF_bit(const void *const hw) |
| 8391 | { |
| 8392 | return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_BUFOVF) >> SERCOM_USART_STATUS_BUFOVF_Pos; |
| 8393 | } |
| 8394 | |
| 8395 | static inline void hri_sercomusart_clear_STATUS_BUFOVF_bit(const void *const hw) |
| 8396 | { |
| 8397 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8398 | ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_BUFOVF; |
| 8399 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8400 | } |
| 8401 | |
| 8402 | static inline bool hri_sercomusart_get_STATUS_CTS_bit(const void *const hw) |
| 8403 | { |
| 8404 | return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_CTS) >> SERCOM_USART_STATUS_CTS_Pos; |
| 8405 | } |
| 8406 | |
| 8407 | static inline void hri_sercomusart_clear_STATUS_CTS_bit(const void *const hw) |
| 8408 | { |
| 8409 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8410 | ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_CTS; |
| 8411 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8412 | } |
| 8413 | |
| 8414 | static inline bool hri_sercomusart_get_STATUS_ISF_bit(const void *const hw) |
| 8415 | { |
| 8416 | return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ISF) >> SERCOM_USART_STATUS_ISF_Pos; |
| 8417 | } |
| 8418 | |
| 8419 | static inline void hri_sercomusart_clear_STATUS_ISF_bit(const void *const hw) |
| 8420 | { |
| 8421 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8422 | ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ISF; |
| 8423 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8424 | } |
| 8425 | |
| 8426 | static inline bool hri_sercomusart_get_STATUS_COLL_bit(const void *const hw) |
| 8427 | { |
| 8428 | return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_COLL) >> SERCOM_USART_STATUS_COLL_Pos; |
| 8429 | } |
| 8430 | |
| 8431 | static inline void hri_sercomusart_clear_STATUS_COLL_bit(const void *const hw) |
| 8432 | { |
| 8433 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8434 | ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_COLL; |
| 8435 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8436 | } |
| 8437 | |
| 8438 | static inline bool hri_sercomusart_get_STATUS_TXE_bit(const void *const hw) |
| 8439 | { |
| 8440 | return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_TXE) >> SERCOM_USART_STATUS_TXE_Pos; |
| 8441 | } |
| 8442 | |
| 8443 | static inline void hri_sercomusart_clear_STATUS_TXE_bit(const void *const hw) |
| 8444 | { |
| 8445 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8446 | ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_TXE; |
| 8447 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8448 | } |
| 8449 | |
| 8450 | static inline bool hri_sercomusart_get_STATUS_ITER_bit(const void *const hw) |
| 8451 | { |
| 8452 | return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ITER) >> SERCOM_USART_STATUS_ITER_Pos; |
| 8453 | } |
| 8454 | |
| 8455 | static inline void hri_sercomusart_clear_STATUS_ITER_bit(const void *const hw) |
| 8456 | { |
| 8457 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8458 | ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ITER; |
| 8459 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8460 | } |
| 8461 | |
| 8462 | static inline hri_sercomusart_status_reg_t hri_sercomusart_get_STATUS_reg(const void *const hw, |
| 8463 | hri_sercomusart_status_reg_t mask) |
| 8464 | { |
| 8465 | uint16_t tmp; |
| 8466 | tmp = ((Sercom *)hw)->USART.STATUS.reg; |
| 8467 | tmp &= mask; |
| 8468 | return tmp; |
| 8469 | } |
| 8470 | |
| 8471 | static inline void hri_sercomusart_clear_STATUS_reg(const void *const hw, hri_sercomusart_status_reg_t mask) |
| 8472 | { |
| 8473 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8474 | ((Sercom *)hw)->USART.STATUS.reg = mask; |
| 8475 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8476 | } |
| 8477 | |
| 8478 | static inline hri_sercomusart_status_reg_t hri_sercomusart_read_STATUS_reg(const void *const hw) |
| 8479 | { |
| 8480 | return ((Sercom *)hw)->USART.STATUS.reg; |
| 8481 | } |
| 8482 | |
| 8483 | static inline void hri_sercomi2cm_set_STATUS_BUSERR_bit(const void *const hw) |
| 8484 | { |
| 8485 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8486 | ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSERR; |
| 8487 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8488 | } |
| 8489 | |
| 8490 | static inline bool hri_sercomi2cm_get_STATUS_BUSERR_bit(const void *const hw) |
| 8491 | { |
| 8492 | return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSERR) >> SERCOM_I2CM_STATUS_BUSERR_Pos; |
| 8493 | } |
| 8494 | |
| 8495 | static inline void hri_sercomi2cm_write_STATUS_BUSERR_bit(const void *const hw, bool value) |
| 8496 | { |
| 8497 | uint16_t tmp; |
| 8498 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8499 | tmp = ((Sercom *)hw)->I2CM.STATUS.reg; |
| 8500 | tmp &= ~SERCOM_I2CM_STATUS_BUSERR; |
| 8501 | tmp |= value << SERCOM_I2CM_STATUS_BUSERR_Pos; |
| 8502 | ((Sercom *)hw)->I2CM.STATUS.reg = tmp; |
| 8503 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8504 | } |
| 8505 | |
| 8506 | static inline void hri_sercomi2cm_clear_STATUS_BUSERR_bit(const void *const hw) |
| 8507 | { |
| 8508 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8509 | ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSERR; |
| 8510 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8511 | } |
| 8512 | |
| 8513 | static inline void hri_sercomi2cm_toggle_STATUS_BUSERR_bit(const void *const hw) |
| 8514 | { |
| 8515 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8516 | ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSERR; |
| 8517 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8518 | } |
| 8519 | |
| 8520 | static inline void hri_sercomi2cm_set_STATUS_ARBLOST_bit(const void *const hw) |
| 8521 | { |
| 8522 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8523 | ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_ARBLOST; |
| 8524 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8525 | } |
| 8526 | |
| 8527 | static inline bool hri_sercomi2cm_get_STATUS_ARBLOST_bit(const void *const hw) |
| 8528 | { |
| 8529 | return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) >> SERCOM_I2CM_STATUS_ARBLOST_Pos; |
| 8530 | } |
| 8531 | |
| 8532 | static inline void hri_sercomi2cm_write_STATUS_ARBLOST_bit(const void *const hw, bool value) |
| 8533 | { |
| 8534 | uint16_t tmp; |
| 8535 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8536 | tmp = ((Sercom *)hw)->I2CM.STATUS.reg; |
| 8537 | tmp &= ~SERCOM_I2CM_STATUS_ARBLOST; |
| 8538 | tmp |= value << SERCOM_I2CM_STATUS_ARBLOST_Pos; |
| 8539 | ((Sercom *)hw)->I2CM.STATUS.reg = tmp; |
| 8540 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8541 | } |
| 8542 | |
| 8543 | static inline void hri_sercomi2cm_clear_STATUS_ARBLOST_bit(const void *const hw) |
| 8544 | { |
| 8545 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8546 | ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_ARBLOST; |
| 8547 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8548 | } |
| 8549 | |
| 8550 | static inline void hri_sercomi2cm_toggle_STATUS_ARBLOST_bit(const void *const hw) |
| 8551 | { |
| 8552 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8553 | ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_ARBLOST; |
| 8554 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8555 | } |
| 8556 | |
| 8557 | static inline void hri_sercomi2cm_set_STATUS_RXNACK_bit(const void *const hw) |
| 8558 | { |
| 8559 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8560 | ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_RXNACK; |
| 8561 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8562 | } |
| 8563 | |
| 8564 | static inline bool hri_sercomi2cm_get_STATUS_RXNACK_bit(const void *const hw) |
| 8565 | { |
| 8566 | return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) >> SERCOM_I2CM_STATUS_RXNACK_Pos; |
| 8567 | } |
| 8568 | |
| 8569 | static inline void hri_sercomi2cm_write_STATUS_RXNACK_bit(const void *const hw, bool value) |
| 8570 | { |
| 8571 | uint16_t tmp; |
| 8572 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8573 | tmp = ((Sercom *)hw)->I2CM.STATUS.reg; |
| 8574 | tmp &= ~SERCOM_I2CM_STATUS_RXNACK; |
| 8575 | tmp |= value << SERCOM_I2CM_STATUS_RXNACK_Pos; |
| 8576 | ((Sercom *)hw)->I2CM.STATUS.reg = tmp; |
| 8577 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8578 | } |
| 8579 | |
| 8580 | static inline void hri_sercomi2cm_clear_STATUS_RXNACK_bit(const void *const hw) |
| 8581 | { |
| 8582 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8583 | ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_RXNACK; |
| 8584 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8585 | } |
| 8586 | |
| 8587 | static inline void hri_sercomi2cm_toggle_STATUS_RXNACK_bit(const void *const hw) |
| 8588 | { |
| 8589 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8590 | ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_RXNACK; |
| 8591 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8592 | } |
| 8593 | |
| 8594 | static inline void hri_sercomi2cm_set_STATUS_LOWTOUT_bit(const void *const hw) |
| 8595 | { |
| 8596 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8597 | ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LOWTOUT; |
| 8598 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8599 | } |
| 8600 | |
| 8601 | static inline bool hri_sercomi2cm_get_STATUS_LOWTOUT_bit(const void *const hw) |
| 8602 | { |
| 8603 | return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LOWTOUT) >> SERCOM_I2CM_STATUS_LOWTOUT_Pos; |
| 8604 | } |
| 8605 | |
| 8606 | static inline void hri_sercomi2cm_write_STATUS_LOWTOUT_bit(const void *const hw, bool value) |
| 8607 | { |
| 8608 | uint16_t tmp; |
| 8609 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8610 | tmp = ((Sercom *)hw)->I2CM.STATUS.reg; |
| 8611 | tmp &= ~SERCOM_I2CM_STATUS_LOWTOUT; |
| 8612 | tmp |= value << SERCOM_I2CM_STATUS_LOWTOUT_Pos; |
| 8613 | ((Sercom *)hw)->I2CM.STATUS.reg = tmp; |
| 8614 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8615 | } |
| 8616 | |
| 8617 | static inline void hri_sercomi2cm_clear_STATUS_LOWTOUT_bit(const void *const hw) |
| 8618 | { |
| 8619 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8620 | ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LOWTOUT; |
| 8621 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8622 | } |
| 8623 | |
| 8624 | static inline void hri_sercomi2cm_toggle_STATUS_LOWTOUT_bit(const void *const hw) |
| 8625 | { |
| 8626 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8627 | ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LOWTOUT; |
| 8628 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8629 | } |
| 8630 | |
| 8631 | static inline void hri_sercomi2cm_set_STATUS_CLKHOLD_bit(const void *const hw) |
| 8632 | { |
| 8633 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8634 | ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_CLKHOLD; |
| 8635 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8636 | } |
| 8637 | |
| 8638 | static inline bool hri_sercomi2cm_get_STATUS_CLKHOLD_bit(const void *const hw) |
| 8639 | { |
| 8640 | return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_CLKHOLD) >> SERCOM_I2CM_STATUS_CLKHOLD_Pos; |
| 8641 | } |
| 8642 | |
| 8643 | static inline void hri_sercomi2cm_write_STATUS_CLKHOLD_bit(const void *const hw, bool value) |
| 8644 | { |
| 8645 | uint16_t tmp; |
| 8646 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8647 | tmp = ((Sercom *)hw)->I2CM.STATUS.reg; |
| 8648 | tmp &= ~SERCOM_I2CM_STATUS_CLKHOLD; |
| 8649 | tmp |= value << SERCOM_I2CM_STATUS_CLKHOLD_Pos; |
| 8650 | ((Sercom *)hw)->I2CM.STATUS.reg = tmp; |
| 8651 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8652 | } |
| 8653 | |
| 8654 | static inline void hri_sercomi2cm_clear_STATUS_CLKHOLD_bit(const void *const hw) |
| 8655 | { |
| 8656 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8657 | ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_CLKHOLD; |
| 8658 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8659 | } |
| 8660 | |
| 8661 | static inline void hri_sercomi2cm_toggle_STATUS_CLKHOLD_bit(const void *const hw) |
| 8662 | { |
| 8663 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8664 | ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_CLKHOLD; |
| 8665 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8666 | } |
| 8667 | |
| 8668 | static inline void hri_sercomi2cm_set_STATUS_MEXTTOUT_bit(const void *const hw) |
| 8669 | { |
| 8670 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8671 | ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_MEXTTOUT; |
| 8672 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8673 | } |
| 8674 | |
| 8675 | static inline bool hri_sercomi2cm_get_STATUS_MEXTTOUT_bit(const void *const hw) |
| 8676 | { |
| 8677 | return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_MEXTTOUT) >> SERCOM_I2CM_STATUS_MEXTTOUT_Pos; |
| 8678 | } |
| 8679 | |
| 8680 | static inline void hri_sercomi2cm_write_STATUS_MEXTTOUT_bit(const void *const hw, bool value) |
| 8681 | { |
| 8682 | uint16_t tmp; |
| 8683 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8684 | tmp = ((Sercom *)hw)->I2CM.STATUS.reg; |
| 8685 | tmp &= ~SERCOM_I2CM_STATUS_MEXTTOUT; |
| 8686 | tmp |= value << SERCOM_I2CM_STATUS_MEXTTOUT_Pos; |
| 8687 | ((Sercom *)hw)->I2CM.STATUS.reg = tmp; |
| 8688 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8689 | } |
| 8690 | |
| 8691 | static inline void hri_sercomi2cm_clear_STATUS_MEXTTOUT_bit(const void *const hw) |
| 8692 | { |
| 8693 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8694 | ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_MEXTTOUT; |
| 8695 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8696 | } |
| 8697 | |
| 8698 | static inline void hri_sercomi2cm_toggle_STATUS_MEXTTOUT_bit(const void *const hw) |
| 8699 | { |
| 8700 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8701 | ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_MEXTTOUT; |
| 8702 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8703 | } |
| 8704 | |
| 8705 | static inline void hri_sercomi2cm_set_STATUS_SEXTTOUT_bit(const void *const hw) |
| 8706 | { |
| 8707 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8708 | ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_SEXTTOUT; |
| 8709 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8710 | } |
| 8711 | |
| 8712 | static inline bool hri_sercomi2cm_get_STATUS_SEXTTOUT_bit(const void *const hw) |
| 8713 | { |
| 8714 | return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_SEXTTOUT) >> SERCOM_I2CM_STATUS_SEXTTOUT_Pos; |
| 8715 | } |
| 8716 | |
| 8717 | static inline void hri_sercomi2cm_write_STATUS_SEXTTOUT_bit(const void *const hw, bool value) |
| 8718 | { |
| 8719 | uint16_t tmp; |
| 8720 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8721 | tmp = ((Sercom *)hw)->I2CM.STATUS.reg; |
| 8722 | tmp &= ~SERCOM_I2CM_STATUS_SEXTTOUT; |
| 8723 | tmp |= value << SERCOM_I2CM_STATUS_SEXTTOUT_Pos; |
| 8724 | ((Sercom *)hw)->I2CM.STATUS.reg = tmp; |
| 8725 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8726 | } |
| 8727 | |
| 8728 | static inline void hri_sercomi2cm_clear_STATUS_SEXTTOUT_bit(const void *const hw) |
| 8729 | { |
| 8730 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8731 | ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_SEXTTOUT; |
| 8732 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8733 | } |
| 8734 | |
| 8735 | static inline void hri_sercomi2cm_toggle_STATUS_SEXTTOUT_bit(const void *const hw) |
| 8736 | { |
| 8737 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8738 | ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_SEXTTOUT; |
| 8739 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8740 | } |
| 8741 | |
| 8742 | static inline void hri_sercomi2cm_set_STATUS_LENERR_bit(const void *const hw) |
| 8743 | { |
| 8744 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8745 | ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LENERR; |
| 8746 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8747 | } |
| 8748 | |
| 8749 | static inline bool hri_sercomi2cm_get_STATUS_LENERR_bit(const void *const hw) |
| 8750 | { |
| 8751 | return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LENERR) >> SERCOM_I2CM_STATUS_LENERR_Pos; |
| 8752 | } |
| 8753 | |
| 8754 | static inline void hri_sercomi2cm_write_STATUS_LENERR_bit(const void *const hw, bool value) |
| 8755 | { |
| 8756 | uint16_t tmp; |
| 8757 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8758 | tmp = ((Sercom *)hw)->I2CM.STATUS.reg; |
| 8759 | tmp &= ~SERCOM_I2CM_STATUS_LENERR; |
| 8760 | tmp |= value << SERCOM_I2CM_STATUS_LENERR_Pos; |
| 8761 | ((Sercom *)hw)->I2CM.STATUS.reg = tmp; |
| 8762 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8763 | } |
| 8764 | |
| 8765 | static inline void hri_sercomi2cm_clear_STATUS_LENERR_bit(const void *const hw) |
| 8766 | { |
| 8767 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8768 | ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LENERR; |
| 8769 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8770 | } |
| 8771 | |
| 8772 | static inline void hri_sercomi2cm_toggle_STATUS_LENERR_bit(const void *const hw) |
| 8773 | { |
| 8774 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8775 | ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LENERR; |
| 8776 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8777 | } |
| 8778 | |
| 8779 | static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_BUSSTATE_bf(const void *const hw, |
| 8780 | hri_sercomi2cm_status_reg_t mask) |
| 8781 | { |
| 8782 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 8783 | return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(mask)) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; |
| 8784 | } |
| 8785 | |
| 8786 | static inline void hri_sercomi2cm_set_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) |
| 8787 | { |
| 8788 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8789 | ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSSTATE(mask); |
| 8790 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 8791 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8792 | } |
| 8793 | |
| 8794 | static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_BUSSTATE_bf(const void *const hw) |
| 8795 | { |
| 8796 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 8797 | return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE_Msk) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; |
| 8798 | } |
| 8799 | |
| 8800 | static inline void hri_sercomi2cm_write_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t data) |
| 8801 | { |
| 8802 | uint16_t tmp; |
| 8803 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8804 | tmp = ((Sercom *)hw)->I2CM.STATUS.reg; |
| 8805 | tmp &= ~SERCOM_I2CM_STATUS_BUSSTATE_Msk; |
| 8806 | tmp |= SERCOM_I2CM_STATUS_BUSSTATE(data); |
| 8807 | ((Sercom *)hw)->I2CM.STATUS.reg = tmp; |
| 8808 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 8809 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8810 | } |
| 8811 | |
| 8812 | static inline void hri_sercomi2cm_toggle_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) |
| 8813 | { |
| 8814 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8815 | ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSSTATE(mask); |
| 8816 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 8817 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8818 | } |
| 8819 | |
| 8820 | static inline void hri_sercomi2cm_clear_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) |
| 8821 | { |
| 8822 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8823 | ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(mask); |
| 8824 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 8825 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8826 | } |
| 8827 | |
| 8828 | static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_reg(const void *const hw, |
| 8829 | hri_sercomi2cm_status_reg_t mask) |
| 8830 | { |
| 8831 | uint16_t tmp; |
| 8832 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 8833 | tmp = ((Sercom *)hw)->I2CM.STATUS.reg; |
| 8834 | tmp &= mask; |
| 8835 | return tmp; |
| 8836 | } |
| 8837 | |
| 8838 | static inline void hri_sercomi2cm_set_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) |
| 8839 | { |
| 8840 | ((Sercom *)hw)->I2CM.STATUS.reg |= mask; |
| 8841 | } |
| 8842 | |
| 8843 | static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_reg(const void *const hw) |
| 8844 | { |
| 8845 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 8846 | return ((Sercom *)hw)->I2CM.STATUS.reg; |
| 8847 | } |
| 8848 | |
| 8849 | static inline void hri_sercomi2cm_write_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t data) |
| 8850 | { |
| 8851 | ((Sercom *)hw)->I2CM.STATUS.reg = data; |
| 8852 | } |
| 8853 | |
| 8854 | static inline void hri_sercomi2cm_toggle_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) |
| 8855 | { |
| 8856 | ((Sercom *)hw)->I2CM.STATUS.reg ^= mask; |
| 8857 | } |
| 8858 | |
| 8859 | static inline void hri_sercomi2cm_clear_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) |
| 8860 | { |
| 8861 | SERCOM_CRITICAL_SECTION_ENTER(); |
| 8862 | ((Sercom *)hw)->I2CM.STATUS.reg = mask; |
| 8863 | hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); |
| 8864 | SERCOM_CRITICAL_SECTION_LEAVE(); |
| 8865 | } |
| 8866 | |
| 8867 | /* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ |
| 8868 | #define hri_sercomusart_set_BAUD_FRAC_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) |
| 8869 | #define hri_sercomusart_get_BAUD_FRAC_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) |
| 8870 | #define hri_sercomusart_write_BAUD_FRAC_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) |
| 8871 | #define hri_sercomusart_clear_BAUD_FRAC_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) |
| 8872 | #define hri_sercomusart_toggle_BAUD_FRAC_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) |
| 8873 | #define hri_sercomusart_read_BAUD_FRAC_reg(a) hri_sercomusart_read_BAUD_reg(a) |
| 8874 | #define hri_sercomusart_set_BAUD_FRACFP_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) |
| 8875 | #define hri_sercomusart_get_BAUD_FRACFP_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) |
| 8876 | #define hri_sercomusart_write_BAUD_FRACFP_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) |
| 8877 | #define hri_sercomusart_clear_BAUD_FRACFP_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) |
| 8878 | #define hri_sercomusart_toggle_BAUD_FRACFP_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) |
| 8879 | #define hri_sercomusart_read_BAUD_FRACFP_reg(a) hri_sercomusart_read_BAUD_reg(a) |
| 8880 | #define hri_sercomusart_set_BAUD_USARTFP_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) |
| 8881 | #define hri_sercomusart_get_BAUD_USARTFP_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) |
| 8882 | #define hri_sercomusart_write_BAUD_USARTFP_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) |
| 8883 | #define hri_sercomusart_clear_BAUD_USARTFP_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) |
| 8884 | #define hri_sercomusart_toggle_BAUD_USARTFP_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) |
| 8885 | #define hri_sercomusart_read_BAUD_USARTFP_reg(a) hri_sercomusart_read_BAUD_reg(a) |
| 8886 | |
| 8887 | #ifdef __cplusplus |
| 8888 | } |
| 8889 | #endif |
| 8890 | |
| 8891 | #endif /* _HRI_SERCOM_E54_H_INCLUDED */ |
| 8892 | #endif /* _SAME54_SERCOM_COMPONENT_ */ |