Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM PAC |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_PAC_COMPONENT_ |
| 35 | #ifndef _HRI_PAC_E54_H_INCLUDED_ |
| 36 | #define _HRI_PAC_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_PAC_CRITICAL_SECTIONS) |
| 46 | #define PAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define PAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define PAC_CRITICAL_SECTION_ENTER() |
| 50 | #define PAC_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint32_t hri_pac_intflaga_reg_t; |
| 54 | typedef uint32_t hri_pac_intflagahb_reg_t; |
| 55 | typedef uint32_t hri_pac_intflagb_reg_t; |
| 56 | typedef uint32_t hri_pac_intflagc_reg_t; |
| 57 | typedef uint32_t hri_pac_intflagd_reg_t; |
| 58 | typedef uint32_t hri_pac_statusa_reg_t; |
| 59 | typedef uint32_t hri_pac_statusb_reg_t; |
| 60 | typedef uint32_t hri_pac_statusc_reg_t; |
| 61 | typedef uint32_t hri_pac_statusd_reg_t; |
| 62 | typedef uint32_t hri_pac_wrctrl_reg_t; |
| 63 | typedef uint8_t hri_pac_evctrl_reg_t; |
| 64 | typedef uint8_t hri_pac_intenset_reg_t; |
| 65 | |
| 66 | static inline bool hri_pac_get_INTFLAGAHB_FLASH_bit(const void *const hw) |
| 67 | { |
| 68 | return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH) >> PAC_INTFLAGAHB_FLASH_Pos; |
| 69 | } |
| 70 | |
| 71 | static inline void hri_pac_clear_INTFLAGAHB_FLASH_bit(const void *const hw) |
| 72 | { |
| 73 | ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH; |
| 74 | } |
| 75 | |
| 76 | static inline bool hri_pac_get_INTFLAGAHB_FLASH_ALT_bit(const void *const hw) |
| 77 | { |
| 78 | return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH_ALT) >> PAC_INTFLAGAHB_FLASH_ALT_Pos; |
| 79 | } |
| 80 | |
| 81 | static inline void hri_pac_clear_INTFLAGAHB_FLASH_ALT_bit(const void *const hw) |
| 82 | { |
| 83 | ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH_ALT; |
| 84 | } |
| 85 | |
| 86 | static inline bool hri_pac_get_INTFLAGAHB_SEEPROM_bit(const void *const hw) |
| 87 | { |
| 88 | return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SEEPROM) >> PAC_INTFLAGAHB_SEEPROM_Pos; |
| 89 | } |
| 90 | |
| 91 | static inline void hri_pac_clear_INTFLAGAHB_SEEPROM_bit(const void *const hw) |
| 92 | { |
| 93 | ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SEEPROM; |
| 94 | } |
| 95 | |
| 96 | static inline bool hri_pac_get_INTFLAGAHB_RAMCM4S_bit(const void *const hw) |
| 97 | { |
| 98 | return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMCM4S) >> PAC_INTFLAGAHB_RAMCM4S_Pos; |
| 99 | } |
| 100 | |
| 101 | static inline void hri_pac_clear_INTFLAGAHB_RAMCM4S_bit(const void *const hw) |
| 102 | { |
| 103 | ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMCM4S; |
| 104 | } |
| 105 | |
| 106 | static inline bool hri_pac_get_INTFLAGAHB_RAMPPPDSU_bit(const void *const hw) |
| 107 | { |
| 108 | return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMPPPDSU) >> PAC_INTFLAGAHB_RAMPPPDSU_Pos; |
| 109 | } |
| 110 | |
| 111 | static inline void hri_pac_clear_INTFLAGAHB_RAMPPPDSU_bit(const void *const hw) |
| 112 | { |
| 113 | ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMPPPDSU; |
| 114 | } |
| 115 | |
| 116 | static inline bool hri_pac_get_INTFLAGAHB_RAMDMAWR_bit(const void *const hw) |
| 117 | { |
| 118 | return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMDMAWR) >> PAC_INTFLAGAHB_RAMDMAWR_Pos; |
| 119 | } |
| 120 | |
| 121 | static inline void hri_pac_clear_INTFLAGAHB_RAMDMAWR_bit(const void *const hw) |
| 122 | { |
| 123 | ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMDMAWR; |
| 124 | } |
| 125 | |
| 126 | static inline bool hri_pac_get_INTFLAGAHB_RAMDMACICM_bit(const void *const hw) |
| 127 | { |
| 128 | return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMDMACICM) >> PAC_INTFLAGAHB_RAMDMACICM_Pos; |
| 129 | } |
| 130 | |
| 131 | static inline void hri_pac_clear_INTFLAGAHB_RAMDMACICM_bit(const void *const hw) |
| 132 | { |
| 133 | ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMDMACICM; |
| 134 | } |
| 135 | |
| 136 | static inline bool hri_pac_get_INTFLAGAHB_HPB0_bit(const void *const hw) |
| 137 | { |
| 138 | return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB0) >> PAC_INTFLAGAHB_HPB0_Pos; |
| 139 | } |
| 140 | |
| 141 | static inline void hri_pac_clear_INTFLAGAHB_HPB0_bit(const void *const hw) |
| 142 | { |
| 143 | ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB0; |
| 144 | } |
| 145 | |
| 146 | static inline bool hri_pac_get_INTFLAGAHB_HPB1_bit(const void *const hw) |
| 147 | { |
| 148 | return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB1) >> PAC_INTFLAGAHB_HPB1_Pos; |
| 149 | } |
| 150 | |
| 151 | static inline void hri_pac_clear_INTFLAGAHB_HPB1_bit(const void *const hw) |
| 152 | { |
| 153 | ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB1; |
| 154 | } |
| 155 | |
| 156 | static inline bool hri_pac_get_INTFLAGAHB_HPB2_bit(const void *const hw) |
| 157 | { |
| 158 | return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB2) >> PAC_INTFLAGAHB_HPB2_Pos; |
| 159 | } |
| 160 | |
| 161 | static inline void hri_pac_clear_INTFLAGAHB_HPB2_bit(const void *const hw) |
| 162 | { |
| 163 | ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB2; |
| 164 | } |
| 165 | |
| 166 | static inline bool hri_pac_get_INTFLAGAHB_HPB3_bit(const void *const hw) |
| 167 | { |
| 168 | return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB3) >> PAC_INTFLAGAHB_HPB3_Pos; |
| 169 | } |
| 170 | |
| 171 | static inline void hri_pac_clear_INTFLAGAHB_HPB3_bit(const void *const hw) |
| 172 | { |
| 173 | ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB3; |
| 174 | } |
| 175 | |
| 176 | static inline bool hri_pac_get_INTFLAGAHB_PUKCC_bit(const void *const hw) |
| 177 | { |
| 178 | return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_PUKCC) >> PAC_INTFLAGAHB_PUKCC_Pos; |
| 179 | } |
| 180 | |
| 181 | static inline void hri_pac_clear_INTFLAGAHB_PUKCC_bit(const void *const hw) |
| 182 | { |
| 183 | ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_PUKCC; |
| 184 | } |
| 185 | |
| 186 | static inline bool hri_pac_get_INTFLAGAHB_SDHC0_bit(const void *const hw) |
| 187 | { |
| 188 | return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SDHC0) >> PAC_INTFLAGAHB_SDHC0_Pos; |
| 189 | } |
| 190 | |
| 191 | static inline void hri_pac_clear_INTFLAGAHB_SDHC0_bit(const void *const hw) |
| 192 | { |
| 193 | ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SDHC0; |
| 194 | } |
| 195 | |
| 196 | static inline bool hri_pac_get_INTFLAGAHB_SDHC1_bit(const void *const hw) |
| 197 | { |
| 198 | return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SDHC1) >> PAC_INTFLAGAHB_SDHC1_Pos; |
| 199 | } |
| 200 | |
| 201 | static inline void hri_pac_clear_INTFLAGAHB_SDHC1_bit(const void *const hw) |
| 202 | { |
| 203 | ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SDHC1; |
| 204 | } |
| 205 | |
| 206 | static inline bool hri_pac_get_INTFLAGAHB_QSPI_bit(const void *const hw) |
| 207 | { |
| 208 | return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_QSPI) >> PAC_INTFLAGAHB_QSPI_Pos; |
| 209 | } |
| 210 | |
| 211 | static inline void hri_pac_clear_INTFLAGAHB_QSPI_bit(const void *const hw) |
| 212 | { |
| 213 | ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_QSPI; |
| 214 | } |
| 215 | |
| 216 | static inline bool hri_pac_get_INTFLAGAHB_BKUPRAM_bit(const void *const hw) |
| 217 | { |
| 218 | return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_BKUPRAM) >> PAC_INTFLAGAHB_BKUPRAM_Pos; |
| 219 | } |
| 220 | |
| 221 | static inline void hri_pac_clear_INTFLAGAHB_BKUPRAM_bit(const void *const hw) |
| 222 | { |
| 223 | ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_BKUPRAM; |
| 224 | } |
| 225 | |
| 226 | static inline hri_pac_intflagahb_reg_t hri_pac_get_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) |
| 227 | { |
| 228 | uint32_t tmp; |
| 229 | tmp = ((Pac *)hw)->INTFLAGAHB.reg; |
| 230 | tmp &= mask; |
| 231 | return tmp; |
| 232 | } |
| 233 | |
| 234 | static inline hri_pac_intflagahb_reg_t hri_pac_read_INTFLAGAHB_reg(const void *const hw) |
| 235 | { |
| 236 | return ((Pac *)hw)->INTFLAGAHB.reg; |
| 237 | } |
| 238 | |
| 239 | static inline void hri_pac_clear_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) |
| 240 | { |
| 241 | ((Pac *)hw)->INTFLAGAHB.reg = mask; |
| 242 | } |
| 243 | |
| 244 | static inline bool hri_pac_get_INTFLAGA_PAC_bit(const void *const hw) |
| 245 | { |
| 246 | return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PAC) >> PAC_INTFLAGA_PAC_Pos; |
| 247 | } |
| 248 | |
| 249 | static inline void hri_pac_clear_INTFLAGA_PAC_bit(const void *const hw) |
| 250 | { |
| 251 | ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PAC; |
| 252 | } |
| 253 | |
| 254 | static inline bool hri_pac_get_INTFLAGA_PM_bit(const void *const hw) |
| 255 | { |
| 256 | return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PM) >> PAC_INTFLAGA_PM_Pos; |
| 257 | } |
| 258 | |
| 259 | static inline void hri_pac_clear_INTFLAGA_PM_bit(const void *const hw) |
| 260 | { |
| 261 | ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PM; |
| 262 | } |
| 263 | |
| 264 | static inline bool hri_pac_get_INTFLAGA_MCLK_bit(const void *const hw) |
| 265 | { |
| 266 | return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_MCLK) >> PAC_INTFLAGA_MCLK_Pos; |
| 267 | } |
| 268 | |
| 269 | static inline void hri_pac_clear_INTFLAGA_MCLK_bit(const void *const hw) |
| 270 | { |
| 271 | ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_MCLK; |
| 272 | } |
| 273 | |
| 274 | static inline bool hri_pac_get_INTFLAGA_RSTC_bit(const void *const hw) |
| 275 | { |
| 276 | return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RSTC) >> PAC_INTFLAGA_RSTC_Pos; |
| 277 | } |
| 278 | |
| 279 | static inline void hri_pac_clear_INTFLAGA_RSTC_bit(const void *const hw) |
| 280 | { |
| 281 | ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RSTC; |
| 282 | } |
| 283 | |
| 284 | static inline bool hri_pac_get_INTFLAGA_OSCCTRL_bit(const void *const hw) |
| 285 | { |
| 286 | return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSCCTRL) >> PAC_INTFLAGA_OSCCTRL_Pos; |
| 287 | } |
| 288 | |
| 289 | static inline void hri_pac_clear_INTFLAGA_OSCCTRL_bit(const void *const hw) |
| 290 | { |
| 291 | ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSCCTRL; |
| 292 | } |
| 293 | |
| 294 | static inline bool hri_pac_get_INTFLAGA_OSC32KCTRL_bit(const void *const hw) |
| 295 | { |
| 296 | return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSC32KCTRL) >> PAC_INTFLAGA_OSC32KCTRL_Pos; |
| 297 | } |
| 298 | |
| 299 | static inline void hri_pac_clear_INTFLAGA_OSC32KCTRL_bit(const void *const hw) |
| 300 | { |
| 301 | ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSC32KCTRL; |
| 302 | } |
| 303 | |
| 304 | static inline bool hri_pac_get_INTFLAGA_SUPC_bit(const void *const hw) |
| 305 | { |
| 306 | return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SUPC) >> PAC_INTFLAGA_SUPC_Pos; |
| 307 | } |
| 308 | |
| 309 | static inline void hri_pac_clear_INTFLAGA_SUPC_bit(const void *const hw) |
| 310 | { |
| 311 | ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SUPC; |
| 312 | } |
| 313 | |
| 314 | static inline bool hri_pac_get_INTFLAGA_GCLK_bit(const void *const hw) |
| 315 | { |
| 316 | return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_GCLK) >> PAC_INTFLAGA_GCLK_Pos; |
| 317 | } |
| 318 | |
| 319 | static inline void hri_pac_clear_INTFLAGA_GCLK_bit(const void *const hw) |
| 320 | { |
| 321 | ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_GCLK; |
| 322 | } |
| 323 | |
| 324 | static inline bool hri_pac_get_INTFLAGA_WDT_bit(const void *const hw) |
| 325 | { |
| 326 | return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_WDT) >> PAC_INTFLAGA_WDT_Pos; |
| 327 | } |
| 328 | |
| 329 | static inline void hri_pac_clear_INTFLAGA_WDT_bit(const void *const hw) |
| 330 | { |
| 331 | ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_WDT; |
| 332 | } |
| 333 | |
| 334 | static inline bool hri_pac_get_INTFLAGA_RTC_bit(const void *const hw) |
| 335 | { |
| 336 | return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RTC) >> PAC_INTFLAGA_RTC_Pos; |
| 337 | } |
| 338 | |
| 339 | static inline void hri_pac_clear_INTFLAGA_RTC_bit(const void *const hw) |
| 340 | { |
| 341 | ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RTC; |
| 342 | } |
| 343 | |
| 344 | static inline bool hri_pac_get_INTFLAGA_EIC_bit(const void *const hw) |
| 345 | { |
| 346 | return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_EIC) >> PAC_INTFLAGA_EIC_Pos; |
| 347 | } |
| 348 | |
| 349 | static inline void hri_pac_clear_INTFLAGA_EIC_bit(const void *const hw) |
| 350 | { |
| 351 | ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_EIC; |
| 352 | } |
| 353 | |
| 354 | static inline bool hri_pac_get_INTFLAGA_FREQM_bit(const void *const hw) |
| 355 | { |
| 356 | return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_FREQM) >> PAC_INTFLAGA_FREQM_Pos; |
| 357 | } |
| 358 | |
| 359 | static inline void hri_pac_clear_INTFLAGA_FREQM_bit(const void *const hw) |
| 360 | { |
| 361 | ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_FREQM; |
| 362 | } |
| 363 | |
| 364 | static inline bool hri_pac_get_INTFLAGA_SERCOM0_bit(const void *const hw) |
| 365 | { |
| 366 | return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SERCOM0) >> PAC_INTFLAGA_SERCOM0_Pos; |
| 367 | } |
| 368 | |
| 369 | static inline void hri_pac_clear_INTFLAGA_SERCOM0_bit(const void *const hw) |
| 370 | { |
| 371 | ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SERCOM0; |
| 372 | } |
| 373 | |
| 374 | static inline bool hri_pac_get_INTFLAGA_SERCOM1_bit(const void *const hw) |
| 375 | { |
| 376 | return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SERCOM1) >> PAC_INTFLAGA_SERCOM1_Pos; |
| 377 | } |
| 378 | |
| 379 | static inline void hri_pac_clear_INTFLAGA_SERCOM1_bit(const void *const hw) |
| 380 | { |
| 381 | ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SERCOM1; |
| 382 | } |
| 383 | |
| 384 | static inline bool hri_pac_get_INTFLAGA_TC0_bit(const void *const hw) |
| 385 | { |
| 386 | return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_TC0) >> PAC_INTFLAGA_TC0_Pos; |
| 387 | } |
| 388 | |
| 389 | static inline void hri_pac_clear_INTFLAGA_TC0_bit(const void *const hw) |
| 390 | { |
| 391 | ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_TC0; |
| 392 | } |
| 393 | |
| 394 | static inline bool hri_pac_get_INTFLAGA_TC1_bit(const void *const hw) |
| 395 | { |
| 396 | return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_TC1) >> PAC_INTFLAGA_TC1_Pos; |
| 397 | } |
| 398 | |
| 399 | static inline void hri_pac_clear_INTFLAGA_TC1_bit(const void *const hw) |
| 400 | { |
| 401 | ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_TC1; |
| 402 | } |
| 403 | |
| 404 | static inline hri_pac_intflaga_reg_t hri_pac_get_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) |
| 405 | { |
| 406 | uint32_t tmp; |
| 407 | tmp = ((Pac *)hw)->INTFLAGA.reg; |
| 408 | tmp &= mask; |
| 409 | return tmp; |
| 410 | } |
| 411 | |
| 412 | static inline hri_pac_intflaga_reg_t hri_pac_read_INTFLAGA_reg(const void *const hw) |
| 413 | { |
| 414 | return ((Pac *)hw)->INTFLAGA.reg; |
| 415 | } |
| 416 | |
| 417 | static inline void hri_pac_clear_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) |
| 418 | { |
| 419 | ((Pac *)hw)->INTFLAGA.reg = mask; |
| 420 | } |
| 421 | |
| 422 | static inline bool hri_pac_get_INTFLAGB_USB_bit(const void *const hw) |
| 423 | { |
| 424 | return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_USB) >> PAC_INTFLAGB_USB_Pos; |
| 425 | } |
| 426 | |
| 427 | static inline void hri_pac_clear_INTFLAGB_USB_bit(const void *const hw) |
| 428 | { |
| 429 | ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_USB; |
| 430 | } |
| 431 | |
| 432 | static inline bool hri_pac_get_INTFLAGB_DSU_bit(const void *const hw) |
| 433 | { |
| 434 | return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DSU) >> PAC_INTFLAGB_DSU_Pos; |
| 435 | } |
| 436 | |
| 437 | static inline void hri_pac_clear_INTFLAGB_DSU_bit(const void *const hw) |
| 438 | { |
| 439 | ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DSU; |
| 440 | } |
| 441 | |
| 442 | static inline bool hri_pac_get_INTFLAGB_NVMCTRL_bit(const void *const hw) |
| 443 | { |
| 444 | return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_NVMCTRL) >> PAC_INTFLAGB_NVMCTRL_Pos; |
| 445 | } |
| 446 | |
| 447 | static inline void hri_pac_clear_INTFLAGB_NVMCTRL_bit(const void *const hw) |
| 448 | { |
| 449 | ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_NVMCTRL; |
| 450 | } |
| 451 | |
| 452 | static inline bool hri_pac_get_INTFLAGB_CMCC_bit(const void *const hw) |
| 453 | { |
| 454 | return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_CMCC) >> PAC_INTFLAGB_CMCC_Pos; |
| 455 | } |
| 456 | |
| 457 | static inline void hri_pac_clear_INTFLAGB_CMCC_bit(const void *const hw) |
| 458 | { |
| 459 | ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_CMCC; |
| 460 | } |
| 461 | |
| 462 | static inline bool hri_pac_get_INTFLAGB_PORT_bit(const void *const hw) |
| 463 | { |
| 464 | return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_PORT) >> PAC_INTFLAGB_PORT_Pos; |
| 465 | } |
| 466 | |
| 467 | static inline void hri_pac_clear_INTFLAGB_PORT_bit(const void *const hw) |
| 468 | { |
| 469 | ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_PORT; |
| 470 | } |
| 471 | |
| 472 | static inline bool hri_pac_get_INTFLAGB_DMAC_bit(const void *const hw) |
| 473 | { |
| 474 | return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DMAC) >> PAC_INTFLAGB_DMAC_Pos; |
| 475 | } |
| 476 | |
| 477 | static inline void hri_pac_clear_INTFLAGB_DMAC_bit(const void *const hw) |
| 478 | { |
| 479 | ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DMAC; |
| 480 | } |
| 481 | |
| 482 | static inline bool hri_pac_get_INTFLAGB_HMATRIX_bit(const void *const hw) |
| 483 | { |
| 484 | return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_HMATRIX) >> PAC_INTFLAGB_HMATRIX_Pos; |
| 485 | } |
| 486 | |
| 487 | static inline void hri_pac_clear_INTFLAGB_HMATRIX_bit(const void *const hw) |
| 488 | { |
| 489 | ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_HMATRIX; |
| 490 | } |
| 491 | |
| 492 | static inline bool hri_pac_get_INTFLAGB_EVSYS_bit(const void *const hw) |
| 493 | { |
| 494 | return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_EVSYS) >> PAC_INTFLAGB_EVSYS_Pos; |
| 495 | } |
| 496 | |
| 497 | static inline void hri_pac_clear_INTFLAGB_EVSYS_bit(const void *const hw) |
| 498 | { |
| 499 | ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_EVSYS; |
| 500 | } |
| 501 | |
| 502 | static inline bool hri_pac_get_INTFLAGB_SERCOM2_bit(const void *const hw) |
| 503 | { |
| 504 | return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_SERCOM2) >> PAC_INTFLAGB_SERCOM2_Pos; |
| 505 | } |
| 506 | |
| 507 | static inline void hri_pac_clear_INTFLAGB_SERCOM2_bit(const void *const hw) |
| 508 | { |
| 509 | ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_SERCOM2; |
| 510 | } |
| 511 | |
| 512 | static inline bool hri_pac_get_INTFLAGB_SERCOM3_bit(const void *const hw) |
| 513 | { |
| 514 | return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_SERCOM3) >> PAC_INTFLAGB_SERCOM3_Pos; |
| 515 | } |
| 516 | |
| 517 | static inline void hri_pac_clear_INTFLAGB_SERCOM3_bit(const void *const hw) |
| 518 | { |
| 519 | ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_SERCOM3; |
| 520 | } |
| 521 | |
| 522 | static inline bool hri_pac_get_INTFLAGB_TCC0_bit(const void *const hw) |
| 523 | { |
| 524 | return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TCC0) >> PAC_INTFLAGB_TCC0_Pos; |
| 525 | } |
| 526 | |
| 527 | static inline void hri_pac_clear_INTFLAGB_TCC0_bit(const void *const hw) |
| 528 | { |
| 529 | ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TCC0; |
| 530 | } |
| 531 | |
| 532 | static inline bool hri_pac_get_INTFLAGB_TCC1_bit(const void *const hw) |
| 533 | { |
| 534 | return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TCC1) >> PAC_INTFLAGB_TCC1_Pos; |
| 535 | } |
| 536 | |
| 537 | static inline void hri_pac_clear_INTFLAGB_TCC1_bit(const void *const hw) |
| 538 | { |
| 539 | ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TCC1; |
| 540 | } |
| 541 | |
| 542 | static inline bool hri_pac_get_INTFLAGB_TC2_bit(const void *const hw) |
| 543 | { |
| 544 | return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TC2) >> PAC_INTFLAGB_TC2_Pos; |
| 545 | } |
| 546 | |
| 547 | static inline void hri_pac_clear_INTFLAGB_TC2_bit(const void *const hw) |
| 548 | { |
| 549 | ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TC2; |
| 550 | } |
| 551 | |
| 552 | static inline bool hri_pac_get_INTFLAGB_TC3_bit(const void *const hw) |
| 553 | { |
| 554 | return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TC3) >> PAC_INTFLAGB_TC3_Pos; |
| 555 | } |
| 556 | |
| 557 | static inline void hri_pac_clear_INTFLAGB_TC3_bit(const void *const hw) |
| 558 | { |
| 559 | ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TC3; |
| 560 | } |
| 561 | |
| 562 | static inline bool hri_pac_get_INTFLAGB_RAMECC_bit(const void *const hw) |
| 563 | { |
| 564 | return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_RAMECC) >> PAC_INTFLAGB_RAMECC_Pos; |
| 565 | } |
| 566 | |
| 567 | static inline void hri_pac_clear_INTFLAGB_RAMECC_bit(const void *const hw) |
| 568 | { |
| 569 | ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_RAMECC; |
| 570 | } |
| 571 | |
| 572 | static inline hri_pac_intflagb_reg_t hri_pac_get_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) |
| 573 | { |
| 574 | uint32_t tmp; |
| 575 | tmp = ((Pac *)hw)->INTFLAGB.reg; |
| 576 | tmp &= mask; |
| 577 | return tmp; |
| 578 | } |
| 579 | |
| 580 | static inline hri_pac_intflagb_reg_t hri_pac_read_INTFLAGB_reg(const void *const hw) |
| 581 | { |
| 582 | return ((Pac *)hw)->INTFLAGB.reg; |
| 583 | } |
| 584 | |
| 585 | static inline void hri_pac_clear_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) |
| 586 | { |
| 587 | ((Pac *)hw)->INTFLAGB.reg = mask; |
| 588 | } |
| 589 | |
| 590 | static inline bool hri_pac_get_INTFLAGC_CAN0_bit(const void *const hw) |
| 591 | { |
| 592 | return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CAN0) >> PAC_INTFLAGC_CAN0_Pos; |
| 593 | } |
| 594 | |
| 595 | static inline void hri_pac_clear_INTFLAGC_CAN0_bit(const void *const hw) |
| 596 | { |
| 597 | ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CAN0; |
| 598 | } |
| 599 | |
| 600 | static inline bool hri_pac_get_INTFLAGC_CAN1_bit(const void *const hw) |
| 601 | { |
| 602 | return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CAN1) >> PAC_INTFLAGC_CAN1_Pos; |
| 603 | } |
| 604 | |
| 605 | static inline void hri_pac_clear_INTFLAGC_CAN1_bit(const void *const hw) |
| 606 | { |
| 607 | ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CAN1; |
| 608 | } |
| 609 | |
| 610 | static inline bool hri_pac_get_INTFLAGC_GMAC_bit(const void *const hw) |
| 611 | { |
| 612 | return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_GMAC) >> PAC_INTFLAGC_GMAC_Pos; |
| 613 | } |
| 614 | |
| 615 | static inline void hri_pac_clear_INTFLAGC_GMAC_bit(const void *const hw) |
| 616 | { |
| 617 | ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_GMAC; |
| 618 | } |
| 619 | |
| 620 | static inline bool hri_pac_get_INTFLAGC_TCC2_bit(const void *const hw) |
| 621 | { |
| 622 | return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC2) >> PAC_INTFLAGC_TCC2_Pos; |
| 623 | } |
| 624 | |
| 625 | static inline void hri_pac_clear_INTFLAGC_TCC2_bit(const void *const hw) |
| 626 | { |
| 627 | ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC2; |
| 628 | } |
| 629 | |
| 630 | static inline bool hri_pac_get_INTFLAGC_TCC3_bit(const void *const hw) |
| 631 | { |
| 632 | return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC3) >> PAC_INTFLAGC_TCC3_Pos; |
| 633 | } |
| 634 | |
| 635 | static inline void hri_pac_clear_INTFLAGC_TCC3_bit(const void *const hw) |
| 636 | { |
| 637 | ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC3; |
| 638 | } |
| 639 | |
| 640 | static inline bool hri_pac_get_INTFLAGC_TC4_bit(const void *const hw) |
| 641 | { |
| 642 | return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC4) >> PAC_INTFLAGC_TC4_Pos; |
| 643 | } |
| 644 | |
| 645 | static inline void hri_pac_clear_INTFLAGC_TC4_bit(const void *const hw) |
| 646 | { |
| 647 | ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC4; |
| 648 | } |
| 649 | |
| 650 | static inline bool hri_pac_get_INTFLAGC_TC5_bit(const void *const hw) |
| 651 | { |
| 652 | return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC5) >> PAC_INTFLAGC_TC5_Pos; |
| 653 | } |
| 654 | |
| 655 | static inline void hri_pac_clear_INTFLAGC_TC5_bit(const void *const hw) |
| 656 | { |
| 657 | ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC5; |
| 658 | } |
| 659 | |
| 660 | static inline bool hri_pac_get_INTFLAGC_PDEC_bit(const void *const hw) |
| 661 | { |
| 662 | return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PDEC) >> PAC_INTFLAGC_PDEC_Pos; |
| 663 | } |
| 664 | |
| 665 | static inline void hri_pac_clear_INTFLAGC_PDEC_bit(const void *const hw) |
| 666 | { |
| 667 | ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PDEC; |
| 668 | } |
| 669 | |
| 670 | static inline bool hri_pac_get_INTFLAGC_AC_bit(const void *const hw) |
| 671 | { |
| 672 | return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AC) >> PAC_INTFLAGC_AC_Pos; |
| 673 | } |
| 674 | |
| 675 | static inline void hri_pac_clear_INTFLAGC_AC_bit(const void *const hw) |
| 676 | { |
| 677 | ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AC; |
| 678 | } |
| 679 | |
| 680 | static inline bool hri_pac_get_INTFLAGC_AES_bit(const void *const hw) |
| 681 | { |
| 682 | return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AES) >> PAC_INTFLAGC_AES_Pos; |
| 683 | } |
| 684 | |
| 685 | static inline void hri_pac_clear_INTFLAGC_AES_bit(const void *const hw) |
| 686 | { |
| 687 | ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AES; |
| 688 | } |
| 689 | |
| 690 | static inline bool hri_pac_get_INTFLAGC_TRNG_bit(const void *const hw) |
| 691 | { |
| 692 | return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TRNG) >> PAC_INTFLAGC_TRNG_Pos; |
| 693 | } |
| 694 | |
| 695 | static inline void hri_pac_clear_INTFLAGC_TRNG_bit(const void *const hw) |
| 696 | { |
| 697 | ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TRNG; |
| 698 | } |
| 699 | |
| 700 | static inline bool hri_pac_get_INTFLAGC_ICM_bit(const void *const hw) |
| 701 | { |
| 702 | return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_ICM) >> PAC_INTFLAGC_ICM_Pos; |
| 703 | } |
| 704 | |
| 705 | static inline void hri_pac_clear_INTFLAGC_ICM_bit(const void *const hw) |
| 706 | { |
| 707 | ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_ICM; |
| 708 | } |
| 709 | |
| 710 | static inline bool hri_pac_get_INTFLAGC_PUKCC_bit(const void *const hw) |
| 711 | { |
| 712 | return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PUKCC) >> PAC_INTFLAGC_PUKCC_Pos; |
| 713 | } |
| 714 | |
| 715 | static inline void hri_pac_clear_INTFLAGC_PUKCC_bit(const void *const hw) |
| 716 | { |
| 717 | ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PUKCC; |
| 718 | } |
| 719 | |
| 720 | static inline bool hri_pac_get_INTFLAGC_QSPI_bit(const void *const hw) |
| 721 | { |
| 722 | return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_QSPI) >> PAC_INTFLAGC_QSPI_Pos; |
| 723 | } |
| 724 | |
| 725 | static inline void hri_pac_clear_INTFLAGC_QSPI_bit(const void *const hw) |
| 726 | { |
| 727 | ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_QSPI; |
| 728 | } |
| 729 | |
| 730 | static inline bool hri_pac_get_INTFLAGC_CCL_bit(const void *const hw) |
| 731 | { |
| 732 | return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CCL) >> PAC_INTFLAGC_CCL_Pos; |
| 733 | } |
| 734 | |
| 735 | static inline void hri_pac_clear_INTFLAGC_CCL_bit(const void *const hw) |
| 736 | { |
| 737 | ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CCL; |
| 738 | } |
| 739 | |
| 740 | static inline hri_pac_intflagc_reg_t hri_pac_get_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) |
| 741 | { |
| 742 | uint32_t tmp; |
| 743 | tmp = ((Pac *)hw)->INTFLAGC.reg; |
| 744 | tmp &= mask; |
| 745 | return tmp; |
| 746 | } |
| 747 | |
| 748 | static inline hri_pac_intflagc_reg_t hri_pac_read_INTFLAGC_reg(const void *const hw) |
| 749 | { |
| 750 | return ((Pac *)hw)->INTFLAGC.reg; |
| 751 | } |
| 752 | |
| 753 | static inline void hri_pac_clear_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) |
| 754 | { |
| 755 | ((Pac *)hw)->INTFLAGC.reg = mask; |
| 756 | } |
| 757 | |
| 758 | static inline bool hri_pac_get_INTFLAGD_SERCOM4_bit(const void *const hw) |
| 759 | { |
| 760 | return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM4) >> PAC_INTFLAGD_SERCOM4_Pos; |
| 761 | } |
| 762 | |
| 763 | static inline void hri_pac_clear_INTFLAGD_SERCOM4_bit(const void *const hw) |
| 764 | { |
| 765 | ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM4; |
| 766 | } |
| 767 | |
| 768 | static inline bool hri_pac_get_INTFLAGD_SERCOM5_bit(const void *const hw) |
| 769 | { |
| 770 | return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM5) >> PAC_INTFLAGD_SERCOM5_Pos; |
| 771 | } |
| 772 | |
| 773 | static inline void hri_pac_clear_INTFLAGD_SERCOM5_bit(const void *const hw) |
| 774 | { |
| 775 | ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM5; |
| 776 | } |
| 777 | |
| 778 | static inline bool hri_pac_get_INTFLAGD_SERCOM6_bit(const void *const hw) |
| 779 | { |
| 780 | return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM6) >> PAC_INTFLAGD_SERCOM6_Pos; |
| 781 | } |
| 782 | |
| 783 | static inline void hri_pac_clear_INTFLAGD_SERCOM6_bit(const void *const hw) |
| 784 | { |
| 785 | ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM6; |
| 786 | } |
| 787 | |
| 788 | static inline bool hri_pac_get_INTFLAGD_SERCOM7_bit(const void *const hw) |
| 789 | { |
| 790 | return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM7) >> PAC_INTFLAGD_SERCOM7_Pos; |
| 791 | } |
| 792 | |
| 793 | static inline void hri_pac_clear_INTFLAGD_SERCOM7_bit(const void *const hw) |
| 794 | { |
| 795 | ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM7; |
| 796 | } |
| 797 | |
| 798 | static inline bool hri_pac_get_INTFLAGD_TCC4_bit(const void *const hw) |
| 799 | { |
| 800 | return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TCC4) >> PAC_INTFLAGD_TCC4_Pos; |
| 801 | } |
| 802 | |
| 803 | static inline void hri_pac_clear_INTFLAGD_TCC4_bit(const void *const hw) |
| 804 | { |
| 805 | ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TCC4; |
| 806 | } |
| 807 | |
| 808 | static inline bool hri_pac_get_INTFLAGD_TC6_bit(const void *const hw) |
| 809 | { |
| 810 | return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TC6) >> PAC_INTFLAGD_TC6_Pos; |
| 811 | } |
| 812 | |
| 813 | static inline void hri_pac_clear_INTFLAGD_TC6_bit(const void *const hw) |
| 814 | { |
| 815 | ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TC6; |
| 816 | } |
| 817 | |
| 818 | static inline bool hri_pac_get_INTFLAGD_TC7_bit(const void *const hw) |
| 819 | { |
| 820 | return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TC7) >> PAC_INTFLAGD_TC7_Pos; |
| 821 | } |
| 822 | |
| 823 | static inline void hri_pac_clear_INTFLAGD_TC7_bit(const void *const hw) |
| 824 | { |
| 825 | ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TC7; |
| 826 | } |
| 827 | |
| 828 | static inline bool hri_pac_get_INTFLAGD_ADC0_bit(const void *const hw) |
| 829 | { |
| 830 | return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_ADC0) >> PAC_INTFLAGD_ADC0_Pos; |
| 831 | } |
| 832 | |
| 833 | static inline void hri_pac_clear_INTFLAGD_ADC0_bit(const void *const hw) |
| 834 | { |
| 835 | ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_ADC0; |
| 836 | } |
| 837 | |
| 838 | static inline bool hri_pac_get_INTFLAGD_ADC1_bit(const void *const hw) |
| 839 | { |
| 840 | return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_ADC1) >> PAC_INTFLAGD_ADC1_Pos; |
| 841 | } |
| 842 | |
| 843 | static inline void hri_pac_clear_INTFLAGD_ADC1_bit(const void *const hw) |
| 844 | { |
| 845 | ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_ADC1; |
| 846 | } |
| 847 | |
| 848 | static inline bool hri_pac_get_INTFLAGD_DAC_bit(const void *const hw) |
| 849 | { |
| 850 | return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_DAC) >> PAC_INTFLAGD_DAC_Pos; |
| 851 | } |
| 852 | |
| 853 | static inline void hri_pac_clear_INTFLAGD_DAC_bit(const void *const hw) |
| 854 | { |
| 855 | ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_DAC; |
| 856 | } |
| 857 | |
| 858 | static inline bool hri_pac_get_INTFLAGD_I2S_bit(const void *const hw) |
| 859 | { |
| 860 | return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_I2S) >> PAC_INTFLAGD_I2S_Pos; |
| 861 | } |
| 862 | |
| 863 | static inline void hri_pac_clear_INTFLAGD_I2S_bit(const void *const hw) |
| 864 | { |
| 865 | ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_I2S; |
| 866 | } |
| 867 | |
| 868 | static inline bool hri_pac_get_INTFLAGD_PCC_bit(const void *const hw) |
| 869 | { |
| 870 | return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_PCC) >> PAC_INTFLAGD_PCC_Pos; |
| 871 | } |
| 872 | |
| 873 | static inline void hri_pac_clear_INTFLAGD_PCC_bit(const void *const hw) |
| 874 | { |
| 875 | ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_PCC; |
| 876 | } |
| 877 | |
| 878 | static inline hri_pac_intflagd_reg_t hri_pac_get_INTFLAGD_reg(const void *const hw, hri_pac_intflagd_reg_t mask) |
| 879 | { |
| 880 | uint32_t tmp; |
| 881 | tmp = ((Pac *)hw)->INTFLAGD.reg; |
| 882 | tmp &= mask; |
| 883 | return tmp; |
| 884 | } |
| 885 | |
| 886 | static inline hri_pac_intflagd_reg_t hri_pac_read_INTFLAGD_reg(const void *const hw) |
| 887 | { |
| 888 | return ((Pac *)hw)->INTFLAGD.reg; |
| 889 | } |
| 890 | |
| 891 | static inline void hri_pac_clear_INTFLAGD_reg(const void *const hw, hri_pac_intflagd_reg_t mask) |
| 892 | { |
| 893 | ((Pac *)hw)->INTFLAGD.reg = mask; |
| 894 | } |
| 895 | |
| 896 | static inline void hri_pac_set_INTEN_ERR_bit(const void *const hw) |
| 897 | { |
| 898 | ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; |
| 899 | } |
| 900 | |
| 901 | static inline bool hri_pac_get_INTEN_ERR_bit(const void *const hw) |
| 902 | { |
| 903 | return (((Pac *)hw)->INTENSET.reg & PAC_INTENSET_ERR) >> PAC_INTENSET_ERR_Pos; |
| 904 | } |
| 905 | |
| 906 | static inline void hri_pac_write_INTEN_ERR_bit(const void *const hw, bool value) |
| 907 | { |
| 908 | if (value == 0x0) { |
| 909 | ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; |
| 910 | } else { |
| 911 | ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; |
| 912 | } |
| 913 | } |
| 914 | |
| 915 | static inline void hri_pac_clear_INTEN_ERR_bit(const void *const hw) |
| 916 | { |
| 917 | ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; |
| 918 | } |
| 919 | |
| 920 | static inline void hri_pac_set_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) |
| 921 | { |
| 922 | ((Pac *)hw)->INTENSET.reg = mask; |
| 923 | } |
| 924 | |
| 925 | static inline hri_pac_intenset_reg_t hri_pac_get_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) |
| 926 | { |
| 927 | uint8_t tmp; |
| 928 | tmp = ((Pac *)hw)->INTENSET.reg; |
| 929 | tmp &= mask; |
| 930 | return tmp; |
| 931 | } |
| 932 | |
| 933 | static inline hri_pac_intenset_reg_t hri_pac_read_INTEN_reg(const void *const hw) |
| 934 | { |
| 935 | return ((Pac *)hw)->INTENSET.reg; |
| 936 | } |
| 937 | |
| 938 | static inline void hri_pac_write_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t data) |
| 939 | { |
| 940 | ((Pac *)hw)->INTENSET.reg = data; |
| 941 | ((Pac *)hw)->INTENCLR.reg = ~data; |
| 942 | } |
| 943 | |
| 944 | static inline void hri_pac_clear_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) |
| 945 | { |
| 946 | ((Pac *)hw)->INTENCLR.reg = mask; |
| 947 | } |
| 948 | |
| 949 | static inline bool hri_pac_get_STATUSA_PAC_bit(const void *const hw) |
| 950 | { |
| 951 | return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PAC) >> PAC_STATUSA_PAC_Pos; |
| 952 | } |
| 953 | |
| 954 | static inline bool hri_pac_get_STATUSA_PM_bit(const void *const hw) |
| 955 | { |
| 956 | return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PM) >> PAC_STATUSA_PM_Pos; |
| 957 | } |
| 958 | |
| 959 | static inline bool hri_pac_get_STATUSA_MCLK_bit(const void *const hw) |
| 960 | { |
| 961 | return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_MCLK) >> PAC_STATUSA_MCLK_Pos; |
| 962 | } |
| 963 | |
| 964 | static inline bool hri_pac_get_STATUSA_RSTC_bit(const void *const hw) |
| 965 | { |
| 966 | return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RSTC) >> PAC_STATUSA_RSTC_Pos; |
| 967 | } |
| 968 | |
| 969 | static inline bool hri_pac_get_STATUSA_OSCCTRL_bit(const void *const hw) |
| 970 | { |
| 971 | return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSCCTRL) >> PAC_STATUSA_OSCCTRL_Pos; |
| 972 | } |
| 973 | |
| 974 | static inline bool hri_pac_get_STATUSA_OSC32KCTRL_bit(const void *const hw) |
| 975 | { |
| 976 | return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSC32KCTRL) >> PAC_STATUSA_OSC32KCTRL_Pos; |
| 977 | } |
| 978 | |
| 979 | static inline bool hri_pac_get_STATUSA_SUPC_bit(const void *const hw) |
| 980 | { |
| 981 | return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SUPC) >> PAC_STATUSA_SUPC_Pos; |
| 982 | } |
| 983 | |
| 984 | static inline bool hri_pac_get_STATUSA_GCLK_bit(const void *const hw) |
| 985 | { |
| 986 | return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_GCLK) >> PAC_STATUSA_GCLK_Pos; |
| 987 | } |
| 988 | |
| 989 | static inline bool hri_pac_get_STATUSA_WDT_bit(const void *const hw) |
| 990 | { |
| 991 | return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_WDT) >> PAC_STATUSA_WDT_Pos; |
| 992 | } |
| 993 | |
| 994 | static inline bool hri_pac_get_STATUSA_RTC_bit(const void *const hw) |
| 995 | { |
| 996 | return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RTC) >> PAC_STATUSA_RTC_Pos; |
| 997 | } |
| 998 | |
| 999 | static inline bool hri_pac_get_STATUSA_EIC_bit(const void *const hw) |
| 1000 | { |
| 1001 | return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_EIC) >> PAC_STATUSA_EIC_Pos; |
| 1002 | } |
| 1003 | |
| 1004 | static inline bool hri_pac_get_STATUSA_FREQM_bit(const void *const hw) |
| 1005 | { |
| 1006 | return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_FREQM) >> PAC_STATUSA_FREQM_Pos; |
| 1007 | } |
| 1008 | |
| 1009 | static inline bool hri_pac_get_STATUSA_SERCOM0_bit(const void *const hw) |
| 1010 | { |
| 1011 | return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SERCOM0) >> PAC_STATUSA_SERCOM0_Pos; |
| 1012 | } |
| 1013 | |
| 1014 | static inline bool hri_pac_get_STATUSA_SERCOM1_bit(const void *const hw) |
| 1015 | { |
| 1016 | return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SERCOM1) >> PAC_STATUSA_SERCOM1_Pos; |
| 1017 | } |
| 1018 | |
| 1019 | static inline bool hri_pac_get_STATUSA_TC0_bit(const void *const hw) |
| 1020 | { |
| 1021 | return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_TC0) >> PAC_STATUSA_TC0_Pos; |
| 1022 | } |
| 1023 | |
| 1024 | static inline bool hri_pac_get_STATUSA_TC1_bit(const void *const hw) |
| 1025 | { |
| 1026 | return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_TC1) >> PAC_STATUSA_TC1_Pos; |
| 1027 | } |
| 1028 | |
| 1029 | static inline hri_pac_statusa_reg_t hri_pac_get_STATUSA_reg(const void *const hw, hri_pac_statusa_reg_t mask) |
| 1030 | { |
| 1031 | uint32_t tmp; |
| 1032 | tmp = ((Pac *)hw)->STATUSA.reg; |
| 1033 | tmp &= mask; |
| 1034 | return tmp; |
| 1035 | } |
| 1036 | |
| 1037 | static inline hri_pac_statusa_reg_t hri_pac_read_STATUSA_reg(const void *const hw) |
| 1038 | { |
| 1039 | return ((Pac *)hw)->STATUSA.reg; |
| 1040 | } |
| 1041 | |
| 1042 | static inline bool hri_pac_get_STATUSB_USB_bit(const void *const hw) |
| 1043 | { |
| 1044 | return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_USB) >> PAC_STATUSB_USB_Pos; |
| 1045 | } |
| 1046 | |
| 1047 | static inline bool hri_pac_get_STATUSB_DSU_bit(const void *const hw) |
| 1048 | { |
| 1049 | return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DSU) >> PAC_STATUSB_DSU_Pos; |
| 1050 | } |
| 1051 | |
| 1052 | static inline bool hri_pac_get_STATUSB_NVMCTRL_bit(const void *const hw) |
| 1053 | { |
| 1054 | return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_NVMCTRL) >> PAC_STATUSB_NVMCTRL_Pos; |
| 1055 | } |
| 1056 | |
| 1057 | static inline bool hri_pac_get_STATUSB_CMCC_bit(const void *const hw) |
| 1058 | { |
| 1059 | return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_CMCC) >> PAC_STATUSB_CMCC_Pos; |
| 1060 | } |
| 1061 | |
| 1062 | static inline bool hri_pac_get_STATUSB_PORT_bit(const void *const hw) |
| 1063 | { |
| 1064 | return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_PORT) >> PAC_STATUSB_PORT_Pos; |
| 1065 | } |
| 1066 | |
| 1067 | static inline bool hri_pac_get_STATUSB_DMAC_bit(const void *const hw) |
| 1068 | { |
| 1069 | return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DMAC) >> PAC_STATUSB_DMAC_Pos; |
| 1070 | } |
| 1071 | |
| 1072 | static inline bool hri_pac_get_STATUSB_HMATRIX_bit(const void *const hw) |
| 1073 | { |
| 1074 | return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_HMATRIX) >> PAC_STATUSB_HMATRIX_Pos; |
| 1075 | } |
| 1076 | |
| 1077 | static inline bool hri_pac_get_STATUSB_EVSYS_bit(const void *const hw) |
| 1078 | { |
| 1079 | return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_EVSYS) >> PAC_STATUSB_EVSYS_Pos; |
| 1080 | } |
| 1081 | |
| 1082 | static inline bool hri_pac_get_STATUSB_SERCOM2_bit(const void *const hw) |
| 1083 | { |
| 1084 | return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_SERCOM2) >> PAC_STATUSB_SERCOM2_Pos; |
| 1085 | } |
| 1086 | |
| 1087 | static inline bool hri_pac_get_STATUSB_SERCOM3_bit(const void *const hw) |
| 1088 | { |
| 1089 | return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_SERCOM3) >> PAC_STATUSB_SERCOM3_Pos; |
| 1090 | } |
| 1091 | |
| 1092 | static inline bool hri_pac_get_STATUSB_TCC0_bit(const void *const hw) |
| 1093 | { |
| 1094 | return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TCC0) >> PAC_STATUSB_TCC0_Pos; |
| 1095 | } |
| 1096 | |
| 1097 | static inline bool hri_pac_get_STATUSB_TCC1_bit(const void *const hw) |
| 1098 | { |
| 1099 | return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TCC1) >> PAC_STATUSB_TCC1_Pos; |
| 1100 | } |
| 1101 | |
| 1102 | static inline bool hri_pac_get_STATUSB_TC2_bit(const void *const hw) |
| 1103 | { |
| 1104 | return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TC2) >> PAC_STATUSB_TC2_Pos; |
| 1105 | } |
| 1106 | |
| 1107 | static inline bool hri_pac_get_STATUSB_TC3_bit(const void *const hw) |
| 1108 | { |
| 1109 | return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TC3) >> PAC_STATUSB_TC3_Pos; |
| 1110 | } |
| 1111 | |
| 1112 | static inline bool hri_pac_get_STATUSB_RAMECC_bit(const void *const hw) |
| 1113 | { |
| 1114 | return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_RAMECC) >> PAC_STATUSB_RAMECC_Pos; |
| 1115 | } |
| 1116 | |
| 1117 | static inline hri_pac_statusb_reg_t hri_pac_get_STATUSB_reg(const void *const hw, hri_pac_statusb_reg_t mask) |
| 1118 | { |
| 1119 | uint32_t tmp; |
| 1120 | tmp = ((Pac *)hw)->STATUSB.reg; |
| 1121 | tmp &= mask; |
| 1122 | return tmp; |
| 1123 | } |
| 1124 | |
| 1125 | static inline hri_pac_statusb_reg_t hri_pac_read_STATUSB_reg(const void *const hw) |
| 1126 | { |
| 1127 | return ((Pac *)hw)->STATUSB.reg; |
| 1128 | } |
| 1129 | |
| 1130 | static inline bool hri_pac_get_STATUSC_CAN0_bit(const void *const hw) |
| 1131 | { |
| 1132 | return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CAN0) >> PAC_STATUSC_CAN0_Pos; |
| 1133 | } |
| 1134 | |
| 1135 | static inline bool hri_pac_get_STATUSC_CAN1_bit(const void *const hw) |
| 1136 | { |
| 1137 | return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CAN1) >> PAC_STATUSC_CAN1_Pos; |
| 1138 | } |
| 1139 | |
| 1140 | static inline bool hri_pac_get_STATUSC_GMAC_bit(const void *const hw) |
| 1141 | { |
| 1142 | return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_GMAC) >> PAC_STATUSC_GMAC_Pos; |
| 1143 | } |
| 1144 | |
| 1145 | static inline bool hri_pac_get_STATUSC_TCC2_bit(const void *const hw) |
| 1146 | { |
| 1147 | return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC2) >> PAC_STATUSC_TCC2_Pos; |
| 1148 | } |
| 1149 | |
| 1150 | static inline bool hri_pac_get_STATUSC_TCC3_bit(const void *const hw) |
| 1151 | { |
| 1152 | return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC3) >> PAC_STATUSC_TCC3_Pos; |
| 1153 | } |
| 1154 | |
| 1155 | static inline bool hri_pac_get_STATUSC_TC4_bit(const void *const hw) |
| 1156 | { |
| 1157 | return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC4) >> PAC_STATUSC_TC4_Pos; |
| 1158 | } |
| 1159 | |
| 1160 | static inline bool hri_pac_get_STATUSC_TC5_bit(const void *const hw) |
| 1161 | { |
| 1162 | return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC5) >> PAC_STATUSC_TC5_Pos; |
| 1163 | } |
| 1164 | |
| 1165 | static inline bool hri_pac_get_STATUSC_PDEC_bit(const void *const hw) |
| 1166 | { |
| 1167 | return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PDEC) >> PAC_STATUSC_PDEC_Pos; |
| 1168 | } |
| 1169 | |
| 1170 | static inline bool hri_pac_get_STATUSC_AC_bit(const void *const hw) |
| 1171 | { |
| 1172 | return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AC) >> PAC_STATUSC_AC_Pos; |
| 1173 | } |
| 1174 | |
| 1175 | static inline bool hri_pac_get_STATUSC_AES_bit(const void *const hw) |
| 1176 | { |
| 1177 | return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AES) >> PAC_STATUSC_AES_Pos; |
| 1178 | } |
| 1179 | |
| 1180 | static inline bool hri_pac_get_STATUSC_TRNG_bit(const void *const hw) |
| 1181 | { |
| 1182 | return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TRNG) >> PAC_STATUSC_TRNG_Pos; |
| 1183 | } |
| 1184 | |
| 1185 | static inline bool hri_pac_get_STATUSC_ICM_bit(const void *const hw) |
| 1186 | { |
| 1187 | return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_ICM) >> PAC_STATUSC_ICM_Pos; |
| 1188 | } |
| 1189 | |
| 1190 | static inline bool hri_pac_get_STATUSC_PUKCC_bit(const void *const hw) |
| 1191 | { |
| 1192 | return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PUKCC) >> PAC_STATUSC_PUKCC_Pos; |
| 1193 | } |
| 1194 | |
| 1195 | static inline bool hri_pac_get_STATUSC_QSPI_bit(const void *const hw) |
| 1196 | { |
| 1197 | return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_QSPI) >> PAC_STATUSC_QSPI_Pos; |
| 1198 | } |
| 1199 | |
| 1200 | static inline bool hri_pac_get_STATUSC_CCL_bit(const void *const hw) |
| 1201 | { |
| 1202 | return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CCL) >> PAC_STATUSC_CCL_Pos; |
| 1203 | } |
| 1204 | |
| 1205 | static inline hri_pac_statusc_reg_t hri_pac_get_STATUSC_reg(const void *const hw, hri_pac_statusc_reg_t mask) |
| 1206 | { |
| 1207 | uint32_t tmp; |
| 1208 | tmp = ((Pac *)hw)->STATUSC.reg; |
| 1209 | tmp &= mask; |
| 1210 | return tmp; |
| 1211 | } |
| 1212 | |
| 1213 | static inline hri_pac_statusc_reg_t hri_pac_read_STATUSC_reg(const void *const hw) |
| 1214 | { |
| 1215 | return ((Pac *)hw)->STATUSC.reg; |
| 1216 | } |
| 1217 | |
| 1218 | static inline bool hri_pac_get_STATUSD_SERCOM4_bit(const void *const hw) |
| 1219 | { |
| 1220 | return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM4) >> PAC_STATUSD_SERCOM4_Pos; |
| 1221 | } |
| 1222 | |
| 1223 | static inline bool hri_pac_get_STATUSD_SERCOM5_bit(const void *const hw) |
| 1224 | { |
| 1225 | return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM5) >> PAC_STATUSD_SERCOM5_Pos; |
| 1226 | } |
| 1227 | |
| 1228 | static inline bool hri_pac_get_STATUSD_SERCOM6_bit(const void *const hw) |
| 1229 | { |
| 1230 | return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM6) >> PAC_STATUSD_SERCOM6_Pos; |
| 1231 | } |
| 1232 | |
| 1233 | static inline bool hri_pac_get_STATUSD_SERCOM7_bit(const void *const hw) |
| 1234 | { |
| 1235 | return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM7) >> PAC_STATUSD_SERCOM7_Pos; |
| 1236 | } |
| 1237 | |
| 1238 | static inline bool hri_pac_get_STATUSD_TCC4_bit(const void *const hw) |
| 1239 | { |
| 1240 | return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TCC4) >> PAC_STATUSD_TCC4_Pos; |
| 1241 | } |
| 1242 | |
| 1243 | static inline bool hri_pac_get_STATUSD_TC6_bit(const void *const hw) |
| 1244 | { |
| 1245 | return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TC6) >> PAC_STATUSD_TC6_Pos; |
| 1246 | } |
| 1247 | |
| 1248 | static inline bool hri_pac_get_STATUSD_TC7_bit(const void *const hw) |
| 1249 | { |
| 1250 | return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TC7) >> PAC_STATUSD_TC7_Pos; |
| 1251 | } |
| 1252 | |
| 1253 | static inline bool hri_pac_get_STATUSD_ADC0_bit(const void *const hw) |
| 1254 | { |
| 1255 | return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_ADC0) >> PAC_STATUSD_ADC0_Pos; |
| 1256 | } |
| 1257 | |
| 1258 | static inline bool hri_pac_get_STATUSD_ADC1_bit(const void *const hw) |
| 1259 | { |
| 1260 | return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_ADC1) >> PAC_STATUSD_ADC1_Pos; |
| 1261 | } |
| 1262 | |
| 1263 | static inline bool hri_pac_get_STATUSD_DAC_bit(const void *const hw) |
| 1264 | { |
| 1265 | return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_DAC) >> PAC_STATUSD_DAC_Pos; |
| 1266 | } |
| 1267 | |
| 1268 | static inline bool hri_pac_get_STATUSD_I2S_bit(const void *const hw) |
| 1269 | { |
| 1270 | return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_I2S) >> PAC_STATUSD_I2S_Pos; |
| 1271 | } |
| 1272 | |
| 1273 | static inline bool hri_pac_get_STATUSD_PCC_bit(const void *const hw) |
| 1274 | { |
| 1275 | return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_PCC) >> PAC_STATUSD_PCC_Pos; |
| 1276 | } |
| 1277 | |
| 1278 | static inline hri_pac_statusd_reg_t hri_pac_get_STATUSD_reg(const void *const hw, hri_pac_statusd_reg_t mask) |
| 1279 | { |
| 1280 | uint32_t tmp; |
| 1281 | tmp = ((Pac *)hw)->STATUSD.reg; |
| 1282 | tmp &= mask; |
| 1283 | return tmp; |
| 1284 | } |
| 1285 | |
| 1286 | static inline hri_pac_statusd_reg_t hri_pac_read_STATUSD_reg(const void *const hw) |
| 1287 | { |
| 1288 | return ((Pac *)hw)->STATUSD.reg; |
| 1289 | } |
| 1290 | |
| 1291 | static inline void hri_pac_set_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) |
| 1292 | { |
| 1293 | PAC_CRITICAL_SECTION_ENTER(); |
| 1294 | ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_PERID(mask); |
| 1295 | PAC_CRITICAL_SECTION_LEAVE(); |
| 1296 | } |
| 1297 | |
| 1298 | static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) |
| 1299 | { |
| 1300 | uint32_t tmp; |
| 1301 | tmp = ((Pac *)hw)->WRCTRL.reg; |
| 1302 | tmp = (tmp & PAC_WRCTRL_PERID(mask)) >> PAC_WRCTRL_PERID_Pos; |
| 1303 | return tmp; |
| 1304 | } |
| 1305 | |
| 1306 | static inline void hri_pac_write_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t data) |
| 1307 | { |
| 1308 | uint32_t tmp; |
| 1309 | PAC_CRITICAL_SECTION_ENTER(); |
| 1310 | tmp = ((Pac *)hw)->WRCTRL.reg; |
| 1311 | tmp &= ~PAC_WRCTRL_PERID_Msk; |
| 1312 | tmp |= PAC_WRCTRL_PERID(data); |
| 1313 | ((Pac *)hw)->WRCTRL.reg = tmp; |
| 1314 | PAC_CRITICAL_SECTION_LEAVE(); |
| 1315 | } |
| 1316 | |
| 1317 | static inline void hri_pac_clear_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) |
| 1318 | { |
| 1319 | PAC_CRITICAL_SECTION_ENTER(); |
| 1320 | ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_PERID(mask); |
| 1321 | PAC_CRITICAL_SECTION_LEAVE(); |
| 1322 | } |
| 1323 | |
| 1324 | static inline void hri_pac_toggle_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) |
| 1325 | { |
| 1326 | PAC_CRITICAL_SECTION_ENTER(); |
| 1327 | ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_PERID(mask); |
| 1328 | PAC_CRITICAL_SECTION_LEAVE(); |
| 1329 | } |
| 1330 | |
| 1331 | static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_PERID_bf(const void *const hw) |
| 1332 | { |
| 1333 | uint32_t tmp; |
| 1334 | tmp = ((Pac *)hw)->WRCTRL.reg; |
| 1335 | tmp = (tmp & PAC_WRCTRL_PERID_Msk) >> PAC_WRCTRL_PERID_Pos; |
| 1336 | return tmp; |
| 1337 | } |
| 1338 | |
| 1339 | static inline void hri_pac_set_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) |
| 1340 | { |
| 1341 | PAC_CRITICAL_SECTION_ENTER(); |
| 1342 | ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_KEY(mask); |
| 1343 | PAC_CRITICAL_SECTION_LEAVE(); |
| 1344 | } |
| 1345 | |
| 1346 | static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) |
| 1347 | { |
| 1348 | uint32_t tmp; |
| 1349 | tmp = ((Pac *)hw)->WRCTRL.reg; |
| 1350 | tmp = (tmp & PAC_WRCTRL_KEY(mask)) >> PAC_WRCTRL_KEY_Pos; |
| 1351 | return tmp; |
| 1352 | } |
| 1353 | |
| 1354 | static inline void hri_pac_write_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t data) |
| 1355 | { |
| 1356 | uint32_t tmp; |
| 1357 | PAC_CRITICAL_SECTION_ENTER(); |
| 1358 | tmp = ((Pac *)hw)->WRCTRL.reg; |
| 1359 | tmp &= ~PAC_WRCTRL_KEY_Msk; |
| 1360 | tmp |= PAC_WRCTRL_KEY(data); |
| 1361 | ((Pac *)hw)->WRCTRL.reg = tmp; |
| 1362 | PAC_CRITICAL_SECTION_LEAVE(); |
| 1363 | } |
| 1364 | |
| 1365 | static inline void hri_pac_clear_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) |
| 1366 | { |
| 1367 | PAC_CRITICAL_SECTION_ENTER(); |
| 1368 | ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_KEY(mask); |
| 1369 | PAC_CRITICAL_SECTION_LEAVE(); |
| 1370 | } |
| 1371 | |
| 1372 | static inline void hri_pac_toggle_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) |
| 1373 | { |
| 1374 | PAC_CRITICAL_SECTION_ENTER(); |
| 1375 | ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_KEY(mask); |
| 1376 | PAC_CRITICAL_SECTION_LEAVE(); |
| 1377 | } |
| 1378 | |
| 1379 | static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_KEY_bf(const void *const hw) |
| 1380 | { |
| 1381 | uint32_t tmp; |
| 1382 | tmp = ((Pac *)hw)->WRCTRL.reg; |
| 1383 | tmp = (tmp & PAC_WRCTRL_KEY_Msk) >> PAC_WRCTRL_KEY_Pos; |
| 1384 | return tmp; |
| 1385 | } |
| 1386 | |
| 1387 | static inline void hri_pac_set_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) |
| 1388 | { |
| 1389 | PAC_CRITICAL_SECTION_ENTER(); |
| 1390 | ((Pac *)hw)->WRCTRL.reg |= mask; |
| 1391 | PAC_CRITICAL_SECTION_LEAVE(); |
| 1392 | } |
| 1393 | |
| 1394 | static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) |
| 1395 | { |
| 1396 | uint32_t tmp; |
| 1397 | tmp = ((Pac *)hw)->WRCTRL.reg; |
| 1398 | tmp &= mask; |
| 1399 | return tmp; |
| 1400 | } |
| 1401 | |
| 1402 | static inline void hri_pac_write_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t data) |
| 1403 | { |
| 1404 | PAC_CRITICAL_SECTION_ENTER(); |
| 1405 | ((Pac *)hw)->WRCTRL.reg = data; |
| 1406 | PAC_CRITICAL_SECTION_LEAVE(); |
| 1407 | } |
| 1408 | |
| 1409 | static inline void hri_pac_clear_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) |
| 1410 | { |
| 1411 | PAC_CRITICAL_SECTION_ENTER(); |
| 1412 | ((Pac *)hw)->WRCTRL.reg &= ~mask; |
| 1413 | PAC_CRITICAL_SECTION_LEAVE(); |
| 1414 | } |
| 1415 | |
| 1416 | static inline void hri_pac_toggle_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) |
| 1417 | { |
| 1418 | PAC_CRITICAL_SECTION_ENTER(); |
| 1419 | ((Pac *)hw)->WRCTRL.reg ^= mask; |
| 1420 | PAC_CRITICAL_SECTION_LEAVE(); |
| 1421 | } |
| 1422 | |
| 1423 | static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_reg(const void *const hw) |
| 1424 | { |
| 1425 | return ((Pac *)hw)->WRCTRL.reg; |
| 1426 | } |
| 1427 | |
| 1428 | static inline void hri_pac_set_EVCTRL_ERREO_bit(const void *const hw) |
| 1429 | { |
| 1430 | PAC_CRITICAL_SECTION_ENTER(); |
| 1431 | ((Pac *)hw)->EVCTRL.reg |= PAC_EVCTRL_ERREO; |
| 1432 | PAC_CRITICAL_SECTION_LEAVE(); |
| 1433 | } |
| 1434 | |
| 1435 | static inline bool hri_pac_get_EVCTRL_ERREO_bit(const void *const hw) |
| 1436 | { |
| 1437 | uint8_t tmp; |
| 1438 | tmp = ((Pac *)hw)->EVCTRL.reg; |
| 1439 | tmp = (tmp & PAC_EVCTRL_ERREO) >> PAC_EVCTRL_ERREO_Pos; |
| 1440 | return (bool)tmp; |
| 1441 | } |
| 1442 | |
| 1443 | static inline void hri_pac_write_EVCTRL_ERREO_bit(const void *const hw, bool value) |
| 1444 | { |
| 1445 | uint8_t tmp; |
| 1446 | PAC_CRITICAL_SECTION_ENTER(); |
| 1447 | tmp = ((Pac *)hw)->EVCTRL.reg; |
| 1448 | tmp &= ~PAC_EVCTRL_ERREO; |
| 1449 | tmp |= value << PAC_EVCTRL_ERREO_Pos; |
| 1450 | ((Pac *)hw)->EVCTRL.reg = tmp; |
| 1451 | PAC_CRITICAL_SECTION_LEAVE(); |
| 1452 | } |
| 1453 | |
| 1454 | static inline void hri_pac_clear_EVCTRL_ERREO_bit(const void *const hw) |
| 1455 | { |
| 1456 | PAC_CRITICAL_SECTION_ENTER(); |
| 1457 | ((Pac *)hw)->EVCTRL.reg &= ~PAC_EVCTRL_ERREO; |
| 1458 | PAC_CRITICAL_SECTION_LEAVE(); |
| 1459 | } |
| 1460 | |
| 1461 | static inline void hri_pac_toggle_EVCTRL_ERREO_bit(const void *const hw) |
| 1462 | { |
| 1463 | PAC_CRITICAL_SECTION_ENTER(); |
| 1464 | ((Pac *)hw)->EVCTRL.reg ^= PAC_EVCTRL_ERREO; |
| 1465 | PAC_CRITICAL_SECTION_LEAVE(); |
| 1466 | } |
| 1467 | |
| 1468 | static inline void hri_pac_set_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) |
| 1469 | { |
| 1470 | PAC_CRITICAL_SECTION_ENTER(); |
| 1471 | ((Pac *)hw)->EVCTRL.reg |= mask; |
| 1472 | PAC_CRITICAL_SECTION_LEAVE(); |
| 1473 | } |
| 1474 | |
| 1475 | static inline hri_pac_evctrl_reg_t hri_pac_get_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) |
| 1476 | { |
| 1477 | uint8_t tmp; |
| 1478 | tmp = ((Pac *)hw)->EVCTRL.reg; |
| 1479 | tmp &= mask; |
| 1480 | return tmp; |
| 1481 | } |
| 1482 | |
| 1483 | static inline void hri_pac_write_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t data) |
| 1484 | { |
| 1485 | PAC_CRITICAL_SECTION_ENTER(); |
| 1486 | ((Pac *)hw)->EVCTRL.reg = data; |
| 1487 | PAC_CRITICAL_SECTION_LEAVE(); |
| 1488 | } |
| 1489 | |
| 1490 | static inline void hri_pac_clear_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) |
| 1491 | { |
| 1492 | PAC_CRITICAL_SECTION_ENTER(); |
| 1493 | ((Pac *)hw)->EVCTRL.reg &= ~mask; |
| 1494 | PAC_CRITICAL_SECTION_LEAVE(); |
| 1495 | } |
| 1496 | |
| 1497 | static inline void hri_pac_toggle_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) |
| 1498 | { |
| 1499 | PAC_CRITICAL_SECTION_ENTER(); |
| 1500 | ((Pac *)hw)->EVCTRL.reg ^= mask; |
| 1501 | PAC_CRITICAL_SECTION_LEAVE(); |
| 1502 | } |
| 1503 | |
| 1504 | static inline hri_pac_evctrl_reg_t hri_pac_read_EVCTRL_reg(const void *const hw) |
| 1505 | { |
| 1506 | return ((Pac *)hw)->EVCTRL.reg; |
| 1507 | } |
| 1508 | |
| 1509 | #ifdef __cplusplus |
| 1510 | } |
| 1511 | #endif |
| 1512 | |
| 1513 | #endif /* _HRI_PAC_E54_H_INCLUDED */ |
| 1514 | #endif /* _SAME54_PAC_COMPONENT_ */ |