Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM OSCCTRL |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_OSCCTRL_COMPONENT_ |
| 35 | #ifndef _HRI_OSCCTRL_E54_H_INCLUDED_ |
| 36 | #define _HRI_OSCCTRL_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_OSCCTRL_CRITICAL_SECTIONS) |
| 46 | #define OSCCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define OSCCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define OSCCTRL_CRITICAL_SECTION_ENTER() |
| 50 | #define OSCCTRL_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint32_t hri_oscctrl_dfllmul_reg_t; |
| 54 | typedef uint32_t hri_oscctrl_dfllval_reg_t; |
| 55 | typedef uint32_t hri_oscctrl_dpllctrlb_reg_t; |
| 56 | typedef uint32_t hri_oscctrl_dpllratio_reg_t; |
| 57 | typedef uint32_t hri_oscctrl_dpllstatus_reg_t; |
| 58 | typedef uint32_t hri_oscctrl_dpllsyncbusy_reg_t; |
| 59 | typedef uint32_t hri_oscctrl_intenset_reg_t; |
| 60 | typedef uint32_t hri_oscctrl_intflag_reg_t; |
| 61 | typedef uint32_t hri_oscctrl_status_reg_t; |
| 62 | typedef uint32_t hri_oscctrl_xoscctrl_reg_t; |
| 63 | typedef uint32_t hri_oscctrldpll_dpllctrlb_reg_t; |
| 64 | typedef uint32_t hri_oscctrldpll_dpllratio_reg_t; |
| 65 | typedef uint32_t hri_oscctrldpll_dpllstatus_reg_t; |
| 66 | typedef uint32_t hri_oscctrldpll_dpllsyncbusy_reg_t; |
| 67 | typedef uint8_t hri_oscctrl_dfllctrla_reg_t; |
| 68 | typedef uint8_t hri_oscctrl_dfllctrlb_reg_t; |
| 69 | typedef uint8_t hri_oscctrl_dfllsync_reg_t; |
| 70 | typedef uint8_t hri_oscctrl_dpllctrla_reg_t; |
| 71 | typedef uint8_t hri_oscctrl_evctrl_reg_t; |
| 72 | typedef uint8_t hri_oscctrldpll_dpllctrla_reg_t; |
| 73 | |
| 74 | static inline void hri_oscctrldpll_wait_for_sync(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg) |
| 75 | { |
| 76 | while (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & reg) { |
| 77 | }; |
| 78 | } |
| 79 | |
| 80 | static inline bool hri_oscctrldpll_is_syncing(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg) |
| 81 | { |
| 82 | return ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & reg; |
| 83 | } |
| 84 | |
| 85 | static inline void hri_oscctrl_wait_for_sync(const void *const hw, uint8_t submodule_index, |
| 86 | hri_oscctrl_dpllsyncbusy_reg_t reg) |
| 87 | { |
| 88 | while (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg) { |
| 89 | }; |
| 90 | } |
| 91 | |
| 92 | static inline bool hri_oscctrl_is_syncing(const void *const hw, uint8_t submodule_index, |
| 93 | hri_oscctrl_dpllsyncbusy_reg_t reg) |
| 94 | { |
| 95 | return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg; |
| 96 | } |
| 97 | |
| 98 | static inline bool hri_oscctrldpll_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw) |
| 99 | { |
| 100 | return (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos; |
| 101 | } |
| 102 | |
| 103 | static inline bool hri_oscctrldpll_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw) |
| 104 | { |
| 105 | return (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) |
| 106 | >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos; |
| 107 | } |
| 108 | |
| 109 | static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrldpll_get_DPLLSYNCBUSY_reg(const void *const hw, |
| 110 | hri_oscctrl_dpllsyncbusy_reg_t mask) |
| 111 | { |
| 112 | uint32_t tmp; |
| 113 | tmp = ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg; |
| 114 | tmp &= mask; |
| 115 | return tmp; |
| 116 | } |
| 117 | |
| 118 | static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrldpll_read_DPLLSYNCBUSY_reg(const void *const hw) |
| 119 | { |
| 120 | return ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg; |
| 121 | } |
| 122 | |
| 123 | static inline bool hri_oscctrldpll_get_DPLLSTATUS_LOCK_bit(const void *const hw) |
| 124 | { |
| 125 | return (((OscctrlDpll *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) >> OSCCTRL_DPLLSTATUS_LOCK_Pos; |
| 126 | } |
| 127 | |
| 128 | static inline bool hri_oscctrldpll_get_DPLLSTATUS_CLKRDY_bit(const void *const hw) |
| 129 | { |
| 130 | return (((OscctrlDpll *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos; |
| 131 | } |
| 132 | |
| 133 | static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrldpll_get_DPLLSTATUS_reg(const void *const hw, |
| 134 | hri_oscctrl_dpllstatus_reg_t mask) |
| 135 | { |
| 136 | uint32_t tmp; |
| 137 | tmp = ((OscctrlDpll *)hw)->DPLLSTATUS.reg; |
| 138 | tmp &= mask; |
| 139 | return tmp; |
| 140 | } |
| 141 | |
| 142 | static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrldpll_read_DPLLSTATUS_reg(const void *const hw) |
| 143 | { |
| 144 | return ((OscctrlDpll *)hw)->DPLLSTATUS.reg; |
| 145 | } |
| 146 | |
| 147 | static inline void hri_oscctrldpll_set_DPLLCTRLA_ENABLE_bit(const void *const hw) |
| 148 | { |
| 149 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 150 | ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE; |
| 151 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); |
| 152 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 153 | } |
| 154 | |
| 155 | static inline bool hri_oscctrldpll_get_DPLLCTRLA_ENABLE_bit(const void *const hw) |
| 156 | { |
| 157 | uint8_t tmp; |
| 158 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); |
| 159 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; |
| 160 | tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos; |
| 161 | return (bool)tmp; |
| 162 | } |
| 163 | |
| 164 | static inline void hri_oscctrldpll_write_DPLLCTRLA_ENABLE_bit(const void *const hw, bool value) |
| 165 | { |
| 166 | uint8_t tmp; |
| 167 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 168 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; |
| 169 | tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE; |
| 170 | tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos; |
| 171 | ((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp; |
| 172 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); |
| 173 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 174 | } |
| 175 | |
| 176 | static inline void hri_oscctrldpll_clear_DPLLCTRLA_ENABLE_bit(const void *const hw) |
| 177 | { |
| 178 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 179 | ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE; |
| 180 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); |
| 181 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 182 | } |
| 183 | |
| 184 | static inline void hri_oscctrldpll_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw) |
| 185 | { |
| 186 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 187 | ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE; |
| 188 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); |
| 189 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 190 | } |
| 191 | |
| 192 | static inline void hri_oscctrldpll_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) |
| 193 | { |
| 194 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 195 | ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY; |
| 196 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 197 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 198 | } |
| 199 | |
| 200 | static inline bool hri_oscctrldpll_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) |
| 201 | { |
| 202 | uint8_t tmp; |
| 203 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; |
| 204 | tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; |
| 205 | return (bool)tmp; |
| 206 | } |
| 207 | |
| 208 | static inline void hri_oscctrldpll_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value) |
| 209 | { |
| 210 | uint8_t tmp; |
| 211 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 212 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; |
| 213 | tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; |
| 214 | tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; |
| 215 | ((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp; |
| 216 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 217 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 218 | } |
| 219 | |
| 220 | static inline void hri_oscctrldpll_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) |
| 221 | { |
| 222 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 223 | ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; |
| 224 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 225 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 226 | } |
| 227 | |
| 228 | static inline void hri_oscctrldpll_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) |
| 229 | { |
| 230 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 231 | ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY; |
| 232 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 233 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 234 | } |
| 235 | |
| 236 | static inline void hri_oscctrldpll_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw) |
| 237 | { |
| 238 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 239 | ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND; |
| 240 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 241 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 242 | } |
| 243 | |
| 244 | static inline bool hri_oscctrldpll_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw) |
| 245 | { |
| 246 | uint8_t tmp; |
| 247 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; |
| 248 | tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; |
| 249 | return (bool)tmp; |
| 250 | } |
| 251 | |
| 252 | static inline void hri_oscctrldpll_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, bool value) |
| 253 | { |
| 254 | uint8_t tmp; |
| 255 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 256 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; |
| 257 | tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; |
| 258 | tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; |
| 259 | ((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp; |
| 260 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 261 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 262 | } |
| 263 | |
| 264 | static inline void hri_oscctrldpll_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw) |
| 265 | { |
| 266 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 267 | ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; |
| 268 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 269 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 270 | } |
| 271 | |
| 272 | static inline void hri_oscctrldpll_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw) |
| 273 | { |
| 274 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 275 | ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND; |
| 276 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 277 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 278 | } |
| 279 | |
| 280 | static inline void hri_oscctrldpll_set_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) |
| 281 | { |
| 282 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 283 | ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= mask; |
| 284 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); |
| 285 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 286 | } |
| 287 | |
| 288 | static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrldpll_get_DPLLCTRLA_reg(const void *const hw, |
| 289 | hri_oscctrl_dpllctrla_reg_t mask) |
| 290 | { |
| 291 | uint8_t tmp; |
| 292 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); |
| 293 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; |
| 294 | tmp &= mask; |
| 295 | return tmp; |
| 296 | } |
| 297 | |
| 298 | static inline void hri_oscctrldpll_write_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t data) |
| 299 | { |
| 300 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 301 | ((OscctrlDpll *)hw)->DPLLCTRLA.reg = data; |
| 302 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); |
| 303 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 304 | } |
| 305 | |
| 306 | static inline void hri_oscctrldpll_clear_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) |
| 307 | { |
| 308 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 309 | ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~mask; |
| 310 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); |
| 311 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 312 | } |
| 313 | |
| 314 | static inline void hri_oscctrldpll_toggle_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) |
| 315 | { |
| 316 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 317 | ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= mask; |
| 318 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); |
| 319 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 320 | } |
| 321 | |
| 322 | static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrldpll_read_DPLLCTRLA_reg(const void *const hw) |
| 323 | { |
| 324 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); |
| 325 | return ((OscctrlDpll *)hw)->DPLLCTRLA.reg; |
| 326 | } |
| 327 | |
| 328 | static inline void hri_oscctrldpll_set_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) |
| 329 | { |
| 330 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 331 | ((OscctrlDpll *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask); |
| 332 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 333 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 334 | } |
| 335 | |
| 336 | static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_LDR_bf(const void *const hw, |
| 337 | hri_oscctrl_dpllratio_reg_t mask) |
| 338 | { |
| 339 | uint32_t tmp; |
| 340 | tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; |
| 341 | tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos; |
| 342 | return tmp; |
| 343 | } |
| 344 | |
| 345 | static inline void hri_oscctrldpll_write_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) |
| 346 | { |
| 347 | uint32_t tmp; |
| 348 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 349 | tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; |
| 350 | tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk; |
| 351 | tmp |= OSCCTRL_DPLLRATIO_LDR(data); |
| 352 | ((OscctrlDpll *)hw)->DPLLRATIO.reg = tmp; |
| 353 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 354 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 355 | } |
| 356 | |
| 357 | static inline void hri_oscctrldpll_clear_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) |
| 358 | { |
| 359 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 360 | ((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask); |
| 361 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 362 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 363 | } |
| 364 | |
| 365 | static inline void hri_oscctrldpll_toggle_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) |
| 366 | { |
| 367 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 368 | ((OscctrlDpll *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask); |
| 369 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 370 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 371 | } |
| 372 | |
| 373 | static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_LDR_bf(const void *const hw) |
| 374 | { |
| 375 | uint32_t tmp; |
| 376 | tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; |
| 377 | tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos; |
| 378 | return tmp; |
| 379 | } |
| 380 | |
| 381 | static inline void hri_oscctrldpll_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) |
| 382 | { |
| 383 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 384 | ((OscctrlDpll *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask); |
| 385 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 386 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 387 | } |
| 388 | |
| 389 | static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, |
| 390 | hri_oscctrl_dpllratio_reg_t mask) |
| 391 | { |
| 392 | uint32_t tmp; |
| 393 | tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; |
| 394 | tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; |
| 395 | return tmp; |
| 396 | } |
| 397 | |
| 398 | static inline void hri_oscctrldpll_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) |
| 399 | { |
| 400 | uint32_t tmp; |
| 401 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 402 | tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; |
| 403 | tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk; |
| 404 | tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data); |
| 405 | ((OscctrlDpll *)hw)->DPLLRATIO.reg = tmp; |
| 406 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 407 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 408 | } |
| 409 | |
| 410 | static inline void hri_oscctrldpll_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) |
| 411 | { |
| 412 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 413 | ((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask); |
| 414 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 415 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 416 | } |
| 417 | |
| 418 | static inline void hri_oscctrldpll_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) |
| 419 | { |
| 420 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 421 | ((OscctrlDpll *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask); |
| 422 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 423 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 424 | } |
| 425 | |
| 426 | static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_LDRFRAC_bf(const void *const hw) |
| 427 | { |
| 428 | uint32_t tmp; |
| 429 | tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; |
| 430 | tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; |
| 431 | return tmp; |
| 432 | } |
| 433 | |
| 434 | static inline void hri_oscctrldpll_set_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) |
| 435 | { |
| 436 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 437 | ((OscctrlDpll *)hw)->DPLLRATIO.reg |= mask; |
| 438 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 439 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 440 | } |
| 441 | |
| 442 | static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_reg(const void *const hw, |
| 443 | hri_oscctrl_dpllratio_reg_t mask) |
| 444 | { |
| 445 | uint32_t tmp; |
| 446 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 447 | tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; |
| 448 | tmp &= mask; |
| 449 | return tmp; |
| 450 | } |
| 451 | |
| 452 | static inline void hri_oscctrldpll_write_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t data) |
| 453 | { |
| 454 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 455 | ((OscctrlDpll *)hw)->DPLLRATIO.reg = data; |
| 456 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 457 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 458 | } |
| 459 | |
| 460 | static inline void hri_oscctrldpll_clear_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) |
| 461 | { |
| 462 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 463 | ((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~mask; |
| 464 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 465 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 466 | } |
| 467 | |
| 468 | static inline void hri_oscctrldpll_toggle_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) |
| 469 | { |
| 470 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 471 | ((OscctrlDpll *)hw)->DPLLRATIO.reg ^= mask; |
| 472 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 473 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 474 | } |
| 475 | |
| 476 | static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_reg(const void *const hw) |
| 477 | { |
| 478 | hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 479 | return ((OscctrlDpll *)hw)->DPLLRATIO.reg; |
| 480 | } |
| 481 | |
| 482 | static inline void hri_oscctrldpll_set_DPLLCTRLB_WUF_bit(const void *const hw) |
| 483 | { |
| 484 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 485 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF; |
| 486 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 487 | } |
| 488 | |
| 489 | static inline bool hri_oscctrldpll_get_DPLLCTRLB_WUF_bit(const void *const hw) |
| 490 | { |
| 491 | uint32_t tmp; |
| 492 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; |
| 493 | tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos; |
| 494 | return (bool)tmp; |
| 495 | } |
| 496 | |
| 497 | static inline void hri_oscctrldpll_write_DPLLCTRLB_WUF_bit(const void *const hw, bool value) |
| 498 | { |
| 499 | uint32_t tmp; |
| 500 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 501 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; |
| 502 | tmp &= ~OSCCTRL_DPLLCTRLB_WUF; |
| 503 | tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos; |
| 504 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; |
| 505 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 506 | } |
| 507 | |
| 508 | static inline void hri_oscctrldpll_clear_DPLLCTRLB_WUF_bit(const void *const hw) |
| 509 | { |
| 510 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 511 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF; |
| 512 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 513 | } |
| 514 | |
| 515 | static inline void hri_oscctrldpll_toggle_DPLLCTRLB_WUF_bit(const void *const hw) |
| 516 | { |
| 517 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 518 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF; |
| 519 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 520 | } |
| 521 | |
| 522 | static inline void hri_oscctrldpll_set_DPLLCTRLB_LBYPASS_bit(const void *const hw) |
| 523 | { |
| 524 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 525 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS; |
| 526 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 527 | } |
| 528 | |
| 529 | static inline bool hri_oscctrldpll_get_DPLLCTRLB_LBYPASS_bit(const void *const hw) |
| 530 | { |
| 531 | uint32_t tmp; |
| 532 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; |
| 533 | tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos; |
| 534 | return (bool)tmp; |
| 535 | } |
| 536 | |
| 537 | static inline void hri_oscctrldpll_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, bool value) |
| 538 | { |
| 539 | uint32_t tmp; |
| 540 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 541 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; |
| 542 | tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS; |
| 543 | tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos; |
| 544 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; |
| 545 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 546 | } |
| 547 | |
| 548 | static inline void hri_oscctrldpll_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw) |
| 549 | { |
| 550 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 551 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS; |
| 552 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 553 | } |
| 554 | |
| 555 | static inline void hri_oscctrldpll_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw) |
| 556 | { |
| 557 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 558 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS; |
| 559 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 560 | } |
| 561 | |
| 562 | static inline void hri_oscctrldpll_set_DPLLCTRLB_DCOEN_bit(const void *const hw) |
| 563 | { |
| 564 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 565 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOEN; |
| 566 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 567 | } |
| 568 | |
| 569 | static inline bool hri_oscctrldpll_get_DPLLCTRLB_DCOEN_bit(const void *const hw) |
| 570 | { |
| 571 | uint32_t tmp; |
| 572 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; |
| 573 | tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOEN) >> OSCCTRL_DPLLCTRLB_DCOEN_Pos; |
| 574 | return (bool)tmp; |
| 575 | } |
| 576 | |
| 577 | static inline void hri_oscctrldpll_write_DPLLCTRLB_DCOEN_bit(const void *const hw, bool value) |
| 578 | { |
| 579 | uint32_t tmp; |
| 580 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 581 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; |
| 582 | tmp &= ~OSCCTRL_DPLLCTRLB_DCOEN; |
| 583 | tmp |= value << OSCCTRL_DPLLCTRLB_DCOEN_Pos; |
| 584 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; |
| 585 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 586 | } |
| 587 | |
| 588 | static inline void hri_oscctrldpll_clear_DPLLCTRLB_DCOEN_bit(const void *const hw) |
| 589 | { |
| 590 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 591 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOEN; |
| 592 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 593 | } |
| 594 | |
| 595 | static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DCOEN_bit(const void *const hw) |
| 596 | { |
| 597 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 598 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOEN; |
| 599 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 600 | } |
| 601 | |
| 602 | static inline void hri_oscctrldpll_set_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) |
| 603 | { |
| 604 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 605 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask); |
| 606 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 607 | } |
| 608 | |
| 609 | static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_FILTER_bf(const void *const hw, |
| 610 | hri_oscctrl_dpllctrlb_reg_t mask) |
| 611 | { |
| 612 | uint32_t tmp; |
| 613 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; |
| 614 | tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; |
| 615 | return tmp; |
| 616 | } |
| 617 | |
| 618 | static inline void hri_oscctrldpll_write_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) |
| 619 | { |
| 620 | uint32_t tmp; |
| 621 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 622 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; |
| 623 | tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk; |
| 624 | tmp |= OSCCTRL_DPLLCTRLB_FILTER(data); |
| 625 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; |
| 626 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 627 | } |
| 628 | |
| 629 | static inline void hri_oscctrldpll_clear_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) |
| 630 | { |
| 631 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 632 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask); |
| 633 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 634 | } |
| 635 | |
| 636 | static inline void hri_oscctrldpll_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) |
| 637 | { |
| 638 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 639 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask); |
| 640 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 641 | } |
| 642 | |
| 643 | static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_FILTER_bf(const void *const hw) |
| 644 | { |
| 645 | uint32_t tmp; |
| 646 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; |
| 647 | tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; |
| 648 | return tmp; |
| 649 | } |
| 650 | |
| 651 | static inline void hri_oscctrldpll_set_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) |
| 652 | { |
| 653 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 654 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask); |
| 655 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 656 | } |
| 657 | |
| 658 | static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_REFCLK_bf(const void *const hw, |
| 659 | hri_oscctrl_dpllctrlb_reg_t mask) |
| 660 | { |
| 661 | uint32_t tmp; |
| 662 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; |
| 663 | tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; |
| 664 | return tmp; |
| 665 | } |
| 666 | |
| 667 | static inline void hri_oscctrldpll_write_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) |
| 668 | { |
| 669 | uint32_t tmp; |
| 670 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 671 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; |
| 672 | tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk; |
| 673 | tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data); |
| 674 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; |
| 675 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 676 | } |
| 677 | |
| 678 | static inline void hri_oscctrldpll_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) |
| 679 | { |
| 680 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 681 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask); |
| 682 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 683 | } |
| 684 | |
| 685 | static inline void hri_oscctrldpll_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) |
| 686 | { |
| 687 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 688 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask); |
| 689 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 690 | } |
| 691 | |
| 692 | static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_REFCLK_bf(const void *const hw) |
| 693 | { |
| 694 | uint32_t tmp; |
| 695 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; |
| 696 | tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; |
| 697 | return tmp; |
| 698 | } |
| 699 | |
| 700 | static inline void hri_oscctrldpll_set_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) |
| 701 | { |
| 702 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 703 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask); |
| 704 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 705 | } |
| 706 | |
| 707 | static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_LTIME_bf(const void *const hw, |
| 708 | hri_oscctrl_dpllctrlb_reg_t mask) |
| 709 | { |
| 710 | uint32_t tmp; |
| 711 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; |
| 712 | tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; |
| 713 | return tmp; |
| 714 | } |
| 715 | |
| 716 | static inline void hri_oscctrldpll_write_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) |
| 717 | { |
| 718 | uint32_t tmp; |
| 719 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 720 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; |
| 721 | tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk; |
| 722 | tmp |= OSCCTRL_DPLLCTRLB_LTIME(data); |
| 723 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; |
| 724 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 725 | } |
| 726 | |
| 727 | static inline void hri_oscctrldpll_clear_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) |
| 728 | { |
| 729 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 730 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask); |
| 731 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 732 | } |
| 733 | |
| 734 | static inline void hri_oscctrldpll_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) |
| 735 | { |
| 736 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 737 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask); |
| 738 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 739 | } |
| 740 | |
| 741 | static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_LTIME_bf(const void *const hw) |
| 742 | { |
| 743 | uint32_t tmp; |
| 744 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; |
| 745 | tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; |
| 746 | return tmp; |
| 747 | } |
| 748 | |
| 749 | static inline void hri_oscctrldpll_set_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) |
| 750 | { |
| 751 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 752 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); |
| 753 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 754 | } |
| 755 | |
| 756 | static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_DCOFILTER_bf(const void *const hw, |
| 757 | hri_oscctrl_dpllctrlb_reg_t mask) |
| 758 | { |
| 759 | uint32_t tmp; |
| 760 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; |
| 761 | tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER(mask)) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; |
| 762 | return tmp; |
| 763 | } |
| 764 | |
| 765 | static inline void hri_oscctrldpll_write_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) |
| 766 | { |
| 767 | uint32_t tmp; |
| 768 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 769 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; |
| 770 | tmp &= ~OSCCTRL_DPLLCTRLB_DCOFILTER_Msk; |
| 771 | tmp |= OSCCTRL_DPLLCTRLB_DCOFILTER(data); |
| 772 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; |
| 773 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 774 | } |
| 775 | |
| 776 | static inline void hri_oscctrldpll_clear_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) |
| 777 | { |
| 778 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 779 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOFILTER(mask); |
| 780 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 781 | } |
| 782 | |
| 783 | static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) |
| 784 | { |
| 785 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 786 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); |
| 787 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 788 | } |
| 789 | |
| 790 | static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_DCOFILTER_bf(const void *const hw) |
| 791 | { |
| 792 | uint32_t tmp; |
| 793 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; |
| 794 | tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER_Msk) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; |
| 795 | return tmp; |
| 796 | } |
| 797 | |
| 798 | static inline void hri_oscctrldpll_set_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) |
| 799 | { |
| 800 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 801 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask); |
| 802 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 803 | } |
| 804 | |
| 805 | static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_DIV_bf(const void *const hw, |
| 806 | hri_oscctrl_dpllctrlb_reg_t mask) |
| 807 | { |
| 808 | uint32_t tmp; |
| 809 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; |
| 810 | tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos; |
| 811 | return tmp; |
| 812 | } |
| 813 | |
| 814 | static inline void hri_oscctrldpll_write_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) |
| 815 | { |
| 816 | uint32_t tmp; |
| 817 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 818 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; |
| 819 | tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk; |
| 820 | tmp |= OSCCTRL_DPLLCTRLB_DIV(data); |
| 821 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; |
| 822 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 823 | } |
| 824 | |
| 825 | static inline void hri_oscctrldpll_clear_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) |
| 826 | { |
| 827 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 828 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask); |
| 829 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 830 | } |
| 831 | |
| 832 | static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) |
| 833 | { |
| 834 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 835 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask); |
| 836 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 837 | } |
| 838 | |
| 839 | static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_DIV_bf(const void *const hw) |
| 840 | { |
| 841 | uint32_t tmp; |
| 842 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; |
| 843 | tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos; |
| 844 | return tmp; |
| 845 | } |
| 846 | |
| 847 | static inline void hri_oscctrldpll_set_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) |
| 848 | { |
| 849 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 850 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= mask; |
| 851 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 852 | } |
| 853 | |
| 854 | static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_reg(const void *const hw, |
| 855 | hri_oscctrl_dpllctrlb_reg_t mask) |
| 856 | { |
| 857 | uint32_t tmp; |
| 858 | tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; |
| 859 | tmp &= mask; |
| 860 | return tmp; |
| 861 | } |
| 862 | |
| 863 | static inline void hri_oscctrldpll_write_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) |
| 864 | { |
| 865 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 866 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg = data; |
| 867 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 868 | } |
| 869 | |
| 870 | static inline void hri_oscctrldpll_clear_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) |
| 871 | { |
| 872 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 873 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~mask; |
| 874 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 875 | } |
| 876 | |
| 877 | static inline void hri_oscctrldpll_toggle_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) |
| 878 | { |
| 879 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 880 | ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= mask; |
| 881 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 882 | } |
| 883 | |
| 884 | static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_reg(const void *const hw) |
| 885 | { |
| 886 | return ((OscctrlDpll *)hw)->DPLLCTRLB.reg; |
| 887 | } |
| 888 | |
| 889 | static inline bool hri_oscctrl_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw, uint8_t submodule_index) |
| 890 | { |
| 891 | return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) |
| 892 | >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos; |
| 893 | } |
| 894 | |
| 895 | static inline bool hri_oscctrl_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw, uint8_t submodule_index) |
| 896 | { |
| 897 | return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) |
| 898 | >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos; |
| 899 | } |
| 900 | |
| 901 | static inline hri_oscctrl_dpllsyncbusy_reg_t |
| 902 | hri_oscctrl_get_DPLLSYNCBUSY_reg(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllsyncbusy_reg_t mask) |
| 903 | { |
| 904 | uint32_t tmp; |
| 905 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg; |
| 906 | tmp &= mask; |
| 907 | return tmp; |
| 908 | } |
| 909 | |
| 910 | static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_read_DPLLSYNCBUSY_reg(const void *const hw, |
| 911 | uint8_t submodule_index) |
| 912 | { |
| 913 | return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg; |
| 914 | } |
| 915 | |
| 916 | static inline bool hri_oscctrl_get_DPLLSTATUS_LOCK_bit(const void *const hw, uint8_t submodule_index) |
| 917 | { |
| 918 | return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) |
| 919 | >> OSCCTRL_DPLLSTATUS_LOCK_Pos; |
| 920 | } |
| 921 | |
| 922 | static inline bool hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(const void *const hw, uint8_t submodule_index) |
| 923 | { |
| 924 | return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) |
| 925 | >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos; |
| 926 | } |
| 927 | |
| 928 | static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_get_DPLLSTATUS_reg(const void *const hw, uint8_t submodule_index, |
| 929 | hri_oscctrl_dpllstatus_reg_t mask) |
| 930 | { |
| 931 | uint32_t tmp; |
| 932 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg; |
| 933 | tmp &= mask; |
| 934 | return tmp; |
| 935 | } |
| 936 | |
| 937 | static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_read_DPLLSTATUS_reg(const void *const hw, |
| 938 | uint8_t submodule_index) |
| 939 | { |
| 940 | return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg; |
| 941 | } |
| 942 | |
| 943 | static inline void hri_oscctrl_set_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) |
| 944 | { |
| 945 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 946 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE; |
| 947 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); |
| 948 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 949 | } |
| 950 | |
| 951 | static inline bool hri_oscctrl_get_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) |
| 952 | { |
| 953 | uint8_t tmp; |
| 954 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); |
| 955 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; |
| 956 | tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos; |
| 957 | return (bool)tmp; |
| 958 | } |
| 959 | |
| 960 | static inline void hri_oscctrl_write_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index, bool value) |
| 961 | { |
| 962 | uint8_t tmp; |
| 963 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 964 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; |
| 965 | tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE; |
| 966 | tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos; |
| 967 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp; |
| 968 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); |
| 969 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 970 | } |
| 971 | |
| 972 | static inline void hri_oscctrl_clear_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) |
| 973 | { |
| 974 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 975 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE; |
| 976 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); |
| 977 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 978 | } |
| 979 | |
| 980 | static inline void hri_oscctrl_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) |
| 981 | { |
| 982 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 983 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE; |
| 984 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); |
| 985 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 986 | } |
| 987 | |
| 988 | static inline void hri_oscctrl_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) |
| 989 | { |
| 990 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 991 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY; |
| 992 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 993 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 994 | } |
| 995 | |
| 996 | static inline bool hri_oscctrl_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) |
| 997 | { |
| 998 | uint8_t tmp; |
| 999 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; |
| 1000 | tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; |
| 1001 | return (bool)tmp; |
| 1002 | } |
| 1003 | |
| 1004 | static inline void hri_oscctrl_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value) |
| 1005 | { |
| 1006 | uint8_t tmp; |
| 1007 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1008 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; |
| 1009 | tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; |
| 1010 | tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; |
| 1011 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp; |
| 1012 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 1013 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1014 | } |
| 1015 | |
| 1016 | static inline void hri_oscctrl_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) |
| 1017 | { |
| 1018 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1019 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; |
| 1020 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 1021 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1022 | } |
| 1023 | |
| 1024 | static inline void hri_oscctrl_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) |
| 1025 | { |
| 1026 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1027 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY; |
| 1028 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 1029 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1030 | } |
| 1031 | |
| 1032 | static inline void hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) |
| 1033 | { |
| 1034 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1035 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND; |
| 1036 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 1037 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1038 | } |
| 1039 | |
| 1040 | static inline bool hri_oscctrl_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) |
| 1041 | { |
| 1042 | uint8_t tmp; |
| 1043 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; |
| 1044 | tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; |
| 1045 | return (bool)tmp; |
| 1046 | } |
| 1047 | |
| 1048 | static inline void hri_oscctrl_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index, bool value) |
| 1049 | { |
| 1050 | uint8_t tmp; |
| 1051 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1052 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; |
| 1053 | tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; |
| 1054 | tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; |
| 1055 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp; |
| 1056 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 1057 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1058 | } |
| 1059 | |
| 1060 | static inline void hri_oscctrl_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) |
| 1061 | { |
| 1062 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1063 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; |
| 1064 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 1065 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1066 | } |
| 1067 | |
| 1068 | static inline void hri_oscctrl_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) |
| 1069 | { |
| 1070 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1071 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND; |
| 1072 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 1073 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1074 | } |
| 1075 | |
| 1076 | static inline void hri_oscctrl_set_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, |
| 1077 | hri_oscctrl_dpllctrla_reg_t mask) |
| 1078 | { |
| 1079 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1080 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= mask; |
| 1081 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); |
| 1082 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1083 | } |
| 1084 | |
| 1085 | static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_get_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, |
| 1086 | hri_oscctrl_dpllctrla_reg_t mask) |
| 1087 | { |
| 1088 | uint8_t tmp; |
| 1089 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); |
| 1090 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; |
| 1091 | tmp &= mask; |
| 1092 | return tmp; |
| 1093 | } |
| 1094 | |
| 1095 | static inline void hri_oscctrl_write_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, |
| 1096 | hri_oscctrl_dpllctrla_reg_t data) |
| 1097 | { |
| 1098 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1099 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = data; |
| 1100 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); |
| 1101 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1102 | } |
| 1103 | |
| 1104 | static inline void hri_oscctrl_clear_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, |
| 1105 | hri_oscctrl_dpllctrla_reg_t mask) |
| 1106 | { |
| 1107 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1108 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~mask; |
| 1109 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); |
| 1110 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1111 | } |
| 1112 | |
| 1113 | static inline void hri_oscctrl_toggle_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, |
| 1114 | hri_oscctrl_dpllctrla_reg_t mask) |
| 1115 | { |
| 1116 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1117 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= mask; |
| 1118 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); |
| 1119 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1120 | } |
| 1121 | |
| 1122 | static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_read_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index) |
| 1123 | { |
| 1124 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); |
| 1125 | return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; |
| 1126 | } |
| 1127 | |
| 1128 | static inline void hri_oscctrl_set_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, |
| 1129 | hri_oscctrl_dpllratio_reg_t mask) |
| 1130 | { |
| 1131 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1132 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask); |
| 1133 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 1134 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1135 | } |
| 1136 | |
| 1137 | static inline hri_oscctrl_dpllratio_reg_t |
| 1138 | hri_oscctrl_get_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllratio_reg_t mask) |
| 1139 | { |
| 1140 | uint32_t tmp; |
| 1141 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; |
| 1142 | tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos; |
| 1143 | return tmp; |
| 1144 | } |
| 1145 | |
| 1146 | static inline void hri_oscctrl_write_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, |
| 1147 | hri_oscctrl_dpllratio_reg_t data) |
| 1148 | { |
| 1149 | uint32_t tmp; |
| 1150 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1151 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; |
| 1152 | tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk; |
| 1153 | tmp |= OSCCTRL_DPLLRATIO_LDR(data); |
| 1154 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = tmp; |
| 1155 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 1156 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1157 | } |
| 1158 | |
| 1159 | static inline void hri_oscctrl_clear_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, |
| 1160 | hri_oscctrl_dpllratio_reg_t mask) |
| 1161 | { |
| 1162 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1163 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask); |
| 1164 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 1165 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1166 | } |
| 1167 | |
| 1168 | static inline void hri_oscctrl_toggle_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, |
| 1169 | hri_oscctrl_dpllratio_reg_t mask) |
| 1170 | { |
| 1171 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1172 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask); |
| 1173 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 1174 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1175 | } |
| 1176 | |
| 1177 | static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDR_bf(const void *const hw, |
| 1178 | uint8_t submodule_index) |
| 1179 | { |
| 1180 | uint32_t tmp; |
| 1181 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; |
| 1182 | tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos; |
| 1183 | return tmp; |
| 1184 | } |
| 1185 | |
| 1186 | static inline void hri_oscctrl_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, |
| 1187 | hri_oscctrl_dpllratio_reg_t mask) |
| 1188 | { |
| 1189 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1190 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask); |
| 1191 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 1192 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1193 | } |
| 1194 | |
| 1195 | static inline hri_oscctrl_dpllratio_reg_t |
| 1196 | hri_oscctrl_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllratio_reg_t mask) |
| 1197 | { |
| 1198 | uint32_t tmp; |
| 1199 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; |
| 1200 | tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; |
| 1201 | return tmp; |
| 1202 | } |
| 1203 | |
| 1204 | static inline void hri_oscctrl_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, |
| 1205 | hri_oscctrl_dpllratio_reg_t data) |
| 1206 | { |
| 1207 | uint32_t tmp; |
| 1208 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1209 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; |
| 1210 | tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk; |
| 1211 | tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data); |
| 1212 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = tmp; |
| 1213 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 1214 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1215 | } |
| 1216 | |
| 1217 | static inline void hri_oscctrl_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, |
| 1218 | hri_oscctrl_dpllratio_reg_t mask) |
| 1219 | { |
| 1220 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1221 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask); |
| 1222 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 1223 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1224 | } |
| 1225 | |
| 1226 | static inline void hri_oscctrl_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, |
| 1227 | hri_oscctrl_dpllratio_reg_t mask) |
| 1228 | { |
| 1229 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1230 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask); |
| 1231 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 1232 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1233 | } |
| 1234 | |
| 1235 | static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDRFRAC_bf(const void *const hw, |
| 1236 | uint8_t submodule_index) |
| 1237 | { |
| 1238 | uint32_t tmp; |
| 1239 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; |
| 1240 | tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; |
| 1241 | return tmp; |
| 1242 | } |
| 1243 | |
| 1244 | static inline void hri_oscctrl_set_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, |
| 1245 | hri_oscctrl_dpllratio_reg_t mask) |
| 1246 | { |
| 1247 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1248 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= mask; |
| 1249 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 1250 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1251 | } |
| 1252 | |
| 1253 | static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, |
| 1254 | hri_oscctrl_dpllratio_reg_t mask) |
| 1255 | { |
| 1256 | uint32_t tmp; |
| 1257 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 1258 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; |
| 1259 | tmp &= mask; |
| 1260 | return tmp; |
| 1261 | } |
| 1262 | |
| 1263 | static inline void hri_oscctrl_write_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, |
| 1264 | hri_oscctrl_dpllratio_reg_t data) |
| 1265 | { |
| 1266 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1267 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = data; |
| 1268 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 1269 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1270 | } |
| 1271 | |
| 1272 | static inline void hri_oscctrl_clear_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, |
| 1273 | hri_oscctrl_dpllratio_reg_t mask) |
| 1274 | { |
| 1275 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1276 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~mask; |
| 1277 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 1278 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1279 | } |
| 1280 | |
| 1281 | static inline void hri_oscctrl_toggle_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, |
| 1282 | hri_oscctrl_dpllratio_reg_t mask) |
| 1283 | { |
| 1284 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1285 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= mask; |
| 1286 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 1287 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1288 | } |
| 1289 | |
| 1290 | static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index) |
| 1291 | { |
| 1292 | hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); |
| 1293 | return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; |
| 1294 | } |
| 1295 | |
| 1296 | static inline void hri_oscctrl_set_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) |
| 1297 | { |
| 1298 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1299 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF; |
| 1300 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1301 | } |
| 1302 | |
| 1303 | static inline bool hri_oscctrl_get_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) |
| 1304 | { |
| 1305 | uint32_t tmp; |
| 1306 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; |
| 1307 | tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos; |
| 1308 | return (bool)tmp; |
| 1309 | } |
| 1310 | |
| 1311 | static inline void hri_oscctrl_write_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index, bool value) |
| 1312 | { |
| 1313 | uint32_t tmp; |
| 1314 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1315 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; |
| 1316 | tmp &= ~OSCCTRL_DPLLCTRLB_WUF; |
| 1317 | tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos; |
| 1318 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; |
| 1319 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1320 | } |
| 1321 | |
| 1322 | static inline void hri_oscctrl_clear_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) |
| 1323 | { |
| 1324 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1325 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF; |
| 1326 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1327 | } |
| 1328 | |
| 1329 | static inline void hri_oscctrl_toggle_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) |
| 1330 | { |
| 1331 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1332 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF; |
| 1333 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1334 | } |
| 1335 | |
| 1336 | static inline void hri_oscctrl_set_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) |
| 1337 | { |
| 1338 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1339 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS; |
| 1340 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1341 | } |
| 1342 | |
| 1343 | static inline bool hri_oscctrl_get_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) |
| 1344 | { |
| 1345 | uint32_t tmp; |
| 1346 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; |
| 1347 | tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos; |
| 1348 | return (bool)tmp; |
| 1349 | } |
| 1350 | |
| 1351 | static inline void hri_oscctrl_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index, bool value) |
| 1352 | { |
| 1353 | uint32_t tmp; |
| 1354 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1355 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; |
| 1356 | tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS; |
| 1357 | tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos; |
| 1358 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; |
| 1359 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1360 | } |
| 1361 | |
| 1362 | static inline void hri_oscctrl_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) |
| 1363 | { |
| 1364 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1365 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS; |
| 1366 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1367 | } |
| 1368 | |
| 1369 | static inline void hri_oscctrl_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) |
| 1370 | { |
| 1371 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1372 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS; |
| 1373 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1374 | } |
| 1375 | |
| 1376 | static inline void hri_oscctrl_set_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) |
| 1377 | { |
| 1378 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1379 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOEN; |
| 1380 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1381 | } |
| 1382 | |
| 1383 | static inline bool hri_oscctrl_get_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) |
| 1384 | { |
| 1385 | uint32_t tmp; |
| 1386 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; |
| 1387 | tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOEN) >> OSCCTRL_DPLLCTRLB_DCOEN_Pos; |
| 1388 | return (bool)tmp; |
| 1389 | } |
| 1390 | |
| 1391 | static inline void hri_oscctrl_write_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index, bool value) |
| 1392 | { |
| 1393 | uint32_t tmp; |
| 1394 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1395 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; |
| 1396 | tmp &= ~OSCCTRL_DPLLCTRLB_DCOEN; |
| 1397 | tmp |= value << OSCCTRL_DPLLCTRLB_DCOEN_Pos; |
| 1398 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; |
| 1399 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1400 | } |
| 1401 | |
| 1402 | static inline void hri_oscctrl_clear_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) |
| 1403 | { |
| 1404 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1405 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOEN; |
| 1406 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1407 | } |
| 1408 | |
| 1409 | static inline void hri_oscctrl_toggle_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) |
| 1410 | { |
| 1411 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1412 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOEN; |
| 1413 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1414 | } |
| 1415 | |
| 1416 | static inline void hri_oscctrl_set_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, |
| 1417 | hri_oscctrl_dpllctrlb_reg_t mask) |
| 1418 | { |
| 1419 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1420 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask); |
| 1421 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1422 | } |
| 1423 | |
| 1424 | static inline hri_oscctrl_dpllctrlb_reg_t |
| 1425 | hri_oscctrl_get_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) |
| 1426 | { |
| 1427 | uint32_t tmp; |
| 1428 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; |
| 1429 | tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; |
| 1430 | return tmp; |
| 1431 | } |
| 1432 | |
| 1433 | static inline void hri_oscctrl_write_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, |
| 1434 | hri_oscctrl_dpllctrlb_reg_t data) |
| 1435 | { |
| 1436 | uint32_t tmp; |
| 1437 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1438 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; |
| 1439 | tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk; |
| 1440 | tmp |= OSCCTRL_DPLLCTRLB_FILTER(data); |
| 1441 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; |
| 1442 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1443 | } |
| 1444 | |
| 1445 | static inline void hri_oscctrl_clear_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, |
| 1446 | hri_oscctrl_dpllctrlb_reg_t mask) |
| 1447 | { |
| 1448 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1449 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask); |
| 1450 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1451 | } |
| 1452 | |
| 1453 | static inline void hri_oscctrl_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, |
| 1454 | hri_oscctrl_dpllctrlb_reg_t mask) |
| 1455 | { |
| 1456 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1457 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask); |
| 1458 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1459 | } |
| 1460 | |
| 1461 | static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_FILTER_bf(const void *const hw, |
| 1462 | uint8_t submodule_index) |
| 1463 | { |
| 1464 | uint32_t tmp; |
| 1465 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; |
| 1466 | tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; |
| 1467 | return tmp; |
| 1468 | } |
| 1469 | |
| 1470 | static inline void hri_oscctrl_set_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, |
| 1471 | hri_oscctrl_dpllctrlb_reg_t mask) |
| 1472 | { |
| 1473 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1474 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask); |
| 1475 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1476 | } |
| 1477 | |
| 1478 | static inline hri_oscctrl_dpllctrlb_reg_t |
| 1479 | hri_oscctrl_get_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) |
| 1480 | { |
| 1481 | uint32_t tmp; |
| 1482 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; |
| 1483 | tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; |
| 1484 | return tmp; |
| 1485 | } |
| 1486 | |
| 1487 | static inline void hri_oscctrl_write_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, |
| 1488 | hri_oscctrl_dpllctrlb_reg_t data) |
| 1489 | { |
| 1490 | uint32_t tmp; |
| 1491 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1492 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; |
| 1493 | tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk; |
| 1494 | tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data); |
| 1495 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; |
| 1496 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1497 | } |
| 1498 | |
| 1499 | static inline void hri_oscctrl_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, |
| 1500 | hri_oscctrl_dpllctrlb_reg_t mask) |
| 1501 | { |
| 1502 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1503 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask); |
| 1504 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1505 | } |
| 1506 | |
| 1507 | static inline void hri_oscctrl_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, |
| 1508 | hri_oscctrl_dpllctrlb_reg_t mask) |
| 1509 | { |
| 1510 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1511 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask); |
| 1512 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1513 | } |
| 1514 | |
| 1515 | static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_REFCLK_bf(const void *const hw, |
| 1516 | uint8_t submodule_index) |
| 1517 | { |
| 1518 | uint32_t tmp; |
| 1519 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; |
| 1520 | tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; |
| 1521 | return tmp; |
| 1522 | } |
| 1523 | |
| 1524 | static inline void hri_oscctrl_set_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, |
| 1525 | hri_oscctrl_dpllctrlb_reg_t mask) |
| 1526 | { |
| 1527 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1528 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask); |
| 1529 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1530 | } |
| 1531 | |
| 1532 | static inline hri_oscctrl_dpllctrlb_reg_t |
| 1533 | hri_oscctrl_get_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) |
| 1534 | { |
| 1535 | uint32_t tmp; |
| 1536 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; |
| 1537 | tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; |
| 1538 | return tmp; |
| 1539 | } |
| 1540 | |
| 1541 | static inline void hri_oscctrl_write_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, |
| 1542 | hri_oscctrl_dpllctrlb_reg_t data) |
| 1543 | { |
| 1544 | uint32_t tmp; |
| 1545 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1546 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; |
| 1547 | tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk; |
| 1548 | tmp |= OSCCTRL_DPLLCTRLB_LTIME(data); |
| 1549 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; |
| 1550 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1551 | } |
| 1552 | |
| 1553 | static inline void hri_oscctrl_clear_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, |
| 1554 | hri_oscctrl_dpllctrlb_reg_t mask) |
| 1555 | { |
| 1556 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1557 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask); |
| 1558 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1559 | } |
| 1560 | |
| 1561 | static inline void hri_oscctrl_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, |
| 1562 | hri_oscctrl_dpllctrlb_reg_t mask) |
| 1563 | { |
| 1564 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1565 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask); |
| 1566 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1567 | } |
| 1568 | |
| 1569 | static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_LTIME_bf(const void *const hw, |
| 1570 | uint8_t submodule_index) |
| 1571 | { |
| 1572 | uint32_t tmp; |
| 1573 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; |
| 1574 | tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; |
| 1575 | return tmp; |
| 1576 | } |
| 1577 | |
| 1578 | static inline void hri_oscctrl_set_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, |
| 1579 | hri_oscctrl_dpllctrlb_reg_t mask) |
| 1580 | { |
| 1581 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1582 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); |
| 1583 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1584 | } |
| 1585 | |
| 1586 | static inline hri_oscctrl_dpllctrlb_reg_t |
| 1587 | hri_oscctrl_get_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) |
| 1588 | { |
| 1589 | uint32_t tmp; |
| 1590 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; |
| 1591 | tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER(mask)) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; |
| 1592 | return tmp; |
| 1593 | } |
| 1594 | |
| 1595 | static inline void hri_oscctrl_write_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, |
| 1596 | hri_oscctrl_dpllctrlb_reg_t data) |
| 1597 | { |
| 1598 | uint32_t tmp; |
| 1599 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1600 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; |
| 1601 | tmp &= ~OSCCTRL_DPLLCTRLB_DCOFILTER_Msk; |
| 1602 | tmp |= OSCCTRL_DPLLCTRLB_DCOFILTER(data); |
| 1603 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; |
| 1604 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1605 | } |
| 1606 | |
| 1607 | static inline void hri_oscctrl_clear_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, |
| 1608 | hri_oscctrl_dpllctrlb_reg_t mask) |
| 1609 | { |
| 1610 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1611 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOFILTER(mask); |
| 1612 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1613 | } |
| 1614 | |
| 1615 | static inline void hri_oscctrl_toggle_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, |
| 1616 | hri_oscctrl_dpllctrlb_reg_t mask) |
| 1617 | { |
| 1618 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1619 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); |
| 1620 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1621 | } |
| 1622 | |
| 1623 | static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DCOFILTER_bf(const void *const hw, |
| 1624 | uint8_t submodule_index) |
| 1625 | { |
| 1626 | uint32_t tmp; |
| 1627 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; |
| 1628 | tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER_Msk) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; |
| 1629 | return tmp; |
| 1630 | } |
| 1631 | |
| 1632 | static inline void hri_oscctrl_set_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, |
| 1633 | hri_oscctrl_dpllctrlb_reg_t mask) |
| 1634 | { |
| 1635 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1636 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask); |
| 1637 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1638 | } |
| 1639 | |
| 1640 | static inline hri_oscctrl_dpllctrlb_reg_t |
| 1641 | hri_oscctrl_get_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) |
| 1642 | { |
| 1643 | uint32_t tmp; |
| 1644 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; |
| 1645 | tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos; |
| 1646 | return tmp; |
| 1647 | } |
| 1648 | |
| 1649 | static inline void hri_oscctrl_write_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, |
| 1650 | hri_oscctrl_dpllctrlb_reg_t data) |
| 1651 | { |
| 1652 | uint32_t tmp; |
| 1653 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1654 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; |
| 1655 | tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk; |
| 1656 | tmp |= OSCCTRL_DPLLCTRLB_DIV(data); |
| 1657 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; |
| 1658 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1659 | } |
| 1660 | |
| 1661 | static inline void hri_oscctrl_clear_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, |
| 1662 | hri_oscctrl_dpllctrlb_reg_t mask) |
| 1663 | { |
| 1664 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1665 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask); |
| 1666 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1667 | } |
| 1668 | |
| 1669 | static inline void hri_oscctrl_toggle_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, |
| 1670 | hri_oscctrl_dpllctrlb_reg_t mask) |
| 1671 | { |
| 1672 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1673 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask); |
| 1674 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1675 | } |
| 1676 | |
| 1677 | static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DIV_bf(const void *const hw, |
| 1678 | uint8_t submodule_index) |
| 1679 | { |
| 1680 | uint32_t tmp; |
| 1681 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; |
| 1682 | tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos; |
| 1683 | return tmp; |
| 1684 | } |
| 1685 | |
| 1686 | static inline void hri_oscctrl_set_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, |
| 1687 | hri_oscctrl_dpllctrlb_reg_t mask) |
| 1688 | { |
| 1689 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1690 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= mask; |
| 1691 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1692 | } |
| 1693 | |
| 1694 | static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, |
| 1695 | hri_oscctrl_dpllctrlb_reg_t mask) |
| 1696 | { |
| 1697 | uint32_t tmp; |
| 1698 | tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; |
| 1699 | tmp &= mask; |
| 1700 | return tmp; |
| 1701 | } |
| 1702 | |
| 1703 | static inline void hri_oscctrl_write_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, |
| 1704 | hri_oscctrl_dpllctrlb_reg_t data) |
| 1705 | { |
| 1706 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1707 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = data; |
| 1708 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1709 | } |
| 1710 | |
| 1711 | static inline void hri_oscctrl_clear_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, |
| 1712 | hri_oscctrl_dpllctrlb_reg_t mask) |
| 1713 | { |
| 1714 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1715 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~mask; |
| 1716 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1717 | } |
| 1718 | |
| 1719 | static inline void hri_oscctrl_toggle_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, |
| 1720 | hri_oscctrl_dpllctrlb_reg_t mask) |
| 1721 | { |
| 1722 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 1723 | ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= mask; |
| 1724 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 1725 | } |
| 1726 | |
| 1727 | static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index) |
| 1728 | { |
| 1729 | return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; |
| 1730 | } |
| 1731 | |
| 1732 | static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY0_bit(const void *const hw) |
| 1733 | { |
| 1734 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY0) >> OSCCTRL_INTFLAG_XOSCRDY0_Pos; |
| 1735 | } |
| 1736 | |
| 1737 | static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY0_bit(const void *const hw) |
| 1738 | { |
| 1739 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY0; |
| 1740 | } |
| 1741 | |
| 1742 | static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY1_bit(const void *const hw) |
| 1743 | { |
| 1744 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY1) >> OSCCTRL_INTFLAG_XOSCRDY1_Pos; |
| 1745 | } |
| 1746 | |
| 1747 | static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY1_bit(const void *const hw) |
| 1748 | { |
| 1749 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY1; |
| 1750 | } |
| 1751 | |
| 1752 | static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL0_bit(const void *const hw) |
| 1753 | { |
| 1754 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL0) >> OSCCTRL_INTFLAG_XOSCFAIL0_Pos; |
| 1755 | } |
| 1756 | |
| 1757 | static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL0_bit(const void *const hw) |
| 1758 | { |
| 1759 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL0; |
| 1760 | } |
| 1761 | |
| 1762 | static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL1_bit(const void *const hw) |
| 1763 | { |
| 1764 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL1) >> OSCCTRL_INTFLAG_XOSCFAIL1_Pos; |
| 1765 | } |
| 1766 | |
| 1767 | static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL1_bit(const void *const hw) |
| 1768 | { |
| 1769 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL1; |
| 1770 | } |
| 1771 | |
| 1772 | static inline bool hri_oscctrl_get_INTFLAG_DFLLRDY_bit(const void *const hw) |
| 1773 | { |
| 1774 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos; |
| 1775 | } |
| 1776 | |
| 1777 | static inline void hri_oscctrl_clear_INTFLAG_DFLLRDY_bit(const void *const hw) |
| 1778 | { |
| 1779 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; |
| 1780 | } |
| 1781 | |
| 1782 | static inline bool hri_oscctrl_get_INTFLAG_DFLLOOB_bit(const void *const hw) |
| 1783 | { |
| 1784 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos; |
| 1785 | } |
| 1786 | |
| 1787 | static inline void hri_oscctrl_clear_INTFLAG_DFLLOOB_bit(const void *const hw) |
| 1788 | { |
| 1789 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB; |
| 1790 | } |
| 1791 | |
| 1792 | static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKF_bit(const void *const hw) |
| 1793 | { |
| 1794 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos; |
| 1795 | } |
| 1796 | |
| 1797 | static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKF_bit(const void *const hw) |
| 1798 | { |
| 1799 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF; |
| 1800 | } |
| 1801 | |
| 1802 | static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKC_bit(const void *const hw) |
| 1803 | { |
| 1804 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos; |
| 1805 | } |
| 1806 | |
| 1807 | static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKC_bit(const void *const hw) |
| 1808 | { |
| 1809 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC; |
| 1810 | } |
| 1811 | |
| 1812 | static inline bool hri_oscctrl_get_INTFLAG_DFLLRCS_bit(const void *const hw) |
| 1813 | { |
| 1814 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos; |
| 1815 | } |
| 1816 | |
| 1817 | static inline void hri_oscctrl_clear_INTFLAG_DFLLRCS_bit(const void *const hw) |
| 1818 | { |
| 1819 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS; |
| 1820 | } |
| 1821 | |
| 1822 | static inline bool hri_oscctrl_get_INTFLAG_DPLL0LCKR_bit(const void *const hw) |
| 1823 | { |
| 1824 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKR) >> OSCCTRL_INTFLAG_DPLL0LCKR_Pos; |
| 1825 | } |
| 1826 | |
| 1827 | static inline void hri_oscctrl_clear_INTFLAG_DPLL0LCKR_bit(const void *const hw) |
| 1828 | { |
| 1829 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKR; |
| 1830 | } |
| 1831 | |
| 1832 | static inline bool hri_oscctrl_get_INTFLAG_DPLL0LCKF_bit(const void *const hw) |
| 1833 | { |
| 1834 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKF) >> OSCCTRL_INTFLAG_DPLL0LCKF_Pos; |
| 1835 | } |
| 1836 | |
| 1837 | static inline void hri_oscctrl_clear_INTFLAG_DPLL0LCKF_bit(const void *const hw) |
| 1838 | { |
| 1839 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKF; |
| 1840 | } |
| 1841 | |
| 1842 | static inline bool hri_oscctrl_get_INTFLAG_DPLL0LTO_bit(const void *const hw) |
| 1843 | { |
| 1844 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LTO) >> OSCCTRL_INTFLAG_DPLL0LTO_Pos; |
| 1845 | } |
| 1846 | |
| 1847 | static inline void hri_oscctrl_clear_INTFLAG_DPLL0LTO_bit(const void *const hw) |
| 1848 | { |
| 1849 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LTO; |
| 1850 | } |
| 1851 | |
| 1852 | static inline bool hri_oscctrl_get_INTFLAG_DPLL0LDRTO_bit(const void *const hw) |
| 1853 | { |
| 1854 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LDRTO) >> OSCCTRL_INTFLAG_DPLL0LDRTO_Pos; |
| 1855 | } |
| 1856 | |
| 1857 | static inline void hri_oscctrl_clear_INTFLAG_DPLL0LDRTO_bit(const void *const hw) |
| 1858 | { |
| 1859 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LDRTO; |
| 1860 | } |
| 1861 | |
| 1862 | static inline bool hri_oscctrl_get_INTFLAG_DPLL1LCKR_bit(const void *const hw) |
| 1863 | { |
| 1864 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKR) >> OSCCTRL_INTFLAG_DPLL1LCKR_Pos; |
| 1865 | } |
| 1866 | |
| 1867 | static inline void hri_oscctrl_clear_INTFLAG_DPLL1LCKR_bit(const void *const hw) |
| 1868 | { |
| 1869 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKR; |
| 1870 | } |
| 1871 | |
| 1872 | static inline bool hri_oscctrl_get_INTFLAG_DPLL1LCKF_bit(const void *const hw) |
| 1873 | { |
| 1874 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKF) >> OSCCTRL_INTFLAG_DPLL1LCKF_Pos; |
| 1875 | } |
| 1876 | |
| 1877 | static inline void hri_oscctrl_clear_INTFLAG_DPLL1LCKF_bit(const void *const hw) |
| 1878 | { |
| 1879 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKF; |
| 1880 | } |
| 1881 | |
| 1882 | static inline bool hri_oscctrl_get_INTFLAG_DPLL1LTO_bit(const void *const hw) |
| 1883 | { |
| 1884 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LTO) >> OSCCTRL_INTFLAG_DPLL1LTO_Pos; |
| 1885 | } |
| 1886 | |
| 1887 | static inline void hri_oscctrl_clear_INTFLAG_DPLL1LTO_bit(const void *const hw) |
| 1888 | { |
| 1889 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LTO; |
| 1890 | } |
| 1891 | |
| 1892 | static inline bool hri_oscctrl_get_INTFLAG_DPLL1LDRTO_bit(const void *const hw) |
| 1893 | { |
| 1894 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LDRTO) >> OSCCTRL_INTFLAG_DPLL1LDRTO_Pos; |
| 1895 | } |
| 1896 | |
| 1897 | static inline void hri_oscctrl_clear_INTFLAG_DPLL1LDRTO_bit(const void *const hw) |
| 1898 | { |
| 1899 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LDRTO; |
| 1900 | } |
| 1901 | |
| 1902 | static inline bool hri_oscctrl_get_interrupt_XOSCRDY0_bit(const void *const hw) |
| 1903 | { |
| 1904 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY0) >> OSCCTRL_INTFLAG_XOSCRDY0_Pos; |
| 1905 | } |
| 1906 | |
| 1907 | static inline void hri_oscctrl_clear_interrupt_XOSCRDY0_bit(const void *const hw) |
| 1908 | { |
| 1909 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY0; |
| 1910 | } |
| 1911 | |
| 1912 | static inline bool hri_oscctrl_get_interrupt_XOSCRDY1_bit(const void *const hw) |
| 1913 | { |
| 1914 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY1) >> OSCCTRL_INTFLAG_XOSCRDY1_Pos; |
| 1915 | } |
| 1916 | |
| 1917 | static inline void hri_oscctrl_clear_interrupt_XOSCRDY1_bit(const void *const hw) |
| 1918 | { |
| 1919 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY1; |
| 1920 | } |
| 1921 | |
| 1922 | static inline bool hri_oscctrl_get_interrupt_XOSCFAIL0_bit(const void *const hw) |
| 1923 | { |
| 1924 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL0) >> OSCCTRL_INTFLAG_XOSCFAIL0_Pos; |
| 1925 | } |
| 1926 | |
| 1927 | static inline void hri_oscctrl_clear_interrupt_XOSCFAIL0_bit(const void *const hw) |
| 1928 | { |
| 1929 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL0; |
| 1930 | } |
| 1931 | |
| 1932 | static inline bool hri_oscctrl_get_interrupt_XOSCFAIL1_bit(const void *const hw) |
| 1933 | { |
| 1934 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL1) >> OSCCTRL_INTFLAG_XOSCFAIL1_Pos; |
| 1935 | } |
| 1936 | |
| 1937 | static inline void hri_oscctrl_clear_interrupt_XOSCFAIL1_bit(const void *const hw) |
| 1938 | { |
| 1939 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL1; |
| 1940 | } |
| 1941 | |
| 1942 | static inline bool hri_oscctrl_get_interrupt_DFLLRDY_bit(const void *const hw) |
| 1943 | { |
| 1944 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos; |
| 1945 | } |
| 1946 | |
| 1947 | static inline void hri_oscctrl_clear_interrupt_DFLLRDY_bit(const void *const hw) |
| 1948 | { |
| 1949 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; |
| 1950 | } |
| 1951 | |
| 1952 | static inline bool hri_oscctrl_get_interrupt_DFLLOOB_bit(const void *const hw) |
| 1953 | { |
| 1954 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos; |
| 1955 | } |
| 1956 | |
| 1957 | static inline void hri_oscctrl_clear_interrupt_DFLLOOB_bit(const void *const hw) |
| 1958 | { |
| 1959 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB; |
| 1960 | } |
| 1961 | |
| 1962 | static inline bool hri_oscctrl_get_interrupt_DFLLLCKF_bit(const void *const hw) |
| 1963 | { |
| 1964 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos; |
| 1965 | } |
| 1966 | |
| 1967 | static inline void hri_oscctrl_clear_interrupt_DFLLLCKF_bit(const void *const hw) |
| 1968 | { |
| 1969 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF; |
| 1970 | } |
| 1971 | |
| 1972 | static inline bool hri_oscctrl_get_interrupt_DFLLLCKC_bit(const void *const hw) |
| 1973 | { |
| 1974 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos; |
| 1975 | } |
| 1976 | |
| 1977 | static inline void hri_oscctrl_clear_interrupt_DFLLLCKC_bit(const void *const hw) |
| 1978 | { |
| 1979 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC; |
| 1980 | } |
| 1981 | |
| 1982 | static inline bool hri_oscctrl_get_interrupt_DFLLRCS_bit(const void *const hw) |
| 1983 | { |
| 1984 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos; |
| 1985 | } |
| 1986 | |
| 1987 | static inline void hri_oscctrl_clear_interrupt_DFLLRCS_bit(const void *const hw) |
| 1988 | { |
| 1989 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS; |
| 1990 | } |
| 1991 | |
| 1992 | static inline bool hri_oscctrl_get_interrupt_DPLL0LCKR_bit(const void *const hw) |
| 1993 | { |
| 1994 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKR) >> OSCCTRL_INTFLAG_DPLL0LCKR_Pos; |
| 1995 | } |
| 1996 | |
| 1997 | static inline void hri_oscctrl_clear_interrupt_DPLL0LCKR_bit(const void *const hw) |
| 1998 | { |
| 1999 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKR; |
| 2000 | } |
| 2001 | |
| 2002 | static inline bool hri_oscctrl_get_interrupt_DPLL0LCKF_bit(const void *const hw) |
| 2003 | { |
| 2004 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKF) >> OSCCTRL_INTFLAG_DPLL0LCKF_Pos; |
| 2005 | } |
| 2006 | |
| 2007 | static inline void hri_oscctrl_clear_interrupt_DPLL0LCKF_bit(const void *const hw) |
| 2008 | { |
| 2009 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKF; |
| 2010 | } |
| 2011 | |
| 2012 | static inline bool hri_oscctrl_get_interrupt_DPLL0LTO_bit(const void *const hw) |
| 2013 | { |
| 2014 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LTO) >> OSCCTRL_INTFLAG_DPLL0LTO_Pos; |
| 2015 | } |
| 2016 | |
| 2017 | static inline void hri_oscctrl_clear_interrupt_DPLL0LTO_bit(const void *const hw) |
| 2018 | { |
| 2019 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LTO; |
| 2020 | } |
| 2021 | |
| 2022 | static inline bool hri_oscctrl_get_interrupt_DPLL0LDRTO_bit(const void *const hw) |
| 2023 | { |
| 2024 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LDRTO) >> OSCCTRL_INTFLAG_DPLL0LDRTO_Pos; |
| 2025 | } |
| 2026 | |
| 2027 | static inline void hri_oscctrl_clear_interrupt_DPLL0LDRTO_bit(const void *const hw) |
| 2028 | { |
| 2029 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LDRTO; |
| 2030 | } |
| 2031 | |
| 2032 | static inline bool hri_oscctrl_get_interrupt_DPLL1LCKR_bit(const void *const hw) |
| 2033 | { |
| 2034 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKR) >> OSCCTRL_INTFLAG_DPLL1LCKR_Pos; |
| 2035 | } |
| 2036 | |
| 2037 | static inline void hri_oscctrl_clear_interrupt_DPLL1LCKR_bit(const void *const hw) |
| 2038 | { |
| 2039 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKR; |
| 2040 | } |
| 2041 | |
| 2042 | static inline bool hri_oscctrl_get_interrupt_DPLL1LCKF_bit(const void *const hw) |
| 2043 | { |
| 2044 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKF) >> OSCCTRL_INTFLAG_DPLL1LCKF_Pos; |
| 2045 | } |
| 2046 | |
| 2047 | static inline void hri_oscctrl_clear_interrupt_DPLL1LCKF_bit(const void *const hw) |
| 2048 | { |
| 2049 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKF; |
| 2050 | } |
| 2051 | |
| 2052 | static inline bool hri_oscctrl_get_interrupt_DPLL1LTO_bit(const void *const hw) |
| 2053 | { |
| 2054 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LTO) >> OSCCTRL_INTFLAG_DPLL1LTO_Pos; |
| 2055 | } |
| 2056 | |
| 2057 | static inline void hri_oscctrl_clear_interrupt_DPLL1LTO_bit(const void *const hw) |
| 2058 | { |
| 2059 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LTO; |
| 2060 | } |
| 2061 | |
| 2062 | static inline bool hri_oscctrl_get_interrupt_DPLL1LDRTO_bit(const void *const hw) |
| 2063 | { |
| 2064 | return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LDRTO) >> OSCCTRL_INTFLAG_DPLL1LDRTO_Pos; |
| 2065 | } |
| 2066 | |
| 2067 | static inline void hri_oscctrl_clear_interrupt_DPLL1LDRTO_bit(const void *const hw) |
| 2068 | { |
| 2069 | ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LDRTO; |
| 2070 | } |
| 2071 | |
| 2072 | static inline hri_oscctrl_intflag_reg_t hri_oscctrl_get_INTFLAG_reg(const void *const hw, |
| 2073 | hri_oscctrl_intflag_reg_t mask) |
| 2074 | { |
| 2075 | uint32_t tmp; |
| 2076 | tmp = ((Oscctrl *)hw)->INTFLAG.reg; |
| 2077 | tmp &= mask; |
| 2078 | return tmp; |
| 2079 | } |
| 2080 | |
| 2081 | static inline hri_oscctrl_intflag_reg_t hri_oscctrl_read_INTFLAG_reg(const void *const hw) |
| 2082 | { |
| 2083 | return ((Oscctrl *)hw)->INTFLAG.reg; |
| 2084 | } |
| 2085 | |
| 2086 | static inline void hri_oscctrl_clear_INTFLAG_reg(const void *const hw, hri_oscctrl_intflag_reg_t mask) |
| 2087 | { |
| 2088 | ((Oscctrl *)hw)->INTFLAG.reg = mask; |
| 2089 | } |
| 2090 | |
| 2091 | static inline void hri_oscctrl_set_INTEN_XOSCRDY0_bit(const void *const hw) |
| 2092 | { |
| 2093 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY0; |
| 2094 | } |
| 2095 | |
| 2096 | static inline bool hri_oscctrl_get_INTEN_XOSCRDY0_bit(const void *const hw) |
| 2097 | { |
| 2098 | return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY0) >> OSCCTRL_INTENSET_XOSCRDY0_Pos; |
| 2099 | } |
| 2100 | |
| 2101 | static inline void hri_oscctrl_write_INTEN_XOSCRDY0_bit(const void *const hw, bool value) |
| 2102 | { |
| 2103 | if (value == 0x0) { |
| 2104 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY0; |
| 2105 | } else { |
| 2106 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY0; |
| 2107 | } |
| 2108 | } |
| 2109 | |
| 2110 | static inline void hri_oscctrl_clear_INTEN_XOSCRDY0_bit(const void *const hw) |
| 2111 | { |
| 2112 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY0; |
| 2113 | } |
| 2114 | |
| 2115 | static inline void hri_oscctrl_set_INTEN_XOSCRDY1_bit(const void *const hw) |
| 2116 | { |
| 2117 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY1; |
| 2118 | } |
| 2119 | |
| 2120 | static inline bool hri_oscctrl_get_INTEN_XOSCRDY1_bit(const void *const hw) |
| 2121 | { |
| 2122 | return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY1) >> OSCCTRL_INTENSET_XOSCRDY1_Pos; |
| 2123 | } |
| 2124 | |
| 2125 | static inline void hri_oscctrl_write_INTEN_XOSCRDY1_bit(const void *const hw, bool value) |
| 2126 | { |
| 2127 | if (value == 0x0) { |
| 2128 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY1; |
| 2129 | } else { |
| 2130 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY1; |
| 2131 | } |
| 2132 | } |
| 2133 | |
| 2134 | static inline void hri_oscctrl_clear_INTEN_XOSCRDY1_bit(const void *const hw) |
| 2135 | { |
| 2136 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY1; |
| 2137 | } |
| 2138 | |
| 2139 | static inline void hri_oscctrl_set_INTEN_XOSCFAIL0_bit(const void *const hw) |
| 2140 | { |
| 2141 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL0; |
| 2142 | } |
| 2143 | |
| 2144 | static inline bool hri_oscctrl_get_INTEN_XOSCFAIL0_bit(const void *const hw) |
| 2145 | { |
| 2146 | return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL0) >> OSCCTRL_INTENSET_XOSCFAIL0_Pos; |
| 2147 | } |
| 2148 | |
| 2149 | static inline void hri_oscctrl_write_INTEN_XOSCFAIL0_bit(const void *const hw, bool value) |
| 2150 | { |
| 2151 | if (value == 0x0) { |
| 2152 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL0; |
| 2153 | } else { |
| 2154 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL0; |
| 2155 | } |
| 2156 | } |
| 2157 | |
| 2158 | static inline void hri_oscctrl_clear_INTEN_XOSCFAIL0_bit(const void *const hw) |
| 2159 | { |
| 2160 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL0; |
| 2161 | } |
| 2162 | |
| 2163 | static inline void hri_oscctrl_set_INTEN_XOSCFAIL1_bit(const void *const hw) |
| 2164 | { |
| 2165 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL1; |
| 2166 | } |
| 2167 | |
| 2168 | static inline bool hri_oscctrl_get_INTEN_XOSCFAIL1_bit(const void *const hw) |
| 2169 | { |
| 2170 | return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL1) >> OSCCTRL_INTENSET_XOSCFAIL1_Pos; |
| 2171 | } |
| 2172 | |
| 2173 | static inline void hri_oscctrl_write_INTEN_XOSCFAIL1_bit(const void *const hw, bool value) |
| 2174 | { |
| 2175 | if (value == 0x0) { |
| 2176 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL1; |
| 2177 | } else { |
| 2178 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL1; |
| 2179 | } |
| 2180 | } |
| 2181 | |
| 2182 | static inline void hri_oscctrl_clear_INTEN_XOSCFAIL1_bit(const void *const hw) |
| 2183 | { |
| 2184 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL1; |
| 2185 | } |
| 2186 | |
| 2187 | static inline void hri_oscctrl_set_INTEN_DFLLRDY_bit(const void *const hw) |
| 2188 | { |
| 2189 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY; |
| 2190 | } |
| 2191 | |
| 2192 | static inline bool hri_oscctrl_get_INTEN_DFLLRDY_bit(const void *const hw) |
| 2193 | { |
| 2194 | return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRDY) >> OSCCTRL_INTENSET_DFLLRDY_Pos; |
| 2195 | } |
| 2196 | |
| 2197 | static inline void hri_oscctrl_write_INTEN_DFLLRDY_bit(const void *const hw, bool value) |
| 2198 | { |
| 2199 | if (value == 0x0) { |
| 2200 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY; |
| 2201 | } else { |
| 2202 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY; |
| 2203 | } |
| 2204 | } |
| 2205 | |
| 2206 | static inline void hri_oscctrl_clear_INTEN_DFLLRDY_bit(const void *const hw) |
| 2207 | { |
| 2208 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY; |
| 2209 | } |
| 2210 | |
| 2211 | static inline void hri_oscctrl_set_INTEN_DFLLOOB_bit(const void *const hw) |
| 2212 | { |
| 2213 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB; |
| 2214 | } |
| 2215 | |
| 2216 | static inline bool hri_oscctrl_get_INTEN_DFLLOOB_bit(const void *const hw) |
| 2217 | { |
| 2218 | return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLOOB) >> OSCCTRL_INTENSET_DFLLOOB_Pos; |
| 2219 | } |
| 2220 | |
| 2221 | static inline void hri_oscctrl_write_INTEN_DFLLOOB_bit(const void *const hw, bool value) |
| 2222 | { |
| 2223 | if (value == 0x0) { |
| 2224 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB; |
| 2225 | } else { |
| 2226 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB; |
| 2227 | } |
| 2228 | } |
| 2229 | |
| 2230 | static inline void hri_oscctrl_clear_INTEN_DFLLOOB_bit(const void *const hw) |
| 2231 | { |
| 2232 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB; |
| 2233 | } |
| 2234 | |
| 2235 | static inline void hri_oscctrl_set_INTEN_DFLLLCKF_bit(const void *const hw) |
| 2236 | { |
| 2237 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF; |
| 2238 | } |
| 2239 | |
| 2240 | static inline bool hri_oscctrl_get_INTEN_DFLLLCKF_bit(const void *const hw) |
| 2241 | { |
| 2242 | return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKF) >> OSCCTRL_INTENSET_DFLLLCKF_Pos; |
| 2243 | } |
| 2244 | |
| 2245 | static inline void hri_oscctrl_write_INTEN_DFLLLCKF_bit(const void *const hw, bool value) |
| 2246 | { |
| 2247 | if (value == 0x0) { |
| 2248 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF; |
| 2249 | } else { |
| 2250 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF; |
| 2251 | } |
| 2252 | } |
| 2253 | |
| 2254 | static inline void hri_oscctrl_clear_INTEN_DFLLLCKF_bit(const void *const hw) |
| 2255 | { |
| 2256 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF; |
| 2257 | } |
| 2258 | |
| 2259 | static inline void hri_oscctrl_set_INTEN_DFLLLCKC_bit(const void *const hw) |
| 2260 | { |
| 2261 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC; |
| 2262 | } |
| 2263 | |
| 2264 | static inline bool hri_oscctrl_get_INTEN_DFLLLCKC_bit(const void *const hw) |
| 2265 | { |
| 2266 | return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKC) >> OSCCTRL_INTENSET_DFLLLCKC_Pos; |
| 2267 | } |
| 2268 | |
| 2269 | static inline void hri_oscctrl_write_INTEN_DFLLLCKC_bit(const void *const hw, bool value) |
| 2270 | { |
| 2271 | if (value == 0x0) { |
| 2272 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC; |
| 2273 | } else { |
| 2274 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC; |
| 2275 | } |
| 2276 | } |
| 2277 | |
| 2278 | static inline void hri_oscctrl_clear_INTEN_DFLLLCKC_bit(const void *const hw) |
| 2279 | { |
| 2280 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC; |
| 2281 | } |
| 2282 | |
| 2283 | static inline void hri_oscctrl_set_INTEN_DFLLRCS_bit(const void *const hw) |
| 2284 | { |
| 2285 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS; |
| 2286 | } |
| 2287 | |
| 2288 | static inline bool hri_oscctrl_get_INTEN_DFLLRCS_bit(const void *const hw) |
| 2289 | { |
| 2290 | return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRCS) >> OSCCTRL_INTENSET_DFLLRCS_Pos; |
| 2291 | } |
| 2292 | |
| 2293 | static inline void hri_oscctrl_write_INTEN_DFLLRCS_bit(const void *const hw, bool value) |
| 2294 | { |
| 2295 | if (value == 0x0) { |
| 2296 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS; |
| 2297 | } else { |
| 2298 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS; |
| 2299 | } |
| 2300 | } |
| 2301 | |
| 2302 | static inline void hri_oscctrl_clear_INTEN_DFLLRCS_bit(const void *const hw) |
| 2303 | { |
| 2304 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS; |
| 2305 | } |
| 2306 | |
| 2307 | static inline void hri_oscctrl_set_INTEN_DPLL0LCKR_bit(const void *const hw) |
| 2308 | { |
| 2309 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKR; |
| 2310 | } |
| 2311 | |
| 2312 | static inline bool hri_oscctrl_get_INTEN_DPLL0LCKR_bit(const void *const hw) |
| 2313 | { |
| 2314 | return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LCKR) >> OSCCTRL_INTENSET_DPLL0LCKR_Pos; |
| 2315 | } |
| 2316 | |
| 2317 | static inline void hri_oscctrl_write_INTEN_DPLL0LCKR_bit(const void *const hw, bool value) |
| 2318 | { |
| 2319 | if (value == 0x0) { |
| 2320 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKR; |
| 2321 | } else { |
| 2322 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKR; |
| 2323 | } |
| 2324 | } |
| 2325 | |
| 2326 | static inline void hri_oscctrl_clear_INTEN_DPLL0LCKR_bit(const void *const hw) |
| 2327 | { |
| 2328 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKR; |
| 2329 | } |
| 2330 | |
| 2331 | static inline void hri_oscctrl_set_INTEN_DPLL0LCKF_bit(const void *const hw) |
| 2332 | { |
| 2333 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKF; |
| 2334 | } |
| 2335 | |
| 2336 | static inline bool hri_oscctrl_get_INTEN_DPLL0LCKF_bit(const void *const hw) |
| 2337 | { |
| 2338 | return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LCKF) >> OSCCTRL_INTENSET_DPLL0LCKF_Pos; |
| 2339 | } |
| 2340 | |
| 2341 | static inline void hri_oscctrl_write_INTEN_DPLL0LCKF_bit(const void *const hw, bool value) |
| 2342 | { |
| 2343 | if (value == 0x0) { |
| 2344 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKF; |
| 2345 | } else { |
| 2346 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKF; |
| 2347 | } |
| 2348 | } |
| 2349 | |
| 2350 | static inline void hri_oscctrl_clear_INTEN_DPLL0LCKF_bit(const void *const hw) |
| 2351 | { |
| 2352 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKF; |
| 2353 | } |
| 2354 | |
| 2355 | static inline void hri_oscctrl_set_INTEN_DPLL0LTO_bit(const void *const hw) |
| 2356 | { |
| 2357 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LTO; |
| 2358 | } |
| 2359 | |
| 2360 | static inline bool hri_oscctrl_get_INTEN_DPLL0LTO_bit(const void *const hw) |
| 2361 | { |
| 2362 | return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LTO) >> OSCCTRL_INTENSET_DPLL0LTO_Pos; |
| 2363 | } |
| 2364 | |
| 2365 | static inline void hri_oscctrl_write_INTEN_DPLL0LTO_bit(const void *const hw, bool value) |
| 2366 | { |
| 2367 | if (value == 0x0) { |
| 2368 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LTO; |
| 2369 | } else { |
| 2370 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LTO; |
| 2371 | } |
| 2372 | } |
| 2373 | |
| 2374 | static inline void hri_oscctrl_clear_INTEN_DPLL0LTO_bit(const void *const hw) |
| 2375 | { |
| 2376 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LTO; |
| 2377 | } |
| 2378 | |
| 2379 | static inline void hri_oscctrl_set_INTEN_DPLL0LDRTO_bit(const void *const hw) |
| 2380 | { |
| 2381 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LDRTO; |
| 2382 | } |
| 2383 | |
| 2384 | static inline bool hri_oscctrl_get_INTEN_DPLL0LDRTO_bit(const void *const hw) |
| 2385 | { |
| 2386 | return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LDRTO) >> OSCCTRL_INTENSET_DPLL0LDRTO_Pos; |
| 2387 | } |
| 2388 | |
| 2389 | static inline void hri_oscctrl_write_INTEN_DPLL0LDRTO_bit(const void *const hw, bool value) |
| 2390 | { |
| 2391 | if (value == 0x0) { |
| 2392 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LDRTO; |
| 2393 | } else { |
| 2394 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LDRTO; |
| 2395 | } |
| 2396 | } |
| 2397 | |
| 2398 | static inline void hri_oscctrl_clear_INTEN_DPLL0LDRTO_bit(const void *const hw) |
| 2399 | { |
| 2400 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LDRTO; |
| 2401 | } |
| 2402 | |
| 2403 | static inline void hri_oscctrl_set_INTEN_DPLL1LCKR_bit(const void *const hw) |
| 2404 | { |
| 2405 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKR; |
| 2406 | } |
| 2407 | |
| 2408 | static inline bool hri_oscctrl_get_INTEN_DPLL1LCKR_bit(const void *const hw) |
| 2409 | { |
| 2410 | return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LCKR) >> OSCCTRL_INTENSET_DPLL1LCKR_Pos; |
| 2411 | } |
| 2412 | |
| 2413 | static inline void hri_oscctrl_write_INTEN_DPLL1LCKR_bit(const void *const hw, bool value) |
| 2414 | { |
| 2415 | if (value == 0x0) { |
| 2416 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKR; |
| 2417 | } else { |
| 2418 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKR; |
| 2419 | } |
| 2420 | } |
| 2421 | |
| 2422 | static inline void hri_oscctrl_clear_INTEN_DPLL1LCKR_bit(const void *const hw) |
| 2423 | { |
| 2424 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKR; |
| 2425 | } |
| 2426 | |
| 2427 | static inline void hri_oscctrl_set_INTEN_DPLL1LCKF_bit(const void *const hw) |
| 2428 | { |
| 2429 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKF; |
| 2430 | } |
| 2431 | |
| 2432 | static inline bool hri_oscctrl_get_INTEN_DPLL1LCKF_bit(const void *const hw) |
| 2433 | { |
| 2434 | return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LCKF) >> OSCCTRL_INTENSET_DPLL1LCKF_Pos; |
| 2435 | } |
| 2436 | |
| 2437 | static inline void hri_oscctrl_write_INTEN_DPLL1LCKF_bit(const void *const hw, bool value) |
| 2438 | { |
| 2439 | if (value == 0x0) { |
| 2440 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKF; |
| 2441 | } else { |
| 2442 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKF; |
| 2443 | } |
| 2444 | } |
| 2445 | |
| 2446 | static inline void hri_oscctrl_clear_INTEN_DPLL1LCKF_bit(const void *const hw) |
| 2447 | { |
| 2448 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKF; |
| 2449 | } |
| 2450 | |
| 2451 | static inline void hri_oscctrl_set_INTEN_DPLL1LTO_bit(const void *const hw) |
| 2452 | { |
| 2453 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LTO; |
| 2454 | } |
| 2455 | |
| 2456 | static inline bool hri_oscctrl_get_INTEN_DPLL1LTO_bit(const void *const hw) |
| 2457 | { |
| 2458 | return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LTO) >> OSCCTRL_INTENSET_DPLL1LTO_Pos; |
| 2459 | } |
| 2460 | |
| 2461 | static inline void hri_oscctrl_write_INTEN_DPLL1LTO_bit(const void *const hw, bool value) |
| 2462 | { |
| 2463 | if (value == 0x0) { |
| 2464 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LTO; |
| 2465 | } else { |
| 2466 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LTO; |
| 2467 | } |
| 2468 | } |
| 2469 | |
| 2470 | static inline void hri_oscctrl_clear_INTEN_DPLL1LTO_bit(const void *const hw) |
| 2471 | { |
| 2472 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LTO; |
| 2473 | } |
| 2474 | |
| 2475 | static inline void hri_oscctrl_set_INTEN_DPLL1LDRTO_bit(const void *const hw) |
| 2476 | { |
| 2477 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LDRTO; |
| 2478 | } |
| 2479 | |
| 2480 | static inline bool hri_oscctrl_get_INTEN_DPLL1LDRTO_bit(const void *const hw) |
| 2481 | { |
| 2482 | return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LDRTO) >> OSCCTRL_INTENSET_DPLL1LDRTO_Pos; |
| 2483 | } |
| 2484 | |
| 2485 | static inline void hri_oscctrl_write_INTEN_DPLL1LDRTO_bit(const void *const hw, bool value) |
| 2486 | { |
| 2487 | if (value == 0x0) { |
| 2488 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LDRTO; |
| 2489 | } else { |
| 2490 | ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LDRTO; |
| 2491 | } |
| 2492 | } |
| 2493 | |
| 2494 | static inline void hri_oscctrl_clear_INTEN_DPLL1LDRTO_bit(const void *const hw) |
| 2495 | { |
| 2496 | ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LDRTO; |
| 2497 | } |
| 2498 | |
| 2499 | static inline void hri_oscctrl_set_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) |
| 2500 | { |
| 2501 | ((Oscctrl *)hw)->INTENSET.reg = mask; |
| 2502 | } |
| 2503 | |
| 2504 | static inline hri_oscctrl_intenset_reg_t hri_oscctrl_get_INTEN_reg(const void *const hw, |
| 2505 | hri_oscctrl_intenset_reg_t mask) |
| 2506 | { |
| 2507 | uint32_t tmp; |
| 2508 | tmp = ((Oscctrl *)hw)->INTENSET.reg; |
| 2509 | tmp &= mask; |
| 2510 | return tmp; |
| 2511 | } |
| 2512 | |
| 2513 | static inline hri_oscctrl_intenset_reg_t hri_oscctrl_read_INTEN_reg(const void *const hw) |
| 2514 | { |
| 2515 | return ((Oscctrl *)hw)->INTENSET.reg; |
| 2516 | } |
| 2517 | |
| 2518 | static inline void hri_oscctrl_write_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t data) |
| 2519 | { |
| 2520 | ((Oscctrl *)hw)->INTENSET.reg = data; |
| 2521 | ((Oscctrl *)hw)->INTENCLR.reg = ~data; |
| 2522 | } |
| 2523 | |
| 2524 | static inline void hri_oscctrl_clear_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) |
| 2525 | { |
| 2526 | ((Oscctrl *)hw)->INTENCLR.reg = mask; |
| 2527 | } |
| 2528 | |
| 2529 | static inline bool hri_oscctrl_get_STATUS_XOSCRDY0_bit(const void *const hw) |
| 2530 | { |
| 2531 | return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY0) >> OSCCTRL_STATUS_XOSCRDY0_Pos; |
| 2532 | } |
| 2533 | |
| 2534 | static inline bool hri_oscctrl_get_STATUS_XOSCRDY1_bit(const void *const hw) |
| 2535 | { |
| 2536 | return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY1) >> OSCCTRL_STATUS_XOSCRDY1_Pos; |
| 2537 | } |
| 2538 | |
| 2539 | static inline bool hri_oscctrl_get_STATUS_XOSCFAIL0_bit(const void *const hw) |
| 2540 | { |
| 2541 | return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL0) >> OSCCTRL_STATUS_XOSCFAIL0_Pos; |
| 2542 | } |
| 2543 | |
| 2544 | static inline bool hri_oscctrl_get_STATUS_XOSCFAIL1_bit(const void *const hw) |
| 2545 | { |
| 2546 | return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL1) >> OSCCTRL_STATUS_XOSCFAIL1_Pos; |
| 2547 | } |
| 2548 | |
| 2549 | static inline bool hri_oscctrl_get_STATUS_XOSCCKSW0_bit(const void *const hw) |
| 2550 | { |
| 2551 | return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW0) >> OSCCTRL_STATUS_XOSCCKSW0_Pos; |
| 2552 | } |
| 2553 | |
| 2554 | static inline bool hri_oscctrl_get_STATUS_XOSCCKSW1_bit(const void *const hw) |
| 2555 | { |
| 2556 | return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW1) >> OSCCTRL_STATUS_XOSCCKSW1_Pos; |
| 2557 | } |
| 2558 | |
| 2559 | static inline bool hri_oscctrl_get_STATUS_DFLLRDY_bit(const void *const hw) |
| 2560 | { |
| 2561 | return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRDY) >> OSCCTRL_STATUS_DFLLRDY_Pos; |
| 2562 | } |
| 2563 | |
| 2564 | static inline bool hri_oscctrl_get_STATUS_DFLLOOB_bit(const void *const hw) |
| 2565 | { |
| 2566 | return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLOOB) >> OSCCTRL_STATUS_DFLLOOB_Pos; |
| 2567 | } |
| 2568 | |
| 2569 | static inline bool hri_oscctrl_get_STATUS_DFLLLCKF_bit(const void *const hw) |
| 2570 | { |
| 2571 | return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKF) >> OSCCTRL_STATUS_DFLLLCKF_Pos; |
| 2572 | } |
| 2573 | |
| 2574 | static inline bool hri_oscctrl_get_STATUS_DFLLLCKC_bit(const void *const hw) |
| 2575 | { |
| 2576 | return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKC) >> OSCCTRL_STATUS_DFLLLCKC_Pos; |
| 2577 | } |
| 2578 | |
| 2579 | static inline bool hri_oscctrl_get_STATUS_DFLLRCS_bit(const void *const hw) |
| 2580 | { |
| 2581 | return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRCS) >> OSCCTRL_STATUS_DFLLRCS_Pos; |
| 2582 | } |
| 2583 | |
| 2584 | static inline bool hri_oscctrl_get_STATUS_DPLL0LCKR_bit(const void *const hw) |
| 2585 | { |
| 2586 | return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LCKR) >> OSCCTRL_STATUS_DPLL0LCKR_Pos; |
| 2587 | } |
| 2588 | |
| 2589 | static inline bool hri_oscctrl_get_STATUS_DPLL0LCKF_bit(const void *const hw) |
| 2590 | { |
| 2591 | return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LCKF) >> OSCCTRL_STATUS_DPLL0LCKF_Pos; |
| 2592 | } |
| 2593 | |
| 2594 | static inline bool hri_oscctrl_get_STATUS_DPLL0TO_bit(const void *const hw) |
| 2595 | { |
| 2596 | return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0TO) >> OSCCTRL_STATUS_DPLL0TO_Pos; |
| 2597 | } |
| 2598 | |
| 2599 | static inline bool hri_oscctrl_get_STATUS_DPLL0LDRTO_bit(const void *const hw) |
| 2600 | { |
| 2601 | return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LDRTO) >> OSCCTRL_STATUS_DPLL0LDRTO_Pos; |
| 2602 | } |
| 2603 | |
| 2604 | static inline bool hri_oscctrl_get_STATUS_DPLL1LCKR_bit(const void *const hw) |
| 2605 | { |
| 2606 | return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LCKR) >> OSCCTRL_STATUS_DPLL1LCKR_Pos; |
| 2607 | } |
| 2608 | |
| 2609 | static inline bool hri_oscctrl_get_STATUS_DPLL1LCKF_bit(const void *const hw) |
| 2610 | { |
| 2611 | return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LCKF) >> OSCCTRL_STATUS_DPLL1LCKF_Pos; |
| 2612 | } |
| 2613 | |
| 2614 | static inline bool hri_oscctrl_get_STATUS_DPLL1TO_bit(const void *const hw) |
| 2615 | { |
| 2616 | return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1TO) >> OSCCTRL_STATUS_DPLL1TO_Pos; |
| 2617 | } |
| 2618 | |
| 2619 | static inline bool hri_oscctrl_get_STATUS_DPLL1LDRTO_bit(const void *const hw) |
| 2620 | { |
| 2621 | return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LDRTO) >> OSCCTRL_STATUS_DPLL1LDRTO_Pos; |
| 2622 | } |
| 2623 | |
| 2624 | static inline hri_oscctrl_status_reg_t hri_oscctrl_get_STATUS_reg(const void *const hw, hri_oscctrl_status_reg_t mask) |
| 2625 | { |
| 2626 | uint32_t tmp; |
| 2627 | tmp = ((Oscctrl *)hw)->STATUS.reg; |
| 2628 | tmp &= mask; |
| 2629 | return tmp; |
| 2630 | } |
| 2631 | |
| 2632 | static inline hri_oscctrl_status_reg_t hri_oscctrl_read_STATUS_reg(const void *const hw) |
| 2633 | { |
| 2634 | return ((Oscctrl *)hw)->STATUS.reg; |
| 2635 | } |
| 2636 | |
| 2637 | static inline void hri_oscctrl_set_EVCTRL_CFDEO0_bit(const void *const hw) |
| 2638 | { |
| 2639 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2640 | ((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO0; |
| 2641 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2642 | } |
| 2643 | |
| 2644 | static inline bool hri_oscctrl_get_EVCTRL_CFDEO0_bit(const void *const hw) |
| 2645 | { |
| 2646 | uint8_t tmp; |
| 2647 | tmp = ((Oscctrl *)hw)->EVCTRL.reg; |
| 2648 | tmp = (tmp & OSCCTRL_EVCTRL_CFDEO0) >> OSCCTRL_EVCTRL_CFDEO0_Pos; |
| 2649 | return (bool)tmp; |
| 2650 | } |
| 2651 | |
| 2652 | static inline void hri_oscctrl_write_EVCTRL_CFDEO0_bit(const void *const hw, bool value) |
| 2653 | { |
| 2654 | uint8_t tmp; |
| 2655 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2656 | tmp = ((Oscctrl *)hw)->EVCTRL.reg; |
| 2657 | tmp &= ~OSCCTRL_EVCTRL_CFDEO0; |
| 2658 | tmp |= value << OSCCTRL_EVCTRL_CFDEO0_Pos; |
| 2659 | ((Oscctrl *)hw)->EVCTRL.reg = tmp; |
| 2660 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2661 | } |
| 2662 | |
| 2663 | static inline void hri_oscctrl_clear_EVCTRL_CFDEO0_bit(const void *const hw) |
| 2664 | { |
| 2665 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2666 | ((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO0; |
| 2667 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2668 | } |
| 2669 | |
| 2670 | static inline void hri_oscctrl_toggle_EVCTRL_CFDEO0_bit(const void *const hw) |
| 2671 | { |
| 2672 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2673 | ((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO0; |
| 2674 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2675 | } |
| 2676 | |
| 2677 | static inline void hri_oscctrl_set_EVCTRL_CFDEO1_bit(const void *const hw) |
| 2678 | { |
| 2679 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2680 | ((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO1; |
| 2681 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2682 | } |
| 2683 | |
| 2684 | static inline bool hri_oscctrl_get_EVCTRL_CFDEO1_bit(const void *const hw) |
| 2685 | { |
| 2686 | uint8_t tmp; |
| 2687 | tmp = ((Oscctrl *)hw)->EVCTRL.reg; |
| 2688 | tmp = (tmp & OSCCTRL_EVCTRL_CFDEO1) >> OSCCTRL_EVCTRL_CFDEO1_Pos; |
| 2689 | return (bool)tmp; |
| 2690 | } |
| 2691 | |
| 2692 | static inline void hri_oscctrl_write_EVCTRL_CFDEO1_bit(const void *const hw, bool value) |
| 2693 | { |
| 2694 | uint8_t tmp; |
| 2695 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2696 | tmp = ((Oscctrl *)hw)->EVCTRL.reg; |
| 2697 | tmp &= ~OSCCTRL_EVCTRL_CFDEO1; |
| 2698 | tmp |= value << OSCCTRL_EVCTRL_CFDEO1_Pos; |
| 2699 | ((Oscctrl *)hw)->EVCTRL.reg = tmp; |
| 2700 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2701 | } |
| 2702 | |
| 2703 | static inline void hri_oscctrl_clear_EVCTRL_CFDEO1_bit(const void *const hw) |
| 2704 | { |
| 2705 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2706 | ((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO1; |
| 2707 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2708 | } |
| 2709 | |
| 2710 | static inline void hri_oscctrl_toggle_EVCTRL_CFDEO1_bit(const void *const hw) |
| 2711 | { |
| 2712 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2713 | ((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO1; |
| 2714 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2715 | } |
| 2716 | |
| 2717 | static inline void hri_oscctrl_set_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) |
| 2718 | { |
| 2719 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2720 | ((Oscctrl *)hw)->EVCTRL.reg |= mask; |
| 2721 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2722 | } |
| 2723 | |
| 2724 | static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_get_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) |
| 2725 | { |
| 2726 | uint8_t tmp; |
| 2727 | tmp = ((Oscctrl *)hw)->EVCTRL.reg; |
| 2728 | tmp &= mask; |
| 2729 | return tmp; |
| 2730 | } |
| 2731 | |
| 2732 | static inline void hri_oscctrl_write_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t data) |
| 2733 | { |
| 2734 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2735 | ((Oscctrl *)hw)->EVCTRL.reg = data; |
| 2736 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2737 | } |
| 2738 | |
| 2739 | static inline void hri_oscctrl_clear_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) |
| 2740 | { |
| 2741 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2742 | ((Oscctrl *)hw)->EVCTRL.reg &= ~mask; |
| 2743 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2744 | } |
| 2745 | |
| 2746 | static inline void hri_oscctrl_toggle_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) |
| 2747 | { |
| 2748 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2749 | ((Oscctrl *)hw)->EVCTRL.reg ^= mask; |
| 2750 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2751 | } |
| 2752 | |
| 2753 | static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_read_EVCTRL_reg(const void *const hw) |
| 2754 | { |
| 2755 | return ((Oscctrl *)hw)->EVCTRL.reg; |
| 2756 | } |
| 2757 | |
| 2758 | static inline void hri_oscctrl_set_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) |
| 2759 | { |
| 2760 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2761 | ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ENABLE; |
| 2762 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2763 | } |
| 2764 | |
| 2765 | static inline bool hri_oscctrl_get_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) |
| 2766 | { |
| 2767 | uint32_t tmp; |
| 2768 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 2769 | tmp = (tmp & OSCCTRL_XOSCCTRL_ENABLE) >> OSCCTRL_XOSCCTRL_ENABLE_Pos; |
| 2770 | return (bool)tmp; |
| 2771 | } |
| 2772 | |
| 2773 | static inline void hri_oscctrl_write_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) |
| 2774 | { |
| 2775 | uint32_t tmp; |
| 2776 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2777 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 2778 | tmp &= ~OSCCTRL_XOSCCTRL_ENABLE; |
| 2779 | tmp |= value << OSCCTRL_XOSCCTRL_ENABLE_Pos; |
| 2780 | ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; |
| 2781 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2782 | } |
| 2783 | |
| 2784 | static inline void hri_oscctrl_clear_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) |
| 2785 | { |
| 2786 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2787 | ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ENABLE; |
| 2788 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2789 | } |
| 2790 | |
| 2791 | static inline void hri_oscctrl_toggle_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) |
| 2792 | { |
| 2793 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2794 | ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ENABLE; |
| 2795 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2796 | } |
| 2797 | |
| 2798 | static inline void hri_oscctrl_set_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) |
| 2799 | { |
| 2800 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2801 | ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_XTALEN; |
| 2802 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2803 | } |
| 2804 | |
| 2805 | static inline bool hri_oscctrl_get_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) |
| 2806 | { |
| 2807 | uint32_t tmp; |
| 2808 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 2809 | tmp = (tmp & OSCCTRL_XOSCCTRL_XTALEN) >> OSCCTRL_XOSCCTRL_XTALEN_Pos; |
| 2810 | return (bool)tmp; |
| 2811 | } |
| 2812 | |
| 2813 | static inline void hri_oscctrl_write_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index, bool value) |
| 2814 | { |
| 2815 | uint32_t tmp; |
| 2816 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2817 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 2818 | tmp &= ~OSCCTRL_XOSCCTRL_XTALEN; |
| 2819 | tmp |= value << OSCCTRL_XOSCCTRL_XTALEN_Pos; |
| 2820 | ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; |
| 2821 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2822 | } |
| 2823 | |
| 2824 | static inline void hri_oscctrl_clear_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) |
| 2825 | { |
| 2826 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2827 | ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_XTALEN; |
| 2828 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2829 | } |
| 2830 | |
| 2831 | static inline void hri_oscctrl_toggle_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) |
| 2832 | { |
| 2833 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2834 | ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_XTALEN; |
| 2835 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2836 | } |
| 2837 | |
| 2838 | static inline void hri_oscctrl_set_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) |
| 2839 | { |
| 2840 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2841 | ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_RUNSTDBY; |
| 2842 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2843 | } |
| 2844 | |
| 2845 | static inline bool hri_oscctrl_get_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) |
| 2846 | { |
| 2847 | uint32_t tmp; |
| 2848 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 2849 | tmp = (tmp & OSCCTRL_XOSCCTRL_RUNSTDBY) >> OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; |
| 2850 | return (bool)tmp; |
| 2851 | } |
| 2852 | |
| 2853 | static inline void hri_oscctrl_write_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) |
| 2854 | { |
| 2855 | uint32_t tmp; |
| 2856 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2857 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 2858 | tmp &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; |
| 2859 | tmp |= value << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; |
| 2860 | ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; |
| 2861 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2862 | } |
| 2863 | |
| 2864 | static inline void hri_oscctrl_clear_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) |
| 2865 | { |
| 2866 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2867 | ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; |
| 2868 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2869 | } |
| 2870 | |
| 2871 | static inline void hri_oscctrl_toggle_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) |
| 2872 | { |
| 2873 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2874 | ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_RUNSTDBY; |
| 2875 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2876 | } |
| 2877 | |
| 2878 | static inline void hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) |
| 2879 | { |
| 2880 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2881 | ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ONDEMAND; |
| 2882 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2883 | } |
| 2884 | |
| 2885 | static inline bool hri_oscctrl_get_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) |
| 2886 | { |
| 2887 | uint32_t tmp; |
| 2888 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 2889 | tmp = (tmp & OSCCTRL_XOSCCTRL_ONDEMAND) >> OSCCTRL_XOSCCTRL_ONDEMAND_Pos; |
| 2890 | return (bool)tmp; |
| 2891 | } |
| 2892 | |
| 2893 | static inline void hri_oscctrl_write_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index, bool value) |
| 2894 | { |
| 2895 | uint32_t tmp; |
| 2896 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2897 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 2898 | tmp &= ~OSCCTRL_XOSCCTRL_ONDEMAND; |
| 2899 | tmp |= value << OSCCTRL_XOSCCTRL_ONDEMAND_Pos; |
| 2900 | ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; |
| 2901 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2902 | } |
| 2903 | |
| 2904 | static inline void hri_oscctrl_clear_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) |
| 2905 | { |
| 2906 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2907 | ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ONDEMAND; |
| 2908 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2909 | } |
| 2910 | |
| 2911 | static inline void hri_oscctrl_toggle_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) |
| 2912 | { |
| 2913 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2914 | ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ONDEMAND; |
| 2915 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2916 | } |
| 2917 | |
| 2918 | static inline void hri_oscctrl_set_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) |
| 2919 | { |
| 2920 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2921 | ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_LOWBUFGAIN; |
| 2922 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2923 | } |
| 2924 | |
| 2925 | static inline bool hri_oscctrl_get_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) |
| 2926 | { |
| 2927 | uint32_t tmp; |
| 2928 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 2929 | tmp = (tmp & OSCCTRL_XOSCCTRL_LOWBUFGAIN) >> OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos; |
| 2930 | return (bool)tmp; |
| 2931 | } |
| 2932 | |
| 2933 | static inline void hri_oscctrl_write_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index, bool value) |
| 2934 | { |
| 2935 | uint32_t tmp; |
| 2936 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2937 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 2938 | tmp &= ~OSCCTRL_XOSCCTRL_LOWBUFGAIN; |
| 2939 | tmp |= value << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos; |
| 2940 | ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; |
| 2941 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2942 | } |
| 2943 | |
| 2944 | static inline void hri_oscctrl_clear_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) |
| 2945 | { |
| 2946 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2947 | ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_LOWBUFGAIN; |
| 2948 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2949 | } |
| 2950 | |
| 2951 | static inline void hri_oscctrl_toggle_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) |
| 2952 | { |
| 2953 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2954 | ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_LOWBUFGAIN; |
| 2955 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2956 | } |
| 2957 | |
| 2958 | static inline void hri_oscctrl_set_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) |
| 2959 | { |
| 2960 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2961 | ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ENALC; |
| 2962 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2963 | } |
| 2964 | |
| 2965 | static inline bool hri_oscctrl_get_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) |
| 2966 | { |
| 2967 | uint32_t tmp; |
| 2968 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 2969 | tmp = (tmp & OSCCTRL_XOSCCTRL_ENALC) >> OSCCTRL_XOSCCTRL_ENALC_Pos; |
| 2970 | return (bool)tmp; |
| 2971 | } |
| 2972 | |
| 2973 | static inline void hri_oscctrl_write_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index, bool value) |
| 2974 | { |
| 2975 | uint32_t tmp; |
| 2976 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2977 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 2978 | tmp &= ~OSCCTRL_XOSCCTRL_ENALC; |
| 2979 | tmp |= value << OSCCTRL_XOSCCTRL_ENALC_Pos; |
| 2980 | ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; |
| 2981 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2982 | } |
| 2983 | |
| 2984 | static inline void hri_oscctrl_clear_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) |
| 2985 | { |
| 2986 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2987 | ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ENALC; |
| 2988 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2989 | } |
| 2990 | |
| 2991 | static inline void hri_oscctrl_toggle_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) |
| 2992 | { |
| 2993 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 2994 | ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ENALC; |
| 2995 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 2996 | } |
| 2997 | |
| 2998 | static inline void hri_oscctrl_set_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) |
| 2999 | { |
| 3000 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3001 | ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_CFDEN; |
| 3002 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3003 | } |
| 3004 | |
| 3005 | static inline bool hri_oscctrl_get_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) |
| 3006 | { |
| 3007 | uint32_t tmp; |
| 3008 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 3009 | tmp = (tmp & OSCCTRL_XOSCCTRL_CFDEN) >> OSCCTRL_XOSCCTRL_CFDEN_Pos; |
| 3010 | return (bool)tmp; |
| 3011 | } |
| 3012 | |
| 3013 | static inline void hri_oscctrl_write_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index, bool value) |
| 3014 | { |
| 3015 | uint32_t tmp; |
| 3016 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3017 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 3018 | tmp &= ~OSCCTRL_XOSCCTRL_CFDEN; |
| 3019 | tmp |= value << OSCCTRL_XOSCCTRL_CFDEN_Pos; |
| 3020 | ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; |
| 3021 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3022 | } |
| 3023 | |
| 3024 | static inline void hri_oscctrl_clear_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) |
| 3025 | { |
| 3026 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3027 | ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_CFDEN; |
| 3028 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3029 | } |
| 3030 | |
| 3031 | static inline void hri_oscctrl_toggle_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) |
| 3032 | { |
| 3033 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3034 | ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_CFDEN; |
| 3035 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3036 | } |
| 3037 | |
| 3038 | static inline void hri_oscctrl_set_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) |
| 3039 | { |
| 3040 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3041 | ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_SWBEN; |
| 3042 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3043 | } |
| 3044 | |
| 3045 | static inline bool hri_oscctrl_get_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) |
| 3046 | { |
| 3047 | uint32_t tmp; |
| 3048 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 3049 | tmp = (tmp & OSCCTRL_XOSCCTRL_SWBEN) >> OSCCTRL_XOSCCTRL_SWBEN_Pos; |
| 3050 | return (bool)tmp; |
| 3051 | } |
| 3052 | |
| 3053 | static inline void hri_oscctrl_write_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index, bool value) |
| 3054 | { |
| 3055 | uint32_t tmp; |
| 3056 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3057 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 3058 | tmp &= ~OSCCTRL_XOSCCTRL_SWBEN; |
| 3059 | tmp |= value << OSCCTRL_XOSCCTRL_SWBEN_Pos; |
| 3060 | ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; |
| 3061 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3062 | } |
| 3063 | |
| 3064 | static inline void hri_oscctrl_clear_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) |
| 3065 | { |
| 3066 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3067 | ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_SWBEN; |
| 3068 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3069 | } |
| 3070 | |
| 3071 | static inline void hri_oscctrl_toggle_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) |
| 3072 | { |
| 3073 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3074 | ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_SWBEN; |
| 3075 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3076 | } |
| 3077 | |
| 3078 | static inline void hri_oscctrl_set_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, |
| 3079 | hri_oscctrl_xoscctrl_reg_t mask) |
| 3080 | { |
| 3081 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3082 | ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_IPTAT(mask); |
| 3083 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3084 | } |
| 3085 | |
| 3086 | static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, |
| 3087 | hri_oscctrl_xoscctrl_reg_t mask) |
| 3088 | { |
| 3089 | uint32_t tmp; |
| 3090 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 3091 | tmp = (tmp & OSCCTRL_XOSCCTRL_IPTAT(mask)) >> OSCCTRL_XOSCCTRL_IPTAT_Pos; |
| 3092 | return tmp; |
| 3093 | } |
| 3094 | |
| 3095 | static inline void hri_oscctrl_write_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, |
| 3096 | hri_oscctrl_xoscctrl_reg_t data) |
| 3097 | { |
| 3098 | uint32_t tmp; |
| 3099 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3100 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 3101 | tmp &= ~OSCCTRL_XOSCCTRL_IPTAT_Msk; |
| 3102 | tmp |= OSCCTRL_XOSCCTRL_IPTAT(data); |
| 3103 | ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; |
| 3104 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3105 | } |
| 3106 | |
| 3107 | static inline void hri_oscctrl_clear_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, |
| 3108 | hri_oscctrl_xoscctrl_reg_t mask) |
| 3109 | { |
| 3110 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3111 | ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_IPTAT(mask); |
| 3112 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3113 | } |
| 3114 | |
| 3115 | static inline void hri_oscctrl_toggle_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, |
| 3116 | hri_oscctrl_xoscctrl_reg_t mask) |
| 3117 | { |
| 3118 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3119 | ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_IPTAT(mask); |
| 3120 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3121 | } |
| 3122 | |
| 3123 | static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index) |
| 3124 | { |
| 3125 | uint32_t tmp; |
| 3126 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 3127 | tmp = (tmp & OSCCTRL_XOSCCTRL_IPTAT_Msk) >> OSCCTRL_XOSCCTRL_IPTAT_Pos; |
| 3128 | return tmp; |
| 3129 | } |
| 3130 | |
| 3131 | static inline void hri_oscctrl_set_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, |
| 3132 | hri_oscctrl_xoscctrl_reg_t mask) |
| 3133 | { |
| 3134 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3135 | ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_IMULT(mask); |
| 3136 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3137 | } |
| 3138 | |
| 3139 | static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, |
| 3140 | hri_oscctrl_xoscctrl_reg_t mask) |
| 3141 | { |
| 3142 | uint32_t tmp; |
| 3143 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 3144 | tmp = (tmp & OSCCTRL_XOSCCTRL_IMULT(mask)) >> OSCCTRL_XOSCCTRL_IMULT_Pos; |
| 3145 | return tmp; |
| 3146 | } |
| 3147 | |
| 3148 | static inline void hri_oscctrl_write_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, |
| 3149 | hri_oscctrl_xoscctrl_reg_t data) |
| 3150 | { |
| 3151 | uint32_t tmp; |
| 3152 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3153 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 3154 | tmp &= ~OSCCTRL_XOSCCTRL_IMULT_Msk; |
| 3155 | tmp |= OSCCTRL_XOSCCTRL_IMULT(data); |
| 3156 | ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; |
| 3157 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3158 | } |
| 3159 | |
| 3160 | static inline void hri_oscctrl_clear_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, |
| 3161 | hri_oscctrl_xoscctrl_reg_t mask) |
| 3162 | { |
| 3163 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3164 | ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_IMULT(mask); |
| 3165 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3166 | } |
| 3167 | |
| 3168 | static inline void hri_oscctrl_toggle_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, |
| 3169 | hri_oscctrl_xoscctrl_reg_t mask) |
| 3170 | { |
| 3171 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3172 | ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_IMULT(mask); |
| 3173 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3174 | } |
| 3175 | |
| 3176 | static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index) |
| 3177 | { |
| 3178 | uint32_t tmp; |
| 3179 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 3180 | tmp = (tmp & OSCCTRL_XOSCCTRL_IMULT_Msk) >> OSCCTRL_XOSCCTRL_IMULT_Pos; |
| 3181 | return tmp; |
| 3182 | } |
| 3183 | |
| 3184 | static inline void hri_oscctrl_set_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, |
| 3185 | hri_oscctrl_xoscctrl_reg_t mask) |
| 3186 | { |
| 3187 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3188 | ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_STARTUP(mask); |
| 3189 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3190 | } |
| 3191 | |
| 3192 | static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, |
| 3193 | hri_oscctrl_xoscctrl_reg_t mask) |
| 3194 | { |
| 3195 | uint32_t tmp; |
| 3196 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 3197 | tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP(mask)) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; |
| 3198 | return tmp; |
| 3199 | } |
| 3200 | |
| 3201 | static inline void hri_oscctrl_write_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, |
| 3202 | hri_oscctrl_xoscctrl_reg_t data) |
| 3203 | { |
| 3204 | uint32_t tmp; |
| 3205 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3206 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 3207 | tmp &= ~OSCCTRL_XOSCCTRL_STARTUP_Msk; |
| 3208 | tmp |= OSCCTRL_XOSCCTRL_STARTUP(data); |
| 3209 | ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; |
| 3210 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3211 | } |
| 3212 | |
| 3213 | static inline void hri_oscctrl_clear_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, |
| 3214 | hri_oscctrl_xoscctrl_reg_t mask) |
| 3215 | { |
| 3216 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3217 | ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_STARTUP(mask); |
| 3218 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3219 | } |
| 3220 | |
| 3221 | static inline void hri_oscctrl_toggle_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, |
| 3222 | hri_oscctrl_xoscctrl_reg_t mask) |
| 3223 | { |
| 3224 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3225 | ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_STARTUP(mask); |
| 3226 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3227 | } |
| 3228 | |
| 3229 | static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index) |
| 3230 | { |
| 3231 | uint32_t tmp; |
| 3232 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 3233 | tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP_Msk) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; |
| 3234 | return tmp; |
| 3235 | } |
| 3236 | |
| 3237 | static inline void hri_oscctrl_set_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, |
| 3238 | hri_oscctrl_xoscctrl_reg_t mask) |
| 3239 | { |
| 3240 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3241 | ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_CFDPRESC(mask); |
| 3242 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3243 | } |
| 3244 | |
| 3245 | static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, |
| 3246 | hri_oscctrl_xoscctrl_reg_t mask) |
| 3247 | { |
| 3248 | uint32_t tmp; |
| 3249 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 3250 | tmp = (tmp & OSCCTRL_XOSCCTRL_CFDPRESC(mask)) >> OSCCTRL_XOSCCTRL_CFDPRESC_Pos; |
| 3251 | return tmp; |
| 3252 | } |
| 3253 | |
| 3254 | static inline void hri_oscctrl_write_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, |
| 3255 | hri_oscctrl_xoscctrl_reg_t data) |
| 3256 | { |
| 3257 | uint32_t tmp; |
| 3258 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3259 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 3260 | tmp &= ~OSCCTRL_XOSCCTRL_CFDPRESC_Msk; |
| 3261 | tmp |= OSCCTRL_XOSCCTRL_CFDPRESC(data); |
| 3262 | ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; |
| 3263 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3264 | } |
| 3265 | |
| 3266 | static inline void hri_oscctrl_clear_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, |
| 3267 | hri_oscctrl_xoscctrl_reg_t mask) |
| 3268 | { |
| 3269 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3270 | ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_CFDPRESC(mask); |
| 3271 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3272 | } |
| 3273 | |
| 3274 | static inline void hri_oscctrl_toggle_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, |
| 3275 | hri_oscctrl_xoscctrl_reg_t mask) |
| 3276 | { |
| 3277 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3278 | ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_CFDPRESC(mask); |
| 3279 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3280 | } |
| 3281 | |
| 3282 | static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index) |
| 3283 | { |
| 3284 | uint32_t tmp; |
| 3285 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 3286 | tmp = (tmp & OSCCTRL_XOSCCTRL_CFDPRESC_Msk) >> OSCCTRL_XOSCCTRL_CFDPRESC_Pos; |
| 3287 | return tmp; |
| 3288 | } |
| 3289 | |
| 3290 | static inline void hri_oscctrl_set_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask) |
| 3291 | { |
| 3292 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3293 | ((Oscctrl *)hw)->XOSCCTRL[index].reg |= mask; |
| 3294 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3295 | } |
| 3296 | |
| 3297 | static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_reg(const void *const hw, uint8_t index, |
| 3298 | hri_oscctrl_xoscctrl_reg_t mask) |
| 3299 | { |
| 3300 | uint32_t tmp; |
| 3301 | tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 3302 | tmp &= mask; |
| 3303 | return tmp; |
| 3304 | } |
| 3305 | |
| 3306 | static inline void hri_oscctrl_write_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t data) |
| 3307 | { |
| 3308 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3309 | ((Oscctrl *)hw)->XOSCCTRL[index].reg = data; |
| 3310 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3311 | } |
| 3312 | |
| 3313 | static inline void hri_oscctrl_clear_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask) |
| 3314 | { |
| 3315 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3316 | ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~mask; |
| 3317 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3318 | } |
| 3319 | |
| 3320 | static inline void hri_oscctrl_toggle_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask) |
| 3321 | { |
| 3322 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3323 | ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= mask; |
| 3324 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3325 | } |
| 3326 | |
| 3327 | static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_reg(const void *const hw, uint8_t index) |
| 3328 | { |
| 3329 | return ((Oscctrl *)hw)->XOSCCTRL[index].reg; |
| 3330 | } |
| 3331 | |
| 3332 | static inline void hri_oscctrl_set_DFLLCTRLA_ENABLE_bit(const void *const hw) |
| 3333 | { |
| 3334 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3335 | ((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ENABLE; |
| 3336 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3337 | } |
| 3338 | |
| 3339 | static inline bool hri_oscctrl_get_DFLLCTRLA_ENABLE_bit(const void *const hw) |
| 3340 | { |
| 3341 | uint8_t tmp; |
| 3342 | tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; |
| 3343 | tmp = (tmp & OSCCTRL_DFLLCTRLA_ENABLE) >> OSCCTRL_DFLLCTRLA_ENABLE_Pos; |
| 3344 | return (bool)tmp; |
| 3345 | } |
| 3346 | |
| 3347 | static inline void hri_oscctrl_write_DFLLCTRLA_ENABLE_bit(const void *const hw, bool value) |
| 3348 | { |
| 3349 | uint8_t tmp; |
| 3350 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3351 | tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; |
| 3352 | tmp &= ~OSCCTRL_DFLLCTRLA_ENABLE; |
| 3353 | tmp |= value << OSCCTRL_DFLLCTRLA_ENABLE_Pos; |
| 3354 | ((Oscctrl *)hw)->DFLLCTRLA.reg = tmp; |
| 3355 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3356 | } |
| 3357 | |
| 3358 | static inline void hri_oscctrl_clear_DFLLCTRLA_ENABLE_bit(const void *const hw) |
| 3359 | { |
| 3360 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3361 | ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_ENABLE; |
| 3362 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3363 | } |
| 3364 | |
| 3365 | static inline void hri_oscctrl_toggle_DFLLCTRLA_ENABLE_bit(const void *const hw) |
| 3366 | { |
| 3367 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3368 | ((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_ENABLE; |
| 3369 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3370 | } |
| 3371 | |
| 3372 | static inline void hri_oscctrl_set_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) |
| 3373 | { |
| 3374 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3375 | ((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_RUNSTDBY; |
| 3376 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3377 | } |
| 3378 | |
| 3379 | static inline bool hri_oscctrl_get_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) |
| 3380 | { |
| 3381 | uint8_t tmp; |
| 3382 | tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; |
| 3383 | tmp = (tmp & OSCCTRL_DFLLCTRLA_RUNSTDBY) >> OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos; |
| 3384 | return (bool)tmp; |
| 3385 | } |
| 3386 | |
| 3387 | static inline void hri_oscctrl_write_DFLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value) |
| 3388 | { |
| 3389 | uint8_t tmp; |
| 3390 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3391 | tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; |
| 3392 | tmp &= ~OSCCTRL_DFLLCTRLA_RUNSTDBY; |
| 3393 | tmp |= value << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos; |
| 3394 | ((Oscctrl *)hw)->DFLLCTRLA.reg = tmp; |
| 3395 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3396 | } |
| 3397 | |
| 3398 | static inline void hri_oscctrl_clear_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) |
| 3399 | { |
| 3400 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3401 | ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_RUNSTDBY; |
| 3402 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3403 | } |
| 3404 | |
| 3405 | static inline void hri_oscctrl_toggle_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) |
| 3406 | { |
| 3407 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3408 | ((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_RUNSTDBY; |
| 3409 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3410 | } |
| 3411 | |
| 3412 | static inline void hri_oscctrl_set_DFLLCTRLA_ONDEMAND_bit(const void *const hw) |
| 3413 | { |
| 3414 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3415 | ((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ONDEMAND; |
| 3416 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3417 | } |
| 3418 | |
| 3419 | static inline bool hri_oscctrl_get_DFLLCTRLA_ONDEMAND_bit(const void *const hw) |
| 3420 | { |
| 3421 | uint8_t tmp; |
| 3422 | tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; |
| 3423 | tmp = (tmp & OSCCTRL_DFLLCTRLA_ONDEMAND) >> OSCCTRL_DFLLCTRLA_ONDEMAND_Pos; |
| 3424 | return (bool)tmp; |
| 3425 | } |
| 3426 | |
| 3427 | static inline void hri_oscctrl_write_DFLLCTRLA_ONDEMAND_bit(const void *const hw, bool value) |
| 3428 | { |
| 3429 | uint8_t tmp; |
| 3430 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3431 | tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; |
| 3432 | tmp &= ~OSCCTRL_DFLLCTRLA_ONDEMAND; |
| 3433 | tmp |= value << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos; |
| 3434 | ((Oscctrl *)hw)->DFLLCTRLA.reg = tmp; |
| 3435 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3436 | } |
| 3437 | |
| 3438 | static inline void hri_oscctrl_clear_DFLLCTRLA_ONDEMAND_bit(const void *const hw) |
| 3439 | { |
| 3440 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3441 | ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_ONDEMAND; |
| 3442 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3443 | } |
| 3444 | |
| 3445 | static inline void hri_oscctrl_toggle_DFLLCTRLA_ONDEMAND_bit(const void *const hw) |
| 3446 | { |
| 3447 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3448 | ((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_ONDEMAND; |
| 3449 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3450 | } |
| 3451 | |
| 3452 | static inline void hri_oscctrl_set_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask) |
| 3453 | { |
| 3454 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3455 | ((Oscctrl *)hw)->DFLLCTRLA.reg |= mask; |
| 3456 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3457 | } |
| 3458 | |
| 3459 | static inline hri_oscctrl_dfllctrla_reg_t hri_oscctrl_get_DFLLCTRLA_reg(const void *const hw, |
| 3460 | hri_oscctrl_dfllctrla_reg_t mask) |
| 3461 | { |
| 3462 | uint8_t tmp; |
| 3463 | tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; |
| 3464 | tmp &= mask; |
| 3465 | return tmp; |
| 3466 | } |
| 3467 | |
| 3468 | static inline void hri_oscctrl_write_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t data) |
| 3469 | { |
| 3470 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3471 | ((Oscctrl *)hw)->DFLLCTRLA.reg = data; |
| 3472 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3473 | } |
| 3474 | |
| 3475 | static inline void hri_oscctrl_clear_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask) |
| 3476 | { |
| 3477 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3478 | ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~mask; |
| 3479 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3480 | } |
| 3481 | |
| 3482 | static inline void hri_oscctrl_toggle_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask) |
| 3483 | { |
| 3484 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3485 | ((Oscctrl *)hw)->DFLLCTRLA.reg ^= mask; |
| 3486 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3487 | } |
| 3488 | |
| 3489 | static inline hri_oscctrl_dfllctrla_reg_t hri_oscctrl_read_DFLLCTRLA_reg(const void *const hw) |
| 3490 | { |
| 3491 | return ((Oscctrl *)hw)->DFLLCTRLA.reg; |
| 3492 | } |
| 3493 | |
| 3494 | static inline void hri_oscctrl_set_DFLLCTRLB_MODE_bit(const void *const hw) |
| 3495 | { |
| 3496 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3497 | ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_MODE; |
| 3498 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3499 | } |
| 3500 | |
| 3501 | static inline bool hri_oscctrl_get_DFLLCTRLB_MODE_bit(const void *const hw) |
| 3502 | { |
| 3503 | uint8_t tmp; |
| 3504 | tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; |
| 3505 | tmp = (tmp & OSCCTRL_DFLLCTRLB_MODE) >> OSCCTRL_DFLLCTRLB_MODE_Pos; |
| 3506 | return (bool)tmp; |
| 3507 | } |
| 3508 | |
| 3509 | static inline void hri_oscctrl_write_DFLLCTRLB_MODE_bit(const void *const hw, bool value) |
| 3510 | { |
| 3511 | uint8_t tmp; |
| 3512 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3513 | tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; |
| 3514 | tmp &= ~OSCCTRL_DFLLCTRLB_MODE; |
| 3515 | tmp |= value << OSCCTRL_DFLLCTRLB_MODE_Pos; |
| 3516 | ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; |
| 3517 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3518 | } |
| 3519 | |
| 3520 | static inline void hri_oscctrl_clear_DFLLCTRLB_MODE_bit(const void *const hw) |
| 3521 | { |
| 3522 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3523 | ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_MODE; |
| 3524 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3525 | } |
| 3526 | |
| 3527 | static inline void hri_oscctrl_toggle_DFLLCTRLB_MODE_bit(const void *const hw) |
| 3528 | { |
| 3529 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3530 | ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_MODE; |
| 3531 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3532 | } |
| 3533 | |
| 3534 | static inline void hri_oscctrl_set_DFLLCTRLB_STABLE_bit(const void *const hw) |
| 3535 | { |
| 3536 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3537 | ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_STABLE; |
| 3538 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3539 | } |
| 3540 | |
| 3541 | static inline bool hri_oscctrl_get_DFLLCTRLB_STABLE_bit(const void *const hw) |
| 3542 | { |
| 3543 | uint8_t tmp; |
| 3544 | tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; |
| 3545 | tmp = (tmp & OSCCTRL_DFLLCTRLB_STABLE) >> OSCCTRL_DFLLCTRLB_STABLE_Pos; |
| 3546 | return (bool)tmp; |
| 3547 | } |
| 3548 | |
| 3549 | static inline void hri_oscctrl_write_DFLLCTRLB_STABLE_bit(const void *const hw, bool value) |
| 3550 | { |
| 3551 | uint8_t tmp; |
| 3552 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3553 | tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; |
| 3554 | tmp &= ~OSCCTRL_DFLLCTRLB_STABLE; |
| 3555 | tmp |= value << OSCCTRL_DFLLCTRLB_STABLE_Pos; |
| 3556 | ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; |
| 3557 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3558 | } |
| 3559 | |
| 3560 | static inline void hri_oscctrl_clear_DFLLCTRLB_STABLE_bit(const void *const hw) |
| 3561 | { |
| 3562 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3563 | ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_STABLE; |
| 3564 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3565 | } |
| 3566 | |
| 3567 | static inline void hri_oscctrl_toggle_DFLLCTRLB_STABLE_bit(const void *const hw) |
| 3568 | { |
| 3569 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3570 | ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_STABLE; |
| 3571 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3572 | } |
| 3573 | |
| 3574 | static inline void hri_oscctrl_set_DFLLCTRLB_LLAW_bit(const void *const hw) |
| 3575 | { |
| 3576 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3577 | ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_LLAW; |
| 3578 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3579 | } |
| 3580 | |
| 3581 | static inline bool hri_oscctrl_get_DFLLCTRLB_LLAW_bit(const void *const hw) |
| 3582 | { |
| 3583 | uint8_t tmp; |
| 3584 | tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; |
| 3585 | tmp = (tmp & OSCCTRL_DFLLCTRLB_LLAW) >> OSCCTRL_DFLLCTRLB_LLAW_Pos; |
| 3586 | return (bool)tmp; |
| 3587 | } |
| 3588 | |
| 3589 | static inline void hri_oscctrl_write_DFLLCTRLB_LLAW_bit(const void *const hw, bool value) |
| 3590 | { |
| 3591 | uint8_t tmp; |
| 3592 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3593 | tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; |
| 3594 | tmp &= ~OSCCTRL_DFLLCTRLB_LLAW; |
| 3595 | tmp |= value << OSCCTRL_DFLLCTRLB_LLAW_Pos; |
| 3596 | ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; |
| 3597 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3598 | } |
| 3599 | |
| 3600 | static inline void hri_oscctrl_clear_DFLLCTRLB_LLAW_bit(const void *const hw) |
| 3601 | { |
| 3602 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3603 | ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_LLAW; |
| 3604 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3605 | } |
| 3606 | |
| 3607 | static inline void hri_oscctrl_toggle_DFLLCTRLB_LLAW_bit(const void *const hw) |
| 3608 | { |
| 3609 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3610 | ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_LLAW; |
| 3611 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3612 | } |
| 3613 | |
| 3614 | static inline void hri_oscctrl_set_DFLLCTRLB_USBCRM_bit(const void *const hw) |
| 3615 | { |
| 3616 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3617 | ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_USBCRM; |
| 3618 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3619 | } |
| 3620 | |
| 3621 | static inline bool hri_oscctrl_get_DFLLCTRLB_USBCRM_bit(const void *const hw) |
| 3622 | { |
| 3623 | uint8_t tmp; |
| 3624 | tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; |
| 3625 | tmp = (tmp & OSCCTRL_DFLLCTRLB_USBCRM) >> OSCCTRL_DFLLCTRLB_USBCRM_Pos; |
| 3626 | return (bool)tmp; |
| 3627 | } |
| 3628 | |
| 3629 | static inline void hri_oscctrl_write_DFLLCTRLB_USBCRM_bit(const void *const hw, bool value) |
| 3630 | { |
| 3631 | uint8_t tmp; |
| 3632 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3633 | tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; |
| 3634 | tmp &= ~OSCCTRL_DFLLCTRLB_USBCRM; |
| 3635 | tmp |= value << OSCCTRL_DFLLCTRLB_USBCRM_Pos; |
| 3636 | ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; |
| 3637 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3638 | } |
| 3639 | |
| 3640 | static inline void hri_oscctrl_clear_DFLLCTRLB_USBCRM_bit(const void *const hw) |
| 3641 | { |
| 3642 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3643 | ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_USBCRM; |
| 3644 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3645 | } |
| 3646 | |
| 3647 | static inline void hri_oscctrl_toggle_DFLLCTRLB_USBCRM_bit(const void *const hw) |
| 3648 | { |
| 3649 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3650 | ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_USBCRM; |
| 3651 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3652 | } |
| 3653 | |
| 3654 | static inline void hri_oscctrl_set_DFLLCTRLB_CCDIS_bit(const void *const hw) |
| 3655 | { |
| 3656 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3657 | ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_CCDIS; |
| 3658 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3659 | } |
| 3660 | |
| 3661 | static inline bool hri_oscctrl_get_DFLLCTRLB_CCDIS_bit(const void *const hw) |
| 3662 | { |
| 3663 | uint8_t tmp; |
| 3664 | tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; |
| 3665 | tmp = (tmp & OSCCTRL_DFLLCTRLB_CCDIS) >> OSCCTRL_DFLLCTRLB_CCDIS_Pos; |
| 3666 | return (bool)tmp; |
| 3667 | } |
| 3668 | |
| 3669 | static inline void hri_oscctrl_write_DFLLCTRLB_CCDIS_bit(const void *const hw, bool value) |
| 3670 | { |
| 3671 | uint8_t tmp; |
| 3672 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3673 | tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; |
| 3674 | tmp &= ~OSCCTRL_DFLLCTRLB_CCDIS; |
| 3675 | tmp |= value << OSCCTRL_DFLLCTRLB_CCDIS_Pos; |
| 3676 | ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; |
| 3677 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3678 | } |
| 3679 | |
| 3680 | static inline void hri_oscctrl_clear_DFLLCTRLB_CCDIS_bit(const void *const hw) |
| 3681 | { |
| 3682 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3683 | ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_CCDIS; |
| 3684 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3685 | } |
| 3686 | |
| 3687 | static inline void hri_oscctrl_toggle_DFLLCTRLB_CCDIS_bit(const void *const hw) |
| 3688 | { |
| 3689 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3690 | ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_CCDIS; |
| 3691 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3692 | } |
| 3693 | |
| 3694 | static inline void hri_oscctrl_set_DFLLCTRLB_QLDIS_bit(const void *const hw) |
| 3695 | { |
| 3696 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3697 | ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_QLDIS; |
| 3698 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3699 | } |
| 3700 | |
| 3701 | static inline bool hri_oscctrl_get_DFLLCTRLB_QLDIS_bit(const void *const hw) |
| 3702 | { |
| 3703 | uint8_t tmp; |
| 3704 | tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; |
| 3705 | tmp = (tmp & OSCCTRL_DFLLCTRLB_QLDIS) >> OSCCTRL_DFLLCTRLB_QLDIS_Pos; |
| 3706 | return (bool)tmp; |
| 3707 | } |
| 3708 | |
| 3709 | static inline void hri_oscctrl_write_DFLLCTRLB_QLDIS_bit(const void *const hw, bool value) |
| 3710 | { |
| 3711 | uint8_t tmp; |
| 3712 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3713 | tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; |
| 3714 | tmp &= ~OSCCTRL_DFLLCTRLB_QLDIS; |
| 3715 | tmp |= value << OSCCTRL_DFLLCTRLB_QLDIS_Pos; |
| 3716 | ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; |
| 3717 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3718 | } |
| 3719 | |
| 3720 | static inline void hri_oscctrl_clear_DFLLCTRLB_QLDIS_bit(const void *const hw) |
| 3721 | { |
| 3722 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3723 | ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_QLDIS; |
| 3724 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3725 | } |
| 3726 | |
| 3727 | static inline void hri_oscctrl_toggle_DFLLCTRLB_QLDIS_bit(const void *const hw) |
| 3728 | { |
| 3729 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3730 | ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_QLDIS; |
| 3731 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3732 | } |
| 3733 | |
| 3734 | static inline void hri_oscctrl_set_DFLLCTRLB_BPLCKC_bit(const void *const hw) |
| 3735 | { |
| 3736 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3737 | ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_BPLCKC; |
| 3738 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3739 | } |
| 3740 | |
| 3741 | static inline bool hri_oscctrl_get_DFLLCTRLB_BPLCKC_bit(const void *const hw) |
| 3742 | { |
| 3743 | uint8_t tmp; |
| 3744 | tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; |
| 3745 | tmp = (tmp & OSCCTRL_DFLLCTRLB_BPLCKC) >> OSCCTRL_DFLLCTRLB_BPLCKC_Pos; |
| 3746 | return (bool)tmp; |
| 3747 | } |
| 3748 | |
| 3749 | static inline void hri_oscctrl_write_DFLLCTRLB_BPLCKC_bit(const void *const hw, bool value) |
| 3750 | { |
| 3751 | uint8_t tmp; |
| 3752 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3753 | tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; |
| 3754 | tmp &= ~OSCCTRL_DFLLCTRLB_BPLCKC; |
| 3755 | tmp |= value << OSCCTRL_DFLLCTRLB_BPLCKC_Pos; |
| 3756 | ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; |
| 3757 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3758 | } |
| 3759 | |
| 3760 | static inline void hri_oscctrl_clear_DFLLCTRLB_BPLCKC_bit(const void *const hw) |
| 3761 | { |
| 3762 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3763 | ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_BPLCKC; |
| 3764 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3765 | } |
| 3766 | |
| 3767 | static inline void hri_oscctrl_toggle_DFLLCTRLB_BPLCKC_bit(const void *const hw) |
| 3768 | { |
| 3769 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3770 | ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_BPLCKC; |
| 3771 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3772 | } |
| 3773 | |
| 3774 | static inline void hri_oscctrl_set_DFLLCTRLB_WAITLOCK_bit(const void *const hw) |
| 3775 | { |
| 3776 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3777 | ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_WAITLOCK; |
| 3778 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3779 | } |
| 3780 | |
| 3781 | static inline bool hri_oscctrl_get_DFLLCTRLB_WAITLOCK_bit(const void *const hw) |
| 3782 | { |
| 3783 | uint8_t tmp; |
| 3784 | tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; |
| 3785 | tmp = (tmp & OSCCTRL_DFLLCTRLB_WAITLOCK) >> OSCCTRL_DFLLCTRLB_WAITLOCK_Pos; |
| 3786 | return (bool)tmp; |
| 3787 | } |
| 3788 | |
| 3789 | static inline void hri_oscctrl_write_DFLLCTRLB_WAITLOCK_bit(const void *const hw, bool value) |
| 3790 | { |
| 3791 | uint8_t tmp; |
| 3792 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3793 | tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; |
| 3794 | tmp &= ~OSCCTRL_DFLLCTRLB_WAITLOCK; |
| 3795 | tmp |= value << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos; |
| 3796 | ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; |
| 3797 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3798 | } |
| 3799 | |
| 3800 | static inline void hri_oscctrl_clear_DFLLCTRLB_WAITLOCK_bit(const void *const hw) |
| 3801 | { |
| 3802 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3803 | ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_WAITLOCK; |
| 3804 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3805 | } |
| 3806 | |
| 3807 | static inline void hri_oscctrl_toggle_DFLLCTRLB_WAITLOCK_bit(const void *const hw) |
| 3808 | { |
| 3809 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3810 | ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_WAITLOCK; |
| 3811 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3812 | } |
| 3813 | |
| 3814 | static inline void hri_oscctrl_set_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask) |
| 3815 | { |
| 3816 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3817 | ((Oscctrl *)hw)->DFLLCTRLB.reg |= mask; |
| 3818 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3819 | } |
| 3820 | |
| 3821 | static inline hri_oscctrl_dfllctrlb_reg_t hri_oscctrl_get_DFLLCTRLB_reg(const void *const hw, |
| 3822 | hri_oscctrl_dfllctrlb_reg_t mask) |
| 3823 | { |
| 3824 | uint8_t tmp; |
| 3825 | tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; |
| 3826 | tmp &= mask; |
| 3827 | return tmp; |
| 3828 | } |
| 3829 | |
| 3830 | static inline void hri_oscctrl_write_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t data) |
| 3831 | { |
| 3832 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3833 | ((Oscctrl *)hw)->DFLLCTRLB.reg = data; |
| 3834 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3835 | } |
| 3836 | |
| 3837 | static inline void hri_oscctrl_clear_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask) |
| 3838 | { |
| 3839 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3840 | ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~mask; |
| 3841 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3842 | } |
| 3843 | |
| 3844 | static inline void hri_oscctrl_toggle_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask) |
| 3845 | { |
| 3846 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3847 | ((Oscctrl *)hw)->DFLLCTRLB.reg ^= mask; |
| 3848 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3849 | } |
| 3850 | |
| 3851 | static inline hri_oscctrl_dfllctrlb_reg_t hri_oscctrl_read_DFLLCTRLB_reg(const void *const hw) |
| 3852 | { |
| 3853 | return ((Oscctrl *)hw)->DFLLCTRLB.reg; |
| 3854 | } |
| 3855 | |
| 3856 | static inline void hri_oscctrl_set_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) |
| 3857 | { |
| 3858 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3859 | ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_FINE(mask); |
| 3860 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3861 | } |
| 3862 | |
| 3863 | static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_FINE_bf(const void *const hw, |
| 3864 | hri_oscctrl_dfllval_reg_t mask) |
| 3865 | { |
| 3866 | uint32_t tmp; |
| 3867 | tmp = ((Oscctrl *)hw)->DFLLVAL.reg; |
| 3868 | tmp = (tmp & OSCCTRL_DFLLVAL_FINE(mask)) >> OSCCTRL_DFLLVAL_FINE_Pos; |
| 3869 | return tmp; |
| 3870 | } |
| 3871 | |
| 3872 | static inline void hri_oscctrl_write_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) |
| 3873 | { |
| 3874 | uint32_t tmp; |
| 3875 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3876 | tmp = ((Oscctrl *)hw)->DFLLVAL.reg; |
| 3877 | tmp &= ~OSCCTRL_DFLLVAL_FINE_Msk; |
| 3878 | tmp |= OSCCTRL_DFLLVAL_FINE(data); |
| 3879 | ((Oscctrl *)hw)->DFLLVAL.reg = tmp; |
| 3880 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3881 | } |
| 3882 | |
| 3883 | static inline void hri_oscctrl_clear_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) |
| 3884 | { |
| 3885 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3886 | ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_FINE(mask); |
| 3887 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3888 | } |
| 3889 | |
| 3890 | static inline void hri_oscctrl_toggle_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) |
| 3891 | { |
| 3892 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3893 | ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_FINE(mask); |
| 3894 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3895 | } |
| 3896 | |
| 3897 | static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_FINE_bf(const void *const hw) |
| 3898 | { |
| 3899 | uint32_t tmp; |
| 3900 | tmp = ((Oscctrl *)hw)->DFLLVAL.reg; |
| 3901 | tmp = (tmp & OSCCTRL_DFLLVAL_FINE_Msk) >> OSCCTRL_DFLLVAL_FINE_Pos; |
| 3902 | return tmp; |
| 3903 | } |
| 3904 | |
| 3905 | static inline void hri_oscctrl_set_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) |
| 3906 | { |
| 3907 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3908 | ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_COARSE(mask); |
| 3909 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3910 | } |
| 3911 | |
| 3912 | static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_COARSE_bf(const void *const hw, |
| 3913 | hri_oscctrl_dfllval_reg_t mask) |
| 3914 | { |
| 3915 | uint32_t tmp; |
| 3916 | tmp = ((Oscctrl *)hw)->DFLLVAL.reg; |
| 3917 | tmp = (tmp & OSCCTRL_DFLLVAL_COARSE(mask)) >> OSCCTRL_DFLLVAL_COARSE_Pos; |
| 3918 | return tmp; |
| 3919 | } |
| 3920 | |
| 3921 | static inline void hri_oscctrl_write_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) |
| 3922 | { |
| 3923 | uint32_t tmp; |
| 3924 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3925 | tmp = ((Oscctrl *)hw)->DFLLVAL.reg; |
| 3926 | tmp &= ~OSCCTRL_DFLLVAL_COARSE_Msk; |
| 3927 | tmp |= OSCCTRL_DFLLVAL_COARSE(data); |
| 3928 | ((Oscctrl *)hw)->DFLLVAL.reg = tmp; |
| 3929 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3930 | } |
| 3931 | |
| 3932 | static inline void hri_oscctrl_clear_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) |
| 3933 | { |
| 3934 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3935 | ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_COARSE(mask); |
| 3936 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3937 | } |
| 3938 | |
| 3939 | static inline void hri_oscctrl_toggle_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) |
| 3940 | { |
| 3941 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3942 | ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_COARSE(mask); |
| 3943 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3944 | } |
| 3945 | |
| 3946 | static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_COARSE_bf(const void *const hw) |
| 3947 | { |
| 3948 | uint32_t tmp; |
| 3949 | tmp = ((Oscctrl *)hw)->DFLLVAL.reg; |
| 3950 | tmp = (tmp & OSCCTRL_DFLLVAL_COARSE_Msk) >> OSCCTRL_DFLLVAL_COARSE_Pos; |
| 3951 | return tmp; |
| 3952 | } |
| 3953 | |
| 3954 | static inline void hri_oscctrl_set_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) |
| 3955 | { |
| 3956 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3957 | ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_DIFF(mask); |
| 3958 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3959 | } |
| 3960 | |
| 3961 | static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_DIFF_bf(const void *const hw, |
| 3962 | hri_oscctrl_dfllval_reg_t mask) |
| 3963 | { |
| 3964 | uint32_t tmp; |
| 3965 | tmp = ((Oscctrl *)hw)->DFLLVAL.reg; |
| 3966 | tmp = (tmp & OSCCTRL_DFLLVAL_DIFF(mask)) >> OSCCTRL_DFLLVAL_DIFF_Pos; |
| 3967 | return tmp; |
| 3968 | } |
| 3969 | |
| 3970 | static inline void hri_oscctrl_write_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) |
| 3971 | { |
| 3972 | uint32_t tmp; |
| 3973 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3974 | tmp = ((Oscctrl *)hw)->DFLLVAL.reg; |
| 3975 | tmp &= ~OSCCTRL_DFLLVAL_DIFF_Msk; |
| 3976 | tmp |= OSCCTRL_DFLLVAL_DIFF(data); |
| 3977 | ((Oscctrl *)hw)->DFLLVAL.reg = tmp; |
| 3978 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3979 | } |
| 3980 | |
| 3981 | static inline void hri_oscctrl_clear_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) |
| 3982 | { |
| 3983 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3984 | ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_DIFF(mask); |
| 3985 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3986 | } |
| 3987 | |
| 3988 | static inline void hri_oscctrl_toggle_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) |
| 3989 | { |
| 3990 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 3991 | ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_DIFF(mask); |
| 3992 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 3993 | } |
| 3994 | |
| 3995 | static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_DIFF_bf(const void *const hw) |
| 3996 | { |
| 3997 | uint32_t tmp; |
| 3998 | tmp = ((Oscctrl *)hw)->DFLLVAL.reg; |
| 3999 | tmp = (tmp & OSCCTRL_DFLLVAL_DIFF_Msk) >> OSCCTRL_DFLLVAL_DIFF_Pos; |
| 4000 | return tmp; |
| 4001 | } |
| 4002 | |
| 4003 | static inline void hri_oscctrl_set_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) |
| 4004 | { |
| 4005 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4006 | ((Oscctrl *)hw)->DFLLVAL.reg |= mask; |
| 4007 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4008 | } |
| 4009 | |
| 4010 | static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_reg(const void *const hw, |
| 4011 | hri_oscctrl_dfllval_reg_t mask) |
| 4012 | { |
| 4013 | uint32_t tmp; |
| 4014 | tmp = ((Oscctrl *)hw)->DFLLVAL.reg; |
| 4015 | tmp &= mask; |
| 4016 | return tmp; |
| 4017 | } |
| 4018 | |
| 4019 | static inline void hri_oscctrl_write_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t data) |
| 4020 | { |
| 4021 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4022 | ((Oscctrl *)hw)->DFLLVAL.reg = data; |
| 4023 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4024 | } |
| 4025 | |
| 4026 | static inline void hri_oscctrl_clear_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) |
| 4027 | { |
| 4028 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4029 | ((Oscctrl *)hw)->DFLLVAL.reg &= ~mask; |
| 4030 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4031 | } |
| 4032 | |
| 4033 | static inline void hri_oscctrl_toggle_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) |
| 4034 | { |
| 4035 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4036 | ((Oscctrl *)hw)->DFLLVAL.reg ^= mask; |
| 4037 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4038 | } |
| 4039 | |
| 4040 | static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_reg(const void *const hw) |
| 4041 | { |
| 4042 | return ((Oscctrl *)hw)->DFLLVAL.reg; |
| 4043 | } |
| 4044 | |
| 4045 | static inline void hri_oscctrl_set_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) |
| 4046 | { |
| 4047 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4048 | ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_MUL(mask); |
| 4049 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4050 | } |
| 4051 | |
| 4052 | static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_MUL_bf(const void *const hw, |
| 4053 | hri_oscctrl_dfllmul_reg_t mask) |
| 4054 | { |
| 4055 | uint32_t tmp; |
| 4056 | tmp = ((Oscctrl *)hw)->DFLLMUL.reg; |
| 4057 | tmp = (tmp & OSCCTRL_DFLLMUL_MUL(mask)) >> OSCCTRL_DFLLMUL_MUL_Pos; |
| 4058 | return tmp; |
| 4059 | } |
| 4060 | |
| 4061 | static inline void hri_oscctrl_write_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) |
| 4062 | { |
| 4063 | uint32_t tmp; |
| 4064 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4065 | tmp = ((Oscctrl *)hw)->DFLLMUL.reg; |
| 4066 | tmp &= ~OSCCTRL_DFLLMUL_MUL_Msk; |
| 4067 | tmp |= OSCCTRL_DFLLMUL_MUL(data); |
| 4068 | ((Oscctrl *)hw)->DFLLMUL.reg = tmp; |
| 4069 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4070 | } |
| 4071 | |
| 4072 | static inline void hri_oscctrl_clear_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) |
| 4073 | { |
| 4074 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4075 | ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_MUL(mask); |
| 4076 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4077 | } |
| 4078 | |
| 4079 | static inline void hri_oscctrl_toggle_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) |
| 4080 | { |
| 4081 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4082 | ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_MUL(mask); |
| 4083 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4084 | } |
| 4085 | |
| 4086 | static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_MUL_bf(const void *const hw) |
| 4087 | { |
| 4088 | uint32_t tmp; |
| 4089 | tmp = ((Oscctrl *)hw)->DFLLMUL.reg; |
| 4090 | tmp = (tmp & OSCCTRL_DFLLMUL_MUL_Msk) >> OSCCTRL_DFLLMUL_MUL_Pos; |
| 4091 | return tmp; |
| 4092 | } |
| 4093 | |
| 4094 | static inline void hri_oscctrl_set_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) |
| 4095 | { |
| 4096 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4097 | ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_FSTEP(mask); |
| 4098 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4099 | } |
| 4100 | |
| 4101 | static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_FSTEP_bf(const void *const hw, |
| 4102 | hri_oscctrl_dfllmul_reg_t mask) |
| 4103 | { |
| 4104 | uint32_t tmp; |
| 4105 | tmp = ((Oscctrl *)hw)->DFLLMUL.reg; |
| 4106 | tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP(mask)) >> OSCCTRL_DFLLMUL_FSTEP_Pos; |
| 4107 | return tmp; |
| 4108 | } |
| 4109 | |
| 4110 | static inline void hri_oscctrl_write_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) |
| 4111 | { |
| 4112 | uint32_t tmp; |
| 4113 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4114 | tmp = ((Oscctrl *)hw)->DFLLMUL.reg; |
| 4115 | tmp &= ~OSCCTRL_DFLLMUL_FSTEP_Msk; |
| 4116 | tmp |= OSCCTRL_DFLLMUL_FSTEP(data); |
| 4117 | ((Oscctrl *)hw)->DFLLMUL.reg = tmp; |
| 4118 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4119 | } |
| 4120 | |
| 4121 | static inline void hri_oscctrl_clear_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) |
| 4122 | { |
| 4123 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4124 | ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_FSTEP(mask); |
| 4125 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4126 | } |
| 4127 | |
| 4128 | static inline void hri_oscctrl_toggle_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) |
| 4129 | { |
| 4130 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4131 | ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_FSTEP(mask); |
| 4132 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4133 | } |
| 4134 | |
| 4135 | static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_FSTEP_bf(const void *const hw) |
| 4136 | { |
| 4137 | uint32_t tmp; |
| 4138 | tmp = ((Oscctrl *)hw)->DFLLMUL.reg; |
| 4139 | tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP_Msk) >> OSCCTRL_DFLLMUL_FSTEP_Pos; |
| 4140 | return tmp; |
| 4141 | } |
| 4142 | |
| 4143 | static inline void hri_oscctrl_set_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) |
| 4144 | { |
| 4145 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4146 | ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_CSTEP(mask); |
| 4147 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4148 | } |
| 4149 | |
| 4150 | static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_CSTEP_bf(const void *const hw, |
| 4151 | hri_oscctrl_dfllmul_reg_t mask) |
| 4152 | { |
| 4153 | uint32_t tmp; |
| 4154 | tmp = ((Oscctrl *)hw)->DFLLMUL.reg; |
| 4155 | tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP(mask)) >> OSCCTRL_DFLLMUL_CSTEP_Pos; |
| 4156 | return tmp; |
| 4157 | } |
| 4158 | |
| 4159 | static inline void hri_oscctrl_write_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) |
| 4160 | { |
| 4161 | uint32_t tmp; |
| 4162 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4163 | tmp = ((Oscctrl *)hw)->DFLLMUL.reg; |
| 4164 | tmp &= ~OSCCTRL_DFLLMUL_CSTEP_Msk; |
| 4165 | tmp |= OSCCTRL_DFLLMUL_CSTEP(data); |
| 4166 | ((Oscctrl *)hw)->DFLLMUL.reg = tmp; |
| 4167 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4168 | } |
| 4169 | |
| 4170 | static inline void hri_oscctrl_clear_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) |
| 4171 | { |
| 4172 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4173 | ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_CSTEP(mask); |
| 4174 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4175 | } |
| 4176 | |
| 4177 | static inline void hri_oscctrl_toggle_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) |
| 4178 | { |
| 4179 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4180 | ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_CSTEP(mask); |
| 4181 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4182 | } |
| 4183 | |
| 4184 | static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_CSTEP_bf(const void *const hw) |
| 4185 | { |
| 4186 | uint32_t tmp; |
| 4187 | tmp = ((Oscctrl *)hw)->DFLLMUL.reg; |
| 4188 | tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP_Msk) >> OSCCTRL_DFLLMUL_CSTEP_Pos; |
| 4189 | return tmp; |
| 4190 | } |
| 4191 | |
| 4192 | static inline void hri_oscctrl_set_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) |
| 4193 | { |
| 4194 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4195 | ((Oscctrl *)hw)->DFLLMUL.reg |= mask; |
| 4196 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4197 | } |
| 4198 | |
| 4199 | static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_reg(const void *const hw, |
| 4200 | hri_oscctrl_dfllmul_reg_t mask) |
| 4201 | { |
| 4202 | uint32_t tmp; |
| 4203 | tmp = ((Oscctrl *)hw)->DFLLMUL.reg; |
| 4204 | tmp &= mask; |
| 4205 | return tmp; |
| 4206 | } |
| 4207 | |
| 4208 | static inline void hri_oscctrl_write_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t data) |
| 4209 | { |
| 4210 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4211 | ((Oscctrl *)hw)->DFLLMUL.reg = data; |
| 4212 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4213 | } |
| 4214 | |
| 4215 | static inline void hri_oscctrl_clear_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) |
| 4216 | { |
| 4217 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4218 | ((Oscctrl *)hw)->DFLLMUL.reg &= ~mask; |
| 4219 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4220 | } |
| 4221 | |
| 4222 | static inline void hri_oscctrl_toggle_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) |
| 4223 | { |
| 4224 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4225 | ((Oscctrl *)hw)->DFLLMUL.reg ^= mask; |
| 4226 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4227 | } |
| 4228 | |
| 4229 | static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_reg(const void *const hw) |
| 4230 | { |
| 4231 | return ((Oscctrl *)hw)->DFLLMUL.reg; |
| 4232 | } |
| 4233 | |
| 4234 | static inline void hri_oscctrl_set_DFLLSYNC_ENABLE_bit(const void *const hw) |
| 4235 | { |
| 4236 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4237 | ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_ENABLE; |
| 4238 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4239 | } |
| 4240 | |
| 4241 | static inline bool hri_oscctrl_get_DFLLSYNC_ENABLE_bit(const void *const hw) |
| 4242 | { |
| 4243 | uint8_t tmp; |
| 4244 | tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; |
| 4245 | tmp = (tmp & OSCCTRL_DFLLSYNC_ENABLE) >> OSCCTRL_DFLLSYNC_ENABLE_Pos; |
| 4246 | return (bool)tmp; |
| 4247 | } |
| 4248 | |
| 4249 | static inline void hri_oscctrl_write_DFLLSYNC_ENABLE_bit(const void *const hw, bool value) |
| 4250 | { |
| 4251 | uint8_t tmp; |
| 4252 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4253 | tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; |
| 4254 | tmp &= ~OSCCTRL_DFLLSYNC_ENABLE; |
| 4255 | tmp |= value << OSCCTRL_DFLLSYNC_ENABLE_Pos; |
| 4256 | ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; |
| 4257 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4258 | } |
| 4259 | |
| 4260 | static inline void hri_oscctrl_clear_DFLLSYNC_ENABLE_bit(const void *const hw) |
| 4261 | { |
| 4262 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4263 | ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_ENABLE; |
| 4264 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4265 | } |
| 4266 | |
| 4267 | static inline void hri_oscctrl_toggle_DFLLSYNC_ENABLE_bit(const void *const hw) |
| 4268 | { |
| 4269 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4270 | ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_ENABLE; |
| 4271 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4272 | } |
| 4273 | |
| 4274 | static inline void hri_oscctrl_set_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) |
| 4275 | { |
| 4276 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4277 | ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLCTRLB; |
| 4278 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4279 | } |
| 4280 | |
| 4281 | static inline bool hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) |
| 4282 | { |
| 4283 | uint8_t tmp; |
| 4284 | tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; |
| 4285 | tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLCTRLB) >> OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos; |
| 4286 | return (bool)tmp; |
| 4287 | } |
| 4288 | |
| 4289 | static inline void hri_oscctrl_write_DFLLSYNC_DFLLCTRLB_bit(const void *const hw, bool value) |
| 4290 | { |
| 4291 | uint8_t tmp; |
| 4292 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4293 | tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; |
| 4294 | tmp &= ~OSCCTRL_DFLLSYNC_DFLLCTRLB; |
| 4295 | tmp |= value << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos; |
| 4296 | ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; |
| 4297 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4298 | } |
| 4299 | |
| 4300 | static inline void hri_oscctrl_clear_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) |
| 4301 | { |
| 4302 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4303 | ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLCTRLB; |
| 4304 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4305 | } |
| 4306 | |
| 4307 | static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) |
| 4308 | { |
| 4309 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4310 | ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLCTRLB; |
| 4311 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4312 | } |
| 4313 | |
| 4314 | static inline void hri_oscctrl_set_DFLLSYNC_DFLLVAL_bit(const void *const hw) |
| 4315 | { |
| 4316 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4317 | ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLVAL; |
| 4318 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4319 | } |
| 4320 | |
| 4321 | static inline bool hri_oscctrl_get_DFLLSYNC_DFLLVAL_bit(const void *const hw) |
| 4322 | { |
| 4323 | uint8_t tmp; |
| 4324 | tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; |
| 4325 | tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLVAL) >> OSCCTRL_DFLLSYNC_DFLLVAL_Pos; |
| 4326 | return (bool)tmp; |
| 4327 | } |
| 4328 | |
| 4329 | static inline void hri_oscctrl_write_DFLLSYNC_DFLLVAL_bit(const void *const hw, bool value) |
| 4330 | { |
| 4331 | uint8_t tmp; |
| 4332 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4333 | tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; |
| 4334 | tmp &= ~OSCCTRL_DFLLSYNC_DFLLVAL; |
| 4335 | tmp |= value << OSCCTRL_DFLLSYNC_DFLLVAL_Pos; |
| 4336 | ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; |
| 4337 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4338 | } |
| 4339 | |
| 4340 | static inline void hri_oscctrl_clear_DFLLSYNC_DFLLVAL_bit(const void *const hw) |
| 4341 | { |
| 4342 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4343 | ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLVAL; |
| 4344 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4345 | } |
| 4346 | |
| 4347 | static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLVAL_bit(const void *const hw) |
| 4348 | { |
| 4349 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4350 | ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLVAL; |
| 4351 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4352 | } |
| 4353 | |
| 4354 | static inline void hri_oscctrl_set_DFLLSYNC_DFLLMUL_bit(const void *const hw) |
| 4355 | { |
| 4356 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4357 | ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLMUL; |
| 4358 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4359 | } |
| 4360 | |
| 4361 | static inline bool hri_oscctrl_get_DFLLSYNC_DFLLMUL_bit(const void *const hw) |
| 4362 | { |
| 4363 | uint8_t tmp; |
| 4364 | tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; |
| 4365 | tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLMUL) >> OSCCTRL_DFLLSYNC_DFLLMUL_Pos; |
| 4366 | return (bool)tmp; |
| 4367 | } |
| 4368 | |
| 4369 | static inline void hri_oscctrl_write_DFLLSYNC_DFLLMUL_bit(const void *const hw, bool value) |
| 4370 | { |
| 4371 | uint8_t tmp; |
| 4372 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4373 | tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; |
| 4374 | tmp &= ~OSCCTRL_DFLLSYNC_DFLLMUL; |
| 4375 | tmp |= value << OSCCTRL_DFLLSYNC_DFLLMUL_Pos; |
| 4376 | ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; |
| 4377 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4378 | } |
| 4379 | |
| 4380 | static inline void hri_oscctrl_clear_DFLLSYNC_DFLLMUL_bit(const void *const hw) |
| 4381 | { |
| 4382 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4383 | ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLMUL; |
| 4384 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4385 | } |
| 4386 | |
| 4387 | static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLMUL_bit(const void *const hw) |
| 4388 | { |
| 4389 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4390 | ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLMUL; |
| 4391 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4392 | } |
| 4393 | |
| 4394 | static inline void hri_oscctrl_set_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) |
| 4395 | { |
| 4396 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4397 | ((Oscctrl *)hw)->DFLLSYNC.reg |= mask; |
| 4398 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4399 | } |
| 4400 | |
| 4401 | static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_get_DFLLSYNC_reg(const void *const hw, |
| 4402 | hri_oscctrl_dfllsync_reg_t mask) |
| 4403 | { |
| 4404 | uint8_t tmp; |
| 4405 | tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; |
| 4406 | tmp &= mask; |
| 4407 | return tmp; |
| 4408 | } |
| 4409 | |
| 4410 | static inline void hri_oscctrl_write_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t data) |
| 4411 | { |
| 4412 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4413 | ((Oscctrl *)hw)->DFLLSYNC.reg = data; |
| 4414 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4415 | } |
| 4416 | |
| 4417 | static inline void hri_oscctrl_clear_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) |
| 4418 | { |
| 4419 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4420 | ((Oscctrl *)hw)->DFLLSYNC.reg &= ~mask; |
| 4421 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4422 | } |
| 4423 | |
| 4424 | static inline void hri_oscctrl_toggle_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) |
| 4425 | { |
| 4426 | OSCCTRL_CRITICAL_SECTION_ENTER(); |
| 4427 | ((Oscctrl *)hw)->DFLLSYNC.reg ^= mask; |
| 4428 | OSCCTRL_CRITICAL_SECTION_LEAVE(); |
| 4429 | } |
| 4430 | |
| 4431 | static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_read_DFLLSYNC_reg(const void *const hw) |
| 4432 | { |
| 4433 | return ((Oscctrl *)hw)->DFLLSYNC.reg; |
| 4434 | } |
| 4435 | |
| 4436 | #ifdef __cplusplus |
| 4437 | } |
| 4438 | #endif |
| 4439 | |
| 4440 | #endif /* _HRI_OSCCTRL_E54_H_INCLUDED */ |
| 4441 | #endif /* _SAME54_OSCCTRL_COMPONENT_ */ |