Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM WDT |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_WDT_COMPONENT_ |
| 35 | #ifndef _HRI_WDT_E54_H_INCLUDED_ |
| 36 | #define _HRI_WDT_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_WDT_CRITICAL_SECTIONS) |
| 46 | #define WDT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define WDT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define WDT_CRITICAL_SECTION_ENTER() |
| 50 | #define WDT_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint32_t hri_wdt_syncbusy_reg_t; |
| 54 | typedef uint8_t hri_wdt_clear_reg_t; |
| 55 | typedef uint8_t hri_wdt_config_reg_t; |
| 56 | typedef uint8_t hri_wdt_ctrla_reg_t; |
| 57 | typedef uint8_t hri_wdt_ewctrl_reg_t; |
| 58 | typedef uint8_t hri_wdt_intenset_reg_t; |
| 59 | typedef uint8_t hri_wdt_intflag_reg_t; |
| 60 | |
| 61 | static inline void hri_wdt_wait_for_sync(const void *const hw, hri_wdt_syncbusy_reg_t reg) |
| 62 | { |
| 63 | while (((Wdt *)hw)->SYNCBUSY.reg & reg) { |
| 64 | }; |
| 65 | } |
| 66 | |
| 67 | static inline bool hri_wdt_is_syncing(const void *const hw, hri_wdt_syncbusy_reg_t reg) |
| 68 | { |
| 69 | return ((Wdt *)hw)->SYNCBUSY.reg & reg; |
| 70 | } |
| 71 | |
| 72 | static inline bool hri_wdt_get_INTFLAG_EW_bit(const void *const hw) |
| 73 | { |
| 74 | return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; |
| 75 | } |
| 76 | |
| 77 | static inline void hri_wdt_clear_INTFLAG_EW_bit(const void *const hw) |
| 78 | { |
| 79 | ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; |
| 80 | } |
| 81 | |
| 82 | static inline bool hri_wdt_get_interrupt_EW_bit(const void *const hw) |
| 83 | { |
| 84 | return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; |
| 85 | } |
| 86 | |
| 87 | static inline void hri_wdt_clear_interrupt_EW_bit(const void *const hw) |
| 88 | { |
| 89 | ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; |
| 90 | } |
| 91 | |
| 92 | static inline hri_wdt_intflag_reg_t hri_wdt_get_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) |
| 93 | { |
| 94 | uint8_t tmp; |
| 95 | tmp = ((Wdt *)hw)->INTFLAG.reg; |
| 96 | tmp &= mask; |
| 97 | return tmp; |
| 98 | } |
| 99 | |
| 100 | static inline hri_wdt_intflag_reg_t hri_wdt_read_INTFLAG_reg(const void *const hw) |
| 101 | { |
| 102 | return ((Wdt *)hw)->INTFLAG.reg; |
| 103 | } |
| 104 | |
| 105 | static inline void hri_wdt_clear_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) |
| 106 | { |
| 107 | ((Wdt *)hw)->INTFLAG.reg = mask; |
| 108 | } |
| 109 | |
| 110 | static inline void hri_wdt_set_INTEN_EW_bit(const void *const hw) |
| 111 | { |
| 112 | ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; |
| 113 | } |
| 114 | |
| 115 | static inline bool hri_wdt_get_INTEN_EW_bit(const void *const hw) |
| 116 | { |
| 117 | return (((Wdt *)hw)->INTENSET.reg & WDT_INTENSET_EW) >> WDT_INTENSET_EW_Pos; |
| 118 | } |
| 119 | |
| 120 | static inline void hri_wdt_write_INTEN_EW_bit(const void *const hw, bool value) |
| 121 | { |
| 122 | if (value == 0x0) { |
| 123 | ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; |
| 124 | } else { |
| 125 | ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; |
| 126 | } |
| 127 | } |
| 128 | |
| 129 | static inline void hri_wdt_clear_INTEN_EW_bit(const void *const hw) |
| 130 | { |
| 131 | ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; |
| 132 | } |
| 133 | |
| 134 | static inline void hri_wdt_set_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) |
| 135 | { |
| 136 | ((Wdt *)hw)->INTENSET.reg = mask; |
| 137 | } |
| 138 | |
| 139 | static inline hri_wdt_intenset_reg_t hri_wdt_get_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) |
| 140 | { |
| 141 | uint8_t tmp; |
| 142 | tmp = ((Wdt *)hw)->INTENSET.reg; |
| 143 | tmp &= mask; |
| 144 | return tmp; |
| 145 | } |
| 146 | |
| 147 | static inline hri_wdt_intenset_reg_t hri_wdt_read_INTEN_reg(const void *const hw) |
| 148 | { |
| 149 | return ((Wdt *)hw)->INTENSET.reg; |
| 150 | } |
| 151 | |
| 152 | static inline void hri_wdt_write_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t data) |
| 153 | { |
| 154 | ((Wdt *)hw)->INTENSET.reg = data; |
| 155 | ((Wdt *)hw)->INTENCLR.reg = ~data; |
| 156 | } |
| 157 | |
| 158 | static inline void hri_wdt_clear_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) |
| 159 | { |
| 160 | ((Wdt *)hw)->INTENCLR.reg = mask; |
| 161 | } |
| 162 | |
| 163 | static inline bool hri_wdt_get_SYNCBUSY_ENABLE_bit(const void *const hw) |
| 164 | { |
| 165 | return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ENABLE) >> WDT_SYNCBUSY_ENABLE_Pos; |
| 166 | } |
| 167 | |
| 168 | static inline bool hri_wdt_get_SYNCBUSY_WEN_bit(const void *const hw) |
| 169 | { |
| 170 | return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_WEN) >> WDT_SYNCBUSY_WEN_Pos; |
| 171 | } |
| 172 | |
| 173 | static inline bool hri_wdt_get_SYNCBUSY_ALWAYSON_bit(const void *const hw) |
| 174 | { |
| 175 | return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ALWAYSON) >> WDT_SYNCBUSY_ALWAYSON_Pos; |
| 176 | } |
| 177 | |
| 178 | static inline bool hri_wdt_get_SYNCBUSY_CLEAR_bit(const void *const hw) |
| 179 | { |
| 180 | return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_CLEAR) >> WDT_SYNCBUSY_CLEAR_Pos; |
| 181 | } |
| 182 | |
| 183 | static inline hri_wdt_syncbusy_reg_t hri_wdt_get_SYNCBUSY_reg(const void *const hw, hri_wdt_syncbusy_reg_t mask) |
| 184 | { |
| 185 | uint32_t tmp; |
| 186 | tmp = ((Wdt *)hw)->SYNCBUSY.reg; |
| 187 | tmp &= mask; |
| 188 | return tmp; |
| 189 | } |
| 190 | |
| 191 | static inline hri_wdt_syncbusy_reg_t hri_wdt_read_SYNCBUSY_reg(const void *const hw) |
| 192 | { |
| 193 | return ((Wdt *)hw)->SYNCBUSY.reg; |
| 194 | } |
| 195 | |
| 196 | static inline void hri_wdt_set_CTRLA_ENABLE_bit(const void *const hw) |
| 197 | { |
| 198 | WDT_CRITICAL_SECTION_ENTER(); |
| 199 | ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ENABLE; |
| 200 | hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); |
| 201 | WDT_CRITICAL_SECTION_LEAVE(); |
| 202 | } |
| 203 | |
| 204 | static inline bool hri_wdt_get_CTRLA_ENABLE_bit(const void *const hw) |
| 205 | { |
| 206 | uint8_t tmp; |
| 207 | hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); |
| 208 | tmp = ((Wdt *)hw)->CTRLA.reg; |
| 209 | tmp = (tmp & WDT_CTRLA_ENABLE) >> WDT_CTRLA_ENABLE_Pos; |
| 210 | return (bool)tmp; |
| 211 | } |
| 212 | |
| 213 | static inline void hri_wdt_write_CTRLA_ENABLE_bit(const void *const hw, bool value) |
| 214 | { |
| 215 | uint8_t tmp; |
| 216 | WDT_CRITICAL_SECTION_ENTER(); |
| 217 | tmp = ((Wdt *)hw)->CTRLA.reg; |
| 218 | tmp &= ~WDT_CTRLA_ENABLE; |
| 219 | tmp |= value << WDT_CTRLA_ENABLE_Pos; |
| 220 | ((Wdt *)hw)->CTRLA.reg = tmp; |
| 221 | hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); |
| 222 | WDT_CRITICAL_SECTION_LEAVE(); |
| 223 | } |
| 224 | |
| 225 | static inline void hri_wdt_clear_CTRLA_ENABLE_bit(const void *const hw) |
| 226 | { |
| 227 | WDT_CRITICAL_SECTION_ENTER(); |
| 228 | ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ENABLE; |
| 229 | hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); |
| 230 | WDT_CRITICAL_SECTION_LEAVE(); |
| 231 | } |
| 232 | |
| 233 | static inline void hri_wdt_toggle_CTRLA_ENABLE_bit(const void *const hw) |
| 234 | { |
| 235 | WDT_CRITICAL_SECTION_ENTER(); |
| 236 | ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ENABLE; |
| 237 | hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); |
| 238 | WDT_CRITICAL_SECTION_LEAVE(); |
| 239 | } |
| 240 | |
| 241 | static inline void hri_wdt_set_CTRLA_WEN_bit(const void *const hw) |
| 242 | { |
| 243 | WDT_CRITICAL_SECTION_ENTER(); |
| 244 | ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_WEN; |
| 245 | hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); |
| 246 | WDT_CRITICAL_SECTION_LEAVE(); |
| 247 | } |
| 248 | |
| 249 | static inline bool hri_wdt_get_CTRLA_WEN_bit(const void *const hw) |
| 250 | { |
| 251 | uint8_t tmp; |
| 252 | hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); |
| 253 | tmp = ((Wdt *)hw)->CTRLA.reg; |
| 254 | tmp = (tmp & WDT_CTRLA_WEN) >> WDT_CTRLA_WEN_Pos; |
| 255 | return (bool)tmp; |
| 256 | } |
| 257 | |
| 258 | static inline void hri_wdt_write_CTRLA_WEN_bit(const void *const hw, bool value) |
| 259 | { |
| 260 | uint8_t tmp; |
| 261 | WDT_CRITICAL_SECTION_ENTER(); |
| 262 | tmp = ((Wdt *)hw)->CTRLA.reg; |
| 263 | tmp &= ~WDT_CTRLA_WEN; |
| 264 | tmp |= value << WDT_CTRLA_WEN_Pos; |
| 265 | ((Wdt *)hw)->CTRLA.reg = tmp; |
| 266 | hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); |
| 267 | WDT_CRITICAL_SECTION_LEAVE(); |
| 268 | } |
| 269 | |
| 270 | static inline void hri_wdt_clear_CTRLA_WEN_bit(const void *const hw) |
| 271 | { |
| 272 | WDT_CRITICAL_SECTION_ENTER(); |
| 273 | ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_WEN; |
| 274 | hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); |
| 275 | WDT_CRITICAL_SECTION_LEAVE(); |
| 276 | } |
| 277 | |
| 278 | static inline void hri_wdt_toggle_CTRLA_WEN_bit(const void *const hw) |
| 279 | { |
| 280 | WDT_CRITICAL_SECTION_ENTER(); |
| 281 | ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_WEN; |
| 282 | hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); |
| 283 | WDT_CRITICAL_SECTION_LEAVE(); |
| 284 | } |
| 285 | |
| 286 | static inline void hri_wdt_set_CTRLA_ALWAYSON_bit(const void *const hw) |
| 287 | { |
| 288 | WDT_CRITICAL_SECTION_ENTER(); |
| 289 | ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ALWAYSON; |
| 290 | hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); |
| 291 | WDT_CRITICAL_SECTION_LEAVE(); |
| 292 | } |
| 293 | |
| 294 | static inline bool hri_wdt_get_CTRLA_ALWAYSON_bit(const void *const hw) |
| 295 | { |
| 296 | uint8_t tmp; |
| 297 | hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); |
| 298 | tmp = ((Wdt *)hw)->CTRLA.reg; |
| 299 | tmp = (tmp & WDT_CTRLA_ALWAYSON) >> WDT_CTRLA_ALWAYSON_Pos; |
| 300 | return (bool)tmp; |
| 301 | } |
| 302 | |
| 303 | static inline void hri_wdt_write_CTRLA_ALWAYSON_bit(const void *const hw, bool value) |
| 304 | { |
| 305 | uint8_t tmp; |
| 306 | WDT_CRITICAL_SECTION_ENTER(); |
| 307 | tmp = ((Wdt *)hw)->CTRLA.reg; |
| 308 | tmp &= ~WDT_CTRLA_ALWAYSON; |
| 309 | tmp |= value << WDT_CTRLA_ALWAYSON_Pos; |
| 310 | ((Wdt *)hw)->CTRLA.reg = tmp; |
| 311 | hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); |
| 312 | WDT_CRITICAL_SECTION_LEAVE(); |
| 313 | } |
| 314 | |
| 315 | static inline void hri_wdt_clear_CTRLA_ALWAYSON_bit(const void *const hw) |
| 316 | { |
| 317 | WDT_CRITICAL_SECTION_ENTER(); |
| 318 | ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ALWAYSON; |
| 319 | hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); |
| 320 | WDT_CRITICAL_SECTION_LEAVE(); |
| 321 | } |
| 322 | |
| 323 | static inline void hri_wdt_toggle_CTRLA_ALWAYSON_bit(const void *const hw) |
| 324 | { |
| 325 | WDT_CRITICAL_SECTION_ENTER(); |
| 326 | ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ALWAYSON; |
| 327 | hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); |
| 328 | WDT_CRITICAL_SECTION_LEAVE(); |
| 329 | } |
| 330 | |
| 331 | static inline void hri_wdt_set_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) |
| 332 | { |
| 333 | WDT_CRITICAL_SECTION_ENTER(); |
| 334 | ((Wdt *)hw)->CTRLA.reg |= mask; |
| 335 | hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); |
| 336 | WDT_CRITICAL_SECTION_LEAVE(); |
| 337 | } |
| 338 | |
| 339 | static inline hri_wdt_ctrla_reg_t hri_wdt_get_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) |
| 340 | { |
| 341 | uint8_t tmp; |
| 342 | hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); |
| 343 | tmp = ((Wdt *)hw)->CTRLA.reg; |
| 344 | tmp &= mask; |
| 345 | return tmp; |
| 346 | } |
| 347 | |
| 348 | static inline void hri_wdt_write_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t data) |
| 349 | { |
| 350 | WDT_CRITICAL_SECTION_ENTER(); |
| 351 | ((Wdt *)hw)->CTRLA.reg = data; |
| 352 | hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); |
| 353 | WDT_CRITICAL_SECTION_LEAVE(); |
| 354 | } |
| 355 | |
| 356 | static inline void hri_wdt_clear_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) |
| 357 | { |
| 358 | WDT_CRITICAL_SECTION_ENTER(); |
| 359 | ((Wdt *)hw)->CTRLA.reg &= ~mask; |
| 360 | hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); |
| 361 | WDT_CRITICAL_SECTION_LEAVE(); |
| 362 | } |
| 363 | |
| 364 | static inline void hri_wdt_toggle_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) |
| 365 | { |
| 366 | WDT_CRITICAL_SECTION_ENTER(); |
| 367 | ((Wdt *)hw)->CTRLA.reg ^= mask; |
| 368 | hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); |
| 369 | WDT_CRITICAL_SECTION_LEAVE(); |
| 370 | } |
| 371 | |
| 372 | static inline hri_wdt_ctrla_reg_t hri_wdt_read_CTRLA_reg(const void *const hw) |
| 373 | { |
| 374 | hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); |
| 375 | return ((Wdt *)hw)->CTRLA.reg; |
| 376 | } |
| 377 | |
| 378 | static inline void hri_wdt_set_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) |
| 379 | { |
| 380 | WDT_CRITICAL_SECTION_ENTER(); |
| 381 | ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_PER(mask); |
| 382 | WDT_CRITICAL_SECTION_LEAVE(); |
| 383 | } |
| 384 | |
| 385 | static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) |
| 386 | { |
| 387 | uint8_t tmp; |
| 388 | tmp = ((Wdt *)hw)->CONFIG.reg; |
| 389 | tmp = (tmp & WDT_CONFIG_PER(mask)) >> WDT_CONFIG_PER_Pos; |
| 390 | return tmp; |
| 391 | } |
| 392 | |
| 393 | static inline void hri_wdt_write_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t data) |
| 394 | { |
| 395 | uint8_t tmp; |
| 396 | WDT_CRITICAL_SECTION_ENTER(); |
| 397 | tmp = ((Wdt *)hw)->CONFIG.reg; |
| 398 | tmp &= ~WDT_CONFIG_PER_Msk; |
| 399 | tmp |= WDT_CONFIG_PER(data); |
| 400 | ((Wdt *)hw)->CONFIG.reg = tmp; |
| 401 | WDT_CRITICAL_SECTION_LEAVE(); |
| 402 | } |
| 403 | |
| 404 | static inline void hri_wdt_clear_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) |
| 405 | { |
| 406 | WDT_CRITICAL_SECTION_ENTER(); |
| 407 | ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_PER(mask); |
| 408 | WDT_CRITICAL_SECTION_LEAVE(); |
| 409 | } |
| 410 | |
| 411 | static inline void hri_wdt_toggle_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) |
| 412 | { |
| 413 | WDT_CRITICAL_SECTION_ENTER(); |
| 414 | ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_PER(mask); |
| 415 | WDT_CRITICAL_SECTION_LEAVE(); |
| 416 | } |
| 417 | |
| 418 | static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_PER_bf(const void *const hw) |
| 419 | { |
| 420 | uint8_t tmp; |
| 421 | tmp = ((Wdt *)hw)->CONFIG.reg; |
| 422 | tmp = (tmp & WDT_CONFIG_PER_Msk) >> WDT_CONFIG_PER_Pos; |
| 423 | return tmp; |
| 424 | } |
| 425 | |
| 426 | static inline void hri_wdt_set_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) |
| 427 | { |
| 428 | WDT_CRITICAL_SECTION_ENTER(); |
| 429 | ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_WINDOW(mask); |
| 430 | WDT_CRITICAL_SECTION_LEAVE(); |
| 431 | } |
| 432 | |
| 433 | static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) |
| 434 | { |
| 435 | uint8_t tmp; |
| 436 | tmp = ((Wdt *)hw)->CONFIG.reg; |
| 437 | tmp = (tmp & WDT_CONFIG_WINDOW(mask)) >> WDT_CONFIG_WINDOW_Pos; |
| 438 | return tmp; |
| 439 | } |
| 440 | |
| 441 | static inline void hri_wdt_write_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t data) |
| 442 | { |
| 443 | uint8_t tmp; |
| 444 | WDT_CRITICAL_SECTION_ENTER(); |
| 445 | tmp = ((Wdt *)hw)->CONFIG.reg; |
| 446 | tmp &= ~WDT_CONFIG_WINDOW_Msk; |
| 447 | tmp |= WDT_CONFIG_WINDOW(data); |
| 448 | ((Wdt *)hw)->CONFIG.reg = tmp; |
| 449 | WDT_CRITICAL_SECTION_LEAVE(); |
| 450 | } |
| 451 | |
| 452 | static inline void hri_wdt_clear_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) |
| 453 | { |
| 454 | WDT_CRITICAL_SECTION_ENTER(); |
| 455 | ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_WINDOW(mask); |
| 456 | WDT_CRITICAL_SECTION_LEAVE(); |
| 457 | } |
| 458 | |
| 459 | static inline void hri_wdt_toggle_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) |
| 460 | { |
| 461 | WDT_CRITICAL_SECTION_ENTER(); |
| 462 | ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_WINDOW(mask); |
| 463 | WDT_CRITICAL_SECTION_LEAVE(); |
| 464 | } |
| 465 | |
| 466 | static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_WINDOW_bf(const void *const hw) |
| 467 | { |
| 468 | uint8_t tmp; |
| 469 | tmp = ((Wdt *)hw)->CONFIG.reg; |
| 470 | tmp = (tmp & WDT_CONFIG_WINDOW_Msk) >> WDT_CONFIG_WINDOW_Pos; |
| 471 | return tmp; |
| 472 | } |
| 473 | |
| 474 | static inline void hri_wdt_set_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) |
| 475 | { |
| 476 | WDT_CRITICAL_SECTION_ENTER(); |
| 477 | ((Wdt *)hw)->CONFIG.reg |= mask; |
| 478 | WDT_CRITICAL_SECTION_LEAVE(); |
| 479 | } |
| 480 | |
| 481 | static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) |
| 482 | { |
| 483 | uint8_t tmp; |
| 484 | tmp = ((Wdt *)hw)->CONFIG.reg; |
| 485 | tmp &= mask; |
| 486 | return tmp; |
| 487 | } |
| 488 | |
| 489 | static inline void hri_wdt_write_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t data) |
| 490 | { |
| 491 | WDT_CRITICAL_SECTION_ENTER(); |
| 492 | ((Wdt *)hw)->CONFIG.reg = data; |
| 493 | WDT_CRITICAL_SECTION_LEAVE(); |
| 494 | } |
| 495 | |
| 496 | static inline void hri_wdt_clear_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) |
| 497 | { |
| 498 | WDT_CRITICAL_SECTION_ENTER(); |
| 499 | ((Wdt *)hw)->CONFIG.reg &= ~mask; |
| 500 | WDT_CRITICAL_SECTION_LEAVE(); |
| 501 | } |
| 502 | |
| 503 | static inline void hri_wdt_toggle_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) |
| 504 | { |
| 505 | WDT_CRITICAL_SECTION_ENTER(); |
| 506 | ((Wdt *)hw)->CONFIG.reg ^= mask; |
| 507 | WDT_CRITICAL_SECTION_LEAVE(); |
| 508 | } |
| 509 | |
| 510 | static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_reg(const void *const hw) |
| 511 | { |
| 512 | return ((Wdt *)hw)->CONFIG.reg; |
| 513 | } |
| 514 | |
| 515 | static inline void hri_wdt_set_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) |
| 516 | { |
| 517 | WDT_CRITICAL_SECTION_ENTER(); |
| 518 | ((Wdt *)hw)->EWCTRL.reg |= WDT_EWCTRL_EWOFFSET(mask); |
| 519 | WDT_CRITICAL_SECTION_LEAVE(); |
| 520 | } |
| 521 | |
| 522 | static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) |
| 523 | { |
| 524 | uint8_t tmp; |
| 525 | tmp = ((Wdt *)hw)->EWCTRL.reg; |
| 526 | tmp = (tmp & WDT_EWCTRL_EWOFFSET(mask)) >> WDT_EWCTRL_EWOFFSET_Pos; |
| 527 | return tmp; |
| 528 | } |
| 529 | |
| 530 | static inline void hri_wdt_write_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t data) |
| 531 | { |
| 532 | uint8_t tmp; |
| 533 | WDT_CRITICAL_SECTION_ENTER(); |
| 534 | tmp = ((Wdt *)hw)->EWCTRL.reg; |
| 535 | tmp &= ~WDT_EWCTRL_EWOFFSET_Msk; |
| 536 | tmp |= WDT_EWCTRL_EWOFFSET(data); |
| 537 | ((Wdt *)hw)->EWCTRL.reg = tmp; |
| 538 | WDT_CRITICAL_SECTION_LEAVE(); |
| 539 | } |
| 540 | |
| 541 | static inline void hri_wdt_clear_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) |
| 542 | { |
| 543 | WDT_CRITICAL_SECTION_ENTER(); |
| 544 | ((Wdt *)hw)->EWCTRL.reg &= ~WDT_EWCTRL_EWOFFSET(mask); |
| 545 | WDT_CRITICAL_SECTION_LEAVE(); |
| 546 | } |
| 547 | |
| 548 | static inline void hri_wdt_toggle_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) |
| 549 | { |
| 550 | WDT_CRITICAL_SECTION_ENTER(); |
| 551 | ((Wdt *)hw)->EWCTRL.reg ^= WDT_EWCTRL_EWOFFSET(mask); |
| 552 | WDT_CRITICAL_SECTION_LEAVE(); |
| 553 | } |
| 554 | |
| 555 | static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_EWOFFSET_bf(const void *const hw) |
| 556 | { |
| 557 | uint8_t tmp; |
| 558 | tmp = ((Wdt *)hw)->EWCTRL.reg; |
| 559 | tmp = (tmp & WDT_EWCTRL_EWOFFSET_Msk) >> WDT_EWCTRL_EWOFFSET_Pos; |
| 560 | return tmp; |
| 561 | } |
| 562 | |
| 563 | static inline void hri_wdt_set_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) |
| 564 | { |
| 565 | WDT_CRITICAL_SECTION_ENTER(); |
| 566 | ((Wdt *)hw)->EWCTRL.reg |= mask; |
| 567 | WDT_CRITICAL_SECTION_LEAVE(); |
| 568 | } |
| 569 | |
| 570 | static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) |
| 571 | { |
| 572 | uint8_t tmp; |
| 573 | tmp = ((Wdt *)hw)->EWCTRL.reg; |
| 574 | tmp &= mask; |
| 575 | return tmp; |
| 576 | } |
| 577 | |
| 578 | static inline void hri_wdt_write_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t data) |
| 579 | { |
| 580 | WDT_CRITICAL_SECTION_ENTER(); |
| 581 | ((Wdt *)hw)->EWCTRL.reg = data; |
| 582 | WDT_CRITICAL_SECTION_LEAVE(); |
| 583 | } |
| 584 | |
| 585 | static inline void hri_wdt_clear_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) |
| 586 | { |
| 587 | WDT_CRITICAL_SECTION_ENTER(); |
| 588 | ((Wdt *)hw)->EWCTRL.reg &= ~mask; |
| 589 | WDT_CRITICAL_SECTION_LEAVE(); |
| 590 | } |
| 591 | |
| 592 | static inline void hri_wdt_toggle_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) |
| 593 | { |
| 594 | WDT_CRITICAL_SECTION_ENTER(); |
| 595 | ((Wdt *)hw)->EWCTRL.reg ^= mask; |
| 596 | WDT_CRITICAL_SECTION_LEAVE(); |
| 597 | } |
| 598 | |
| 599 | static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_reg(const void *const hw) |
| 600 | { |
| 601 | return ((Wdt *)hw)->EWCTRL.reg; |
| 602 | } |
| 603 | |
| 604 | static inline void hri_wdt_write_CLEAR_reg(const void *const hw, hri_wdt_clear_reg_t data) |
| 605 | { |
| 606 | WDT_CRITICAL_SECTION_ENTER(); |
| 607 | ((Wdt *)hw)->CLEAR.reg = data; |
| 608 | hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_CLEAR); |
| 609 | WDT_CRITICAL_SECTION_LEAVE(); |
| 610 | } |
| 611 | |
| 612 | #ifdef __cplusplus |
| 613 | } |
| 614 | #endif |
| 615 | |
| 616 | #endif /* _HRI_WDT_E54_H_INCLUDED */ |
| 617 | #endif /* _SAME54_WDT_COMPONENT_ */ |