Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM PM |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_PM_COMPONENT_ |
| 35 | #ifndef _HRI_PM_E54_H_INCLUDED_ |
| 36 | #define _HRI_PM_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_PM_CRITICAL_SECTIONS) |
| 46 | #define PM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define PM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define PM_CRITICAL_SECTION_ENTER() |
| 50 | #define PM_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint8_t hri_pm_bkupcfg_reg_t; |
| 54 | typedef uint8_t hri_pm_ctrla_reg_t; |
| 55 | typedef uint8_t hri_pm_hibcfg_reg_t; |
| 56 | typedef uint8_t hri_pm_intenset_reg_t; |
| 57 | typedef uint8_t hri_pm_intflag_reg_t; |
| 58 | typedef uint8_t hri_pm_pwsakdly_reg_t; |
| 59 | typedef uint8_t hri_pm_sleepcfg_reg_t; |
| 60 | typedef uint8_t hri_pm_stdbycfg_reg_t; |
| 61 | |
| 62 | static inline bool hri_pm_get_INTFLAG_SLEEPRDY_bit(const void *const hw) |
| 63 | { |
| 64 | return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_SLEEPRDY) >> PM_INTFLAG_SLEEPRDY_Pos; |
| 65 | } |
| 66 | |
| 67 | static inline void hri_pm_clear_INTFLAG_SLEEPRDY_bit(const void *const hw) |
| 68 | { |
| 69 | ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_SLEEPRDY; |
| 70 | } |
| 71 | |
| 72 | static inline bool hri_pm_get_interrupt_SLEEPRDY_bit(const void *const hw) |
| 73 | { |
| 74 | return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_SLEEPRDY) >> PM_INTFLAG_SLEEPRDY_Pos; |
| 75 | } |
| 76 | |
| 77 | static inline void hri_pm_clear_interrupt_SLEEPRDY_bit(const void *const hw) |
| 78 | { |
| 79 | ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_SLEEPRDY; |
| 80 | } |
| 81 | |
| 82 | static inline hri_pm_intflag_reg_t hri_pm_get_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) |
| 83 | { |
| 84 | uint8_t tmp; |
| 85 | tmp = ((Pm *)hw)->INTFLAG.reg; |
| 86 | tmp &= mask; |
| 87 | return tmp; |
| 88 | } |
| 89 | |
| 90 | static inline hri_pm_intflag_reg_t hri_pm_read_INTFLAG_reg(const void *const hw) |
| 91 | { |
| 92 | return ((Pm *)hw)->INTFLAG.reg; |
| 93 | } |
| 94 | |
| 95 | static inline void hri_pm_clear_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) |
| 96 | { |
| 97 | ((Pm *)hw)->INTFLAG.reg = mask; |
| 98 | } |
| 99 | |
| 100 | static inline void hri_pm_set_INTEN_SLEEPRDY_bit(const void *const hw) |
| 101 | { |
| 102 | ((Pm *)hw)->INTENSET.reg = PM_INTENSET_SLEEPRDY; |
| 103 | } |
| 104 | |
| 105 | static inline bool hri_pm_get_INTEN_SLEEPRDY_bit(const void *const hw) |
| 106 | { |
| 107 | return (((Pm *)hw)->INTENSET.reg & PM_INTENSET_SLEEPRDY) >> PM_INTENSET_SLEEPRDY_Pos; |
| 108 | } |
| 109 | |
| 110 | static inline void hri_pm_write_INTEN_SLEEPRDY_bit(const void *const hw, bool value) |
| 111 | { |
| 112 | if (value == 0x0) { |
| 113 | ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_SLEEPRDY; |
| 114 | } else { |
| 115 | ((Pm *)hw)->INTENSET.reg = PM_INTENSET_SLEEPRDY; |
| 116 | } |
| 117 | } |
| 118 | |
| 119 | static inline void hri_pm_clear_INTEN_SLEEPRDY_bit(const void *const hw) |
| 120 | { |
| 121 | ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_SLEEPRDY; |
| 122 | } |
| 123 | |
| 124 | static inline void hri_pm_set_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) |
| 125 | { |
| 126 | ((Pm *)hw)->INTENSET.reg = mask; |
| 127 | } |
| 128 | |
| 129 | static inline hri_pm_intenset_reg_t hri_pm_get_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) |
| 130 | { |
| 131 | uint8_t tmp; |
| 132 | tmp = ((Pm *)hw)->INTENSET.reg; |
| 133 | tmp &= mask; |
| 134 | return tmp; |
| 135 | } |
| 136 | |
| 137 | static inline hri_pm_intenset_reg_t hri_pm_read_INTEN_reg(const void *const hw) |
| 138 | { |
| 139 | return ((Pm *)hw)->INTENSET.reg; |
| 140 | } |
| 141 | |
| 142 | static inline void hri_pm_write_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t data) |
| 143 | { |
| 144 | ((Pm *)hw)->INTENSET.reg = data; |
| 145 | ((Pm *)hw)->INTENCLR.reg = ~data; |
| 146 | } |
| 147 | |
| 148 | static inline void hri_pm_clear_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) |
| 149 | { |
| 150 | ((Pm *)hw)->INTENCLR.reg = mask; |
| 151 | } |
| 152 | |
| 153 | static inline void hri_pm_set_CTRLA_IORET_bit(const void *const hw) |
| 154 | { |
| 155 | PM_CRITICAL_SECTION_ENTER(); |
| 156 | ((Pm *)hw)->CTRLA.reg |= PM_CTRLA_IORET; |
| 157 | PM_CRITICAL_SECTION_LEAVE(); |
| 158 | } |
| 159 | |
| 160 | static inline bool hri_pm_get_CTRLA_IORET_bit(const void *const hw) |
| 161 | { |
| 162 | uint8_t tmp; |
| 163 | tmp = ((Pm *)hw)->CTRLA.reg; |
| 164 | tmp = (tmp & PM_CTRLA_IORET) >> PM_CTRLA_IORET_Pos; |
| 165 | return (bool)tmp; |
| 166 | } |
| 167 | |
| 168 | static inline void hri_pm_write_CTRLA_IORET_bit(const void *const hw, bool value) |
| 169 | { |
| 170 | uint8_t tmp; |
| 171 | PM_CRITICAL_SECTION_ENTER(); |
| 172 | tmp = ((Pm *)hw)->CTRLA.reg; |
| 173 | tmp &= ~PM_CTRLA_IORET; |
| 174 | tmp |= value << PM_CTRLA_IORET_Pos; |
| 175 | ((Pm *)hw)->CTRLA.reg = tmp; |
| 176 | PM_CRITICAL_SECTION_LEAVE(); |
| 177 | } |
| 178 | |
| 179 | static inline void hri_pm_clear_CTRLA_IORET_bit(const void *const hw) |
| 180 | { |
| 181 | PM_CRITICAL_SECTION_ENTER(); |
| 182 | ((Pm *)hw)->CTRLA.reg &= ~PM_CTRLA_IORET; |
| 183 | PM_CRITICAL_SECTION_LEAVE(); |
| 184 | } |
| 185 | |
| 186 | static inline void hri_pm_toggle_CTRLA_IORET_bit(const void *const hw) |
| 187 | { |
| 188 | PM_CRITICAL_SECTION_ENTER(); |
| 189 | ((Pm *)hw)->CTRLA.reg ^= PM_CTRLA_IORET; |
| 190 | PM_CRITICAL_SECTION_LEAVE(); |
| 191 | } |
| 192 | |
| 193 | static inline void hri_pm_set_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) |
| 194 | { |
| 195 | PM_CRITICAL_SECTION_ENTER(); |
| 196 | ((Pm *)hw)->CTRLA.reg |= mask; |
| 197 | PM_CRITICAL_SECTION_LEAVE(); |
| 198 | } |
| 199 | |
| 200 | static inline hri_pm_ctrla_reg_t hri_pm_get_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) |
| 201 | { |
| 202 | uint8_t tmp; |
| 203 | tmp = ((Pm *)hw)->CTRLA.reg; |
| 204 | tmp &= mask; |
| 205 | return tmp; |
| 206 | } |
| 207 | |
| 208 | static inline void hri_pm_write_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t data) |
| 209 | { |
| 210 | PM_CRITICAL_SECTION_ENTER(); |
| 211 | ((Pm *)hw)->CTRLA.reg = data; |
| 212 | PM_CRITICAL_SECTION_LEAVE(); |
| 213 | } |
| 214 | |
| 215 | static inline void hri_pm_clear_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) |
| 216 | { |
| 217 | PM_CRITICAL_SECTION_ENTER(); |
| 218 | ((Pm *)hw)->CTRLA.reg &= ~mask; |
| 219 | PM_CRITICAL_SECTION_LEAVE(); |
| 220 | } |
| 221 | |
| 222 | static inline void hri_pm_toggle_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) |
| 223 | { |
| 224 | PM_CRITICAL_SECTION_ENTER(); |
| 225 | ((Pm *)hw)->CTRLA.reg ^= mask; |
| 226 | PM_CRITICAL_SECTION_LEAVE(); |
| 227 | } |
| 228 | |
| 229 | static inline hri_pm_ctrla_reg_t hri_pm_read_CTRLA_reg(const void *const hw) |
| 230 | { |
| 231 | return ((Pm *)hw)->CTRLA.reg; |
| 232 | } |
| 233 | |
| 234 | static inline void hri_pm_set_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) |
| 235 | { |
| 236 | PM_CRITICAL_SECTION_ENTER(); |
| 237 | ((Pm *)hw)->SLEEPCFG.reg |= PM_SLEEPCFG_SLEEPMODE(mask); |
| 238 | PM_CRITICAL_SECTION_LEAVE(); |
| 239 | } |
| 240 | |
| 241 | static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) |
| 242 | { |
| 243 | uint8_t tmp; |
| 244 | tmp = ((Pm *)hw)->SLEEPCFG.reg; |
| 245 | tmp = (tmp & PM_SLEEPCFG_SLEEPMODE(mask)) >> PM_SLEEPCFG_SLEEPMODE_Pos; |
| 246 | return tmp; |
| 247 | } |
| 248 | |
| 249 | static inline void hri_pm_write_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t data) |
| 250 | { |
| 251 | uint8_t tmp; |
| 252 | PM_CRITICAL_SECTION_ENTER(); |
| 253 | tmp = ((Pm *)hw)->SLEEPCFG.reg; |
| 254 | tmp &= ~PM_SLEEPCFG_SLEEPMODE_Msk; |
| 255 | tmp |= PM_SLEEPCFG_SLEEPMODE(data); |
| 256 | ((Pm *)hw)->SLEEPCFG.reg = tmp; |
| 257 | PM_CRITICAL_SECTION_LEAVE(); |
| 258 | } |
| 259 | |
| 260 | static inline void hri_pm_clear_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) |
| 261 | { |
| 262 | PM_CRITICAL_SECTION_ENTER(); |
| 263 | ((Pm *)hw)->SLEEPCFG.reg &= ~PM_SLEEPCFG_SLEEPMODE(mask); |
| 264 | PM_CRITICAL_SECTION_LEAVE(); |
| 265 | } |
| 266 | |
| 267 | static inline void hri_pm_toggle_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) |
| 268 | { |
| 269 | PM_CRITICAL_SECTION_ENTER(); |
| 270 | ((Pm *)hw)->SLEEPCFG.reg ^= PM_SLEEPCFG_SLEEPMODE(mask); |
| 271 | PM_CRITICAL_SECTION_LEAVE(); |
| 272 | } |
| 273 | |
| 274 | static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_SLEEPMODE_bf(const void *const hw) |
| 275 | { |
| 276 | uint8_t tmp; |
| 277 | tmp = ((Pm *)hw)->SLEEPCFG.reg; |
| 278 | tmp = (tmp & PM_SLEEPCFG_SLEEPMODE_Msk) >> PM_SLEEPCFG_SLEEPMODE_Pos; |
| 279 | return tmp; |
| 280 | } |
| 281 | |
| 282 | static inline void hri_pm_set_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) |
| 283 | { |
| 284 | PM_CRITICAL_SECTION_ENTER(); |
| 285 | ((Pm *)hw)->SLEEPCFG.reg |= mask; |
| 286 | PM_CRITICAL_SECTION_LEAVE(); |
| 287 | } |
| 288 | |
| 289 | static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) |
| 290 | { |
| 291 | uint8_t tmp; |
| 292 | tmp = ((Pm *)hw)->SLEEPCFG.reg; |
| 293 | tmp &= mask; |
| 294 | return tmp; |
| 295 | } |
| 296 | |
| 297 | static inline void hri_pm_write_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t data) |
| 298 | { |
| 299 | PM_CRITICAL_SECTION_ENTER(); |
| 300 | ((Pm *)hw)->SLEEPCFG.reg = data; |
| 301 | PM_CRITICAL_SECTION_LEAVE(); |
| 302 | } |
| 303 | |
| 304 | static inline void hri_pm_clear_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) |
| 305 | { |
| 306 | PM_CRITICAL_SECTION_ENTER(); |
| 307 | ((Pm *)hw)->SLEEPCFG.reg &= ~mask; |
| 308 | PM_CRITICAL_SECTION_LEAVE(); |
| 309 | } |
| 310 | |
| 311 | static inline void hri_pm_toggle_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) |
| 312 | { |
| 313 | PM_CRITICAL_SECTION_ENTER(); |
| 314 | ((Pm *)hw)->SLEEPCFG.reg ^= mask; |
| 315 | PM_CRITICAL_SECTION_LEAVE(); |
| 316 | } |
| 317 | |
| 318 | static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_reg(const void *const hw) |
| 319 | { |
| 320 | return ((Pm *)hw)->SLEEPCFG.reg; |
| 321 | } |
| 322 | |
| 323 | static inline void hri_pm_set_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) |
| 324 | { |
| 325 | PM_CRITICAL_SECTION_ENTER(); |
| 326 | ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_RAMCFG(mask); |
| 327 | PM_CRITICAL_SECTION_LEAVE(); |
| 328 | } |
| 329 | |
| 330 | static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) |
| 331 | { |
| 332 | uint8_t tmp; |
| 333 | tmp = ((Pm *)hw)->STDBYCFG.reg; |
| 334 | tmp = (tmp & PM_STDBYCFG_RAMCFG(mask)) >> PM_STDBYCFG_RAMCFG_Pos; |
| 335 | return tmp; |
| 336 | } |
| 337 | |
| 338 | static inline void hri_pm_write_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) |
| 339 | { |
| 340 | uint8_t tmp; |
| 341 | PM_CRITICAL_SECTION_ENTER(); |
| 342 | tmp = ((Pm *)hw)->STDBYCFG.reg; |
| 343 | tmp &= ~PM_STDBYCFG_RAMCFG_Msk; |
| 344 | tmp |= PM_STDBYCFG_RAMCFG(data); |
| 345 | ((Pm *)hw)->STDBYCFG.reg = tmp; |
| 346 | PM_CRITICAL_SECTION_LEAVE(); |
| 347 | } |
| 348 | |
| 349 | static inline void hri_pm_clear_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) |
| 350 | { |
| 351 | PM_CRITICAL_SECTION_ENTER(); |
| 352 | ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_RAMCFG(mask); |
| 353 | PM_CRITICAL_SECTION_LEAVE(); |
| 354 | } |
| 355 | |
| 356 | static inline void hri_pm_toggle_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) |
| 357 | { |
| 358 | PM_CRITICAL_SECTION_ENTER(); |
| 359 | ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_RAMCFG(mask); |
| 360 | PM_CRITICAL_SECTION_LEAVE(); |
| 361 | } |
| 362 | |
| 363 | static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_RAMCFG_bf(const void *const hw) |
| 364 | { |
| 365 | uint8_t tmp; |
| 366 | tmp = ((Pm *)hw)->STDBYCFG.reg; |
| 367 | tmp = (tmp & PM_STDBYCFG_RAMCFG_Msk) >> PM_STDBYCFG_RAMCFG_Pos; |
| 368 | return tmp; |
| 369 | } |
| 370 | |
| 371 | static inline void hri_pm_set_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) |
| 372 | { |
| 373 | PM_CRITICAL_SECTION_ENTER(); |
| 374 | ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_FASTWKUP(mask); |
| 375 | PM_CRITICAL_SECTION_LEAVE(); |
| 376 | } |
| 377 | |
| 378 | static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) |
| 379 | { |
| 380 | uint8_t tmp; |
| 381 | tmp = ((Pm *)hw)->STDBYCFG.reg; |
| 382 | tmp = (tmp & PM_STDBYCFG_FASTWKUP(mask)) >> PM_STDBYCFG_FASTWKUP_Pos; |
| 383 | return tmp; |
| 384 | } |
| 385 | |
| 386 | static inline void hri_pm_write_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) |
| 387 | { |
| 388 | uint8_t tmp; |
| 389 | PM_CRITICAL_SECTION_ENTER(); |
| 390 | tmp = ((Pm *)hw)->STDBYCFG.reg; |
| 391 | tmp &= ~PM_STDBYCFG_FASTWKUP_Msk; |
| 392 | tmp |= PM_STDBYCFG_FASTWKUP(data); |
| 393 | ((Pm *)hw)->STDBYCFG.reg = tmp; |
| 394 | PM_CRITICAL_SECTION_LEAVE(); |
| 395 | } |
| 396 | |
| 397 | static inline void hri_pm_clear_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) |
| 398 | { |
| 399 | PM_CRITICAL_SECTION_ENTER(); |
| 400 | ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_FASTWKUP(mask); |
| 401 | PM_CRITICAL_SECTION_LEAVE(); |
| 402 | } |
| 403 | |
| 404 | static inline void hri_pm_toggle_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) |
| 405 | { |
| 406 | PM_CRITICAL_SECTION_ENTER(); |
| 407 | ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_FASTWKUP(mask); |
| 408 | PM_CRITICAL_SECTION_LEAVE(); |
| 409 | } |
| 410 | |
| 411 | static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_FASTWKUP_bf(const void *const hw) |
| 412 | { |
| 413 | uint8_t tmp; |
| 414 | tmp = ((Pm *)hw)->STDBYCFG.reg; |
| 415 | tmp = (tmp & PM_STDBYCFG_FASTWKUP_Msk) >> PM_STDBYCFG_FASTWKUP_Pos; |
| 416 | return tmp; |
| 417 | } |
| 418 | |
| 419 | static inline void hri_pm_set_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) |
| 420 | { |
| 421 | PM_CRITICAL_SECTION_ENTER(); |
| 422 | ((Pm *)hw)->STDBYCFG.reg |= mask; |
| 423 | PM_CRITICAL_SECTION_LEAVE(); |
| 424 | } |
| 425 | |
| 426 | static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) |
| 427 | { |
| 428 | uint8_t tmp; |
| 429 | tmp = ((Pm *)hw)->STDBYCFG.reg; |
| 430 | tmp &= mask; |
| 431 | return tmp; |
| 432 | } |
| 433 | |
| 434 | static inline void hri_pm_write_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t data) |
| 435 | { |
| 436 | PM_CRITICAL_SECTION_ENTER(); |
| 437 | ((Pm *)hw)->STDBYCFG.reg = data; |
| 438 | PM_CRITICAL_SECTION_LEAVE(); |
| 439 | } |
| 440 | |
| 441 | static inline void hri_pm_clear_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) |
| 442 | { |
| 443 | PM_CRITICAL_SECTION_ENTER(); |
| 444 | ((Pm *)hw)->STDBYCFG.reg &= ~mask; |
| 445 | PM_CRITICAL_SECTION_LEAVE(); |
| 446 | } |
| 447 | |
| 448 | static inline void hri_pm_toggle_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) |
| 449 | { |
| 450 | PM_CRITICAL_SECTION_ENTER(); |
| 451 | ((Pm *)hw)->STDBYCFG.reg ^= mask; |
| 452 | PM_CRITICAL_SECTION_LEAVE(); |
| 453 | } |
| 454 | |
| 455 | static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_reg(const void *const hw) |
| 456 | { |
| 457 | return ((Pm *)hw)->STDBYCFG.reg; |
| 458 | } |
| 459 | |
| 460 | static inline void hri_pm_set_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) |
| 461 | { |
| 462 | PM_CRITICAL_SECTION_ENTER(); |
| 463 | ((Pm *)hw)->HIBCFG.reg |= PM_HIBCFG_RAMCFG(mask); |
| 464 | PM_CRITICAL_SECTION_LEAVE(); |
| 465 | } |
| 466 | |
| 467 | static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) |
| 468 | { |
| 469 | uint8_t tmp; |
| 470 | tmp = ((Pm *)hw)->HIBCFG.reg; |
| 471 | tmp = (tmp & PM_HIBCFG_RAMCFG(mask)) >> PM_HIBCFG_RAMCFG_Pos; |
| 472 | return tmp; |
| 473 | } |
| 474 | |
| 475 | static inline void hri_pm_write_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t data) |
| 476 | { |
| 477 | uint8_t tmp; |
| 478 | PM_CRITICAL_SECTION_ENTER(); |
| 479 | tmp = ((Pm *)hw)->HIBCFG.reg; |
| 480 | tmp &= ~PM_HIBCFG_RAMCFG_Msk; |
| 481 | tmp |= PM_HIBCFG_RAMCFG(data); |
| 482 | ((Pm *)hw)->HIBCFG.reg = tmp; |
| 483 | PM_CRITICAL_SECTION_LEAVE(); |
| 484 | } |
| 485 | |
| 486 | static inline void hri_pm_clear_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) |
| 487 | { |
| 488 | PM_CRITICAL_SECTION_ENTER(); |
| 489 | ((Pm *)hw)->HIBCFG.reg &= ~PM_HIBCFG_RAMCFG(mask); |
| 490 | PM_CRITICAL_SECTION_LEAVE(); |
| 491 | } |
| 492 | |
| 493 | static inline void hri_pm_toggle_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) |
| 494 | { |
| 495 | PM_CRITICAL_SECTION_ENTER(); |
| 496 | ((Pm *)hw)->HIBCFG.reg ^= PM_HIBCFG_RAMCFG(mask); |
| 497 | PM_CRITICAL_SECTION_LEAVE(); |
| 498 | } |
| 499 | |
| 500 | static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_RAMCFG_bf(const void *const hw) |
| 501 | { |
| 502 | uint8_t tmp; |
| 503 | tmp = ((Pm *)hw)->HIBCFG.reg; |
| 504 | tmp = (tmp & PM_HIBCFG_RAMCFG_Msk) >> PM_HIBCFG_RAMCFG_Pos; |
| 505 | return tmp; |
| 506 | } |
| 507 | |
| 508 | static inline void hri_pm_set_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) |
| 509 | { |
| 510 | PM_CRITICAL_SECTION_ENTER(); |
| 511 | ((Pm *)hw)->HIBCFG.reg |= PM_HIBCFG_BRAMCFG(mask); |
| 512 | PM_CRITICAL_SECTION_LEAVE(); |
| 513 | } |
| 514 | |
| 515 | static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) |
| 516 | { |
| 517 | uint8_t tmp; |
| 518 | tmp = ((Pm *)hw)->HIBCFG.reg; |
| 519 | tmp = (tmp & PM_HIBCFG_BRAMCFG(mask)) >> PM_HIBCFG_BRAMCFG_Pos; |
| 520 | return tmp; |
| 521 | } |
| 522 | |
| 523 | static inline void hri_pm_write_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t data) |
| 524 | { |
| 525 | uint8_t tmp; |
| 526 | PM_CRITICAL_SECTION_ENTER(); |
| 527 | tmp = ((Pm *)hw)->HIBCFG.reg; |
| 528 | tmp &= ~PM_HIBCFG_BRAMCFG_Msk; |
| 529 | tmp |= PM_HIBCFG_BRAMCFG(data); |
| 530 | ((Pm *)hw)->HIBCFG.reg = tmp; |
| 531 | PM_CRITICAL_SECTION_LEAVE(); |
| 532 | } |
| 533 | |
| 534 | static inline void hri_pm_clear_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) |
| 535 | { |
| 536 | PM_CRITICAL_SECTION_ENTER(); |
| 537 | ((Pm *)hw)->HIBCFG.reg &= ~PM_HIBCFG_BRAMCFG(mask); |
| 538 | PM_CRITICAL_SECTION_LEAVE(); |
| 539 | } |
| 540 | |
| 541 | static inline void hri_pm_toggle_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) |
| 542 | { |
| 543 | PM_CRITICAL_SECTION_ENTER(); |
| 544 | ((Pm *)hw)->HIBCFG.reg ^= PM_HIBCFG_BRAMCFG(mask); |
| 545 | PM_CRITICAL_SECTION_LEAVE(); |
| 546 | } |
| 547 | |
| 548 | static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_BRAMCFG_bf(const void *const hw) |
| 549 | { |
| 550 | uint8_t tmp; |
| 551 | tmp = ((Pm *)hw)->HIBCFG.reg; |
| 552 | tmp = (tmp & PM_HIBCFG_BRAMCFG_Msk) >> PM_HIBCFG_BRAMCFG_Pos; |
| 553 | return tmp; |
| 554 | } |
| 555 | |
| 556 | static inline void hri_pm_set_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) |
| 557 | { |
| 558 | PM_CRITICAL_SECTION_ENTER(); |
| 559 | ((Pm *)hw)->HIBCFG.reg |= mask; |
| 560 | PM_CRITICAL_SECTION_LEAVE(); |
| 561 | } |
| 562 | |
| 563 | static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) |
| 564 | { |
| 565 | uint8_t tmp; |
| 566 | tmp = ((Pm *)hw)->HIBCFG.reg; |
| 567 | tmp &= mask; |
| 568 | return tmp; |
| 569 | } |
| 570 | |
| 571 | static inline void hri_pm_write_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t data) |
| 572 | { |
| 573 | PM_CRITICAL_SECTION_ENTER(); |
| 574 | ((Pm *)hw)->HIBCFG.reg = data; |
| 575 | PM_CRITICAL_SECTION_LEAVE(); |
| 576 | } |
| 577 | |
| 578 | static inline void hri_pm_clear_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) |
| 579 | { |
| 580 | PM_CRITICAL_SECTION_ENTER(); |
| 581 | ((Pm *)hw)->HIBCFG.reg &= ~mask; |
| 582 | PM_CRITICAL_SECTION_LEAVE(); |
| 583 | } |
| 584 | |
| 585 | static inline void hri_pm_toggle_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) |
| 586 | { |
| 587 | PM_CRITICAL_SECTION_ENTER(); |
| 588 | ((Pm *)hw)->HIBCFG.reg ^= mask; |
| 589 | PM_CRITICAL_SECTION_LEAVE(); |
| 590 | } |
| 591 | |
| 592 | static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_reg(const void *const hw) |
| 593 | { |
| 594 | return ((Pm *)hw)->HIBCFG.reg; |
| 595 | } |
| 596 | |
| 597 | static inline void hri_pm_set_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) |
| 598 | { |
| 599 | PM_CRITICAL_SECTION_ENTER(); |
| 600 | ((Pm *)hw)->BKUPCFG.reg |= PM_BKUPCFG_BRAMCFG(mask); |
| 601 | PM_CRITICAL_SECTION_LEAVE(); |
| 602 | } |
| 603 | |
| 604 | static inline hri_pm_bkupcfg_reg_t hri_pm_get_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) |
| 605 | { |
| 606 | uint8_t tmp; |
| 607 | tmp = ((Pm *)hw)->BKUPCFG.reg; |
| 608 | tmp = (tmp & PM_BKUPCFG_BRAMCFG(mask)) >> PM_BKUPCFG_BRAMCFG_Pos; |
| 609 | return tmp; |
| 610 | } |
| 611 | |
| 612 | static inline void hri_pm_write_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t data) |
| 613 | { |
| 614 | uint8_t tmp; |
| 615 | PM_CRITICAL_SECTION_ENTER(); |
| 616 | tmp = ((Pm *)hw)->BKUPCFG.reg; |
| 617 | tmp &= ~PM_BKUPCFG_BRAMCFG_Msk; |
| 618 | tmp |= PM_BKUPCFG_BRAMCFG(data); |
| 619 | ((Pm *)hw)->BKUPCFG.reg = tmp; |
| 620 | PM_CRITICAL_SECTION_LEAVE(); |
| 621 | } |
| 622 | |
| 623 | static inline void hri_pm_clear_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) |
| 624 | { |
| 625 | PM_CRITICAL_SECTION_ENTER(); |
| 626 | ((Pm *)hw)->BKUPCFG.reg &= ~PM_BKUPCFG_BRAMCFG(mask); |
| 627 | PM_CRITICAL_SECTION_LEAVE(); |
| 628 | } |
| 629 | |
| 630 | static inline void hri_pm_toggle_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) |
| 631 | { |
| 632 | PM_CRITICAL_SECTION_ENTER(); |
| 633 | ((Pm *)hw)->BKUPCFG.reg ^= PM_BKUPCFG_BRAMCFG(mask); |
| 634 | PM_CRITICAL_SECTION_LEAVE(); |
| 635 | } |
| 636 | |
| 637 | static inline hri_pm_bkupcfg_reg_t hri_pm_read_BKUPCFG_BRAMCFG_bf(const void *const hw) |
| 638 | { |
| 639 | uint8_t tmp; |
| 640 | tmp = ((Pm *)hw)->BKUPCFG.reg; |
| 641 | tmp = (tmp & PM_BKUPCFG_BRAMCFG_Msk) >> PM_BKUPCFG_BRAMCFG_Pos; |
| 642 | return tmp; |
| 643 | } |
| 644 | |
| 645 | static inline void hri_pm_set_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) |
| 646 | { |
| 647 | PM_CRITICAL_SECTION_ENTER(); |
| 648 | ((Pm *)hw)->BKUPCFG.reg |= mask; |
| 649 | PM_CRITICAL_SECTION_LEAVE(); |
| 650 | } |
| 651 | |
| 652 | static inline hri_pm_bkupcfg_reg_t hri_pm_get_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) |
| 653 | { |
| 654 | uint8_t tmp; |
| 655 | tmp = ((Pm *)hw)->BKUPCFG.reg; |
| 656 | tmp &= mask; |
| 657 | return tmp; |
| 658 | } |
| 659 | |
| 660 | static inline void hri_pm_write_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t data) |
| 661 | { |
| 662 | PM_CRITICAL_SECTION_ENTER(); |
| 663 | ((Pm *)hw)->BKUPCFG.reg = data; |
| 664 | PM_CRITICAL_SECTION_LEAVE(); |
| 665 | } |
| 666 | |
| 667 | static inline void hri_pm_clear_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) |
| 668 | { |
| 669 | PM_CRITICAL_SECTION_ENTER(); |
| 670 | ((Pm *)hw)->BKUPCFG.reg &= ~mask; |
| 671 | PM_CRITICAL_SECTION_LEAVE(); |
| 672 | } |
| 673 | |
| 674 | static inline void hri_pm_toggle_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) |
| 675 | { |
| 676 | PM_CRITICAL_SECTION_ENTER(); |
| 677 | ((Pm *)hw)->BKUPCFG.reg ^= mask; |
| 678 | PM_CRITICAL_SECTION_LEAVE(); |
| 679 | } |
| 680 | |
| 681 | static inline hri_pm_bkupcfg_reg_t hri_pm_read_BKUPCFG_reg(const void *const hw) |
| 682 | { |
| 683 | return ((Pm *)hw)->BKUPCFG.reg; |
| 684 | } |
| 685 | |
| 686 | static inline void hri_pm_set_PWSAKDLY_IGNACK_bit(const void *const hw) |
| 687 | { |
| 688 | PM_CRITICAL_SECTION_ENTER(); |
| 689 | ((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_IGNACK; |
| 690 | PM_CRITICAL_SECTION_LEAVE(); |
| 691 | } |
| 692 | |
| 693 | static inline bool hri_pm_get_PWSAKDLY_IGNACK_bit(const void *const hw) |
| 694 | { |
| 695 | uint8_t tmp; |
| 696 | tmp = ((Pm *)hw)->PWSAKDLY.reg; |
| 697 | tmp = (tmp & PM_PWSAKDLY_IGNACK) >> PM_PWSAKDLY_IGNACK_Pos; |
| 698 | return (bool)tmp; |
| 699 | } |
| 700 | |
| 701 | static inline void hri_pm_write_PWSAKDLY_IGNACK_bit(const void *const hw, bool value) |
| 702 | { |
| 703 | uint8_t tmp; |
| 704 | PM_CRITICAL_SECTION_ENTER(); |
| 705 | tmp = ((Pm *)hw)->PWSAKDLY.reg; |
| 706 | tmp &= ~PM_PWSAKDLY_IGNACK; |
| 707 | tmp |= value << PM_PWSAKDLY_IGNACK_Pos; |
| 708 | ((Pm *)hw)->PWSAKDLY.reg = tmp; |
| 709 | PM_CRITICAL_SECTION_LEAVE(); |
| 710 | } |
| 711 | |
| 712 | static inline void hri_pm_clear_PWSAKDLY_IGNACK_bit(const void *const hw) |
| 713 | { |
| 714 | PM_CRITICAL_SECTION_ENTER(); |
| 715 | ((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_IGNACK; |
| 716 | PM_CRITICAL_SECTION_LEAVE(); |
| 717 | } |
| 718 | |
| 719 | static inline void hri_pm_toggle_PWSAKDLY_IGNACK_bit(const void *const hw) |
| 720 | { |
| 721 | PM_CRITICAL_SECTION_ENTER(); |
| 722 | ((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_IGNACK; |
| 723 | PM_CRITICAL_SECTION_LEAVE(); |
| 724 | } |
| 725 | |
| 726 | static inline void hri_pm_set_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) |
| 727 | { |
| 728 | PM_CRITICAL_SECTION_ENTER(); |
| 729 | ((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_DLYVAL(mask); |
| 730 | PM_CRITICAL_SECTION_LEAVE(); |
| 731 | } |
| 732 | |
| 733 | static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) |
| 734 | { |
| 735 | uint8_t tmp; |
| 736 | tmp = ((Pm *)hw)->PWSAKDLY.reg; |
| 737 | tmp = (tmp & PM_PWSAKDLY_DLYVAL(mask)) >> PM_PWSAKDLY_DLYVAL_Pos; |
| 738 | return tmp; |
| 739 | } |
| 740 | |
| 741 | static inline void hri_pm_write_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t data) |
| 742 | { |
| 743 | uint8_t tmp; |
| 744 | PM_CRITICAL_SECTION_ENTER(); |
| 745 | tmp = ((Pm *)hw)->PWSAKDLY.reg; |
| 746 | tmp &= ~PM_PWSAKDLY_DLYVAL_Msk; |
| 747 | tmp |= PM_PWSAKDLY_DLYVAL(data); |
| 748 | ((Pm *)hw)->PWSAKDLY.reg = tmp; |
| 749 | PM_CRITICAL_SECTION_LEAVE(); |
| 750 | } |
| 751 | |
| 752 | static inline void hri_pm_clear_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) |
| 753 | { |
| 754 | PM_CRITICAL_SECTION_ENTER(); |
| 755 | ((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_DLYVAL(mask); |
| 756 | PM_CRITICAL_SECTION_LEAVE(); |
| 757 | } |
| 758 | |
| 759 | static inline void hri_pm_toggle_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) |
| 760 | { |
| 761 | PM_CRITICAL_SECTION_ENTER(); |
| 762 | ((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_DLYVAL(mask); |
| 763 | PM_CRITICAL_SECTION_LEAVE(); |
| 764 | } |
| 765 | |
| 766 | static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_DLYVAL_bf(const void *const hw) |
| 767 | { |
| 768 | uint8_t tmp; |
| 769 | tmp = ((Pm *)hw)->PWSAKDLY.reg; |
| 770 | tmp = (tmp & PM_PWSAKDLY_DLYVAL_Msk) >> PM_PWSAKDLY_DLYVAL_Pos; |
| 771 | return tmp; |
| 772 | } |
| 773 | |
| 774 | static inline void hri_pm_set_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) |
| 775 | { |
| 776 | PM_CRITICAL_SECTION_ENTER(); |
| 777 | ((Pm *)hw)->PWSAKDLY.reg |= mask; |
| 778 | PM_CRITICAL_SECTION_LEAVE(); |
| 779 | } |
| 780 | |
| 781 | static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) |
| 782 | { |
| 783 | uint8_t tmp; |
| 784 | tmp = ((Pm *)hw)->PWSAKDLY.reg; |
| 785 | tmp &= mask; |
| 786 | return tmp; |
| 787 | } |
| 788 | |
| 789 | static inline void hri_pm_write_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t data) |
| 790 | { |
| 791 | PM_CRITICAL_SECTION_ENTER(); |
| 792 | ((Pm *)hw)->PWSAKDLY.reg = data; |
| 793 | PM_CRITICAL_SECTION_LEAVE(); |
| 794 | } |
| 795 | |
| 796 | static inline void hri_pm_clear_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) |
| 797 | { |
| 798 | PM_CRITICAL_SECTION_ENTER(); |
| 799 | ((Pm *)hw)->PWSAKDLY.reg &= ~mask; |
| 800 | PM_CRITICAL_SECTION_LEAVE(); |
| 801 | } |
| 802 | |
| 803 | static inline void hri_pm_toggle_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) |
| 804 | { |
| 805 | PM_CRITICAL_SECTION_ENTER(); |
| 806 | ((Pm *)hw)->PWSAKDLY.reg ^= mask; |
| 807 | PM_CRITICAL_SECTION_LEAVE(); |
| 808 | } |
| 809 | |
| 810 | static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_reg(const void *const hw) |
| 811 | { |
| 812 | return ((Pm *)hw)->PWSAKDLY.reg; |
| 813 | } |
| 814 | |
| 815 | #ifdef __cplusplus |
| 816 | } |
| 817 | #endif |
| 818 | |
| 819 | #endif /* _HRI_PM_E54_H_INCLUDED */ |
| 820 | #endif /* _SAME54_PM_COMPONENT_ */ |