Blame - sysmoOCTSIM/include/component/sdhc.h - osmo-ccid-firmware

Kévin Redon

f041136

2019-06-06 17:42:44 +0200

[diff] [blame]

/**

* \file

*

* \brief Component description for SDHC

*

*

* \asf_license_start

*

* \page License

*

* SPDX-License-Identifier: Apache-2.0

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*

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* Licensed under the Apache License, Version 2.0 (the "License"); you may

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* not use this file except in compliance with the License.

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* You may obtain a copy of the Licence at

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*

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* http://www.apache.org/licenses/LICENSE-2.0

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*

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* Unless required by applicable law or agreed to in writing, software

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* distributed under the License is distributed on an AS IS BASIS, WITHOUT

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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

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* See the License for the specific language governing permissions and

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* limitations under the License.

*

* \asf_license_stop

*

*/

#ifndef _SAME54_SDHC_COMPONENT_

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#define _SAME54_SDHC_COMPONENT_

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/* ========================================================================== */

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/** SOFTWARE API DEFINITION FOR SDHC */

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/* ========================================================================== */

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/** \addtogroup SAME54_SDHC SD/MMC Host Controller */

/*@{*/

#define SDHC_U2011

#define REV_SDHC 0x183

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/* -------- SDHC_SSAR : (SDHC Offset: 0x000) (R/W 32) SDMA System Address / Argument 2 -------- */

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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

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typedef union {

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struct { // CMD23 mode

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uint32_t ARG2:32; /*!< bit: 0..31 Argument 2 */

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} CMD23; /*!< Structure used for CMD23 */

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struct {

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uint32_t ADDR:32; /*!< bit: 0..31 SDMA System Address */

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} bit; /*!< Structure used for bit access */

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uint32_t reg; /*!< Type used for register access */

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} SDHC_SSAR_Type;

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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

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#define SDHC_SSAR_OFFSET 0x000 /**< \brief (SDHC_SSAR offset) SDMA System Address / Argument 2 */

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#define SDHC_SSAR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_SSAR reset_value) SDMA System Address / Argument 2 */

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// CMD23 mode

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#define SDHC_SSAR_CMD23_ARG2_Pos 0 /**< \brief (SDHC_SSAR_CMD23) Argument 2 */

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#define SDHC_SSAR_CMD23_ARG2_Msk (_U_(0xFFFFFFFF) << SDHC_SSAR_CMD23_ARG2_Pos)

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#define SDHC_SSAR_CMD23_ARG2(value) (SDHC_SSAR_CMD23_ARG2_Msk & ((value) << SDHC_SSAR_CMD23_ARG2_Pos))

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#define SDHC_SSAR_CMD23_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_SSAR_CMD23) MASK Register */

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#define SDHC_SSAR_ADDR_Pos 0 /**< \brief (SDHC_SSAR) SDMA System Address */

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#define SDHC_SSAR_ADDR_Msk (_U_(0xFFFFFFFF) << SDHC_SSAR_ADDR_Pos)

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#define SDHC_SSAR_ADDR(value) (SDHC_SSAR_ADDR_Msk & ((value) << SDHC_SSAR_ADDR_Pos))

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#define SDHC_SSAR_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_SSAR) MASK Register */

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/* -------- SDHC_BSR : (SDHC Offset: 0x004) (R/W 16) Block Size -------- */

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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

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typedef union {

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struct {

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uint16_t BLOCKSIZE:10; /*!< bit: 0.. 9 Transfer Block Size */

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uint16_t :2; /*!< bit: 10..11 Reserved */

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uint16_t BOUNDARY:3; /*!< bit: 12..14 SDMA Buffer Boundary */

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uint16_t :1; /*!< bit: 15 Reserved */

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} bit; /*!< Structure used for bit access */

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uint16_t reg; /*!< Type used for register access */

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} SDHC_BSR_Type;

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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

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#define SDHC_BSR_OFFSET 0x004 /**< \brief (SDHC_BSR offset) Block Size */

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#define SDHC_BSR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_BSR reset_value) Block Size */

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#define SDHC_BSR_BLOCKSIZE_Pos 0 /**< \brief (SDHC_BSR) Transfer Block Size */

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#define SDHC_BSR_BLOCKSIZE_Msk (_U_(0x3FF) << SDHC_BSR_BLOCKSIZE_Pos)

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#define SDHC_BSR_BLOCKSIZE(value) (SDHC_BSR_BLOCKSIZE_Msk & ((value) << SDHC_BSR_BLOCKSIZE_Pos))

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#define SDHC_BSR_BOUNDARY_Pos 12 /**< \brief (SDHC_BSR) SDMA Buffer Boundary */

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#define SDHC_BSR_BOUNDARY_Msk (_U_(0x7) << SDHC_BSR_BOUNDARY_Pos)

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#define SDHC_BSR_BOUNDARY(value) (SDHC_BSR_BOUNDARY_Msk & ((value) << SDHC_BSR_BOUNDARY_Pos))

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#define SDHC_BSR_BOUNDARY_4K_Val _U_(0x0) /**< \brief (SDHC_BSR) 4k bytes */

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#define SDHC_BSR_BOUNDARY_8K_Val _U_(0x1) /**< \brief (SDHC_BSR) 8k bytes */

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#define SDHC_BSR_BOUNDARY_16K_Val _U_(0x2) /**< \brief (SDHC_BSR) 16k bytes */

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#define SDHC_BSR_BOUNDARY_32K_Val _U_(0x3) /**< \brief (SDHC_BSR) 32k bytes */

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#define SDHC_BSR_BOUNDARY_64K_Val _U_(0x4) /**< \brief (SDHC_BSR) 64k bytes */

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#define SDHC_BSR_BOUNDARY_128K_Val _U_(0x5) /**< \brief (SDHC_BSR) 128k bytes */

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#define SDHC_BSR_BOUNDARY_256K_Val _U_(0x6) /**< \brief (SDHC_BSR) 256k bytes */

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#define SDHC_BSR_BOUNDARY_512K_Val _U_(0x7) /**< \brief (SDHC_BSR) 512k bytes */

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#define SDHC_BSR_BOUNDARY_4K (SDHC_BSR_BOUNDARY_4K_Val << SDHC_BSR_BOUNDARY_Pos)

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#define SDHC_BSR_BOUNDARY_8K (SDHC_BSR_BOUNDARY_8K_Val << SDHC_BSR_BOUNDARY_Pos)

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#define SDHC_BSR_BOUNDARY_16K (SDHC_BSR_BOUNDARY_16K_Val << SDHC_BSR_BOUNDARY_Pos)

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#define SDHC_BSR_BOUNDARY_32K (SDHC_BSR_BOUNDARY_32K_Val << SDHC_BSR_BOUNDARY_Pos)

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#define SDHC_BSR_BOUNDARY_64K (SDHC_BSR_BOUNDARY_64K_Val << SDHC_BSR_BOUNDARY_Pos)

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#define SDHC_BSR_BOUNDARY_128K (SDHC_BSR_BOUNDARY_128K_Val << SDHC_BSR_BOUNDARY_Pos)

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#define SDHC_BSR_BOUNDARY_256K (SDHC_BSR_BOUNDARY_256K_Val << SDHC_BSR_BOUNDARY_Pos)

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#define SDHC_BSR_BOUNDARY_512K (SDHC_BSR_BOUNDARY_512K_Val << SDHC_BSR_BOUNDARY_Pos)

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#define SDHC_BSR_MASK _U_(0x73FF) /**< \brief (SDHC_BSR) MASK Register */

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/* -------- SDHC_BCR : (SDHC Offset: 0x006) (R/W 16) Block Count -------- */

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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

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typedef union {

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struct {

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uint16_t BCNT:16; /*!< bit: 0..15 Blocks Count for Current Transfer */

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} bit; /*!< Structure used for bit access */

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uint16_t reg; /*!< Type used for register access */

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} SDHC_BCR_Type;

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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

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#define SDHC_BCR_OFFSET 0x006 /**< \brief (SDHC_BCR offset) Block Count */

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#define SDHC_BCR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_BCR reset_value) Block Count */

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#define SDHC_BCR_BCNT_Pos 0 /**< \brief (SDHC_BCR) Blocks Count for Current Transfer */

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#define SDHC_BCR_BCNT_Msk (_U_(0xFFFF) << SDHC_BCR_BCNT_Pos)

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#define SDHC_BCR_BCNT(value) (SDHC_BCR_BCNT_Msk & ((value) << SDHC_BCR_BCNT_Pos))

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#define SDHC_BCR_MASK _U_(0xFFFF) /**< \brief (SDHC_BCR) MASK Register */

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/* -------- SDHC_ARG1R : (SDHC Offset: 0x008) (R/W 32) Argument 1 -------- */

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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

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typedef union {

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struct {

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uint32_t ARG:32; /*!< bit: 0..31 Argument 1 */

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} bit; /*!< Structure used for bit access */

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uint32_t reg; /*!< Type used for register access */

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} SDHC_ARG1R_Type;

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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

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#define SDHC_ARG1R_OFFSET 0x008 /**< \brief (SDHC_ARG1R offset) Argument 1 */

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#define SDHC_ARG1R_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_ARG1R reset_value) Argument 1 */

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#define SDHC_ARG1R_ARG_Pos 0 /**< \brief (SDHC_ARG1R) Argument 1 */

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#define SDHC_ARG1R_ARG_Msk (_U_(0xFFFFFFFF) << SDHC_ARG1R_ARG_Pos)

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#define SDHC_ARG1R_ARG(value) (SDHC_ARG1R_ARG_Msk & ((value) << SDHC_ARG1R_ARG_Pos))

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#define SDHC_ARG1R_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_ARG1R) MASK Register */

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/* -------- SDHC_TMR : (SDHC Offset: 0x00C) (R/W 16) Transfer Mode -------- */

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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

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typedef union {

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struct {

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uint16_t DMAEN:1; /*!< bit: 0 DMA Enable */

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uint16_t BCEN:1; /*!< bit: 1 Block Count Enable */

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uint16_t ACMDEN:2; /*!< bit: 2.. 3 Auto Command Enable */

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uint16_t DTDSEL:1; /*!< bit: 4 Data Transfer Direction Selection */

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uint16_t MSBSEL:1; /*!< bit: 5 Multi/Single Block Selection */

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uint16_t :10; /*!< bit: 6..15 Reserved */

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} bit; /*!< Structure used for bit access */

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uint16_t reg; /*!< Type used for register access */

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} SDHC_TMR_Type;

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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

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#define SDHC_TMR_OFFSET 0x00C /**< \brief (SDHC_TMR offset) Transfer Mode */

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#define SDHC_TMR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_TMR reset_value) Transfer Mode */

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#define SDHC_TMR_DMAEN_Pos 0 /**< \brief (SDHC_TMR) DMA Enable */

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#define SDHC_TMR_DMAEN (_U_(0x1) << SDHC_TMR_DMAEN_Pos)

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#define SDHC_TMR_DMAEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_TMR) No data transfer or Non DMA data transfer */

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#define SDHC_TMR_DMAEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_TMR) DMA data transfer */

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#define SDHC_TMR_DMAEN_DISABLE (SDHC_TMR_DMAEN_DISABLE_Val << SDHC_TMR_DMAEN_Pos)

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#define SDHC_TMR_DMAEN_ENABLE (SDHC_TMR_DMAEN_ENABLE_Val << SDHC_TMR_DMAEN_Pos)

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#define SDHC_TMR_BCEN_Pos 1 /**< \brief (SDHC_TMR) Block Count Enable */

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#define SDHC_TMR_BCEN (_U_(0x1) << SDHC_TMR_BCEN_Pos)

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#define SDHC_TMR_BCEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_TMR) Disable */

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#define SDHC_TMR_BCEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_TMR) Enable */

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#define SDHC_TMR_BCEN_DISABLE (SDHC_TMR_BCEN_DISABLE_Val << SDHC_TMR_BCEN_Pos)

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#define SDHC_TMR_BCEN_ENABLE (SDHC_TMR_BCEN_ENABLE_Val << SDHC_TMR_BCEN_Pos)

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#define SDHC_TMR_ACMDEN_Pos 2 /**< \brief (SDHC_TMR) Auto Command Enable */

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#define SDHC_TMR_ACMDEN_Msk (_U_(0x3) << SDHC_TMR_ACMDEN_Pos)

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#define SDHC_TMR_ACMDEN(value) (SDHC_TMR_ACMDEN_Msk & ((value) << SDHC_TMR_ACMDEN_Pos))

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#define SDHC_TMR_ACMDEN_DISABLED_Val _U_(0x0) /**< \brief (SDHC_TMR) Auto Command Disabled */

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#define SDHC_TMR_ACMDEN_CMD12_Val _U_(0x1) /**< \brief (SDHC_TMR) Auto CMD12 Enable */

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#define SDHC_TMR_ACMDEN_CMD23_Val _U_(0x2) /**< \brief (SDHC_TMR) Auto CMD23 Enable */

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#define SDHC_TMR_ACMDEN_3_Val _U_(0x3) /**< \brief (SDHC_TMR) Reserved */

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#define SDHC_TMR_ACMDEN_DISABLED (SDHC_TMR_ACMDEN_DISABLED_Val << SDHC_TMR_ACMDEN_Pos)

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#define SDHC_TMR_ACMDEN_CMD12 (SDHC_TMR_ACMDEN_CMD12_Val << SDHC_TMR_ACMDEN_Pos)

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#define SDHC_TMR_ACMDEN_CMD23 (SDHC_TMR_ACMDEN_CMD23_Val << SDHC_TMR_ACMDEN_Pos)

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#define SDHC_TMR_ACMDEN_3 (SDHC_TMR_ACMDEN_3_Val << SDHC_TMR_ACMDEN_Pos)

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#define SDHC_TMR_DTDSEL_Pos 4 /**< \brief (SDHC_TMR) Data Transfer Direction Selection */

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#define SDHC_TMR_DTDSEL (_U_(0x1) << SDHC_TMR_DTDSEL_Pos)

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#define SDHC_TMR_DTDSEL_WRITE_Val _U_(0x0) /**< \brief (SDHC_TMR) Write (Host to Card) */

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#define SDHC_TMR_DTDSEL_READ_Val _U_(0x1) /**< \brief (SDHC_TMR) Read (Card to Host) */

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#define SDHC_TMR_DTDSEL_WRITE (SDHC_TMR_DTDSEL_WRITE_Val << SDHC_TMR_DTDSEL_Pos)

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#define SDHC_TMR_DTDSEL_READ (SDHC_TMR_DTDSEL_READ_Val << SDHC_TMR_DTDSEL_Pos)

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#define SDHC_TMR_MSBSEL_Pos 5 /**< \brief (SDHC_TMR) Multi/Single Block Selection */

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#define SDHC_TMR_MSBSEL (_U_(0x1) << SDHC_TMR_MSBSEL_Pos)

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#define SDHC_TMR_MSBSEL_SINGLE_Val _U_(0x0) /**< \brief (SDHC_TMR) Single Block */

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#define SDHC_TMR_MSBSEL_MULTIPLE_Val _U_(0x1) /**< \brief (SDHC_TMR) Multiple Block */

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#define SDHC_TMR_MSBSEL_SINGLE (SDHC_TMR_MSBSEL_SINGLE_Val << SDHC_TMR_MSBSEL_Pos)

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#define SDHC_TMR_MSBSEL_MULTIPLE (SDHC_TMR_MSBSEL_MULTIPLE_Val << SDHC_TMR_MSBSEL_Pos)

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#define SDHC_TMR_MASK _U_(0x003F) /**< \brief (SDHC_TMR) MASK Register */

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/* -------- SDHC_CR : (SDHC Offset: 0x00E) (R/W 16) Command -------- */

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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

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typedef union {

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struct {

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uint16_t RESPTYP:2; /*!< bit: 0.. 1 Response Type */

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uint16_t :1; /*!< bit: 2 Reserved */

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uint16_t CMDCCEN:1; /*!< bit: 3 Command CRC Check Enable */

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uint16_t CMDICEN:1; /*!< bit: 4 Command Index Check Enable */

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uint16_t DPSEL:1; /*!< bit: 5 Data Present Select */

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uint16_t CMDTYP:2; /*!< bit: 6.. 7 Command Type */

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uint16_t CMDIDX:6; /*!< bit: 8..13 Command Index */

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uint16_t :2; /*!< bit: 14..15 Reserved */

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} bit; /*!< Structure used for bit access */

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uint16_t reg; /*!< Type used for register access */

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} SDHC_CR_Type;

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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

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#define SDHC_CR_OFFSET 0x00E /**< \brief (SDHC_CR offset) Command */

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#define SDHC_CR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_CR reset_value) Command */

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#define SDHC_CR_RESPTYP_Pos 0 /**< \brief (SDHC_CR) Response Type */

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#define SDHC_CR_RESPTYP_Msk (_U_(0x3) << SDHC_CR_RESPTYP_Pos)

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#define SDHC_CR_RESPTYP(value) (SDHC_CR_RESPTYP_Msk & ((value) << SDHC_CR_RESPTYP_Pos))

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#define SDHC_CR_RESPTYP_NONE_Val _U_(0x0) /**< \brief (SDHC_CR) No response */

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#define SDHC_CR_RESPTYP_136_BIT_Val _U_(0x1) /**< \brief (SDHC_CR) 136-bit response */

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#define SDHC_CR_RESPTYP_48_BIT_Val _U_(0x2) /**< \brief (SDHC_CR) 48-bit response */

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#define SDHC_CR_RESPTYP_48_BIT_BUSY_Val _U_(0x3) /**< \brief (SDHC_CR) 48-bit response check busy after response */

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#define SDHC_CR_RESPTYP_NONE (SDHC_CR_RESPTYP_NONE_Val << SDHC_CR_RESPTYP_Pos)

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#define SDHC_CR_RESPTYP_136_BIT (SDHC_CR_RESPTYP_136_BIT_Val << SDHC_CR_RESPTYP_Pos)

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#define SDHC_CR_RESPTYP_48_BIT (SDHC_CR_RESPTYP_48_BIT_Val << SDHC_CR_RESPTYP_Pos)

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#define SDHC_CR_RESPTYP_48_BIT_BUSY (SDHC_CR_RESPTYP_48_BIT_BUSY_Val << SDHC_CR_RESPTYP_Pos)

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#define SDHC_CR_CMDCCEN_Pos 3 /**< \brief (SDHC_CR) Command CRC Check Enable */

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#define SDHC_CR_CMDCCEN (_U_(0x1) << SDHC_CR_CMDCCEN_Pos)

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#define SDHC_CR_CMDCCEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_CR) Disable */

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#define SDHC_CR_CMDCCEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_CR) Enable */

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#define SDHC_CR_CMDCCEN_DISABLE (SDHC_CR_CMDCCEN_DISABLE_Val << SDHC_CR_CMDCCEN_Pos)

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#define SDHC_CR_CMDCCEN_ENABLE (SDHC_CR_CMDCCEN_ENABLE_Val << SDHC_CR_CMDCCEN_Pos)

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#define SDHC_CR_CMDICEN_Pos 4 /**< \brief (SDHC_CR) Command Index Check Enable */

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#define SDHC_CR_CMDICEN (_U_(0x1) << SDHC_CR_CMDICEN_Pos)

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#define SDHC_CR_CMDICEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_CR) Disable */

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#define SDHC_CR_CMDICEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_CR) Enable */

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#define SDHC_CR_CMDICEN_DISABLE (SDHC_CR_CMDICEN_DISABLE_Val << SDHC_CR_CMDICEN_Pos)

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#define SDHC_CR_CMDICEN_ENABLE (SDHC_CR_CMDICEN_ENABLE_Val << SDHC_CR_CMDICEN_Pos)

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#define SDHC_CR_DPSEL_Pos 5 /**< \brief (SDHC_CR) Data Present Select */

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#define SDHC_CR_DPSEL (_U_(0x1) << SDHC_CR_DPSEL_Pos)

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#define SDHC_CR_DPSEL_NO_DATA_Val _U_(0x0) /**< \brief (SDHC_CR) No Data Present */

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#define SDHC_CR_DPSEL_DATA_Val _U_(0x1) /**< \brief (SDHC_CR) Data Present */

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#define SDHC_CR_DPSEL_NO_DATA (SDHC_CR_DPSEL_NO_DATA_Val << SDHC_CR_DPSEL_Pos)

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#define SDHC_CR_DPSEL_DATA (SDHC_CR_DPSEL_DATA_Val << SDHC_CR_DPSEL_Pos)

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#define SDHC_CR_CMDTYP_Pos 6 /**< \brief (SDHC_CR) Command Type */

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#define SDHC_CR_CMDTYP_Msk (_U_(0x3) << SDHC_CR_CMDTYP_Pos)

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#define SDHC_CR_CMDTYP(value) (SDHC_CR_CMDTYP_Msk & ((value) << SDHC_CR_CMDTYP_Pos))

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#define SDHC_CR_CMDTYP_NORMAL_Val _U_(0x0) /**< \brief (SDHC_CR) Other commands */

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#define SDHC_CR_CMDTYP_SUSPEND_Val _U_(0x1) /**< \brief (SDHC_CR) CMD52 for writing Bus Suspend in CCCR */

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#define SDHC_CR_CMDTYP_RESUME_Val _U_(0x2) /**< \brief (SDHC_CR) CMD52 for writing Function Select in CCCR */

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#define SDHC_CR_CMDTYP_ABORT_Val _U_(0x3) /**< \brief (SDHC_CR) CMD12, CMD52 for writing I/O Abort in CCCR */

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#define SDHC_CR_CMDTYP_NORMAL (SDHC_CR_CMDTYP_NORMAL_Val << SDHC_CR_CMDTYP_Pos)

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#define SDHC_CR_CMDTYP_SUSPEND (SDHC_CR_CMDTYP_SUSPEND_Val << SDHC_CR_CMDTYP_Pos)

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#define SDHC_CR_CMDTYP_RESUME (SDHC_CR_CMDTYP_RESUME_Val << SDHC_CR_CMDTYP_Pos)

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#define SDHC_CR_CMDTYP_ABORT (SDHC_CR_CMDTYP_ABORT_Val << SDHC_CR_CMDTYP_Pos)

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#define SDHC_CR_CMDIDX_Pos 8 /**< \brief (SDHC_CR) Command Index */

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#define SDHC_CR_CMDIDX_Msk (_U_(0x3F) << SDHC_CR_CMDIDX_Pos)

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#define SDHC_CR_CMDIDX(value) (SDHC_CR_CMDIDX_Msk & ((value) << SDHC_CR_CMDIDX_Pos))

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#define SDHC_CR_MASK _U_(0x3FFB) /**< \brief (SDHC_CR) MASK Register */

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/* -------- SDHC_RR : (SDHC Offset: 0x010) (R/ 32) Response -------- */

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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

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typedef union {

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struct {

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uint32_t CMDRESP:32; /*!< bit: 0..31 Command Response */

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} bit; /*!< Structure used for bit access */

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uint32_t reg; /*!< Type used for register access */

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} SDHC_RR_Type;

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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

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#define SDHC_RR_OFFSET 0x010 /**< \brief (SDHC_RR offset) Response */

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#define SDHC_RR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_RR reset_value) Response */

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#define SDHC_RR_CMDRESP_Pos 0 /**< \brief (SDHC_RR) Command Response */

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#define SDHC_RR_CMDRESP_Msk (_U_(0xFFFFFFFF) << SDHC_RR_CMDRESP_Pos)

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#define SDHC_RR_CMDRESP(value) (SDHC_RR_CMDRESP_Msk & ((value) << SDHC_RR_CMDRESP_Pos))

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#define SDHC_RR_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_RR) MASK Register */

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/* -------- SDHC_BDPR : (SDHC Offset: 0x020) (R/W 32) Buffer Data Port -------- */

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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

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typedef union {

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struct {

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uint32_t BUFDATA:32; /*!< bit: 0..31 Buffer Data */

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} bit; /*!< Structure used for bit access */

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uint32_t reg; /*!< Type used for register access */

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} SDHC_BDPR_Type;

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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

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#define SDHC_BDPR_OFFSET 0x020 /**< \brief (SDHC_BDPR offset) Buffer Data Port */

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#define SDHC_BDPR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_BDPR reset_value) Buffer Data Port */

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#define SDHC_BDPR_BUFDATA_Pos 0 /**< \brief (SDHC_BDPR) Buffer Data */

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#define SDHC_BDPR_BUFDATA_Msk (_U_(0xFFFFFFFF) << SDHC_BDPR_BUFDATA_Pos)

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#define SDHC_BDPR_BUFDATA(value) (SDHC_BDPR_BUFDATA_Msk & ((value) << SDHC_BDPR_BUFDATA_Pos))

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#define SDHC_BDPR_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_BDPR) MASK Register */

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/* -------- SDHC_PSR : (SDHC Offset: 0x024) (R/ 32) Present State -------- */

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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

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typedef union {

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struct {

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uint32_t CMDINHC:1; /*!< bit: 0 Command Inhibit (CMD) */

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uint32_t CMDINHD:1; /*!< bit: 1 Command Inhibit (DAT) */

307

uint32_t DLACT:1; /*!< bit: 2 DAT Line Active */

308

uint32_t RTREQ:1; /*!< bit: 3 Re-Tuning Request */

309

uint32_t :4; /*!< bit: 4.. 7 Reserved */

310

uint32_t WTACT:1; /*!< bit: 8 Write Transfer Active */

311

uint32_t RTACT:1; /*!< bit: 9 Read Transfer Active */

312

uint32_t BUFWREN:1; /*!< bit: 10 Buffer Write Enable */

313

uint32_t BUFRDEN:1; /*!< bit: 11 Buffer Read Enable */

314

uint32_t :4; /*!< bit: 12..15 Reserved */

315

uint32_t CARDINS:1; /*!< bit: 16 Card Inserted */

316

uint32_t CARDSS:1; /*!< bit: 17 Card State Stable */

317

uint32_t CARDDPL:1; /*!< bit: 18 Card Detect Pin Level */

318

uint32_t WRPPL:1; /*!< bit: 19 Write Protect Pin Level */

319

uint32_t DATLL:4; /*!< bit: 20..23 DAT[3:0] Line Level */

320

uint32_t CMDLL:1; /*!< bit: 24 CMD Line Level */

321

uint32_t :7; /*!< bit: 25..31 Reserved */

322

} bit; /*!< Structure used for bit access */

323

uint32_t reg; /*!< Type used for register access */

324

} SDHC_PSR_Type;

325

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

326

327

#define SDHC_PSR_OFFSET 0x024 /**< \brief (SDHC_PSR offset) Present State */

328

#define SDHC_PSR_RESETVALUE _U_(0x00F80000) /**< \brief (SDHC_PSR reset_value) Present State */

329

330

#define SDHC_PSR_CMDINHC_Pos 0 /**< \brief (SDHC_PSR) Command Inhibit (CMD) */

331

#define SDHC_PSR_CMDINHC (_U_(0x1) << SDHC_PSR_CMDINHC_Pos)

332

#define SDHC_PSR_CMDINHC_CAN_Val _U_(0x0) /**< \brief (SDHC_PSR) Can issue command using only CMD line */

333

#define SDHC_PSR_CMDINHC_CANNOT_Val _U_(0x1) /**< \brief (SDHC_PSR) Cannot issue command */

334

#define SDHC_PSR_CMDINHC_CAN (SDHC_PSR_CMDINHC_CAN_Val << SDHC_PSR_CMDINHC_Pos)

335

#define SDHC_PSR_CMDINHC_CANNOT (SDHC_PSR_CMDINHC_CANNOT_Val << SDHC_PSR_CMDINHC_Pos)

336

#define SDHC_PSR_CMDINHD_Pos 1 /**< \brief (SDHC_PSR) Command Inhibit (DAT) */

337

#define SDHC_PSR_CMDINHD (_U_(0x1) << SDHC_PSR_CMDINHD_Pos)

338

#define SDHC_PSR_CMDINHD_CAN_Val _U_(0x0) /**< \brief (SDHC_PSR) Can issue command which uses the DAT line */

339

#define SDHC_PSR_CMDINHD_CANNOT_Val _U_(0x1) /**< \brief (SDHC_PSR) Cannot issue command which uses the DAT line */

340

#define SDHC_PSR_CMDINHD_CAN (SDHC_PSR_CMDINHD_CAN_Val << SDHC_PSR_CMDINHD_Pos)

341

#define SDHC_PSR_CMDINHD_CANNOT (SDHC_PSR_CMDINHD_CANNOT_Val << SDHC_PSR_CMDINHD_Pos)

342

#define SDHC_PSR_DLACT_Pos 2 /**< \brief (SDHC_PSR) DAT Line Active */

343

#define SDHC_PSR_DLACT (_U_(0x1) << SDHC_PSR_DLACT_Pos)

344

#define SDHC_PSR_DLACT_INACTIVE_Val _U_(0x0) /**< \brief (SDHC_PSR) DAT Line Inactive */

345

#define SDHC_PSR_DLACT_ACTIVE_Val _U_(0x1) /**< \brief (SDHC_PSR) DAT Line Active */

346

#define SDHC_PSR_DLACT_INACTIVE (SDHC_PSR_DLACT_INACTIVE_Val << SDHC_PSR_DLACT_Pos)

347

#define SDHC_PSR_DLACT_ACTIVE (SDHC_PSR_DLACT_ACTIVE_Val << SDHC_PSR_DLACT_Pos)

348

#define SDHC_PSR_RTREQ_Pos 3 /**< \brief (SDHC_PSR) Re-Tuning Request */

349

#define SDHC_PSR_RTREQ (_U_(0x1) << SDHC_PSR_RTREQ_Pos)

350

#define SDHC_PSR_RTREQ_OK_Val _U_(0x0) /**< \brief (SDHC_PSR) Fixed or well-tuned sampling clock */

351

#define SDHC_PSR_RTREQ_REQUIRED_Val _U_(0x1) /**< \brief (SDHC_PSR) Sampling clock needs re-tuning */

352

#define SDHC_PSR_RTREQ_OK (SDHC_PSR_RTREQ_OK_Val << SDHC_PSR_RTREQ_Pos)

353

#define SDHC_PSR_RTREQ_REQUIRED (SDHC_PSR_RTREQ_REQUIRED_Val << SDHC_PSR_RTREQ_Pos)

354

#define SDHC_PSR_WTACT_Pos 8 /**< \brief (SDHC_PSR) Write Transfer Active */

355

#define SDHC_PSR_WTACT (_U_(0x1) << SDHC_PSR_WTACT_Pos)

356

#define SDHC_PSR_WTACT_NO_Val _U_(0x0) /**< \brief (SDHC_PSR) No valid data */

357

#define SDHC_PSR_WTACT_YES_Val _U_(0x1) /**< \brief (SDHC_PSR) Transferring data */

358

#define SDHC_PSR_WTACT_NO (SDHC_PSR_WTACT_NO_Val << SDHC_PSR_WTACT_Pos)

359

#define SDHC_PSR_WTACT_YES (SDHC_PSR_WTACT_YES_Val << SDHC_PSR_WTACT_Pos)

360

#define SDHC_PSR_RTACT_Pos 9 /**< \brief (SDHC_PSR) Read Transfer Active */

361

#define SDHC_PSR_RTACT (_U_(0x1) << SDHC_PSR_RTACT_Pos)

362

#define SDHC_PSR_RTACT_NO_Val _U_(0x0) /**< \brief (SDHC_PSR) No valid data */

363

#define SDHC_PSR_RTACT_YES_Val _U_(0x1) /**< \brief (SDHC_PSR) Transferring data */

364

#define SDHC_PSR_RTACT_NO (SDHC_PSR_RTACT_NO_Val << SDHC_PSR_RTACT_Pos)

365

#define SDHC_PSR_RTACT_YES (SDHC_PSR_RTACT_YES_Val << SDHC_PSR_RTACT_Pos)

366

#define SDHC_PSR_BUFWREN_Pos 10 /**< \brief (SDHC_PSR) Buffer Write Enable */

367

#define SDHC_PSR_BUFWREN (_U_(0x1) << SDHC_PSR_BUFWREN_Pos)

368

#define SDHC_PSR_BUFWREN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_PSR) Write disable */

369

#define SDHC_PSR_BUFWREN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_PSR) Write enable */

370

#define SDHC_PSR_BUFWREN_DISABLE (SDHC_PSR_BUFWREN_DISABLE_Val << SDHC_PSR_BUFWREN_Pos)

371

#define SDHC_PSR_BUFWREN_ENABLE (SDHC_PSR_BUFWREN_ENABLE_Val << SDHC_PSR_BUFWREN_Pos)

372

#define SDHC_PSR_BUFRDEN_Pos 11 /**< \brief (SDHC_PSR) Buffer Read Enable */

373

#define SDHC_PSR_BUFRDEN (_U_(0x1) << SDHC_PSR_BUFRDEN_Pos)

374

#define SDHC_PSR_BUFRDEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_PSR) Read disable */

375

#define SDHC_PSR_BUFRDEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_PSR) Read enable */

376

#define SDHC_PSR_BUFRDEN_DISABLE (SDHC_PSR_BUFRDEN_DISABLE_Val << SDHC_PSR_BUFRDEN_Pos)

377

#define SDHC_PSR_BUFRDEN_ENABLE (SDHC_PSR_BUFRDEN_ENABLE_Val << SDHC_PSR_BUFRDEN_Pos)

378

#define SDHC_PSR_CARDINS_Pos 16 /**< \brief (SDHC_PSR) Card Inserted */

379

#define SDHC_PSR_CARDINS (_U_(0x1) << SDHC_PSR_CARDINS_Pos)

380

#define SDHC_PSR_CARDINS_NO_Val _U_(0x0) /**< \brief (SDHC_PSR) Reset or Debouncing or No Card */

381

#define SDHC_PSR_CARDINS_YES_Val _U_(0x1) /**< \brief (SDHC_PSR) Card inserted */

382

#define SDHC_PSR_CARDINS_NO (SDHC_PSR_CARDINS_NO_Val << SDHC_PSR_CARDINS_Pos)

383

#define SDHC_PSR_CARDINS_YES (SDHC_PSR_CARDINS_YES_Val << SDHC_PSR_CARDINS_Pos)

384

#define SDHC_PSR_CARDSS_Pos 17 /**< \brief (SDHC_PSR) Card State Stable */

385

#define SDHC_PSR_CARDSS (_U_(0x1) << SDHC_PSR_CARDSS_Pos)

386

#define SDHC_PSR_CARDSS_NO_Val _U_(0x0) /**< \brief (SDHC_PSR) Reset or Debouncing */

387

#define SDHC_PSR_CARDSS_YES_Val _U_(0x1) /**< \brief (SDHC_PSR) No Card or Insered */

388

#define SDHC_PSR_CARDSS_NO (SDHC_PSR_CARDSS_NO_Val << SDHC_PSR_CARDSS_Pos)

389

#define SDHC_PSR_CARDSS_YES (SDHC_PSR_CARDSS_YES_Val << SDHC_PSR_CARDSS_Pos)

390

#define SDHC_PSR_CARDDPL_Pos 18 /**< \brief (SDHC_PSR) Card Detect Pin Level */

391

#define SDHC_PSR_CARDDPL (_U_(0x1) << SDHC_PSR_CARDDPL_Pos)

392

#define SDHC_PSR_CARDDPL_NO_Val _U_(0x0) /**< \brief (SDHC_PSR) No card present (SDCD#=1) */

393

#define SDHC_PSR_CARDDPL_YES_Val _U_(0x1) /**< \brief (SDHC_PSR) Card present (SDCD#=0) */

394

#define SDHC_PSR_CARDDPL_NO (SDHC_PSR_CARDDPL_NO_Val << SDHC_PSR_CARDDPL_Pos)

395

#define SDHC_PSR_CARDDPL_YES (SDHC_PSR_CARDDPL_YES_Val << SDHC_PSR_CARDDPL_Pos)

396

#define SDHC_PSR_WRPPL_Pos 19 /**< \brief (SDHC_PSR) Write Protect Pin Level */

397

#define SDHC_PSR_WRPPL (_U_(0x1) << SDHC_PSR_WRPPL_Pos)

398

#define SDHC_PSR_WRPPL_PROTECTED_Val _U_(0x0) /**< \brief (SDHC_PSR) Write protected (SDWP#=0) */

399

#define SDHC_PSR_WRPPL_ENABLED_Val _U_(0x1) /**< \brief (SDHC_PSR) Write enabled (SDWP#=1) */

400

#define SDHC_PSR_WRPPL_PROTECTED (SDHC_PSR_WRPPL_PROTECTED_Val << SDHC_PSR_WRPPL_Pos)

401

#define SDHC_PSR_WRPPL_ENABLED (SDHC_PSR_WRPPL_ENABLED_Val << SDHC_PSR_WRPPL_Pos)

402

#define SDHC_PSR_DATLL_Pos 20 /**< \brief (SDHC_PSR) DAT[3:0] Line Level */

403

#define SDHC_PSR_DATLL_Msk (_U_(0xF) << SDHC_PSR_DATLL_Pos)

404

#define SDHC_PSR_DATLL(value) (SDHC_PSR_DATLL_Msk & ((value) << SDHC_PSR_DATLL_Pos))

405

#define SDHC_PSR_CMDLL_Pos 24 /**< \brief (SDHC_PSR) CMD Line Level */

406

#define SDHC_PSR_CMDLL (_U_(0x1) << SDHC_PSR_CMDLL_Pos)

407

#define SDHC_PSR_MASK _U_(0x01FF0F0F) /**< \brief (SDHC_PSR) MASK Register */

408

409

/* -------- SDHC_HC1R : (SDHC Offset: 0x028) (R/W 8) Host Control 1 -------- */

410

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

411

typedef union {

412

struct {

413

uint8_t LEDCTRL:1; /*!< bit: 0 LED Control */

414

uint8_t DW:1; /*!< bit: 1 Data Width */

415

uint8_t HSEN:1; /*!< bit: 2 High Speed Enable */

416

uint8_t DMASEL:2; /*!< bit: 3.. 4 DMA Select */

417

uint8_t :1; /*!< bit: 5 Reserved */

418

uint8_t CARDDTL:1; /*!< bit: 6 Card Detect Test Level */

419

uint8_t CARDDSEL:1; /*!< bit: 7 Card Detect Signal Selection */

420

} bit; /*!< Structure used for bit access */

421

struct { // EMMC mode

422

uint8_t :1; /*!< bit: 0 Reserved */

423

uint8_t DW:1; /*!< bit: 1 Data Width */

424

uint8_t HSEN:1; /*!< bit: 2 High Speed Enable */

425

uint8_t DMASEL:2; /*!< bit: 3.. 4 DMA Select */

426

uint8_t :3; /*!< bit: 5.. 7 Reserved */

427

} EMMC; /*!< Structure used for EMMC */

428

uint8_t reg; /*!< Type used for register access */

429

} SDHC_HC1R_Type;

430

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

431

432

#define SDHC_HC1R_OFFSET 0x028 /**< \brief (SDHC_HC1R offset) Host Control 1 */

433

#define SDHC_HC1R_RESETVALUE _U_(0xE00) /**< \brief (SDHC_HC1R reset_value) Host Control 1 */

434

435

#define SDHC_HC1R_LEDCTRL_Pos 0 /**< \brief (SDHC_HC1R) LED Control */

436

#define SDHC_HC1R_LEDCTRL (_U_(0x1) << SDHC_HC1R_LEDCTRL_Pos)

437

#define SDHC_HC1R_LEDCTRL_OFF_Val _U_(0x0) /**< \brief (SDHC_HC1R) LED off */

438

#define SDHC_HC1R_LEDCTRL_ON_Val _U_(0x1) /**< \brief (SDHC_HC1R) LED on */

439

#define SDHC_HC1R_LEDCTRL_OFF (SDHC_HC1R_LEDCTRL_OFF_Val << SDHC_HC1R_LEDCTRL_Pos)

440

#define SDHC_HC1R_LEDCTRL_ON (SDHC_HC1R_LEDCTRL_ON_Val << SDHC_HC1R_LEDCTRL_Pos)

441

#define SDHC_HC1R_DW_Pos 1 /**< \brief (SDHC_HC1R) Data Width */

442

#define SDHC_HC1R_DW (_U_(0x1) << SDHC_HC1R_DW_Pos)

443

#define SDHC_HC1R_DW_1BIT_Val _U_(0x0) /**< \brief (SDHC_HC1R) 1-bit mode */

444

#define SDHC_HC1R_DW_4BIT_Val _U_(0x1) /**< \brief (SDHC_HC1R) 4-bit mode */

445

#define SDHC_HC1R_DW_1BIT (SDHC_HC1R_DW_1BIT_Val << SDHC_HC1R_DW_Pos)

446

#define SDHC_HC1R_DW_4BIT (SDHC_HC1R_DW_4BIT_Val << SDHC_HC1R_DW_Pos)

447

#define SDHC_HC1R_HSEN_Pos 2 /**< \brief (SDHC_HC1R) High Speed Enable */

448

#define SDHC_HC1R_HSEN (_U_(0x1) << SDHC_HC1R_HSEN_Pos)

449

#define SDHC_HC1R_HSEN_NORMAL_Val _U_(0x0) /**< \brief (SDHC_HC1R) Normal Speed mode */

450

#define SDHC_HC1R_HSEN_HIGH_Val _U_(0x1) /**< \brief (SDHC_HC1R) High Speed mode */

451

#define SDHC_HC1R_HSEN_NORMAL (SDHC_HC1R_HSEN_NORMAL_Val << SDHC_HC1R_HSEN_Pos)

452

#define SDHC_HC1R_HSEN_HIGH (SDHC_HC1R_HSEN_HIGH_Val << SDHC_HC1R_HSEN_Pos)

453

#define SDHC_HC1R_DMASEL_Pos 3 /**< \brief (SDHC_HC1R) DMA Select */

454

#define SDHC_HC1R_DMASEL_Msk (_U_(0x3) << SDHC_HC1R_DMASEL_Pos)

455

#define SDHC_HC1R_DMASEL(value) (SDHC_HC1R_DMASEL_Msk & ((value) << SDHC_HC1R_DMASEL_Pos))

456

#define SDHC_HC1R_DMASEL_SDMA_Val _U_(0x0) /**< \brief (SDHC_HC1R) SDMA is selected */

457

#define SDHC_HC1R_DMASEL_1_Val _U_(0x1) /**< \brief (SDHC_HC1R) Reserved */

458

#define SDHC_HC1R_DMASEL_32BIT_Val _U_(0x2) /**< \brief (SDHC_HC1R) 32-bit Address ADMA2 is selected */

459

#define SDHC_HC1R_DMASEL_SDMA (SDHC_HC1R_DMASEL_SDMA_Val << SDHC_HC1R_DMASEL_Pos)

460

#define SDHC_HC1R_DMASEL_1 (SDHC_HC1R_DMASEL_1_Val << SDHC_HC1R_DMASEL_Pos)

461

#define SDHC_HC1R_DMASEL_32BIT (SDHC_HC1R_DMASEL_32BIT_Val << SDHC_HC1R_DMASEL_Pos)

462

#define SDHC_HC1R_CARDDTL_Pos 6 /**< \brief (SDHC_HC1R) Card Detect Test Level */

463

#define SDHC_HC1R_CARDDTL (_U_(0x1) << SDHC_HC1R_CARDDTL_Pos)

464

#define SDHC_HC1R_CARDDTL_NO_Val _U_(0x0) /**< \brief (SDHC_HC1R) No Card */

465

#define SDHC_HC1R_CARDDTL_YES_Val _U_(0x1) /**< \brief (SDHC_HC1R) Card Inserted */

466

#define SDHC_HC1R_CARDDTL_NO (SDHC_HC1R_CARDDTL_NO_Val << SDHC_HC1R_CARDDTL_Pos)

467

#define SDHC_HC1R_CARDDTL_YES (SDHC_HC1R_CARDDTL_YES_Val << SDHC_HC1R_CARDDTL_Pos)

468

#define SDHC_HC1R_CARDDSEL_Pos 7 /**< \brief (SDHC_HC1R) Card Detect Signal Selection */

469

#define SDHC_HC1R_CARDDSEL (_U_(0x1) << SDHC_HC1R_CARDDSEL_Pos)

470

#define SDHC_HC1R_CARDDSEL_NORMAL_Val _U_(0x0) /**< \brief (SDHC_HC1R) SDCD# is selected (for normal use) */

471

#define SDHC_HC1R_CARDDSEL_TEST_Val _U_(0x1) /**< \brief (SDHC_HC1R) The Card Select Test Level is selected (for test purpose) */

472

#define SDHC_HC1R_CARDDSEL_NORMAL (SDHC_HC1R_CARDDSEL_NORMAL_Val << SDHC_HC1R_CARDDSEL_Pos)

473

#define SDHC_HC1R_CARDDSEL_TEST (SDHC_HC1R_CARDDSEL_TEST_Val << SDHC_HC1R_CARDDSEL_Pos)

474

#define SDHC_HC1R_MASK _U_(0xDF) /**< \brief (SDHC_HC1R) MASK Register */

475

476

// EMMC mode

477

#define SDHC_HC1R_EMMC_DW_Pos 1 /**< \brief (SDHC_HC1R_EMMC) Data Width */

478

#define SDHC_HC1R_EMMC_DW (_U_(0x1) << SDHC_HC1R_EMMC_DW_Pos)

479

#define SDHC_HC1R_EMMC_DW_1BIT_Val _U_(0x0) /**< \brief (SDHC_HC1R_EMMC) 1-bit mode */

480

#define SDHC_HC1R_EMMC_DW_4BIT_Val _U_(0x1) /**< \brief (SDHC_HC1R_EMMC) 4-bit mode */

481

#define SDHC_HC1R_EMMC_DW_1BIT (SDHC_HC1R_EMMC_DW_1BIT_Val << SDHC_HC1R_EMMC_DW_Pos)

482

#define SDHC_HC1R_EMMC_DW_4BIT (SDHC_HC1R_EMMC_DW_4BIT_Val << SDHC_HC1R_EMMC_DW_Pos)

483

#define SDHC_HC1R_EMMC_HSEN_Pos 2 /**< \brief (SDHC_HC1R_EMMC) High Speed Enable */

484

#define SDHC_HC1R_EMMC_HSEN (_U_(0x1) << SDHC_HC1R_EMMC_HSEN_Pos)

485

#define SDHC_HC1R_EMMC_HSEN_NORMAL_Val _U_(0x0) /**< \brief (SDHC_HC1R_EMMC) Normal Speed mode */

486

#define SDHC_HC1R_EMMC_HSEN_HIGH_Val _U_(0x1) /**< \brief (SDHC_HC1R_EMMC) High Speed mode */

487

#define SDHC_HC1R_EMMC_HSEN_NORMAL (SDHC_HC1R_EMMC_HSEN_NORMAL_Val << SDHC_HC1R_EMMC_HSEN_Pos)

488

#define SDHC_HC1R_EMMC_HSEN_HIGH (SDHC_HC1R_EMMC_HSEN_HIGH_Val << SDHC_HC1R_EMMC_HSEN_Pos)

489

#define SDHC_HC1R_EMMC_DMASEL_Pos 3 /**< \brief (SDHC_HC1R_EMMC) DMA Select */

490

#define SDHC_HC1R_EMMC_DMASEL_Msk (_U_(0x3) << SDHC_HC1R_EMMC_DMASEL_Pos)

491

#define SDHC_HC1R_EMMC_DMASEL(value) (SDHC_HC1R_EMMC_DMASEL_Msk & ((value) << SDHC_HC1R_EMMC_DMASEL_Pos))

492

#define SDHC_HC1R_EMMC_DMASEL_SDMA_Val _U_(0x0) /**< \brief (SDHC_HC1R_EMMC) SDMA is selected */

493

#define SDHC_HC1R_EMMC_DMASEL_1_Val _U_(0x1) /**< \brief (SDHC_HC1R_EMMC) Reserved */

494

#define SDHC_HC1R_EMMC_DMASEL_32BIT_Val _U_(0x2) /**< \brief (SDHC_HC1R_EMMC) 32-bit Address ADMA2 is selected */

495

#define SDHC_HC1R_EMMC_DMASEL_SDMA (SDHC_HC1R_EMMC_DMASEL_SDMA_Val << SDHC_HC1R_EMMC_DMASEL_Pos)

496

#define SDHC_HC1R_EMMC_DMASEL_1 (SDHC_HC1R_EMMC_DMASEL_1_Val << SDHC_HC1R_EMMC_DMASEL_Pos)

497

#define SDHC_HC1R_EMMC_DMASEL_32BIT (SDHC_HC1R_EMMC_DMASEL_32BIT_Val << SDHC_HC1R_EMMC_DMASEL_Pos)

498

#define SDHC_HC1R_EMMC_MASK _U_(0x1E) /**< \brief (SDHC_HC1R_EMMC) MASK Register */

499

500

/* -------- SDHC_PCR : (SDHC Offset: 0x029) (R/W 8) Power Control -------- */

501

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

502

typedef union {

503

struct {

504

uint8_t SDBPWR:1; /*!< bit: 0 SD Bus Power */

505

uint8_t SDBVSEL:3; /*!< bit: 1.. 3 SD Bus Voltage Select */

506

uint8_t :4; /*!< bit: 4.. 7 Reserved */

507

} bit; /*!< Structure used for bit access */

508

uint8_t reg; /*!< Type used for register access */

509

} SDHC_PCR_Type;

510

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

511

512

#define SDHC_PCR_OFFSET 0x029 /**< \brief (SDHC_PCR offset) Power Control */

513

#define SDHC_PCR_RESETVALUE _U_(0x0E) /**< \brief (SDHC_PCR reset_value) Power Control */

514

515

#define SDHC_PCR_SDBPWR_Pos 0 /**< \brief (SDHC_PCR) SD Bus Power */

516

#define SDHC_PCR_SDBPWR (_U_(0x1) << SDHC_PCR_SDBPWR_Pos)

517

#define SDHC_PCR_SDBPWR_OFF_Val _U_(0x0) /**< \brief (SDHC_PCR) Power off */

518

#define SDHC_PCR_SDBPWR_ON_Val _U_(0x1) /**< \brief (SDHC_PCR) Power on */

519

#define SDHC_PCR_SDBPWR_OFF (SDHC_PCR_SDBPWR_OFF_Val << SDHC_PCR_SDBPWR_Pos)

520

#define SDHC_PCR_SDBPWR_ON (SDHC_PCR_SDBPWR_ON_Val << SDHC_PCR_SDBPWR_Pos)

521

#define SDHC_PCR_SDBVSEL_Pos 1 /**< \brief (SDHC_PCR) SD Bus Voltage Select */

522

#define SDHC_PCR_SDBVSEL_Msk (_U_(0x7) << SDHC_PCR_SDBVSEL_Pos)

523

#define SDHC_PCR_SDBVSEL(value) (SDHC_PCR_SDBVSEL_Msk & ((value) << SDHC_PCR_SDBVSEL_Pos))

524

#define SDHC_PCR_SDBVSEL_1V8_Val _U_(0x5) /**< \brief (SDHC_PCR) 1.8V (Typ.) */

525

#define SDHC_PCR_SDBVSEL_3V0_Val _U_(0x6) /**< \brief (SDHC_PCR) 3.0V (Typ.) */

526

#define SDHC_PCR_SDBVSEL_3V3_Val _U_(0x7) /**< \brief (SDHC_PCR) 3.3V (Typ.) */

527

#define SDHC_PCR_SDBVSEL_1V8 (SDHC_PCR_SDBVSEL_1V8_Val << SDHC_PCR_SDBVSEL_Pos)

528

#define SDHC_PCR_SDBVSEL_3V0 (SDHC_PCR_SDBVSEL_3V0_Val << SDHC_PCR_SDBVSEL_Pos)

529

#define SDHC_PCR_SDBVSEL_3V3 (SDHC_PCR_SDBVSEL_3V3_Val << SDHC_PCR_SDBVSEL_Pos)

530

#define SDHC_PCR_MASK _U_(0x0F) /**< \brief (SDHC_PCR) MASK Register */

531

532

/* -------- SDHC_BGCR : (SDHC Offset: 0x02A) (R/W 8) Block Gap Control -------- */

533

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

534

typedef union {

535

struct {

536

uint8_t STPBGR:1; /*!< bit: 0 Stop at Block Gap Request */

537

uint8_t CONTR:1; /*!< bit: 1 Continue Request */

538

uint8_t RWCTRL:1; /*!< bit: 2 Read Wait Control */

539

uint8_t INTBG:1; /*!< bit: 3 Interrupt at Block Gap */

540

uint8_t :4; /*!< bit: 4.. 7 Reserved */

541

} bit; /*!< Structure used for bit access */

542

struct { // EMMC mode

543

uint8_t STPBGR:1; /*!< bit: 0 Stop at Block Gap Request */

544

uint8_t CONTR:1; /*!< bit: 1 Continue Request */

545

uint8_t :6; /*!< bit: 2.. 7 Reserved */

546

} EMMC; /*!< Structure used for EMMC */

547

uint8_t reg; /*!< Type used for register access */

548

} SDHC_BGCR_Type;

549

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

550

551

#define SDHC_BGCR_OFFSET 0x02A /**< \brief (SDHC_BGCR offset) Block Gap Control */

552

#define SDHC_BGCR_RESETVALUE _U_(0x00) /**< \brief (SDHC_BGCR reset_value) Block Gap Control */

553

554

#define SDHC_BGCR_STPBGR_Pos 0 /**< \brief (SDHC_BGCR) Stop at Block Gap Request */

555

#define SDHC_BGCR_STPBGR (_U_(0x1) << SDHC_BGCR_STPBGR_Pos)

556

#define SDHC_BGCR_STPBGR_TRANSFER_Val _U_(0x0) /**< \brief (SDHC_BGCR) Transfer */

557

#define SDHC_BGCR_STPBGR_STOP_Val _U_(0x1) /**< \brief (SDHC_BGCR) Stop */

558

#define SDHC_BGCR_STPBGR_TRANSFER (SDHC_BGCR_STPBGR_TRANSFER_Val << SDHC_BGCR_STPBGR_Pos)

559

#define SDHC_BGCR_STPBGR_STOP (SDHC_BGCR_STPBGR_STOP_Val << SDHC_BGCR_STPBGR_Pos)

560

#define SDHC_BGCR_CONTR_Pos 1 /**< \brief (SDHC_BGCR) Continue Request */

561

#define SDHC_BGCR_CONTR (_U_(0x1) << SDHC_BGCR_CONTR_Pos)

562

#define SDHC_BGCR_CONTR_GO_ON_Val _U_(0x0) /**< \brief (SDHC_BGCR) Not affected */

563

#define SDHC_BGCR_CONTR_RESTART_Val _U_(0x1) /**< \brief (SDHC_BGCR) Restart */

564

#define SDHC_BGCR_CONTR_GO_ON (SDHC_BGCR_CONTR_GO_ON_Val << SDHC_BGCR_CONTR_Pos)

565

#define SDHC_BGCR_CONTR_RESTART (SDHC_BGCR_CONTR_RESTART_Val << SDHC_BGCR_CONTR_Pos)

566

#define SDHC_BGCR_RWCTRL_Pos 2 /**< \brief (SDHC_BGCR) Read Wait Control */

567

#define SDHC_BGCR_RWCTRL (_U_(0x1) << SDHC_BGCR_RWCTRL_Pos)

568

#define SDHC_BGCR_RWCTRL_DISABLE_Val _U_(0x0) /**< \brief (SDHC_BGCR) Disable Read Wait Control */

569

#define SDHC_BGCR_RWCTRL_ENABLE_Val _U_(0x1) /**< \brief (SDHC_BGCR) Enable Read Wait Control */

570

#define SDHC_BGCR_RWCTRL_DISABLE (SDHC_BGCR_RWCTRL_DISABLE_Val << SDHC_BGCR_RWCTRL_Pos)

571

#define SDHC_BGCR_RWCTRL_ENABLE (SDHC_BGCR_RWCTRL_ENABLE_Val << SDHC_BGCR_RWCTRL_Pos)

572

#define SDHC_BGCR_INTBG_Pos 3 /**< \brief (SDHC_BGCR) Interrupt at Block Gap */

573

#define SDHC_BGCR_INTBG (_U_(0x1) << SDHC_BGCR_INTBG_Pos)

574

#define SDHC_BGCR_INTBG_DISABLED_Val _U_(0x0) /**< \brief (SDHC_BGCR) Disabled */

575

#define SDHC_BGCR_INTBG_ENABLED_Val _U_(0x1) /**< \brief (SDHC_BGCR) Enabled */

576

#define SDHC_BGCR_INTBG_DISABLED (SDHC_BGCR_INTBG_DISABLED_Val << SDHC_BGCR_INTBG_Pos)

577

#define SDHC_BGCR_INTBG_ENABLED (SDHC_BGCR_INTBG_ENABLED_Val << SDHC_BGCR_INTBG_Pos)

578

#define SDHC_BGCR_MASK _U_(0x0F) /**< \brief (SDHC_BGCR) MASK Register */

579

580

// EMMC mode

581

#define SDHC_BGCR_EMMC_STPBGR_Pos 0 /**< \brief (SDHC_BGCR_EMMC) Stop at Block Gap Request */

582

#define SDHC_BGCR_EMMC_STPBGR (_U_(0x1) << SDHC_BGCR_EMMC_STPBGR_Pos)

583

#define SDHC_BGCR_EMMC_STPBGR_TRANSFER_Val _U_(0x0) /**< \brief (SDHC_BGCR_EMMC) Transfer */

584

#define SDHC_BGCR_EMMC_STPBGR_STOP_Val _U_(0x1) /**< \brief (SDHC_BGCR_EMMC) Stop */

585

#define SDHC_BGCR_EMMC_STPBGR_TRANSFER (SDHC_BGCR_EMMC_STPBGR_TRANSFER_Val << SDHC_BGCR_EMMC_STPBGR_Pos)

586

#define SDHC_BGCR_EMMC_STPBGR_STOP (SDHC_BGCR_EMMC_STPBGR_STOP_Val << SDHC_BGCR_EMMC_STPBGR_Pos)

587

#define SDHC_BGCR_EMMC_CONTR_Pos 1 /**< \brief (SDHC_BGCR_EMMC) Continue Request */

588

#define SDHC_BGCR_EMMC_CONTR (_U_(0x1) << SDHC_BGCR_EMMC_CONTR_Pos)

589

#define SDHC_BGCR_EMMC_CONTR_GO_ON_Val _U_(0x0) /**< \brief (SDHC_BGCR_EMMC) Not affected */

590

#define SDHC_BGCR_EMMC_CONTR_RESTART_Val _U_(0x1) /**< \brief (SDHC_BGCR_EMMC) Restart */

591

#define SDHC_BGCR_EMMC_CONTR_GO_ON (SDHC_BGCR_EMMC_CONTR_GO_ON_Val << SDHC_BGCR_EMMC_CONTR_Pos)

592

#define SDHC_BGCR_EMMC_CONTR_RESTART (SDHC_BGCR_EMMC_CONTR_RESTART_Val << SDHC_BGCR_EMMC_CONTR_Pos)

593

#define SDHC_BGCR_EMMC_MASK _U_(0x03) /**< \brief (SDHC_BGCR_EMMC) MASK Register */

594

595

/* -------- SDHC_WCR : (SDHC Offset: 0x02B) (R/W 8) Wakeup Control -------- */

596

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

597

typedef union {

598

struct {

599

uint8_t WKENCINT:1; /*!< bit: 0 Wakeup Event Enable on Card Interrupt */

600

uint8_t WKENCINS:1; /*!< bit: 1 Wakeup Event Enable on Card Insertion */

601

uint8_t WKENCREM:1; /*!< bit: 2 Wakeup Event Enable on Card Removal */

602

uint8_t :5; /*!< bit: 3.. 7 Reserved */

603

} bit; /*!< Structure used for bit access */

604

uint8_t reg; /*!< Type used for register access */

605

} SDHC_WCR_Type;

606

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

607

608

#define SDHC_WCR_OFFSET 0x02B /**< \brief (SDHC_WCR offset) Wakeup Control */

609

#define SDHC_WCR_RESETVALUE _U_(0x00) /**< \brief (SDHC_WCR reset_value) Wakeup Control */

610

611

#define SDHC_WCR_WKENCINT_Pos 0 /**< \brief (SDHC_WCR) Wakeup Event Enable on Card Interrupt */

612

#define SDHC_WCR_WKENCINT (_U_(0x1) << SDHC_WCR_WKENCINT_Pos)

613

#define SDHC_WCR_WKENCINT_DISABLE_Val _U_(0x0) /**< \brief (SDHC_WCR) Disable */

614

#define SDHC_WCR_WKENCINT_ENABLE_Val _U_(0x1) /**< \brief (SDHC_WCR) Enable */

615

#define SDHC_WCR_WKENCINT_DISABLE (SDHC_WCR_WKENCINT_DISABLE_Val << SDHC_WCR_WKENCINT_Pos)

616

#define SDHC_WCR_WKENCINT_ENABLE (SDHC_WCR_WKENCINT_ENABLE_Val << SDHC_WCR_WKENCINT_Pos)

617

#define SDHC_WCR_WKENCINS_Pos 1 /**< \brief (SDHC_WCR) Wakeup Event Enable on Card Insertion */

618

#define SDHC_WCR_WKENCINS (_U_(0x1) << SDHC_WCR_WKENCINS_Pos)

619

#define SDHC_WCR_WKENCINS_DISABLE_Val _U_(0x0) /**< \brief (SDHC_WCR) Disable */

620

#define SDHC_WCR_WKENCINS_ENABLE_Val _U_(0x1) /**< \brief (SDHC_WCR) Enable */

621

#define SDHC_WCR_WKENCINS_DISABLE (SDHC_WCR_WKENCINS_DISABLE_Val << SDHC_WCR_WKENCINS_Pos)

622

#define SDHC_WCR_WKENCINS_ENABLE (SDHC_WCR_WKENCINS_ENABLE_Val << SDHC_WCR_WKENCINS_Pos)

623

#define SDHC_WCR_WKENCREM_Pos 2 /**< \brief (SDHC_WCR) Wakeup Event Enable on Card Removal */

624

#define SDHC_WCR_WKENCREM (_U_(0x1) << SDHC_WCR_WKENCREM_Pos)

625

#define SDHC_WCR_WKENCREM_DISABLE_Val _U_(0x0) /**< \brief (SDHC_WCR) Disable */

626

#define SDHC_WCR_WKENCREM_ENABLE_Val _U_(0x1) /**< \brief (SDHC_WCR) Enable */

627

#define SDHC_WCR_WKENCREM_DISABLE (SDHC_WCR_WKENCREM_DISABLE_Val << SDHC_WCR_WKENCREM_Pos)

628

#define SDHC_WCR_WKENCREM_ENABLE (SDHC_WCR_WKENCREM_ENABLE_Val << SDHC_WCR_WKENCREM_Pos)

629

#define SDHC_WCR_MASK _U_(0x07) /**< \brief (SDHC_WCR) MASK Register */

630

631

/* -------- SDHC_CCR : (SDHC Offset: 0x02C) (R/W 16) Clock Control -------- */

632

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

633

typedef union {

634

struct {

635

uint16_t INTCLKEN:1; /*!< bit: 0 Internal Clock Enable */

636

uint16_t INTCLKS:1; /*!< bit: 1 Internal Clock Stable */

637

uint16_t SDCLKEN:1; /*!< bit: 2 SD Clock Enable */

638

uint16_t :2; /*!< bit: 3.. 4 Reserved */

639

uint16_t CLKGSEL:1; /*!< bit: 5 Clock Generator Select */

640

uint16_t USDCLKFSEL:2; /*!< bit: 6.. 7 Upper Bits of SDCLK Frequency Select */

641

uint16_t SDCLKFSEL:8; /*!< bit: 8..15 SDCLK Frequency Select */

642

} bit; /*!< Structure used for bit access */

643

uint16_t reg; /*!< Type used for register access */

644

} SDHC_CCR_Type;

645

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

646

647

#define SDHC_CCR_OFFSET 0x02C /**< \brief (SDHC_CCR offset) Clock Control */

648

#define SDHC_CCR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_CCR reset_value) Clock Control */

649

650

#define SDHC_CCR_INTCLKEN_Pos 0 /**< \brief (SDHC_CCR) Internal Clock Enable */

651

#define SDHC_CCR_INTCLKEN (_U_(0x1) << SDHC_CCR_INTCLKEN_Pos)

652

#define SDHC_CCR_INTCLKEN_OFF_Val _U_(0x0) /**< \brief (SDHC_CCR) Stop */

653

#define SDHC_CCR_INTCLKEN_ON_Val _U_(0x1) /**< \brief (SDHC_CCR) Oscillate */

654

#define SDHC_CCR_INTCLKEN_OFF (SDHC_CCR_INTCLKEN_OFF_Val << SDHC_CCR_INTCLKEN_Pos)

655

#define SDHC_CCR_INTCLKEN_ON (SDHC_CCR_INTCLKEN_ON_Val << SDHC_CCR_INTCLKEN_Pos)

656

#define SDHC_CCR_INTCLKS_Pos 1 /**< \brief (SDHC_CCR) Internal Clock Stable */

657

#define SDHC_CCR_INTCLKS (_U_(0x1) << SDHC_CCR_INTCLKS_Pos)

658

#define SDHC_CCR_INTCLKS_NOT_READY_Val _U_(0x0) /**< \brief (SDHC_CCR) Not Ready */

659

#define SDHC_CCR_INTCLKS_READY_Val _U_(0x1) /**< \brief (SDHC_CCR) Ready */

660

#define SDHC_CCR_INTCLKS_NOT_READY (SDHC_CCR_INTCLKS_NOT_READY_Val << SDHC_CCR_INTCLKS_Pos)

661

#define SDHC_CCR_INTCLKS_READY (SDHC_CCR_INTCLKS_READY_Val << SDHC_CCR_INTCLKS_Pos)

662

#define SDHC_CCR_SDCLKEN_Pos 2 /**< \brief (SDHC_CCR) SD Clock Enable */

663

#define SDHC_CCR_SDCLKEN (_U_(0x1) << SDHC_CCR_SDCLKEN_Pos)

664

#define SDHC_CCR_SDCLKEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_CCR) Disable */

665

#define SDHC_CCR_SDCLKEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_CCR) Enable */

666

#define SDHC_CCR_SDCLKEN_DISABLE (SDHC_CCR_SDCLKEN_DISABLE_Val << SDHC_CCR_SDCLKEN_Pos)

667

#define SDHC_CCR_SDCLKEN_ENABLE (SDHC_CCR_SDCLKEN_ENABLE_Val << SDHC_CCR_SDCLKEN_Pos)

668

#define SDHC_CCR_CLKGSEL_Pos 5 /**< \brief (SDHC_CCR) Clock Generator Select */

669

#define SDHC_CCR_CLKGSEL (_U_(0x1) << SDHC_CCR_CLKGSEL_Pos)

670

#define SDHC_CCR_CLKGSEL_DIV_Val _U_(0x0) /**< \brief (SDHC_CCR) Divided Clock Mode */

671

#define SDHC_CCR_CLKGSEL_PROG_Val _U_(0x1) /**< \brief (SDHC_CCR) Programmable Clock Mode */

672

#define SDHC_CCR_CLKGSEL_DIV (SDHC_CCR_CLKGSEL_DIV_Val << SDHC_CCR_CLKGSEL_Pos)

673

#define SDHC_CCR_CLKGSEL_PROG (SDHC_CCR_CLKGSEL_PROG_Val << SDHC_CCR_CLKGSEL_Pos)

674

#define SDHC_CCR_USDCLKFSEL_Pos 6 /**< \brief (SDHC_CCR) Upper Bits of SDCLK Frequency Select */

675

#define SDHC_CCR_USDCLKFSEL_Msk (_U_(0x3) << SDHC_CCR_USDCLKFSEL_Pos)

676

#define SDHC_CCR_USDCLKFSEL(value) (SDHC_CCR_USDCLKFSEL_Msk & ((value) << SDHC_CCR_USDCLKFSEL_Pos))

677

#define SDHC_CCR_SDCLKFSEL_Pos 8 /**< \brief (SDHC_CCR) SDCLK Frequency Select */

678

#define SDHC_CCR_SDCLKFSEL_Msk (_U_(0xFF) << SDHC_CCR_SDCLKFSEL_Pos)

679

#define SDHC_CCR_SDCLKFSEL(value) (SDHC_CCR_SDCLKFSEL_Msk & ((value) << SDHC_CCR_SDCLKFSEL_Pos))

680

#define SDHC_CCR_MASK _U_(0xFFE7) /**< \brief (SDHC_CCR) MASK Register */

681

682

/* -------- SDHC_TCR : (SDHC Offset: 0x02E) (R/W 8) Timeout Control -------- */

683

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

684

typedef union {

685

struct {

686

uint8_t DTCVAL:4; /*!< bit: 0.. 3 Data Timeout Counter Value */

687

uint8_t :4; /*!< bit: 4.. 7 Reserved */

688

} bit; /*!< Structure used for bit access */

689

uint8_t reg; /*!< Type used for register access */

690

} SDHC_TCR_Type;

691

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

692

693

#define SDHC_TCR_OFFSET 0x02E /**< \brief (SDHC_TCR offset) Timeout Control */

694

#define SDHC_TCR_RESETVALUE _U_(0x00) /**< \brief (SDHC_TCR reset_value) Timeout Control */

695

696

#define SDHC_TCR_DTCVAL_Pos 0 /**< \brief (SDHC_TCR) Data Timeout Counter Value */

697

#define SDHC_TCR_DTCVAL_Msk (_U_(0xF) << SDHC_TCR_DTCVAL_Pos)

698

#define SDHC_TCR_DTCVAL(value) (SDHC_TCR_DTCVAL_Msk & ((value) << SDHC_TCR_DTCVAL_Pos))

699

#define SDHC_TCR_MASK _U_(0x0F) /**< \brief (SDHC_TCR) MASK Register */

700

701

/* -------- SDHC_SRR : (SDHC Offset: 0x02F) (R/W 8) Software Reset -------- */

702

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

703

typedef union {

704

struct {

705

uint8_t SWRSTALL:1; /*!< bit: 0 Software Reset For All */

706

uint8_t SWRSTCMD:1; /*!< bit: 1 Software Reset For CMD Line */

707

uint8_t SWRSTDAT:1; /*!< bit: 2 Software Reset For DAT Line */

708

uint8_t :5; /*!< bit: 3.. 7 Reserved */

709

} bit; /*!< Structure used for bit access */

710

uint8_t reg; /*!< Type used for register access */

711

} SDHC_SRR_Type;

712

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

713

714

#define SDHC_SRR_OFFSET 0x02F /**< \brief (SDHC_SRR offset) Software Reset */

715

#define SDHC_SRR_RESETVALUE _U_(0x00) /**< \brief (SDHC_SRR reset_value) Software Reset */

716

717

#define SDHC_SRR_SWRSTALL_Pos 0 /**< \brief (SDHC_SRR) Software Reset For All */

718

#define SDHC_SRR_SWRSTALL (_U_(0x1) << SDHC_SRR_SWRSTALL_Pos)

719

#define SDHC_SRR_SWRSTALL_WORK_Val _U_(0x0) /**< \brief (SDHC_SRR) Work */

720

#define SDHC_SRR_SWRSTALL_RESET_Val _U_(0x1) /**< \brief (SDHC_SRR) Reset */

721

#define SDHC_SRR_SWRSTALL_WORK (SDHC_SRR_SWRSTALL_WORK_Val << SDHC_SRR_SWRSTALL_Pos)

722

#define SDHC_SRR_SWRSTALL_RESET (SDHC_SRR_SWRSTALL_RESET_Val << SDHC_SRR_SWRSTALL_Pos)

723

#define SDHC_SRR_SWRSTCMD_Pos 1 /**< \brief (SDHC_SRR) Software Reset For CMD Line */

724

#define SDHC_SRR_SWRSTCMD (_U_(0x1) << SDHC_SRR_SWRSTCMD_Pos)

725

#define SDHC_SRR_SWRSTCMD_WORK_Val _U_(0x0) /**< \brief (SDHC_SRR) Work */

726

#define SDHC_SRR_SWRSTCMD_RESET_Val _U_(0x1) /**< \brief (SDHC_SRR) Reset */

727

#define SDHC_SRR_SWRSTCMD_WORK (SDHC_SRR_SWRSTCMD_WORK_Val << SDHC_SRR_SWRSTCMD_Pos)

728

#define SDHC_SRR_SWRSTCMD_RESET (SDHC_SRR_SWRSTCMD_RESET_Val << SDHC_SRR_SWRSTCMD_Pos)

729

#define SDHC_SRR_SWRSTDAT_Pos 2 /**< \brief (SDHC_SRR) Software Reset For DAT Line */

730

#define SDHC_SRR_SWRSTDAT (_U_(0x1) << SDHC_SRR_SWRSTDAT_Pos)

731

#define SDHC_SRR_SWRSTDAT_WORK_Val _U_(0x0) /**< \brief (SDHC_SRR) Work */

732

#define SDHC_SRR_SWRSTDAT_RESET_Val _U_(0x1) /**< \brief (SDHC_SRR) Reset */

733

#define SDHC_SRR_SWRSTDAT_WORK (SDHC_SRR_SWRSTDAT_WORK_Val << SDHC_SRR_SWRSTDAT_Pos)

734

#define SDHC_SRR_SWRSTDAT_RESET (SDHC_SRR_SWRSTDAT_RESET_Val << SDHC_SRR_SWRSTDAT_Pos)

735

#define SDHC_SRR_MASK _U_(0x07) /**< \brief (SDHC_SRR) MASK Register */

736

737

/* -------- SDHC_NISTR : (SDHC Offset: 0x030) (R/W 16) Normal Interrupt Status -------- */

738

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

739

typedef union {

740

struct {

741

uint16_t CMDC:1; /*!< bit: 0 Command Complete */

742

uint16_t TRFC:1; /*!< bit: 1 Transfer Complete */

743

uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event */

744

uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt */

745

uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready */

746

uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready */

747

uint16_t CINS:1; /*!< bit: 6 Card Insertion */

748

uint16_t CREM:1; /*!< bit: 7 Card Removal */

749

uint16_t CINT:1; /*!< bit: 8 Card Interrupt */

750

uint16_t :6; /*!< bit: 9..14 Reserved */

751

uint16_t ERRINT:1; /*!< bit: 15 Error Interrupt */

752

} bit; /*!< Structure used for bit access */

753

struct { // EMMC mode

754

uint16_t CMDC:1; /*!< bit: 0 Command Complete */

755

uint16_t TRFC:1; /*!< bit: 1 Transfer Complete */

756

uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event */

757

uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt */

758

uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready */

759

uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready */

760

uint16_t :8; /*!< bit: 6..13 Reserved */

761

uint16_t BOOTAR:1; /*!< bit: 14 Boot Acknowledge Received */

762

uint16_t ERRINT:1; /*!< bit: 15 Error Interrupt */

763

} EMMC; /*!< Structure used for EMMC */

764

uint16_t reg; /*!< Type used for register access */

765

} SDHC_NISTR_Type;

766

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

767

768

#define SDHC_NISTR_OFFSET 0x030 /**< \brief (SDHC_NISTR offset) Normal Interrupt Status */

769

#define SDHC_NISTR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_NISTR reset_value) Normal Interrupt Status */

770

771

#define SDHC_NISTR_CMDC_Pos 0 /**< \brief (SDHC_NISTR) Command Complete */

772

#define SDHC_NISTR_CMDC (_U_(0x1) << SDHC_NISTR_CMDC_Pos)

773

#define SDHC_NISTR_CMDC_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) No command complete */

774

#define SDHC_NISTR_CMDC_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Command complete */

775

#define SDHC_NISTR_CMDC_NO (SDHC_NISTR_CMDC_NO_Val << SDHC_NISTR_CMDC_Pos)

776

#define SDHC_NISTR_CMDC_YES (SDHC_NISTR_CMDC_YES_Val << SDHC_NISTR_CMDC_Pos)

777

#define SDHC_NISTR_TRFC_Pos 1 /**< \brief (SDHC_NISTR) Transfer Complete */

778

#define SDHC_NISTR_TRFC (_U_(0x1) << SDHC_NISTR_TRFC_Pos)

779

#define SDHC_NISTR_TRFC_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) Not complete */

780

#define SDHC_NISTR_TRFC_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Command execution is completed */

781

#define SDHC_NISTR_TRFC_NO (SDHC_NISTR_TRFC_NO_Val << SDHC_NISTR_TRFC_Pos)

782

#define SDHC_NISTR_TRFC_YES (SDHC_NISTR_TRFC_YES_Val << SDHC_NISTR_TRFC_Pos)

783

#define SDHC_NISTR_BLKGE_Pos 2 /**< \brief (SDHC_NISTR) Block Gap Event */

784

#define SDHC_NISTR_BLKGE (_U_(0x1) << SDHC_NISTR_BLKGE_Pos)

785

#define SDHC_NISTR_BLKGE_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) No Block Gap Event */

786

#define SDHC_NISTR_BLKGE_STOP_Val _U_(0x1) /**< \brief (SDHC_NISTR) Transaction stopped at block gap */

787

#define SDHC_NISTR_BLKGE_NO (SDHC_NISTR_BLKGE_NO_Val << SDHC_NISTR_BLKGE_Pos)

788

#define SDHC_NISTR_BLKGE_STOP (SDHC_NISTR_BLKGE_STOP_Val << SDHC_NISTR_BLKGE_Pos)

789

#define SDHC_NISTR_DMAINT_Pos 3 /**< \brief (SDHC_NISTR) DMA Interrupt */

790

#define SDHC_NISTR_DMAINT (_U_(0x1) << SDHC_NISTR_DMAINT_Pos)

791

#define SDHC_NISTR_DMAINT_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) No DMA Interrupt */

792

#define SDHC_NISTR_DMAINT_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) DMA Interrupt is generated */

793

#define SDHC_NISTR_DMAINT_NO (SDHC_NISTR_DMAINT_NO_Val << SDHC_NISTR_DMAINT_Pos)

794

#define SDHC_NISTR_DMAINT_YES (SDHC_NISTR_DMAINT_YES_Val << SDHC_NISTR_DMAINT_Pos)

795

#define SDHC_NISTR_BWRRDY_Pos 4 /**< \brief (SDHC_NISTR) Buffer Write Ready */

796

#define SDHC_NISTR_BWRRDY (_U_(0x1) << SDHC_NISTR_BWRRDY_Pos)

797

#define SDHC_NISTR_BWRRDY_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) Not ready to write buffer */

798

#define SDHC_NISTR_BWRRDY_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Ready to write buffer */

799

#define SDHC_NISTR_BWRRDY_NO (SDHC_NISTR_BWRRDY_NO_Val << SDHC_NISTR_BWRRDY_Pos)

800

#define SDHC_NISTR_BWRRDY_YES (SDHC_NISTR_BWRRDY_YES_Val << SDHC_NISTR_BWRRDY_Pos)

801

#define SDHC_NISTR_BRDRDY_Pos 5 /**< \brief (SDHC_NISTR) Buffer Read Ready */

802

#define SDHC_NISTR_BRDRDY (_U_(0x1) << SDHC_NISTR_BRDRDY_Pos)

803

#define SDHC_NISTR_BRDRDY_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) Not ready to read buffer */

804

#define SDHC_NISTR_BRDRDY_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Ready to read buffer */

805

#define SDHC_NISTR_BRDRDY_NO (SDHC_NISTR_BRDRDY_NO_Val << SDHC_NISTR_BRDRDY_Pos)

806

#define SDHC_NISTR_BRDRDY_YES (SDHC_NISTR_BRDRDY_YES_Val << SDHC_NISTR_BRDRDY_Pos)

807

#define SDHC_NISTR_CINS_Pos 6 /**< \brief (SDHC_NISTR) Card Insertion */

808

#define SDHC_NISTR_CINS (_U_(0x1) << SDHC_NISTR_CINS_Pos)

809

#define SDHC_NISTR_CINS_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) Card state stable or Debouncing */

810

#define SDHC_NISTR_CINS_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Card inserted */

811

#define SDHC_NISTR_CINS_NO (SDHC_NISTR_CINS_NO_Val << SDHC_NISTR_CINS_Pos)

812

#define SDHC_NISTR_CINS_YES (SDHC_NISTR_CINS_YES_Val << SDHC_NISTR_CINS_Pos)

813

#define SDHC_NISTR_CREM_Pos 7 /**< \brief (SDHC_NISTR) Card Removal */

814

#define SDHC_NISTR_CREM (_U_(0x1) << SDHC_NISTR_CREM_Pos)

815

#define SDHC_NISTR_CREM_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) Card state stable or Debouncing */

816

#define SDHC_NISTR_CREM_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Card Removed */

817

#define SDHC_NISTR_CREM_NO (SDHC_NISTR_CREM_NO_Val << SDHC_NISTR_CREM_Pos)

818

#define SDHC_NISTR_CREM_YES (SDHC_NISTR_CREM_YES_Val << SDHC_NISTR_CREM_Pos)

819

#define SDHC_NISTR_CINT_Pos 8 /**< \brief (SDHC_NISTR) Card Interrupt */

820

#define SDHC_NISTR_CINT (_U_(0x1) << SDHC_NISTR_CINT_Pos)

821

#define SDHC_NISTR_CINT_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) No Card Interrupt */

822

#define SDHC_NISTR_CINT_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Generate Card Interrupt */

823

#define SDHC_NISTR_CINT_NO (SDHC_NISTR_CINT_NO_Val << SDHC_NISTR_CINT_Pos)

824

#define SDHC_NISTR_CINT_YES (SDHC_NISTR_CINT_YES_Val << SDHC_NISTR_CINT_Pos)

825

#define SDHC_NISTR_ERRINT_Pos 15 /**< \brief (SDHC_NISTR) Error Interrupt */

826

#define SDHC_NISTR_ERRINT (_U_(0x1) << SDHC_NISTR_ERRINT_Pos)

827

#define SDHC_NISTR_ERRINT_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR) No Error */

828

#define SDHC_NISTR_ERRINT_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR) Error */

829

#define SDHC_NISTR_ERRINT_NO (SDHC_NISTR_ERRINT_NO_Val << SDHC_NISTR_ERRINT_Pos)

830

#define SDHC_NISTR_ERRINT_YES (SDHC_NISTR_ERRINT_YES_Val << SDHC_NISTR_ERRINT_Pos)

831

#define SDHC_NISTR_MASK _U_(0x81FF) /**< \brief (SDHC_NISTR) MASK Register */

832

833

// EMMC mode

834

#define SDHC_NISTR_EMMC_CMDC_Pos 0 /**< \brief (SDHC_NISTR_EMMC) Command Complete */

835

#define SDHC_NISTR_EMMC_CMDC (_U_(0x1) << SDHC_NISTR_EMMC_CMDC_Pos)

836

#define SDHC_NISTR_EMMC_CMDC_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR_EMMC) No command complete */

837

#define SDHC_NISTR_EMMC_CMDC_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR_EMMC) Command complete */

838

#define SDHC_NISTR_EMMC_CMDC_NO (SDHC_NISTR_EMMC_CMDC_NO_Val << SDHC_NISTR_EMMC_CMDC_Pos)

839

#define SDHC_NISTR_EMMC_CMDC_YES (SDHC_NISTR_EMMC_CMDC_YES_Val << SDHC_NISTR_EMMC_CMDC_Pos)

840

#define SDHC_NISTR_EMMC_TRFC_Pos 1 /**< \brief (SDHC_NISTR_EMMC) Transfer Complete */

841

#define SDHC_NISTR_EMMC_TRFC (_U_(0x1) << SDHC_NISTR_EMMC_TRFC_Pos)

842

#define SDHC_NISTR_EMMC_TRFC_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR_EMMC) Not complete */

843

#define SDHC_NISTR_EMMC_TRFC_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR_EMMC) Command execution is completed */

844

#define SDHC_NISTR_EMMC_TRFC_NO (SDHC_NISTR_EMMC_TRFC_NO_Val << SDHC_NISTR_EMMC_TRFC_Pos)

845

#define SDHC_NISTR_EMMC_TRFC_YES (SDHC_NISTR_EMMC_TRFC_YES_Val << SDHC_NISTR_EMMC_TRFC_Pos)

846

#define SDHC_NISTR_EMMC_BLKGE_Pos 2 /**< \brief (SDHC_NISTR_EMMC) Block Gap Event */

847

#define SDHC_NISTR_EMMC_BLKGE (_U_(0x1) << SDHC_NISTR_EMMC_BLKGE_Pos)

848

#define SDHC_NISTR_EMMC_BLKGE_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR_EMMC) No Block Gap Event */

849

#define SDHC_NISTR_EMMC_BLKGE_STOP_Val _U_(0x1) /**< \brief (SDHC_NISTR_EMMC) Transaction stopped at block gap */

850

#define SDHC_NISTR_EMMC_BLKGE_NO (SDHC_NISTR_EMMC_BLKGE_NO_Val << SDHC_NISTR_EMMC_BLKGE_Pos)

851

#define SDHC_NISTR_EMMC_BLKGE_STOP (SDHC_NISTR_EMMC_BLKGE_STOP_Val << SDHC_NISTR_EMMC_BLKGE_Pos)

852

#define SDHC_NISTR_EMMC_DMAINT_Pos 3 /**< \brief (SDHC_NISTR_EMMC) DMA Interrupt */

853

#define SDHC_NISTR_EMMC_DMAINT (_U_(0x1) << SDHC_NISTR_EMMC_DMAINT_Pos)

854

#define SDHC_NISTR_EMMC_DMAINT_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR_EMMC) No DMA Interrupt */

855

#define SDHC_NISTR_EMMC_DMAINT_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR_EMMC) DMA Interrupt is generated */

856

#define SDHC_NISTR_EMMC_DMAINT_NO (SDHC_NISTR_EMMC_DMAINT_NO_Val << SDHC_NISTR_EMMC_DMAINT_Pos)

857

#define SDHC_NISTR_EMMC_DMAINT_YES (SDHC_NISTR_EMMC_DMAINT_YES_Val << SDHC_NISTR_EMMC_DMAINT_Pos)

858

#define SDHC_NISTR_EMMC_BWRRDY_Pos 4 /**< \brief (SDHC_NISTR_EMMC) Buffer Write Ready */

859

#define SDHC_NISTR_EMMC_BWRRDY (_U_(0x1) << SDHC_NISTR_EMMC_BWRRDY_Pos)

860

#define SDHC_NISTR_EMMC_BWRRDY_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR_EMMC) Not ready to write buffer */

861

#define SDHC_NISTR_EMMC_BWRRDY_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR_EMMC) Ready to write buffer */

862

#define SDHC_NISTR_EMMC_BWRRDY_NO (SDHC_NISTR_EMMC_BWRRDY_NO_Val << SDHC_NISTR_EMMC_BWRRDY_Pos)

863

#define SDHC_NISTR_EMMC_BWRRDY_YES (SDHC_NISTR_EMMC_BWRRDY_YES_Val << SDHC_NISTR_EMMC_BWRRDY_Pos)

864

#define SDHC_NISTR_EMMC_BRDRDY_Pos 5 /**< \brief (SDHC_NISTR_EMMC) Buffer Read Ready */

865

#define SDHC_NISTR_EMMC_BRDRDY (_U_(0x1) << SDHC_NISTR_EMMC_BRDRDY_Pos)

866

#define SDHC_NISTR_EMMC_BRDRDY_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR_EMMC) Not ready to read buffer */

867

#define SDHC_NISTR_EMMC_BRDRDY_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR_EMMC) Ready to read buffer */

868

#define SDHC_NISTR_EMMC_BRDRDY_NO (SDHC_NISTR_EMMC_BRDRDY_NO_Val << SDHC_NISTR_EMMC_BRDRDY_Pos)

869

#define SDHC_NISTR_EMMC_BRDRDY_YES (SDHC_NISTR_EMMC_BRDRDY_YES_Val << SDHC_NISTR_EMMC_BRDRDY_Pos)

870

#define SDHC_NISTR_EMMC_BOOTAR_Pos 14 /**< \brief (SDHC_NISTR_EMMC) Boot Acknowledge Received */

871

#define SDHC_NISTR_EMMC_BOOTAR (_U_(0x1) << SDHC_NISTR_EMMC_BOOTAR_Pos)

872

#define SDHC_NISTR_EMMC_ERRINT_Pos 15 /**< \brief (SDHC_NISTR_EMMC) Error Interrupt */

873

#define SDHC_NISTR_EMMC_ERRINT (_U_(0x1) << SDHC_NISTR_EMMC_ERRINT_Pos)

874

#define SDHC_NISTR_EMMC_ERRINT_NO_Val _U_(0x0) /**< \brief (SDHC_NISTR_EMMC) No Error */

875

#define SDHC_NISTR_EMMC_ERRINT_YES_Val _U_(0x1) /**< \brief (SDHC_NISTR_EMMC) Error */

876

#define SDHC_NISTR_EMMC_ERRINT_NO (SDHC_NISTR_EMMC_ERRINT_NO_Val << SDHC_NISTR_EMMC_ERRINT_Pos)

877

#define SDHC_NISTR_EMMC_ERRINT_YES (SDHC_NISTR_EMMC_ERRINT_YES_Val << SDHC_NISTR_EMMC_ERRINT_Pos)

878

#define SDHC_NISTR_EMMC_MASK _U_(0xC03F) /**< \brief (SDHC_NISTR_EMMC) MASK Register */

879

880

/* -------- SDHC_EISTR : (SDHC Offset: 0x032) (R/W 16) Error Interrupt Status -------- */

881

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

882

typedef union {

883

struct {

884

uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error */

885

uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error */

886

uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error */

887

uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error */

888

uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error */

889

uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error */

890

uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error */

891

uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error */

892

uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error */

893

uint16_t ADMA:1; /*!< bit: 9 ADMA Error */

894

uint16_t :6; /*!< bit: 10..15 Reserved */

895

} bit; /*!< Structure used for bit access */

896

struct { // EMMC mode

897

uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error */

898

uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error */

899

uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error */

900

uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error */

901

uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error */

902

uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error */

903

uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error */

904

uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error */

905

uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error */

906

uint16_t ADMA:1; /*!< bit: 9 ADMA Error */

907

uint16_t :2; /*!< bit: 10..11 Reserved */

908

uint16_t BOOTAE:1; /*!< bit: 12 Boot Acknowledge Error */

909

uint16_t :3; /*!< bit: 13..15 Reserved */

910

} EMMC; /*!< Structure used for EMMC */

911

uint16_t reg; /*!< Type used for register access */

912

} SDHC_EISTR_Type;

913

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

914

915

#define SDHC_EISTR_OFFSET 0x032 /**< \brief (SDHC_EISTR offset) Error Interrupt Status */

916

#define SDHC_EISTR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_EISTR reset_value) Error Interrupt Status */

917

918

#define SDHC_EISTR_CMDTEO_Pos 0 /**< \brief (SDHC_EISTR) Command Timeout Error */

919

#define SDHC_EISTR_CMDTEO (_U_(0x1) << SDHC_EISTR_CMDTEO_Pos)

920

#define SDHC_EISTR_CMDTEO_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */

921

#define SDHC_EISTR_CMDTEO_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Timeout */

922

#define SDHC_EISTR_CMDTEO_NO (SDHC_EISTR_CMDTEO_NO_Val << SDHC_EISTR_CMDTEO_Pos)

923

#define SDHC_EISTR_CMDTEO_YES (SDHC_EISTR_CMDTEO_YES_Val << SDHC_EISTR_CMDTEO_Pos)

924

#define SDHC_EISTR_CMDCRC_Pos 1 /**< \brief (SDHC_EISTR) Command CRC Error */

925

#define SDHC_EISTR_CMDCRC (_U_(0x1) << SDHC_EISTR_CMDCRC_Pos)

926

#define SDHC_EISTR_CMDCRC_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */

927

#define SDHC_EISTR_CMDCRC_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) CRC Error Generated */

928

#define SDHC_EISTR_CMDCRC_NO (SDHC_EISTR_CMDCRC_NO_Val << SDHC_EISTR_CMDCRC_Pos)

929

#define SDHC_EISTR_CMDCRC_YES (SDHC_EISTR_CMDCRC_YES_Val << SDHC_EISTR_CMDCRC_Pos)

930

#define SDHC_EISTR_CMDEND_Pos 2 /**< \brief (SDHC_EISTR) Command End Bit Error */

931

#define SDHC_EISTR_CMDEND (_U_(0x1) << SDHC_EISTR_CMDEND_Pos)

932

#define SDHC_EISTR_CMDEND_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No error */

933

#define SDHC_EISTR_CMDEND_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) End Bit Error Generated */

934

#define SDHC_EISTR_CMDEND_NO (SDHC_EISTR_CMDEND_NO_Val << SDHC_EISTR_CMDEND_Pos)

935

#define SDHC_EISTR_CMDEND_YES (SDHC_EISTR_CMDEND_YES_Val << SDHC_EISTR_CMDEND_Pos)

936

#define SDHC_EISTR_CMDIDX_Pos 3 /**< \brief (SDHC_EISTR) Command Index Error */

937

#define SDHC_EISTR_CMDIDX (_U_(0x1) << SDHC_EISTR_CMDIDX_Pos)

938

#define SDHC_EISTR_CMDIDX_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */

939

#define SDHC_EISTR_CMDIDX_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Error */

940

#define SDHC_EISTR_CMDIDX_NO (SDHC_EISTR_CMDIDX_NO_Val << SDHC_EISTR_CMDIDX_Pos)

941

#define SDHC_EISTR_CMDIDX_YES (SDHC_EISTR_CMDIDX_YES_Val << SDHC_EISTR_CMDIDX_Pos)

942

#define SDHC_EISTR_DATTEO_Pos 4 /**< \brief (SDHC_EISTR) Data Timeout Error */

943

#define SDHC_EISTR_DATTEO (_U_(0x1) << SDHC_EISTR_DATTEO_Pos)

944

#define SDHC_EISTR_DATTEO_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */

945

#define SDHC_EISTR_DATTEO_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Timeout */

946

#define SDHC_EISTR_DATTEO_NO (SDHC_EISTR_DATTEO_NO_Val << SDHC_EISTR_DATTEO_Pos)

947

#define SDHC_EISTR_DATTEO_YES (SDHC_EISTR_DATTEO_YES_Val << SDHC_EISTR_DATTEO_Pos)

948

#define SDHC_EISTR_DATCRC_Pos 5 /**< \brief (SDHC_EISTR) Data CRC Error */

949

#define SDHC_EISTR_DATCRC (_U_(0x1) << SDHC_EISTR_DATCRC_Pos)

950

#define SDHC_EISTR_DATCRC_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */

951

#define SDHC_EISTR_DATCRC_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Error */

952

#define SDHC_EISTR_DATCRC_NO (SDHC_EISTR_DATCRC_NO_Val << SDHC_EISTR_DATCRC_Pos)

953

#define SDHC_EISTR_DATCRC_YES (SDHC_EISTR_DATCRC_YES_Val << SDHC_EISTR_DATCRC_Pos)

954

#define SDHC_EISTR_DATEND_Pos 6 /**< \brief (SDHC_EISTR) Data End Bit Error */

955

#define SDHC_EISTR_DATEND (_U_(0x1) << SDHC_EISTR_DATEND_Pos)

956

#define SDHC_EISTR_DATEND_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */

957

#define SDHC_EISTR_DATEND_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Error */

958

#define SDHC_EISTR_DATEND_NO (SDHC_EISTR_DATEND_NO_Val << SDHC_EISTR_DATEND_Pos)

959

#define SDHC_EISTR_DATEND_YES (SDHC_EISTR_DATEND_YES_Val << SDHC_EISTR_DATEND_Pos)

960

#define SDHC_EISTR_CURLIM_Pos 7 /**< \brief (SDHC_EISTR) Current Limit Error */

961

#define SDHC_EISTR_CURLIM (_U_(0x1) << SDHC_EISTR_CURLIM_Pos)

962

#define SDHC_EISTR_CURLIM_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */

963

#define SDHC_EISTR_CURLIM_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Power Fail */

964

#define SDHC_EISTR_CURLIM_NO (SDHC_EISTR_CURLIM_NO_Val << SDHC_EISTR_CURLIM_Pos)

965

#define SDHC_EISTR_CURLIM_YES (SDHC_EISTR_CURLIM_YES_Val << SDHC_EISTR_CURLIM_Pos)

966

#define SDHC_EISTR_ACMD_Pos 8 /**< \brief (SDHC_EISTR) Auto CMD Error */

967

#define SDHC_EISTR_ACMD (_U_(0x1) << SDHC_EISTR_ACMD_Pos)

968

#define SDHC_EISTR_ACMD_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */

969

#define SDHC_EISTR_ACMD_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Error */

970

#define SDHC_EISTR_ACMD_NO (SDHC_EISTR_ACMD_NO_Val << SDHC_EISTR_ACMD_Pos)

971

#define SDHC_EISTR_ACMD_YES (SDHC_EISTR_ACMD_YES_Val << SDHC_EISTR_ACMD_Pos)

972

#define SDHC_EISTR_ADMA_Pos 9 /**< \brief (SDHC_EISTR) ADMA Error */

973

#define SDHC_EISTR_ADMA (_U_(0x1) << SDHC_EISTR_ADMA_Pos)

974

#define SDHC_EISTR_ADMA_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR) No Error */

975

#define SDHC_EISTR_ADMA_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR) Error */

976

#define SDHC_EISTR_ADMA_NO (SDHC_EISTR_ADMA_NO_Val << SDHC_EISTR_ADMA_Pos)

977

#define SDHC_EISTR_ADMA_YES (SDHC_EISTR_ADMA_YES_Val << SDHC_EISTR_ADMA_Pos)

978

#define SDHC_EISTR_MASK _U_(0x03FF) /**< \brief (SDHC_EISTR) MASK Register */

979

980

// EMMC mode

981

#define SDHC_EISTR_EMMC_CMDTEO_Pos 0 /**< \brief (SDHC_EISTR_EMMC) Command Timeout Error */

982

#define SDHC_EISTR_EMMC_CMDTEO (_U_(0x1) << SDHC_EISTR_EMMC_CMDTEO_Pos)

983

#define SDHC_EISTR_EMMC_CMDTEO_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */

984

#define SDHC_EISTR_EMMC_CMDTEO_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Timeout */

985

#define SDHC_EISTR_EMMC_CMDTEO_NO (SDHC_EISTR_EMMC_CMDTEO_NO_Val << SDHC_EISTR_EMMC_CMDTEO_Pos)

986

#define SDHC_EISTR_EMMC_CMDTEO_YES (SDHC_EISTR_EMMC_CMDTEO_YES_Val << SDHC_EISTR_EMMC_CMDTEO_Pos)

987

#define SDHC_EISTR_EMMC_CMDCRC_Pos 1 /**< \brief (SDHC_EISTR_EMMC) Command CRC Error */

988

#define SDHC_EISTR_EMMC_CMDCRC (_U_(0x1) << SDHC_EISTR_EMMC_CMDCRC_Pos)

989

#define SDHC_EISTR_EMMC_CMDCRC_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */

990

#define SDHC_EISTR_EMMC_CMDCRC_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) CRC Error Generated */

991

#define SDHC_EISTR_EMMC_CMDCRC_NO (SDHC_EISTR_EMMC_CMDCRC_NO_Val << SDHC_EISTR_EMMC_CMDCRC_Pos)

992

#define SDHC_EISTR_EMMC_CMDCRC_YES (SDHC_EISTR_EMMC_CMDCRC_YES_Val << SDHC_EISTR_EMMC_CMDCRC_Pos)

993

#define SDHC_EISTR_EMMC_CMDEND_Pos 2 /**< \brief (SDHC_EISTR_EMMC) Command End Bit Error */

994

#define SDHC_EISTR_EMMC_CMDEND (_U_(0x1) << SDHC_EISTR_EMMC_CMDEND_Pos)

995

#define SDHC_EISTR_EMMC_CMDEND_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No error */

996

#define SDHC_EISTR_EMMC_CMDEND_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) End Bit Error Generated */

997

#define SDHC_EISTR_EMMC_CMDEND_NO (SDHC_EISTR_EMMC_CMDEND_NO_Val << SDHC_EISTR_EMMC_CMDEND_Pos)

998

#define SDHC_EISTR_EMMC_CMDEND_YES (SDHC_EISTR_EMMC_CMDEND_YES_Val << SDHC_EISTR_EMMC_CMDEND_Pos)

999

#define SDHC_EISTR_EMMC_CMDIDX_Pos 3 /**< \brief (SDHC_EISTR_EMMC) Command Index Error */

1000

#define SDHC_EISTR_EMMC_CMDIDX (_U_(0x1) << SDHC_EISTR_EMMC_CMDIDX_Pos)

1001

#define SDHC_EISTR_EMMC_CMDIDX_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */

1002

#define SDHC_EISTR_EMMC_CMDIDX_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Error */

1003

#define SDHC_EISTR_EMMC_CMDIDX_NO (SDHC_EISTR_EMMC_CMDIDX_NO_Val << SDHC_EISTR_EMMC_CMDIDX_Pos)

1004

#define SDHC_EISTR_EMMC_CMDIDX_YES (SDHC_EISTR_EMMC_CMDIDX_YES_Val << SDHC_EISTR_EMMC_CMDIDX_Pos)

1005

#define SDHC_EISTR_EMMC_DATTEO_Pos 4 /**< \brief (SDHC_EISTR_EMMC) Data Timeout Error */

1006

#define SDHC_EISTR_EMMC_DATTEO (_U_(0x1) << SDHC_EISTR_EMMC_DATTEO_Pos)

1007

#define SDHC_EISTR_EMMC_DATTEO_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */

1008

#define SDHC_EISTR_EMMC_DATTEO_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Timeout */

1009

#define SDHC_EISTR_EMMC_DATTEO_NO (SDHC_EISTR_EMMC_DATTEO_NO_Val << SDHC_EISTR_EMMC_DATTEO_Pos)

1010

#define SDHC_EISTR_EMMC_DATTEO_YES (SDHC_EISTR_EMMC_DATTEO_YES_Val << SDHC_EISTR_EMMC_DATTEO_Pos)

1011

#define SDHC_EISTR_EMMC_DATCRC_Pos 5 /**< \brief (SDHC_EISTR_EMMC) Data CRC Error */

1012

#define SDHC_EISTR_EMMC_DATCRC (_U_(0x1) << SDHC_EISTR_EMMC_DATCRC_Pos)

1013

#define SDHC_EISTR_EMMC_DATCRC_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */

1014

#define SDHC_EISTR_EMMC_DATCRC_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Error */

1015

#define SDHC_EISTR_EMMC_DATCRC_NO (SDHC_EISTR_EMMC_DATCRC_NO_Val << SDHC_EISTR_EMMC_DATCRC_Pos)

1016

#define SDHC_EISTR_EMMC_DATCRC_YES (SDHC_EISTR_EMMC_DATCRC_YES_Val << SDHC_EISTR_EMMC_DATCRC_Pos)

1017

#define SDHC_EISTR_EMMC_DATEND_Pos 6 /**< \brief (SDHC_EISTR_EMMC) Data End Bit Error */

1018

#define SDHC_EISTR_EMMC_DATEND (_U_(0x1) << SDHC_EISTR_EMMC_DATEND_Pos)

1019

#define SDHC_EISTR_EMMC_DATEND_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */

1020

#define SDHC_EISTR_EMMC_DATEND_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Error */

1021

#define SDHC_EISTR_EMMC_DATEND_NO (SDHC_EISTR_EMMC_DATEND_NO_Val << SDHC_EISTR_EMMC_DATEND_Pos)

1022

#define SDHC_EISTR_EMMC_DATEND_YES (SDHC_EISTR_EMMC_DATEND_YES_Val << SDHC_EISTR_EMMC_DATEND_Pos)

1023

#define SDHC_EISTR_EMMC_CURLIM_Pos 7 /**< \brief (SDHC_EISTR_EMMC) Current Limit Error */

1024

#define SDHC_EISTR_EMMC_CURLIM (_U_(0x1) << SDHC_EISTR_EMMC_CURLIM_Pos)

1025

#define SDHC_EISTR_EMMC_CURLIM_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */

1026

#define SDHC_EISTR_EMMC_CURLIM_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Power Fail */

1027

#define SDHC_EISTR_EMMC_CURLIM_NO (SDHC_EISTR_EMMC_CURLIM_NO_Val << SDHC_EISTR_EMMC_CURLIM_Pos)

1028

#define SDHC_EISTR_EMMC_CURLIM_YES (SDHC_EISTR_EMMC_CURLIM_YES_Val << SDHC_EISTR_EMMC_CURLIM_Pos)

1029

#define SDHC_EISTR_EMMC_ACMD_Pos 8 /**< \brief (SDHC_EISTR_EMMC) Auto CMD Error */

1030

#define SDHC_EISTR_EMMC_ACMD (_U_(0x1) << SDHC_EISTR_EMMC_ACMD_Pos)

1031

#define SDHC_EISTR_EMMC_ACMD_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */

1032

#define SDHC_EISTR_EMMC_ACMD_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Error */

1033

#define SDHC_EISTR_EMMC_ACMD_NO (SDHC_EISTR_EMMC_ACMD_NO_Val << SDHC_EISTR_EMMC_ACMD_Pos)

1034

#define SDHC_EISTR_EMMC_ACMD_YES (SDHC_EISTR_EMMC_ACMD_YES_Val << SDHC_EISTR_EMMC_ACMD_Pos)

1035

#define SDHC_EISTR_EMMC_ADMA_Pos 9 /**< \brief (SDHC_EISTR_EMMC) ADMA Error */

1036

#define SDHC_EISTR_EMMC_ADMA (_U_(0x1) << SDHC_EISTR_EMMC_ADMA_Pos)

1037

#define SDHC_EISTR_EMMC_ADMA_NO_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) No Error */

1038

#define SDHC_EISTR_EMMC_ADMA_YES_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) Error */

1039

#define SDHC_EISTR_EMMC_ADMA_NO (SDHC_EISTR_EMMC_ADMA_NO_Val << SDHC_EISTR_EMMC_ADMA_Pos)

1040

#define SDHC_EISTR_EMMC_ADMA_YES (SDHC_EISTR_EMMC_ADMA_YES_Val << SDHC_EISTR_EMMC_ADMA_Pos)

1041

#define SDHC_EISTR_EMMC_BOOTAE_Pos 12 /**< \brief (SDHC_EISTR_EMMC) Boot Acknowledge Error */

1042

#define SDHC_EISTR_EMMC_BOOTAE (_U_(0x1) << SDHC_EISTR_EMMC_BOOTAE_Pos)

1043

#define SDHC_EISTR_EMMC_BOOTAE_0_Val _U_(0x0) /**< \brief (SDHC_EISTR_EMMC) FIFO contains at least one byte */

1044

#define SDHC_EISTR_EMMC_BOOTAE_1_Val _U_(0x1) /**< \brief (SDHC_EISTR_EMMC) FIFO is empty */

1045

#define SDHC_EISTR_EMMC_BOOTAE_0 (SDHC_EISTR_EMMC_BOOTAE_0_Val << SDHC_EISTR_EMMC_BOOTAE_Pos)

1046

#define SDHC_EISTR_EMMC_BOOTAE_1 (SDHC_EISTR_EMMC_BOOTAE_1_Val << SDHC_EISTR_EMMC_BOOTAE_Pos)

1047

#define SDHC_EISTR_EMMC_MASK _U_(0x13FF) /**< \brief (SDHC_EISTR_EMMC) MASK Register */

1048

1049

/* -------- SDHC_NISTER : (SDHC Offset: 0x034) (R/W 16) Normal Interrupt Status Enable -------- */

1050

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

1051

typedef union {

1052

struct {

1053

uint16_t CMDC:1; /*!< bit: 0 Command Complete Status Enable */

1054

uint16_t TRFC:1; /*!< bit: 1 Transfer Complete Status Enable */

1055

uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event Status Enable */

1056

uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt Status Enable */

1057

uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready Status Enable */

1058

uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready Status Enable */

1059

uint16_t CINS:1; /*!< bit: 6 Card Insertion Status Enable */

1060

uint16_t CREM:1; /*!< bit: 7 Card Removal Status Enable */

1061

uint16_t CINT:1; /*!< bit: 8 Card Interrupt Status Enable */

1062

uint16_t :7; /*!< bit: 9..15 Reserved */

1063

} bit; /*!< Structure used for bit access */

1064

struct { // EMMC mode

1065

uint16_t CMDC:1; /*!< bit: 0 Command Complete Status Enable */

1066

uint16_t TRFC:1; /*!< bit: 1 Transfer Complete Status Enable */

1067

uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event Status Enable */

1068

uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt Status Enable */

1069

uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready Status Enable */

1070

uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready Status Enable */

1071

uint16_t :8; /*!< bit: 6..13 Reserved */

1072

uint16_t BOOTAR:1; /*!< bit: 14 Boot Acknowledge Received Status Enable */

1073

uint16_t :1; /*!< bit: 15 Reserved */

1074

} EMMC; /*!< Structure used for EMMC */

1075

uint16_t reg; /*!< Type used for register access */

1076

} SDHC_NISTER_Type;

1077

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

1078

1079

#define SDHC_NISTER_OFFSET 0x034 /**< \brief (SDHC_NISTER offset) Normal Interrupt Status Enable */

1080

#define SDHC_NISTER_RESETVALUE _U_(0x0000) /**< \brief (SDHC_NISTER reset_value) Normal Interrupt Status Enable */

1081

1082

#define SDHC_NISTER_CMDC_Pos 0 /**< \brief (SDHC_NISTER) Command Complete Status Enable */

1083

#define SDHC_NISTER_CMDC (_U_(0x1) << SDHC_NISTER_CMDC_Pos)

1084

#define SDHC_NISTER_CMDC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */

1085

#define SDHC_NISTER_CMDC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */

1086

#define SDHC_NISTER_CMDC_MASKED (SDHC_NISTER_CMDC_MASKED_Val << SDHC_NISTER_CMDC_Pos)

1087

#define SDHC_NISTER_CMDC_ENABLED (SDHC_NISTER_CMDC_ENABLED_Val << SDHC_NISTER_CMDC_Pos)

1088

#define SDHC_NISTER_TRFC_Pos 1 /**< \brief (SDHC_NISTER) Transfer Complete Status Enable */

1089

#define SDHC_NISTER_TRFC (_U_(0x1) << SDHC_NISTER_TRFC_Pos)

1090

#define SDHC_NISTER_TRFC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */

1091

#define SDHC_NISTER_TRFC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */

1092

#define SDHC_NISTER_TRFC_MASKED (SDHC_NISTER_TRFC_MASKED_Val << SDHC_NISTER_TRFC_Pos)

1093

#define SDHC_NISTER_TRFC_ENABLED (SDHC_NISTER_TRFC_ENABLED_Val << SDHC_NISTER_TRFC_Pos)

1094

#define SDHC_NISTER_BLKGE_Pos 2 /**< \brief (SDHC_NISTER) Block Gap Event Status Enable */

1095

#define SDHC_NISTER_BLKGE (_U_(0x1) << SDHC_NISTER_BLKGE_Pos)

1096

#define SDHC_NISTER_BLKGE_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */

1097

#define SDHC_NISTER_BLKGE_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */

1098

#define SDHC_NISTER_BLKGE_MASKED (SDHC_NISTER_BLKGE_MASKED_Val << SDHC_NISTER_BLKGE_Pos)

1099

#define SDHC_NISTER_BLKGE_ENABLED (SDHC_NISTER_BLKGE_ENABLED_Val << SDHC_NISTER_BLKGE_Pos)

1100

#define SDHC_NISTER_DMAINT_Pos 3 /**< \brief (SDHC_NISTER) DMA Interrupt Status Enable */

1101

#define SDHC_NISTER_DMAINT (_U_(0x1) << SDHC_NISTER_DMAINT_Pos)

1102

#define SDHC_NISTER_DMAINT_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */

1103

#define SDHC_NISTER_DMAINT_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */

1104

#define SDHC_NISTER_DMAINT_MASKED (SDHC_NISTER_DMAINT_MASKED_Val << SDHC_NISTER_DMAINT_Pos)

1105

#define SDHC_NISTER_DMAINT_ENABLED (SDHC_NISTER_DMAINT_ENABLED_Val << SDHC_NISTER_DMAINT_Pos)

1106

#define SDHC_NISTER_BWRRDY_Pos 4 /**< \brief (SDHC_NISTER) Buffer Write Ready Status Enable */

1107

#define SDHC_NISTER_BWRRDY (_U_(0x1) << SDHC_NISTER_BWRRDY_Pos)

1108

#define SDHC_NISTER_BWRRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */

1109

#define SDHC_NISTER_BWRRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */

1110

#define SDHC_NISTER_BWRRDY_MASKED (SDHC_NISTER_BWRRDY_MASKED_Val << SDHC_NISTER_BWRRDY_Pos)

1111

#define SDHC_NISTER_BWRRDY_ENABLED (SDHC_NISTER_BWRRDY_ENABLED_Val << SDHC_NISTER_BWRRDY_Pos)

1112

#define SDHC_NISTER_BRDRDY_Pos 5 /**< \brief (SDHC_NISTER) Buffer Read Ready Status Enable */

1113

#define SDHC_NISTER_BRDRDY (_U_(0x1) << SDHC_NISTER_BRDRDY_Pos)

1114

#define SDHC_NISTER_BRDRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */

1115

#define SDHC_NISTER_BRDRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */

1116

#define SDHC_NISTER_BRDRDY_MASKED (SDHC_NISTER_BRDRDY_MASKED_Val << SDHC_NISTER_BRDRDY_Pos)

1117

#define SDHC_NISTER_BRDRDY_ENABLED (SDHC_NISTER_BRDRDY_ENABLED_Val << SDHC_NISTER_BRDRDY_Pos)

1118

#define SDHC_NISTER_CINS_Pos 6 /**< \brief (SDHC_NISTER) Card Insertion Status Enable */

1119

#define SDHC_NISTER_CINS (_U_(0x1) << SDHC_NISTER_CINS_Pos)

1120

#define SDHC_NISTER_CINS_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */

1121

#define SDHC_NISTER_CINS_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */

1122

#define SDHC_NISTER_CINS_MASKED (SDHC_NISTER_CINS_MASKED_Val << SDHC_NISTER_CINS_Pos)

1123

#define SDHC_NISTER_CINS_ENABLED (SDHC_NISTER_CINS_ENABLED_Val << SDHC_NISTER_CINS_Pos)

1124

#define SDHC_NISTER_CREM_Pos 7 /**< \brief (SDHC_NISTER) Card Removal Status Enable */

1125

#define SDHC_NISTER_CREM (_U_(0x1) << SDHC_NISTER_CREM_Pos)

1126

#define SDHC_NISTER_CREM_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */

1127

#define SDHC_NISTER_CREM_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */

1128

#define SDHC_NISTER_CREM_MASKED (SDHC_NISTER_CREM_MASKED_Val << SDHC_NISTER_CREM_Pos)

1129

#define SDHC_NISTER_CREM_ENABLED (SDHC_NISTER_CREM_ENABLED_Val << SDHC_NISTER_CREM_Pos)

1130

#define SDHC_NISTER_CINT_Pos 8 /**< \brief (SDHC_NISTER) Card Interrupt Status Enable */

1131

#define SDHC_NISTER_CINT (_U_(0x1) << SDHC_NISTER_CINT_Pos)

1132

#define SDHC_NISTER_CINT_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER) Masked */

1133

#define SDHC_NISTER_CINT_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER) Enabled */

1134

#define SDHC_NISTER_CINT_MASKED (SDHC_NISTER_CINT_MASKED_Val << SDHC_NISTER_CINT_Pos)

1135

#define SDHC_NISTER_CINT_ENABLED (SDHC_NISTER_CINT_ENABLED_Val << SDHC_NISTER_CINT_Pos)

1136

#define SDHC_NISTER_MASK _U_(0x01FF) /**< \brief (SDHC_NISTER) MASK Register */

1137

1138

// EMMC mode

1139

#define SDHC_NISTER_EMMC_CMDC_Pos 0 /**< \brief (SDHC_NISTER_EMMC) Command Complete Status Enable */

1140

#define SDHC_NISTER_EMMC_CMDC (_U_(0x1) << SDHC_NISTER_EMMC_CMDC_Pos)

1141

#define SDHC_NISTER_EMMC_CMDC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER_EMMC) Masked */

1142

#define SDHC_NISTER_EMMC_CMDC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER_EMMC) Enabled */

1143

#define SDHC_NISTER_EMMC_CMDC_MASKED (SDHC_NISTER_EMMC_CMDC_MASKED_Val << SDHC_NISTER_EMMC_CMDC_Pos)

1144

#define SDHC_NISTER_EMMC_CMDC_ENABLED (SDHC_NISTER_EMMC_CMDC_ENABLED_Val << SDHC_NISTER_EMMC_CMDC_Pos)

1145

#define SDHC_NISTER_EMMC_TRFC_Pos 1 /**< \brief (SDHC_NISTER_EMMC) Transfer Complete Status Enable */

1146

#define SDHC_NISTER_EMMC_TRFC (_U_(0x1) << SDHC_NISTER_EMMC_TRFC_Pos)

1147

#define SDHC_NISTER_EMMC_TRFC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER_EMMC) Masked */

1148

#define SDHC_NISTER_EMMC_TRFC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER_EMMC) Enabled */

1149

#define SDHC_NISTER_EMMC_TRFC_MASKED (SDHC_NISTER_EMMC_TRFC_MASKED_Val << SDHC_NISTER_EMMC_TRFC_Pos)

1150

#define SDHC_NISTER_EMMC_TRFC_ENABLED (SDHC_NISTER_EMMC_TRFC_ENABLED_Val << SDHC_NISTER_EMMC_TRFC_Pos)

1151

#define SDHC_NISTER_EMMC_BLKGE_Pos 2 /**< \brief (SDHC_NISTER_EMMC) Block Gap Event Status Enable */

1152

#define SDHC_NISTER_EMMC_BLKGE (_U_(0x1) << SDHC_NISTER_EMMC_BLKGE_Pos)

1153

#define SDHC_NISTER_EMMC_BLKGE_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER_EMMC) Masked */

1154

#define SDHC_NISTER_EMMC_BLKGE_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER_EMMC) Enabled */

1155

#define SDHC_NISTER_EMMC_BLKGE_MASKED (SDHC_NISTER_EMMC_BLKGE_MASKED_Val << SDHC_NISTER_EMMC_BLKGE_Pos)

1156

#define SDHC_NISTER_EMMC_BLKGE_ENABLED (SDHC_NISTER_EMMC_BLKGE_ENABLED_Val << SDHC_NISTER_EMMC_BLKGE_Pos)

1157

#define SDHC_NISTER_EMMC_DMAINT_Pos 3 /**< \brief (SDHC_NISTER_EMMC) DMA Interrupt Status Enable */

1158

#define SDHC_NISTER_EMMC_DMAINT (_U_(0x1) << SDHC_NISTER_EMMC_DMAINT_Pos)

1159

#define SDHC_NISTER_EMMC_DMAINT_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER_EMMC) Masked */

1160

#define SDHC_NISTER_EMMC_DMAINT_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER_EMMC) Enabled */

1161

#define SDHC_NISTER_EMMC_DMAINT_MASKED (SDHC_NISTER_EMMC_DMAINT_MASKED_Val << SDHC_NISTER_EMMC_DMAINT_Pos)

1162

#define SDHC_NISTER_EMMC_DMAINT_ENABLED (SDHC_NISTER_EMMC_DMAINT_ENABLED_Val << SDHC_NISTER_EMMC_DMAINT_Pos)

1163

#define SDHC_NISTER_EMMC_BWRRDY_Pos 4 /**< \brief (SDHC_NISTER_EMMC) Buffer Write Ready Status Enable */

1164

#define SDHC_NISTER_EMMC_BWRRDY (_U_(0x1) << SDHC_NISTER_EMMC_BWRRDY_Pos)

1165

#define SDHC_NISTER_EMMC_BWRRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER_EMMC) Masked */

1166

#define SDHC_NISTER_EMMC_BWRRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER_EMMC) Enabled */

1167

#define SDHC_NISTER_EMMC_BWRRDY_MASKED (SDHC_NISTER_EMMC_BWRRDY_MASKED_Val << SDHC_NISTER_EMMC_BWRRDY_Pos)

1168

#define SDHC_NISTER_EMMC_BWRRDY_ENABLED (SDHC_NISTER_EMMC_BWRRDY_ENABLED_Val << SDHC_NISTER_EMMC_BWRRDY_Pos)

1169

#define SDHC_NISTER_EMMC_BRDRDY_Pos 5 /**< \brief (SDHC_NISTER_EMMC) Buffer Read Ready Status Enable */

1170

#define SDHC_NISTER_EMMC_BRDRDY (_U_(0x1) << SDHC_NISTER_EMMC_BRDRDY_Pos)

1171

#define SDHC_NISTER_EMMC_BRDRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISTER_EMMC) Masked */

1172

#define SDHC_NISTER_EMMC_BRDRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISTER_EMMC) Enabled */

1173

#define SDHC_NISTER_EMMC_BRDRDY_MASKED (SDHC_NISTER_EMMC_BRDRDY_MASKED_Val << SDHC_NISTER_EMMC_BRDRDY_Pos)

1174

#define SDHC_NISTER_EMMC_BRDRDY_ENABLED (SDHC_NISTER_EMMC_BRDRDY_ENABLED_Val << SDHC_NISTER_EMMC_BRDRDY_Pos)

1175

#define SDHC_NISTER_EMMC_BOOTAR_Pos 14 /**< \brief (SDHC_NISTER_EMMC) Boot Acknowledge Received Status Enable */

1176

#define SDHC_NISTER_EMMC_BOOTAR (_U_(0x1) << SDHC_NISTER_EMMC_BOOTAR_Pos)

1177

#define SDHC_NISTER_EMMC_MASK _U_(0x403F) /**< \brief (SDHC_NISTER_EMMC) MASK Register */

1178

1179

/* -------- SDHC_EISTER : (SDHC Offset: 0x036) (R/W 16) Error Interrupt Status Enable -------- */

1180

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

1181

typedef union {

1182

struct {

1183

uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error Status Enable */

1184

uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error Status Enable */

1185

uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error Status Enable */

1186

uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error Status Enable */

1187

uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error Status Enable */

1188

uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error Status Enable */

1189

uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error Status Enable */

1190

uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error Status Enable */

1191

uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error Status Enable */

1192

uint16_t ADMA:1; /*!< bit: 9 ADMA Error Status Enable */

1193

uint16_t :6; /*!< bit: 10..15 Reserved */

1194

} bit; /*!< Structure used for bit access */

1195

struct { // EMMC mode

1196

uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error Status Enable */

1197

uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error Status Enable */

1198

uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error Status Enable */

1199

uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error Status Enable */

1200

uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error Status Enable */

1201

uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error Status Enable */

1202

uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error Status Enable */

1203

uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error Status Enable */

1204

uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error Status Enable */

1205

uint16_t ADMA:1; /*!< bit: 9 ADMA Error Status Enable */

1206

uint16_t :2; /*!< bit: 10..11 Reserved */

1207

uint16_t BOOTAE:1; /*!< bit: 12 Boot Acknowledge Error Status Enable */

1208

uint16_t :3; /*!< bit: 13..15 Reserved */

1209

} EMMC; /*!< Structure used for EMMC */

1210

uint16_t reg; /*!< Type used for register access */

1211

} SDHC_EISTER_Type;

1212

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

1213

1214

#define SDHC_EISTER_OFFSET 0x036 /**< \brief (SDHC_EISTER offset) Error Interrupt Status Enable */

1215

#define SDHC_EISTER_RESETVALUE _U_(0x0000) /**< \brief (SDHC_EISTER reset_value) Error Interrupt Status Enable */

1216

1217

#define SDHC_EISTER_CMDTEO_Pos 0 /**< \brief (SDHC_EISTER) Command Timeout Error Status Enable */

1218

#define SDHC_EISTER_CMDTEO (_U_(0x1) << SDHC_EISTER_CMDTEO_Pos)

1219

#define SDHC_EISTER_CMDTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */

1220

#define SDHC_EISTER_CMDTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */

1221

#define SDHC_EISTER_CMDTEO_MASKED (SDHC_EISTER_CMDTEO_MASKED_Val << SDHC_EISTER_CMDTEO_Pos)

1222

#define SDHC_EISTER_CMDTEO_ENABLED (SDHC_EISTER_CMDTEO_ENABLED_Val << SDHC_EISTER_CMDTEO_Pos)

1223

#define SDHC_EISTER_CMDCRC_Pos 1 /**< \brief (SDHC_EISTER) Command CRC Error Status Enable */

1224

#define SDHC_EISTER_CMDCRC (_U_(0x1) << SDHC_EISTER_CMDCRC_Pos)

1225

#define SDHC_EISTER_CMDCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */

1226

#define SDHC_EISTER_CMDCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */

1227

#define SDHC_EISTER_CMDCRC_MASKED (SDHC_EISTER_CMDCRC_MASKED_Val << SDHC_EISTER_CMDCRC_Pos)

1228

#define SDHC_EISTER_CMDCRC_ENABLED (SDHC_EISTER_CMDCRC_ENABLED_Val << SDHC_EISTER_CMDCRC_Pos)

1229

#define SDHC_EISTER_CMDEND_Pos 2 /**< \brief (SDHC_EISTER) Command End Bit Error Status Enable */

1230

#define SDHC_EISTER_CMDEND (_U_(0x1) << SDHC_EISTER_CMDEND_Pos)

1231

#define SDHC_EISTER_CMDEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */

1232

#define SDHC_EISTER_CMDEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */

1233

#define SDHC_EISTER_CMDEND_MASKED (SDHC_EISTER_CMDEND_MASKED_Val << SDHC_EISTER_CMDEND_Pos)

1234

#define SDHC_EISTER_CMDEND_ENABLED (SDHC_EISTER_CMDEND_ENABLED_Val << SDHC_EISTER_CMDEND_Pos)

1235

#define SDHC_EISTER_CMDIDX_Pos 3 /**< \brief (SDHC_EISTER) Command Index Error Status Enable */

1236

#define SDHC_EISTER_CMDIDX (_U_(0x1) << SDHC_EISTER_CMDIDX_Pos)

1237

#define SDHC_EISTER_CMDIDX_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */

1238

#define SDHC_EISTER_CMDIDX_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */

1239

#define SDHC_EISTER_CMDIDX_MASKED (SDHC_EISTER_CMDIDX_MASKED_Val << SDHC_EISTER_CMDIDX_Pos)

1240

#define SDHC_EISTER_CMDIDX_ENABLED (SDHC_EISTER_CMDIDX_ENABLED_Val << SDHC_EISTER_CMDIDX_Pos)

1241

#define SDHC_EISTER_DATTEO_Pos 4 /**< \brief (SDHC_EISTER) Data Timeout Error Status Enable */

1242

#define SDHC_EISTER_DATTEO (_U_(0x1) << SDHC_EISTER_DATTEO_Pos)

1243

#define SDHC_EISTER_DATTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */

1244

#define SDHC_EISTER_DATTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */

1245

#define SDHC_EISTER_DATTEO_MASKED (SDHC_EISTER_DATTEO_MASKED_Val << SDHC_EISTER_DATTEO_Pos)

1246

#define SDHC_EISTER_DATTEO_ENABLED (SDHC_EISTER_DATTEO_ENABLED_Val << SDHC_EISTER_DATTEO_Pos)

1247

#define SDHC_EISTER_DATCRC_Pos 5 /**< \brief (SDHC_EISTER) Data CRC Error Status Enable */

1248

#define SDHC_EISTER_DATCRC (_U_(0x1) << SDHC_EISTER_DATCRC_Pos)

1249

#define SDHC_EISTER_DATCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */

1250

#define SDHC_EISTER_DATCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */

1251

#define SDHC_EISTER_DATCRC_MASKED (SDHC_EISTER_DATCRC_MASKED_Val << SDHC_EISTER_DATCRC_Pos)

1252

#define SDHC_EISTER_DATCRC_ENABLED (SDHC_EISTER_DATCRC_ENABLED_Val << SDHC_EISTER_DATCRC_Pos)

1253

#define SDHC_EISTER_DATEND_Pos 6 /**< \brief (SDHC_EISTER) Data End Bit Error Status Enable */

1254

#define SDHC_EISTER_DATEND (_U_(0x1) << SDHC_EISTER_DATEND_Pos)

1255

#define SDHC_EISTER_DATEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */

1256

#define SDHC_EISTER_DATEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */

1257

#define SDHC_EISTER_DATEND_MASKED (SDHC_EISTER_DATEND_MASKED_Val << SDHC_EISTER_DATEND_Pos)

1258

#define SDHC_EISTER_DATEND_ENABLED (SDHC_EISTER_DATEND_ENABLED_Val << SDHC_EISTER_DATEND_Pos)

1259

#define SDHC_EISTER_CURLIM_Pos 7 /**< \brief (SDHC_EISTER) Current Limit Error Status Enable */

1260

#define SDHC_EISTER_CURLIM (_U_(0x1) << SDHC_EISTER_CURLIM_Pos)

1261

#define SDHC_EISTER_CURLIM_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */

1262

#define SDHC_EISTER_CURLIM_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */

1263

#define SDHC_EISTER_CURLIM_MASKED (SDHC_EISTER_CURLIM_MASKED_Val << SDHC_EISTER_CURLIM_Pos)

1264

#define SDHC_EISTER_CURLIM_ENABLED (SDHC_EISTER_CURLIM_ENABLED_Val << SDHC_EISTER_CURLIM_Pos)

1265

#define SDHC_EISTER_ACMD_Pos 8 /**< \brief (SDHC_EISTER) Auto CMD Error Status Enable */

1266

#define SDHC_EISTER_ACMD (_U_(0x1) << SDHC_EISTER_ACMD_Pos)

1267

#define SDHC_EISTER_ACMD_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */

1268

#define SDHC_EISTER_ACMD_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */

1269

#define SDHC_EISTER_ACMD_MASKED (SDHC_EISTER_ACMD_MASKED_Val << SDHC_EISTER_ACMD_Pos)

1270

#define SDHC_EISTER_ACMD_ENABLED (SDHC_EISTER_ACMD_ENABLED_Val << SDHC_EISTER_ACMD_Pos)

1271

#define SDHC_EISTER_ADMA_Pos 9 /**< \brief (SDHC_EISTER) ADMA Error Status Enable */

1272

#define SDHC_EISTER_ADMA (_U_(0x1) << SDHC_EISTER_ADMA_Pos)

1273

#define SDHC_EISTER_ADMA_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER) Masked */

1274

#define SDHC_EISTER_ADMA_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER) Enabled */

1275

#define SDHC_EISTER_ADMA_MASKED (SDHC_EISTER_ADMA_MASKED_Val << SDHC_EISTER_ADMA_Pos)

1276

#define SDHC_EISTER_ADMA_ENABLED (SDHC_EISTER_ADMA_ENABLED_Val << SDHC_EISTER_ADMA_Pos)

1277

#define SDHC_EISTER_MASK _U_(0x03FF) /**< \brief (SDHC_EISTER) MASK Register */

1278

1279

// EMMC mode

1280

#define SDHC_EISTER_EMMC_CMDTEO_Pos 0 /**< \brief (SDHC_EISTER_EMMC) Command Timeout Error Status Enable */

1281

#define SDHC_EISTER_EMMC_CMDTEO (_U_(0x1) << SDHC_EISTER_EMMC_CMDTEO_Pos)

1282

#define SDHC_EISTER_EMMC_CMDTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */

1283

#define SDHC_EISTER_EMMC_CMDTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */

1284

#define SDHC_EISTER_EMMC_CMDTEO_MASKED (SDHC_EISTER_EMMC_CMDTEO_MASKED_Val << SDHC_EISTER_EMMC_CMDTEO_Pos)

1285

#define SDHC_EISTER_EMMC_CMDTEO_ENABLED (SDHC_EISTER_EMMC_CMDTEO_ENABLED_Val << SDHC_EISTER_EMMC_CMDTEO_Pos)

1286

#define SDHC_EISTER_EMMC_CMDCRC_Pos 1 /**< \brief (SDHC_EISTER_EMMC) Command CRC Error Status Enable */

1287

#define SDHC_EISTER_EMMC_CMDCRC (_U_(0x1) << SDHC_EISTER_EMMC_CMDCRC_Pos)

1288

#define SDHC_EISTER_EMMC_CMDCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */

1289

#define SDHC_EISTER_EMMC_CMDCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */

1290

#define SDHC_EISTER_EMMC_CMDCRC_MASKED (SDHC_EISTER_EMMC_CMDCRC_MASKED_Val << SDHC_EISTER_EMMC_CMDCRC_Pos)

1291

#define SDHC_EISTER_EMMC_CMDCRC_ENABLED (SDHC_EISTER_EMMC_CMDCRC_ENABLED_Val << SDHC_EISTER_EMMC_CMDCRC_Pos)

1292

#define SDHC_EISTER_EMMC_CMDEND_Pos 2 /**< \brief (SDHC_EISTER_EMMC) Command End Bit Error Status Enable */

1293

#define SDHC_EISTER_EMMC_CMDEND (_U_(0x1) << SDHC_EISTER_EMMC_CMDEND_Pos)

1294

#define SDHC_EISTER_EMMC_CMDEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */

1295

#define SDHC_EISTER_EMMC_CMDEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */

1296

#define SDHC_EISTER_EMMC_CMDEND_MASKED (SDHC_EISTER_EMMC_CMDEND_MASKED_Val << SDHC_EISTER_EMMC_CMDEND_Pos)

1297

#define SDHC_EISTER_EMMC_CMDEND_ENABLED (SDHC_EISTER_EMMC_CMDEND_ENABLED_Val << SDHC_EISTER_EMMC_CMDEND_Pos)

1298

#define SDHC_EISTER_EMMC_CMDIDX_Pos 3 /**< \brief (SDHC_EISTER_EMMC) Command Index Error Status Enable */

1299

#define SDHC_EISTER_EMMC_CMDIDX (_U_(0x1) << SDHC_EISTER_EMMC_CMDIDX_Pos)

1300

#define SDHC_EISTER_EMMC_CMDIDX_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */

1301

#define SDHC_EISTER_EMMC_CMDIDX_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */

1302

#define SDHC_EISTER_EMMC_CMDIDX_MASKED (SDHC_EISTER_EMMC_CMDIDX_MASKED_Val << SDHC_EISTER_EMMC_CMDIDX_Pos)

1303

#define SDHC_EISTER_EMMC_CMDIDX_ENABLED (SDHC_EISTER_EMMC_CMDIDX_ENABLED_Val << SDHC_EISTER_EMMC_CMDIDX_Pos)

1304

#define SDHC_EISTER_EMMC_DATTEO_Pos 4 /**< \brief (SDHC_EISTER_EMMC) Data Timeout Error Status Enable */

1305

#define SDHC_EISTER_EMMC_DATTEO (_U_(0x1) << SDHC_EISTER_EMMC_DATTEO_Pos)

1306

#define SDHC_EISTER_EMMC_DATTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */

1307

#define SDHC_EISTER_EMMC_DATTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */

1308

#define SDHC_EISTER_EMMC_DATTEO_MASKED (SDHC_EISTER_EMMC_DATTEO_MASKED_Val << SDHC_EISTER_EMMC_DATTEO_Pos)

1309

#define SDHC_EISTER_EMMC_DATTEO_ENABLED (SDHC_EISTER_EMMC_DATTEO_ENABLED_Val << SDHC_EISTER_EMMC_DATTEO_Pos)

1310

#define SDHC_EISTER_EMMC_DATCRC_Pos 5 /**< \brief (SDHC_EISTER_EMMC) Data CRC Error Status Enable */

1311

#define SDHC_EISTER_EMMC_DATCRC (_U_(0x1) << SDHC_EISTER_EMMC_DATCRC_Pos)

1312

#define SDHC_EISTER_EMMC_DATCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */

1313

#define SDHC_EISTER_EMMC_DATCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */

1314

#define SDHC_EISTER_EMMC_DATCRC_MASKED (SDHC_EISTER_EMMC_DATCRC_MASKED_Val << SDHC_EISTER_EMMC_DATCRC_Pos)

1315

#define SDHC_EISTER_EMMC_DATCRC_ENABLED (SDHC_EISTER_EMMC_DATCRC_ENABLED_Val << SDHC_EISTER_EMMC_DATCRC_Pos)

1316

#define SDHC_EISTER_EMMC_DATEND_Pos 6 /**< \brief (SDHC_EISTER_EMMC) Data End Bit Error Status Enable */

1317

#define SDHC_EISTER_EMMC_DATEND (_U_(0x1) << SDHC_EISTER_EMMC_DATEND_Pos)

1318

#define SDHC_EISTER_EMMC_DATEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */

1319

#define SDHC_EISTER_EMMC_DATEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */

1320

#define SDHC_EISTER_EMMC_DATEND_MASKED (SDHC_EISTER_EMMC_DATEND_MASKED_Val << SDHC_EISTER_EMMC_DATEND_Pos)

1321

#define SDHC_EISTER_EMMC_DATEND_ENABLED (SDHC_EISTER_EMMC_DATEND_ENABLED_Val << SDHC_EISTER_EMMC_DATEND_Pos)

1322

#define SDHC_EISTER_EMMC_CURLIM_Pos 7 /**< \brief (SDHC_EISTER_EMMC) Current Limit Error Status Enable */

1323

#define SDHC_EISTER_EMMC_CURLIM (_U_(0x1) << SDHC_EISTER_EMMC_CURLIM_Pos)

1324

#define SDHC_EISTER_EMMC_CURLIM_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */

1325

#define SDHC_EISTER_EMMC_CURLIM_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */

1326

#define SDHC_EISTER_EMMC_CURLIM_MASKED (SDHC_EISTER_EMMC_CURLIM_MASKED_Val << SDHC_EISTER_EMMC_CURLIM_Pos)

1327

#define SDHC_EISTER_EMMC_CURLIM_ENABLED (SDHC_EISTER_EMMC_CURLIM_ENABLED_Val << SDHC_EISTER_EMMC_CURLIM_Pos)

1328

#define SDHC_EISTER_EMMC_ACMD_Pos 8 /**< \brief (SDHC_EISTER_EMMC) Auto CMD Error Status Enable */

1329

#define SDHC_EISTER_EMMC_ACMD (_U_(0x1) << SDHC_EISTER_EMMC_ACMD_Pos)

1330

#define SDHC_EISTER_EMMC_ACMD_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */

1331

#define SDHC_EISTER_EMMC_ACMD_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */

1332

#define SDHC_EISTER_EMMC_ACMD_MASKED (SDHC_EISTER_EMMC_ACMD_MASKED_Val << SDHC_EISTER_EMMC_ACMD_Pos)

1333

#define SDHC_EISTER_EMMC_ACMD_ENABLED (SDHC_EISTER_EMMC_ACMD_ENABLED_Val << SDHC_EISTER_EMMC_ACMD_Pos)

1334

#define SDHC_EISTER_EMMC_ADMA_Pos 9 /**< \brief (SDHC_EISTER_EMMC) ADMA Error Status Enable */

1335

#define SDHC_EISTER_EMMC_ADMA (_U_(0x1) << SDHC_EISTER_EMMC_ADMA_Pos)

1336

#define SDHC_EISTER_EMMC_ADMA_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISTER_EMMC) Masked */

1337

#define SDHC_EISTER_EMMC_ADMA_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISTER_EMMC) Enabled */

1338

#define SDHC_EISTER_EMMC_ADMA_MASKED (SDHC_EISTER_EMMC_ADMA_MASKED_Val << SDHC_EISTER_EMMC_ADMA_Pos)

1339

#define SDHC_EISTER_EMMC_ADMA_ENABLED (SDHC_EISTER_EMMC_ADMA_ENABLED_Val << SDHC_EISTER_EMMC_ADMA_Pos)

1340

#define SDHC_EISTER_EMMC_BOOTAE_Pos 12 /**< \brief (SDHC_EISTER_EMMC) Boot Acknowledge Error Status Enable */

1341

#define SDHC_EISTER_EMMC_BOOTAE (_U_(0x1) << SDHC_EISTER_EMMC_BOOTAE_Pos)

1342

#define SDHC_EISTER_EMMC_MASK _U_(0x13FF) /**< \brief (SDHC_EISTER_EMMC) MASK Register */

1343

1344

/* -------- SDHC_NISIER : (SDHC Offset: 0x038) (R/W 16) Normal Interrupt Signal Enable -------- */

1345

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

1346

typedef union {

1347

struct {

1348

uint16_t CMDC:1; /*!< bit: 0 Command Complete Signal Enable */

1349

uint16_t TRFC:1; /*!< bit: 1 Transfer Complete Signal Enable */

1350

uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event Signal Enable */

1351

uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt Signal Enable */

1352

uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready Signal Enable */

1353

uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready Signal Enable */

1354

uint16_t CINS:1; /*!< bit: 6 Card Insertion Signal Enable */

1355

uint16_t CREM:1; /*!< bit: 7 Card Removal Signal Enable */

1356

uint16_t CINT:1; /*!< bit: 8 Card Interrupt Signal Enable */

1357

uint16_t :7; /*!< bit: 9..15 Reserved */

1358

} bit; /*!< Structure used for bit access */

1359

struct { // EMMC mode

1360

uint16_t CMDC:1; /*!< bit: 0 Command Complete Signal Enable */

1361

uint16_t TRFC:1; /*!< bit: 1 Transfer Complete Signal Enable */

1362

uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event Signal Enable */

1363

uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt Signal Enable */

1364

uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready Signal Enable */

1365

uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready Signal Enable */

1366

uint16_t :8; /*!< bit: 6..13 Reserved */

1367

uint16_t BOOTAR:1; /*!< bit: 14 Boot Acknowledge Received Signal Enable */

1368

uint16_t :1; /*!< bit: 15 Reserved */

1369

} EMMC; /*!< Structure used for EMMC */

1370

uint16_t reg; /*!< Type used for register access */

1371

} SDHC_NISIER_Type;

1372

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

1373

1374

#define SDHC_NISIER_OFFSET 0x038 /**< \brief (SDHC_NISIER offset) Normal Interrupt Signal Enable */

1375

#define SDHC_NISIER_RESETVALUE _U_(0x0000) /**< \brief (SDHC_NISIER reset_value) Normal Interrupt Signal Enable */

1376

1377

#define SDHC_NISIER_CMDC_Pos 0 /**< \brief (SDHC_NISIER) Command Complete Signal Enable */

1378

#define SDHC_NISIER_CMDC (_U_(0x1) << SDHC_NISIER_CMDC_Pos)

1379

#define SDHC_NISIER_CMDC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */

1380

#define SDHC_NISIER_CMDC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */

1381

#define SDHC_NISIER_CMDC_MASKED (SDHC_NISIER_CMDC_MASKED_Val << SDHC_NISIER_CMDC_Pos)

1382

#define SDHC_NISIER_CMDC_ENABLED (SDHC_NISIER_CMDC_ENABLED_Val << SDHC_NISIER_CMDC_Pos)

1383

#define SDHC_NISIER_TRFC_Pos 1 /**< \brief (SDHC_NISIER) Transfer Complete Signal Enable */

1384

#define SDHC_NISIER_TRFC (_U_(0x1) << SDHC_NISIER_TRFC_Pos)

1385

#define SDHC_NISIER_TRFC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */

1386

#define SDHC_NISIER_TRFC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */

1387

#define SDHC_NISIER_TRFC_MASKED (SDHC_NISIER_TRFC_MASKED_Val << SDHC_NISIER_TRFC_Pos)

1388

#define SDHC_NISIER_TRFC_ENABLED (SDHC_NISIER_TRFC_ENABLED_Val << SDHC_NISIER_TRFC_Pos)

1389

#define SDHC_NISIER_BLKGE_Pos 2 /**< \brief (SDHC_NISIER) Block Gap Event Signal Enable */

1390

#define SDHC_NISIER_BLKGE (_U_(0x1) << SDHC_NISIER_BLKGE_Pos)

1391

#define SDHC_NISIER_BLKGE_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */

1392

#define SDHC_NISIER_BLKGE_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */

1393

#define SDHC_NISIER_BLKGE_MASKED (SDHC_NISIER_BLKGE_MASKED_Val << SDHC_NISIER_BLKGE_Pos)

1394

#define SDHC_NISIER_BLKGE_ENABLED (SDHC_NISIER_BLKGE_ENABLED_Val << SDHC_NISIER_BLKGE_Pos)

1395

#define SDHC_NISIER_DMAINT_Pos 3 /**< \brief (SDHC_NISIER) DMA Interrupt Signal Enable */

1396

#define SDHC_NISIER_DMAINT (_U_(0x1) << SDHC_NISIER_DMAINT_Pos)

1397

#define SDHC_NISIER_DMAINT_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */

1398

#define SDHC_NISIER_DMAINT_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */

1399

#define SDHC_NISIER_DMAINT_MASKED (SDHC_NISIER_DMAINT_MASKED_Val << SDHC_NISIER_DMAINT_Pos)

1400

#define SDHC_NISIER_DMAINT_ENABLED (SDHC_NISIER_DMAINT_ENABLED_Val << SDHC_NISIER_DMAINT_Pos)

1401

#define SDHC_NISIER_BWRRDY_Pos 4 /**< \brief (SDHC_NISIER) Buffer Write Ready Signal Enable */

1402

#define SDHC_NISIER_BWRRDY (_U_(0x1) << SDHC_NISIER_BWRRDY_Pos)

1403

#define SDHC_NISIER_BWRRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */

1404

#define SDHC_NISIER_BWRRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */

1405

#define SDHC_NISIER_BWRRDY_MASKED (SDHC_NISIER_BWRRDY_MASKED_Val << SDHC_NISIER_BWRRDY_Pos)

1406

#define SDHC_NISIER_BWRRDY_ENABLED (SDHC_NISIER_BWRRDY_ENABLED_Val << SDHC_NISIER_BWRRDY_Pos)

1407

#define SDHC_NISIER_BRDRDY_Pos 5 /**< \brief (SDHC_NISIER) Buffer Read Ready Signal Enable */

1408

#define SDHC_NISIER_BRDRDY (_U_(0x1) << SDHC_NISIER_BRDRDY_Pos)

1409

#define SDHC_NISIER_BRDRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */

1410

#define SDHC_NISIER_BRDRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */

1411

#define SDHC_NISIER_BRDRDY_MASKED (SDHC_NISIER_BRDRDY_MASKED_Val << SDHC_NISIER_BRDRDY_Pos)

1412

#define SDHC_NISIER_BRDRDY_ENABLED (SDHC_NISIER_BRDRDY_ENABLED_Val << SDHC_NISIER_BRDRDY_Pos)

1413

#define SDHC_NISIER_CINS_Pos 6 /**< \brief (SDHC_NISIER) Card Insertion Signal Enable */

1414

#define SDHC_NISIER_CINS (_U_(0x1) << SDHC_NISIER_CINS_Pos)

1415

#define SDHC_NISIER_CINS_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */

1416

#define SDHC_NISIER_CINS_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */

1417

#define SDHC_NISIER_CINS_MASKED (SDHC_NISIER_CINS_MASKED_Val << SDHC_NISIER_CINS_Pos)

1418

#define SDHC_NISIER_CINS_ENABLED (SDHC_NISIER_CINS_ENABLED_Val << SDHC_NISIER_CINS_Pos)

1419

#define SDHC_NISIER_CREM_Pos 7 /**< \brief (SDHC_NISIER) Card Removal Signal Enable */

1420

#define SDHC_NISIER_CREM (_U_(0x1) << SDHC_NISIER_CREM_Pos)

1421

#define SDHC_NISIER_CREM_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */

1422

#define SDHC_NISIER_CREM_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */

1423

#define SDHC_NISIER_CREM_MASKED (SDHC_NISIER_CREM_MASKED_Val << SDHC_NISIER_CREM_Pos)

1424

#define SDHC_NISIER_CREM_ENABLED (SDHC_NISIER_CREM_ENABLED_Val << SDHC_NISIER_CREM_Pos)

1425

#define SDHC_NISIER_CINT_Pos 8 /**< \brief (SDHC_NISIER) Card Interrupt Signal Enable */

1426

#define SDHC_NISIER_CINT (_U_(0x1) << SDHC_NISIER_CINT_Pos)

1427

#define SDHC_NISIER_CINT_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER) Masked */

1428

#define SDHC_NISIER_CINT_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER) Enabled */

1429

#define SDHC_NISIER_CINT_MASKED (SDHC_NISIER_CINT_MASKED_Val << SDHC_NISIER_CINT_Pos)

1430

#define SDHC_NISIER_CINT_ENABLED (SDHC_NISIER_CINT_ENABLED_Val << SDHC_NISIER_CINT_Pos)

1431

#define SDHC_NISIER_MASK _U_(0x01FF) /**< \brief (SDHC_NISIER) MASK Register */

1432

1433

// EMMC mode

1434

#define SDHC_NISIER_EMMC_CMDC_Pos 0 /**< \brief (SDHC_NISIER_EMMC) Command Complete Signal Enable */

1435

#define SDHC_NISIER_EMMC_CMDC (_U_(0x1) << SDHC_NISIER_EMMC_CMDC_Pos)

1436

#define SDHC_NISIER_EMMC_CMDC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER_EMMC) Masked */

1437

#define SDHC_NISIER_EMMC_CMDC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER_EMMC) Enabled */

1438

#define SDHC_NISIER_EMMC_CMDC_MASKED (SDHC_NISIER_EMMC_CMDC_MASKED_Val << SDHC_NISIER_EMMC_CMDC_Pos)

1439

#define SDHC_NISIER_EMMC_CMDC_ENABLED (SDHC_NISIER_EMMC_CMDC_ENABLED_Val << SDHC_NISIER_EMMC_CMDC_Pos)

1440

#define SDHC_NISIER_EMMC_TRFC_Pos 1 /**< \brief (SDHC_NISIER_EMMC) Transfer Complete Signal Enable */

1441

#define SDHC_NISIER_EMMC_TRFC (_U_(0x1) << SDHC_NISIER_EMMC_TRFC_Pos)

1442

#define SDHC_NISIER_EMMC_TRFC_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER_EMMC) Masked */

1443

#define SDHC_NISIER_EMMC_TRFC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER_EMMC) Enabled */

1444

#define SDHC_NISIER_EMMC_TRFC_MASKED (SDHC_NISIER_EMMC_TRFC_MASKED_Val << SDHC_NISIER_EMMC_TRFC_Pos)

1445

#define SDHC_NISIER_EMMC_TRFC_ENABLED (SDHC_NISIER_EMMC_TRFC_ENABLED_Val << SDHC_NISIER_EMMC_TRFC_Pos)

1446

#define SDHC_NISIER_EMMC_BLKGE_Pos 2 /**< \brief (SDHC_NISIER_EMMC) Block Gap Event Signal Enable */

1447

#define SDHC_NISIER_EMMC_BLKGE (_U_(0x1) << SDHC_NISIER_EMMC_BLKGE_Pos)

1448

#define SDHC_NISIER_EMMC_BLKGE_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER_EMMC) Masked */

1449

#define SDHC_NISIER_EMMC_BLKGE_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER_EMMC) Enabled */

1450

#define SDHC_NISIER_EMMC_BLKGE_MASKED (SDHC_NISIER_EMMC_BLKGE_MASKED_Val << SDHC_NISIER_EMMC_BLKGE_Pos)

1451

#define SDHC_NISIER_EMMC_BLKGE_ENABLED (SDHC_NISIER_EMMC_BLKGE_ENABLED_Val << SDHC_NISIER_EMMC_BLKGE_Pos)

1452

#define SDHC_NISIER_EMMC_DMAINT_Pos 3 /**< \brief (SDHC_NISIER_EMMC) DMA Interrupt Signal Enable */

1453

#define SDHC_NISIER_EMMC_DMAINT (_U_(0x1) << SDHC_NISIER_EMMC_DMAINT_Pos)

1454

#define SDHC_NISIER_EMMC_DMAINT_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER_EMMC) Masked */

1455

#define SDHC_NISIER_EMMC_DMAINT_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER_EMMC) Enabled */

1456

#define SDHC_NISIER_EMMC_DMAINT_MASKED (SDHC_NISIER_EMMC_DMAINT_MASKED_Val << SDHC_NISIER_EMMC_DMAINT_Pos)

1457

#define SDHC_NISIER_EMMC_DMAINT_ENABLED (SDHC_NISIER_EMMC_DMAINT_ENABLED_Val << SDHC_NISIER_EMMC_DMAINT_Pos)

1458

#define SDHC_NISIER_EMMC_BWRRDY_Pos 4 /**< \brief (SDHC_NISIER_EMMC) Buffer Write Ready Signal Enable */

1459

#define SDHC_NISIER_EMMC_BWRRDY (_U_(0x1) << SDHC_NISIER_EMMC_BWRRDY_Pos)

1460

#define SDHC_NISIER_EMMC_BWRRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER_EMMC) Masked */

1461

#define SDHC_NISIER_EMMC_BWRRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER_EMMC) Enabled */

1462

#define SDHC_NISIER_EMMC_BWRRDY_MASKED (SDHC_NISIER_EMMC_BWRRDY_MASKED_Val << SDHC_NISIER_EMMC_BWRRDY_Pos)

1463

#define SDHC_NISIER_EMMC_BWRRDY_ENABLED (SDHC_NISIER_EMMC_BWRRDY_ENABLED_Val << SDHC_NISIER_EMMC_BWRRDY_Pos)

1464

#define SDHC_NISIER_EMMC_BRDRDY_Pos 5 /**< \brief (SDHC_NISIER_EMMC) Buffer Read Ready Signal Enable */

1465

#define SDHC_NISIER_EMMC_BRDRDY (_U_(0x1) << SDHC_NISIER_EMMC_BRDRDY_Pos)

1466

#define SDHC_NISIER_EMMC_BRDRDY_MASKED_Val _U_(0x0) /**< \brief (SDHC_NISIER_EMMC) Masked */

1467

#define SDHC_NISIER_EMMC_BRDRDY_ENABLED_Val _U_(0x1) /**< \brief (SDHC_NISIER_EMMC) Enabled */

1468

#define SDHC_NISIER_EMMC_BRDRDY_MASKED (SDHC_NISIER_EMMC_BRDRDY_MASKED_Val << SDHC_NISIER_EMMC_BRDRDY_Pos)

1469

#define SDHC_NISIER_EMMC_BRDRDY_ENABLED (SDHC_NISIER_EMMC_BRDRDY_ENABLED_Val << SDHC_NISIER_EMMC_BRDRDY_Pos)

1470

#define SDHC_NISIER_EMMC_BOOTAR_Pos 14 /**< \brief (SDHC_NISIER_EMMC) Boot Acknowledge Received Signal Enable */

1471

#define SDHC_NISIER_EMMC_BOOTAR (_U_(0x1) << SDHC_NISIER_EMMC_BOOTAR_Pos)

1472

#define SDHC_NISIER_EMMC_MASK _U_(0x403F) /**< \brief (SDHC_NISIER_EMMC) MASK Register */

1473

1474

/* -------- SDHC_EISIER : (SDHC Offset: 0x03A) (R/W 16) Error Interrupt Signal Enable -------- */

1475

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

1476

typedef union {

1477

struct {

1478

uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error Signal Enable */

1479

uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error Signal Enable */

1480

uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error Signal Enable */

1481

uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error Signal Enable */

1482

uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error Signal Enable */

1483

uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error Signal Enable */

1484

uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error Signal Enable */

1485

uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error Signal Enable */

1486

uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error Signal Enable */

1487

uint16_t ADMA:1; /*!< bit: 9 ADMA Error Signal Enable */

1488

uint16_t :6; /*!< bit: 10..15 Reserved */

1489

} bit; /*!< Structure used for bit access */

1490

struct { // EMMC mode

1491

uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error Signal Enable */

1492

uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error Signal Enable */

1493

uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error Signal Enable */

1494

uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error Signal Enable */

1495

uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error Signal Enable */

1496

uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error Signal Enable */

1497

uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error Signal Enable */

1498

uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error Signal Enable */

1499

uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error Signal Enable */

1500

uint16_t ADMA:1; /*!< bit: 9 ADMA Error Signal Enable */

1501

uint16_t :2; /*!< bit: 10..11 Reserved */

1502

uint16_t BOOTAE:1; /*!< bit: 12 Boot Acknowledge Error Signal Enable */

1503

uint16_t :3; /*!< bit: 13..15 Reserved */

1504

} EMMC; /*!< Structure used for EMMC */

1505

uint16_t reg; /*!< Type used for register access */

1506

} SDHC_EISIER_Type;

1507

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

1508

1509

#define SDHC_EISIER_OFFSET 0x03A /**< \brief (SDHC_EISIER offset) Error Interrupt Signal Enable */

1510

#define SDHC_EISIER_RESETVALUE _U_(0x0000) /**< \brief (SDHC_EISIER reset_value) Error Interrupt Signal Enable */

1511

1512

#define SDHC_EISIER_CMDTEO_Pos 0 /**< \brief (SDHC_EISIER) Command Timeout Error Signal Enable */

1513

#define SDHC_EISIER_CMDTEO (_U_(0x1) << SDHC_EISIER_CMDTEO_Pos)

1514

#define SDHC_EISIER_CMDTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */

1515

#define SDHC_EISIER_CMDTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */

1516

#define SDHC_EISIER_CMDTEO_MASKED (SDHC_EISIER_CMDTEO_MASKED_Val << SDHC_EISIER_CMDTEO_Pos)

1517

#define SDHC_EISIER_CMDTEO_ENABLED (SDHC_EISIER_CMDTEO_ENABLED_Val << SDHC_EISIER_CMDTEO_Pos)

1518

#define SDHC_EISIER_CMDCRC_Pos 1 /**< \brief (SDHC_EISIER) Command CRC Error Signal Enable */

1519

#define SDHC_EISIER_CMDCRC (_U_(0x1) << SDHC_EISIER_CMDCRC_Pos)

1520

#define SDHC_EISIER_CMDCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */

1521

#define SDHC_EISIER_CMDCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */

1522

#define SDHC_EISIER_CMDCRC_MASKED (SDHC_EISIER_CMDCRC_MASKED_Val << SDHC_EISIER_CMDCRC_Pos)

1523

#define SDHC_EISIER_CMDCRC_ENABLED (SDHC_EISIER_CMDCRC_ENABLED_Val << SDHC_EISIER_CMDCRC_Pos)

1524

#define SDHC_EISIER_CMDEND_Pos 2 /**< \brief (SDHC_EISIER) Command End Bit Error Signal Enable */

1525

#define SDHC_EISIER_CMDEND (_U_(0x1) << SDHC_EISIER_CMDEND_Pos)

1526

#define SDHC_EISIER_CMDEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */

1527

#define SDHC_EISIER_CMDEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */

1528

#define SDHC_EISIER_CMDEND_MASKED (SDHC_EISIER_CMDEND_MASKED_Val << SDHC_EISIER_CMDEND_Pos)

1529

#define SDHC_EISIER_CMDEND_ENABLED (SDHC_EISIER_CMDEND_ENABLED_Val << SDHC_EISIER_CMDEND_Pos)

1530

#define SDHC_EISIER_CMDIDX_Pos 3 /**< \brief (SDHC_EISIER) Command Index Error Signal Enable */

1531

#define SDHC_EISIER_CMDIDX (_U_(0x1) << SDHC_EISIER_CMDIDX_Pos)

1532

#define SDHC_EISIER_CMDIDX_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */

1533

#define SDHC_EISIER_CMDIDX_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */

1534

#define SDHC_EISIER_CMDIDX_MASKED (SDHC_EISIER_CMDIDX_MASKED_Val << SDHC_EISIER_CMDIDX_Pos)

1535

#define SDHC_EISIER_CMDIDX_ENABLED (SDHC_EISIER_CMDIDX_ENABLED_Val << SDHC_EISIER_CMDIDX_Pos)

1536

#define SDHC_EISIER_DATTEO_Pos 4 /**< \brief (SDHC_EISIER) Data Timeout Error Signal Enable */

1537

#define SDHC_EISIER_DATTEO (_U_(0x1) << SDHC_EISIER_DATTEO_Pos)

1538

#define SDHC_EISIER_DATTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */

1539

#define SDHC_EISIER_DATTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */

1540

#define SDHC_EISIER_DATTEO_MASKED (SDHC_EISIER_DATTEO_MASKED_Val << SDHC_EISIER_DATTEO_Pos)

1541

#define SDHC_EISIER_DATTEO_ENABLED (SDHC_EISIER_DATTEO_ENABLED_Val << SDHC_EISIER_DATTEO_Pos)

1542

#define SDHC_EISIER_DATCRC_Pos 5 /**< \brief (SDHC_EISIER) Data CRC Error Signal Enable */

1543

#define SDHC_EISIER_DATCRC (_U_(0x1) << SDHC_EISIER_DATCRC_Pos)

1544

#define SDHC_EISIER_DATCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */

1545

#define SDHC_EISIER_DATCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */

1546

#define SDHC_EISIER_DATCRC_MASKED (SDHC_EISIER_DATCRC_MASKED_Val << SDHC_EISIER_DATCRC_Pos)

1547

#define SDHC_EISIER_DATCRC_ENABLED (SDHC_EISIER_DATCRC_ENABLED_Val << SDHC_EISIER_DATCRC_Pos)

1548

#define SDHC_EISIER_DATEND_Pos 6 /**< \brief (SDHC_EISIER) Data End Bit Error Signal Enable */

1549

#define SDHC_EISIER_DATEND (_U_(0x1) << SDHC_EISIER_DATEND_Pos)

1550

#define SDHC_EISIER_DATEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */

1551

#define SDHC_EISIER_DATEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */

1552

#define SDHC_EISIER_DATEND_MASKED (SDHC_EISIER_DATEND_MASKED_Val << SDHC_EISIER_DATEND_Pos)

1553

#define SDHC_EISIER_DATEND_ENABLED (SDHC_EISIER_DATEND_ENABLED_Val << SDHC_EISIER_DATEND_Pos)

1554

#define SDHC_EISIER_CURLIM_Pos 7 /**< \brief (SDHC_EISIER) Current Limit Error Signal Enable */

1555

#define SDHC_EISIER_CURLIM (_U_(0x1) << SDHC_EISIER_CURLIM_Pos)

1556

#define SDHC_EISIER_CURLIM_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */

1557

#define SDHC_EISIER_CURLIM_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */

1558

#define SDHC_EISIER_CURLIM_MASKED (SDHC_EISIER_CURLIM_MASKED_Val << SDHC_EISIER_CURLIM_Pos)

1559

#define SDHC_EISIER_CURLIM_ENABLED (SDHC_EISIER_CURLIM_ENABLED_Val << SDHC_EISIER_CURLIM_Pos)

1560

#define SDHC_EISIER_ACMD_Pos 8 /**< \brief (SDHC_EISIER) Auto CMD Error Signal Enable */

1561

#define SDHC_EISIER_ACMD (_U_(0x1) << SDHC_EISIER_ACMD_Pos)

1562

#define SDHC_EISIER_ACMD_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */

1563

#define SDHC_EISIER_ACMD_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */

1564

#define SDHC_EISIER_ACMD_MASKED (SDHC_EISIER_ACMD_MASKED_Val << SDHC_EISIER_ACMD_Pos)

1565

#define SDHC_EISIER_ACMD_ENABLED (SDHC_EISIER_ACMD_ENABLED_Val << SDHC_EISIER_ACMD_Pos)

1566

#define SDHC_EISIER_ADMA_Pos 9 /**< \brief (SDHC_EISIER) ADMA Error Signal Enable */

1567

#define SDHC_EISIER_ADMA (_U_(0x1) << SDHC_EISIER_ADMA_Pos)

1568

#define SDHC_EISIER_ADMA_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER) Masked */

1569

#define SDHC_EISIER_ADMA_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER) Enabled */

1570

#define SDHC_EISIER_ADMA_MASKED (SDHC_EISIER_ADMA_MASKED_Val << SDHC_EISIER_ADMA_Pos)

1571

#define SDHC_EISIER_ADMA_ENABLED (SDHC_EISIER_ADMA_ENABLED_Val << SDHC_EISIER_ADMA_Pos)

1572

#define SDHC_EISIER_MASK _U_(0x03FF) /**< \brief (SDHC_EISIER) MASK Register */

1573

1574

// EMMC mode

1575

#define SDHC_EISIER_EMMC_CMDTEO_Pos 0 /**< \brief (SDHC_EISIER_EMMC) Command Timeout Error Signal Enable */

1576

#define SDHC_EISIER_EMMC_CMDTEO (_U_(0x1) << SDHC_EISIER_EMMC_CMDTEO_Pos)

1577

#define SDHC_EISIER_EMMC_CMDTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */

1578

#define SDHC_EISIER_EMMC_CMDTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */

1579

#define SDHC_EISIER_EMMC_CMDTEO_MASKED (SDHC_EISIER_EMMC_CMDTEO_MASKED_Val << SDHC_EISIER_EMMC_CMDTEO_Pos)

1580

#define SDHC_EISIER_EMMC_CMDTEO_ENABLED (SDHC_EISIER_EMMC_CMDTEO_ENABLED_Val << SDHC_EISIER_EMMC_CMDTEO_Pos)

1581

#define SDHC_EISIER_EMMC_CMDCRC_Pos 1 /**< \brief (SDHC_EISIER_EMMC) Command CRC Error Signal Enable */

1582

#define SDHC_EISIER_EMMC_CMDCRC (_U_(0x1) << SDHC_EISIER_EMMC_CMDCRC_Pos)

1583

#define SDHC_EISIER_EMMC_CMDCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */

1584

#define SDHC_EISIER_EMMC_CMDCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */

1585

#define SDHC_EISIER_EMMC_CMDCRC_MASKED (SDHC_EISIER_EMMC_CMDCRC_MASKED_Val << SDHC_EISIER_EMMC_CMDCRC_Pos)

1586

#define SDHC_EISIER_EMMC_CMDCRC_ENABLED (SDHC_EISIER_EMMC_CMDCRC_ENABLED_Val << SDHC_EISIER_EMMC_CMDCRC_Pos)

1587

#define SDHC_EISIER_EMMC_CMDEND_Pos 2 /**< \brief (SDHC_EISIER_EMMC) Command End Bit Error Signal Enable */

1588

#define SDHC_EISIER_EMMC_CMDEND (_U_(0x1) << SDHC_EISIER_EMMC_CMDEND_Pos)

1589

#define SDHC_EISIER_EMMC_CMDEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */

1590

#define SDHC_EISIER_EMMC_CMDEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */

1591

#define SDHC_EISIER_EMMC_CMDEND_MASKED (SDHC_EISIER_EMMC_CMDEND_MASKED_Val << SDHC_EISIER_EMMC_CMDEND_Pos)

1592

#define SDHC_EISIER_EMMC_CMDEND_ENABLED (SDHC_EISIER_EMMC_CMDEND_ENABLED_Val << SDHC_EISIER_EMMC_CMDEND_Pos)

1593

#define SDHC_EISIER_EMMC_CMDIDX_Pos 3 /**< \brief (SDHC_EISIER_EMMC) Command Index Error Signal Enable */

1594

#define SDHC_EISIER_EMMC_CMDIDX (_U_(0x1) << SDHC_EISIER_EMMC_CMDIDX_Pos)

1595

#define SDHC_EISIER_EMMC_CMDIDX_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */

1596

#define SDHC_EISIER_EMMC_CMDIDX_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */

1597

#define SDHC_EISIER_EMMC_CMDIDX_MASKED (SDHC_EISIER_EMMC_CMDIDX_MASKED_Val << SDHC_EISIER_EMMC_CMDIDX_Pos)

1598

#define SDHC_EISIER_EMMC_CMDIDX_ENABLED (SDHC_EISIER_EMMC_CMDIDX_ENABLED_Val << SDHC_EISIER_EMMC_CMDIDX_Pos)

1599

#define SDHC_EISIER_EMMC_DATTEO_Pos 4 /**< \brief (SDHC_EISIER_EMMC) Data Timeout Error Signal Enable */

1600

#define SDHC_EISIER_EMMC_DATTEO (_U_(0x1) << SDHC_EISIER_EMMC_DATTEO_Pos)

1601

#define SDHC_EISIER_EMMC_DATTEO_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */

1602

#define SDHC_EISIER_EMMC_DATTEO_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */

1603

#define SDHC_EISIER_EMMC_DATTEO_MASKED (SDHC_EISIER_EMMC_DATTEO_MASKED_Val << SDHC_EISIER_EMMC_DATTEO_Pos)

1604

#define SDHC_EISIER_EMMC_DATTEO_ENABLED (SDHC_EISIER_EMMC_DATTEO_ENABLED_Val << SDHC_EISIER_EMMC_DATTEO_Pos)

1605

#define SDHC_EISIER_EMMC_DATCRC_Pos 5 /**< \brief (SDHC_EISIER_EMMC) Data CRC Error Signal Enable */

1606

#define SDHC_EISIER_EMMC_DATCRC (_U_(0x1) << SDHC_EISIER_EMMC_DATCRC_Pos)

1607

#define SDHC_EISIER_EMMC_DATCRC_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */

1608

#define SDHC_EISIER_EMMC_DATCRC_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */

1609

#define SDHC_EISIER_EMMC_DATCRC_MASKED (SDHC_EISIER_EMMC_DATCRC_MASKED_Val << SDHC_EISIER_EMMC_DATCRC_Pos)

1610

#define SDHC_EISIER_EMMC_DATCRC_ENABLED (SDHC_EISIER_EMMC_DATCRC_ENABLED_Val << SDHC_EISIER_EMMC_DATCRC_Pos)

1611

#define SDHC_EISIER_EMMC_DATEND_Pos 6 /**< \brief (SDHC_EISIER_EMMC) Data End Bit Error Signal Enable */

1612

#define SDHC_EISIER_EMMC_DATEND (_U_(0x1) << SDHC_EISIER_EMMC_DATEND_Pos)

1613

#define SDHC_EISIER_EMMC_DATEND_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */

1614

#define SDHC_EISIER_EMMC_DATEND_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */

1615

#define SDHC_EISIER_EMMC_DATEND_MASKED (SDHC_EISIER_EMMC_DATEND_MASKED_Val << SDHC_EISIER_EMMC_DATEND_Pos)

1616

#define SDHC_EISIER_EMMC_DATEND_ENABLED (SDHC_EISIER_EMMC_DATEND_ENABLED_Val << SDHC_EISIER_EMMC_DATEND_Pos)

1617

#define SDHC_EISIER_EMMC_CURLIM_Pos 7 /**< \brief (SDHC_EISIER_EMMC) Current Limit Error Signal Enable */

1618

#define SDHC_EISIER_EMMC_CURLIM (_U_(0x1) << SDHC_EISIER_EMMC_CURLIM_Pos)

1619

#define SDHC_EISIER_EMMC_CURLIM_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */

1620

#define SDHC_EISIER_EMMC_CURLIM_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */

1621

#define SDHC_EISIER_EMMC_CURLIM_MASKED (SDHC_EISIER_EMMC_CURLIM_MASKED_Val << SDHC_EISIER_EMMC_CURLIM_Pos)

1622

#define SDHC_EISIER_EMMC_CURLIM_ENABLED (SDHC_EISIER_EMMC_CURLIM_ENABLED_Val << SDHC_EISIER_EMMC_CURLIM_Pos)

1623

#define SDHC_EISIER_EMMC_ACMD_Pos 8 /**< \brief (SDHC_EISIER_EMMC) Auto CMD Error Signal Enable */

1624

#define SDHC_EISIER_EMMC_ACMD (_U_(0x1) << SDHC_EISIER_EMMC_ACMD_Pos)

1625

#define SDHC_EISIER_EMMC_ACMD_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */

1626

#define SDHC_EISIER_EMMC_ACMD_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */

1627

#define SDHC_EISIER_EMMC_ACMD_MASKED (SDHC_EISIER_EMMC_ACMD_MASKED_Val << SDHC_EISIER_EMMC_ACMD_Pos)

1628

#define SDHC_EISIER_EMMC_ACMD_ENABLED (SDHC_EISIER_EMMC_ACMD_ENABLED_Val << SDHC_EISIER_EMMC_ACMD_Pos)

1629

#define SDHC_EISIER_EMMC_ADMA_Pos 9 /**< \brief (SDHC_EISIER_EMMC) ADMA Error Signal Enable */

1630

#define SDHC_EISIER_EMMC_ADMA (_U_(0x1) << SDHC_EISIER_EMMC_ADMA_Pos)

1631

#define SDHC_EISIER_EMMC_ADMA_MASKED_Val _U_(0x0) /**< \brief (SDHC_EISIER_EMMC) Masked */

1632

#define SDHC_EISIER_EMMC_ADMA_ENABLED_Val _U_(0x1) /**< \brief (SDHC_EISIER_EMMC) Enabled */

1633

#define SDHC_EISIER_EMMC_ADMA_MASKED (SDHC_EISIER_EMMC_ADMA_MASKED_Val << SDHC_EISIER_EMMC_ADMA_Pos)

1634

#define SDHC_EISIER_EMMC_ADMA_ENABLED (SDHC_EISIER_EMMC_ADMA_ENABLED_Val << SDHC_EISIER_EMMC_ADMA_Pos)

1635

#define SDHC_EISIER_EMMC_BOOTAE_Pos 12 /**< \brief (SDHC_EISIER_EMMC) Boot Acknowledge Error Signal Enable */

1636

#define SDHC_EISIER_EMMC_BOOTAE (_U_(0x1) << SDHC_EISIER_EMMC_BOOTAE_Pos)

1637

#define SDHC_EISIER_EMMC_MASK _U_(0x13FF) /**< \brief (SDHC_EISIER_EMMC) MASK Register */

1638

1639

/* -------- SDHC_ACESR : (SDHC Offset: 0x03C) (R/ 16) Auto CMD Error Status -------- */

1640

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

1641

typedef union {

1642

struct {

1643

uint16_t ACMD12NE:1; /*!< bit: 0 Auto CMD12 Not Executed */

1644

uint16_t ACMDTEO:1; /*!< bit: 1 Auto CMD Timeout Error */

1645

uint16_t ACMDCRC:1; /*!< bit: 2 Auto CMD CRC Error */

1646

uint16_t ACMDEND:1; /*!< bit: 3 Auto CMD End Bit Error */

1647

uint16_t ACMDIDX:1; /*!< bit: 4 Auto CMD Index Error */

1648

uint16_t :2; /*!< bit: 5.. 6 Reserved */

1649

uint16_t CMDNI:1; /*!< bit: 7 Command not Issued By Auto CMD12 Error */

1650

uint16_t :8; /*!< bit: 8..15 Reserved */

1651

} bit; /*!< Structure used for bit access */

1652

uint16_t reg; /*!< Type used for register access */

1653

} SDHC_ACESR_Type;

1654

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

1655

1656

#define SDHC_ACESR_OFFSET 0x03C /**< \brief (SDHC_ACESR offset) Auto CMD Error Status */

1657

#define SDHC_ACESR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_ACESR reset_value) Auto CMD Error Status */

1658

1659

#define SDHC_ACESR_ACMD12NE_Pos 0 /**< \brief (SDHC_ACESR) Auto CMD12 Not Executed */

1660

#define SDHC_ACESR_ACMD12NE (_U_(0x1) << SDHC_ACESR_ACMD12NE_Pos)

1661

#define SDHC_ACESR_ACMD12NE_EXEC_Val _U_(0x0) /**< \brief (SDHC_ACESR) Executed */

1662

#define SDHC_ACESR_ACMD12NE_NOT_EXEC_Val _U_(0x1) /**< \brief (SDHC_ACESR) Not executed */

1663

#define SDHC_ACESR_ACMD12NE_EXEC (SDHC_ACESR_ACMD12NE_EXEC_Val << SDHC_ACESR_ACMD12NE_Pos)

1664

#define SDHC_ACESR_ACMD12NE_NOT_EXEC (SDHC_ACESR_ACMD12NE_NOT_EXEC_Val << SDHC_ACESR_ACMD12NE_Pos)

1665

#define SDHC_ACESR_ACMDTEO_Pos 1 /**< \brief (SDHC_ACESR) Auto CMD Timeout Error */

1666

#define SDHC_ACESR_ACMDTEO (_U_(0x1) << SDHC_ACESR_ACMDTEO_Pos)

1667

#define SDHC_ACESR_ACMDTEO_NO_Val _U_(0x0) /**< \brief (SDHC_ACESR) No error */

1668

#define SDHC_ACESR_ACMDTEO_YES_Val _U_(0x1) /**< \brief (SDHC_ACESR) Timeout */

1669

#define SDHC_ACESR_ACMDTEO_NO (SDHC_ACESR_ACMDTEO_NO_Val << SDHC_ACESR_ACMDTEO_Pos)

1670

#define SDHC_ACESR_ACMDTEO_YES (SDHC_ACESR_ACMDTEO_YES_Val << SDHC_ACESR_ACMDTEO_Pos)

1671

#define SDHC_ACESR_ACMDCRC_Pos 2 /**< \brief (SDHC_ACESR) Auto CMD CRC Error */

1672

#define SDHC_ACESR_ACMDCRC (_U_(0x1) << SDHC_ACESR_ACMDCRC_Pos)

1673

#define SDHC_ACESR_ACMDCRC_NO_Val _U_(0x0) /**< \brief (SDHC_ACESR) No error */

1674

#define SDHC_ACESR_ACMDCRC_YES_Val _U_(0x1) /**< \brief (SDHC_ACESR) CRC Error Generated */

1675

#define SDHC_ACESR_ACMDCRC_NO (SDHC_ACESR_ACMDCRC_NO_Val << SDHC_ACESR_ACMDCRC_Pos)

1676

#define SDHC_ACESR_ACMDCRC_YES (SDHC_ACESR_ACMDCRC_YES_Val << SDHC_ACESR_ACMDCRC_Pos)

1677

#define SDHC_ACESR_ACMDEND_Pos 3 /**< \brief (SDHC_ACESR) Auto CMD End Bit Error */

1678

#define SDHC_ACESR_ACMDEND (_U_(0x1) << SDHC_ACESR_ACMDEND_Pos)

1679

#define SDHC_ACESR_ACMDEND_NO_Val _U_(0x0) /**< \brief (SDHC_ACESR) No error */

1680

#define SDHC_ACESR_ACMDEND_YES_Val _U_(0x1) /**< \brief (SDHC_ACESR) End Bit Error Generated */

1681

#define SDHC_ACESR_ACMDEND_NO (SDHC_ACESR_ACMDEND_NO_Val << SDHC_ACESR_ACMDEND_Pos)

1682

#define SDHC_ACESR_ACMDEND_YES (SDHC_ACESR_ACMDEND_YES_Val << SDHC_ACESR_ACMDEND_Pos)

1683

#define SDHC_ACESR_ACMDIDX_Pos 4 /**< \brief (SDHC_ACESR) Auto CMD Index Error */

1684

#define SDHC_ACESR_ACMDIDX (_U_(0x1) << SDHC_ACESR_ACMDIDX_Pos)

1685

#define SDHC_ACESR_ACMDIDX_NO_Val _U_(0x0) /**< \brief (SDHC_ACESR) No error */

1686

#define SDHC_ACESR_ACMDIDX_YES_Val _U_(0x1) /**< \brief (SDHC_ACESR) Error */

1687

#define SDHC_ACESR_ACMDIDX_NO (SDHC_ACESR_ACMDIDX_NO_Val << SDHC_ACESR_ACMDIDX_Pos)

1688

#define SDHC_ACESR_ACMDIDX_YES (SDHC_ACESR_ACMDIDX_YES_Val << SDHC_ACESR_ACMDIDX_Pos)

1689

#define SDHC_ACESR_CMDNI_Pos 7 /**< \brief (SDHC_ACESR) Command not Issued By Auto CMD12 Error */

1690

#define SDHC_ACESR_CMDNI (_U_(0x1) << SDHC_ACESR_CMDNI_Pos)

1691

#define SDHC_ACESR_CMDNI_OK_Val _U_(0x0) /**< \brief (SDHC_ACESR) No error */

1692

#define SDHC_ACESR_CMDNI_NOT_ISSUED_Val _U_(0x1) /**< \brief (SDHC_ACESR) Not Issued */

1693

#define SDHC_ACESR_CMDNI_OK (SDHC_ACESR_CMDNI_OK_Val << SDHC_ACESR_CMDNI_Pos)

1694

#define SDHC_ACESR_CMDNI_NOT_ISSUED (SDHC_ACESR_CMDNI_NOT_ISSUED_Val << SDHC_ACESR_CMDNI_Pos)

1695

#define SDHC_ACESR_MASK _U_(0x009F) /**< \brief (SDHC_ACESR) MASK Register */

1696

1697

/* -------- SDHC_HC2R : (SDHC Offset: 0x03E) (R/W 16) Host Control 2 -------- */

1698

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

1699

typedef union {

1700

struct {

1701

uint16_t UHSMS:3; /*!< bit: 0.. 2 UHS Mode Select */

1702

uint16_t VS18EN:1; /*!< bit: 3 1.8V Signaling Enable */

1703

uint16_t DRVSEL:2; /*!< bit: 4.. 5 Driver Strength Select */

1704

uint16_t EXTUN:1; /*!< bit: 6 Execute Tuning */

1705

uint16_t SLCKSEL:1; /*!< bit: 7 Sampling Clock Select */

1706

uint16_t :6; /*!< bit: 8..13 Reserved */

1707

uint16_t ASINTEN:1; /*!< bit: 14 Asynchronous Interrupt Enable */

1708

uint16_t PVALEN:1; /*!< bit: 15 Preset Value Enable */

1709

} bit; /*!< Structure used for bit access */

1710

struct { // EMMC mode

1711

uint16_t HS200EN:4; /*!< bit: 0.. 3 HS200 Mode Enable */

1712

uint16_t DRVSEL:2; /*!< bit: 4.. 5 Driver Strength Select */

1713

uint16_t EXTUN:1; /*!< bit: 6 Execute Tuning */

1714

uint16_t SLCKSEL:1; /*!< bit: 7 Sampling Clock Select */

1715

uint16_t :7; /*!< bit: 8..14 Reserved */

1716

uint16_t PVALEN:1; /*!< bit: 15 Preset Value Enable */

1717

} EMMC; /*!< Structure used for EMMC */

1718

uint16_t reg; /*!< Type used for register access */

1719

} SDHC_HC2R_Type;

1720

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

1721

1722

#define SDHC_HC2R_OFFSET 0x03E /**< \brief (SDHC_HC2R offset) Host Control 2 */

1723

#define SDHC_HC2R_RESETVALUE _U_(0x0000) /**< \brief (SDHC_HC2R reset_value) Host Control 2 */

1724

1725

#define SDHC_HC2R_UHSMS_Pos 0 /**< \brief (SDHC_HC2R) UHS Mode Select */

1726

#define SDHC_HC2R_UHSMS_Msk (_U_(0x7) << SDHC_HC2R_UHSMS_Pos)

1727

#define SDHC_HC2R_UHSMS(value) (SDHC_HC2R_UHSMS_Msk & ((value) << SDHC_HC2R_UHSMS_Pos))

1728

#define SDHC_HC2R_UHSMS_SDR12_Val _U_(0x0) /**< \brief (SDHC_HC2R) SDR12 */

1729

#define SDHC_HC2R_UHSMS_SDR25_Val _U_(0x1) /**< \brief (SDHC_HC2R) SDR25 */

1730

#define SDHC_HC2R_UHSMS_SDR50_Val _U_(0x2) /**< \brief (SDHC_HC2R) SDR50 */

1731

#define SDHC_HC2R_UHSMS_SDR104_Val _U_(0x3) /**< \brief (SDHC_HC2R) SDR104 */

1732

#define SDHC_HC2R_UHSMS_DDR50_Val _U_(0x4) /**< \brief (SDHC_HC2R) DDR50 */

1733

#define SDHC_HC2R_UHSMS_SDR12 (SDHC_HC2R_UHSMS_SDR12_Val << SDHC_HC2R_UHSMS_Pos)

1734

#define SDHC_HC2R_UHSMS_SDR25 (SDHC_HC2R_UHSMS_SDR25_Val << SDHC_HC2R_UHSMS_Pos)

1735

#define SDHC_HC2R_UHSMS_SDR50 (SDHC_HC2R_UHSMS_SDR50_Val << SDHC_HC2R_UHSMS_Pos)

1736

#define SDHC_HC2R_UHSMS_SDR104 (SDHC_HC2R_UHSMS_SDR104_Val << SDHC_HC2R_UHSMS_Pos)

1737

#define SDHC_HC2R_UHSMS_DDR50 (SDHC_HC2R_UHSMS_DDR50_Val << SDHC_HC2R_UHSMS_Pos)

1738

#define SDHC_HC2R_VS18EN_Pos 3 /**< \brief (SDHC_HC2R) 1.8V Signaling Enable */

1739

#define SDHC_HC2R_VS18EN (_U_(0x1) << SDHC_HC2R_VS18EN_Pos)

1740

#define SDHC_HC2R_VS18EN_S33V_Val _U_(0x0) /**< \brief (SDHC_HC2R) 3.3V Signaling */

1741

#define SDHC_HC2R_VS18EN_S18V_Val _U_(0x1) /**< \brief (SDHC_HC2R) 1.8V Signaling */

1742

#define SDHC_HC2R_VS18EN_S33V (SDHC_HC2R_VS18EN_S33V_Val << SDHC_HC2R_VS18EN_Pos)

1743

#define SDHC_HC2R_VS18EN_S18V (SDHC_HC2R_VS18EN_S18V_Val << SDHC_HC2R_VS18EN_Pos)

1744

#define SDHC_HC2R_DRVSEL_Pos 4 /**< \brief (SDHC_HC2R) Driver Strength Select */

1745

#define SDHC_HC2R_DRVSEL_Msk (_U_(0x3) << SDHC_HC2R_DRVSEL_Pos)

1746

#define SDHC_HC2R_DRVSEL(value) (SDHC_HC2R_DRVSEL_Msk & ((value) << SDHC_HC2R_DRVSEL_Pos))

1747

#define SDHC_HC2R_DRVSEL_B_Val _U_(0x0) /**< \brief (SDHC_HC2R) Driver Type B is Selected (Default) */

1748

#define SDHC_HC2R_DRVSEL_A_Val _U_(0x1) /**< \brief (SDHC_HC2R) Driver Type A is Selected */

1749

#define SDHC_HC2R_DRVSEL_C_Val _U_(0x2) /**< \brief (SDHC_HC2R) Driver Type C is Selected */

1750

#define SDHC_HC2R_DRVSEL_D_Val _U_(0x3) /**< \brief (SDHC_HC2R) Driver Type D is Selected */

1751

#define SDHC_HC2R_DRVSEL_B (SDHC_HC2R_DRVSEL_B_Val << SDHC_HC2R_DRVSEL_Pos)

1752

#define SDHC_HC2R_DRVSEL_A (SDHC_HC2R_DRVSEL_A_Val << SDHC_HC2R_DRVSEL_Pos)

1753

#define SDHC_HC2R_DRVSEL_C (SDHC_HC2R_DRVSEL_C_Val << SDHC_HC2R_DRVSEL_Pos)

1754

#define SDHC_HC2R_DRVSEL_D (SDHC_HC2R_DRVSEL_D_Val << SDHC_HC2R_DRVSEL_Pos)

1755

#define SDHC_HC2R_EXTUN_Pos 6 /**< \brief (SDHC_HC2R) Execute Tuning */

1756

#define SDHC_HC2R_EXTUN (_U_(0x1) << SDHC_HC2R_EXTUN_Pos)

1757

#define SDHC_HC2R_EXTUN_NO_Val _U_(0x0) /**< \brief (SDHC_HC2R) Not Tuned or Tuning Completed */

1758

#define SDHC_HC2R_EXTUN_REQUESTED_Val _U_(0x1) /**< \brief (SDHC_HC2R) Execute Tuning */

1759

#define SDHC_HC2R_EXTUN_NO (SDHC_HC2R_EXTUN_NO_Val << SDHC_HC2R_EXTUN_Pos)

1760

#define SDHC_HC2R_EXTUN_REQUESTED (SDHC_HC2R_EXTUN_REQUESTED_Val << SDHC_HC2R_EXTUN_Pos)

1761

#define SDHC_HC2R_SLCKSEL_Pos 7 /**< \brief (SDHC_HC2R) Sampling Clock Select */

1762

#define SDHC_HC2R_SLCKSEL (_U_(0x1) << SDHC_HC2R_SLCKSEL_Pos)

1763

#define SDHC_HC2R_SLCKSEL_FIXED_Val _U_(0x0) /**< \brief (SDHC_HC2R) Fixed clock is used to sample data */

1764

#define SDHC_HC2R_SLCKSEL_TUNED_Val _U_(0x1) /**< \brief (SDHC_HC2R) Tuned clock is used to sample data */

1765

#define SDHC_HC2R_SLCKSEL_FIXED (SDHC_HC2R_SLCKSEL_FIXED_Val << SDHC_HC2R_SLCKSEL_Pos)

1766

#define SDHC_HC2R_SLCKSEL_TUNED (SDHC_HC2R_SLCKSEL_TUNED_Val << SDHC_HC2R_SLCKSEL_Pos)

1767

#define SDHC_HC2R_ASINTEN_Pos 14 /**< \brief (SDHC_HC2R) Asynchronous Interrupt Enable */

1768

#define SDHC_HC2R_ASINTEN (_U_(0x1) << SDHC_HC2R_ASINTEN_Pos)

1769

#define SDHC_HC2R_ASINTEN_DISABLED_Val _U_(0x0) /**< \brief (SDHC_HC2R) Disabled */

1770

#define SDHC_HC2R_ASINTEN_ENABLED_Val _U_(0x1) /**< \brief (SDHC_HC2R) Enabled */

1771

#define SDHC_HC2R_ASINTEN_DISABLED (SDHC_HC2R_ASINTEN_DISABLED_Val << SDHC_HC2R_ASINTEN_Pos)

1772

#define SDHC_HC2R_ASINTEN_ENABLED (SDHC_HC2R_ASINTEN_ENABLED_Val << SDHC_HC2R_ASINTEN_Pos)

1773

#define SDHC_HC2R_PVALEN_Pos 15 /**< \brief (SDHC_HC2R) Preset Value Enable */

1774

#define SDHC_HC2R_PVALEN (_U_(0x1) << SDHC_HC2R_PVALEN_Pos)

1775

#define SDHC_HC2R_PVALEN_HOST_Val _U_(0x0) /**< \brief (SDHC_HC2R) SDCLK and Driver Strength are controlled by Host Controller */

1776

#define SDHC_HC2R_PVALEN_AUTO_Val _U_(0x1) /**< \brief (SDHC_HC2R) Automatic Selection by Preset Value is Enabled */

1777

#define SDHC_HC2R_PVALEN_HOST (SDHC_HC2R_PVALEN_HOST_Val << SDHC_HC2R_PVALEN_Pos)

1778

#define SDHC_HC2R_PVALEN_AUTO (SDHC_HC2R_PVALEN_AUTO_Val << SDHC_HC2R_PVALEN_Pos)

1779

#define SDHC_HC2R_MASK _U_(0xC0FF) /**< \brief (SDHC_HC2R) MASK Register */

1780

1781

// EMMC mode

1782

#define SDHC_HC2R_EMMC_HS200EN_Pos 0 /**< \brief (SDHC_HC2R_EMMC) HS200 Mode Enable */

1783

#define SDHC_HC2R_EMMC_HS200EN_Msk (_U_(0xF) << SDHC_HC2R_EMMC_HS200EN_Pos)

1784

#define SDHC_HC2R_EMMC_HS200EN(value) (SDHC_HC2R_EMMC_HS200EN_Msk & ((value) << SDHC_HC2R_EMMC_HS200EN_Pos))

1785

#define SDHC_HC2R_EMMC_HS200EN_SDR12_Val _U_(0x0) /**< \brief (SDHC_HC2R_EMMC) SDR12 */

1786

#define SDHC_HC2R_EMMC_HS200EN_SDR25_Val _U_(0x1) /**< \brief (SDHC_HC2R_EMMC) SDR25 */

1787

#define SDHC_HC2R_EMMC_HS200EN_SDR50_Val _U_(0x2) /**< \brief (SDHC_HC2R_EMMC) SDR50 */

1788

#define SDHC_HC2R_EMMC_HS200EN_SDR104_Val _U_(0x3) /**< \brief (SDHC_HC2R_EMMC) SDR104 */

1789

#define SDHC_HC2R_EMMC_HS200EN_DDR50_Val _U_(0x4) /**< \brief (SDHC_HC2R_EMMC) DDR50 */

1790

#define SDHC_HC2R_EMMC_HS200EN_SDR12 (SDHC_HC2R_EMMC_HS200EN_SDR12_Val << SDHC_HC2R_EMMC_HS200EN_Pos)

1791

#define SDHC_HC2R_EMMC_HS200EN_SDR25 (SDHC_HC2R_EMMC_HS200EN_SDR25_Val << SDHC_HC2R_EMMC_HS200EN_Pos)

1792

#define SDHC_HC2R_EMMC_HS200EN_SDR50 (SDHC_HC2R_EMMC_HS200EN_SDR50_Val << SDHC_HC2R_EMMC_HS200EN_Pos)

1793

#define SDHC_HC2R_EMMC_HS200EN_SDR104 (SDHC_HC2R_EMMC_HS200EN_SDR104_Val << SDHC_HC2R_EMMC_HS200EN_Pos)

1794

#define SDHC_HC2R_EMMC_HS200EN_DDR50 (SDHC_HC2R_EMMC_HS200EN_DDR50_Val << SDHC_HC2R_EMMC_HS200EN_Pos)

1795

#define SDHC_HC2R_EMMC_DRVSEL_Pos 4 /**< \brief (SDHC_HC2R_EMMC) Driver Strength Select */

1796

#define SDHC_HC2R_EMMC_DRVSEL_Msk (_U_(0x3) << SDHC_HC2R_EMMC_DRVSEL_Pos)

1797

#define SDHC_HC2R_EMMC_DRVSEL(value) (SDHC_HC2R_EMMC_DRVSEL_Msk & ((value) << SDHC_HC2R_EMMC_DRVSEL_Pos))

1798

#define SDHC_HC2R_EMMC_DRVSEL_B_Val _U_(0x0) /**< \brief (SDHC_HC2R_EMMC) Driver Type B is Selected (Default) */

1799

#define SDHC_HC2R_EMMC_DRVSEL_A_Val _U_(0x1) /**< \brief (SDHC_HC2R_EMMC) Driver Type A is Selected */

1800

#define SDHC_HC2R_EMMC_DRVSEL_C_Val _U_(0x2) /**< \brief (SDHC_HC2R_EMMC) Driver Type C is Selected */

1801

#define SDHC_HC2R_EMMC_DRVSEL_D_Val _U_(0x3) /**< \brief (SDHC_HC2R_EMMC) Driver Type D is Selected */

1802

#define SDHC_HC2R_EMMC_DRVSEL_B (SDHC_HC2R_EMMC_DRVSEL_B_Val << SDHC_HC2R_EMMC_DRVSEL_Pos)

1803

#define SDHC_HC2R_EMMC_DRVSEL_A (SDHC_HC2R_EMMC_DRVSEL_A_Val << SDHC_HC2R_EMMC_DRVSEL_Pos)

1804

#define SDHC_HC2R_EMMC_DRVSEL_C (SDHC_HC2R_EMMC_DRVSEL_C_Val << SDHC_HC2R_EMMC_DRVSEL_Pos)

1805

#define SDHC_HC2R_EMMC_DRVSEL_D (SDHC_HC2R_EMMC_DRVSEL_D_Val << SDHC_HC2R_EMMC_DRVSEL_Pos)

1806

#define SDHC_HC2R_EMMC_EXTUN_Pos 6 /**< \brief (SDHC_HC2R_EMMC) Execute Tuning */

1807

#define SDHC_HC2R_EMMC_EXTUN (_U_(0x1) << SDHC_HC2R_EMMC_EXTUN_Pos)

1808

#define SDHC_HC2R_EMMC_EXTUN_NO_Val _U_(0x0) /**< \brief (SDHC_HC2R_EMMC) Not Tuned or Tuning Completed */

1809

#define SDHC_HC2R_EMMC_EXTUN_REQUESTED_Val _U_(0x1) /**< \brief (SDHC_HC2R_EMMC) Execute Tuning */

1810

#define SDHC_HC2R_EMMC_EXTUN_NO (SDHC_HC2R_EMMC_EXTUN_NO_Val << SDHC_HC2R_EMMC_EXTUN_Pos)

1811

#define SDHC_HC2R_EMMC_EXTUN_REQUESTED (SDHC_HC2R_EMMC_EXTUN_REQUESTED_Val << SDHC_HC2R_EMMC_EXTUN_Pos)

1812

#define SDHC_HC2R_EMMC_SLCKSEL_Pos 7 /**< \brief (SDHC_HC2R_EMMC) Sampling Clock Select */

1813

#define SDHC_HC2R_EMMC_SLCKSEL (_U_(0x1) << SDHC_HC2R_EMMC_SLCKSEL_Pos)

1814

#define SDHC_HC2R_EMMC_SLCKSEL_FIXED_Val _U_(0x0) /**< \brief (SDHC_HC2R_EMMC) Fixed clock is used to sample data */

1815

#define SDHC_HC2R_EMMC_SLCKSEL_TUNED_Val _U_(0x1) /**< \brief (SDHC_HC2R_EMMC) Tuned clock is used to sample data */

1816

#define SDHC_HC2R_EMMC_SLCKSEL_FIXED (SDHC_HC2R_EMMC_SLCKSEL_FIXED_Val << SDHC_HC2R_EMMC_SLCKSEL_Pos)

1817

#define SDHC_HC2R_EMMC_SLCKSEL_TUNED (SDHC_HC2R_EMMC_SLCKSEL_TUNED_Val << SDHC_HC2R_EMMC_SLCKSEL_Pos)

1818

#define SDHC_HC2R_EMMC_PVALEN_Pos 15 /**< \brief (SDHC_HC2R_EMMC) Preset Value Enable */

1819

#define SDHC_HC2R_EMMC_PVALEN (_U_(0x1) << SDHC_HC2R_EMMC_PVALEN_Pos)

1820

#define SDHC_HC2R_EMMC_PVALEN_HOST_Val _U_(0x0) /**< \brief (SDHC_HC2R_EMMC) SDCLK and Driver Strength are controlled by Host Controller */

1821

#define SDHC_HC2R_EMMC_PVALEN_AUTO_Val _U_(0x1) /**< \brief (SDHC_HC2R_EMMC) Automatic Selection by Preset Value is Enabled */

1822

#define SDHC_HC2R_EMMC_PVALEN_HOST (SDHC_HC2R_EMMC_PVALEN_HOST_Val << SDHC_HC2R_EMMC_PVALEN_Pos)

1823

#define SDHC_HC2R_EMMC_PVALEN_AUTO (SDHC_HC2R_EMMC_PVALEN_AUTO_Val << SDHC_HC2R_EMMC_PVALEN_Pos)

1824

#define SDHC_HC2R_EMMC_MASK _U_(0x80FF) /**< \brief (SDHC_HC2R_EMMC) MASK Register */

1825

1826

/* -------- SDHC_CA0R : (SDHC Offset: 0x040) (R/ 32) Capabilities 0 -------- */

1827

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

1828

typedef union {

1829

struct {

1830

uint32_t TEOCLKF:6; /*!< bit: 0.. 5 Timeout Clock Frequency */

1831

uint32_t :1; /*!< bit: 6 Reserved */

1832

uint32_t TEOCLKU:1; /*!< bit: 7 Timeout Clock Unit */

1833

uint32_t BASECLKF:8; /*!< bit: 8..15 Base Clock Frequency */

1834

uint32_t MAXBLKL:2; /*!< bit: 16..17 Max Block Length */

1835

uint32_t ED8SUP:1; /*!< bit: 18 8-bit Support for Embedded Device */

1836

uint32_t ADMA2SUP:1; /*!< bit: 19 ADMA2 Support */

1837

uint32_t :1; /*!< bit: 20 Reserved */

1838

uint32_t HSSUP:1; /*!< bit: 21 High Speed Support */

1839

uint32_t SDMASUP:1; /*!< bit: 22 SDMA Support */

1840

uint32_t SRSUP:1; /*!< bit: 23 Suspend/Resume Support */

1841

uint32_t V33VSUP:1; /*!< bit: 24 Voltage Support 3.3V */

1842

uint32_t V30VSUP:1; /*!< bit: 25 Voltage Support 3.0V */

1843

uint32_t V18VSUP:1; /*!< bit: 26 Voltage Support 1.8V */

1844

uint32_t :1; /*!< bit: 27 Reserved */

1845

uint32_t SB64SUP:1; /*!< bit: 28 64-Bit System Bus Support */

1846

uint32_t ASINTSUP:1; /*!< bit: 29 Asynchronous Interrupt Support */

1847

uint32_t SLTYPE:2; /*!< bit: 30..31 Slot Type */

1848

} bit; /*!< Structure used for bit access */

1849

uint32_t reg; /*!< Type used for register access */

1850

} SDHC_CA0R_Type;

1851

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

1852

1853

#define SDHC_CA0R_OFFSET 0x040 /**< \brief (SDHC_CA0R offset) Capabilities 0 */

1854

#define SDHC_CA0R_RESETVALUE _U_(0x27E80080) /**< \brief (SDHC_CA0R reset_value) Capabilities 0 */

1855

1856

#define SDHC_CA0R_TEOCLKF_Pos 0 /**< \brief (SDHC_CA0R) Timeout Clock Frequency */

1857

#define SDHC_CA0R_TEOCLKF_Msk (_U_(0x3F) << SDHC_CA0R_TEOCLKF_Pos)

1858

#define SDHC_CA0R_TEOCLKF(value) (SDHC_CA0R_TEOCLKF_Msk & ((value) << SDHC_CA0R_TEOCLKF_Pos))

1859

#define SDHC_CA0R_TEOCLKF_OTHER_Val _U_(0x0) /**< \brief (SDHC_CA0R) Get information via another method */

1860

#define SDHC_CA0R_TEOCLKF_OTHER (SDHC_CA0R_TEOCLKF_OTHER_Val << SDHC_CA0R_TEOCLKF_Pos)

1861

#define SDHC_CA0R_TEOCLKU_Pos 7 /**< \brief (SDHC_CA0R) Timeout Clock Unit */

1862

#define SDHC_CA0R_TEOCLKU (_U_(0x1) << SDHC_CA0R_TEOCLKU_Pos)

1863

#define SDHC_CA0R_TEOCLKU_KHZ_Val _U_(0x0) /**< \brief (SDHC_CA0R) kHz */

1864

#define SDHC_CA0R_TEOCLKU_MHZ_Val _U_(0x1) /**< \brief (SDHC_CA0R) MHz */

1865

#define SDHC_CA0R_TEOCLKU_KHZ (SDHC_CA0R_TEOCLKU_KHZ_Val << SDHC_CA0R_TEOCLKU_Pos)

1866

#define SDHC_CA0R_TEOCLKU_MHZ (SDHC_CA0R_TEOCLKU_MHZ_Val << SDHC_CA0R_TEOCLKU_Pos)

1867

#define SDHC_CA0R_BASECLKF_Pos 8 /**< \brief (SDHC_CA0R) Base Clock Frequency */

1868

#define SDHC_CA0R_BASECLKF_Msk (_U_(0xFF) << SDHC_CA0R_BASECLKF_Pos)

1869

#define SDHC_CA0R_BASECLKF(value) (SDHC_CA0R_BASECLKF_Msk & ((value) << SDHC_CA0R_BASECLKF_Pos))

1870

#define SDHC_CA0R_BASECLKF_OTHER_Val _U_(0x0) /**< \brief (SDHC_CA0R) Get information via another method */

1871

#define SDHC_CA0R_BASECLKF_OTHER (SDHC_CA0R_BASECLKF_OTHER_Val << SDHC_CA0R_BASECLKF_Pos)

1872

#define SDHC_CA0R_MAXBLKL_Pos 16 /**< \brief (SDHC_CA0R) Max Block Length */

1873

#define SDHC_CA0R_MAXBLKL_Msk (_U_(0x3) << SDHC_CA0R_MAXBLKL_Pos)

1874

#define SDHC_CA0R_MAXBLKL(value) (SDHC_CA0R_MAXBLKL_Msk & ((value) << SDHC_CA0R_MAXBLKL_Pos))

1875

#define SDHC_CA0R_MAXBLKL_512_Val _U_(0x0) /**< \brief (SDHC_CA0R) 512 bytes */

1876

#define SDHC_CA0R_MAXBLKL_1024_Val _U_(0x1) /**< \brief (SDHC_CA0R) 1024 bytes */

1877

#define SDHC_CA0R_MAXBLKL_2048_Val _U_(0x2) /**< \brief (SDHC_CA0R) 2048 bytes */

1878

#define SDHC_CA0R_MAXBLKL_512 (SDHC_CA0R_MAXBLKL_512_Val << SDHC_CA0R_MAXBLKL_Pos)

1879

#define SDHC_CA0R_MAXBLKL_1024 (SDHC_CA0R_MAXBLKL_1024_Val << SDHC_CA0R_MAXBLKL_Pos)

1880

#define SDHC_CA0R_MAXBLKL_2048 (SDHC_CA0R_MAXBLKL_2048_Val << SDHC_CA0R_MAXBLKL_Pos)

1881

#define SDHC_CA0R_ED8SUP_Pos 18 /**< \brief (SDHC_CA0R) 8-bit Support for Embedded Device */

1882

#define SDHC_CA0R_ED8SUP (_U_(0x1) << SDHC_CA0R_ED8SUP_Pos)

1883

#define SDHC_CA0R_ED8SUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) 8-bit Bus Width not Supported */

1884

#define SDHC_CA0R_ED8SUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) 8-bit Bus Width Supported */

1885

#define SDHC_CA0R_ED8SUP_NO (SDHC_CA0R_ED8SUP_NO_Val << SDHC_CA0R_ED8SUP_Pos)

1886

#define SDHC_CA0R_ED8SUP_YES (SDHC_CA0R_ED8SUP_YES_Val << SDHC_CA0R_ED8SUP_Pos)

1887

#define SDHC_CA0R_ADMA2SUP_Pos 19 /**< \brief (SDHC_CA0R) ADMA2 Support */

1888

#define SDHC_CA0R_ADMA2SUP (_U_(0x1) << SDHC_CA0R_ADMA2SUP_Pos)

1889

#define SDHC_CA0R_ADMA2SUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) ADMA2 not Supported */

1890

#define SDHC_CA0R_ADMA2SUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) ADMA2 Supported */

1891

#define SDHC_CA0R_ADMA2SUP_NO (SDHC_CA0R_ADMA2SUP_NO_Val << SDHC_CA0R_ADMA2SUP_Pos)

1892

#define SDHC_CA0R_ADMA2SUP_YES (SDHC_CA0R_ADMA2SUP_YES_Val << SDHC_CA0R_ADMA2SUP_Pos)

1893

#define SDHC_CA0R_HSSUP_Pos 21 /**< \brief (SDHC_CA0R) High Speed Support */

1894

#define SDHC_CA0R_HSSUP (_U_(0x1) << SDHC_CA0R_HSSUP_Pos)

1895

#define SDHC_CA0R_HSSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) High Speed not Supported */

1896

#define SDHC_CA0R_HSSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) High Speed Supported */

1897

#define SDHC_CA0R_HSSUP_NO (SDHC_CA0R_HSSUP_NO_Val << SDHC_CA0R_HSSUP_Pos)

1898

#define SDHC_CA0R_HSSUP_YES (SDHC_CA0R_HSSUP_YES_Val << SDHC_CA0R_HSSUP_Pos)

1899

#define SDHC_CA0R_SDMASUP_Pos 22 /**< \brief (SDHC_CA0R) SDMA Support */

1900

#define SDHC_CA0R_SDMASUP (_U_(0x1) << SDHC_CA0R_SDMASUP_Pos)

1901

#define SDHC_CA0R_SDMASUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) SDMA not Supported */

1902

#define SDHC_CA0R_SDMASUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) SDMA Supported */

1903

#define SDHC_CA0R_SDMASUP_NO (SDHC_CA0R_SDMASUP_NO_Val << SDHC_CA0R_SDMASUP_Pos)

1904

#define SDHC_CA0R_SDMASUP_YES (SDHC_CA0R_SDMASUP_YES_Val << SDHC_CA0R_SDMASUP_Pos)

1905

#define SDHC_CA0R_SRSUP_Pos 23 /**< \brief (SDHC_CA0R) Suspend/Resume Support */

1906

#define SDHC_CA0R_SRSUP (_U_(0x1) << SDHC_CA0R_SRSUP_Pos)

1907

#define SDHC_CA0R_SRSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) Suspend/Resume not Supported */

1908

#define SDHC_CA0R_SRSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) Suspend/Resume Supported */

1909

#define SDHC_CA0R_SRSUP_NO (SDHC_CA0R_SRSUP_NO_Val << SDHC_CA0R_SRSUP_Pos)

1910

#define SDHC_CA0R_SRSUP_YES (SDHC_CA0R_SRSUP_YES_Val << SDHC_CA0R_SRSUP_Pos)

1911

#define SDHC_CA0R_V33VSUP_Pos 24 /**< \brief (SDHC_CA0R) Voltage Support 3.3V */

1912

#define SDHC_CA0R_V33VSUP (_U_(0x1) << SDHC_CA0R_V33VSUP_Pos)

1913

#define SDHC_CA0R_V33VSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) 3.3V Not Supported */

1914

#define SDHC_CA0R_V33VSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) 3.3V Supported */

1915

#define SDHC_CA0R_V33VSUP_NO (SDHC_CA0R_V33VSUP_NO_Val << SDHC_CA0R_V33VSUP_Pos)

1916

#define SDHC_CA0R_V33VSUP_YES (SDHC_CA0R_V33VSUP_YES_Val << SDHC_CA0R_V33VSUP_Pos)

1917

#define SDHC_CA0R_V30VSUP_Pos 25 /**< \brief (SDHC_CA0R) Voltage Support 3.0V */

1918

#define SDHC_CA0R_V30VSUP (_U_(0x1) << SDHC_CA0R_V30VSUP_Pos)

1919

#define SDHC_CA0R_V30VSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) 3.0V Not Supported */

1920

#define SDHC_CA0R_V30VSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) 3.0V Supported */

1921

#define SDHC_CA0R_V30VSUP_NO (SDHC_CA0R_V30VSUP_NO_Val << SDHC_CA0R_V30VSUP_Pos)

1922

#define SDHC_CA0R_V30VSUP_YES (SDHC_CA0R_V30VSUP_YES_Val << SDHC_CA0R_V30VSUP_Pos)

1923

#define SDHC_CA0R_V18VSUP_Pos 26 /**< \brief (SDHC_CA0R) Voltage Support 1.8V */

1924

#define SDHC_CA0R_V18VSUP (_U_(0x1) << SDHC_CA0R_V18VSUP_Pos)

1925

#define SDHC_CA0R_V18VSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) 1.8V Not Supported */

1926

#define SDHC_CA0R_V18VSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) 1.8V Supported */

1927

#define SDHC_CA0R_V18VSUP_NO (SDHC_CA0R_V18VSUP_NO_Val << SDHC_CA0R_V18VSUP_Pos)

1928

#define SDHC_CA0R_V18VSUP_YES (SDHC_CA0R_V18VSUP_YES_Val << SDHC_CA0R_V18VSUP_Pos)

1929

#define SDHC_CA0R_SB64SUP_Pos 28 /**< \brief (SDHC_CA0R) 64-Bit System Bus Support */

1930

#define SDHC_CA0R_SB64SUP (_U_(0x1) << SDHC_CA0R_SB64SUP_Pos)

1931

#define SDHC_CA0R_SB64SUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) 32-bit Address Descriptors and System Bus */

1932

#define SDHC_CA0R_SB64SUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) 64-bit Address Descriptors and System Bus */

1933

#define SDHC_CA0R_SB64SUP_NO (SDHC_CA0R_SB64SUP_NO_Val << SDHC_CA0R_SB64SUP_Pos)

1934

#define SDHC_CA0R_SB64SUP_YES (SDHC_CA0R_SB64SUP_YES_Val << SDHC_CA0R_SB64SUP_Pos)

1935

#define SDHC_CA0R_ASINTSUP_Pos 29 /**< \brief (SDHC_CA0R) Asynchronous Interrupt Support */

1936

#define SDHC_CA0R_ASINTSUP (_U_(0x1) << SDHC_CA0R_ASINTSUP_Pos)

1937

#define SDHC_CA0R_ASINTSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA0R) Asynchronous Interrupt not Supported */

1938

#define SDHC_CA0R_ASINTSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA0R) Asynchronous Interrupt supported */

1939

#define SDHC_CA0R_ASINTSUP_NO (SDHC_CA0R_ASINTSUP_NO_Val << SDHC_CA0R_ASINTSUP_Pos)

1940

#define SDHC_CA0R_ASINTSUP_YES (SDHC_CA0R_ASINTSUP_YES_Val << SDHC_CA0R_ASINTSUP_Pos)

1941

#define SDHC_CA0R_SLTYPE_Pos 30 /**< \brief (SDHC_CA0R) Slot Type */

1942

#define SDHC_CA0R_SLTYPE_Msk (_U_(0x3) << SDHC_CA0R_SLTYPE_Pos)

1943

#define SDHC_CA0R_SLTYPE(value) (SDHC_CA0R_SLTYPE_Msk & ((value) << SDHC_CA0R_SLTYPE_Pos))

1944

#define SDHC_CA0R_SLTYPE_REMOVABLE_Val _U_(0x0) /**< \brief (SDHC_CA0R) Removable Card Slot */

1945

#define SDHC_CA0R_SLTYPE_EMBEDDED_Val _U_(0x1) /**< \brief (SDHC_CA0R) Embedded Slot for One Device */

1946

#define SDHC_CA0R_SLTYPE_REMOVABLE (SDHC_CA0R_SLTYPE_REMOVABLE_Val << SDHC_CA0R_SLTYPE_Pos)

1947

#define SDHC_CA0R_SLTYPE_EMBEDDED (SDHC_CA0R_SLTYPE_EMBEDDED_Val << SDHC_CA0R_SLTYPE_Pos)

1948

#define SDHC_CA0R_MASK _U_(0xF7EFFFBF) /**< \brief (SDHC_CA0R) MASK Register */

1949

1950

/* -------- SDHC_CA1R : (SDHC Offset: 0x044) (R/ 32) Capabilities 1 -------- */

1951

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

1952

typedef union {

1953

struct {

1954

uint32_t SDR50SUP:1; /*!< bit: 0 SDR50 Support */

1955

uint32_t SDR104SUP:1; /*!< bit: 1 SDR104 Support */

1956

uint32_t DDR50SUP:1; /*!< bit: 2 DDR50 Support */

1957

uint32_t :1; /*!< bit: 3 Reserved */

1958

uint32_t DRVASUP:1; /*!< bit: 4 Driver Type A Support */

1959

uint32_t DRVCSUP:1; /*!< bit: 5 Driver Type C Support */

1960

uint32_t DRVDSUP:1; /*!< bit: 6 Driver Type D Support */

1961

uint32_t :1; /*!< bit: 7 Reserved */

1962

uint32_t TCNTRT:4; /*!< bit: 8..11 Timer Count for Re-Tuning */

1963

uint32_t :1; /*!< bit: 12 Reserved */

1964

uint32_t TSDR50:1; /*!< bit: 13 Use Tuning for SDR50 */

1965

uint32_t :2; /*!< bit: 14..15 Reserved */

1966

uint32_t CLKMULT:8; /*!< bit: 16..23 Clock Multiplier */

1967

uint32_t :8; /*!< bit: 24..31 Reserved */

1968

} bit; /*!< Structure used for bit access */

1969

uint32_t reg; /*!< Type used for register access */

1970

} SDHC_CA1R_Type;

1971

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

1972

1973

#define SDHC_CA1R_OFFSET 0x044 /**< \brief (SDHC_CA1R offset) Capabilities 1 */

1974

#define SDHC_CA1R_RESETVALUE _U_(0x00000070) /**< \brief (SDHC_CA1R reset_value) Capabilities 1 */

1975

1976

#define SDHC_CA1R_SDR50SUP_Pos 0 /**< \brief (SDHC_CA1R) SDR50 Support */

1977

#define SDHC_CA1R_SDR50SUP (_U_(0x1) << SDHC_CA1R_SDR50SUP_Pos)

1978

#define SDHC_CA1R_SDR50SUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) SDR50 is Not Supported */

1979

#define SDHC_CA1R_SDR50SUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA1R) SDR50 is Supported */

1980

#define SDHC_CA1R_SDR50SUP_NO (SDHC_CA1R_SDR50SUP_NO_Val << SDHC_CA1R_SDR50SUP_Pos)

1981

#define SDHC_CA1R_SDR50SUP_YES (SDHC_CA1R_SDR50SUP_YES_Val << SDHC_CA1R_SDR50SUP_Pos)

1982

#define SDHC_CA1R_SDR104SUP_Pos 1 /**< \brief (SDHC_CA1R) SDR104 Support */

1983

#define SDHC_CA1R_SDR104SUP (_U_(0x1) << SDHC_CA1R_SDR104SUP_Pos)

1984

#define SDHC_CA1R_SDR104SUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) SDR104 is Not Supported */

1985

#define SDHC_CA1R_SDR104SUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA1R) SDR104 is Supported */

1986

#define SDHC_CA1R_SDR104SUP_NO (SDHC_CA1R_SDR104SUP_NO_Val << SDHC_CA1R_SDR104SUP_Pos)

1987

#define SDHC_CA1R_SDR104SUP_YES (SDHC_CA1R_SDR104SUP_YES_Val << SDHC_CA1R_SDR104SUP_Pos)

1988

#define SDHC_CA1R_DDR50SUP_Pos 2 /**< \brief (SDHC_CA1R) DDR50 Support */

1989

#define SDHC_CA1R_DDR50SUP (_U_(0x1) << SDHC_CA1R_DDR50SUP_Pos)

1990

#define SDHC_CA1R_DDR50SUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) DDR50 is Not Supported */

1991

#define SDHC_CA1R_DDR50SUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA1R) DDR50 is Supported */

1992

#define SDHC_CA1R_DDR50SUP_NO (SDHC_CA1R_DDR50SUP_NO_Val << SDHC_CA1R_DDR50SUP_Pos)

1993

#define SDHC_CA1R_DDR50SUP_YES (SDHC_CA1R_DDR50SUP_YES_Val << SDHC_CA1R_DDR50SUP_Pos)

1994

#define SDHC_CA1R_DRVASUP_Pos 4 /**< \brief (SDHC_CA1R) Driver Type A Support */

1995

#define SDHC_CA1R_DRVASUP (_U_(0x1) << SDHC_CA1R_DRVASUP_Pos)

1996

#define SDHC_CA1R_DRVASUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) Driver Type A is Not Supported */

1997

#define SDHC_CA1R_DRVASUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA1R) Driver Type A is Supported */

1998

#define SDHC_CA1R_DRVASUP_NO (SDHC_CA1R_DRVASUP_NO_Val << SDHC_CA1R_DRVASUP_Pos)

1999

#define SDHC_CA1R_DRVASUP_YES (SDHC_CA1R_DRVASUP_YES_Val << SDHC_CA1R_DRVASUP_Pos)

2000

#define SDHC_CA1R_DRVCSUP_Pos 5 /**< \brief (SDHC_CA1R) Driver Type C Support */

2001

#define SDHC_CA1R_DRVCSUP (_U_(0x1) << SDHC_CA1R_DRVCSUP_Pos)

2002

#define SDHC_CA1R_DRVCSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) Driver Type C is Not Supported */

2003

#define SDHC_CA1R_DRVCSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA1R) Driver Type C is Supported */

2004

#define SDHC_CA1R_DRVCSUP_NO (SDHC_CA1R_DRVCSUP_NO_Val << SDHC_CA1R_DRVCSUP_Pos)

2005

#define SDHC_CA1R_DRVCSUP_YES (SDHC_CA1R_DRVCSUP_YES_Val << SDHC_CA1R_DRVCSUP_Pos)

2006

#define SDHC_CA1R_DRVDSUP_Pos 6 /**< \brief (SDHC_CA1R) Driver Type D Support */

2007

#define SDHC_CA1R_DRVDSUP (_U_(0x1) << SDHC_CA1R_DRVDSUP_Pos)

2008

#define SDHC_CA1R_DRVDSUP_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) Driver Type D is Not Supported */

2009

#define SDHC_CA1R_DRVDSUP_YES_Val _U_(0x1) /**< \brief (SDHC_CA1R) Driver Type D is Supported */

2010

#define SDHC_CA1R_DRVDSUP_NO (SDHC_CA1R_DRVDSUP_NO_Val << SDHC_CA1R_DRVDSUP_Pos)

2011

#define SDHC_CA1R_DRVDSUP_YES (SDHC_CA1R_DRVDSUP_YES_Val << SDHC_CA1R_DRVDSUP_Pos)

2012

#define SDHC_CA1R_TCNTRT_Pos 8 /**< \brief (SDHC_CA1R) Timer Count for Re-Tuning */

2013

#define SDHC_CA1R_TCNTRT_Msk (_U_(0xF) << SDHC_CA1R_TCNTRT_Pos)

2014

#define SDHC_CA1R_TCNTRT(value) (SDHC_CA1R_TCNTRT_Msk & ((value) << SDHC_CA1R_TCNTRT_Pos))

2015

#define SDHC_CA1R_TCNTRT_DISABLED_Val _U_(0x0) /**< \brief (SDHC_CA1R) Re-Tuning Timer disabled */

2016

#define SDHC_CA1R_TCNTRT_1S_Val _U_(0x1) /**< \brief (SDHC_CA1R) 1 second */

2017

#define SDHC_CA1R_TCNTRT_2S_Val _U_(0x2) /**< \brief (SDHC_CA1R) 2 seconds */

2018

#define SDHC_CA1R_TCNTRT_4S_Val _U_(0x3) /**< \brief (SDHC_CA1R) 4 seconds */

2019

#define SDHC_CA1R_TCNTRT_8S_Val _U_(0x4) /**< \brief (SDHC_CA1R) 8 seconds */

2020

#define SDHC_CA1R_TCNTRT_16S_Val _U_(0x5) /**< \brief (SDHC_CA1R) 16 seconds */

2021

#define SDHC_CA1R_TCNTRT_32S_Val _U_(0x6) /**< \brief (SDHC_CA1R) 32 seconds */

2022

#define SDHC_CA1R_TCNTRT_64S_Val _U_(0x7) /**< \brief (SDHC_CA1R) 64 seconds */

2023

#define SDHC_CA1R_TCNTRT_128S_Val _U_(0x8) /**< \brief (SDHC_CA1R) 128 seconds */

2024

#define SDHC_CA1R_TCNTRT_256S_Val _U_(0x9) /**< \brief (SDHC_CA1R) 256 seconds */

2025

#define SDHC_CA1R_TCNTRT_512S_Val _U_(0xA) /**< \brief (SDHC_CA1R) 512 seconds */

2026

#define SDHC_CA1R_TCNTRT_1024S_Val _U_(0xB) /**< \brief (SDHC_CA1R) 1024 seconds */

2027

#define SDHC_CA1R_TCNTRT_OTHER_Val _U_(0xF) /**< \brief (SDHC_CA1R) Get information from other source */

2028

#define SDHC_CA1R_TCNTRT_DISABLED (SDHC_CA1R_TCNTRT_DISABLED_Val << SDHC_CA1R_TCNTRT_Pos)

2029

#define SDHC_CA1R_TCNTRT_1S (SDHC_CA1R_TCNTRT_1S_Val << SDHC_CA1R_TCNTRT_Pos)

2030

#define SDHC_CA1R_TCNTRT_2S (SDHC_CA1R_TCNTRT_2S_Val << SDHC_CA1R_TCNTRT_Pos)

2031

#define SDHC_CA1R_TCNTRT_4S (SDHC_CA1R_TCNTRT_4S_Val << SDHC_CA1R_TCNTRT_Pos)

2032

#define SDHC_CA1R_TCNTRT_8S (SDHC_CA1R_TCNTRT_8S_Val << SDHC_CA1R_TCNTRT_Pos)

2033

#define SDHC_CA1R_TCNTRT_16S (SDHC_CA1R_TCNTRT_16S_Val << SDHC_CA1R_TCNTRT_Pos)

2034

#define SDHC_CA1R_TCNTRT_32S (SDHC_CA1R_TCNTRT_32S_Val << SDHC_CA1R_TCNTRT_Pos)

2035

#define SDHC_CA1R_TCNTRT_64S (SDHC_CA1R_TCNTRT_64S_Val << SDHC_CA1R_TCNTRT_Pos)

2036

#define SDHC_CA1R_TCNTRT_128S (SDHC_CA1R_TCNTRT_128S_Val << SDHC_CA1R_TCNTRT_Pos)

2037

#define SDHC_CA1R_TCNTRT_256S (SDHC_CA1R_TCNTRT_256S_Val << SDHC_CA1R_TCNTRT_Pos)

2038

#define SDHC_CA1R_TCNTRT_512S (SDHC_CA1R_TCNTRT_512S_Val << SDHC_CA1R_TCNTRT_Pos)

2039

#define SDHC_CA1R_TCNTRT_1024S (SDHC_CA1R_TCNTRT_1024S_Val << SDHC_CA1R_TCNTRT_Pos)

2040

#define SDHC_CA1R_TCNTRT_OTHER (SDHC_CA1R_TCNTRT_OTHER_Val << SDHC_CA1R_TCNTRT_Pos)

2041

#define SDHC_CA1R_TSDR50_Pos 13 /**< \brief (SDHC_CA1R) Use Tuning for SDR50 */

2042

#define SDHC_CA1R_TSDR50 (_U_(0x1) << SDHC_CA1R_TSDR50_Pos)

2043

#define SDHC_CA1R_TSDR50_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) SDR50 does not require tuning */

2044

#define SDHC_CA1R_TSDR50_YES_Val _U_(0x1) /**< \brief (SDHC_CA1R) SDR50 requires tuning */

2045

#define SDHC_CA1R_TSDR50_NO (SDHC_CA1R_TSDR50_NO_Val << SDHC_CA1R_TSDR50_Pos)

2046

#define SDHC_CA1R_TSDR50_YES (SDHC_CA1R_TSDR50_YES_Val << SDHC_CA1R_TSDR50_Pos)

2047

#define SDHC_CA1R_CLKMULT_Pos 16 /**< \brief (SDHC_CA1R) Clock Multiplier */

2048

#define SDHC_CA1R_CLKMULT_Msk (_U_(0xFF) << SDHC_CA1R_CLKMULT_Pos)

2049

#define SDHC_CA1R_CLKMULT(value) (SDHC_CA1R_CLKMULT_Msk & ((value) << SDHC_CA1R_CLKMULT_Pos))

2050

#define SDHC_CA1R_CLKMULT_NO_Val _U_(0x0) /**< \brief (SDHC_CA1R) Clock Multiplier is Not Supported */

2051

#define SDHC_CA1R_CLKMULT_NO (SDHC_CA1R_CLKMULT_NO_Val << SDHC_CA1R_CLKMULT_Pos)

2052

#define SDHC_CA1R_MASK _U_(0x00FF2F77) /**< \brief (SDHC_CA1R) MASK Register */

2053

2054

/* -------- SDHC_MCCAR : (SDHC Offset: 0x048) (R/ 32) Maximum Current Capabilities -------- */

2055

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

2056

typedef union {

2057

struct {

2058

uint32_t MAXCUR33V:8; /*!< bit: 0.. 7 Maximum Current for 3.3V */

2059

uint32_t MAXCUR30V:8; /*!< bit: 8..15 Maximum Current for 3.0V */

2060

uint32_t MAXCUR18V:8; /*!< bit: 16..23 Maximum Current for 1.8V */

2061

uint32_t :8; /*!< bit: 24..31 Reserved */

2062

} bit; /*!< Structure used for bit access */

2063

uint32_t reg; /*!< Type used for register access */

2064

} SDHC_MCCAR_Type;

2065

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

2066

2067

#define SDHC_MCCAR_OFFSET 0x048 /**< \brief (SDHC_MCCAR offset) Maximum Current Capabilities */

2068

#define SDHC_MCCAR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_MCCAR reset_value) Maximum Current Capabilities */

2069

2070

#define SDHC_MCCAR_MAXCUR33V_Pos 0 /**< \brief (SDHC_MCCAR) Maximum Current for 3.3V */

2071

#define SDHC_MCCAR_MAXCUR33V_Msk (_U_(0xFF) << SDHC_MCCAR_MAXCUR33V_Pos)

2072

#define SDHC_MCCAR_MAXCUR33V(value) (SDHC_MCCAR_MAXCUR33V_Msk & ((value) << SDHC_MCCAR_MAXCUR33V_Pos))

2073

#define SDHC_MCCAR_MAXCUR33V_OTHER_Val _U_(0x0) /**< \brief (SDHC_MCCAR) Get information via another method */

2074

#define SDHC_MCCAR_MAXCUR33V_4MA_Val _U_(0x1) /**< \brief (SDHC_MCCAR) 4mA */

2075

#define SDHC_MCCAR_MAXCUR33V_8MA_Val _U_(0x2) /**< \brief (SDHC_MCCAR) 8mA */

2076

#define SDHC_MCCAR_MAXCUR33V_12MA_Val _U_(0x3) /**< \brief (SDHC_MCCAR) 12mA */

2077

#define SDHC_MCCAR_MAXCUR33V_OTHER (SDHC_MCCAR_MAXCUR33V_OTHER_Val << SDHC_MCCAR_MAXCUR33V_Pos)

2078

#define SDHC_MCCAR_MAXCUR33V_4MA (SDHC_MCCAR_MAXCUR33V_4MA_Val << SDHC_MCCAR_MAXCUR33V_Pos)

2079

#define SDHC_MCCAR_MAXCUR33V_8MA (SDHC_MCCAR_MAXCUR33V_8MA_Val << SDHC_MCCAR_MAXCUR33V_Pos)

2080

#define SDHC_MCCAR_MAXCUR33V_12MA (SDHC_MCCAR_MAXCUR33V_12MA_Val << SDHC_MCCAR_MAXCUR33V_Pos)

2081

#define SDHC_MCCAR_MAXCUR30V_Pos 8 /**< \brief (SDHC_MCCAR) Maximum Current for 3.0V */

2082

#define SDHC_MCCAR_MAXCUR30V_Msk (_U_(0xFF) << SDHC_MCCAR_MAXCUR30V_Pos)

2083

#define SDHC_MCCAR_MAXCUR30V(value) (SDHC_MCCAR_MAXCUR30V_Msk & ((value) << SDHC_MCCAR_MAXCUR30V_Pos))

2084

#define SDHC_MCCAR_MAXCUR30V_OTHER_Val _U_(0x0) /**< \brief (SDHC_MCCAR) Get information via another method */

2085

#define SDHC_MCCAR_MAXCUR30V_4MA_Val _U_(0x1) /**< \brief (SDHC_MCCAR) 4mA */

2086

#define SDHC_MCCAR_MAXCUR30V_8MA_Val _U_(0x2) /**< \brief (SDHC_MCCAR) 8mA */

2087

#define SDHC_MCCAR_MAXCUR30V_12MA_Val _U_(0x3) /**< \brief (SDHC_MCCAR) 12mA */

2088

#define SDHC_MCCAR_MAXCUR30V_OTHER (SDHC_MCCAR_MAXCUR30V_OTHER_Val << SDHC_MCCAR_MAXCUR30V_Pos)

2089

#define SDHC_MCCAR_MAXCUR30V_4MA (SDHC_MCCAR_MAXCUR30V_4MA_Val << SDHC_MCCAR_MAXCUR30V_Pos)

2090

#define SDHC_MCCAR_MAXCUR30V_8MA (SDHC_MCCAR_MAXCUR30V_8MA_Val << SDHC_MCCAR_MAXCUR30V_Pos)

2091

#define SDHC_MCCAR_MAXCUR30V_12MA (SDHC_MCCAR_MAXCUR30V_12MA_Val << SDHC_MCCAR_MAXCUR30V_Pos)

2092

#define SDHC_MCCAR_MAXCUR18V_Pos 16 /**< \brief (SDHC_MCCAR) Maximum Current for 1.8V */

2093

#define SDHC_MCCAR_MAXCUR18V_Msk (_U_(0xFF) << SDHC_MCCAR_MAXCUR18V_Pos)

2094

#define SDHC_MCCAR_MAXCUR18V(value) (SDHC_MCCAR_MAXCUR18V_Msk & ((value) << SDHC_MCCAR_MAXCUR18V_Pos))

2095

#define SDHC_MCCAR_MAXCUR18V_OTHER_Val _U_(0x0) /**< \brief (SDHC_MCCAR) Get information via another method */

2096

#define SDHC_MCCAR_MAXCUR18V_4MA_Val _U_(0x1) /**< \brief (SDHC_MCCAR) 4mA */

2097

#define SDHC_MCCAR_MAXCUR18V_8MA_Val _U_(0x2) /**< \brief (SDHC_MCCAR) 8mA */

2098

#define SDHC_MCCAR_MAXCUR18V_12MA_Val _U_(0x3) /**< \brief (SDHC_MCCAR) 12mA */

2099

#define SDHC_MCCAR_MAXCUR18V_OTHER (SDHC_MCCAR_MAXCUR18V_OTHER_Val << SDHC_MCCAR_MAXCUR18V_Pos)

2100

#define SDHC_MCCAR_MAXCUR18V_4MA (SDHC_MCCAR_MAXCUR18V_4MA_Val << SDHC_MCCAR_MAXCUR18V_Pos)

2101

#define SDHC_MCCAR_MAXCUR18V_8MA (SDHC_MCCAR_MAXCUR18V_8MA_Val << SDHC_MCCAR_MAXCUR18V_Pos)

2102

#define SDHC_MCCAR_MAXCUR18V_12MA (SDHC_MCCAR_MAXCUR18V_12MA_Val << SDHC_MCCAR_MAXCUR18V_Pos)

2103

#define SDHC_MCCAR_MASK _U_(0x00FFFFFF) /**< \brief (SDHC_MCCAR) MASK Register */

2104

2105

/* -------- SDHC_FERACES : (SDHC Offset: 0x050) ( /W 16) Force Event for Auto CMD Error Status -------- */

2106

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

2107

typedef union {

2108

struct {

2109

uint16_t ACMD12NE:1; /*!< bit: 0 Force Event for Auto CMD12 Not Executed */

2110

uint16_t ACMDTEO:1; /*!< bit: 1 Force Event for Auto CMD Timeout Error */

2111

uint16_t ACMDCRC:1; /*!< bit: 2 Force Event for Auto CMD CRC Error */

2112

uint16_t ACMDEND:1; /*!< bit: 3 Force Event for Auto CMD End Bit Error */

2113

uint16_t ACMDIDX:1; /*!< bit: 4 Force Event for Auto CMD Index Error */

2114

uint16_t :2; /*!< bit: 5.. 6 Reserved */

2115

uint16_t CMDNI:1; /*!< bit: 7 Force Event for Command Not Issued By Auto CMD12 Error */

2116

uint16_t :8; /*!< bit: 8..15 Reserved */

2117

} bit; /*!< Structure used for bit access */

2118

uint16_t reg; /*!< Type used for register access */

2119

} SDHC_FERACES_Type;

2120

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

2121

2122

#define SDHC_FERACES_OFFSET 0x050 /**< \brief (SDHC_FERACES offset) Force Event for Auto CMD Error Status */

2123

#define SDHC_FERACES_RESETVALUE _U_(0x0000) /**< \brief (SDHC_FERACES reset_value) Force Event for Auto CMD Error Status */

2124

2125

#define SDHC_FERACES_ACMD12NE_Pos 0 /**< \brief (SDHC_FERACES) Force Event for Auto CMD12 Not Executed */

2126

#define SDHC_FERACES_ACMD12NE (_U_(0x1) << SDHC_FERACES_ACMD12NE_Pos)

2127

#define SDHC_FERACES_ACMD12NE_NO_Val _U_(0x0) /**< \brief (SDHC_FERACES) No Interrupt */

2128

#define SDHC_FERACES_ACMD12NE_YES_Val _U_(0x1) /**< \brief (SDHC_FERACES) Interrupt is generated */

2129

#define SDHC_FERACES_ACMD12NE_NO (SDHC_FERACES_ACMD12NE_NO_Val << SDHC_FERACES_ACMD12NE_Pos)

2130

#define SDHC_FERACES_ACMD12NE_YES (SDHC_FERACES_ACMD12NE_YES_Val << SDHC_FERACES_ACMD12NE_Pos)

2131

#define SDHC_FERACES_ACMDTEO_Pos 1 /**< \brief (SDHC_FERACES) Force Event for Auto CMD Timeout Error */

2132

#define SDHC_FERACES_ACMDTEO (_U_(0x1) << SDHC_FERACES_ACMDTEO_Pos)

2133

#define SDHC_FERACES_ACMDTEO_NO_Val _U_(0x0) /**< \brief (SDHC_FERACES) No Interrupt */

2134

#define SDHC_FERACES_ACMDTEO_YES_Val _U_(0x1) /**< \brief (SDHC_FERACES) Interrupt is generated */

2135

#define SDHC_FERACES_ACMDTEO_NO (SDHC_FERACES_ACMDTEO_NO_Val << SDHC_FERACES_ACMDTEO_Pos)

2136

#define SDHC_FERACES_ACMDTEO_YES (SDHC_FERACES_ACMDTEO_YES_Val << SDHC_FERACES_ACMDTEO_Pos)

2137

#define SDHC_FERACES_ACMDCRC_Pos 2 /**< \brief (SDHC_FERACES) Force Event for Auto CMD CRC Error */

2138

#define SDHC_FERACES_ACMDCRC (_U_(0x1) << SDHC_FERACES_ACMDCRC_Pos)

2139

#define SDHC_FERACES_ACMDCRC_NO_Val _U_(0x0) /**< \brief (SDHC_FERACES) No Interrupt */

2140

#define SDHC_FERACES_ACMDCRC_YES_Val _U_(0x1) /**< \brief (SDHC_FERACES) Interrupt is generated */

2141

#define SDHC_FERACES_ACMDCRC_NO (SDHC_FERACES_ACMDCRC_NO_Val << SDHC_FERACES_ACMDCRC_Pos)

2142

#define SDHC_FERACES_ACMDCRC_YES (SDHC_FERACES_ACMDCRC_YES_Val << SDHC_FERACES_ACMDCRC_Pos)

2143

#define SDHC_FERACES_ACMDEND_Pos 3 /**< \brief (SDHC_FERACES) Force Event for Auto CMD End Bit Error */

2144

#define SDHC_FERACES_ACMDEND (_U_(0x1) << SDHC_FERACES_ACMDEND_Pos)

2145

#define SDHC_FERACES_ACMDEND_NO_Val _U_(0x0) /**< \brief (SDHC_FERACES) No Interrupt */

2146

#define SDHC_FERACES_ACMDEND_YES_Val _U_(0x1) /**< \brief (SDHC_FERACES) Interrupt is generated */

2147

#define SDHC_FERACES_ACMDEND_NO (SDHC_FERACES_ACMDEND_NO_Val << SDHC_FERACES_ACMDEND_Pos)

2148

#define SDHC_FERACES_ACMDEND_YES (SDHC_FERACES_ACMDEND_YES_Val << SDHC_FERACES_ACMDEND_Pos)

2149

#define SDHC_FERACES_ACMDIDX_Pos 4 /**< \brief (SDHC_FERACES) Force Event for Auto CMD Index Error */

2150

#define SDHC_FERACES_ACMDIDX (_U_(0x1) << SDHC_FERACES_ACMDIDX_Pos)

2151

#define SDHC_FERACES_ACMDIDX_NO_Val _U_(0x0) /**< \brief (SDHC_FERACES) No Interrupt */

2152

#define SDHC_FERACES_ACMDIDX_YES_Val _U_(0x1) /**< \brief (SDHC_FERACES) Interrupt is generated */

2153

#define SDHC_FERACES_ACMDIDX_NO (SDHC_FERACES_ACMDIDX_NO_Val << SDHC_FERACES_ACMDIDX_Pos)

2154

#define SDHC_FERACES_ACMDIDX_YES (SDHC_FERACES_ACMDIDX_YES_Val << SDHC_FERACES_ACMDIDX_Pos)

2155

#define SDHC_FERACES_CMDNI_Pos 7 /**< \brief (SDHC_FERACES) Force Event for Command Not Issued By Auto CMD12 Error */

2156

#define SDHC_FERACES_CMDNI (_U_(0x1) << SDHC_FERACES_CMDNI_Pos)

2157

#define SDHC_FERACES_CMDNI_NO_Val _U_(0x0) /**< \brief (SDHC_FERACES) No Interrupt */

2158

#define SDHC_FERACES_CMDNI_YES_Val _U_(0x1) /**< \brief (SDHC_FERACES) Interrupt is generated */

2159

#define SDHC_FERACES_CMDNI_NO (SDHC_FERACES_CMDNI_NO_Val << SDHC_FERACES_CMDNI_Pos)

2160

#define SDHC_FERACES_CMDNI_YES (SDHC_FERACES_CMDNI_YES_Val << SDHC_FERACES_CMDNI_Pos)

2161

#define SDHC_FERACES_MASK _U_(0x009F) /**< \brief (SDHC_FERACES) MASK Register */

2162

2163

/* -------- SDHC_FEREIS : (SDHC Offset: 0x052) ( /W 16) Force Event for Error Interrupt Status -------- */

2164

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

2165

typedef union {

2166

struct {

2167

uint16_t CMDTEO:1; /*!< bit: 0 Force Event for Command Timeout Error */

2168

uint16_t CMDCRC:1; /*!< bit: 1 Force Event for Command CRC Error */

2169

uint16_t CMDEND:1; /*!< bit: 2 Force Event for Command End Bit Error */

2170

uint16_t CMDIDX:1; /*!< bit: 3 Force Event for Command Index Error */

2171

uint16_t DATTEO:1; /*!< bit: 4 Force Event for Data Timeout Error */

2172

uint16_t DATCRC:1; /*!< bit: 5 Force Event for Data CRC Error */

2173

uint16_t DATEND:1; /*!< bit: 6 Force Event for Data End Bit Error */

2174

uint16_t CURLIM:1; /*!< bit: 7 Force Event for Current Limit Error */

2175

uint16_t ACMD:1; /*!< bit: 8 Force Event for Auto CMD Error */

2176

uint16_t ADMA:1; /*!< bit: 9 Force Event for ADMA Error */

2177

uint16_t :2; /*!< bit: 10..11 Reserved */

2178

uint16_t BOOTAE:1; /*!< bit: 12 Force Event for Boot Acknowledge Error */

2179

uint16_t :3; /*!< bit: 13..15 Reserved */

2180

} bit; /*!< Structure used for bit access */

2181

uint16_t reg; /*!< Type used for register access */

2182

} SDHC_FEREIS_Type;

2183

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

2184

2185

#define SDHC_FEREIS_OFFSET 0x052 /**< \brief (SDHC_FEREIS offset) Force Event for Error Interrupt Status */

2186

#define SDHC_FEREIS_RESETVALUE _U_(0x0000) /**< \brief (SDHC_FEREIS reset_value) Force Event for Error Interrupt Status */

2187

2188

#define SDHC_FEREIS_CMDTEO_Pos 0 /**< \brief (SDHC_FEREIS) Force Event for Command Timeout Error */

2189

#define SDHC_FEREIS_CMDTEO (_U_(0x1) << SDHC_FEREIS_CMDTEO_Pos)

2190

#define SDHC_FEREIS_CMDTEO_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */

2191

#define SDHC_FEREIS_CMDTEO_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */

2192

#define SDHC_FEREIS_CMDTEO_NO (SDHC_FEREIS_CMDTEO_NO_Val << SDHC_FEREIS_CMDTEO_Pos)

2193

#define SDHC_FEREIS_CMDTEO_YES (SDHC_FEREIS_CMDTEO_YES_Val << SDHC_FEREIS_CMDTEO_Pos)

2194

#define SDHC_FEREIS_CMDCRC_Pos 1 /**< \brief (SDHC_FEREIS) Force Event for Command CRC Error */

2195

#define SDHC_FEREIS_CMDCRC (_U_(0x1) << SDHC_FEREIS_CMDCRC_Pos)

2196

#define SDHC_FEREIS_CMDCRC_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */

2197

#define SDHC_FEREIS_CMDCRC_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */

2198

#define SDHC_FEREIS_CMDCRC_NO (SDHC_FEREIS_CMDCRC_NO_Val << SDHC_FEREIS_CMDCRC_Pos)

2199

#define SDHC_FEREIS_CMDCRC_YES (SDHC_FEREIS_CMDCRC_YES_Val << SDHC_FEREIS_CMDCRC_Pos)

2200

#define SDHC_FEREIS_CMDEND_Pos 2 /**< \brief (SDHC_FEREIS) Force Event for Command End Bit Error */

2201

#define SDHC_FEREIS_CMDEND (_U_(0x1) << SDHC_FEREIS_CMDEND_Pos)

2202

#define SDHC_FEREIS_CMDEND_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */

2203

#define SDHC_FEREIS_CMDEND_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */

2204

#define SDHC_FEREIS_CMDEND_NO (SDHC_FEREIS_CMDEND_NO_Val << SDHC_FEREIS_CMDEND_Pos)

2205

#define SDHC_FEREIS_CMDEND_YES (SDHC_FEREIS_CMDEND_YES_Val << SDHC_FEREIS_CMDEND_Pos)

2206

#define SDHC_FEREIS_CMDIDX_Pos 3 /**< \brief (SDHC_FEREIS) Force Event for Command Index Error */

2207

#define SDHC_FEREIS_CMDIDX (_U_(0x1) << SDHC_FEREIS_CMDIDX_Pos)

2208

#define SDHC_FEREIS_CMDIDX_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */

2209

#define SDHC_FEREIS_CMDIDX_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */

2210

#define SDHC_FEREIS_CMDIDX_NO (SDHC_FEREIS_CMDIDX_NO_Val << SDHC_FEREIS_CMDIDX_Pos)

2211

#define SDHC_FEREIS_CMDIDX_YES (SDHC_FEREIS_CMDIDX_YES_Val << SDHC_FEREIS_CMDIDX_Pos)

2212

#define SDHC_FEREIS_DATTEO_Pos 4 /**< \brief (SDHC_FEREIS) Force Event for Data Timeout Error */

2213

#define SDHC_FEREIS_DATTEO (_U_(0x1) << SDHC_FEREIS_DATTEO_Pos)

2214

#define SDHC_FEREIS_DATTEO_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */

2215

#define SDHC_FEREIS_DATTEO_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */

2216

#define SDHC_FEREIS_DATTEO_NO (SDHC_FEREIS_DATTEO_NO_Val << SDHC_FEREIS_DATTEO_Pos)

2217

#define SDHC_FEREIS_DATTEO_YES (SDHC_FEREIS_DATTEO_YES_Val << SDHC_FEREIS_DATTEO_Pos)

2218

#define SDHC_FEREIS_DATCRC_Pos 5 /**< \brief (SDHC_FEREIS) Force Event for Data CRC Error */

2219

#define SDHC_FEREIS_DATCRC (_U_(0x1) << SDHC_FEREIS_DATCRC_Pos)

2220

#define SDHC_FEREIS_DATCRC_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */

2221

#define SDHC_FEREIS_DATCRC_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */

2222

#define SDHC_FEREIS_DATCRC_NO (SDHC_FEREIS_DATCRC_NO_Val << SDHC_FEREIS_DATCRC_Pos)

2223

#define SDHC_FEREIS_DATCRC_YES (SDHC_FEREIS_DATCRC_YES_Val << SDHC_FEREIS_DATCRC_Pos)

2224

#define SDHC_FEREIS_DATEND_Pos 6 /**< \brief (SDHC_FEREIS) Force Event for Data End Bit Error */

2225

#define SDHC_FEREIS_DATEND (_U_(0x1) << SDHC_FEREIS_DATEND_Pos)

2226

#define SDHC_FEREIS_DATEND_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */

2227

#define SDHC_FEREIS_DATEND_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */

2228

#define SDHC_FEREIS_DATEND_NO (SDHC_FEREIS_DATEND_NO_Val << SDHC_FEREIS_DATEND_Pos)

2229

#define SDHC_FEREIS_DATEND_YES (SDHC_FEREIS_DATEND_YES_Val << SDHC_FEREIS_DATEND_Pos)

2230

#define SDHC_FEREIS_CURLIM_Pos 7 /**< \brief (SDHC_FEREIS) Force Event for Current Limit Error */

2231

#define SDHC_FEREIS_CURLIM (_U_(0x1) << SDHC_FEREIS_CURLIM_Pos)

2232

#define SDHC_FEREIS_CURLIM_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */

2233

#define SDHC_FEREIS_CURLIM_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */

2234

#define SDHC_FEREIS_CURLIM_NO (SDHC_FEREIS_CURLIM_NO_Val << SDHC_FEREIS_CURLIM_Pos)

2235

#define SDHC_FEREIS_CURLIM_YES (SDHC_FEREIS_CURLIM_YES_Val << SDHC_FEREIS_CURLIM_Pos)

2236

#define SDHC_FEREIS_ACMD_Pos 8 /**< \brief (SDHC_FEREIS) Force Event for Auto CMD Error */

2237

#define SDHC_FEREIS_ACMD (_U_(0x1) << SDHC_FEREIS_ACMD_Pos)

2238

#define SDHC_FEREIS_ACMD_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */

2239

#define SDHC_FEREIS_ACMD_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */

2240

#define SDHC_FEREIS_ACMD_NO (SDHC_FEREIS_ACMD_NO_Val << SDHC_FEREIS_ACMD_Pos)

2241

#define SDHC_FEREIS_ACMD_YES (SDHC_FEREIS_ACMD_YES_Val << SDHC_FEREIS_ACMD_Pos)

2242

#define SDHC_FEREIS_ADMA_Pos 9 /**< \brief (SDHC_FEREIS) Force Event for ADMA Error */

2243

#define SDHC_FEREIS_ADMA (_U_(0x1) << SDHC_FEREIS_ADMA_Pos)

2244

#define SDHC_FEREIS_ADMA_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */

2245

#define SDHC_FEREIS_ADMA_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */

2246

#define SDHC_FEREIS_ADMA_NO (SDHC_FEREIS_ADMA_NO_Val << SDHC_FEREIS_ADMA_Pos)

2247

#define SDHC_FEREIS_ADMA_YES (SDHC_FEREIS_ADMA_YES_Val << SDHC_FEREIS_ADMA_Pos)

2248

#define SDHC_FEREIS_BOOTAE_Pos 12 /**< \brief (SDHC_FEREIS) Force Event for Boot Acknowledge Error */

2249

#define SDHC_FEREIS_BOOTAE (_U_(0x1) << SDHC_FEREIS_BOOTAE_Pos)

2250

#define SDHC_FEREIS_BOOTAE_NO_Val _U_(0x0) /**< \brief (SDHC_FEREIS) No Interrupt */

2251

#define SDHC_FEREIS_BOOTAE_YES_Val _U_(0x1) /**< \brief (SDHC_FEREIS) Interrupt is generated */

2252

#define SDHC_FEREIS_BOOTAE_NO (SDHC_FEREIS_BOOTAE_NO_Val << SDHC_FEREIS_BOOTAE_Pos)

2253

#define SDHC_FEREIS_BOOTAE_YES (SDHC_FEREIS_BOOTAE_YES_Val << SDHC_FEREIS_BOOTAE_Pos)

2254

#define SDHC_FEREIS_MASK _U_(0x13FF) /**< \brief (SDHC_FEREIS) MASK Register */

2255

2256

/* -------- SDHC_AESR : (SDHC Offset: 0x054) (R/ 8) ADMA Error Status -------- */

2257

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

2258

typedef union {

2259

struct {

2260

uint8_t ERRST:2; /*!< bit: 0.. 1 ADMA Error State */

2261

uint8_t LMIS:1; /*!< bit: 2 ADMA Length Mismatch Error */

2262

uint8_t :5; /*!< bit: 3.. 7 Reserved */

2263

} bit; /*!< Structure used for bit access */

2264

uint8_t reg; /*!< Type used for register access */

2265

} SDHC_AESR_Type;

2266

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

2267

2268

#define SDHC_AESR_OFFSET 0x054 /**< \brief (SDHC_AESR offset) ADMA Error Status */

2269

#define SDHC_AESR_RESETVALUE _U_(0x00) /**< \brief (SDHC_AESR reset_value) ADMA Error Status */

2270

2271

#define SDHC_AESR_ERRST_Pos 0 /**< \brief (SDHC_AESR) ADMA Error State */

2272

#define SDHC_AESR_ERRST_Msk (_U_(0x3) << SDHC_AESR_ERRST_Pos)

2273

#define SDHC_AESR_ERRST(value) (SDHC_AESR_ERRST_Msk & ((value) << SDHC_AESR_ERRST_Pos))

2274

#define SDHC_AESR_ERRST_STOP_Val _U_(0x0) /**< \brief (SDHC_AESR) ST_STOP (Stop DMA) */

2275

#define SDHC_AESR_ERRST_FDS_Val _U_(0x1) /**< \brief (SDHC_AESR) ST_FDS (Fetch Descriptor) */

2276

#define SDHC_AESR_ERRST_2_Val _U_(0x2) /**< \brief (SDHC_AESR) Reserved */

2277

#define SDHC_AESR_ERRST_TFR_Val _U_(0x3) /**< \brief (SDHC_AESR) ST_TFR (Transfer Data) */

2278

#define SDHC_AESR_ERRST_STOP (SDHC_AESR_ERRST_STOP_Val << SDHC_AESR_ERRST_Pos)

2279

#define SDHC_AESR_ERRST_FDS (SDHC_AESR_ERRST_FDS_Val << SDHC_AESR_ERRST_Pos)

2280

#define SDHC_AESR_ERRST_2 (SDHC_AESR_ERRST_2_Val << SDHC_AESR_ERRST_Pos)

2281

#define SDHC_AESR_ERRST_TFR (SDHC_AESR_ERRST_TFR_Val << SDHC_AESR_ERRST_Pos)

2282

#define SDHC_AESR_LMIS_Pos 2 /**< \brief (SDHC_AESR) ADMA Length Mismatch Error */

2283

#define SDHC_AESR_LMIS (_U_(0x1) << SDHC_AESR_LMIS_Pos)

2284

#define SDHC_AESR_LMIS_NO_Val _U_(0x0) /**< \brief (SDHC_AESR) No Error */

2285

#define SDHC_AESR_LMIS_YES_Val _U_(0x1) /**< \brief (SDHC_AESR) Error */

2286

#define SDHC_AESR_LMIS_NO (SDHC_AESR_LMIS_NO_Val << SDHC_AESR_LMIS_Pos)

2287

#define SDHC_AESR_LMIS_YES (SDHC_AESR_LMIS_YES_Val << SDHC_AESR_LMIS_Pos)

2288

#define SDHC_AESR_MASK _U_(0x07) /**< \brief (SDHC_AESR) MASK Register */

2289

2290

/* -------- SDHC_ASAR : (SDHC Offset: 0x058) (R/W 32) ADMA System Address n -------- */

2291

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

2292

typedef union {

2293

struct {

2294

uint32_t ADMASA:32; /*!< bit: 0..31 ADMA System Address */

2295

} bit; /*!< Structure used for bit access */

2296

uint32_t reg; /*!< Type used for register access */

2297

} SDHC_ASAR_Type;

2298

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

2299

2300

#define SDHC_ASAR_OFFSET 0x058 /**< \brief (SDHC_ASAR offset) ADMA System Address n */

2301

#define SDHC_ASAR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_ASAR reset_value) ADMA System Address n */

2302

2303

#define SDHC_ASAR_ADMASA_Pos 0 /**< \brief (SDHC_ASAR) ADMA System Address */

2304

#define SDHC_ASAR_ADMASA_Msk (_U_(0xFFFFFFFF) << SDHC_ASAR_ADMASA_Pos)

2305

#define SDHC_ASAR_ADMASA(value) (SDHC_ASAR_ADMASA_Msk & ((value) << SDHC_ASAR_ADMASA_Pos))

2306

#define SDHC_ASAR_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_ASAR) MASK Register */

2307

2308

/* -------- SDHC_PVR : (SDHC Offset: 0x060) (R/W 16) Preset Value n -------- */

2309

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

2310

typedef union {

2311

struct {

2312

uint16_t SDCLKFSEL:10; /*!< bit: 0.. 9 SDCLK Frequency Select Value for Initialization */

2313

uint16_t CLKGSEL:1; /*!< bit: 10 Clock Generator Select Value for Initialization */

2314

uint16_t :3; /*!< bit: 11..13 Reserved */

2315

uint16_t DRVSEL:2; /*!< bit: 14..15 Driver Strength Select Value for Initialization */

2316

} bit; /*!< Structure used for bit access */

2317

uint16_t reg; /*!< Type used for register access */

2318

} SDHC_PVR_Type;

2319

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

2320

2321

#define SDHC_PVR_OFFSET 0x060 /**< \brief (SDHC_PVR offset) Preset Value n */

2322

#define SDHC_PVR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_PVR reset_value) Preset Value n */

2323

2324

#define SDHC_PVR_SDCLKFSEL_Pos 0 /**< \brief (SDHC_PVR) SDCLK Frequency Select Value for Initialization */

2325

#define SDHC_PVR_SDCLKFSEL_Msk (_U_(0x3FF) << SDHC_PVR_SDCLKFSEL_Pos)

2326

#define SDHC_PVR_SDCLKFSEL(value) (SDHC_PVR_SDCLKFSEL_Msk & ((value) << SDHC_PVR_SDCLKFSEL_Pos))

2327

#define SDHC_PVR_CLKGSEL_Pos 10 /**< \brief (SDHC_PVR) Clock Generator Select Value for Initialization */

2328

#define SDHC_PVR_CLKGSEL (_U_(0x1) << SDHC_PVR_CLKGSEL_Pos)

2329

#define SDHC_PVR_CLKGSEL_DIV_Val _U_(0x0) /**< \brief (SDHC_PVR) Host Controller Ver2.00 Compatible Clock Generator (Divider) */

2330

#define SDHC_PVR_CLKGSEL_PROG_Val _U_(0x1) /**< \brief (SDHC_PVR) Programmable Clock Generator */

2331

#define SDHC_PVR_CLKGSEL_DIV (SDHC_PVR_CLKGSEL_DIV_Val << SDHC_PVR_CLKGSEL_Pos)

2332

#define SDHC_PVR_CLKGSEL_PROG (SDHC_PVR_CLKGSEL_PROG_Val << SDHC_PVR_CLKGSEL_Pos)

2333

#define SDHC_PVR_DRVSEL_Pos 14 /**< \brief (SDHC_PVR) Driver Strength Select Value for Initialization */

2334

#define SDHC_PVR_DRVSEL_Msk (_U_(0x3) << SDHC_PVR_DRVSEL_Pos)

2335

#define SDHC_PVR_DRVSEL(value) (SDHC_PVR_DRVSEL_Msk & ((value) << SDHC_PVR_DRVSEL_Pos))

2336

#define SDHC_PVR_DRVSEL_B_Val _U_(0x0) /**< \brief (SDHC_PVR) Driver Type B is Selected */

2337

#define SDHC_PVR_DRVSEL_A_Val _U_(0x1) /**< \brief (SDHC_PVR) Driver Type A is Selected */

2338

#define SDHC_PVR_DRVSEL_C_Val _U_(0x2) /**< \brief (SDHC_PVR) Driver Type C is Selected */

2339

#define SDHC_PVR_DRVSEL_D_Val _U_(0x3) /**< \brief (SDHC_PVR) Driver Type D is Selected */

2340

#define SDHC_PVR_DRVSEL_B (SDHC_PVR_DRVSEL_B_Val << SDHC_PVR_DRVSEL_Pos)

2341

#define SDHC_PVR_DRVSEL_A (SDHC_PVR_DRVSEL_A_Val << SDHC_PVR_DRVSEL_Pos)

2342

#define SDHC_PVR_DRVSEL_C (SDHC_PVR_DRVSEL_C_Val << SDHC_PVR_DRVSEL_Pos)

2343

#define SDHC_PVR_DRVSEL_D (SDHC_PVR_DRVSEL_D_Val << SDHC_PVR_DRVSEL_Pos)

2344

#define SDHC_PVR_MASK _U_(0xC7FF) /**< \brief (SDHC_PVR) MASK Register */

2345

2346

/* -------- SDHC_SISR : (SDHC Offset: 0x0FC) (R/ 16) Slot Interrupt Status -------- */

2347

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

2348

typedef union {

2349

struct {

2350

uint16_t INTSSL:1; /*!< bit: 0 Interrupt Signal for Each Slot */

2351

uint16_t :15; /*!< bit: 1..15 Reserved */

2352

} bit; /*!< Structure used for bit access */

2353

uint16_t reg; /*!< Type used for register access */

2354

} SDHC_SISR_Type;

2355

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

2356

2357

#define SDHC_SISR_OFFSET 0x0FC /**< \brief (SDHC_SISR offset) Slot Interrupt Status */

2358

#define SDHC_SISR_RESETVALUE _U_(0x20000) /**< \brief (SDHC_SISR reset_value) Slot Interrupt Status */

2359

2360

#define SDHC_SISR_INTSSL_Pos 0 /**< \brief (SDHC_SISR) Interrupt Signal for Each Slot */

2361

#define SDHC_SISR_INTSSL_Msk (_U_(0x1) << SDHC_SISR_INTSSL_Pos)

2362

#define SDHC_SISR_INTSSL(value) (SDHC_SISR_INTSSL_Msk & ((value) << SDHC_SISR_INTSSL_Pos))

2363

#define SDHC_SISR_MASK _U_(0x0001) /**< \brief (SDHC_SISR) MASK Register */

2364

2365

/* -------- SDHC_HCVR : (SDHC Offset: 0x0FE) (R/ 16) Host Controller Version -------- */

2366

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

2367

typedef union {

2368

struct {

2369

uint16_t SVER:8; /*!< bit: 0.. 7 Spec Version */

2370

uint16_t VVER:8; /*!< bit: 8..15 Vendor Version */

2371

} bit; /*!< Structure used for bit access */

2372

uint16_t reg; /*!< Type used for register access */

2373

} SDHC_HCVR_Type;

2374

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

2375

2376

#define SDHC_HCVR_OFFSET 0x0FE /**< \brief (SDHC_HCVR offset) Host Controller Version */

2377

#define SDHC_HCVR_RESETVALUE _U_(0x1802) /**< \brief (SDHC_HCVR reset_value) Host Controller Version */

2378

2379

#define SDHC_HCVR_SVER_Pos 0 /**< \brief (SDHC_HCVR) Spec Version */

2380

#define SDHC_HCVR_SVER_Msk (_U_(0xFF) << SDHC_HCVR_SVER_Pos)

2381

#define SDHC_HCVR_SVER(value) (SDHC_HCVR_SVER_Msk & ((value) << SDHC_HCVR_SVER_Pos))

2382

#define SDHC_HCVR_VVER_Pos 8 /**< \brief (SDHC_HCVR) Vendor Version */

2383

#define SDHC_HCVR_VVER_Msk (_U_(0xFF) << SDHC_HCVR_VVER_Pos)

2384

#define SDHC_HCVR_VVER(value) (SDHC_HCVR_VVER_Msk & ((value) << SDHC_HCVR_VVER_Pos))

2385

#define SDHC_HCVR_MASK _U_(0xFFFF) /**< \brief (SDHC_HCVR) MASK Register */

2386

2387

/* -------- SDHC_MC1R : (SDHC Offset: 0x204) (R/W 8) MMC Control 1 -------- */

2388

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

2389

typedef union {

2390

struct {

2391

uint8_t CMDTYP:2; /*!< bit: 0.. 1 e.MMC Command Type */

2392

uint8_t :1; /*!< bit: 2 Reserved */

2393

uint8_t DDR:1; /*!< bit: 3 e.MMC HSDDR Mode */

2394

uint8_t OPD:1; /*!< bit: 4 e.MMC Open Drain Mode */

2395

uint8_t BOOTA:1; /*!< bit: 5 e.MMC Boot Acknowledge Enable */

2396

uint8_t RSTN:1; /*!< bit: 6 e.MMC Reset Signal */

2397

uint8_t FCD:1; /*!< bit: 7 e.MMC Force Card Detect */

2398

} bit; /*!< Structure used for bit access */

2399

uint8_t reg; /*!< Type used for register access */

2400

} SDHC_MC1R_Type;

2401

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

2402

2403

#define SDHC_MC1R_OFFSET 0x204 /**< \brief (SDHC_MC1R offset) MMC Control 1 */

2404

#define SDHC_MC1R_RESETVALUE _U_(0x00) /**< \brief (SDHC_MC1R reset_value) MMC Control 1 */

2405

2406

#define SDHC_MC1R_CMDTYP_Pos 0 /**< \brief (SDHC_MC1R) e.MMC Command Type */

2407

#define SDHC_MC1R_CMDTYP_Msk (_U_(0x3) << SDHC_MC1R_CMDTYP_Pos)

2408

#define SDHC_MC1R_CMDTYP(value) (SDHC_MC1R_CMDTYP_Msk & ((value) << SDHC_MC1R_CMDTYP_Pos))

2409

#define SDHC_MC1R_CMDTYP_NORMAL_Val _U_(0x0) /**< \brief (SDHC_MC1R) Not a MMC specific command */

2410

#define SDHC_MC1R_CMDTYP_WAITIRQ_Val _U_(0x1) /**< \brief (SDHC_MC1R) Wait IRQ Command */

2411

#define SDHC_MC1R_CMDTYP_STREAM_Val _U_(0x2) /**< \brief (SDHC_MC1R) Stream Command */

2412

#define SDHC_MC1R_CMDTYP_BOOT_Val _U_(0x3) /**< \brief (SDHC_MC1R) Boot Command */

2413

#define SDHC_MC1R_CMDTYP_NORMAL (SDHC_MC1R_CMDTYP_NORMAL_Val << SDHC_MC1R_CMDTYP_Pos)

2414

#define SDHC_MC1R_CMDTYP_WAITIRQ (SDHC_MC1R_CMDTYP_WAITIRQ_Val << SDHC_MC1R_CMDTYP_Pos)

2415

#define SDHC_MC1R_CMDTYP_STREAM (SDHC_MC1R_CMDTYP_STREAM_Val << SDHC_MC1R_CMDTYP_Pos)

2416

#define SDHC_MC1R_CMDTYP_BOOT (SDHC_MC1R_CMDTYP_BOOT_Val << SDHC_MC1R_CMDTYP_Pos)

2417

#define SDHC_MC1R_DDR_Pos 3 /**< \brief (SDHC_MC1R) e.MMC HSDDR Mode */

2418

#define SDHC_MC1R_DDR (_U_(0x1) << SDHC_MC1R_DDR_Pos)

2419

#define SDHC_MC1R_OPD_Pos 4 /**< \brief (SDHC_MC1R) e.MMC Open Drain Mode */

2420

#define SDHC_MC1R_OPD (_U_(0x1) << SDHC_MC1R_OPD_Pos)

2421

#define SDHC_MC1R_BOOTA_Pos 5 /**< \brief (SDHC_MC1R) e.MMC Boot Acknowledge Enable */

2422

#define SDHC_MC1R_BOOTA (_U_(0x1) << SDHC_MC1R_BOOTA_Pos)

2423

#define SDHC_MC1R_RSTN_Pos 6 /**< \brief (SDHC_MC1R) e.MMC Reset Signal */

2424

#define SDHC_MC1R_RSTN (_U_(0x1) << SDHC_MC1R_RSTN_Pos)

2425

#define SDHC_MC1R_FCD_Pos 7 /**< \brief (SDHC_MC1R) e.MMC Force Card Detect */

2426

#define SDHC_MC1R_FCD (_U_(0x1) << SDHC_MC1R_FCD_Pos)

2427

#define SDHC_MC1R_MASK _U_(0xFB) /**< \brief (SDHC_MC1R) MASK Register */

2428

2429

/* -------- SDHC_MC2R : (SDHC Offset: 0x205) ( /W 8) MMC Control 2 -------- */

2430

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

2431

typedef union {

2432

struct {

2433

uint8_t SRESP:1; /*!< bit: 0 e.MMC Abort Wait IRQ */

2434

uint8_t ABOOT:1; /*!< bit: 1 e.MMC Abort Boot */

2435

uint8_t :6; /*!< bit: 2.. 7 Reserved */

2436

} bit; /*!< Structure used for bit access */

2437

uint8_t reg; /*!< Type used for register access */

2438

} SDHC_MC2R_Type;

2439

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

2440

2441

#define SDHC_MC2R_OFFSET 0x205 /**< \brief (SDHC_MC2R offset) MMC Control 2 */

2442

#define SDHC_MC2R_RESETVALUE _U_(0x00) /**< \brief (SDHC_MC2R reset_value) MMC Control 2 */

2443

2444

#define SDHC_MC2R_SRESP_Pos 0 /**< \brief (SDHC_MC2R) e.MMC Abort Wait IRQ */

2445

#define SDHC_MC2R_SRESP (_U_(0x1) << SDHC_MC2R_SRESP_Pos)

2446

#define SDHC_MC2R_ABOOT_Pos 1 /**< \brief (SDHC_MC2R) e.MMC Abort Boot */

2447

#define SDHC_MC2R_ABOOT (_U_(0x1) << SDHC_MC2R_ABOOT_Pos)

2448

#define SDHC_MC2R_MASK _U_(0x03) /**< \brief (SDHC_MC2R) MASK Register */

2449

2450

/* -------- SDHC_ACR : (SDHC Offset: 0x208) (R/W 32) AHB Control -------- */

2451

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

2452

typedef union {

2453

struct {

2454

uint32_t BMAX:2; /*!< bit: 0.. 1 AHB Maximum Burst */

2455

uint32_t :30; /*!< bit: 2..31 Reserved */

2456

} bit; /*!< Structure used for bit access */

2457

uint32_t reg; /*!< Type used for register access */

2458

} SDHC_ACR_Type;

2459

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

2460

2461

#define SDHC_ACR_OFFSET 0x208 /**< \brief (SDHC_ACR offset) AHB Control */

2462

#define SDHC_ACR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_ACR reset_value) AHB Control */

2463

2464

#define SDHC_ACR_BMAX_Pos 0 /**< \brief (SDHC_ACR) AHB Maximum Burst */

2465

#define SDHC_ACR_BMAX_Msk (_U_(0x3) << SDHC_ACR_BMAX_Pos)

2466

#define SDHC_ACR_BMAX(value) (SDHC_ACR_BMAX_Msk & ((value) << SDHC_ACR_BMAX_Pos))

2467

#define SDHC_ACR_BMAX_INCR16_Val _U_(0x0) /**< \brief (SDHC_ACR) */

2468

#define SDHC_ACR_BMAX_INCR8_Val _U_(0x1) /**< \brief (SDHC_ACR) */

2469

#define SDHC_ACR_BMAX_INCR4_Val _U_(0x2) /**< \brief (SDHC_ACR) */

2470

#define SDHC_ACR_BMAX_SINGLE_Val _U_(0x3) /**< \brief (SDHC_ACR) */

2471

#define SDHC_ACR_BMAX_INCR16 (SDHC_ACR_BMAX_INCR16_Val << SDHC_ACR_BMAX_Pos)

2472

#define SDHC_ACR_BMAX_INCR8 (SDHC_ACR_BMAX_INCR8_Val << SDHC_ACR_BMAX_Pos)

2473

#define SDHC_ACR_BMAX_INCR4 (SDHC_ACR_BMAX_INCR4_Val << SDHC_ACR_BMAX_Pos)

2474

#define SDHC_ACR_BMAX_SINGLE (SDHC_ACR_BMAX_SINGLE_Val << SDHC_ACR_BMAX_Pos)

2475

#define SDHC_ACR_MASK _U_(0x00000003) /**< \brief (SDHC_ACR) MASK Register */

2476

2477

/* -------- SDHC_CC2R : (SDHC Offset: 0x20C) (R/W 32) Clock Control 2 -------- */

2478

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

2479

typedef union {

2480

struct {

2481

uint32_t FSDCLKD:1; /*!< bit: 0 Force SDCK Disabled */

2482

uint32_t :31; /*!< bit: 1..31 Reserved */

2483

} bit; /*!< Structure used for bit access */

2484

uint32_t reg; /*!< Type used for register access */

2485

} SDHC_CC2R_Type;

2486

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

2487

2488

#define SDHC_CC2R_OFFSET 0x20C /**< \brief (SDHC_CC2R offset) Clock Control 2 */

2489

#define SDHC_CC2R_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_CC2R reset_value) Clock Control 2 */

2490

2491

#define SDHC_CC2R_FSDCLKD_Pos 0 /**< \brief (SDHC_CC2R) Force SDCK Disabled */

2492

#define SDHC_CC2R_FSDCLKD (_U_(0x1) << SDHC_CC2R_FSDCLKD_Pos)

2493

#define SDHC_CC2R_FSDCLKD_NOEFFECT_Val _U_(0x0) /**< \brief (SDHC_CC2R) No effect */

2494

#define SDHC_CC2R_FSDCLKD_DISABLE_Val _U_(0x1) /**< \brief (SDHC_CC2R) SDCLK can be stopped at any time after DATA transfer.SDCLK enable forcing for 8 SDCLK cycles is disabled */

2495

#define SDHC_CC2R_FSDCLKD_NOEFFECT (SDHC_CC2R_FSDCLKD_NOEFFECT_Val << SDHC_CC2R_FSDCLKD_Pos)

2496

#define SDHC_CC2R_FSDCLKD_DISABLE (SDHC_CC2R_FSDCLKD_DISABLE_Val << SDHC_CC2R_FSDCLKD_Pos)

2497

#define SDHC_CC2R_MASK _U_(0x00000001) /**< \brief (SDHC_CC2R) MASK Register */

2498

2499

/* -------- SDHC_CACR : (SDHC Offset: 0x230) (R/W 32) Capabilities Control -------- */

2500

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

2501

typedef union {

2502

struct {

2503

uint32_t CAPWREN:1; /*!< bit: 0 Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers) */

2504

uint32_t :7; /*!< bit: 1.. 7 Reserved */

2505

uint32_t KEY:8; /*!< bit: 8..15 Key (0x46) */

2506

uint32_t :16; /*!< bit: 16..31 Reserved */

2507

} bit; /*!< Structure used for bit access */

2508

uint32_t reg; /*!< Type used for register access */

2509

} SDHC_CACR_Type;

2510

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

2511

2512

#define SDHC_CACR_OFFSET 0x230 /**< \brief (SDHC_CACR offset) Capabilities Control */

2513

#define SDHC_CACR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_CACR reset_value) Capabilities Control */

2514

2515

#define SDHC_CACR_CAPWREN_Pos 0 /**< \brief (SDHC_CACR) Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers) */

2516

#define SDHC_CACR_CAPWREN (_U_(0x1) << SDHC_CACR_CAPWREN_Pos)

2517

#define SDHC_CACR_KEY_Pos 8 /**< \brief (SDHC_CACR) Key (0x46) */

2518

#define SDHC_CACR_KEY_Msk (_U_(0xFF) << SDHC_CACR_KEY_Pos)

2519

#define SDHC_CACR_KEY(value) (SDHC_CACR_KEY_Msk & ((value) << SDHC_CACR_KEY_Pos))

2520

#define SDHC_CACR_MASK _U_(0x0000FF01) /**< \brief (SDHC_CACR) MASK Register */

2521

2522

/* -------- SDHC_DBGR : (SDHC Offset: 0x234) (R/W 8) Debug -------- */

2523

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

2524

typedef union {

2525

struct {

2526

uint8_t NIDBG:1; /*!< bit: 0 Non-intrusive debug enable */

2527

uint8_t :7; /*!< bit: 1.. 7 Reserved */

2528

} bit; /*!< Structure used for bit access */

2529

uint8_t reg; /*!< Type used for register access */

2530

} SDHC_DBGR_Type;

2531

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

2532

2533

#define SDHC_DBGR_OFFSET 0x234 /**< \brief (SDHC_DBGR offset) Debug */

2534

#define SDHC_DBGR_RESETVALUE _U_(0x00) /**< \brief (SDHC_DBGR reset_value) Debug */

2535

2536

#define SDHC_DBGR_NIDBG_Pos 0 /**< \brief (SDHC_DBGR) Non-intrusive debug enable */

2537

#define SDHC_DBGR_NIDBG (_U_(0x1) << SDHC_DBGR_NIDBG_Pos)

2538

#define SDHC_DBGR_NIDBG_IDBG_Val _U_(0x0) /**< \brief (SDHC_DBGR) Debugging is intrusive (reads of BDPR from debugger are considered and increment the internal buffer pointer) */

2539

#define SDHC_DBGR_NIDBG_NIDBG_Val _U_(0x1) /**< \brief (SDHC_DBGR) Debugging is not intrusive (reads of BDPR from debugger are discarded and do not increment the internal buffer pointer) */

2540

#define SDHC_DBGR_NIDBG_IDBG (SDHC_DBGR_NIDBG_IDBG_Val << SDHC_DBGR_NIDBG_Pos)

2541

#define SDHC_DBGR_NIDBG_NIDBG (SDHC_DBGR_NIDBG_NIDBG_Val << SDHC_DBGR_NIDBG_Pos)

2542

#define SDHC_DBGR_MASK _U_(0x01) /**< \brief (SDHC_DBGR) MASK Register */

2543

2544

/** \brief SDHC hardware registers */

2545

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

2546

typedef struct {

2547

__IO SDHC_SSAR_Type SSAR; /**< \brief Offset: 0x000 (R/W 32) SDMA System Address / Argument 2 */

2548

__IO SDHC_BSR_Type BSR; /**< \brief Offset: 0x004 (R/W 16) Block Size */

2549

__IO SDHC_BCR_Type BCR; /**< \brief Offset: 0x006 (R/W 16) Block Count */

2550

__IO SDHC_ARG1R_Type ARG1R; /**< \brief Offset: 0x008 (R/W 32) Argument 1 */

2551

__IO SDHC_TMR_Type TMR; /**< \brief Offset: 0x00C (R/W 16) Transfer Mode */

2552

__IO SDHC_CR_Type CR; /**< \brief Offset: 0x00E (R/W 16) Command */

2553

__I SDHC_RR_Type RR[4]; /**< \brief Offset: 0x010 (R/ 32) Response */

2554

__IO SDHC_BDPR_Type BDPR; /**< \brief Offset: 0x020 (R/W 32) Buffer Data Port */

2555

__I SDHC_PSR_Type PSR; /**< \brief Offset: 0x024 (R/ 32) Present State */

2556

__IO SDHC_HC1R_Type HC1R; /**< \brief Offset: 0x028 (R/W 8) Host Control 1 */

2557

__IO SDHC_PCR_Type PCR; /**< \brief Offset: 0x029 (R/W 8) Power Control */

2558

__IO SDHC_BGCR_Type BGCR; /**< \brief Offset: 0x02A (R/W 8) Block Gap Control */

2559

__IO SDHC_WCR_Type WCR; /**< \brief Offset: 0x02B (R/W 8) Wakeup Control */

2560

__IO SDHC_CCR_Type CCR; /**< \brief Offset: 0x02C (R/W 16) Clock Control */

2561

__IO SDHC_TCR_Type TCR; /**< \brief Offset: 0x02E (R/W 8) Timeout Control */

2562

__IO SDHC_SRR_Type SRR; /**< \brief Offset: 0x02F (R/W 8) Software Reset */

2563

__IO SDHC_NISTR_Type NISTR; /**< \brief Offset: 0x030 (R/W 16) Normal Interrupt Status */

2564

__IO SDHC_EISTR_Type EISTR; /**< \brief Offset: 0x032 (R/W 16) Error Interrupt Status */

2565

__IO SDHC_NISTER_Type NISTER; /**< \brief Offset: 0x034 (R/W 16) Normal Interrupt Status Enable */

2566

__IO SDHC_EISTER_Type EISTER; /**< \brief Offset: 0x036 (R/W 16) Error Interrupt Status Enable */

2567

__IO SDHC_NISIER_Type NISIER; /**< \brief Offset: 0x038 (R/W 16) Normal Interrupt Signal Enable */

2568

__IO SDHC_EISIER_Type EISIER; /**< \brief Offset: 0x03A (R/W 16) Error Interrupt Signal Enable */

2569

__I SDHC_ACESR_Type ACESR; /**< \brief Offset: 0x03C (R/ 16) Auto CMD Error Status */

2570

__IO SDHC_HC2R_Type HC2R; /**< \brief Offset: 0x03E (R/W 16) Host Control 2 */

2571

__I SDHC_CA0R_Type CA0R; /**< \brief Offset: 0x040 (R/ 32) Capabilities 0 */

2572

__I SDHC_CA1R_Type CA1R; /**< \brief Offset: 0x044 (R/ 32) Capabilities 1 */

2573

__I SDHC_MCCAR_Type MCCAR; /**< \brief Offset: 0x048 (R/ 32) Maximum Current Capabilities */

2574

RoReg8 Reserved1[0x4];

2575

__O SDHC_FERACES_Type FERACES; /**< \brief Offset: 0x050 ( /W 16) Force Event for Auto CMD Error Status */

2576

__O SDHC_FEREIS_Type FEREIS; /**< \brief Offset: 0x052 ( /W 16) Force Event for Error Interrupt Status */

2577

__I SDHC_AESR_Type AESR; /**< \brief Offset: 0x054 (R/ 8) ADMA Error Status */

2578

RoReg8 Reserved2[0x3];

2579

__IO SDHC_ASAR_Type ASAR[1]; /**< \brief Offset: 0x058 (R/W 32) ADMA System Address n */

2580

RoReg8 Reserved3[0x4];

2581

__IO SDHC_PVR_Type PVR[8]; /**< \brief Offset: 0x060 (R/W 16) Preset Value n */

2582

RoReg8 Reserved4[0x8C];

2583

__I SDHC_SISR_Type SISR; /**< \brief Offset: 0x0FC (R/ 16) Slot Interrupt Status */

2584

__I SDHC_HCVR_Type HCVR; /**< \brief Offset: 0x0FE (R/ 16) Host Controller Version */

2585

RoReg8 Reserved5[0x104];

2586

__IO SDHC_MC1R_Type MC1R; /**< \brief Offset: 0x204 (R/W 8) MMC Control 1 */

2587

__O SDHC_MC2R_Type MC2R; /**< \brief Offset: 0x205 ( /W 8) MMC Control 2 */

2588

RoReg8 Reserved6[0x2];

2589

__IO SDHC_ACR_Type ACR; /**< \brief Offset: 0x208 (R/W 32) AHB Control */

2590

__IO SDHC_CC2R_Type CC2R; /**< \brief Offset: 0x20C (R/W 32) Clock Control 2 */

2591

RoReg8 Reserved7[0x20];

2592

__IO SDHC_CACR_Type CACR; /**< \brief Offset: 0x230 (R/W 32) Capabilities Control */

2593

__IO SDHC_DBGR_Type DBGR; /**< \brief Offset: 0x234 (R/W 8) Debug */

2594

} Sdhc;

2595

#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

/*@}*/

#endif /* _SAME54_SDHC_COMPONENT_ */