Gitiles
Code Review Sign In
gerrit.osmocom.org / osmo-ccid-firmware / 727d67536ded3c2ea27b3dd00013f893336739db / . / sysmoOCTSIM / hri / hri_mclk_e54.h
blob: 7e3963b19237c4a762afaf849af080b8a6d403e1 [file] [log] [blame]
Kévin Redon69b92d92019-01-24 16:39:20 +0100[diff] [blame]1/**
2 * \file
3 *
4 * \brief SAM MCLK
5 *
6 * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Subject to your compliance with these terms, you may use Microchip
13 * software and any derivatives exclusively with Microchip products.
14 * It is your responsibility to comply with third party license terms applicable
15 * to your use of third party software (including open source software) that
16 * may accompany Microchip software.
17 *
18 * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
19 * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
20 * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
21 * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
22 * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
23 * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
24 * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
25 * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
26 * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
27 * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
28 * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
29 *
30 * \asf_license_stop
31 *
32 */
33
34#ifdef _SAME54_MCLK_COMPONENT_
35#ifndef _HRI_MCLK_E54_H_INCLUDED_
36#define _HRI_MCLK_E54_H_INCLUDED_
37
38#ifdef __cplusplus
39extern "C" {
40#endif
41
42#include <stdbool.h>
43#include <hal_atomic.h>
44
45#if defined(ENABLE_MCLK_CRITICAL_SECTIONS)
46#define MCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
47#define MCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
48#else
49#define MCLK_CRITICAL_SECTION_ENTER()
50#define MCLK_CRITICAL_SECTION_LEAVE()
51#endif
52
53typedef uint32_t hri_mclk_ahbmask_reg_t;
54typedef uint32_t hri_mclk_apbamask_reg_t;
55typedef uint32_t hri_mclk_apbbmask_reg_t;
56typedef uint32_t hri_mclk_apbcmask_reg_t;
57typedef uint32_t hri_mclk_apbdmask_reg_t;
58typedef uint8_t hri_mclk_cpudiv_reg_t;
59typedef uint8_t hri_mclk_hsdiv_reg_t;
60typedef uint8_t hri_mclk_intenset_reg_t;
61typedef uint8_t hri_mclk_intflag_reg_t;
62
63static inline bool hri_mclk_get_INTFLAG_CKRDY_bit(const void *const hw)
64{
65 return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos;
66}
67
68static inline void hri_mclk_clear_INTFLAG_CKRDY_bit(const void *const hw)
69{
70 ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY;
71}
72
73static inline bool hri_mclk_get_interrupt_CKRDY_bit(const void *const hw)
74{
75 return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos;
76}
77
78static inline void hri_mclk_clear_interrupt_CKRDY_bit(const void *const hw)
79{
80 ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY;
81}
82
83static inline hri_mclk_intflag_reg_t hri_mclk_get_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask)
84{
85 uint8_t tmp;
86 tmp = ((Mclk *)hw)->INTFLAG.reg;
87 tmp &= mask;
88 return tmp;
89}
90
91static inline hri_mclk_intflag_reg_t hri_mclk_read_INTFLAG_reg(const void *const hw)
92{
93 return ((Mclk *)hw)->INTFLAG.reg;
94}
95
96static inline void hri_mclk_clear_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask)
97{
98 ((Mclk *)hw)->INTFLAG.reg = mask;
99}
100
101static inline void hri_mclk_set_INTEN_CKRDY_bit(const void *const hw)
102{
103 ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY;
104}
105
106static inline bool hri_mclk_get_INTEN_CKRDY_bit(const void *const hw)
107{
108 return (((Mclk *)hw)->INTENSET.reg & MCLK_INTENSET_CKRDY) >> MCLK_INTENSET_CKRDY_Pos;
109}
110
111static inline void hri_mclk_write_INTEN_CKRDY_bit(const void *const hw, bool value)
112{
113 if (value == 0x0) {
114 ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY;
115 } else {
116 ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY;
117 }
118}
119
120static inline void hri_mclk_clear_INTEN_CKRDY_bit(const void *const hw)
121{
122 ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY;
123}
124
125static inline void hri_mclk_set_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask)
126{
127 ((Mclk *)hw)->INTENSET.reg = mask;
128}
129
130static inline hri_mclk_intenset_reg_t hri_mclk_get_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask)
131{
132 uint8_t tmp;
133 tmp = ((Mclk *)hw)->INTENSET.reg;
134 tmp &= mask;
135 return tmp;
136}
137
138static inline hri_mclk_intenset_reg_t hri_mclk_read_INTEN_reg(const void *const hw)
139{
140 return ((Mclk *)hw)->INTENSET.reg;
141}
142
143static inline void hri_mclk_write_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t data)
144{
145 ((Mclk *)hw)->INTENSET.reg = data;
146 ((Mclk *)hw)->INTENCLR.reg = ~data;
147}
148
149static inline void hri_mclk_clear_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask)
150{
151 ((Mclk *)hw)->INTENCLR.reg = mask;
152}
153
154static inline hri_mclk_hsdiv_reg_t hri_mclk_get_HSDIV_DIV_bf(const void *const hw, hri_mclk_hsdiv_reg_t mask)
155{
156 return (((Mclk *)hw)->HSDIV.reg & MCLK_HSDIV_DIV(mask)) >> MCLK_HSDIV_DIV_Pos;
157}
158
159static inline hri_mclk_hsdiv_reg_t hri_mclk_read_HSDIV_DIV_bf(const void *const hw)
160{
161 return (((Mclk *)hw)->HSDIV.reg & MCLK_HSDIV_DIV_Msk) >> MCLK_HSDIV_DIV_Pos;
162}
163
164static inline hri_mclk_hsdiv_reg_t hri_mclk_get_HSDIV_reg(const void *const hw, hri_mclk_hsdiv_reg_t mask)
165{
166 uint8_t tmp;
167 tmp = ((Mclk *)hw)->HSDIV.reg;
168 tmp &= mask;
169 return tmp;
170}
171
172static inline hri_mclk_hsdiv_reg_t hri_mclk_read_HSDIV_reg(const void *const hw)
173{
174 return ((Mclk *)hw)->HSDIV.reg;
175}
176
177static inline void hri_mclk_set_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask)
178{
179 MCLK_CRITICAL_SECTION_ENTER();
180 ((Mclk *)hw)->CPUDIV.reg |= MCLK_CPUDIV_DIV(mask);
181 MCLK_CRITICAL_SECTION_LEAVE();
182}
183
184static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask)
185{
186 uint8_t tmp;
187 tmp = ((Mclk *)hw)->CPUDIV.reg;
188 tmp = (tmp & MCLK_CPUDIV_DIV(mask)) >> MCLK_CPUDIV_DIV_Pos;
189 return tmp;
190}
191
192static inline void hri_mclk_write_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t data)
193{
194 uint8_t tmp;
195 MCLK_CRITICAL_SECTION_ENTER();
196 tmp = ((Mclk *)hw)->CPUDIV.reg;
197 tmp &= ~MCLK_CPUDIV_DIV_Msk;
198 tmp |= MCLK_CPUDIV_DIV(data);
199 ((Mclk *)hw)->CPUDIV.reg = tmp;
200 MCLK_CRITICAL_SECTION_LEAVE();
201}
202
203static inline void hri_mclk_clear_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask)
204{
205 MCLK_CRITICAL_SECTION_ENTER();
206 ((Mclk *)hw)->CPUDIV.reg &= ~MCLK_CPUDIV_DIV(mask);
207 MCLK_CRITICAL_SECTION_LEAVE();
208}
209
210static inline void hri_mclk_toggle_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask)
211{
212 MCLK_CRITICAL_SECTION_ENTER();
213 ((Mclk *)hw)->CPUDIV.reg ^= MCLK_CPUDIV_DIV(mask);
214 MCLK_CRITICAL_SECTION_LEAVE();
215}
216
217static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_DIV_bf(const void *const hw)
218{
219 uint8_t tmp;
220 tmp = ((Mclk *)hw)->CPUDIV.reg;
221 tmp = (tmp & MCLK_CPUDIV_DIV_Msk) >> MCLK_CPUDIV_DIV_Pos;
222 return tmp;
223}
224
225static inline void hri_mclk_set_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask)
226{
227 MCLK_CRITICAL_SECTION_ENTER();
228 ((Mclk *)hw)->CPUDIV.reg |= mask;
229 MCLK_CRITICAL_SECTION_LEAVE();
230}
231
232static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask)
233{
234 uint8_t tmp;
235 tmp = ((Mclk *)hw)->CPUDIV.reg;
236 tmp &= mask;
237 return tmp;
238}
239
240static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data)
241{
242 MCLK_CRITICAL_SECTION_ENTER();
243 ((Mclk *)hw)->CPUDIV.reg = data;
244 MCLK_CRITICAL_SECTION_LEAVE();
245}
246
247static inline void hri_mclk_clear_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask)
248{
249 MCLK_CRITICAL_SECTION_ENTER();
250 ((Mclk *)hw)->CPUDIV.reg &= ~mask;
251 MCLK_CRITICAL_SECTION_LEAVE();
252}
253
254static inline void hri_mclk_toggle_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask)
255{
256 MCLK_CRITICAL_SECTION_ENTER();
257 ((Mclk *)hw)->CPUDIV.reg ^= mask;
258 MCLK_CRITICAL_SECTION_LEAVE();
259}
260
261static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_reg(const void *const hw)
262{
263 return ((Mclk *)hw)->CPUDIV.reg;
264}
265
266static inline void hri_mclk_set_AHBMASK_HPB0_bit(const void *const hw)
267{
268 MCLK_CRITICAL_SECTION_ENTER();
269 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB0;
270 MCLK_CRITICAL_SECTION_LEAVE();
271}
272
273static inline bool hri_mclk_get_AHBMASK_HPB0_bit(const void *const hw)
274{
275 uint32_t tmp;
276 tmp = ((Mclk *)hw)->AHBMASK.reg;
277 tmp = (tmp & MCLK_AHBMASK_HPB0) >> MCLK_AHBMASK_HPB0_Pos;
278 return (bool)tmp;
279}
280
281static inline void hri_mclk_write_AHBMASK_HPB0_bit(const void *const hw, bool value)
282{
283 uint32_t tmp;
284 MCLK_CRITICAL_SECTION_ENTER();
285 tmp = ((Mclk *)hw)->AHBMASK.reg;
286 tmp &= ~MCLK_AHBMASK_HPB0;
287 tmp |= value << MCLK_AHBMASK_HPB0_Pos;
288 ((Mclk *)hw)->AHBMASK.reg = tmp;
289 MCLK_CRITICAL_SECTION_LEAVE();
290}
291
292static inline void hri_mclk_clear_AHBMASK_HPB0_bit(const void *const hw)
293{
294 MCLK_CRITICAL_SECTION_ENTER();
295 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB0;
296 MCLK_CRITICAL_SECTION_LEAVE();
297}
298
299static inline void hri_mclk_toggle_AHBMASK_HPB0_bit(const void *const hw)
300{
301 MCLK_CRITICAL_SECTION_ENTER();
302 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB0;
303 MCLK_CRITICAL_SECTION_LEAVE();
304}
305
306static inline void hri_mclk_set_AHBMASK_HPB1_bit(const void *const hw)
307{
308 MCLK_CRITICAL_SECTION_ENTER();
309 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB1;
310 MCLK_CRITICAL_SECTION_LEAVE();
311}
312
313static inline bool hri_mclk_get_AHBMASK_HPB1_bit(const void *const hw)
314{
315 uint32_t tmp;
316 tmp = ((Mclk *)hw)->AHBMASK.reg;
317 tmp = (tmp & MCLK_AHBMASK_HPB1) >> MCLK_AHBMASK_HPB1_Pos;
318 return (bool)tmp;
319}
320
321static inline void hri_mclk_write_AHBMASK_HPB1_bit(const void *const hw, bool value)
322{
323 uint32_t tmp;
324 MCLK_CRITICAL_SECTION_ENTER();
325 tmp = ((Mclk *)hw)->AHBMASK.reg;
326 tmp &= ~MCLK_AHBMASK_HPB1;
327 tmp |= value << MCLK_AHBMASK_HPB1_Pos;
328 ((Mclk *)hw)->AHBMASK.reg = tmp;
329 MCLK_CRITICAL_SECTION_LEAVE();
330}
331
332static inline void hri_mclk_clear_AHBMASK_HPB1_bit(const void *const hw)
333{
334 MCLK_CRITICAL_SECTION_ENTER();
335 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB1;
336 MCLK_CRITICAL_SECTION_LEAVE();
337}
338
339static inline void hri_mclk_toggle_AHBMASK_HPB1_bit(const void *const hw)
340{
341 MCLK_CRITICAL_SECTION_ENTER();
342 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB1;
343 MCLK_CRITICAL_SECTION_LEAVE();
344}
345
346static inline void hri_mclk_set_AHBMASK_HPB2_bit(const void *const hw)
347{
348 MCLK_CRITICAL_SECTION_ENTER();
349 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB2;
350 MCLK_CRITICAL_SECTION_LEAVE();
351}
352
353static inline bool hri_mclk_get_AHBMASK_HPB2_bit(const void *const hw)
354{
355 uint32_t tmp;
356 tmp = ((Mclk *)hw)->AHBMASK.reg;
357 tmp = (tmp & MCLK_AHBMASK_HPB2) >> MCLK_AHBMASK_HPB2_Pos;
358 return (bool)tmp;
359}
360
361static inline void hri_mclk_write_AHBMASK_HPB2_bit(const void *const hw, bool value)
362{
363 uint32_t tmp;
364 MCLK_CRITICAL_SECTION_ENTER();
365 tmp = ((Mclk *)hw)->AHBMASK.reg;
366 tmp &= ~MCLK_AHBMASK_HPB2;
367 tmp |= value << MCLK_AHBMASK_HPB2_Pos;
368 ((Mclk *)hw)->AHBMASK.reg = tmp;
369 MCLK_CRITICAL_SECTION_LEAVE();
370}
371
372static inline void hri_mclk_clear_AHBMASK_HPB2_bit(const void *const hw)
373{
374 MCLK_CRITICAL_SECTION_ENTER();
375 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB2;
376 MCLK_CRITICAL_SECTION_LEAVE();
377}
378
379static inline void hri_mclk_toggle_AHBMASK_HPB2_bit(const void *const hw)
380{
381 MCLK_CRITICAL_SECTION_ENTER();
382 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB2;
383 MCLK_CRITICAL_SECTION_LEAVE();
384}
385
386static inline void hri_mclk_set_AHBMASK_HPB3_bit(const void *const hw)
387{
388 MCLK_CRITICAL_SECTION_ENTER();
389 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB3;
390 MCLK_CRITICAL_SECTION_LEAVE();
391}
392
393static inline bool hri_mclk_get_AHBMASK_HPB3_bit(const void *const hw)
394{
395 uint32_t tmp;
396 tmp = ((Mclk *)hw)->AHBMASK.reg;
397 tmp = (tmp & MCLK_AHBMASK_HPB3) >> MCLK_AHBMASK_HPB3_Pos;
398 return (bool)tmp;
399}
400
401static inline void hri_mclk_write_AHBMASK_HPB3_bit(const void *const hw, bool value)
402{
403 uint32_t tmp;
404 MCLK_CRITICAL_SECTION_ENTER();
405 tmp = ((Mclk *)hw)->AHBMASK.reg;
406 tmp &= ~MCLK_AHBMASK_HPB3;
407 tmp |= value << MCLK_AHBMASK_HPB3_Pos;
408 ((Mclk *)hw)->AHBMASK.reg = tmp;
409 MCLK_CRITICAL_SECTION_LEAVE();
410}
411
412static inline void hri_mclk_clear_AHBMASK_HPB3_bit(const void *const hw)
413{
414 MCLK_CRITICAL_SECTION_ENTER();
415 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB3;
416 MCLK_CRITICAL_SECTION_LEAVE();
417}
418
419static inline void hri_mclk_toggle_AHBMASK_HPB3_bit(const void *const hw)
420{
421 MCLK_CRITICAL_SECTION_ENTER();
422 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB3;
423 MCLK_CRITICAL_SECTION_LEAVE();
424}
425
426static inline void hri_mclk_set_AHBMASK_DSU_bit(const void *const hw)
427{
428 MCLK_CRITICAL_SECTION_ENTER();
429 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DSU;
430 MCLK_CRITICAL_SECTION_LEAVE();
431}
432
433static inline bool hri_mclk_get_AHBMASK_DSU_bit(const void *const hw)
434{
435 uint32_t tmp;
436 tmp = ((Mclk *)hw)->AHBMASK.reg;
437 tmp = (tmp & MCLK_AHBMASK_DSU) >> MCLK_AHBMASK_DSU_Pos;
438 return (bool)tmp;
439}
440
441static inline void hri_mclk_write_AHBMASK_DSU_bit(const void *const hw, bool value)
442{
443 uint32_t tmp;
444 MCLK_CRITICAL_SECTION_ENTER();
445 tmp = ((Mclk *)hw)->AHBMASK.reg;
446 tmp &= ~MCLK_AHBMASK_DSU;
447 tmp |= value << MCLK_AHBMASK_DSU_Pos;
448 ((Mclk *)hw)->AHBMASK.reg = tmp;
449 MCLK_CRITICAL_SECTION_LEAVE();
450}
451
452static inline void hri_mclk_clear_AHBMASK_DSU_bit(const void *const hw)
453{
454 MCLK_CRITICAL_SECTION_ENTER();
455 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DSU;
456 MCLK_CRITICAL_SECTION_LEAVE();
457}
458
459static inline void hri_mclk_toggle_AHBMASK_DSU_bit(const void *const hw)
460{
461 MCLK_CRITICAL_SECTION_ENTER();
462 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DSU;
463 MCLK_CRITICAL_SECTION_LEAVE();
464}
465
466static inline void hri_mclk_set_AHBMASK_HMATRIX_bit(const void *const hw)
467{
468 MCLK_CRITICAL_SECTION_ENTER();
469 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HMATRIX;
470 MCLK_CRITICAL_SECTION_LEAVE();
471}
472
473static inline bool hri_mclk_get_AHBMASK_HMATRIX_bit(const void *const hw)
474{
475 uint32_t tmp;
476 tmp = ((Mclk *)hw)->AHBMASK.reg;
477 tmp = (tmp & MCLK_AHBMASK_HMATRIX) >> MCLK_AHBMASK_HMATRIX_Pos;
478 return (bool)tmp;
479}
480
481static inline void hri_mclk_write_AHBMASK_HMATRIX_bit(const void *const hw, bool value)
482{
483 uint32_t tmp;
484 MCLK_CRITICAL_SECTION_ENTER();
485 tmp = ((Mclk *)hw)->AHBMASK.reg;
486 tmp &= ~MCLK_AHBMASK_HMATRIX;
487 tmp |= value << MCLK_AHBMASK_HMATRIX_Pos;
488 ((Mclk *)hw)->AHBMASK.reg = tmp;
489 MCLK_CRITICAL_SECTION_LEAVE();
490}
491
492static inline void hri_mclk_clear_AHBMASK_HMATRIX_bit(const void *const hw)
493{
494 MCLK_CRITICAL_SECTION_ENTER();
495 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HMATRIX;
496 MCLK_CRITICAL_SECTION_LEAVE();
497}
498
499static inline void hri_mclk_toggle_AHBMASK_HMATRIX_bit(const void *const hw)
500{
501 MCLK_CRITICAL_SECTION_ENTER();
502 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HMATRIX;
503 MCLK_CRITICAL_SECTION_LEAVE();
504}
505
506static inline void hri_mclk_set_AHBMASK_NVMCTRL_bit(const void *const hw)
507{
508 MCLK_CRITICAL_SECTION_ENTER();
509 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL;
510 MCLK_CRITICAL_SECTION_LEAVE();
511}
512
513static inline bool hri_mclk_get_AHBMASK_NVMCTRL_bit(const void *const hw)
514{
515 uint32_t tmp;
516 tmp = ((Mclk *)hw)->AHBMASK.reg;
517 tmp = (tmp & MCLK_AHBMASK_NVMCTRL) >> MCLK_AHBMASK_NVMCTRL_Pos;
518 return (bool)tmp;
519}
520
521static inline void hri_mclk_write_AHBMASK_NVMCTRL_bit(const void *const hw, bool value)
522{
523 uint32_t tmp;
524 MCLK_CRITICAL_SECTION_ENTER();
525 tmp = ((Mclk *)hw)->AHBMASK.reg;
526 tmp &= ~MCLK_AHBMASK_NVMCTRL;
527 tmp |= value << MCLK_AHBMASK_NVMCTRL_Pos;
528 ((Mclk *)hw)->AHBMASK.reg = tmp;
529 MCLK_CRITICAL_SECTION_LEAVE();
530}
531
532static inline void hri_mclk_clear_AHBMASK_NVMCTRL_bit(const void *const hw)
533{
534 MCLK_CRITICAL_SECTION_ENTER();
535 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL;
536 MCLK_CRITICAL_SECTION_LEAVE();
537}
538
539static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_bit(const void *const hw)
540{
541 MCLK_CRITICAL_SECTION_ENTER();
542 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL;
543 MCLK_CRITICAL_SECTION_LEAVE();
544}
545
546static inline void hri_mclk_set_AHBMASK_HSRAM_bit(const void *const hw)
547{
548 MCLK_CRITICAL_SECTION_ENTER();
549 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HSRAM;
550 MCLK_CRITICAL_SECTION_LEAVE();
551}
552
553static inline bool hri_mclk_get_AHBMASK_HSRAM_bit(const void *const hw)
554{
555 uint32_t tmp;
556 tmp = ((Mclk *)hw)->AHBMASK.reg;
557 tmp = (tmp & MCLK_AHBMASK_HSRAM) >> MCLK_AHBMASK_HSRAM_Pos;
558 return (bool)tmp;
559}
560
561static inline void hri_mclk_write_AHBMASK_HSRAM_bit(const void *const hw, bool value)
562{
563 uint32_t tmp;
564 MCLK_CRITICAL_SECTION_ENTER();
565 tmp = ((Mclk *)hw)->AHBMASK.reg;
566 tmp &= ~MCLK_AHBMASK_HSRAM;
567 tmp |= value << MCLK_AHBMASK_HSRAM_Pos;
568 ((Mclk *)hw)->AHBMASK.reg = tmp;
569 MCLK_CRITICAL_SECTION_LEAVE();
570}
571
572static inline void hri_mclk_clear_AHBMASK_HSRAM_bit(const void *const hw)
573{
574 MCLK_CRITICAL_SECTION_ENTER();
575 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HSRAM;
576 MCLK_CRITICAL_SECTION_LEAVE();
577}
578
579static inline void hri_mclk_toggle_AHBMASK_HSRAM_bit(const void *const hw)
580{
581 MCLK_CRITICAL_SECTION_ENTER();
582 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HSRAM;
583 MCLK_CRITICAL_SECTION_LEAVE();
584}
585
586static inline void hri_mclk_set_AHBMASK_CMCC_bit(const void *const hw)
587{
588 MCLK_CRITICAL_SECTION_ENTER();
589 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CMCC;
590 MCLK_CRITICAL_SECTION_LEAVE();
591}
592
593static inline bool hri_mclk_get_AHBMASK_CMCC_bit(const void *const hw)
594{
595 uint32_t tmp;
596 tmp = ((Mclk *)hw)->AHBMASK.reg;
597 tmp = (tmp & MCLK_AHBMASK_CMCC) >> MCLK_AHBMASK_CMCC_Pos;
598 return (bool)tmp;
599}
600
601static inline void hri_mclk_write_AHBMASK_CMCC_bit(const void *const hw, bool value)
602{
603 uint32_t tmp;
604 MCLK_CRITICAL_SECTION_ENTER();
605 tmp = ((Mclk *)hw)->AHBMASK.reg;
606 tmp &= ~MCLK_AHBMASK_CMCC;
607 tmp |= value << MCLK_AHBMASK_CMCC_Pos;
608 ((Mclk *)hw)->AHBMASK.reg = tmp;
609 MCLK_CRITICAL_SECTION_LEAVE();
610}
611
612static inline void hri_mclk_clear_AHBMASK_CMCC_bit(const void *const hw)
613{
614 MCLK_CRITICAL_SECTION_ENTER();
615 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CMCC;
616 MCLK_CRITICAL_SECTION_LEAVE();
617}
618
619static inline void hri_mclk_toggle_AHBMASK_CMCC_bit(const void *const hw)
620{
621 MCLK_CRITICAL_SECTION_ENTER();
622 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CMCC;
623 MCLK_CRITICAL_SECTION_LEAVE();
624}
625
626static inline void hri_mclk_set_AHBMASK_DMAC_bit(const void *const hw)
627{
628 MCLK_CRITICAL_SECTION_ENTER();
629 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DMAC;
630 MCLK_CRITICAL_SECTION_LEAVE();
631}
632
633static inline bool hri_mclk_get_AHBMASK_DMAC_bit(const void *const hw)
634{
635 uint32_t tmp;
636 tmp = ((Mclk *)hw)->AHBMASK.reg;
637 tmp = (tmp & MCLK_AHBMASK_DMAC) >> MCLK_AHBMASK_DMAC_Pos;
638 return (bool)tmp;
639}
640
641static inline void hri_mclk_write_AHBMASK_DMAC_bit(const void *const hw, bool value)
642{
643 uint32_t tmp;
644 MCLK_CRITICAL_SECTION_ENTER();
645 tmp = ((Mclk *)hw)->AHBMASK.reg;
646 tmp &= ~MCLK_AHBMASK_DMAC;
647 tmp |= value << MCLK_AHBMASK_DMAC_Pos;
648 ((Mclk *)hw)->AHBMASK.reg = tmp;
649 MCLK_CRITICAL_SECTION_LEAVE();
650}
651
652static inline void hri_mclk_clear_AHBMASK_DMAC_bit(const void *const hw)
653{
654 MCLK_CRITICAL_SECTION_ENTER();
655 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DMAC;
656 MCLK_CRITICAL_SECTION_LEAVE();
657}
658
659static inline void hri_mclk_toggle_AHBMASK_DMAC_bit(const void *const hw)
660{
661 MCLK_CRITICAL_SECTION_ENTER();
662 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DMAC;
663 MCLK_CRITICAL_SECTION_LEAVE();
664}
665
666static inline void hri_mclk_set_AHBMASK_USB_bit(const void *const hw)
667{
668 MCLK_CRITICAL_SECTION_ENTER();
669 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_USB;
670 MCLK_CRITICAL_SECTION_LEAVE();
671}
672
673static inline bool hri_mclk_get_AHBMASK_USB_bit(const void *const hw)
674{
675 uint32_t tmp;
676 tmp = ((Mclk *)hw)->AHBMASK.reg;
677 tmp = (tmp & MCLK_AHBMASK_USB) >> MCLK_AHBMASK_USB_Pos;
678 return (bool)tmp;
679}
680
681static inline void hri_mclk_write_AHBMASK_USB_bit(const void *const hw, bool value)
682{
683 uint32_t tmp;
684 MCLK_CRITICAL_SECTION_ENTER();
685 tmp = ((Mclk *)hw)->AHBMASK.reg;
686 tmp &= ~MCLK_AHBMASK_USB;
687 tmp |= value << MCLK_AHBMASK_USB_Pos;
688 ((Mclk *)hw)->AHBMASK.reg = tmp;
689 MCLK_CRITICAL_SECTION_LEAVE();
690}
691
692static inline void hri_mclk_clear_AHBMASK_USB_bit(const void *const hw)
693{
694 MCLK_CRITICAL_SECTION_ENTER();
695 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_USB;
696 MCLK_CRITICAL_SECTION_LEAVE();
697}
698
699static inline void hri_mclk_toggle_AHBMASK_USB_bit(const void *const hw)
700{
701 MCLK_CRITICAL_SECTION_ENTER();
702 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_USB;
703 MCLK_CRITICAL_SECTION_LEAVE();
704}
705
706static inline void hri_mclk_set_AHBMASK_BKUPRAM_bit(const void *const hw)
707{
708 MCLK_CRITICAL_SECTION_ENTER();
709 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_BKUPRAM;
710 MCLK_CRITICAL_SECTION_LEAVE();
711}
712
713static inline bool hri_mclk_get_AHBMASK_BKUPRAM_bit(const void *const hw)
714{
715 uint32_t tmp;
716 tmp = ((Mclk *)hw)->AHBMASK.reg;
717 tmp = (tmp & MCLK_AHBMASK_BKUPRAM) >> MCLK_AHBMASK_BKUPRAM_Pos;
718 return (bool)tmp;
719}
720
721static inline void hri_mclk_write_AHBMASK_BKUPRAM_bit(const void *const hw, bool value)
722{
723 uint32_t tmp;
724 MCLK_CRITICAL_SECTION_ENTER();
725 tmp = ((Mclk *)hw)->AHBMASK.reg;
726 tmp &= ~MCLK_AHBMASK_BKUPRAM;
727 tmp |= value << MCLK_AHBMASK_BKUPRAM_Pos;
728 ((Mclk *)hw)->AHBMASK.reg = tmp;
729 MCLK_CRITICAL_SECTION_LEAVE();
730}
731
732static inline void hri_mclk_clear_AHBMASK_BKUPRAM_bit(const void *const hw)
733{
734 MCLK_CRITICAL_SECTION_ENTER();
735 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_BKUPRAM;
736 MCLK_CRITICAL_SECTION_LEAVE();
737}
738
739static inline void hri_mclk_toggle_AHBMASK_BKUPRAM_bit(const void *const hw)
740{
741 MCLK_CRITICAL_SECTION_ENTER();
742 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_BKUPRAM;
743 MCLK_CRITICAL_SECTION_LEAVE();
744}
745
746static inline void hri_mclk_set_AHBMASK_PAC_bit(const void *const hw)
747{
748 MCLK_CRITICAL_SECTION_ENTER();
749 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PAC;
750 MCLK_CRITICAL_SECTION_LEAVE();
751}
752
753static inline bool hri_mclk_get_AHBMASK_PAC_bit(const void *const hw)
754{
755 uint32_t tmp;
756 tmp = ((Mclk *)hw)->AHBMASK.reg;
757 tmp = (tmp & MCLK_AHBMASK_PAC) >> MCLK_AHBMASK_PAC_Pos;
758 return (bool)tmp;
759}
760
761static inline void hri_mclk_write_AHBMASK_PAC_bit(const void *const hw, bool value)
762{
763 uint32_t tmp;
764 MCLK_CRITICAL_SECTION_ENTER();
765 tmp = ((Mclk *)hw)->AHBMASK.reg;
766 tmp &= ~MCLK_AHBMASK_PAC;
767 tmp |= value << MCLK_AHBMASK_PAC_Pos;
768 ((Mclk *)hw)->AHBMASK.reg = tmp;
769 MCLK_CRITICAL_SECTION_LEAVE();
770}
771
772static inline void hri_mclk_clear_AHBMASK_PAC_bit(const void *const hw)
773{
774 MCLK_CRITICAL_SECTION_ENTER();
775 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PAC;
776 MCLK_CRITICAL_SECTION_LEAVE();
777}
778
779static inline void hri_mclk_toggle_AHBMASK_PAC_bit(const void *const hw)
780{
781 MCLK_CRITICAL_SECTION_ENTER();
782 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PAC;
783 MCLK_CRITICAL_SECTION_LEAVE();
784}
785
786static inline void hri_mclk_set_AHBMASK_QSPI_bit(const void *const hw)
787{
788 MCLK_CRITICAL_SECTION_ENTER();
789 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_QSPI;
790 MCLK_CRITICAL_SECTION_LEAVE();
791}
792
793static inline bool hri_mclk_get_AHBMASK_QSPI_bit(const void *const hw)
794{
795 uint32_t tmp;
796 tmp = ((Mclk *)hw)->AHBMASK.reg;
797 tmp = (tmp & MCLK_AHBMASK_QSPI) >> MCLK_AHBMASK_QSPI_Pos;
798 return (bool)tmp;
799}
800
801static inline void hri_mclk_write_AHBMASK_QSPI_bit(const void *const hw, bool value)
802{
803 uint32_t tmp;
804 MCLK_CRITICAL_SECTION_ENTER();
805 tmp = ((Mclk *)hw)->AHBMASK.reg;
806 tmp &= ~MCLK_AHBMASK_QSPI;
807 tmp |= value << MCLK_AHBMASK_QSPI_Pos;
808 ((Mclk *)hw)->AHBMASK.reg = tmp;
809 MCLK_CRITICAL_SECTION_LEAVE();
810}
811
812static inline void hri_mclk_clear_AHBMASK_QSPI_bit(const void *const hw)
813{
814 MCLK_CRITICAL_SECTION_ENTER();
815 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_QSPI;
816 MCLK_CRITICAL_SECTION_LEAVE();
817}
818
819static inline void hri_mclk_toggle_AHBMASK_QSPI_bit(const void *const hw)
820{
821 MCLK_CRITICAL_SECTION_ENTER();
822 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_QSPI;
823 MCLK_CRITICAL_SECTION_LEAVE();
824}
825
826static inline void hri_mclk_set_AHBMASK_GMAC_bit(const void *const hw)
827{
828 MCLK_CRITICAL_SECTION_ENTER();
829 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_GMAC;
830 MCLK_CRITICAL_SECTION_LEAVE();
831}
832
833static inline bool hri_mclk_get_AHBMASK_GMAC_bit(const void *const hw)
834{
835 uint32_t tmp;
836 tmp = ((Mclk *)hw)->AHBMASK.reg;
837 tmp = (tmp & MCLK_AHBMASK_GMAC) >> MCLK_AHBMASK_GMAC_Pos;
838 return (bool)tmp;
839}
840
841static inline void hri_mclk_write_AHBMASK_GMAC_bit(const void *const hw, bool value)
842{
843 uint32_t tmp;
844 MCLK_CRITICAL_SECTION_ENTER();
845 tmp = ((Mclk *)hw)->AHBMASK.reg;
846 tmp &= ~MCLK_AHBMASK_GMAC;
847 tmp |= value << MCLK_AHBMASK_GMAC_Pos;
848 ((Mclk *)hw)->AHBMASK.reg = tmp;
849 MCLK_CRITICAL_SECTION_LEAVE();
850}
851
852static inline void hri_mclk_clear_AHBMASK_GMAC_bit(const void *const hw)
853{
854 MCLK_CRITICAL_SECTION_ENTER();
855 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_GMAC;
856 MCLK_CRITICAL_SECTION_LEAVE();
857}
858
859static inline void hri_mclk_toggle_AHBMASK_GMAC_bit(const void *const hw)
860{
861 MCLK_CRITICAL_SECTION_ENTER();
862 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_GMAC;
863 MCLK_CRITICAL_SECTION_LEAVE();
864}
865
866static inline void hri_mclk_set_AHBMASK_SDHC0_bit(const void *const hw)
867{
868 MCLK_CRITICAL_SECTION_ENTER();
869 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_SDHC0;
870 MCLK_CRITICAL_SECTION_LEAVE();
871}
872
873static inline bool hri_mclk_get_AHBMASK_SDHC0_bit(const void *const hw)
874{
875 uint32_t tmp;
876 tmp = ((Mclk *)hw)->AHBMASK.reg;
877 tmp = (tmp & MCLK_AHBMASK_SDHC0) >> MCLK_AHBMASK_SDHC0_Pos;
878 return (bool)tmp;
879}
880
881static inline void hri_mclk_write_AHBMASK_SDHC0_bit(const void *const hw, bool value)
882{
883 uint32_t tmp;
884 MCLK_CRITICAL_SECTION_ENTER();
885 tmp = ((Mclk *)hw)->AHBMASK.reg;
886 tmp &= ~MCLK_AHBMASK_SDHC0;
887 tmp |= value << MCLK_AHBMASK_SDHC0_Pos;
888 ((Mclk *)hw)->AHBMASK.reg = tmp;
889 MCLK_CRITICAL_SECTION_LEAVE();
890}
891
892static inline void hri_mclk_clear_AHBMASK_SDHC0_bit(const void *const hw)
893{
894 MCLK_CRITICAL_SECTION_ENTER();
895 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_SDHC0;
896 MCLK_CRITICAL_SECTION_LEAVE();
897}
898
899static inline void hri_mclk_toggle_AHBMASK_SDHC0_bit(const void *const hw)
900{
901 MCLK_CRITICAL_SECTION_ENTER();
902 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_SDHC0;
903 MCLK_CRITICAL_SECTION_LEAVE();
904}
905
906static inline void hri_mclk_set_AHBMASK_SDHC1_bit(const void *const hw)
907{
908 MCLK_CRITICAL_SECTION_ENTER();
909 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_SDHC1;
910 MCLK_CRITICAL_SECTION_LEAVE();
911}
912
913static inline bool hri_mclk_get_AHBMASK_SDHC1_bit(const void *const hw)
914{
915 uint32_t tmp;
916 tmp = ((Mclk *)hw)->AHBMASK.reg;
917 tmp = (tmp & MCLK_AHBMASK_SDHC1) >> MCLK_AHBMASK_SDHC1_Pos;
918 return (bool)tmp;
919}
920
921static inline void hri_mclk_write_AHBMASK_SDHC1_bit(const void *const hw, bool value)
922{
923 uint32_t tmp;
924 MCLK_CRITICAL_SECTION_ENTER();
925 tmp = ((Mclk *)hw)->AHBMASK.reg;
926 tmp &= ~MCLK_AHBMASK_SDHC1;
927 tmp |= value << MCLK_AHBMASK_SDHC1_Pos;
928 ((Mclk *)hw)->AHBMASK.reg = tmp;
929 MCLK_CRITICAL_SECTION_LEAVE();
930}
931
932static inline void hri_mclk_clear_AHBMASK_SDHC1_bit(const void *const hw)
933{
934 MCLK_CRITICAL_SECTION_ENTER();
935 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_SDHC1;
936 MCLK_CRITICAL_SECTION_LEAVE();
937}
938
939static inline void hri_mclk_toggle_AHBMASK_SDHC1_bit(const void *const hw)
940{
941 MCLK_CRITICAL_SECTION_ENTER();
942 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_SDHC1;
943 MCLK_CRITICAL_SECTION_LEAVE();
944}
945
946static inline void hri_mclk_set_AHBMASK_CAN0_bit(const void *const hw)
947{
948 MCLK_CRITICAL_SECTION_ENTER();
949 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CAN0;
950 MCLK_CRITICAL_SECTION_LEAVE();
951}
952
953static inline bool hri_mclk_get_AHBMASK_CAN0_bit(const void *const hw)
954{
955 uint32_t tmp;
956 tmp = ((Mclk *)hw)->AHBMASK.reg;
957 tmp = (tmp & MCLK_AHBMASK_CAN0) >> MCLK_AHBMASK_CAN0_Pos;
958 return (bool)tmp;
959}
960
961static inline void hri_mclk_write_AHBMASK_CAN0_bit(const void *const hw, bool value)
962{
963 uint32_t tmp;
964 MCLK_CRITICAL_SECTION_ENTER();
965 tmp = ((Mclk *)hw)->AHBMASK.reg;
966 tmp &= ~MCLK_AHBMASK_CAN0;
967 tmp |= value << MCLK_AHBMASK_CAN0_Pos;
968 ((Mclk *)hw)->AHBMASK.reg = tmp;
969 MCLK_CRITICAL_SECTION_LEAVE();
970}
971
972static inline void hri_mclk_clear_AHBMASK_CAN0_bit(const void *const hw)
973{
974 MCLK_CRITICAL_SECTION_ENTER();
975 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CAN0;
976 MCLK_CRITICAL_SECTION_LEAVE();
977}
978
979static inline void hri_mclk_toggle_AHBMASK_CAN0_bit(const void *const hw)
980{
981 MCLK_CRITICAL_SECTION_ENTER();
982 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CAN0;
983 MCLK_CRITICAL_SECTION_LEAVE();
984}
985
986static inline void hri_mclk_set_AHBMASK_CAN1_bit(const void *const hw)
987{
988 MCLK_CRITICAL_SECTION_ENTER();
989 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CAN1;
990 MCLK_CRITICAL_SECTION_LEAVE();
991}
992
993static inline bool hri_mclk_get_AHBMASK_CAN1_bit(const void *const hw)
994{
995 uint32_t tmp;
996 tmp = ((Mclk *)hw)->AHBMASK.reg;
997 tmp = (tmp & MCLK_AHBMASK_CAN1) >> MCLK_AHBMASK_CAN1_Pos;
998 return (bool)tmp;
999}
1000
1001static inline void hri_mclk_write_AHBMASK_CAN1_bit(const void *const hw, bool value)
1002{
1003 uint32_t tmp;
1004 MCLK_CRITICAL_SECTION_ENTER();
1005 tmp = ((Mclk *)hw)->AHBMASK.reg;
1006 tmp &= ~MCLK_AHBMASK_CAN1;
1007 tmp |= value << MCLK_AHBMASK_CAN1_Pos;
1008 ((Mclk *)hw)->AHBMASK.reg = tmp;
1009 MCLK_CRITICAL_SECTION_LEAVE();
1010}
1011
1012static inline void hri_mclk_clear_AHBMASK_CAN1_bit(const void *const hw)
1013{
1014 MCLK_CRITICAL_SECTION_ENTER();
1015 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CAN1;
1016 MCLK_CRITICAL_SECTION_LEAVE();
1017}
1018
1019static inline void hri_mclk_toggle_AHBMASK_CAN1_bit(const void *const hw)
1020{
1021 MCLK_CRITICAL_SECTION_ENTER();
1022 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CAN1;
1023 MCLK_CRITICAL_SECTION_LEAVE();
1024}
1025
1026static inline void hri_mclk_set_AHBMASK_ICM_bit(const void *const hw)
1027{
1028 MCLK_CRITICAL_SECTION_ENTER();
1029 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_ICM;
1030 MCLK_CRITICAL_SECTION_LEAVE();
1031}
1032
1033static inline bool hri_mclk_get_AHBMASK_ICM_bit(const void *const hw)
1034{
1035 uint32_t tmp;
1036 tmp = ((Mclk *)hw)->AHBMASK.reg;
1037 tmp = (tmp & MCLK_AHBMASK_ICM) >> MCLK_AHBMASK_ICM_Pos;
1038 return (bool)tmp;
1039}
1040
1041static inline void hri_mclk_write_AHBMASK_ICM_bit(const void *const hw, bool value)
1042{
1043 uint32_t tmp;
1044 MCLK_CRITICAL_SECTION_ENTER();
1045 tmp = ((Mclk *)hw)->AHBMASK.reg;
1046 tmp &= ~MCLK_AHBMASK_ICM;
1047 tmp |= value << MCLK_AHBMASK_ICM_Pos;
1048 ((Mclk *)hw)->AHBMASK.reg = tmp;
1049 MCLK_CRITICAL_SECTION_LEAVE();
1050}
1051
1052static inline void hri_mclk_clear_AHBMASK_ICM_bit(const void *const hw)
1053{
1054 MCLK_CRITICAL_SECTION_ENTER();
1055 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_ICM;
1056 MCLK_CRITICAL_SECTION_LEAVE();
1057}
1058
1059static inline void hri_mclk_toggle_AHBMASK_ICM_bit(const void *const hw)
1060{
1061 MCLK_CRITICAL_SECTION_ENTER();
1062 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_ICM;
1063 MCLK_CRITICAL_SECTION_LEAVE();
1064}
1065
1066static inline void hri_mclk_set_AHBMASK_PUKCC_bit(const void *const hw)
1067{
1068 MCLK_CRITICAL_SECTION_ENTER();
1069 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PUKCC;
1070 MCLK_CRITICAL_SECTION_LEAVE();
1071}
1072
1073static inline bool hri_mclk_get_AHBMASK_PUKCC_bit(const void *const hw)
1074{
1075 uint32_t tmp;
1076 tmp = ((Mclk *)hw)->AHBMASK.reg;
1077 tmp = (tmp & MCLK_AHBMASK_PUKCC) >> MCLK_AHBMASK_PUKCC_Pos;
1078 return (bool)tmp;
1079}
1080
1081static inline void hri_mclk_write_AHBMASK_PUKCC_bit(const void *const hw, bool value)
1082{
1083 uint32_t tmp;
1084 MCLK_CRITICAL_SECTION_ENTER();
1085 tmp = ((Mclk *)hw)->AHBMASK.reg;
1086 tmp &= ~MCLK_AHBMASK_PUKCC;
1087 tmp |= value << MCLK_AHBMASK_PUKCC_Pos;
1088 ((Mclk *)hw)->AHBMASK.reg = tmp;
1089 MCLK_CRITICAL_SECTION_LEAVE();
1090}
1091
1092static inline void hri_mclk_clear_AHBMASK_PUKCC_bit(const void *const hw)
1093{
1094 MCLK_CRITICAL_SECTION_ENTER();
1095 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PUKCC;
1096 MCLK_CRITICAL_SECTION_LEAVE();
1097}
1098
1099static inline void hri_mclk_toggle_AHBMASK_PUKCC_bit(const void *const hw)
1100{
1101 MCLK_CRITICAL_SECTION_ENTER();
1102 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PUKCC;
1103 MCLK_CRITICAL_SECTION_LEAVE();
1104}
1105
1106static inline void hri_mclk_set_AHBMASK_QSPI_2X_bit(const void *const hw)
1107{
1108 MCLK_CRITICAL_SECTION_ENTER();
1109 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_QSPI_2X;
1110 MCLK_CRITICAL_SECTION_LEAVE();
1111}
1112
1113static inline bool hri_mclk_get_AHBMASK_QSPI_2X_bit(const void *const hw)
1114{
1115 uint32_t tmp;
1116 tmp = ((Mclk *)hw)->AHBMASK.reg;
1117 tmp = (tmp & MCLK_AHBMASK_QSPI_2X) >> MCLK_AHBMASK_QSPI_2X_Pos;
1118 return (bool)tmp;
1119}
1120
1121static inline void hri_mclk_write_AHBMASK_QSPI_2X_bit(const void *const hw, bool value)
1122{
1123 uint32_t tmp;
1124 MCLK_CRITICAL_SECTION_ENTER();
1125 tmp = ((Mclk *)hw)->AHBMASK.reg;
1126 tmp &= ~MCLK_AHBMASK_QSPI_2X;
1127 tmp |= value << MCLK_AHBMASK_QSPI_2X_Pos;
1128 ((Mclk *)hw)->AHBMASK.reg = tmp;
1129 MCLK_CRITICAL_SECTION_LEAVE();
1130}
1131
1132static inline void hri_mclk_clear_AHBMASK_QSPI_2X_bit(const void *const hw)
1133{
1134 MCLK_CRITICAL_SECTION_ENTER();
1135 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_QSPI_2X;
1136 MCLK_CRITICAL_SECTION_LEAVE();
1137}
1138
1139static inline void hri_mclk_toggle_AHBMASK_QSPI_2X_bit(const void *const hw)
1140{
1141 MCLK_CRITICAL_SECTION_ENTER();
1142 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_QSPI_2X;
1143 MCLK_CRITICAL_SECTION_LEAVE();
1144}
1145
1146static inline void hri_mclk_set_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw)
1147{
1148 MCLK_CRITICAL_SECTION_ENTER();
1149 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_SMEEPROM;
1150 MCLK_CRITICAL_SECTION_LEAVE();
1151}
1152
1153static inline bool hri_mclk_get_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw)
1154{
1155 uint32_t tmp;
1156 tmp = ((Mclk *)hw)->AHBMASK.reg;
1157 tmp = (tmp & MCLK_AHBMASK_NVMCTRL_SMEEPROM) >> MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos;
1158 return (bool)tmp;
1159}
1160
1161static inline void hri_mclk_write_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw, bool value)
1162{
1163 uint32_t tmp;
1164 MCLK_CRITICAL_SECTION_ENTER();
1165 tmp = ((Mclk *)hw)->AHBMASK.reg;
1166 tmp &= ~MCLK_AHBMASK_NVMCTRL_SMEEPROM;
1167 tmp |= value << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos;
1168 ((Mclk *)hw)->AHBMASK.reg = tmp;
1169 MCLK_CRITICAL_SECTION_LEAVE();
1170}
1171
1172static inline void hri_mclk_clear_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw)
1173{
1174 MCLK_CRITICAL_SECTION_ENTER();
1175 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_SMEEPROM;
1176 MCLK_CRITICAL_SECTION_LEAVE();
1177}
1178
1179static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw)
1180{
1181 MCLK_CRITICAL_SECTION_ENTER();
1182 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_SMEEPROM;
1183 MCLK_CRITICAL_SECTION_LEAVE();
1184}
1185
1186static inline void hri_mclk_set_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw)
1187{
1188 MCLK_CRITICAL_SECTION_ENTER();
1189 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_CACHE;
1190 MCLK_CRITICAL_SECTION_LEAVE();
1191}
1192
1193static inline bool hri_mclk_get_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw)
1194{
1195 uint32_t tmp;
1196 tmp = ((Mclk *)hw)->AHBMASK.reg;
1197 tmp = (tmp & MCLK_AHBMASK_NVMCTRL_CACHE) >> MCLK_AHBMASK_NVMCTRL_CACHE_Pos;
1198 return (bool)tmp;
1199}
1200
1201static inline void hri_mclk_write_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw, bool value)
1202{
1203 uint32_t tmp;
1204 MCLK_CRITICAL_SECTION_ENTER();
1205 tmp = ((Mclk *)hw)->AHBMASK.reg;
1206 tmp &= ~MCLK_AHBMASK_NVMCTRL_CACHE;
1207 tmp |= value << MCLK_AHBMASK_NVMCTRL_CACHE_Pos;
1208 ((Mclk *)hw)->AHBMASK.reg = tmp;
1209 MCLK_CRITICAL_SECTION_LEAVE();
1210}
1211
1212static inline void hri_mclk_clear_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw)
1213{
1214 MCLK_CRITICAL_SECTION_ENTER();
1215 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_CACHE;
1216 MCLK_CRITICAL_SECTION_LEAVE();
1217}
1218
1219static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw)
1220{
1221 MCLK_CRITICAL_SECTION_ENTER();
1222 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_CACHE;
1223 MCLK_CRITICAL_SECTION_LEAVE();
1224}
1225
1226static inline void hri_mclk_set_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask)
1227{
1228 MCLK_CRITICAL_SECTION_ENTER();
1229 ((Mclk *)hw)->AHBMASK.reg |= mask;
1230 MCLK_CRITICAL_SECTION_LEAVE();
1231}
1232
1233static inline hri_mclk_ahbmask_reg_t hri_mclk_get_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask)
1234{
1235 uint32_t tmp;
1236 tmp = ((Mclk *)hw)->AHBMASK.reg;
1237 tmp &= mask;
1238 return tmp;
1239}
1240
1241static inline void hri_mclk_write_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t data)
1242{
1243 MCLK_CRITICAL_SECTION_ENTER();
1244 ((Mclk *)hw)->AHBMASK.reg = data;
1245 MCLK_CRITICAL_SECTION_LEAVE();
1246}
1247
1248static inline void hri_mclk_clear_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask)
1249{
1250 MCLK_CRITICAL_SECTION_ENTER();
1251 ((Mclk *)hw)->AHBMASK.reg &= ~mask;
1252 MCLK_CRITICAL_SECTION_LEAVE();
1253}
1254
1255static inline void hri_mclk_toggle_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask)
1256{
1257 MCLK_CRITICAL_SECTION_ENTER();
1258 ((Mclk *)hw)->AHBMASK.reg ^= mask;
1259 MCLK_CRITICAL_SECTION_LEAVE();
1260}
1261
1262static inline hri_mclk_ahbmask_reg_t hri_mclk_read_AHBMASK_reg(const void *const hw)
1263{
1264 return ((Mclk *)hw)->AHBMASK.reg;
1265}
1266
1267static inline void hri_mclk_set_APBAMASK_PAC_bit(const void *const hw)
1268{
1269 MCLK_CRITICAL_SECTION_ENTER();
1270 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PAC;
1271 MCLK_CRITICAL_SECTION_LEAVE();
1272}
1273
1274static inline bool hri_mclk_get_APBAMASK_PAC_bit(const void *const hw)
1275{
1276 uint32_t tmp;
1277 tmp = ((Mclk *)hw)->APBAMASK.reg;
1278 tmp = (tmp & MCLK_APBAMASK_PAC) >> MCLK_APBAMASK_PAC_Pos;
1279 return (bool)tmp;
1280}
1281
1282static inline void hri_mclk_write_APBAMASK_PAC_bit(const void *const hw, bool value)
1283{
1284 uint32_t tmp;
1285 MCLK_CRITICAL_SECTION_ENTER();
1286 tmp = ((Mclk *)hw)->APBAMASK.reg;
1287 tmp &= ~MCLK_APBAMASK_PAC;
1288 tmp |= value << MCLK_APBAMASK_PAC_Pos;
1289 ((Mclk *)hw)->APBAMASK.reg = tmp;
1290 MCLK_CRITICAL_SECTION_LEAVE();
1291}
1292
1293static inline void hri_mclk_clear_APBAMASK_PAC_bit(const void *const hw)
1294{
1295 MCLK_CRITICAL_SECTION_ENTER();
1296 ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PAC;
1297 MCLK_CRITICAL_SECTION_LEAVE();
1298}
1299
1300static inline void hri_mclk_toggle_APBAMASK_PAC_bit(const void *const hw)
1301{
1302 MCLK_CRITICAL_SECTION_ENTER();
1303 ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PAC;
1304 MCLK_CRITICAL_SECTION_LEAVE();
1305}
1306
1307static inline void hri_mclk_set_APBAMASK_PM_bit(const void *const hw)
1308{
1309 MCLK_CRITICAL_SECTION_ENTER();
1310 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PM;
1311 MCLK_CRITICAL_SECTION_LEAVE();
1312}
1313
1314static inline bool hri_mclk_get_APBAMASK_PM_bit(const void *const hw)
1315{
1316 uint32_t tmp;
1317 tmp = ((Mclk *)hw)->APBAMASK.reg;
1318 tmp = (tmp & MCLK_APBAMASK_PM) >> MCLK_APBAMASK_PM_Pos;
1319 return (bool)tmp;
1320}
1321
1322static inline void hri_mclk_write_APBAMASK_PM_bit(const void *const hw, bool value)
1323{
1324 uint32_t tmp;
1325 MCLK_CRITICAL_SECTION_ENTER();
1326 tmp = ((Mclk *)hw)->APBAMASK.reg;
1327 tmp &= ~MCLK_APBAMASK_PM;
1328 tmp |= value << MCLK_APBAMASK_PM_Pos;
1329 ((Mclk *)hw)->APBAMASK.reg = tmp;
1330 MCLK_CRITICAL_SECTION_LEAVE();
1331}
1332
1333static inline void hri_mclk_clear_APBAMASK_PM_bit(const void *const hw)
1334{
1335 MCLK_CRITICAL_SECTION_ENTER();
1336 ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PM;
1337 MCLK_CRITICAL_SECTION_LEAVE();
1338}
1339
1340static inline void hri_mclk_toggle_APBAMASK_PM_bit(const void *const hw)
1341{
1342 MCLK_CRITICAL_SECTION_ENTER();
1343 ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PM;
1344 MCLK_CRITICAL_SECTION_LEAVE();
1345}
1346
1347static inline void hri_mclk_set_APBAMASK_MCLK_bit(const void *const hw)
1348{
1349 MCLK_CRITICAL_SECTION_ENTER();
1350 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_MCLK;
1351 MCLK_CRITICAL_SECTION_LEAVE();
1352}
1353
1354static inline bool hri_mclk_get_APBAMASK_MCLK_bit(const void *const hw)
1355{
1356 uint32_t tmp;
1357 tmp = ((Mclk *)hw)->APBAMASK.reg;
1358 tmp = (tmp & MCLK_APBAMASK_MCLK) >> MCLK_APBAMASK_MCLK_Pos;
1359 return (bool)tmp;
1360}
1361
1362static inline void hri_mclk_write_APBAMASK_MCLK_bit(const void *const hw, bool value)
1363{
1364 uint32_t tmp;
1365 MCLK_CRITICAL_SECTION_ENTER();
1366 tmp = ((Mclk *)hw)->APBAMASK.reg;
1367 tmp &= ~MCLK_APBAMASK_MCLK;
1368 tmp |= value << MCLK_APBAMASK_MCLK_Pos;
1369 ((Mclk *)hw)->APBAMASK.reg = tmp;
1370 MCLK_CRITICAL_SECTION_LEAVE();
1371}
1372
1373static inline void hri_mclk_clear_APBAMASK_MCLK_bit(const void *const hw)
1374{
1375 MCLK_CRITICAL_SECTION_ENTER();
1376 ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_MCLK;
1377 MCLK_CRITICAL_SECTION_LEAVE();
1378}
1379
1380static inline void hri_mclk_toggle_APBAMASK_MCLK_bit(const void *const hw)
1381{
1382 MCLK_CRITICAL_SECTION_ENTER();
1383 ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_MCLK;
1384 MCLK_CRITICAL_SECTION_LEAVE();
1385}
1386
1387static inline void hri_mclk_set_APBAMASK_RSTC_bit(const void *const hw)
1388{
1389 MCLK_CRITICAL_SECTION_ENTER();
1390 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RSTC;
1391 MCLK_CRITICAL_SECTION_LEAVE();
1392}
1393
1394static inline bool hri_mclk_get_APBAMASK_RSTC_bit(const void *const hw)
1395{
1396 uint32_t tmp;
1397 tmp = ((Mclk *)hw)->APBAMASK.reg;
1398 tmp = (tmp & MCLK_APBAMASK_RSTC) >> MCLK_APBAMASK_RSTC_Pos;
1399 return (bool)tmp;
1400}
1401
1402static inline void hri_mclk_write_APBAMASK_RSTC_bit(const void *const hw, bool value)
1403{
1404 uint32_t tmp;
1405 MCLK_CRITICAL_SECTION_ENTER();
1406 tmp = ((Mclk *)hw)->APBAMASK.reg;
1407 tmp &= ~MCLK_APBAMASK_RSTC;
1408 tmp |= value << MCLK_APBAMASK_RSTC_Pos;
1409 ((Mclk *)hw)->APBAMASK.reg = tmp;
1410 MCLK_CRITICAL_SECTION_LEAVE();
1411}
1412
1413static inline void hri_mclk_clear_APBAMASK_RSTC_bit(const void *const hw)
1414{
1415 MCLK_CRITICAL_SECTION_ENTER();
1416 ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RSTC;
1417 MCLK_CRITICAL_SECTION_LEAVE();
1418}
1419
1420static inline void hri_mclk_toggle_APBAMASK_RSTC_bit(const void *const hw)
1421{
1422 MCLK_CRITICAL_SECTION_ENTER();
1423 ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RSTC;
1424 MCLK_CRITICAL_SECTION_LEAVE();
1425}
1426
1427static inline void hri_mclk_set_APBAMASK_OSCCTRL_bit(const void *const hw)
1428{
1429 MCLK_CRITICAL_SECTION_ENTER();
1430 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSCCTRL;
1431 MCLK_CRITICAL_SECTION_LEAVE();
1432}
1433
1434static inline bool hri_mclk_get_APBAMASK_OSCCTRL_bit(const void *const hw)
1435{
1436 uint32_t tmp;
1437 tmp = ((Mclk *)hw)->APBAMASK.reg;
1438 tmp = (tmp & MCLK_APBAMASK_OSCCTRL) >> MCLK_APBAMASK_OSCCTRL_Pos;
1439 return (bool)tmp;
1440}
1441
1442static inline void hri_mclk_write_APBAMASK_OSCCTRL_bit(const void *const hw, bool value)
1443{
1444 uint32_t tmp;
1445 MCLK_CRITICAL_SECTION_ENTER();
1446 tmp = ((Mclk *)hw)->APBAMASK.reg;
1447 tmp &= ~MCLK_APBAMASK_OSCCTRL;
1448 tmp |= value << MCLK_APBAMASK_OSCCTRL_Pos;
1449 ((Mclk *)hw)->APBAMASK.reg = tmp;
1450 MCLK_CRITICAL_SECTION_LEAVE();
1451}
1452
1453static inline void hri_mclk_clear_APBAMASK_OSCCTRL_bit(const void *const hw)
1454{
1455 MCLK_CRITICAL_SECTION_ENTER();
1456 ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSCCTRL;
1457 MCLK_CRITICAL_SECTION_LEAVE();
1458}
1459
1460static inline void hri_mclk_toggle_APBAMASK_OSCCTRL_bit(const void *const hw)
1461{
1462 MCLK_CRITICAL_SECTION_ENTER();
1463 ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSCCTRL;
1464 MCLK_CRITICAL_SECTION_LEAVE();
1465}
1466
1467static inline void hri_mclk_set_APBAMASK_OSC32KCTRL_bit(const void *const hw)
1468{
1469 MCLK_CRITICAL_SECTION_ENTER();
1470 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSC32KCTRL;
1471 MCLK_CRITICAL_SECTION_LEAVE();
1472}
1473
1474static inline bool hri_mclk_get_APBAMASK_OSC32KCTRL_bit(const void *const hw)
1475{
1476 uint32_t tmp;
1477 tmp = ((Mclk *)hw)->APBAMASK.reg;
1478 tmp = (tmp & MCLK_APBAMASK_OSC32KCTRL) >> MCLK_APBAMASK_OSC32KCTRL_Pos;
1479 return (bool)tmp;
1480}
1481
1482static inline void hri_mclk_write_APBAMASK_OSC32KCTRL_bit(const void *const hw, bool value)
1483{
1484 uint32_t tmp;
1485 MCLK_CRITICAL_SECTION_ENTER();
1486 tmp = ((Mclk *)hw)->APBAMASK.reg;
1487 tmp &= ~MCLK_APBAMASK_OSC32KCTRL;
1488 tmp |= value << MCLK_APBAMASK_OSC32KCTRL_Pos;
1489 ((Mclk *)hw)->APBAMASK.reg = tmp;
1490 MCLK_CRITICAL_SECTION_LEAVE();
1491}
1492
1493static inline void hri_mclk_clear_APBAMASK_OSC32KCTRL_bit(const void *const hw)
1494{
1495 MCLK_CRITICAL_SECTION_ENTER();
1496 ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSC32KCTRL;
1497 MCLK_CRITICAL_SECTION_LEAVE();
1498}
1499
1500static inline void hri_mclk_toggle_APBAMASK_OSC32KCTRL_bit(const void *const hw)
1501{
1502 MCLK_CRITICAL_SECTION_ENTER();
1503 ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSC32KCTRL;
1504 MCLK_CRITICAL_SECTION_LEAVE();
1505}
1506
1507static inline void hri_mclk_set_APBAMASK_SUPC_bit(const void *const hw)
1508{
1509 MCLK_CRITICAL_SECTION_ENTER();
1510 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SUPC;
1511 MCLK_CRITICAL_SECTION_LEAVE();
1512}
1513
1514static inline bool hri_mclk_get_APBAMASK_SUPC_bit(const void *const hw)
1515{
1516 uint32_t tmp;
1517 tmp = ((Mclk *)hw)->APBAMASK.reg;
1518 tmp = (tmp & MCLK_APBAMASK_SUPC) >> MCLK_APBAMASK_SUPC_Pos;
1519 return (bool)tmp;
1520}
1521
1522static inline void hri_mclk_write_APBAMASK_SUPC_bit(const void *const hw, bool value)
1523{
1524 uint32_t tmp;
1525 MCLK_CRITICAL_SECTION_ENTER();
1526 tmp = ((Mclk *)hw)->APBAMASK.reg;
1527 tmp &= ~MCLK_APBAMASK_SUPC;
1528 tmp |= value << MCLK_APBAMASK_SUPC_Pos;
1529 ((Mclk *)hw)->APBAMASK.reg = tmp;
1530 MCLK_CRITICAL_SECTION_LEAVE();
1531}
1532
1533static inline void hri_mclk_clear_APBAMASK_SUPC_bit(const void *const hw)
1534{
1535 MCLK_CRITICAL_SECTION_ENTER();
1536 ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SUPC;
1537 MCLK_CRITICAL_SECTION_LEAVE();
1538}
1539
1540static inline void hri_mclk_toggle_APBAMASK_SUPC_bit(const void *const hw)
1541{
1542 MCLK_CRITICAL_SECTION_ENTER();
1543 ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SUPC;
1544 MCLK_CRITICAL_SECTION_LEAVE();
1545}
1546
1547static inline void hri_mclk_set_APBAMASK_GCLK_bit(const void *const hw)
1548{
1549 MCLK_CRITICAL_SECTION_ENTER();
1550 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_GCLK;
1551 MCLK_CRITICAL_SECTION_LEAVE();
1552}
1553
1554static inline bool hri_mclk_get_APBAMASK_GCLK_bit(const void *const hw)
1555{
1556 uint32_t tmp;
1557 tmp = ((Mclk *)hw)->APBAMASK.reg;
1558 tmp = (tmp & MCLK_APBAMASK_GCLK) >> MCLK_APBAMASK_GCLK_Pos;
1559 return (bool)tmp;
1560}
1561
1562static inline void hri_mclk_write_APBAMASK_GCLK_bit(const void *const hw, bool value)
1563{
1564 uint32_t tmp;
1565 MCLK_CRITICAL_SECTION_ENTER();
1566 tmp = ((Mclk *)hw)->APBAMASK.reg;
1567 tmp &= ~MCLK_APBAMASK_GCLK;
1568 tmp |= value << MCLK_APBAMASK_GCLK_Pos;
1569 ((Mclk *)hw)->APBAMASK.reg = tmp;
1570 MCLK_CRITICAL_SECTION_LEAVE();
1571}
1572
1573static inline void hri_mclk_clear_APBAMASK_GCLK_bit(const void *const hw)
1574{
1575 MCLK_CRITICAL_SECTION_ENTER();
1576 ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_GCLK;
1577 MCLK_CRITICAL_SECTION_LEAVE();
1578}
1579
1580static inline void hri_mclk_toggle_APBAMASK_GCLK_bit(const void *const hw)
1581{
1582 MCLK_CRITICAL_SECTION_ENTER();
1583 ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_GCLK;
1584 MCLK_CRITICAL_SECTION_LEAVE();
1585}
1586
1587static inline void hri_mclk_set_APBAMASK_WDT_bit(const void *const hw)
1588{
1589 MCLK_CRITICAL_SECTION_ENTER();
1590 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_WDT;
1591 MCLK_CRITICAL_SECTION_LEAVE();
1592}
1593
1594static inline bool hri_mclk_get_APBAMASK_WDT_bit(const void *const hw)
1595{
1596 uint32_t tmp;
1597 tmp = ((Mclk *)hw)->APBAMASK.reg;
1598 tmp = (tmp & MCLK_APBAMASK_WDT) >> MCLK_APBAMASK_WDT_Pos;
1599 return (bool)tmp;
1600}
1601
1602static inline void hri_mclk_write_APBAMASK_WDT_bit(const void *const hw, bool value)
1603{
1604 uint32_t tmp;
1605 MCLK_CRITICAL_SECTION_ENTER();
1606 tmp = ((Mclk *)hw)->APBAMASK.reg;
1607 tmp &= ~MCLK_APBAMASK_WDT;
1608 tmp |= value << MCLK_APBAMASK_WDT_Pos;
1609 ((Mclk *)hw)->APBAMASK.reg = tmp;
1610 MCLK_CRITICAL_SECTION_LEAVE();
1611}
1612
1613static inline void hri_mclk_clear_APBAMASK_WDT_bit(const void *const hw)
1614{
1615 MCLK_CRITICAL_SECTION_ENTER();
1616 ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_WDT;
1617 MCLK_CRITICAL_SECTION_LEAVE();
1618}
1619
1620static inline void hri_mclk_toggle_APBAMASK_WDT_bit(const void *const hw)
1621{
1622 MCLK_CRITICAL_SECTION_ENTER();
1623 ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_WDT;
1624 MCLK_CRITICAL_SECTION_LEAVE();
1625}
1626
1627static inline void hri_mclk_set_APBAMASK_RTC_bit(const void *const hw)
1628{
1629 MCLK_CRITICAL_SECTION_ENTER();
1630 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RTC;
1631 MCLK_CRITICAL_SECTION_LEAVE();
1632}
1633
1634static inline bool hri_mclk_get_APBAMASK_RTC_bit(const void *const hw)
1635{
1636 uint32_t tmp;
1637 tmp = ((Mclk *)hw)->APBAMASK.reg;
1638 tmp = (tmp & MCLK_APBAMASK_RTC) >> MCLK_APBAMASK_RTC_Pos;
1639 return (bool)tmp;
1640}
1641
1642static inline void hri_mclk_write_APBAMASK_RTC_bit(const void *const hw, bool value)
1643{
1644 uint32_t tmp;
1645 MCLK_CRITICAL_SECTION_ENTER();
1646 tmp = ((Mclk *)hw)->APBAMASK.reg;
1647 tmp &= ~MCLK_APBAMASK_RTC;
1648 tmp |= value << MCLK_APBAMASK_RTC_Pos;
1649 ((Mclk *)hw)->APBAMASK.reg = tmp;
1650 MCLK_CRITICAL_SECTION_LEAVE();
1651}
1652
1653static inline void hri_mclk_clear_APBAMASK_RTC_bit(const void *const hw)
1654{
1655 MCLK_CRITICAL_SECTION_ENTER();
1656 ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RTC;
1657 MCLK_CRITICAL_SECTION_LEAVE();
1658}
1659
1660static inline void hri_mclk_toggle_APBAMASK_RTC_bit(const void *const hw)
1661{
1662 MCLK_CRITICAL_SECTION_ENTER();
1663 ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RTC;
1664 MCLK_CRITICAL_SECTION_LEAVE();
1665}
1666
1667static inline void hri_mclk_set_APBAMASK_EIC_bit(const void *const hw)
1668{
1669 MCLK_CRITICAL_SECTION_ENTER();
1670 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_EIC;
1671 MCLK_CRITICAL_SECTION_LEAVE();
1672}
1673
1674static inline bool hri_mclk_get_APBAMASK_EIC_bit(const void *const hw)
1675{
1676 uint32_t tmp;
1677 tmp = ((Mclk *)hw)->APBAMASK.reg;
1678 tmp = (tmp & MCLK_APBAMASK_EIC) >> MCLK_APBAMASK_EIC_Pos;
1679 return (bool)tmp;
1680}
1681
1682static inline void hri_mclk_write_APBAMASK_EIC_bit(const void *const hw, bool value)
1683{
1684 uint32_t tmp;
1685 MCLK_CRITICAL_SECTION_ENTER();
1686 tmp = ((Mclk *)hw)->APBAMASK.reg;
1687 tmp &= ~MCLK_APBAMASK_EIC;
1688 tmp |= value << MCLK_APBAMASK_EIC_Pos;
1689 ((Mclk *)hw)->APBAMASK.reg = tmp;
1690 MCLK_CRITICAL_SECTION_LEAVE();
1691}
1692
1693static inline void hri_mclk_clear_APBAMASK_EIC_bit(const void *const hw)
1694{
1695 MCLK_CRITICAL_SECTION_ENTER();
1696 ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_EIC;
1697 MCLK_CRITICAL_SECTION_LEAVE();
1698}
1699
1700static inline void hri_mclk_toggle_APBAMASK_EIC_bit(const void *const hw)
1701{
1702 MCLK_CRITICAL_SECTION_ENTER();
1703 ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_EIC;
1704 MCLK_CRITICAL_SECTION_LEAVE();
1705}
1706
1707static inline void hri_mclk_set_APBAMASK_FREQM_bit(const void *const hw)
1708{
1709 MCLK_CRITICAL_SECTION_ENTER();
1710 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_FREQM;
1711 MCLK_CRITICAL_SECTION_LEAVE();
1712}
1713
1714static inline bool hri_mclk_get_APBAMASK_FREQM_bit(const void *const hw)
1715{
1716 uint32_t tmp;
1717 tmp = ((Mclk *)hw)->APBAMASK.reg;
1718 tmp = (tmp & MCLK_APBAMASK_FREQM) >> MCLK_APBAMASK_FREQM_Pos;
1719 return (bool)tmp;
1720}
1721
1722static inline void hri_mclk_write_APBAMASK_FREQM_bit(const void *const hw, bool value)
1723{
1724 uint32_t tmp;
1725 MCLK_CRITICAL_SECTION_ENTER();
1726 tmp = ((Mclk *)hw)->APBAMASK.reg;
1727 tmp &= ~MCLK_APBAMASK_FREQM;
1728 tmp |= value << MCLK_APBAMASK_FREQM_Pos;
1729 ((Mclk *)hw)->APBAMASK.reg = tmp;
1730 MCLK_CRITICAL_SECTION_LEAVE();
1731}
1732
1733static inline void hri_mclk_clear_APBAMASK_FREQM_bit(const void *const hw)
1734{
1735 MCLK_CRITICAL_SECTION_ENTER();
1736 ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_FREQM;
1737 MCLK_CRITICAL_SECTION_LEAVE();
1738}
1739
1740static inline void hri_mclk_toggle_APBAMASK_FREQM_bit(const void *const hw)
1741{
1742 MCLK_CRITICAL_SECTION_ENTER();
1743 ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_FREQM;
1744 MCLK_CRITICAL_SECTION_LEAVE();
1745}
1746
1747static inline void hri_mclk_set_APBAMASK_SERCOM0_bit(const void *const hw)
1748{
1749 MCLK_CRITICAL_SECTION_ENTER();
1750 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SERCOM0;
1751 MCLK_CRITICAL_SECTION_LEAVE();
1752}
1753
1754static inline bool hri_mclk_get_APBAMASK_SERCOM0_bit(const void *const hw)
1755{
1756 uint32_t tmp;
1757 tmp = ((Mclk *)hw)->APBAMASK.reg;
1758 tmp = (tmp & MCLK_APBAMASK_SERCOM0) >> MCLK_APBAMASK_SERCOM0_Pos;
1759 return (bool)tmp;
1760}
1761
1762static inline void hri_mclk_write_APBAMASK_SERCOM0_bit(const void *const hw, bool value)
1763{
1764 uint32_t tmp;
1765 MCLK_CRITICAL_SECTION_ENTER();
1766 tmp = ((Mclk *)hw)->APBAMASK.reg;
1767 tmp &= ~MCLK_APBAMASK_SERCOM0;
1768 tmp |= value << MCLK_APBAMASK_SERCOM0_Pos;
1769 ((Mclk *)hw)->APBAMASK.reg = tmp;
1770 MCLK_CRITICAL_SECTION_LEAVE();
1771}
1772
1773static inline void hri_mclk_clear_APBAMASK_SERCOM0_bit(const void *const hw)
1774{
1775 MCLK_CRITICAL_SECTION_ENTER();
1776 ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SERCOM0;
1777 MCLK_CRITICAL_SECTION_LEAVE();
1778}
1779
1780static inline void hri_mclk_toggle_APBAMASK_SERCOM0_bit(const void *const hw)
1781{
1782 MCLK_CRITICAL_SECTION_ENTER();
1783 ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SERCOM0;
1784 MCLK_CRITICAL_SECTION_LEAVE();
1785}
1786
1787static inline void hri_mclk_set_APBAMASK_SERCOM1_bit(const void *const hw)
1788{
1789 MCLK_CRITICAL_SECTION_ENTER();
1790 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SERCOM1;
1791 MCLK_CRITICAL_SECTION_LEAVE();
1792}
1793
1794static inline bool hri_mclk_get_APBAMASK_SERCOM1_bit(const void *const hw)
1795{
1796 uint32_t tmp;
1797 tmp = ((Mclk *)hw)->APBAMASK.reg;
1798 tmp = (tmp & MCLK_APBAMASK_SERCOM1) >> MCLK_APBAMASK_SERCOM1_Pos;
1799 return (bool)tmp;
1800}
1801
1802static inline void hri_mclk_write_APBAMASK_SERCOM1_bit(const void *const hw, bool value)
1803{
1804 uint32_t tmp;
1805 MCLK_CRITICAL_SECTION_ENTER();
1806 tmp = ((Mclk *)hw)->APBAMASK.reg;
1807 tmp &= ~MCLK_APBAMASK_SERCOM1;
1808 tmp |= value << MCLK_APBAMASK_SERCOM1_Pos;
1809 ((Mclk *)hw)->APBAMASK.reg = tmp;
1810 MCLK_CRITICAL_SECTION_LEAVE();
1811}
1812
1813static inline void hri_mclk_clear_APBAMASK_SERCOM1_bit(const void *const hw)
1814{
1815 MCLK_CRITICAL_SECTION_ENTER();
1816 ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SERCOM1;
1817 MCLK_CRITICAL_SECTION_LEAVE();
1818}
1819
1820static inline void hri_mclk_toggle_APBAMASK_SERCOM1_bit(const void *const hw)
1821{
1822 MCLK_CRITICAL_SECTION_ENTER();
1823 ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SERCOM1;
1824 MCLK_CRITICAL_SECTION_LEAVE();
1825}
1826
1827static inline void hri_mclk_set_APBAMASK_TC0_bit(const void *const hw)
1828{
1829 MCLK_CRITICAL_SECTION_ENTER();
1830 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC0;
1831 MCLK_CRITICAL_SECTION_LEAVE();
1832}
1833
1834static inline bool hri_mclk_get_APBAMASK_TC0_bit(const void *const hw)
1835{
1836 uint32_t tmp;
1837 tmp = ((Mclk *)hw)->APBAMASK.reg;
1838 tmp = (tmp & MCLK_APBAMASK_TC0) >> MCLK_APBAMASK_TC0_Pos;
1839 return (bool)tmp;
1840}
1841
1842static inline void hri_mclk_write_APBAMASK_TC0_bit(const void *const hw, bool value)
1843{
1844 uint32_t tmp;
1845 MCLK_CRITICAL_SECTION_ENTER();
1846 tmp = ((Mclk *)hw)->APBAMASK.reg;
1847 tmp &= ~MCLK_APBAMASK_TC0;
1848 tmp |= value << MCLK_APBAMASK_TC0_Pos;
1849 ((Mclk *)hw)->APBAMASK.reg = tmp;
1850 MCLK_CRITICAL_SECTION_LEAVE();
1851}
1852
1853static inline void hri_mclk_clear_APBAMASK_TC0_bit(const void *const hw)
1854{
1855 MCLK_CRITICAL_SECTION_ENTER();
1856 ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_TC0;
1857 MCLK_CRITICAL_SECTION_LEAVE();
1858}
1859
1860static inline void hri_mclk_toggle_APBAMASK_TC0_bit(const void *const hw)
1861{
1862 MCLK_CRITICAL_SECTION_ENTER();
1863 ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_TC0;
1864 MCLK_CRITICAL_SECTION_LEAVE();
1865}
1866
1867static inline void hri_mclk_set_APBAMASK_TC1_bit(const void *const hw)
1868{
1869 MCLK_CRITICAL_SECTION_ENTER();
1870 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC1;
1871 MCLK_CRITICAL_SECTION_LEAVE();
1872}
1873
1874static inline bool hri_mclk_get_APBAMASK_TC1_bit(const void *const hw)
1875{
1876 uint32_t tmp;
1877 tmp = ((Mclk *)hw)->APBAMASK.reg;
1878 tmp = (tmp & MCLK_APBAMASK_TC1) >> MCLK_APBAMASK_TC1_Pos;
1879 return (bool)tmp;
1880}
1881
1882static inline void hri_mclk_write_APBAMASK_TC1_bit(const void *const hw, bool value)
1883{
1884 uint32_t tmp;
1885 MCLK_CRITICAL_SECTION_ENTER();
1886 tmp = ((Mclk *)hw)->APBAMASK.reg;
1887 tmp &= ~MCLK_APBAMASK_TC1;
1888 tmp |= value << MCLK_APBAMASK_TC1_Pos;
1889 ((Mclk *)hw)->APBAMASK.reg = tmp;
1890 MCLK_CRITICAL_SECTION_LEAVE();
1891}
1892
1893static inline void hri_mclk_clear_APBAMASK_TC1_bit(const void *const hw)
1894{
1895 MCLK_CRITICAL_SECTION_ENTER();
1896 ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_TC1;
1897 MCLK_CRITICAL_SECTION_LEAVE();
1898}
1899
1900static inline void hri_mclk_toggle_APBAMASK_TC1_bit(const void *const hw)
1901{
1902 MCLK_CRITICAL_SECTION_ENTER();
1903 ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_TC1;
1904 MCLK_CRITICAL_SECTION_LEAVE();
1905}
1906
1907static inline void hri_mclk_set_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask)
1908{
1909 MCLK_CRITICAL_SECTION_ENTER();
1910 ((Mclk *)hw)->APBAMASK.reg |= mask;
1911 MCLK_CRITICAL_SECTION_LEAVE();
1912}
1913
1914static inline hri_mclk_apbamask_reg_t hri_mclk_get_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask)
1915{
1916 uint32_t tmp;
1917 tmp = ((Mclk *)hw)->APBAMASK.reg;
1918 tmp &= mask;
1919 return tmp;
1920}
1921
1922static inline void hri_mclk_write_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t data)
1923{
1924 MCLK_CRITICAL_SECTION_ENTER();
1925 ((Mclk *)hw)->APBAMASK.reg = data;
1926 MCLK_CRITICAL_SECTION_LEAVE();
1927}
1928
1929static inline void hri_mclk_clear_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask)
1930{
1931 MCLK_CRITICAL_SECTION_ENTER();
1932 ((Mclk *)hw)->APBAMASK.reg &= ~mask;
1933 MCLK_CRITICAL_SECTION_LEAVE();
1934}
1935
1936static inline void hri_mclk_toggle_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask)
1937{
1938 MCLK_CRITICAL_SECTION_ENTER();
1939 ((Mclk *)hw)->APBAMASK.reg ^= mask;
1940 MCLK_CRITICAL_SECTION_LEAVE();
1941}
1942
1943static inline hri_mclk_apbamask_reg_t hri_mclk_read_APBAMASK_reg(const void *const hw)
1944{
1945 return ((Mclk *)hw)->APBAMASK.reg;
1946}
1947
1948static inline void hri_mclk_set_APBBMASK_USB_bit(const void *const hw)
1949{
1950 MCLK_CRITICAL_SECTION_ENTER();
1951 ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_USB;
1952 MCLK_CRITICAL_SECTION_LEAVE();
1953}
1954
1955static inline bool hri_mclk_get_APBBMASK_USB_bit(const void *const hw)
1956{
1957 uint32_t tmp;
1958 tmp = ((Mclk *)hw)->APBBMASK.reg;
1959 tmp = (tmp & MCLK_APBBMASK_USB) >> MCLK_APBBMASK_USB_Pos;
1960 return (bool)tmp;
1961}
1962
1963static inline void hri_mclk_write_APBBMASK_USB_bit(const void *const hw, bool value)
1964{
1965 uint32_t tmp;
1966 MCLK_CRITICAL_SECTION_ENTER();
1967 tmp = ((Mclk *)hw)->APBBMASK.reg;
1968 tmp &= ~MCLK_APBBMASK_USB;
1969 tmp |= value << MCLK_APBBMASK_USB_Pos;
1970 ((Mclk *)hw)->APBBMASK.reg = tmp;
1971 MCLK_CRITICAL_SECTION_LEAVE();
1972}
1973
1974static inline void hri_mclk_clear_APBBMASK_USB_bit(const void *const hw)
1975{
1976 MCLK_CRITICAL_SECTION_ENTER();
1977 ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_USB;
1978 MCLK_CRITICAL_SECTION_LEAVE();
1979}
1980
1981static inline void hri_mclk_toggle_APBBMASK_USB_bit(const void *const hw)
1982{
1983 MCLK_CRITICAL_SECTION_ENTER();
1984 ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_USB;
1985 MCLK_CRITICAL_SECTION_LEAVE();
1986}
1987
1988static inline void hri_mclk_set_APBBMASK_DSU_bit(const void *const hw)
1989{
1990 MCLK_CRITICAL_SECTION_ENTER();
1991 ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_DSU;
1992 MCLK_CRITICAL_SECTION_LEAVE();
1993}
1994
1995static inline bool hri_mclk_get_APBBMASK_DSU_bit(const void *const hw)
1996{
1997 uint32_t tmp;
1998 tmp = ((Mclk *)hw)->APBBMASK.reg;
1999 tmp = (tmp & MCLK_APBBMASK_DSU) >> MCLK_APBBMASK_DSU_Pos;
2000 return (bool)tmp;
2001}
2002
2003static inline void hri_mclk_write_APBBMASK_DSU_bit(const void *const hw, bool value)
2004{
2005 uint32_t tmp;
2006 MCLK_CRITICAL_SECTION_ENTER();
2007 tmp = ((Mclk *)hw)->APBBMASK.reg;
2008 tmp &= ~MCLK_APBBMASK_DSU;
2009 tmp |= value << MCLK_APBBMASK_DSU_Pos;
2010 ((Mclk *)hw)->APBBMASK.reg = tmp;
2011 MCLK_CRITICAL_SECTION_LEAVE();
2012}
2013
2014static inline void hri_mclk_clear_APBBMASK_DSU_bit(const void *const hw)
2015{
2016 MCLK_CRITICAL_SECTION_ENTER();
2017 ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_DSU;
2018 MCLK_CRITICAL_SECTION_LEAVE();
2019}
2020
2021static inline void hri_mclk_toggle_APBBMASK_DSU_bit(const void *const hw)
2022{
2023 MCLK_CRITICAL_SECTION_ENTER();
2024 ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_DSU;
2025 MCLK_CRITICAL_SECTION_LEAVE();
2026}
2027
2028static inline void hri_mclk_set_APBBMASK_NVMCTRL_bit(const void *const hw)
2029{
2030 MCLK_CRITICAL_SECTION_ENTER();
2031 ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL;
2032 MCLK_CRITICAL_SECTION_LEAVE();
2033}
2034
2035static inline bool hri_mclk_get_APBBMASK_NVMCTRL_bit(const void *const hw)
2036{
2037 uint32_t tmp;
2038 tmp = ((Mclk *)hw)->APBBMASK.reg;
2039 tmp = (tmp & MCLK_APBBMASK_NVMCTRL) >> MCLK_APBBMASK_NVMCTRL_Pos;
2040 return (bool)tmp;
2041}
2042
2043static inline void hri_mclk_write_APBBMASK_NVMCTRL_bit(const void *const hw, bool value)
2044{
2045 uint32_t tmp;
2046 MCLK_CRITICAL_SECTION_ENTER();
2047 tmp = ((Mclk *)hw)->APBBMASK.reg;
2048 tmp &= ~MCLK_APBBMASK_NVMCTRL;
2049 tmp |= value << MCLK_APBBMASK_NVMCTRL_Pos;
2050 ((Mclk *)hw)->APBBMASK.reg = tmp;
2051 MCLK_CRITICAL_SECTION_LEAVE();
2052}
2053
2054static inline void hri_mclk_clear_APBBMASK_NVMCTRL_bit(const void *const hw)
2055{
2056 MCLK_CRITICAL_SECTION_ENTER();
2057 ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_NVMCTRL;
2058 MCLK_CRITICAL_SECTION_LEAVE();
2059}
2060
2061static inline void hri_mclk_toggle_APBBMASK_NVMCTRL_bit(const void *const hw)
2062{
2063 MCLK_CRITICAL_SECTION_ENTER();
2064 ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_NVMCTRL;
2065 MCLK_CRITICAL_SECTION_LEAVE();
2066}
2067
2068static inline void hri_mclk_set_APBBMASK_PORT_bit(const void *const hw)
2069{
2070 MCLK_CRITICAL_SECTION_ENTER();
2071 ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_PORT;
2072 MCLK_CRITICAL_SECTION_LEAVE();
2073}
2074
2075static inline bool hri_mclk_get_APBBMASK_PORT_bit(const void *const hw)
2076{
2077 uint32_t tmp;
2078 tmp = ((Mclk *)hw)->APBBMASK.reg;
2079 tmp = (tmp & MCLK_APBBMASK_PORT) >> MCLK_APBBMASK_PORT_Pos;
2080 return (bool)tmp;
2081}
2082
2083static inline void hri_mclk_write_APBBMASK_PORT_bit(const void *const hw, bool value)
2084{
2085 uint32_t tmp;
2086 MCLK_CRITICAL_SECTION_ENTER();
2087 tmp = ((Mclk *)hw)->APBBMASK.reg;
2088 tmp &= ~MCLK_APBBMASK_PORT;
2089 tmp |= value << MCLK_APBBMASK_PORT_Pos;
2090 ((Mclk *)hw)->APBBMASK.reg = tmp;
2091 MCLK_CRITICAL_SECTION_LEAVE();
2092}
2093
2094static inline void hri_mclk_clear_APBBMASK_PORT_bit(const void *const hw)
2095{
2096 MCLK_CRITICAL_SECTION_ENTER();
2097 ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_PORT;
2098 MCLK_CRITICAL_SECTION_LEAVE();
2099}
2100
2101static inline void hri_mclk_toggle_APBBMASK_PORT_bit(const void *const hw)
2102{
2103 MCLK_CRITICAL_SECTION_ENTER();
2104 ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_PORT;
2105 MCLK_CRITICAL_SECTION_LEAVE();
2106}
2107
2108static inline void hri_mclk_set_APBBMASK_HMATRIX_bit(const void *const hw)
2109{
2110 MCLK_CRITICAL_SECTION_ENTER();
2111 ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_HMATRIX;
2112 MCLK_CRITICAL_SECTION_LEAVE();
2113}
2114
2115static inline bool hri_mclk_get_APBBMASK_HMATRIX_bit(const void *const hw)
2116{
2117 uint32_t tmp;
2118 tmp = ((Mclk *)hw)->APBBMASK.reg;
2119 tmp = (tmp & MCLK_APBBMASK_HMATRIX) >> MCLK_APBBMASK_HMATRIX_Pos;
2120 return (bool)tmp;
2121}
2122
2123static inline void hri_mclk_write_APBBMASK_HMATRIX_bit(const void *const hw, bool value)
2124{
2125 uint32_t tmp;
2126 MCLK_CRITICAL_SECTION_ENTER();
2127 tmp = ((Mclk *)hw)->APBBMASK.reg;
2128 tmp &= ~MCLK_APBBMASK_HMATRIX;
2129 tmp |= value << MCLK_APBBMASK_HMATRIX_Pos;
2130 ((Mclk *)hw)->APBBMASK.reg = tmp;
2131 MCLK_CRITICAL_SECTION_LEAVE();
2132}
2133
2134static inline void hri_mclk_clear_APBBMASK_HMATRIX_bit(const void *const hw)
2135{
2136 MCLK_CRITICAL_SECTION_ENTER();
2137 ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_HMATRIX;
2138 MCLK_CRITICAL_SECTION_LEAVE();
2139}
2140
2141static inline void hri_mclk_toggle_APBBMASK_HMATRIX_bit(const void *const hw)
2142{
2143 MCLK_CRITICAL_SECTION_ENTER();
2144 ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_HMATRIX;
2145 MCLK_CRITICAL_SECTION_LEAVE();
2146}
2147
2148static inline void hri_mclk_set_APBBMASK_EVSYS_bit(const void *const hw)
2149{
2150 MCLK_CRITICAL_SECTION_ENTER();
2151 ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_EVSYS;
2152 MCLK_CRITICAL_SECTION_LEAVE();
2153}
2154
2155static inline bool hri_mclk_get_APBBMASK_EVSYS_bit(const void *const hw)
2156{
2157 uint32_t tmp;
2158 tmp = ((Mclk *)hw)->APBBMASK.reg;
2159 tmp = (tmp & MCLK_APBBMASK_EVSYS) >> MCLK_APBBMASK_EVSYS_Pos;
2160 return (bool)tmp;
2161}
2162
2163static inline void hri_mclk_write_APBBMASK_EVSYS_bit(const void *const hw, bool value)
2164{
2165 uint32_t tmp;
2166 MCLK_CRITICAL_SECTION_ENTER();
2167 tmp = ((Mclk *)hw)->APBBMASK.reg;
2168 tmp &= ~MCLK_APBBMASK_EVSYS;
2169 tmp |= value << MCLK_APBBMASK_EVSYS_Pos;
2170 ((Mclk *)hw)->APBBMASK.reg = tmp;
2171 MCLK_CRITICAL_SECTION_LEAVE();
2172}
2173
2174static inline void hri_mclk_clear_APBBMASK_EVSYS_bit(const void *const hw)
2175{
2176 MCLK_CRITICAL_SECTION_ENTER();
2177 ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_EVSYS;
2178 MCLK_CRITICAL_SECTION_LEAVE();
2179}
2180
2181static inline void hri_mclk_toggle_APBBMASK_EVSYS_bit(const void *const hw)
2182{
2183 MCLK_CRITICAL_SECTION_ENTER();
2184 ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_EVSYS;
2185 MCLK_CRITICAL_SECTION_LEAVE();
2186}
2187
2188static inline void hri_mclk_set_APBBMASK_SERCOM2_bit(const void *const hw)
2189{
2190 MCLK_CRITICAL_SECTION_ENTER();
2191 ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2;
2192 MCLK_CRITICAL_SECTION_LEAVE();
2193}
2194
2195static inline bool hri_mclk_get_APBBMASK_SERCOM2_bit(const void *const hw)
2196{
2197 uint32_t tmp;
2198 tmp = ((Mclk *)hw)->APBBMASK.reg;
2199 tmp = (tmp & MCLK_APBBMASK_SERCOM2) >> MCLK_APBBMASK_SERCOM2_Pos;
2200 return (bool)tmp;
2201}
2202
2203static inline void hri_mclk_write_APBBMASK_SERCOM2_bit(const void *const hw, bool value)
2204{
2205 uint32_t tmp;
2206 MCLK_CRITICAL_SECTION_ENTER();
2207 tmp = ((Mclk *)hw)->APBBMASK.reg;
2208 tmp &= ~MCLK_APBBMASK_SERCOM2;
2209 tmp |= value << MCLK_APBBMASK_SERCOM2_Pos;
2210 ((Mclk *)hw)->APBBMASK.reg = tmp;
2211 MCLK_CRITICAL_SECTION_LEAVE();
2212}
2213
2214static inline void hri_mclk_clear_APBBMASK_SERCOM2_bit(const void *const hw)
2215{
2216 MCLK_CRITICAL_SECTION_ENTER();
2217 ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_SERCOM2;
2218 MCLK_CRITICAL_SECTION_LEAVE();
2219}
2220
2221static inline void hri_mclk_toggle_APBBMASK_SERCOM2_bit(const void *const hw)
2222{
2223 MCLK_CRITICAL_SECTION_ENTER();
2224 ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_SERCOM2;
2225 MCLK_CRITICAL_SECTION_LEAVE();
2226}
2227
2228static inline void hri_mclk_set_APBBMASK_SERCOM3_bit(const void *const hw)
2229{
2230 MCLK_CRITICAL_SECTION_ENTER();
2231 ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM3;
2232 MCLK_CRITICAL_SECTION_LEAVE();
2233}
2234
2235static inline bool hri_mclk_get_APBBMASK_SERCOM3_bit(const void *const hw)
2236{
2237 uint32_t tmp;
2238 tmp = ((Mclk *)hw)->APBBMASK.reg;
2239 tmp = (tmp & MCLK_APBBMASK_SERCOM3) >> MCLK_APBBMASK_SERCOM3_Pos;
2240 return (bool)tmp;
2241}
2242
2243static inline void hri_mclk_write_APBBMASK_SERCOM3_bit(const void *const hw, bool value)
2244{
2245 uint32_t tmp;
2246 MCLK_CRITICAL_SECTION_ENTER();
2247 tmp = ((Mclk *)hw)->APBBMASK.reg;
2248 tmp &= ~MCLK_APBBMASK_SERCOM3;
2249 tmp |= value << MCLK_APBBMASK_SERCOM3_Pos;
2250 ((Mclk *)hw)->APBBMASK.reg = tmp;
2251 MCLK_CRITICAL_SECTION_LEAVE();
2252}
2253
2254static inline void hri_mclk_clear_APBBMASK_SERCOM3_bit(const void *const hw)
2255{
2256 MCLK_CRITICAL_SECTION_ENTER();
2257 ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_SERCOM3;
2258 MCLK_CRITICAL_SECTION_LEAVE();
2259}
2260
2261static inline void hri_mclk_toggle_APBBMASK_SERCOM3_bit(const void *const hw)
2262{
2263 MCLK_CRITICAL_SECTION_ENTER();
2264 ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_SERCOM3;
2265 MCLK_CRITICAL_SECTION_LEAVE();
2266}
2267
2268static inline void hri_mclk_set_APBBMASK_TCC0_bit(const void *const hw)
2269{
2270 MCLK_CRITICAL_SECTION_ENTER();
2271 ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TCC0;
2272 MCLK_CRITICAL_SECTION_LEAVE();
2273}
2274
2275static inline bool hri_mclk_get_APBBMASK_TCC0_bit(const void *const hw)
2276{
2277 uint32_t tmp;
2278 tmp = ((Mclk *)hw)->APBBMASK.reg;
2279 tmp = (tmp & MCLK_APBBMASK_TCC0) >> MCLK_APBBMASK_TCC0_Pos;
2280 return (bool)tmp;
2281}
2282
2283static inline void hri_mclk_write_APBBMASK_TCC0_bit(const void *const hw, bool value)
2284{
2285 uint32_t tmp;
2286 MCLK_CRITICAL_SECTION_ENTER();
2287 tmp = ((Mclk *)hw)->APBBMASK.reg;
2288 tmp &= ~MCLK_APBBMASK_TCC0;
2289 tmp |= value << MCLK_APBBMASK_TCC0_Pos;
2290 ((Mclk *)hw)->APBBMASK.reg = tmp;
2291 MCLK_CRITICAL_SECTION_LEAVE();
2292}
2293
2294static inline void hri_mclk_clear_APBBMASK_TCC0_bit(const void *const hw)
2295{
2296 MCLK_CRITICAL_SECTION_ENTER();
2297 ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TCC0;
2298 MCLK_CRITICAL_SECTION_LEAVE();
2299}
2300
2301static inline void hri_mclk_toggle_APBBMASK_TCC0_bit(const void *const hw)
2302{
2303 MCLK_CRITICAL_SECTION_ENTER();
2304 ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TCC0;
2305 MCLK_CRITICAL_SECTION_LEAVE();
2306}
2307
2308static inline void hri_mclk_set_APBBMASK_TCC1_bit(const void *const hw)
2309{
2310 MCLK_CRITICAL_SECTION_ENTER();
2311 ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TCC1;
2312 MCLK_CRITICAL_SECTION_LEAVE();
2313}
2314
2315static inline bool hri_mclk_get_APBBMASK_TCC1_bit(const void *const hw)
2316{
2317 uint32_t tmp;
2318 tmp = ((Mclk *)hw)->APBBMASK.reg;
2319 tmp = (tmp & MCLK_APBBMASK_TCC1) >> MCLK_APBBMASK_TCC1_Pos;
2320 return (bool)tmp;
2321}
2322
2323static inline void hri_mclk_write_APBBMASK_TCC1_bit(const void *const hw, bool value)
2324{
2325 uint32_t tmp;
2326 MCLK_CRITICAL_SECTION_ENTER();
2327 tmp = ((Mclk *)hw)->APBBMASK.reg;
2328 tmp &= ~MCLK_APBBMASK_TCC1;
2329 tmp |= value << MCLK_APBBMASK_TCC1_Pos;
2330 ((Mclk *)hw)->APBBMASK.reg = tmp;
2331 MCLK_CRITICAL_SECTION_LEAVE();
2332}
2333
2334static inline void hri_mclk_clear_APBBMASK_TCC1_bit(const void *const hw)
2335{
2336 MCLK_CRITICAL_SECTION_ENTER();
2337 ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TCC1;
2338 MCLK_CRITICAL_SECTION_LEAVE();
2339}
2340
2341static inline void hri_mclk_toggle_APBBMASK_TCC1_bit(const void *const hw)
2342{
2343 MCLK_CRITICAL_SECTION_ENTER();
2344 ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TCC1;
2345 MCLK_CRITICAL_SECTION_LEAVE();
2346}
2347
2348static inline void hri_mclk_set_APBBMASK_TC2_bit(const void *const hw)
2349{
2350 MCLK_CRITICAL_SECTION_ENTER();
2351 ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TC2;
2352 MCLK_CRITICAL_SECTION_LEAVE();
2353}
2354
2355static inline bool hri_mclk_get_APBBMASK_TC2_bit(const void *const hw)
2356{
2357 uint32_t tmp;
2358 tmp = ((Mclk *)hw)->APBBMASK.reg;
2359 tmp = (tmp & MCLK_APBBMASK_TC2) >> MCLK_APBBMASK_TC2_Pos;
2360 return (bool)tmp;
2361}
2362
2363static inline void hri_mclk_write_APBBMASK_TC2_bit(const void *const hw, bool value)
2364{
2365 uint32_t tmp;
2366 MCLK_CRITICAL_SECTION_ENTER();
2367 tmp = ((Mclk *)hw)->APBBMASK.reg;
2368 tmp &= ~MCLK_APBBMASK_TC2;
2369 tmp |= value << MCLK_APBBMASK_TC2_Pos;
2370 ((Mclk *)hw)->APBBMASK.reg = tmp;
2371 MCLK_CRITICAL_SECTION_LEAVE();
2372}
2373
2374static inline void hri_mclk_clear_APBBMASK_TC2_bit(const void *const hw)
2375{
2376 MCLK_CRITICAL_SECTION_ENTER();
2377 ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TC2;
2378 MCLK_CRITICAL_SECTION_LEAVE();
2379}
2380
2381static inline void hri_mclk_toggle_APBBMASK_TC2_bit(const void *const hw)
2382{
2383 MCLK_CRITICAL_SECTION_ENTER();
2384 ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TC2;
2385 MCLK_CRITICAL_SECTION_LEAVE();
2386}
2387
2388static inline void hri_mclk_set_APBBMASK_TC3_bit(const void *const hw)
2389{
2390 MCLK_CRITICAL_SECTION_ENTER();
2391 ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TC3;
2392 MCLK_CRITICAL_SECTION_LEAVE();
2393}
2394
2395static inline bool hri_mclk_get_APBBMASK_TC3_bit(const void *const hw)
2396{
2397 uint32_t tmp;
2398 tmp = ((Mclk *)hw)->APBBMASK.reg;
2399 tmp = (tmp & MCLK_APBBMASK_TC3) >> MCLK_APBBMASK_TC3_Pos;
2400 return (bool)tmp;
2401}
2402
2403static inline void hri_mclk_write_APBBMASK_TC3_bit(const void *const hw, bool value)
2404{
2405 uint32_t tmp;
2406 MCLK_CRITICAL_SECTION_ENTER();
2407 tmp = ((Mclk *)hw)->APBBMASK.reg;
2408 tmp &= ~MCLK_APBBMASK_TC3;
2409 tmp |= value << MCLK_APBBMASK_TC3_Pos;
2410 ((Mclk *)hw)->APBBMASK.reg = tmp;
2411 MCLK_CRITICAL_SECTION_LEAVE();
2412}
2413
2414static inline void hri_mclk_clear_APBBMASK_TC3_bit(const void *const hw)
2415{
2416 MCLK_CRITICAL_SECTION_ENTER();
2417 ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TC3;
2418 MCLK_CRITICAL_SECTION_LEAVE();
2419}
2420
2421static inline void hri_mclk_toggle_APBBMASK_TC3_bit(const void *const hw)
2422{
2423 MCLK_CRITICAL_SECTION_ENTER();
2424 ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TC3;
2425 MCLK_CRITICAL_SECTION_LEAVE();
2426}
2427
2428static inline void hri_mclk_set_APBBMASK_RAMECC_bit(const void *const hw)
2429{
2430 MCLK_CRITICAL_SECTION_ENTER();
2431 ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_RAMECC;
2432 MCLK_CRITICAL_SECTION_LEAVE();
2433}
2434
2435static inline bool hri_mclk_get_APBBMASK_RAMECC_bit(const void *const hw)
2436{
2437 uint32_t tmp;
2438 tmp = ((Mclk *)hw)->APBBMASK.reg;
2439 tmp = (tmp & MCLK_APBBMASK_RAMECC) >> MCLK_APBBMASK_RAMECC_Pos;
2440 return (bool)tmp;
2441}
2442
2443static inline void hri_mclk_write_APBBMASK_RAMECC_bit(const void *const hw, bool value)
2444{
2445 uint32_t tmp;
2446 MCLK_CRITICAL_SECTION_ENTER();
2447 tmp = ((Mclk *)hw)->APBBMASK.reg;
2448 tmp &= ~MCLK_APBBMASK_RAMECC;
2449 tmp |= value << MCLK_APBBMASK_RAMECC_Pos;
2450 ((Mclk *)hw)->APBBMASK.reg = tmp;
2451 MCLK_CRITICAL_SECTION_LEAVE();
2452}
2453
2454static inline void hri_mclk_clear_APBBMASK_RAMECC_bit(const void *const hw)
2455{
2456 MCLK_CRITICAL_SECTION_ENTER();
2457 ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_RAMECC;
2458 MCLK_CRITICAL_SECTION_LEAVE();
2459}
2460
2461static inline void hri_mclk_toggle_APBBMASK_RAMECC_bit(const void *const hw)
2462{
2463 MCLK_CRITICAL_SECTION_ENTER();
2464 ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_RAMECC;
2465 MCLK_CRITICAL_SECTION_LEAVE();
2466}
2467
2468static inline void hri_mclk_set_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask)
2469{
2470 MCLK_CRITICAL_SECTION_ENTER();
2471 ((Mclk *)hw)->APBBMASK.reg |= mask;
2472 MCLK_CRITICAL_SECTION_LEAVE();
2473}
2474
2475static inline hri_mclk_apbbmask_reg_t hri_mclk_get_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask)
2476{
2477 uint32_t tmp;
2478 tmp = ((Mclk *)hw)->APBBMASK.reg;
2479 tmp &= mask;
2480 return tmp;
2481}
2482
2483static inline void hri_mclk_write_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t data)
2484{
2485 MCLK_CRITICAL_SECTION_ENTER();
2486 ((Mclk *)hw)->APBBMASK.reg = data;
2487 MCLK_CRITICAL_SECTION_LEAVE();
2488}
2489
2490static inline void hri_mclk_clear_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask)
2491{
2492 MCLK_CRITICAL_SECTION_ENTER();
2493 ((Mclk *)hw)->APBBMASK.reg &= ~mask;
2494 MCLK_CRITICAL_SECTION_LEAVE();
2495}
2496
2497static inline void hri_mclk_toggle_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask)
2498{
2499 MCLK_CRITICAL_SECTION_ENTER();
2500 ((Mclk *)hw)->APBBMASK.reg ^= mask;
2501 MCLK_CRITICAL_SECTION_LEAVE();
2502}
2503
2504static inline hri_mclk_apbbmask_reg_t hri_mclk_read_APBBMASK_reg(const void *const hw)
2505{
2506 return ((Mclk *)hw)->APBBMASK.reg;
2507}
2508
2509static inline void hri_mclk_set_APBCMASK_GMAC_bit(const void *const hw)
2510{
2511 MCLK_CRITICAL_SECTION_ENTER();
2512 ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_GMAC;
2513 MCLK_CRITICAL_SECTION_LEAVE();
2514}
2515
2516static inline bool hri_mclk_get_APBCMASK_GMAC_bit(const void *const hw)
2517{
2518 uint32_t tmp;
2519 tmp = ((Mclk *)hw)->APBCMASK.reg;
2520 tmp = (tmp & MCLK_APBCMASK_GMAC) >> MCLK_APBCMASK_GMAC_Pos;
2521 return (bool)tmp;
2522}
2523
2524static inline void hri_mclk_write_APBCMASK_GMAC_bit(const void *const hw, bool value)
2525{
2526 uint32_t tmp;
2527 MCLK_CRITICAL_SECTION_ENTER();
2528 tmp = ((Mclk *)hw)->APBCMASK.reg;
2529 tmp &= ~MCLK_APBCMASK_GMAC;
2530 tmp |= value << MCLK_APBCMASK_GMAC_Pos;
2531 ((Mclk *)hw)->APBCMASK.reg = tmp;
2532 MCLK_CRITICAL_SECTION_LEAVE();
2533}
2534
2535static inline void hri_mclk_clear_APBCMASK_GMAC_bit(const void *const hw)
2536{
2537 MCLK_CRITICAL_SECTION_ENTER();
2538 ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_GMAC;
2539 MCLK_CRITICAL_SECTION_LEAVE();
2540}
2541
2542static inline void hri_mclk_toggle_APBCMASK_GMAC_bit(const void *const hw)
2543{
2544 MCLK_CRITICAL_SECTION_ENTER();
2545 ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_GMAC;
2546 MCLK_CRITICAL_SECTION_LEAVE();
2547}
2548
2549static inline void hri_mclk_set_APBCMASK_TCC2_bit(const void *const hw)
2550{
2551 MCLK_CRITICAL_SECTION_ENTER();
2552 ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC2;
2553 MCLK_CRITICAL_SECTION_LEAVE();
2554}
2555
2556static inline bool hri_mclk_get_APBCMASK_TCC2_bit(const void *const hw)
2557{
2558 uint32_t tmp;
2559 tmp = ((Mclk *)hw)->APBCMASK.reg;
2560 tmp = (tmp & MCLK_APBCMASK_TCC2) >> MCLK_APBCMASK_TCC2_Pos;
2561 return (bool)tmp;
2562}
2563
2564static inline void hri_mclk_write_APBCMASK_TCC2_bit(const void *const hw, bool value)
2565{
2566 uint32_t tmp;
2567 MCLK_CRITICAL_SECTION_ENTER();
2568 tmp = ((Mclk *)hw)->APBCMASK.reg;
2569 tmp &= ~MCLK_APBCMASK_TCC2;
2570 tmp |= value << MCLK_APBCMASK_TCC2_Pos;
2571 ((Mclk *)hw)->APBCMASK.reg = tmp;
2572 MCLK_CRITICAL_SECTION_LEAVE();
2573}
2574
2575static inline void hri_mclk_clear_APBCMASK_TCC2_bit(const void *const hw)
2576{
2577 MCLK_CRITICAL_SECTION_ENTER();
2578 ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC2;
2579 MCLK_CRITICAL_SECTION_LEAVE();
2580}
2581
2582static inline void hri_mclk_toggle_APBCMASK_TCC2_bit(const void *const hw)
2583{
2584 MCLK_CRITICAL_SECTION_ENTER();
2585 ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC2;
2586 MCLK_CRITICAL_SECTION_LEAVE();
2587}
2588
2589static inline void hri_mclk_set_APBCMASK_TCC3_bit(const void *const hw)
2590{
2591 MCLK_CRITICAL_SECTION_ENTER();
2592 ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC3;
2593 MCLK_CRITICAL_SECTION_LEAVE();
2594}
2595
2596static inline bool hri_mclk_get_APBCMASK_TCC3_bit(const void *const hw)
2597{
2598 uint32_t tmp;
2599 tmp = ((Mclk *)hw)->APBCMASK.reg;
2600 tmp = (tmp & MCLK_APBCMASK_TCC3) >> MCLK_APBCMASK_TCC3_Pos;
2601 return (bool)tmp;
2602}
2603
2604static inline void hri_mclk_write_APBCMASK_TCC3_bit(const void *const hw, bool value)
2605{
2606 uint32_t tmp;
2607 MCLK_CRITICAL_SECTION_ENTER();
2608 tmp = ((Mclk *)hw)->APBCMASK.reg;
2609 tmp &= ~MCLK_APBCMASK_TCC3;
2610 tmp |= value << MCLK_APBCMASK_TCC3_Pos;
2611 ((Mclk *)hw)->APBCMASK.reg = tmp;
2612 MCLK_CRITICAL_SECTION_LEAVE();
2613}
2614
2615static inline void hri_mclk_clear_APBCMASK_TCC3_bit(const void *const hw)
2616{
2617 MCLK_CRITICAL_SECTION_ENTER();
2618 ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC3;
2619 MCLK_CRITICAL_SECTION_LEAVE();
2620}
2621
2622static inline void hri_mclk_toggle_APBCMASK_TCC3_bit(const void *const hw)
2623{
2624 MCLK_CRITICAL_SECTION_ENTER();
2625 ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC3;
2626 MCLK_CRITICAL_SECTION_LEAVE();
2627}
2628
2629static inline void hri_mclk_set_APBCMASK_TC4_bit(const void *const hw)
2630{
2631 MCLK_CRITICAL_SECTION_ENTER();
2632 ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC4;
2633 MCLK_CRITICAL_SECTION_LEAVE();
2634}
2635
2636static inline bool hri_mclk_get_APBCMASK_TC4_bit(const void *const hw)
2637{
2638 uint32_t tmp;
2639 tmp = ((Mclk *)hw)->APBCMASK.reg;
2640 tmp = (tmp & MCLK_APBCMASK_TC4) >> MCLK_APBCMASK_TC4_Pos;
2641 return (bool)tmp;
2642}
2643
2644static inline void hri_mclk_write_APBCMASK_TC4_bit(const void *const hw, bool value)
2645{
2646 uint32_t tmp;
2647 MCLK_CRITICAL_SECTION_ENTER();
2648 tmp = ((Mclk *)hw)->APBCMASK.reg;
2649 tmp &= ~MCLK_APBCMASK_TC4;
2650 tmp |= value << MCLK_APBCMASK_TC4_Pos;
2651 ((Mclk *)hw)->APBCMASK.reg = tmp;
2652 MCLK_CRITICAL_SECTION_LEAVE();
2653}
2654
2655static inline void hri_mclk_clear_APBCMASK_TC4_bit(const void *const hw)
2656{
2657 MCLK_CRITICAL_SECTION_ENTER();
2658 ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC4;
2659 MCLK_CRITICAL_SECTION_LEAVE();
2660}
2661
2662static inline void hri_mclk_toggle_APBCMASK_TC4_bit(const void *const hw)
2663{
2664 MCLK_CRITICAL_SECTION_ENTER();
2665 ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC4;
2666 MCLK_CRITICAL_SECTION_LEAVE();
2667}
2668
2669static inline void hri_mclk_set_APBCMASK_TC5_bit(const void *const hw)
2670{
2671 MCLK_CRITICAL_SECTION_ENTER();
2672 ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC5;
2673 MCLK_CRITICAL_SECTION_LEAVE();
2674}
2675
2676static inline bool hri_mclk_get_APBCMASK_TC5_bit(const void *const hw)
2677{
2678 uint32_t tmp;
2679 tmp = ((Mclk *)hw)->APBCMASK.reg;
2680 tmp = (tmp & MCLK_APBCMASK_TC5) >> MCLK_APBCMASK_TC5_Pos;
2681 return (bool)tmp;
2682}
2683
2684static inline void hri_mclk_write_APBCMASK_TC5_bit(const void *const hw, bool value)
2685{
2686 uint32_t tmp;
2687 MCLK_CRITICAL_SECTION_ENTER();
2688 tmp = ((Mclk *)hw)->APBCMASK.reg;
2689 tmp &= ~MCLK_APBCMASK_TC5;
2690 tmp |= value << MCLK_APBCMASK_TC5_Pos;
2691 ((Mclk *)hw)->APBCMASK.reg = tmp;
2692 MCLK_CRITICAL_SECTION_LEAVE();
2693}
2694
2695static inline void hri_mclk_clear_APBCMASK_TC5_bit(const void *const hw)
2696{
2697 MCLK_CRITICAL_SECTION_ENTER();
2698 ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC5;
2699 MCLK_CRITICAL_SECTION_LEAVE();
2700}
2701
2702static inline void hri_mclk_toggle_APBCMASK_TC5_bit(const void *const hw)
2703{
2704 MCLK_CRITICAL_SECTION_ENTER();
2705 ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC5;
2706 MCLK_CRITICAL_SECTION_LEAVE();
2707}
2708
2709static inline void hri_mclk_set_APBCMASK_PDEC_bit(const void *const hw)
2710{
2711 MCLK_CRITICAL_SECTION_ENTER();
2712 ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_PDEC;
2713 MCLK_CRITICAL_SECTION_LEAVE();
2714}
2715
2716static inline bool hri_mclk_get_APBCMASK_PDEC_bit(const void *const hw)
2717{
2718 uint32_t tmp;
2719 tmp = ((Mclk *)hw)->APBCMASK.reg;
2720 tmp = (tmp & MCLK_APBCMASK_PDEC) >> MCLK_APBCMASK_PDEC_Pos;
2721 return (bool)tmp;
2722}
2723
2724static inline void hri_mclk_write_APBCMASK_PDEC_bit(const void *const hw, bool value)
2725{
2726 uint32_t tmp;
2727 MCLK_CRITICAL_SECTION_ENTER();
2728 tmp = ((Mclk *)hw)->APBCMASK.reg;
2729 tmp &= ~MCLK_APBCMASK_PDEC;
2730 tmp |= value << MCLK_APBCMASK_PDEC_Pos;
2731 ((Mclk *)hw)->APBCMASK.reg = tmp;
2732 MCLK_CRITICAL_SECTION_LEAVE();
2733}
2734
2735static inline void hri_mclk_clear_APBCMASK_PDEC_bit(const void *const hw)
2736{
2737 MCLK_CRITICAL_SECTION_ENTER();
2738 ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_PDEC;
2739 MCLK_CRITICAL_SECTION_LEAVE();
2740}
2741
2742static inline void hri_mclk_toggle_APBCMASK_PDEC_bit(const void *const hw)
2743{
2744 MCLK_CRITICAL_SECTION_ENTER();
2745 ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_PDEC;
2746 MCLK_CRITICAL_SECTION_LEAVE();
2747}
2748
2749static inline void hri_mclk_set_APBCMASK_AC_bit(const void *const hw)
2750{
2751 MCLK_CRITICAL_SECTION_ENTER();
2752 ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AC;
2753 MCLK_CRITICAL_SECTION_LEAVE();
2754}
2755
2756static inline bool hri_mclk_get_APBCMASK_AC_bit(const void *const hw)
2757{
2758 uint32_t tmp;
2759 tmp = ((Mclk *)hw)->APBCMASK.reg;
2760 tmp = (tmp & MCLK_APBCMASK_AC) >> MCLK_APBCMASK_AC_Pos;
2761 return (bool)tmp;
2762}
2763
2764static inline void hri_mclk_write_APBCMASK_AC_bit(const void *const hw, bool value)
2765{
2766 uint32_t tmp;
2767 MCLK_CRITICAL_SECTION_ENTER();
2768 tmp = ((Mclk *)hw)->APBCMASK.reg;
2769 tmp &= ~MCLK_APBCMASK_AC;
2770 tmp |= value << MCLK_APBCMASK_AC_Pos;
2771 ((Mclk *)hw)->APBCMASK.reg = tmp;
2772 MCLK_CRITICAL_SECTION_LEAVE();
2773}
2774
2775static inline void hri_mclk_clear_APBCMASK_AC_bit(const void *const hw)
2776{
2777 MCLK_CRITICAL_SECTION_ENTER();
2778 ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AC;
2779 MCLK_CRITICAL_SECTION_LEAVE();
2780}
2781
2782static inline void hri_mclk_toggle_APBCMASK_AC_bit(const void *const hw)
2783{
2784 MCLK_CRITICAL_SECTION_ENTER();
2785 ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AC;
2786 MCLK_CRITICAL_SECTION_LEAVE();
2787}
2788
2789static inline void hri_mclk_set_APBCMASK_AES_bit(const void *const hw)
2790{
2791 MCLK_CRITICAL_SECTION_ENTER();
2792 ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AES;
2793 MCLK_CRITICAL_SECTION_LEAVE();
2794}
2795
2796static inline bool hri_mclk_get_APBCMASK_AES_bit(const void *const hw)
2797{
2798 uint32_t tmp;
2799 tmp = ((Mclk *)hw)->APBCMASK.reg;
2800 tmp = (tmp & MCLK_APBCMASK_AES) >> MCLK_APBCMASK_AES_Pos;
2801 return (bool)tmp;
2802}
2803
2804static inline void hri_mclk_write_APBCMASK_AES_bit(const void *const hw, bool value)
2805{
2806 uint32_t tmp;
2807 MCLK_CRITICAL_SECTION_ENTER();
2808 tmp = ((Mclk *)hw)->APBCMASK.reg;
2809 tmp &= ~MCLK_APBCMASK_AES;
2810 tmp |= value << MCLK_APBCMASK_AES_Pos;
2811 ((Mclk *)hw)->APBCMASK.reg = tmp;
2812 MCLK_CRITICAL_SECTION_LEAVE();
2813}
2814
2815static inline void hri_mclk_clear_APBCMASK_AES_bit(const void *const hw)
2816{
2817 MCLK_CRITICAL_SECTION_ENTER();
2818 ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AES;
2819 MCLK_CRITICAL_SECTION_LEAVE();
2820}
2821
2822static inline void hri_mclk_toggle_APBCMASK_AES_bit(const void *const hw)
2823{
2824 MCLK_CRITICAL_SECTION_ENTER();
2825 ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AES;
2826 MCLK_CRITICAL_SECTION_LEAVE();
2827}
2828
2829static inline void hri_mclk_set_APBCMASK_TRNG_bit(const void *const hw)
2830{
2831 MCLK_CRITICAL_SECTION_ENTER();
2832 ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TRNG;
2833 MCLK_CRITICAL_SECTION_LEAVE();
2834}
2835
2836static inline bool hri_mclk_get_APBCMASK_TRNG_bit(const void *const hw)
2837{
2838 uint32_t tmp;
2839 tmp = ((Mclk *)hw)->APBCMASK.reg;
2840 tmp = (tmp & MCLK_APBCMASK_TRNG) >> MCLK_APBCMASK_TRNG_Pos;
2841 return (bool)tmp;
2842}
2843
2844static inline void hri_mclk_write_APBCMASK_TRNG_bit(const void *const hw, bool value)
2845{
2846 uint32_t tmp;
2847 MCLK_CRITICAL_SECTION_ENTER();
2848 tmp = ((Mclk *)hw)->APBCMASK.reg;
2849 tmp &= ~MCLK_APBCMASK_TRNG;
2850 tmp |= value << MCLK_APBCMASK_TRNG_Pos;
2851 ((Mclk *)hw)->APBCMASK.reg = tmp;
2852 MCLK_CRITICAL_SECTION_LEAVE();
2853}
2854
2855static inline void hri_mclk_clear_APBCMASK_TRNG_bit(const void *const hw)
2856{
2857 MCLK_CRITICAL_SECTION_ENTER();
2858 ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TRNG;
2859 MCLK_CRITICAL_SECTION_LEAVE();
2860}
2861
2862static inline void hri_mclk_toggle_APBCMASK_TRNG_bit(const void *const hw)
2863{
2864 MCLK_CRITICAL_SECTION_ENTER();
2865 ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TRNG;
2866 MCLK_CRITICAL_SECTION_LEAVE();
2867}
2868
2869static inline void hri_mclk_set_APBCMASK_ICM_bit(const void *const hw)
2870{
2871 MCLK_CRITICAL_SECTION_ENTER();
2872 ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_ICM;
2873 MCLK_CRITICAL_SECTION_LEAVE();
2874}
2875
2876static inline bool hri_mclk_get_APBCMASK_ICM_bit(const void *const hw)
2877{
2878 uint32_t tmp;
2879 tmp = ((Mclk *)hw)->APBCMASK.reg;
2880 tmp = (tmp & MCLK_APBCMASK_ICM) >> MCLK_APBCMASK_ICM_Pos;
2881 return (bool)tmp;
2882}
2883
2884static inline void hri_mclk_write_APBCMASK_ICM_bit(const void *const hw, bool value)
2885{
2886 uint32_t tmp;
2887 MCLK_CRITICAL_SECTION_ENTER();
2888 tmp = ((Mclk *)hw)->APBCMASK.reg;
2889 tmp &= ~MCLK_APBCMASK_ICM;
2890 tmp |= value << MCLK_APBCMASK_ICM_Pos;
2891 ((Mclk *)hw)->APBCMASK.reg = tmp;
2892 MCLK_CRITICAL_SECTION_LEAVE();
2893}
2894
2895static inline void hri_mclk_clear_APBCMASK_ICM_bit(const void *const hw)
2896{
2897 MCLK_CRITICAL_SECTION_ENTER();
2898 ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_ICM;
2899 MCLK_CRITICAL_SECTION_LEAVE();
2900}
2901
2902static inline void hri_mclk_toggle_APBCMASK_ICM_bit(const void *const hw)
2903{
2904 MCLK_CRITICAL_SECTION_ENTER();
2905 ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_ICM;
2906 MCLK_CRITICAL_SECTION_LEAVE();
2907}
2908
2909static inline void hri_mclk_set_APBCMASK_QSPI_bit(const void *const hw)
2910{
2911 MCLK_CRITICAL_SECTION_ENTER();
2912 ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_QSPI;
2913 MCLK_CRITICAL_SECTION_LEAVE();
2914}
2915
2916static inline bool hri_mclk_get_APBCMASK_QSPI_bit(const void *const hw)
2917{
2918 uint32_t tmp;
2919 tmp = ((Mclk *)hw)->APBCMASK.reg;
2920 tmp = (tmp & MCLK_APBCMASK_QSPI) >> MCLK_APBCMASK_QSPI_Pos;
2921 return (bool)tmp;
2922}
2923
2924static inline void hri_mclk_write_APBCMASK_QSPI_bit(const void *const hw, bool value)
2925{
2926 uint32_t tmp;
2927 MCLK_CRITICAL_SECTION_ENTER();
2928 tmp = ((Mclk *)hw)->APBCMASK.reg;
2929 tmp &= ~MCLK_APBCMASK_QSPI;
2930 tmp |= value << MCLK_APBCMASK_QSPI_Pos;
2931 ((Mclk *)hw)->APBCMASK.reg = tmp;
2932 MCLK_CRITICAL_SECTION_LEAVE();
2933}
2934
2935static inline void hri_mclk_clear_APBCMASK_QSPI_bit(const void *const hw)
2936{
2937 MCLK_CRITICAL_SECTION_ENTER();
2938 ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_QSPI;
2939 MCLK_CRITICAL_SECTION_LEAVE();
2940}
2941
2942static inline void hri_mclk_toggle_APBCMASK_QSPI_bit(const void *const hw)
2943{
2944 MCLK_CRITICAL_SECTION_ENTER();
2945 ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_QSPI;
2946 MCLK_CRITICAL_SECTION_LEAVE();
2947}
2948
2949static inline void hri_mclk_set_APBCMASK_CCL_bit(const void *const hw)
2950{
2951 MCLK_CRITICAL_SECTION_ENTER();
2952 ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_CCL;
2953 MCLK_CRITICAL_SECTION_LEAVE();
2954}
2955
2956static inline bool hri_mclk_get_APBCMASK_CCL_bit(const void *const hw)
2957{
2958 uint32_t tmp;
2959 tmp = ((Mclk *)hw)->APBCMASK.reg;
2960 tmp = (tmp & MCLK_APBCMASK_CCL) >> MCLK_APBCMASK_CCL_Pos;
2961 return (bool)tmp;
2962}
2963
2964static inline void hri_mclk_write_APBCMASK_CCL_bit(const void *const hw, bool value)
2965{
2966 uint32_t tmp;
2967 MCLK_CRITICAL_SECTION_ENTER();
2968 tmp = ((Mclk *)hw)->APBCMASK.reg;
2969 tmp &= ~MCLK_APBCMASK_CCL;
2970 tmp |= value << MCLK_APBCMASK_CCL_Pos;
2971 ((Mclk *)hw)->APBCMASK.reg = tmp;
2972 MCLK_CRITICAL_SECTION_LEAVE();
2973}
2974
2975static inline void hri_mclk_clear_APBCMASK_CCL_bit(const void *const hw)
2976{
2977 MCLK_CRITICAL_SECTION_ENTER();
2978 ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_CCL;
2979 MCLK_CRITICAL_SECTION_LEAVE();
2980}
2981
2982static inline void hri_mclk_toggle_APBCMASK_CCL_bit(const void *const hw)
2983{
2984 MCLK_CRITICAL_SECTION_ENTER();
2985 ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_CCL;
2986 MCLK_CRITICAL_SECTION_LEAVE();
2987}
2988
2989static inline void hri_mclk_set_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask)
2990{
2991 MCLK_CRITICAL_SECTION_ENTER();
2992 ((Mclk *)hw)->APBCMASK.reg |= mask;
2993 MCLK_CRITICAL_SECTION_LEAVE();
2994}
2995
2996static inline hri_mclk_apbcmask_reg_t hri_mclk_get_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask)
2997{
2998 uint32_t tmp;
2999 tmp = ((Mclk *)hw)->APBCMASK.reg;
3000 tmp &= mask;
3001 return tmp;
3002}
3003
3004static inline void hri_mclk_write_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t data)
3005{
3006 MCLK_CRITICAL_SECTION_ENTER();
3007 ((Mclk *)hw)->APBCMASK.reg = data;
3008 MCLK_CRITICAL_SECTION_LEAVE();
3009}
3010
3011static inline void hri_mclk_clear_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask)
3012{
3013 MCLK_CRITICAL_SECTION_ENTER();
3014 ((Mclk *)hw)->APBCMASK.reg &= ~mask;
3015 MCLK_CRITICAL_SECTION_LEAVE();
3016}
3017
3018static inline void hri_mclk_toggle_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask)
3019{
3020 MCLK_CRITICAL_SECTION_ENTER();
3021 ((Mclk *)hw)->APBCMASK.reg ^= mask;
3022 MCLK_CRITICAL_SECTION_LEAVE();
3023}
3024
3025static inline hri_mclk_apbcmask_reg_t hri_mclk_read_APBCMASK_reg(const void *const hw)
3026{
3027 return ((Mclk *)hw)->APBCMASK.reg;
3028}
3029
3030static inline void hri_mclk_set_APBDMASK_SERCOM4_bit(const void *const hw)
3031{
3032 MCLK_CRITICAL_SECTION_ENTER();
3033 ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM4;
3034 MCLK_CRITICAL_SECTION_LEAVE();
3035}
3036
3037static inline bool hri_mclk_get_APBDMASK_SERCOM4_bit(const void *const hw)
3038{
3039 uint32_t tmp;
3040 tmp = ((Mclk *)hw)->APBDMASK.reg;
3041 tmp = (tmp & MCLK_APBDMASK_SERCOM4) >> MCLK_APBDMASK_SERCOM4_Pos;
3042 return (bool)tmp;
3043}
3044
3045static inline void hri_mclk_write_APBDMASK_SERCOM4_bit(const void *const hw, bool value)
3046{
3047 uint32_t tmp;
3048 MCLK_CRITICAL_SECTION_ENTER();
3049 tmp = ((Mclk *)hw)->APBDMASK.reg;
3050 tmp &= ~MCLK_APBDMASK_SERCOM4;
3051 tmp |= value << MCLK_APBDMASK_SERCOM4_Pos;
3052 ((Mclk *)hw)->APBDMASK.reg = tmp;
3053 MCLK_CRITICAL_SECTION_LEAVE();
3054}
3055
3056static inline void hri_mclk_clear_APBDMASK_SERCOM4_bit(const void *const hw)
3057{
3058 MCLK_CRITICAL_SECTION_ENTER();
3059 ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM4;
3060 MCLK_CRITICAL_SECTION_LEAVE();
3061}
3062
3063static inline void hri_mclk_toggle_APBDMASK_SERCOM4_bit(const void *const hw)
3064{
3065 MCLK_CRITICAL_SECTION_ENTER();
3066 ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM4;
3067 MCLK_CRITICAL_SECTION_LEAVE();
3068}
3069
3070static inline void hri_mclk_set_APBDMASK_SERCOM5_bit(const void *const hw)
3071{
3072 MCLK_CRITICAL_SECTION_ENTER();
3073 ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM5;
3074 MCLK_CRITICAL_SECTION_LEAVE();
3075}
3076
3077static inline bool hri_mclk_get_APBDMASK_SERCOM5_bit(const void *const hw)
3078{
3079 uint32_t tmp;
3080 tmp = ((Mclk *)hw)->APBDMASK.reg;
3081 tmp = (tmp & MCLK_APBDMASK_SERCOM5) >> MCLK_APBDMASK_SERCOM5_Pos;
3082 return (bool)tmp;
3083}
3084
3085static inline void hri_mclk_write_APBDMASK_SERCOM5_bit(const void *const hw, bool value)
3086{
3087 uint32_t tmp;
3088 MCLK_CRITICAL_SECTION_ENTER();
3089 tmp = ((Mclk *)hw)->APBDMASK.reg;
3090 tmp &= ~MCLK_APBDMASK_SERCOM5;
3091 tmp |= value << MCLK_APBDMASK_SERCOM5_Pos;
3092 ((Mclk *)hw)->APBDMASK.reg = tmp;
3093 MCLK_CRITICAL_SECTION_LEAVE();
3094}
3095
3096static inline void hri_mclk_clear_APBDMASK_SERCOM5_bit(const void *const hw)
3097{
3098 MCLK_CRITICAL_SECTION_ENTER();
3099 ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM5;
3100 MCLK_CRITICAL_SECTION_LEAVE();
3101}
3102
3103static inline void hri_mclk_toggle_APBDMASK_SERCOM5_bit(const void *const hw)
3104{
3105 MCLK_CRITICAL_SECTION_ENTER();
3106 ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM5;
3107 MCLK_CRITICAL_SECTION_LEAVE();
3108}
3109
3110static inline void hri_mclk_set_APBDMASK_SERCOM6_bit(const void *const hw)
3111{
3112 MCLK_CRITICAL_SECTION_ENTER();
3113 ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM6;
3114 MCLK_CRITICAL_SECTION_LEAVE();
3115}
3116
3117static inline bool hri_mclk_get_APBDMASK_SERCOM6_bit(const void *const hw)
3118{
3119 uint32_t tmp;
3120 tmp = ((Mclk *)hw)->APBDMASK.reg;
3121 tmp = (tmp & MCLK_APBDMASK_SERCOM6) >> MCLK_APBDMASK_SERCOM6_Pos;
3122 return (bool)tmp;
3123}
3124
3125static inline void hri_mclk_write_APBDMASK_SERCOM6_bit(const void *const hw, bool value)
3126{
3127 uint32_t tmp;
3128 MCLK_CRITICAL_SECTION_ENTER();
3129 tmp = ((Mclk *)hw)->APBDMASK.reg;
3130 tmp &= ~MCLK_APBDMASK_SERCOM6;
3131 tmp |= value << MCLK_APBDMASK_SERCOM6_Pos;
3132 ((Mclk *)hw)->APBDMASK.reg = tmp;
3133 MCLK_CRITICAL_SECTION_LEAVE();
3134}
3135
3136static inline void hri_mclk_clear_APBDMASK_SERCOM6_bit(const void *const hw)
3137{
3138 MCLK_CRITICAL_SECTION_ENTER();
3139 ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM6;
3140 MCLK_CRITICAL_SECTION_LEAVE();
3141}
3142
3143static inline void hri_mclk_toggle_APBDMASK_SERCOM6_bit(const void *const hw)
3144{
3145 MCLK_CRITICAL_SECTION_ENTER();
3146 ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM6;
3147 MCLK_CRITICAL_SECTION_LEAVE();
3148}
3149
3150static inline void hri_mclk_set_APBDMASK_SERCOM7_bit(const void *const hw)
3151{
3152 MCLK_CRITICAL_SECTION_ENTER();
3153 ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM7;
3154 MCLK_CRITICAL_SECTION_LEAVE();
3155}
3156
3157static inline bool hri_mclk_get_APBDMASK_SERCOM7_bit(const void *const hw)
3158{
3159 uint32_t tmp;
3160 tmp = ((Mclk *)hw)->APBDMASK.reg;
3161 tmp = (tmp & MCLK_APBDMASK_SERCOM7) >> MCLK_APBDMASK_SERCOM7_Pos;
3162 return (bool)tmp;
3163}
3164
3165static inline void hri_mclk_write_APBDMASK_SERCOM7_bit(const void *const hw, bool value)
3166{
3167 uint32_t tmp;
3168 MCLK_CRITICAL_SECTION_ENTER();
3169 tmp = ((Mclk *)hw)->APBDMASK.reg;
3170 tmp &= ~MCLK_APBDMASK_SERCOM7;
3171 tmp |= value << MCLK_APBDMASK_SERCOM7_Pos;
3172 ((Mclk *)hw)->APBDMASK.reg = tmp;
3173 MCLK_CRITICAL_SECTION_LEAVE();
3174}
3175
3176static inline void hri_mclk_clear_APBDMASK_SERCOM7_bit(const void *const hw)
3177{
3178 MCLK_CRITICAL_SECTION_ENTER();
3179 ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM7;
3180 MCLK_CRITICAL_SECTION_LEAVE();
3181}
3182
3183static inline void hri_mclk_toggle_APBDMASK_SERCOM7_bit(const void *const hw)
3184{
3185 MCLK_CRITICAL_SECTION_ENTER();
3186 ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM7;
3187 MCLK_CRITICAL_SECTION_LEAVE();
3188}
3189
3190static inline void hri_mclk_set_APBDMASK_TCC4_bit(const void *const hw)
3191{
3192 MCLK_CRITICAL_SECTION_ENTER();
3193 ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TCC4;
3194 MCLK_CRITICAL_SECTION_LEAVE();
3195}
3196
3197static inline bool hri_mclk_get_APBDMASK_TCC4_bit(const void *const hw)
3198{
3199 uint32_t tmp;
3200 tmp = ((Mclk *)hw)->APBDMASK.reg;
3201 tmp = (tmp & MCLK_APBDMASK_TCC4) >> MCLK_APBDMASK_TCC4_Pos;
3202 return (bool)tmp;
3203}
3204
3205static inline void hri_mclk_write_APBDMASK_TCC4_bit(const void *const hw, bool value)
3206{
3207 uint32_t tmp;
3208 MCLK_CRITICAL_SECTION_ENTER();
3209 tmp = ((Mclk *)hw)->APBDMASK.reg;
3210 tmp &= ~MCLK_APBDMASK_TCC4;
3211 tmp |= value << MCLK_APBDMASK_TCC4_Pos;
3212 ((Mclk *)hw)->APBDMASK.reg = tmp;
3213 MCLK_CRITICAL_SECTION_LEAVE();
3214}
3215
3216static inline void hri_mclk_clear_APBDMASK_TCC4_bit(const void *const hw)
3217{
3218 MCLK_CRITICAL_SECTION_ENTER();
3219 ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TCC4;
3220 MCLK_CRITICAL_SECTION_LEAVE();
3221}
3222
3223static inline void hri_mclk_toggle_APBDMASK_TCC4_bit(const void *const hw)
3224{
3225 MCLK_CRITICAL_SECTION_ENTER();
3226 ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TCC4;
3227 MCLK_CRITICAL_SECTION_LEAVE();
3228}
3229
3230static inline void hri_mclk_set_APBDMASK_TC6_bit(const void *const hw)
3231{
3232 MCLK_CRITICAL_SECTION_ENTER();
3233 ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TC6;
3234 MCLK_CRITICAL_SECTION_LEAVE();
3235}
3236
3237static inline bool hri_mclk_get_APBDMASK_TC6_bit(const void *const hw)
3238{
3239 uint32_t tmp;
3240 tmp = ((Mclk *)hw)->APBDMASK.reg;
3241 tmp = (tmp & MCLK_APBDMASK_TC6) >> MCLK_APBDMASK_TC6_Pos;
3242 return (bool)tmp;
3243}
3244
3245static inline void hri_mclk_write_APBDMASK_TC6_bit(const void *const hw, bool value)
3246{
3247 uint32_t tmp;
3248 MCLK_CRITICAL_SECTION_ENTER();
3249 tmp = ((Mclk *)hw)->APBDMASK.reg;
3250 tmp &= ~MCLK_APBDMASK_TC6;
3251 tmp |= value << MCLK_APBDMASK_TC6_Pos;
3252 ((Mclk *)hw)->APBDMASK.reg = tmp;
3253 MCLK_CRITICAL_SECTION_LEAVE();
3254}
3255
3256static inline void hri_mclk_clear_APBDMASK_TC6_bit(const void *const hw)
3257{
3258 MCLK_CRITICAL_SECTION_ENTER();
3259 ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TC6;
3260 MCLK_CRITICAL_SECTION_LEAVE();
3261}
3262
3263static inline void hri_mclk_toggle_APBDMASK_TC6_bit(const void *const hw)
3264{
3265 MCLK_CRITICAL_SECTION_ENTER();
3266 ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TC6;
3267 MCLK_CRITICAL_SECTION_LEAVE();
3268}
3269
3270static inline void hri_mclk_set_APBDMASK_TC7_bit(const void *const hw)
3271{
3272 MCLK_CRITICAL_SECTION_ENTER();
3273 ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TC7;
3274 MCLK_CRITICAL_SECTION_LEAVE();
3275}
3276
3277static inline bool hri_mclk_get_APBDMASK_TC7_bit(const void *const hw)
3278{
3279 uint32_t tmp;
3280 tmp = ((Mclk *)hw)->APBDMASK.reg;
3281 tmp = (tmp & MCLK_APBDMASK_TC7) >> MCLK_APBDMASK_TC7_Pos;
3282 return (bool)tmp;
3283}
3284
3285static inline void hri_mclk_write_APBDMASK_TC7_bit(const void *const hw, bool value)
3286{
3287 uint32_t tmp;
3288 MCLK_CRITICAL_SECTION_ENTER();
3289 tmp = ((Mclk *)hw)->APBDMASK.reg;
3290 tmp &= ~MCLK_APBDMASK_TC7;
3291 tmp |= value << MCLK_APBDMASK_TC7_Pos;
3292 ((Mclk *)hw)->APBDMASK.reg = tmp;
3293 MCLK_CRITICAL_SECTION_LEAVE();
3294}
3295
3296static inline void hri_mclk_clear_APBDMASK_TC7_bit(const void *const hw)
3297{
3298 MCLK_CRITICAL_SECTION_ENTER();
3299 ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TC7;
3300 MCLK_CRITICAL_SECTION_LEAVE();
3301}
3302
3303static inline void hri_mclk_toggle_APBDMASK_TC7_bit(const void *const hw)
3304{
3305 MCLK_CRITICAL_SECTION_ENTER();
3306 ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TC7;
3307 MCLK_CRITICAL_SECTION_LEAVE();
3308}
3309
3310static inline void hri_mclk_set_APBDMASK_ADC0_bit(const void *const hw)
3311{
3312 MCLK_CRITICAL_SECTION_ENTER();
3313 ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC0;
3314 MCLK_CRITICAL_SECTION_LEAVE();
3315}
3316
3317static inline bool hri_mclk_get_APBDMASK_ADC0_bit(const void *const hw)
3318{
3319 uint32_t tmp;
3320 tmp = ((Mclk *)hw)->APBDMASK.reg;
3321 tmp = (tmp & MCLK_APBDMASK_ADC0) >> MCLK_APBDMASK_ADC0_Pos;
3322 return (bool)tmp;
3323}
3324
3325static inline void hri_mclk_write_APBDMASK_ADC0_bit(const void *const hw, bool value)
3326{
3327 uint32_t tmp;
3328 MCLK_CRITICAL_SECTION_ENTER();
3329 tmp = ((Mclk *)hw)->APBDMASK.reg;
3330 tmp &= ~MCLK_APBDMASK_ADC0;
3331 tmp |= value << MCLK_APBDMASK_ADC0_Pos;
3332 ((Mclk *)hw)->APBDMASK.reg = tmp;
3333 MCLK_CRITICAL_SECTION_LEAVE();
3334}
3335
3336static inline void hri_mclk_clear_APBDMASK_ADC0_bit(const void *const hw)
3337{
3338 MCLK_CRITICAL_SECTION_ENTER();
3339 ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_ADC0;
3340 MCLK_CRITICAL_SECTION_LEAVE();
3341}
3342
3343static inline void hri_mclk_toggle_APBDMASK_ADC0_bit(const void *const hw)
3344{
3345 MCLK_CRITICAL_SECTION_ENTER();
3346 ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_ADC0;
3347 MCLK_CRITICAL_SECTION_LEAVE();
3348}
3349
3350static inline void hri_mclk_set_APBDMASK_ADC1_bit(const void *const hw)
3351{
3352 MCLK_CRITICAL_SECTION_ENTER();
3353 ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC1;
3354 MCLK_CRITICAL_SECTION_LEAVE();
3355}
3356
3357static inline bool hri_mclk_get_APBDMASK_ADC1_bit(const void *const hw)
3358{
3359 uint32_t tmp;
3360 tmp = ((Mclk *)hw)->APBDMASK.reg;
3361 tmp = (tmp & MCLK_APBDMASK_ADC1) >> MCLK_APBDMASK_ADC1_Pos;
3362 return (bool)tmp;
3363}
3364
3365static inline void hri_mclk_write_APBDMASK_ADC1_bit(const void *const hw, bool value)
3366{
3367 uint32_t tmp;
3368 MCLK_CRITICAL_SECTION_ENTER();
3369 tmp = ((Mclk *)hw)->APBDMASK.reg;
3370 tmp &= ~MCLK_APBDMASK_ADC1;
3371 tmp |= value << MCLK_APBDMASK_ADC1_Pos;
3372 ((Mclk *)hw)->APBDMASK.reg = tmp;
3373 MCLK_CRITICAL_SECTION_LEAVE();
3374}
3375
3376static inline void hri_mclk_clear_APBDMASK_ADC1_bit(const void *const hw)
3377{
3378 MCLK_CRITICAL_SECTION_ENTER();
3379 ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_ADC1;
3380 MCLK_CRITICAL_SECTION_LEAVE();
3381}
3382
3383static inline void hri_mclk_toggle_APBDMASK_ADC1_bit(const void *const hw)
3384{
3385 MCLK_CRITICAL_SECTION_ENTER();
3386 ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_ADC1;
3387 MCLK_CRITICAL_SECTION_LEAVE();
3388}
3389
3390static inline void hri_mclk_set_APBDMASK_DAC_bit(const void *const hw)
3391{
3392 MCLK_CRITICAL_SECTION_ENTER();
3393 ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_DAC;
3394 MCLK_CRITICAL_SECTION_LEAVE();
3395}
3396
3397static inline bool hri_mclk_get_APBDMASK_DAC_bit(const void *const hw)
3398{
3399 uint32_t tmp;
3400 tmp = ((Mclk *)hw)->APBDMASK.reg;
3401 tmp = (tmp & MCLK_APBDMASK_DAC) >> MCLK_APBDMASK_DAC_Pos;
3402 return (bool)tmp;
3403}
3404
3405static inline void hri_mclk_write_APBDMASK_DAC_bit(const void *const hw, bool value)
3406{
3407 uint32_t tmp;
3408 MCLK_CRITICAL_SECTION_ENTER();
3409 tmp = ((Mclk *)hw)->APBDMASK.reg;
3410 tmp &= ~MCLK_APBDMASK_DAC;
3411 tmp |= value << MCLK_APBDMASK_DAC_Pos;
3412 ((Mclk *)hw)->APBDMASK.reg = tmp;
3413 MCLK_CRITICAL_SECTION_LEAVE();
3414}
3415
3416static inline void hri_mclk_clear_APBDMASK_DAC_bit(const void *const hw)
3417{
3418 MCLK_CRITICAL_SECTION_ENTER();
3419 ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_DAC;
3420 MCLK_CRITICAL_SECTION_LEAVE();
3421}
3422
3423static inline void hri_mclk_toggle_APBDMASK_DAC_bit(const void *const hw)
3424{
3425 MCLK_CRITICAL_SECTION_ENTER();
3426 ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_DAC;
3427 MCLK_CRITICAL_SECTION_LEAVE();
3428}
3429
3430static inline void hri_mclk_set_APBDMASK_I2S_bit(const void *const hw)
3431{
3432 MCLK_CRITICAL_SECTION_ENTER();
3433 ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_I2S;
3434 MCLK_CRITICAL_SECTION_LEAVE();
3435}
3436
3437static inline bool hri_mclk_get_APBDMASK_I2S_bit(const void *const hw)
3438{
3439 uint32_t tmp;
3440 tmp = ((Mclk *)hw)->APBDMASK.reg;
3441 tmp = (tmp & MCLK_APBDMASK_I2S) >> MCLK_APBDMASK_I2S_Pos;
3442 return (bool)tmp;
3443}
3444
3445static inline void hri_mclk_write_APBDMASK_I2S_bit(const void *const hw, bool value)
3446{
3447 uint32_t tmp;
3448 MCLK_CRITICAL_SECTION_ENTER();
3449 tmp = ((Mclk *)hw)->APBDMASK.reg;
3450 tmp &= ~MCLK_APBDMASK_I2S;
3451 tmp |= value << MCLK_APBDMASK_I2S_Pos;
3452 ((Mclk *)hw)->APBDMASK.reg = tmp;
3453 MCLK_CRITICAL_SECTION_LEAVE();
3454}
3455
3456static inline void hri_mclk_clear_APBDMASK_I2S_bit(const void *const hw)
3457{
3458 MCLK_CRITICAL_SECTION_ENTER();
3459 ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_I2S;
3460 MCLK_CRITICAL_SECTION_LEAVE();
3461}
3462
3463static inline void hri_mclk_toggle_APBDMASK_I2S_bit(const void *const hw)
3464{
3465 MCLK_CRITICAL_SECTION_ENTER();
3466 ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_I2S;
3467 MCLK_CRITICAL_SECTION_LEAVE();
3468}
3469
3470static inline void hri_mclk_set_APBDMASK_PCC_bit(const void *const hw)
3471{
3472 MCLK_CRITICAL_SECTION_ENTER();
3473 ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_PCC;
3474 MCLK_CRITICAL_SECTION_LEAVE();
3475}
3476
3477static inline bool hri_mclk_get_APBDMASK_PCC_bit(const void *const hw)
3478{
3479 uint32_t tmp;
3480 tmp = ((Mclk *)hw)->APBDMASK.reg;
3481 tmp = (tmp & MCLK_APBDMASK_PCC) >> MCLK_APBDMASK_PCC_Pos;
3482 return (bool)tmp;
3483}
3484
3485static inline void hri_mclk_write_APBDMASK_PCC_bit(const void *const hw, bool value)
3486{
3487 uint32_t tmp;
3488 MCLK_CRITICAL_SECTION_ENTER();
3489 tmp = ((Mclk *)hw)->APBDMASK.reg;
3490 tmp &= ~MCLK_APBDMASK_PCC;
3491 tmp |= value << MCLK_APBDMASK_PCC_Pos;
3492 ((Mclk *)hw)->APBDMASK.reg = tmp;
3493 MCLK_CRITICAL_SECTION_LEAVE();
3494}
3495
3496static inline void hri_mclk_clear_APBDMASK_PCC_bit(const void *const hw)
3497{
3498 MCLK_CRITICAL_SECTION_ENTER();
3499 ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_PCC;
3500 MCLK_CRITICAL_SECTION_LEAVE();
3501}
3502
3503static inline void hri_mclk_toggle_APBDMASK_PCC_bit(const void *const hw)
3504{
3505 MCLK_CRITICAL_SECTION_ENTER();
3506 ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_PCC;
3507 MCLK_CRITICAL_SECTION_LEAVE();
3508}
3509
3510static inline void hri_mclk_set_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask)
3511{
3512 MCLK_CRITICAL_SECTION_ENTER();
3513 ((Mclk *)hw)->APBDMASK.reg |= mask;
3514 MCLK_CRITICAL_SECTION_LEAVE();
3515}
3516
3517static inline hri_mclk_apbdmask_reg_t hri_mclk_get_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask)
3518{
3519 uint32_t tmp;
3520 tmp = ((Mclk *)hw)->APBDMASK.reg;
3521 tmp &= mask;
3522 return tmp;
3523}
3524
3525static inline void hri_mclk_write_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t data)
3526{
3527 MCLK_CRITICAL_SECTION_ENTER();
3528 ((Mclk *)hw)->APBDMASK.reg = data;
3529 MCLK_CRITICAL_SECTION_LEAVE();
3530}
3531
3532static inline void hri_mclk_clear_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask)
3533{
3534 MCLK_CRITICAL_SECTION_ENTER();
3535 ((Mclk *)hw)->APBDMASK.reg &= ~mask;
3536 MCLK_CRITICAL_SECTION_LEAVE();
3537}
3538
3539static inline void hri_mclk_toggle_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask)
3540{
3541 MCLK_CRITICAL_SECTION_ENTER();
3542 ((Mclk *)hw)->APBDMASK.reg ^= mask;
3543 MCLK_CRITICAL_SECTION_LEAVE();
3544}
3545
3546static inline hri_mclk_apbdmask_reg_t hri_mclk_read_APBDMASK_reg(const void *const hw)
3547{
3548 return ((Mclk *)hw)->APBDMASK.reg;
3549}
3550
3551#ifdef __cplusplus
3552}
3553#endif
3554
3555#endif /* _HRI_MCLK_E54_H_INCLUDED */
3556#endif /* _SAME54_MCLK_COMPONENT_ */