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gerrit.osmocom.org / osmo-ccid-firmware / 727d67536ded3c2ea27b3dd00013f893336739db / . / sysmoOCTSIM / hri / hri_i2s_e54.h
blob: 42b88dc095bbe87f1f7d09906e019f09e3ad5eac [file] [log] [blame]
Kévin Redon69b92d92019-01-24 16:39:20 +0100[diff] [blame]1/**
2 * \file
3 *
4 * \brief SAM I2S
5 *
6 * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Subject to your compliance with these terms, you may use Microchip
13 * software and any derivatives exclusively with Microchip products.
14 * It is your responsibility to comply with third party license terms applicable
15 * to your use of third party software (including open source software) that
16 * may accompany Microchip software.
17 *
18 * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
19 * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
20 * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
21 * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
22 * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
23 * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
24 * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
25 * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
26 * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
27 * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
28 * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
29 *
30 * \asf_license_stop
31 *
32 */
33
34#ifdef _SAME54_I2S_COMPONENT_
35#ifndef _HRI_I2S_E54_H_INCLUDED_
36#define _HRI_I2S_E54_H_INCLUDED_
37
38#ifdef __cplusplus
39extern "C" {
40#endif
41
42#include <stdbool.h>
43#include <hal_atomic.h>
44
45#if defined(ENABLE_I2S_CRITICAL_SECTIONS)
46#define I2S_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
47#define I2S_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
48#else
49#define I2S_CRITICAL_SECTION_ENTER()
50#define I2S_CRITICAL_SECTION_LEAVE()
51#endif
52
53typedef uint16_t hri_i2s_intenset_reg_t;
54typedef uint16_t hri_i2s_intflag_reg_t;
55typedef uint16_t hri_i2s_syncbusy_reg_t;
56typedef uint32_t hri_i2s_clkctrl_reg_t;
57typedef uint32_t hri_i2s_rxctrl_reg_t;
58typedef uint32_t hri_i2s_rxdata_reg_t;
59typedef uint32_t hri_i2s_txctrl_reg_t;
60typedef uint32_t hri_i2s_txdata_reg_t;
61typedef uint8_t hri_i2s_ctrla_reg_t;
62
63static inline void hri_i2s_wait_for_sync(const void *const hw, hri_i2s_syncbusy_reg_t reg)
64{
65 while (((I2s *)hw)->SYNCBUSY.reg & reg) {
66 };
67}
68
69static inline bool hri_i2s_is_syncing(const void *const hw, hri_i2s_syncbusy_reg_t reg)
70{
71 return ((I2s *)hw)->SYNCBUSY.reg & reg;
72}
73
74static inline bool hri_i2s_get_INTFLAG_RXRDY0_bit(const void *const hw)
75{
76 return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos;
77}
78
79static inline void hri_i2s_clear_INTFLAG_RXRDY0_bit(const void *const hw)
80{
81 ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0;
82}
83
84static inline bool hri_i2s_get_INTFLAG_RXRDY1_bit(const void *const hw)
85{
86 return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos;
87}
88
89static inline void hri_i2s_clear_INTFLAG_RXRDY1_bit(const void *const hw)
90{
91 ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1;
92}
93
94static inline bool hri_i2s_get_INTFLAG_RXOR0_bit(const void *const hw)
95{
96 return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos;
97}
98
99static inline void hri_i2s_clear_INTFLAG_RXOR0_bit(const void *const hw)
100{
101 ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0;
102}
103
104static inline bool hri_i2s_get_INTFLAG_RXOR1_bit(const void *const hw)
105{
106 return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos;
107}
108
109static inline void hri_i2s_clear_INTFLAG_RXOR1_bit(const void *const hw)
110{
111 ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1;
112}
113
114static inline bool hri_i2s_get_INTFLAG_TXRDY0_bit(const void *const hw)
115{
116 return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos;
117}
118
119static inline void hri_i2s_clear_INTFLAG_TXRDY0_bit(const void *const hw)
120{
121 ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0;
122}
123
124static inline bool hri_i2s_get_INTFLAG_TXRDY1_bit(const void *const hw)
125{
126 return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos;
127}
128
129static inline void hri_i2s_clear_INTFLAG_TXRDY1_bit(const void *const hw)
130{
131 ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1;
132}
133
134static inline bool hri_i2s_get_INTFLAG_TXUR0_bit(const void *const hw)
135{
136 return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos;
137}
138
139static inline void hri_i2s_clear_INTFLAG_TXUR0_bit(const void *const hw)
140{
141 ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0;
142}
143
144static inline bool hri_i2s_get_INTFLAG_TXUR1_bit(const void *const hw)
145{
146 return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos;
147}
148
149static inline void hri_i2s_clear_INTFLAG_TXUR1_bit(const void *const hw)
150{
151 ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1;
152}
153
154static inline bool hri_i2s_get_interrupt_RXRDY0_bit(const void *const hw)
155{
156 return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos;
157}
158
159static inline void hri_i2s_clear_interrupt_RXRDY0_bit(const void *const hw)
160{
161 ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0;
162}
163
164static inline bool hri_i2s_get_interrupt_RXRDY1_bit(const void *const hw)
165{
166 return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos;
167}
168
169static inline void hri_i2s_clear_interrupt_RXRDY1_bit(const void *const hw)
170{
171 ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1;
172}
173
174static inline bool hri_i2s_get_interrupt_RXOR0_bit(const void *const hw)
175{
176 return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos;
177}
178
179static inline void hri_i2s_clear_interrupt_RXOR0_bit(const void *const hw)
180{
181 ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0;
182}
183
184static inline bool hri_i2s_get_interrupt_RXOR1_bit(const void *const hw)
185{
186 return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos;
187}
188
189static inline void hri_i2s_clear_interrupt_RXOR1_bit(const void *const hw)
190{
191 ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1;
192}
193
194static inline bool hri_i2s_get_interrupt_TXRDY0_bit(const void *const hw)
195{
196 return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos;
197}
198
199static inline void hri_i2s_clear_interrupt_TXRDY0_bit(const void *const hw)
200{
201 ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0;
202}
203
204static inline bool hri_i2s_get_interrupt_TXRDY1_bit(const void *const hw)
205{
206 return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos;
207}
208
209static inline void hri_i2s_clear_interrupt_TXRDY1_bit(const void *const hw)
210{
211 ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1;
212}
213
214static inline bool hri_i2s_get_interrupt_TXUR0_bit(const void *const hw)
215{
216 return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos;
217}
218
219static inline void hri_i2s_clear_interrupt_TXUR0_bit(const void *const hw)
220{
221 ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0;
222}
223
224static inline bool hri_i2s_get_interrupt_TXUR1_bit(const void *const hw)
225{
226 return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos;
227}
228
229static inline void hri_i2s_clear_interrupt_TXUR1_bit(const void *const hw)
230{
231 ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1;
232}
233
234static inline hri_i2s_intflag_reg_t hri_i2s_get_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask)
235{
236 uint16_t tmp;
237 tmp = ((I2s *)hw)->INTFLAG.reg;
238 tmp &= mask;
239 return tmp;
240}
241
242static inline hri_i2s_intflag_reg_t hri_i2s_read_INTFLAG_reg(const void *const hw)
243{
244 return ((I2s *)hw)->INTFLAG.reg;
245}
246
247static inline void hri_i2s_clear_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask)
248{
249 ((I2s *)hw)->INTFLAG.reg = mask;
250}
251
252static inline void hri_i2s_set_INTEN_RXRDY0_bit(const void *const hw)
253{
254 ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0;
255}
256
257static inline bool hri_i2s_get_INTEN_RXRDY0_bit(const void *const hw)
258{
259 return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY0) >> I2S_INTENSET_RXRDY0_Pos;
260}
261
262static inline void hri_i2s_write_INTEN_RXRDY0_bit(const void *const hw, bool value)
263{
264 if (value == 0x0) {
265 ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0;
266 } else {
267 ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0;
268 }
269}
270
271static inline void hri_i2s_clear_INTEN_RXRDY0_bit(const void *const hw)
272{
273 ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0;
274}
275
276static inline void hri_i2s_set_INTEN_RXRDY1_bit(const void *const hw)
277{
278 ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1;
279}
280
281static inline bool hri_i2s_get_INTEN_RXRDY1_bit(const void *const hw)
282{
283 return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY1) >> I2S_INTENSET_RXRDY1_Pos;
284}
285
286static inline void hri_i2s_write_INTEN_RXRDY1_bit(const void *const hw, bool value)
287{
288 if (value == 0x0) {
289 ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1;
290 } else {
291 ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1;
292 }
293}
294
295static inline void hri_i2s_clear_INTEN_RXRDY1_bit(const void *const hw)
296{
297 ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1;
298}
299
300static inline void hri_i2s_set_INTEN_RXOR0_bit(const void *const hw)
301{
302 ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0;
303}
304
305static inline bool hri_i2s_get_INTEN_RXOR0_bit(const void *const hw)
306{
307 return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR0) >> I2S_INTENSET_RXOR0_Pos;
308}
309
310static inline void hri_i2s_write_INTEN_RXOR0_bit(const void *const hw, bool value)
311{
312 if (value == 0x0) {
313 ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0;
314 } else {
315 ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0;
316 }
317}
318
319static inline void hri_i2s_clear_INTEN_RXOR0_bit(const void *const hw)
320{
321 ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0;
322}
323
324static inline void hri_i2s_set_INTEN_RXOR1_bit(const void *const hw)
325{
326 ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1;
327}
328
329static inline bool hri_i2s_get_INTEN_RXOR1_bit(const void *const hw)
330{
331 return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR1) >> I2S_INTENSET_RXOR1_Pos;
332}
333
334static inline void hri_i2s_write_INTEN_RXOR1_bit(const void *const hw, bool value)
335{
336 if (value == 0x0) {
337 ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1;
338 } else {
339 ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1;
340 }
341}
342
343static inline void hri_i2s_clear_INTEN_RXOR1_bit(const void *const hw)
344{
345 ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1;
346}
347
348static inline void hri_i2s_set_INTEN_TXRDY0_bit(const void *const hw)
349{
350 ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0;
351}
352
353static inline bool hri_i2s_get_INTEN_TXRDY0_bit(const void *const hw)
354{
355 return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY0) >> I2S_INTENSET_TXRDY0_Pos;
356}
357
358static inline void hri_i2s_write_INTEN_TXRDY0_bit(const void *const hw, bool value)
359{
360 if (value == 0x0) {
361 ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0;
362 } else {
363 ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0;
364 }
365}
366
367static inline void hri_i2s_clear_INTEN_TXRDY0_bit(const void *const hw)
368{
369 ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0;
370}
371
372static inline void hri_i2s_set_INTEN_TXRDY1_bit(const void *const hw)
373{
374 ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1;
375}
376
377static inline bool hri_i2s_get_INTEN_TXRDY1_bit(const void *const hw)
378{
379 return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY1) >> I2S_INTENSET_TXRDY1_Pos;
380}
381
382static inline void hri_i2s_write_INTEN_TXRDY1_bit(const void *const hw, bool value)
383{
384 if (value == 0x0) {
385 ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1;
386 } else {
387 ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1;
388 }
389}
390
391static inline void hri_i2s_clear_INTEN_TXRDY1_bit(const void *const hw)
392{
393 ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1;
394}
395
396static inline void hri_i2s_set_INTEN_TXUR0_bit(const void *const hw)
397{
398 ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0;
399}
400
401static inline bool hri_i2s_get_INTEN_TXUR0_bit(const void *const hw)
402{
403 return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR0) >> I2S_INTENSET_TXUR0_Pos;
404}
405
406static inline void hri_i2s_write_INTEN_TXUR0_bit(const void *const hw, bool value)
407{
408 if (value == 0x0) {
409 ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0;
410 } else {
411 ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0;
412 }
413}
414
415static inline void hri_i2s_clear_INTEN_TXUR0_bit(const void *const hw)
416{
417 ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0;
418}
419
420static inline void hri_i2s_set_INTEN_TXUR1_bit(const void *const hw)
421{
422 ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1;
423}
424
425static inline bool hri_i2s_get_INTEN_TXUR1_bit(const void *const hw)
426{
427 return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR1) >> I2S_INTENSET_TXUR1_Pos;
428}
429
430static inline void hri_i2s_write_INTEN_TXUR1_bit(const void *const hw, bool value)
431{
432 if (value == 0x0) {
433 ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1;
434 } else {
435 ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1;
436 }
437}
438
439static inline void hri_i2s_clear_INTEN_TXUR1_bit(const void *const hw)
440{
441 ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1;
442}
443
444static inline void hri_i2s_set_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask)
445{
446 ((I2s *)hw)->INTENSET.reg = mask;
447}
448
449static inline hri_i2s_intenset_reg_t hri_i2s_get_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask)
450{
451 uint16_t tmp;
452 tmp = ((I2s *)hw)->INTENSET.reg;
453 tmp &= mask;
454 return tmp;
455}
456
457static inline hri_i2s_intenset_reg_t hri_i2s_read_INTEN_reg(const void *const hw)
458{
459 return ((I2s *)hw)->INTENSET.reg;
460}
461
462static inline void hri_i2s_write_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t data)
463{
464 ((I2s *)hw)->INTENSET.reg = data;
465 ((I2s *)hw)->INTENCLR.reg = ~data;
466}
467
468static inline void hri_i2s_clear_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask)
469{
470 ((I2s *)hw)->INTENCLR.reg = mask;
471}
472
473static inline bool hri_i2s_get_SYNCBUSY_SWRST_bit(const void *const hw)
474{
475 return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_SWRST) >> I2S_SYNCBUSY_SWRST_Pos;
476}
477
478static inline bool hri_i2s_get_SYNCBUSY_ENABLE_bit(const void *const hw)
479{
480 return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_ENABLE) >> I2S_SYNCBUSY_ENABLE_Pos;
481}
482
483static inline bool hri_i2s_get_SYNCBUSY_CKEN0_bit(const void *const hw)
484{
485 return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN0) >> I2S_SYNCBUSY_CKEN0_Pos;
486}
487
488static inline bool hri_i2s_get_SYNCBUSY_CKEN1_bit(const void *const hw)
489{
490 return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN1) >> I2S_SYNCBUSY_CKEN1_Pos;
491}
492
493static inline bool hri_i2s_get_SYNCBUSY_TXEN_bit(const void *const hw)
494{
495 return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_TXEN) >> I2S_SYNCBUSY_TXEN_Pos;
496}
497
498static inline bool hri_i2s_get_SYNCBUSY_RXEN_bit(const void *const hw)
499{
500 return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_RXEN) >> I2S_SYNCBUSY_RXEN_Pos;
501}
502
503static inline bool hri_i2s_get_SYNCBUSY_TXDATA_bit(const void *const hw)
504{
505 return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_TXDATA) >> I2S_SYNCBUSY_TXDATA_Pos;
506}
507
508static inline bool hri_i2s_get_SYNCBUSY_RXDATA_bit(const void *const hw)
509{
510 return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_RXDATA) >> I2S_SYNCBUSY_RXDATA_Pos;
511}
512
513static inline hri_i2s_syncbusy_reg_t hri_i2s_get_SYNCBUSY_reg(const void *const hw, hri_i2s_syncbusy_reg_t mask)
514{
515 uint16_t tmp;
516 tmp = ((I2s *)hw)->SYNCBUSY.reg;
517 tmp &= mask;
518 return tmp;
519}
520
521static inline hri_i2s_syncbusy_reg_t hri_i2s_read_SYNCBUSY_reg(const void *const hw)
522{
523 return ((I2s *)hw)->SYNCBUSY.reg;
524}
525
526static inline hri_i2s_rxdata_reg_t hri_i2s_get_RXDATA_DATA_bf(const void *const hw, hri_i2s_rxdata_reg_t mask)
527{
528 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
529 return (((I2s *)hw)->RXDATA.reg & I2S_RXDATA_DATA(mask)) >> I2S_RXDATA_DATA_Pos;
530}
531
532static inline hri_i2s_rxdata_reg_t hri_i2s_read_RXDATA_DATA_bf(const void *const hw)
533{
534 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
535 return (((I2s *)hw)->RXDATA.reg & I2S_RXDATA_DATA_Msk) >> I2S_RXDATA_DATA_Pos;
536}
537
538static inline hri_i2s_rxdata_reg_t hri_i2s_get_RXDATA_reg(const void *const hw, hri_i2s_rxdata_reg_t mask)
539{
540 uint32_t tmp;
541 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
542 tmp = ((I2s *)hw)->RXDATA.reg;
543 tmp &= mask;
544 return tmp;
545}
546
547static inline hri_i2s_rxdata_reg_t hri_i2s_read_RXDATA_reg(const void *const hw)
548{
549 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
550 return ((I2s *)hw)->RXDATA.reg;
551}
552
553static inline void hri_i2s_set_CTRLA_SWRST_bit(const void *const hw)
554{
555 I2S_CRITICAL_SECTION_ENTER();
556 ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_SWRST;
557 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST);
558 I2S_CRITICAL_SECTION_LEAVE();
559}
560
561static inline bool hri_i2s_get_CTRLA_SWRST_bit(const void *const hw)
562{
563 uint8_t tmp;
564 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST);
565 tmp = ((I2s *)hw)->CTRLA.reg;
566 tmp = (tmp & I2S_CTRLA_SWRST) >> I2S_CTRLA_SWRST_Pos;
567 return (bool)tmp;
568}
569
570static inline void hri_i2s_set_CTRLA_ENABLE_bit(const void *const hw)
571{
572 I2S_CRITICAL_SECTION_ENTER();
573 ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_ENABLE;
574 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
575 I2S_CRITICAL_SECTION_LEAVE();
576}
577
578static inline bool hri_i2s_get_CTRLA_ENABLE_bit(const void *const hw)
579{
580 uint8_t tmp;
581 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
582 tmp = ((I2s *)hw)->CTRLA.reg;
583 tmp = (tmp & I2S_CTRLA_ENABLE) >> I2S_CTRLA_ENABLE_Pos;
584 return (bool)tmp;
585}
586
587static inline void hri_i2s_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
588{
589 uint8_t tmp;
590 I2S_CRITICAL_SECTION_ENTER();
591 tmp = ((I2s *)hw)->CTRLA.reg;
592 tmp &= ~I2S_CTRLA_ENABLE;
593 tmp |= value << I2S_CTRLA_ENABLE_Pos;
594 ((I2s *)hw)->CTRLA.reg = tmp;
595 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
596 I2S_CRITICAL_SECTION_LEAVE();
597}
598
599static inline void hri_i2s_clear_CTRLA_ENABLE_bit(const void *const hw)
600{
601 I2S_CRITICAL_SECTION_ENTER();
602 ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_ENABLE;
603 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
604 I2S_CRITICAL_SECTION_LEAVE();
605}
606
607static inline void hri_i2s_toggle_CTRLA_ENABLE_bit(const void *const hw)
608{
609 I2S_CRITICAL_SECTION_ENTER();
610 ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_ENABLE;
611 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
612 I2S_CRITICAL_SECTION_LEAVE();
613}
614
615static inline void hri_i2s_set_CTRLA_CKEN0_bit(const void *const hw)
616{
617 I2S_CRITICAL_SECTION_ENTER();
618 ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN0;
619 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
620 I2S_CRITICAL_SECTION_LEAVE();
621}
622
623static inline bool hri_i2s_get_CTRLA_CKEN0_bit(const void *const hw)
624{
625 uint8_t tmp;
626 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
627 tmp = ((I2s *)hw)->CTRLA.reg;
628 tmp = (tmp & I2S_CTRLA_CKEN0) >> I2S_CTRLA_CKEN0_Pos;
629 return (bool)tmp;
630}
631
632static inline void hri_i2s_write_CTRLA_CKEN0_bit(const void *const hw, bool value)
633{
634 uint8_t tmp;
635 I2S_CRITICAL_SECTION_ENTER();
636 tmp = ((I2s *)hw)->CTRLA.reg;
637 tmp &= ~I2S_CTRLA_CKEN0;
638 tmp |= value << I2S_CTRLA_CKEN0_Pos;
639 ((I2s *)hw)->CTRLA.reg = tmp;
640 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
641 I2S_CRITICAL_SECTION_LEAVE();
642}
643
644static inline void hri_i2s_clear_CTRLA_CKEN0_bit(const void *const hw)
645{
646 I2S_CRITICAL_SECTION_ENTER();
647 ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN0;
648 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
649 I2S_CRITICAL_SECTION_LEAVE();
650}
651
652static inline void hri_i2s_toggle_CTRLA_CKEN0_bit(const void *const hw)
653{
654 I2S_CRITICAL_SECTION_ENTER();
655 ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN0;
656 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
657 I2S_CRITICAL_SECTION_LEAVE();
658}
659
660static inline void hri_i2s_set_CTRLA_CKEN1_bit(const void *const hw)
661{
662 I2S_CRITICAL_SECTION_ENTER();
663 ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN1;
664 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
665 I2S_CRITICAL_SECTION_LEAVE();
666}
667
668static inline bool hri_i2s_get_CTRLA_CKEN1_bit(const void *const hw)
669{
670 uint8_t tmp;
671 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
672 tmp = ((I2s *)hw)->CTRLA.reg;
673 tmp = (tmp & I2S_CTRLA_CKEN1) >> I2S_CTRLA_CKEN1_Pos;
674 return (bool)tmp;
675}
676
677static inline void hri_i2s_write_CTRLA_CKEN1_bit(const void *const hw, bool value)
678{
679 uint8_t tmp;
680 I2S_CRITICAL_SECTION_ENTER();
681 tmp = ((I2s *)hw)->CTRLA.reg;
682 tmp &= ~I2S_CTRLA_CKEN1;
683 tmp |= value << I2S_CTRLA_CKEN1_Pos;
684 ((I2s *)hw)->CTRLA.reg = tmp;
685 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
686 I2S_CRITICAL_SECTION_LEAVE();
687}
688
689static inline void hri_i2s_clear_CTRLA_CKEN1_bit(const void *const hw)
690{
691 I2S_CRITICAL_SECTION_ENTER();
692 ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN1;
693 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
694 I2S_CRITICAL_SECTION_LEAVE();
695}
696
697static inline void hri_i2s_toggle_CTRLA_CKEN1_bit(const void *const hw)
698{
699 I2S_CRITICAL_SECTION_ENTER();
700 ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN1;
701 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
702 I2S_CRITICAL_SECTION_LEAVE();
703}
704
705static inline void hri_i2s_set_CTRLA_TXEN_bit(const void *const hw)
706{
707 I2S_CRITICAL_SECTION_ENTER();
708 ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_TXEN;
709 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
710 I2S_CRITICAL_SECTION_LEAVE();
711}
712
713static inline bool hri_i2s_get_CTRLA_TXEN_bit(const void *const hw)
714{
715 uint8_t tmp;
716 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
717 tmp = ((I2s *)hw)->CTRLA.reg;
718 tmp = (tmp & I2S_CTRLA_TXEN) >> I2S_CTRLA_TXEN_Pos;
719 return (bool)tmp;
720}
721
722static inline void hri_i2s_write_CTRLA_TXEN_bit(const void *const hw, bool value)
723{
724 uint8_t tmp;
725 I2S_CRITICAL_SECTION_ENTER();
726 tmp = ((I2s *)hw)->CTRLA.reg;
727 tmp &= ~I2S_CTRLA_TXEN;
728 tmp |= value << I2S_CTRLA_TXEN_Pos;
729 ((I2s *)hw)->CTRLA.reg = tmp;
730 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
731 I2S_CRITICAL_SECTION_LEAVE();
732}
733
734static inline void hri_i2s_clear_CTRLA_TXEN_bit(const void *const hw)
735{
736 I2S_CRITICAL_SECTION_ENTER();
737 ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_TXEN;
738 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
739 I2S_CRITICAL_SECTION_LEAVE();
740}
741
742static inline void hri_i2s_toggle_CTRLA_TXEN_bit(const void *const hw)
743{
744 I2S_CRITICAL_SECTION_ENTER();
745 ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_TXEN;
746 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
747 I2S_CRITICAL_SECTION_LEAVE();
748}
749
750static inline void hri_i2s_set_CTRLA_RXEN_bit(const void *const hw)
751{
752 I2S_CRITICAL_SECTION_ENTER();
753 ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_RXEN;
754 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
755 I2S_CRITICAL_SECTION_LEAVE();
756}
757
758static inline bool hri_i2s_get_CTRLA_RXEN_bit(const void *const hw)
759{
760 uint8_t tmp;
761 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
762 tmp = ((I2s *)hw)->CTRLA.reg;
763 tmp = (tmp & I2S_CTRLA_RXEN) >> I2S_CTRLA_RXEN_Pos;
764 return (bool)tmp;
765}
766
767static inline void hri_i2s_write_CTRLA_RXEN_bit(const void *const hw, bool value)
768{
769 uint8_t tmp;
770 I2S_CRITICAL_SECTION_ENTER();
771 tmp = ((I2s *)hw)->CTRLA.reg;
772 tmp &= ~I2S_CTRLA_RXEN;
773 tmp |= value << I2S_CTRLA_RXEN_Pos;
774 ((I2s *)hw)->CTRLA.reg = tmp;
775 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
776 I2S_CRITICAL_SECTION_LEAVE();
777}
778
779static inline void hri_i2s_clear_CTRLA_RXEN_bit(const void *const hw)
780{
781 I2S_CRITICAL_SECTION_ENTER();
782 ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_RXEN;
783 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
784 I2S_CRITICAL_SECTION_LEAVE();
785}
786
787static inline void hri_i2s_toggle_CTRLA_RXEN_bit(const void *const hw)
788{
789 I2S_CRITICAL_SECTION_ENTER();
790 ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_RXEN;
791 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
792 I2S_CRITICAL_SECTION_LEAVE();
793}
794
795static inline void hri_i2s_set_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask)
796{
797 I2S_CRITICAL_SECTION_ENTER();
798 ((I2s *)hw)->CTRLA.reg |= mask;
799 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
800 I2S_CRITICAL_SECTION_LEAVE();
801}
802
803static inline hri_i2s_ctrla_reg_t hri_i2s_get_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask)
804{
805 uint8_t tmp;
806 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
807 tmp = ((I2s *)hw)->CTRLA.reg;
808 tmp &= mask;
809 return tmp;
810}
811
812static inline void hri_i2s_write_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t data)
813{
814 I2S_CRITICAL_SECTION_ENTER();
815 ((I2s *)hw)->CTRLA.reg = data;
816 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
817 I2S_CRITICAL_SECTION_LEAVE();
818}
819
820static inline void hri_i2s_clear_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask)
821{
822 I2S_CRITICAL_SECTION_ENTER();
823 ((I2s *)hw)->CTRLA.reg &= ~mask;
824 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
825 I2S_CRITICAL_SECTION_LEAVE();
826}
827
828static inline void hri_i2s_toggle_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask)
829{
830 I2S_CRITICAL_SECTION_ENTER();
831 ((I2s *)hw)->CTRLA.reg ^= mask;
832 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
833 I2S_CRITICAL_SECTION_LEAVE();
834}
835
836static inline hri_i2s_ctrla_reg_t hri_i2s_read_CTRLA_reg(const void *const hw)
837{
838 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN);
839 return ((I2s *)hw)->CTRLA.reg;
840}
841
842static inline void hri_i2s_set_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index)
843{
844 I2S_CRITICAL_SECTION_ENTER();
845 ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_BITDELAY;
846 I2S_CRITICAL_SECTION_LEAVE();
847}
848
849static inline bool hri_i2s_get_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index)
850{
851 uint32_t tmp;
852 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
853 tmp = (tmp & I2S_CLKCTRL_BITDELAY) >> I2S_CLKCTRL_BITDELAY_Pos;
854 return (bool)tmp;
855}
856
857static inline void hri_i2s_write_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index, bool value)
858{
859 uint32_t tmp;
860 I2S_CRITICAL_SECTION_ENTER();
861 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
862 tmp &= ~I2S_CLKCTRL_BITDELAY;
863 tmp |= value << I2S_CLKCTRL_BITDELAY_Pos;
864 ((I2s *)hw)->CLKCTRL[index].reg = tmp;
865 I2S_CRITICAL_SECTION_LEAVE();
866}
867
868static inline void hri_i2s_clear_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index)
869{
870 I2S_CRITICAL_SECTION_ENTER();
871 ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_BITDELAY;
872 I2S_CRITICAL_SECTION_LEAVE();
873}
874
875static inline void hri_i2s_toggle_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index)
876{
877 I2S_CRITICAL_SECTION_ENTER();
878 ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_BITDELAY;
879 I2S_CRITICAL_SECTION_LEAVE();
880}
881
882static inline void hri_i2s_set_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index)
883{
884 I2S_CRITICAL_SECTION_ENTER();
885 ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSSEL;
886 I2S_CRITICAL_SECTION_LEAVE();
887}
888
889static inline bool hri_i2s_get_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index)
890{
891 uint32_t tmp;
892 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
893 tmp = (tmp & I2S_CLKCTRL_FSSEL) >> I2S_CLKCTRL_FSSEL_Pos;
894 return (bool)tmp;
895}
896
897static inline void hri_i2s_write_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index, bool value)
898{
899 uint32_t tmp;
900 I2S_CRITICAL_SECTION_ENTER();
901 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
902 tmp &= ~I2S_CLKCTRL_FSSEL;
903 tmp |= value << I2S_CLKCTRL_FSSEL_Pos;
904 ((I2s *)hw)->CLKCTRL[index].reg = tmp;
905 I2S_CRITICAL_SECTION_LEAVE();
906}
907
908static inline void hri_i2s_clear_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index)
909{
910 I2S_CRITICAL_SECTION_ENTER();
911 ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSSEL;
912 I2S_CRITICAL_SECTION_LEAVE();
913}
914
915static inline void hri_i2s_toggle_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index)
916{
917 I2S_CRITICAL_SECTION_ENTER();
918 ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSSEL;
919 I2S_CRITICAL_SECTION_LEAVE();
920}
921
922static inline void hri_i2s_set_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index)
923{
924 I2S_CRITICAL_SECTION_ENTER();
925 ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSINV;
926 I2S_CRITICAL_SECTION_LEAVE();
927}
928
929static inline bool hri_i2s_get_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index)
930{
931 uint32_t tmp;
932 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
933 tmp = (tmp & I2S_CLKCTRL_FSINV) >> I2S_CLKCTRL_FSINV_Pos;
934 return (bool)tmp;
935}
936
937static inline void hri_i2s_write_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index, bool value)
938{
939 uint32_t tmp;
940 I2S_CRITICAL_SECTION_ENTER();
941 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
942 tmp &= ~I2S_CLKCTRL_FSINV;
943 tmp |= value << I2S_CLKCTRL_FSINV_Pos;
944 ((I2s *)hw)->CLKCTRL[index].reg = tmp;
945 I2S_CRITICAL_SECTION_LEAVE();
946}
947
948static inline void hri_i2s_clear_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index)
949{
950 I2S_CRITICAL_SECTION_ENTER();
951 ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSINV;
952 I2S_CRITICAL_SECTION_LEAVE();
953}
954
955static inline void hri_i2s_toggle_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index)
956{
957 I2S_CRITICAL_SECTION_ENTER();
958 ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSINV;
959 I2S_CRITICAL_SECTION_LEAVE();
960}
961
962static inline void hri_i2s_set_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index)
963{
964 I2S_CRITICAL_SECTION_ENTER();
965 ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSOUTINV;
966 I2S_CRITICAL_SECTION_LEAVE();
967}
968
969static inline bool hri_i2s_get_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index)
970{
971 uint32_t tmp;
972 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
973 tmp = (tmp & I2S_CLKCTRL_FSOUTINV) >> I2S_CLKCTRL_FSOUTINV_Pos;
974 return (bool)tmp;
975}
976
977static inline void hri_i2s_write_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index, bool value)
978{
979 uint32_t tmp;
980 I2S_CRITICAL_SECTION_ENTER();
981 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
982 tmp &= ~I2S_CLKCTRL_FSOUTINV;
983 tmp |= value << I2S_CLKCTRL_FSOUTINV_Pos;
984 ((I2s *)hw)->CLKCTRL[index].reg = tmp;
985 I2S_CRITICAL_SECTION_LEAVE();
986}
987
988static inline void hri_i2s_clear_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index)
989{
990 I2S_CRITICAL_SECTION_ENTER();
991 ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSOUTINV;
992 I2S_CRITICAL_SECTION_LEAVE();
993}
994
995static inline void hri_i2s_toggle_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index)
996{
997 I2S_CRITICAL_SECTION_ENTER();
998 ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSOUTINV;
999 I2S_CRITICAL_SECTION_LEAVE();
1000}
1001
1002static inline void hri_i2s_set_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index)
1003{
1004 I2S_CRITICAL_SECTION_ENTER();
1005 ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKSEL;
1006 I2S_CRITICAL_SECTION_LEAVE();
1007}
1008
1009static inline bool hri_i2s_get_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index)
1010{
1011 uint32_t tmp;
1012 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
1013 tmp = (tmp & I2S_CLKCTRL_SCKSEL) >> I2S_CLKCTRL_SCKSEL_Pos;
1014 return (bool)tmp;
1015}
1016
1017static inline void hri_i2s_write_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index, bool value)
1018{
1019 uint32_t tmp;
1020 I2S_CRITICAL_SECTION_ENTER();
1021 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
1022 tmp &= ~I2S_CLKCTRL_SCKSEL;
1023 tmp |= value << I2S_CLKCTRL_SCKSEL_Pos;
1024 ((I2s *)hw)->CLKCTRL[index].reg = tmp;
1025 I2S_CRITICAL_SECTION_LEAVE();
1026}
1027
1028static inline void hri_i2s_clear_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index)
1029{
1030 I2S_CRITICAL_SECTION_ENTER();
1031 ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKSEL;
1032 I2S_CRITICAL_SECTION_LEAVE();
1033}
1034
1035static inline void hri_i2s_toggle_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index)
1036{
1037 I2S_CRITICAL_SECTION_ENTER();
1038 ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKSEL;
1039 I2S_CRITICAL_SECTION_LEAVE();
1040}
1041
1042static inline void hri_i2s_set_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index)
1043{
1044 I2S_CRITICAL_SECTION_ENTER();
1045 ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKOUTINV;
1046 I2S_CRITICAL_SECTION_LEAVE();
1047}
1048
1049static inline bool hri_i2s_get_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index)
1050{
1051 uint32_t tmp;
1052 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
1053 tmp = (tmp & I2S_CLKCTRL_SCKOUTINV) >> I2S_CLKCTRL_SCKOUTINV_Pos;
1054 return (bool)tmp;
1055}
1056
1057static inline void hri_i2s_write_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index, bool value)
1058{
1059 uint32_t tmp;
1060 I2S_CRITICAL_SECTION_ENTER();
1061 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
1062 tmp &= ~I2S_CLKCTRL_SCKOUTINV;
1063 tmp |= value << I2S_CLKCTRL_SCKOUTINV_Pos;
1064 ((I2s *)hw)->CLKCTRL[index].reg = tmp;
1065 I2S_CRITICAL_SECTION_LEAVE();
1066}
1067
1068static inline void hri_i2s_clear_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index)
1069{
1070 I2S_CRITICAL_SECTION_ENTER();
1071 ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKOUTINV;
1072 I2S_CRITICAL_SECTION_LEAVE();
1073}
1074
1075static inline void hri_i2s_toggle_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index)
1076{
1077 I2S_CRITICAL_SECTION_ENTER();
1078 ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKOUTINV;
1079 I2S_CRITICAL_SECTION_LEAVE();
1080}
1081
1082static inline void hri_i2s_set_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index)
1083{
1084 I2S_CRITICAL_SECTION_ENTER();
1085 ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKSEL;
1086 I2S_CRITICAL_SECTION_LEAVE();
1087}
1088
1089static inline bool hri_i2s_get_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index)
1090{
1091 uint32_t tmp;
1092 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
1093 tmp = (tmp & I2S_CLKCTRL_MCKSEL) >> I2S_CLKCTRL_MCKSEL_Pos;
1094 return (bool)tmp;
1095}
1096
1097static inline void hri_i2s_write_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index, bool value)
1098{
1099 uint32_t tmp;
1100 I2S_CRITICAL_SECTION_ENTER();
1101 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
1102 tmp &= ~I2S_CLKCTRL_MCKSEL;
1103 tmp |= value << I2S_CLKCTRL_MCKSEL_Pos;
1104 ((I2s *)hw)->CLKCTRL[index].reg = tmp;
1105 I2S_CRITICAL_SECTION_LEAVE();
1106}
1107
1108static inline void hri_i2s_clear_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index)
1109{
1110 I2S_CRITICAL_SECTION_ENTER();
1111 ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKSEL;
1112 I2S_CRITICAL_SECTION_LEAVE();
1113}
1114
1115static inline void hri_i2s_toggle_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index)
1116{
1117 I2S_CRITICAL_SECTION_ENTER();
1118 ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKSEL;
1119 I2S_CRITICAL_SECTION_LEAVE();
1120}
1121
1122static inline void hri_i2s_set_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index)
1123{
1124 I2S_CRITICAL_SECTION_ENTER();
1125 ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKEN;
1126 I2S_CRITICAL_SECTION_LEAVE();
1127}
1128
1129static inline bool hri_i2s_get_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index)
1130{
1131 uint32_t tmp;
1132 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
1133 tmp = (tmp & I2S_CLKCTRL_MCKEN) >> I2S_CLKCTRL_MCKEN_Pos;
1134 return (bool)tmp;
1135}
1136
1137static inline void hri_i2s_write_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index, bool value)
1138{
1139 uint32_t tmp;
1140 I2S_CRITICAL_SECTION_ENTER();
1141 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
1142 tmp &= ~I2S_CLKCTRL_MCKEN;
1143 tmp |= value << I2S_CLKCTRL_MCKEN_Pos;
1144 ((I2s *)hw)->CLKCTRL[index].reg = tmp;
1145 I2S_CRITICAL_SECTION_LEAVE();
1146}
1147
1148static inline void hri_i2s_clear_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index)
1149{
1150 I2S_CRITICAL_SECTION_ENTER();
1151 ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKEN;
1152 I2S_CRITICAL_SECTION_LEAVE();
1153}
1154
1155static inline void hri_i2s_toggle_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index)
1156{
1157 I2S_CRITICAL_SECTION_ENTER();
1158 ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKEN;
1159 I2S_CRITICAL_SECTION_LEAVE();
1160}
1161
1162static inline void hri_i2s_set_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index)
1163{
1164 I2S_CRITICAL_SECTION_ENTER();
1165 ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTINV;
1166 I2S_CRITICAL_SECTION_LEAVE();
1167}
1168
1169static inline bool hri_i2s_get_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index)
1170{
1171 uint32_t tmp;
1172 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
1173 tmp = (tmp & I2S_CLKCTRL_MCKOUTINV) >> I2S_CLKCTRL_MCKOUTINV_Pos;
1174 return (bool)tmp;
1175}
1176
1177static inline void hri_i2s_write_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index, bool value)
1178{
1179 uint32_t tmp;
1180 I2S_CRITICAL_SECTION_ENTER();
1181 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
1182 tmp &= ~I2S_CLKCTRL_MCKOUTINV;
1183 tmp |= value << I2S_CLKCTRL_MCKOUTINV_Pos;
1184 ((I2s *)hw)->CLKCTRL[index].reg = tmp;
1185 I2S_CRITICAL_SECTION_LEAVE();
1186}
1187
1188static inline void hri_i2s_clear_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index)
1189{
1190 I2S_CRITICAL_SECTION_ENTER();
1191 ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTINV;
1192 I2S_CRITICAL_SECTION_LEAVE();
1193}
1194
1195static inline void hri_i2s_toggle_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index)
1196{
1197 I2S_CRITICAL_SECTION_ENTER();
1198 ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTINV;
1199 I2S_CRITICAL_SECTION_LEAVE();
1200}
1201
1202static inline void hri_i2s_set_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
1203{
1204 I2S_CRITICAL_SECTION_ENTER();
1205 ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SLOTSIZE(mask);
1206 I2S_CRITICAL_SECTION_LEAVE();
1207}
1208
1209static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index,
1210 hri_i2s_clkctrl_reg_t mask)
1211{
1212 uint32_t tmp;
1213 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
1214 tmp = (tmp & I2S_CLKCTRL_SLOTSIZE(mask)) >> I2S_CLKCTRL_SLOTSIZE_Pos;
1215 return tmp;
1216}
1217
1218static inline void hri_i2s_write_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
1219{
1220 uint32_t tmp;
1221 I2S_CRITICAL_SECTION_ENTER();
1222 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
1223 tmp &= ~I2S_CLKCTRL_SLOTSIZE_Msk;
1224 tmp |= I2S_CLKCTRL_SLOTSIZE(data);
1225 ((I2s *)hw)->CLKCTRL[index].reg = tmp;
1226 I2S_CRITICAL_SECTION_LEAVE();
1227}
1228
1229static inline void hri_i2s_clear_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
1230{
1231 I2S_CRITICAL_SECTION_ENTER();
1232 ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SLOTSIZE(mask);
1233 I2S_CRITICAL_SECTION_LEAVE();
1234}
1235
1236static inline void hri_i2s_toggle_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
1237{
1238 I2S_CRITICAL_SECTION_ENTER();
1239 ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SLOTSIZE(mask);
1240 I2S_CRITICAL_SECTION_LEAVE();
1241}
1242
1243static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index)
1244{
1245 uint32_t tmp;
1246 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
1247 tmp = (tmp & I2S_CLKCTRL_SLOTSIZE_Msk) >> I2S_CLKCTRL_SLOTSIZE_Pos;
1248 return tmp;
1249}
1250
1251static inline void hri_i2s_set_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
1252{
1253 I2S_CRITICAL_SECTION_ENTER();
1254 ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_NBSLOTS(mask);
1255 I2S_CRITICAL_SECTION_LEAVE();
1256}
1257
1258static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index,
1259 hri_i2s_clkctrl_reg_t mask)
1260{
1261 uint32_t tmp;
1262 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
1263 tmp = (tmp & I2S_CLKCTRL_NBSLOTS(mask)) >> I2S_CLKCTRL_NBSLOTS_Pos;
1264 return tmp;
1265}
1266
1267static inline void hri_i2s_write_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
1268{
1269 uint32_t tmp;
1270 I2S_CRITICAL_SECTION_ENTER();
1271 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
1272 tmp &= ~I2S_CLKCTRL_NBSLOTS_Msk;
1273 tmp |= I2S_CLKCTRL_NBSLOTS(data);
1274 ((I2s *)hw)->CLKCTRL[index].reg = tmp;
1275 I2S_CRITICAL_SECTION_LEAVE();
1276}
1277
1278static inline void hri_i2s_clear_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
1279{
1280 I2S_CRITICAL_SECTION_ENTER();
1281 ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_NBSLOTS(mask);
1282 I2S_CRITICAL_SECTION_LEAVE();
1283}
1284
1285static inline void hri_i2s_toggle_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
1286{
1287 I2S_CRITICAL_SECTION_ENTER();
1288 ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_NBSLOTS(mask);
1289 I2S_CRITICAL_SECTION_LEAVE();
1290}
1291
1292static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index)
1293{
1294 uint32_t tmp;
1295 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
1296 tmp = (tmp & I2S_CLKCTRL_NBSLOTS_Msk) >> I2S_CLKCTRL_NBSLOTS_Pos;
1297 return tmp;
1298}
1299
1300static inline void hri_i2s_set_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
1301{
1302 I2S_CRITICAL_SECTION_ENTER();
1303 ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSWIDTH(mask);
1304 I2S_CRITICAL_SECTION_LEAVE();
1305}
1306
1307static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index,
1308 hri_i2s_clkctrl_reg_t mask)
1309{
1310 uint32_t tmp;
1311 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
1312 tmp = (tmp & I2S_CLKCTRL_FSWIDTH(mask)) >> I2S_CLKCTRL_FSWIDTH_Pos;
1313 return tmp;
1314}
1315
1316static inline void hri_i2s_write_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
1317{
1318 uint32_t tmp;
1319 I2S_CRITICAL_SECTION_ENTER();
1320 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
1321 tmp &= ~I2S_CLKCTRL_FSWIDTH_Msk;
1322 tmp |= I2S_CLKCTRL_FSWIDTH(data);
1323 ((I2s *)hw)->CLKCTRL[index].reg = tmp;
1324 I2S_CRITICAL_SECTION_LEAVE();
1325}
1326
1327static inline void hri_i2s_clear_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
1328{
1329 I2S_CRITICAL_SECTION_ENTER();
1330 ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSWIDTH(mask);
1331 I2S_CRITICAL_SECTION_LEAVE();
1332}
1333
1334static inline void hri_i2s_toggle_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
1335{
1336 I2S_CRITICAL_SECTION_ENTER();
1337 ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSWIDTH(mask);
1338 I2S_CRITICAL_SECTION_LEAVE();
1339}
1340
1341static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index)
1342{
1343 uint32_t tmp;
1344 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
1345 tmp = (tmp & I2S_CLKCTRL_FSWIDTH_Msk) >> I2S_CLKCTRL_FSWIDTH_Pos;
1346 return tmp;
1347}
1348
1349static inline void hri_i2s_set_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
1350{
1351 I2S_CRITICAL_SECTION_ENTER();
1352 ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKDIV(mask);
1353 I2S_CRITICAL_SECTION_LEAVE();
1354}
1355
1356static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index,
1357 hri_i2s_clkctrl_reg_t mask)
1358{
1359 uint32_t tmp;
1360 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
1361 tmp = (tmp & I2S_CLKCTRL_MCKDIV(mask)) >> I2S_CLKCTRL_MCKDIV_Pos;
1362 return tmp;
1363}
1364
1365static inline void hri_i2s_write_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
1366{
1367 uint32_t tmp;
1368 I2S_CRITICAL_SECTION_ENTER();
1369 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
1370 tmp &= ~I2S_CLKCTRL_MCKDIV_Msk;
1371 tmp |= I2S_CLKCTRL_MCKDIV(data);
1372 ((I2s *)hw)->CLKCTRL[index].reg = tmp;
1373 I2S_CRITICAL_SECTION_LEAVE();
1374}
1375
1376static inline void hri_i2s_clear_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
1377{
1378 I2S_CRITICAL_SECTION_ENTER();
1379 ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKDIV(mask);
1380 I2S_CRITICAL_SECTION_LEAVE();
1381}
1382
1383static inline void hri_i2s_toggle_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
1384{
1385 I2S_CRITICAL_SECTION_ENTER();
1386 ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKDIV(mask);
1387 I2S_CRITICAL_SECTION_LEAVE();
1388}
1389
1390static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index)
1391{
1392 uint32_t tmp;
1393 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
1394 tmp = (tmp & I2S_CLKCTRL_MCKDIV_Msk) >> I2S_CLKCTRL_MCKDIV_Pos;
1395 return tmp;
1396}
1397
1398static inline void hri_i2s_set_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
1399{
1400 I2S_CRITICAL_SECTION_ENTER();
1401 ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTDIV(mask);
1402 I2S_CRITICAL_SECTION_LEAVE();
1403}
1404
1405static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index,
1406 hri_i2s_clkctrl_reg_t mask)
1407{
1408 uint32_t tmp;
1409 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
1410 tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV(mask)) >> I2S_CLKCTRL_MCKOUTDIV_Pos;
1411 return tmp;
1412}
1413
1414static inline void hri_i2s_write_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
1415{
1416 uint32_t tmp;
1417 I2S_CRITICAL_SECTION_ENTER();
1418 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
1419 tmp &= ~I2S_CLKCTRL_MCKOUTDIV_Msk;
1420 tmp |= I2S_CLKCTRL_MCKOUTDIV(data);
1421 ((I2s *)hw)->CLKCTRL[index].reg = tmp;
1422 I2S_CRITICAL_SECTION_LEAVE();
1423}
1424
1425static inline void hri_i2s_clear_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
1426{
1427 I2S_CRITICAL_SECTION_ENTER();
1428 ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTDIV(mask);
1429 I2S_CRITICAL_SECTION_LEAVE();
1430}
1431
1432static inline void hri_i2s_toggle_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
1433{
1434 I2S_CRITICAL_SECTION_ENTER();
1435 ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTDIV(mask);
1436 I2S_CRITICAL_SECTION_LEAVE();
1437}
1438
1439static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index)
1440{
1441 uint32_t tmp;
1442 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
1443 tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV_Msk) >> I2S_CLKCTRL_MCKOUTDIV_Pos;
1444 return tmp;
1445}
1446
1447static inline void hri_i2s_set_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
1448{
1449 I2S_CRITICAL_SECTION_ENTER();
1450 ((I2s *)hw)->CLKCTRL[index].reg |= mask;
1451 I2S_CRITICAL_SECTION_LEAVE();
1452}
1453
1454static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_reg(const void *const hw, uint8_t index,
1455 hri_i2s_clkctrl_reg_t mask)
1456{
1457 uint32_t tmp;
1458 tmp = ((I2s *)hw)->CLKCTRL[index].reg;
1459 tmp &= mask;
1460 return tmp;
1461}
1462
1463static inline void hri_i2s_write_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data)
1464{
1465 I2S_CRITICAL_SECTION_ENTER();
1466 ((I2s *)hw)->CLKCTRL[index].reg = data;
1467 I2S_CRITICAL_SECTION_LEAVE();
1468}
1469
1470static inline void hri_i2s_clear_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
1471{
1472 I2S_CRITICAL_SECTION_ENTER();
1473 ((I2s *)hw)->CLKCTRL[index].reg &= ~mask;
1474 I2S_CRITICAL_SECTION_LEAVE();
1475}
1476
1477static inline void hri_i2s_toggle_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask)
1478{
1479 I2S_CRITICAL_SECTION_ENTER();
1480 ((I2s *)hw)->CLKCTRL[index].reg ^= mask;
1481 I2S_CRITICAL_SECTION_LEAVE();
1482}
1483
1484static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_reg(const void *const hw, uint8_t index)
1485{
1486 return ((I2s *)hw)->CLKCTRL[index].reg;
1487}
1488
1489static inline void hri_i2s_set_TXCTRL_TXSAME_bit(const void *const hw)
1490{
1491 I2S_CRITICAL_SECTION_ENTER();
1492 ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_TXSAME;
1493 I2S_CRITICAL_SECTION_LEAVE();
1494}
1495
1496static inline bool hri_i2s_get_TXCTRL_TXSAME_bit(const void *const hw)
1497{
1498 uint32_t tmp;
1499 tmp = ((I2s *)hw)->TXCTRL.reg;
1500 tmp = (tmp & I2S_TXCTRL_TXSAME) >> I2S_TXCTRL_TXSAME_Pos;
1501 return (bool)tmp;
1502}
1503
1504static inline void hri_i2s_write_TXCTRL_TXSAME_bit(const void *const hw, bool value)
1505{
1506 uint32_t tmp;
1507 I2S_CRITICAL_SECTION_ENTER();
1508 tmp = ((I2s *)hw)->TXCTRL.reg;
1509 tmp &= ~I2S_TXCTRL_TXSAME;
1510 tmp |= value << I2S_TXCTRL_TXSAME_Pos;
1511 ((I2s *)hw)->TXCTRL.reg = tmp;
1512 I2S_CRITICAL_SECTION_LEAVE();
1513}
1514
1515static inline void hri_i2s_clear_TXCTRL_TXSAME_bit(const void *const hw)
1516{
1517 I2S_CRITICAL_SECTION_ENTER();
1518 ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_TXSAME;
1519 I2S_CRITICAL_SECTION_LEAVE();
1520}
1521
1522static inline void hri_i2s_toggle_TXCTRL_TXSAME_bit(const void *const hw)
1523{
1524 I2S_CRITICAL_SECTION_ENTER();
1525 ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_TXSAME;
1526 I2S_CRITICAL_SECTION_LEAVE();
1527}
1528
1529static inline void hri_i2s_set_TXCTRL_SLOTADJ_bit(const void *const hw)
1530{
1531 I2S_CRITICAL_SECTION_ENTER();
1532 ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTADJ;
1533 I2S_CRITICAL_SECTION_LEAVE();
1534}
1535
1536static inline bool hri_i2s_get_TXCTRL_SLOTADJ_bit(const void *const hw)
1537{
1538 uint32_t tmp;
1539 tmp = ((I2s *)hw)->TXCTRL.reg;
1540 tmp = (tmp & I2S_TXCTRL_SLOTADJ) >> I2S_TXCTRL_SLOTADJ_Pos;
1541 return (bool)tmp;
1542}
1543
1544static inline void hri_i2s_write_TXCTRL_SLOTADJ_bit(const void *const hw, bool value)
1545{
1546 uint32_t tmp;
1547 I2S_CRITICAL_SECTION_ENTER();
1548 tmp = ((I2s *)hw)->TXCTRL.reg;
1549 tmp &= ~I2S_TXCTRL_SLOTADJ;
1550 tmp |= value << I2S_TXCTRL_SLOTADJ_Pos;
1551 ((I2s *)hw)->TXCTRL.reg = tmp;
1552 I2S_CRITICAL_SECTION_LEAVE();
1553}
1554
1555static inline void hri_i2s_clear_TXCTRL_SLOTADJ_bit(const void *const hw)
1556{
1557 I2S_CRITICAL_SECTION_ENTER();
1558 ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTADJ;
1559 I2S_CRITICAL_SECTION_LEAVE();
1560}
1561
1562static inline void hri_i2s_toggle_TXCTRL_SLOTADJ_bit(const void *const hw)
1563{
1564 I2S_CRITICAL_SECTION_ENTER();
1565 ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTADJ;
1566 I2S_CRITICAL_SECTION_LEAVE();
1567}
1568
1569static inline void hri_i2s_set_TXCTRL_WORDADJ_bit(const void *const hw)
1570{
1571 I2S_CRITICAL_SECTION_ENTER();
1572 ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_WORDADJ;
1573 I2S_CRITICAL_SECTION_LEAVE();
1574}
1575
1576static inline bool hri_i2s_get_TXCTRL_WORDADJ_bit(const void *const hw)
1577{
1578 uint32_t tmp;
1579 tmp = ((I2s *)hw)->TXCTRL.reg;
1580 tmp = (tmp & I2S_TXCTRL_WORDADJ) >> I2S_TXCTRL_WORDADJ_Pos;
1581 return (bool)tmp;
1582}
1583
1584static inline void hri_i2s_write_TXCTRL_WORDADJ_bit(const void *const hw, bool value)
1585{
1586 uint32_t tmp;
1587 I2S_CRITICAL_SECTION_ENTER();
1588 tmp = ((I2s *)hw)->TXCTRL.reg;
1589 tmp &= ~I2S_TXCTRL_WORDADJ;
1590 tmp |= value << I2S_TXCTRL_WORDADJ_Pos;
1591 ((I2s *)hw)->TXCTRL.reg = tmp;
1592 I2S_CRITICAL_SECTION_LEAVE();
1593}
1594
1595static inline void hri_i2s_clear_TXCTRL_WORDADJ_bit(const void *const hw)
1596{
1597 I2S_CRITICAL_SECTION_ENTER();
1598 ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_WORDADJ;
1599 I2S_CRITICAL_SECTION_LEAVE();
1600}
1601
1602static inline void hri_i2s_toggle_TXCTRL_WORDADJ_bit(const void *const hw)
1603{
1604 I2S_CRITICAL_SECTION_ENTER();
1605 ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_WORDADJ;
1606 I2S_CRITICAL_SECTION_LEAVE();
1607}
1608
1609static inline void hri_i2s_set_TXCTRL_BITREV_bit(const void *const hw)
1610{
1611 I2S_CRITICAL_SECTION_ENTER();
1612 ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_BITREV;
1613 I2S_CRITICAL_SECTION_LEAVE();
1614}
1615
1616static inline bool hri_i2s_get_TXCTRL_BITREV_bit(const void *const hw)
1617{
1618 uint32_t tmp;
1619 tmp = ((I2s *)hw)->TXCTRL.reg;
1620 tmp = (tmp & I2S_TXCTRL_BITREV) >> I2S_TXCTRL_BITREV_Pos;
1621 return (bool)tmp;
1622}
1623
1624static inline void hri_i2s_write_TXCTRL_BITREV_bit(const void *const hw, bool value)
1625{
1626 uint32_t tmp;
1627 I2S_CRITICAL_SECTION_ENTER();
1628 tmp = ((I2s *)hw)->TXCTRL.reg;
1629 tmp &= ~I2S_TXCTRL_BITREV;
1630 tmp |= value << I2S_TXCTRL_BITREV_Pos;
1631 ((I2s *)hw)->TXCTRL.reg = tmp;
1632 I2S_CRITICAL_SECTION_LEAVE();
1633}
1634
1635static inline void hri_i2s_clear_TXCTRL_BITREV_bit(const void *const hw)
1636{
1637 I2S_CRITICAL_SECTION_ENTER();
1638 ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_BITREV;
1639 I2S_CRITICAL_SECTION_LEAVE();
1640}
1641
1642static inline void hri_i2s_toggle_TXCTRL_BITREV_bit(const void *const hw)
1643{
1644 I2S_CRITICAL_SECTION_ENTER();
1645 ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_BITREV;
1646 I2S_CRITICAL_SECTION_LEAVE();
1647}
1648
1649static inline void hri_i2s_set_TXCTRL_SLOTDIS0_bit(const void *const hw)
1650{
1651 I2S_CRITICAL_SECTION_ENTER();
1652 ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS0;
1653 I2S_CRITICAL_SECTION_LEAVE();
1654}
1655
1656static inline bool hri_i2s_get_TXCTRL_SLOTDIS0_bit(const void *const hw)
1657{
1658 uint32_t tmp;
1659 tmp = ((I2s *)hw)->TXCTRL.reg;
1660 tmp = (tmp & I2S_TXCTRL_SLOTDIS0) >> I2S_TXCTRL_SLOTDIS0_Pos;
1661 return (bool)tmp;
1662}
1663
1664static inline void hri_i2s_write_TXCTRL_SLOTDIS0_bit(const void *const hw, bool value)
1665{
1666 uint32_t tmp;
1667 I2S_CRITICAL_SECTION_ENTER();
1668 tmp = ((I2s *)hw)->TXCTRL.reg;
1669 tmp &= ~I2S_TXCTRL_SLOTDIS0;
1670 tmp |= value << I2S_TXCTRL_SLOTDIS0_Pos;
1671 ((I2s *)hw)->TXCTRL.reg = tmp;
1672 I2S_CRITICAL_SECTION_LEAVE();
1673}
1674
1675static inline void hri_i2s_clear_TXCTRL_SLOTDIS0_bit(const void *const hw)
1676{
1677 I2S_CRITICAL_SECTION_ENTER();
1678 ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS0;
1679 I2S_CRITICAL_SECTION_LEAVE();
1680}
1681
1682static inline void hri_i2s_toggle_TXCTRL_SLOTDIS0_bit(const void *const hw)
1683{
1684 I2S_CRITICAL_SECTION_ENTER();
1685 ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS0;
1686 I2S_CRITICAL_SECTION_LEAVE();
1687}
1688
1689static inline void hri_i2s_set_TXCTRL_SLOTDIS1_bit(const void *const hw)
1690{
1691 I2S_CRITICAL_SECTION_ENTER();
1692 ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS1;
1693 I2S_CRITICAL_SECTION_LEAVE();
1694}
1695
1696static inline bool hri_i2s_get_TXCTRL_SLOTDIS1_bit(const void *const hw)
1697{
1698 uint32_t tmp;
1699 tmp = ((I2s *)hw)->TXCTRL.reg;
1700 tmp = (tmp & I2S_TXCTRL_SLOTDIS1) >> I2S_TXCTRL_SLOTDIS1_Pos;
1701 return (bool)tmp;
1702}
1703
1704static inline void hri_i2s_write_TXCTRL_SLOTDIS1_bit(const void *const hw, bool value)
1705{
1706 uint32_t tmp;
1707 I2S_CRITICAL_SECTION_ENTER();
1708 tmp = ((I2s *)hw)->TXCTRL.reg;
1709 tmp &= ~I2S_TXCTRL_SLOTDIS1;
1710 tmp |= value << I2S_TXCTRL_SLOTDIS1_Pos;
1711 ((I2s *)hw)->TXCTRL.reg = tmp;
1712 I2S_CRITICAL_SECTION_LEAVE();
1713}
1714
1715static inline void hri_i2s_clear_TXCTRL_SLOTDIS1_bit(const void *const hw)
1716{
1717 I2S_CRITICAL_SECTION_ENTER();
1718 ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS1;
1719 I2S_CRITICAL_SECTION_LEAVE();
1720}
1721
1722static inline void hri_i2s_toggle_TXCTRL_SLOTDIS1_bit(const void *const hw)
1723{
1724 I2S_CRITICAL_SECTION_ENTER();
1725 ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS1;
1726 I2S_CRITICAL_SECTION_LEAVE();
1727}
1728
1729static inline void hri_i2s_set_TXCTRL_SLOTDIS2_bit(const void *const hw)
1730{
1731 I2S_CRITICAL_SECTION_ENTER();
1732 ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS2;
1733 I2S_CRITICAL_SECTION_LEAVE();
1734}
1735
1736static inline bool hri_i2s_get_TXCTRL_SLOTDIS2_bit(const void *const hw)
1737{
1738 uint32_t tmp;
1739 tmp = ((I2s *)hw)->TXCTRL.reg;
1740 tmp = (tmp & I2S_TXCTRL_SLOTDIS2) >> I2S_TXCTRL_SLOTDIS2_Pos;
1741 return (bool)tmp;
1742}
1743
1744static inline void hri_i2s_write_TXCTRL_SLOTDIS2_bit(const void *const hw, bool value)
1745{
1746 uint32_t tmp;
1747 I2S_CRITICAL_SECTION_ENTER();
1748 tmp = ((I2s *)hw)->TXCTRL.reg;
1749 tmp &= ~I2S_TXCTRL_SLOTDIS2;
1750 tmp |= value << I2S_TXCTRL_SLOTDIS2_Pos;
1751 ((I2s *)hw)->TXCTRL.reg = tmp;
1752 I2S_CRITICAL_SECTION_LEAVE();
1753}
1754
1755static inline void hri_i2s_clear_TXCTRL_SLOTDIS2_bit(const void *const hw)
1756{
1757 I2S_CRITICAL_SECTION_ENTER();
1758 ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS2;
1759 I2S_CRITICAL_SECTION_LEAVE();
1760}
1761
1762static inline void hri_i2s_toggle_TXCTRL_SLOTDIS2_bit(const void *const hw)
1763{
1764 I2S_CRITICAL_SECTION_ENTER();
1765 ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS2;
1766 I2S_CRITICAL_SECTION_LEAVE();
1767}
1768
1769static inline void hri_i2s_set_TXCTRL_SLOTDIS3_bit(const void *const hw)
1770{
1771 I2S_CRITICAL_SECTION_ENTER();
1772 ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS3;
1773 I2S_CRITICAL_SECTION_LEAVE();
1774}
1775
1776static inline bool hri_i2s_get_TXCTRL_SLOTDIS3_bit(const void *const hw)
1777{
1778 uint32_t tmp;
1779 tmp = ((I2s *)hw)->TXCTRL.reg;
1780 tmp = (tmp & I2S_TXCTRL_SLOTDIS3) >> I2S_TXCTRL_SLOTDIS3_Pos;
1781 return (bool)tmp;
1782}
1783
1784static inline void hri_i2s_write_TXCTRL_SLOTDIS3_bit(const void *const hw, bool value)
1785{
1786 uint32_t tmp;
1787 I2S_CRITICAL_SECTION_ENTER();
1788 tmp = ((I2s *)hw)->TXCTRL.reg;
1789 tmp &= ~I2S_TXCTRL_SLOTDIS3;
1790 tmp |= value << I2S_TXCTRL_SLOTDIS3_Pos;
1791 ((I2s *)hw)->TXCTRL.reg = tmp;
1792 I2S_CRITICAL_SECTION_LEAVE();
1793}
1794
1795static inline void hri_i2s_clear_TXCTRL_SLOTDIS3_bit(const void *const hw)
1796{
1797 I2S_CRITICAL_SECTION_ENTER();
1798 ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS3;
1799 I2S_CRITICAL_SECTION_LEAVE();
1800}
1801
1802static inline void hri_i2s_toggle_TXCTRL_SLOTDIS3_bit(const void *const hw)
1803{
1804 I2S_CRITICAL_SECTION_ENTER();
1805 ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS3;
1806 I2S_CRITICAL_SECTION_LEAVE();
1807}
1808
1809static inline void hri_i2s_set_TXCTRL_SLOTDIS4_bit(const void *const hw)
1810{
1811 I2S_CRITICAL_SECTION_ENTER();
1812 ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS4;
1813 I2S_CRITICAL_SECTION_LEAVE();
1814}
1815
1816static inline bool hri_i2s_get_TXCTRL_SLOTDIS4_bit(const void *const hw)
1817{
1818 uint32_t tmp;
1819 tmp = ((I2s *)hw)->TXCTRL.reg;
1820 tmp = (tmp & I2S_TXCTRL_SLOTDIS4) >> I2S_TXCTRL_SLOTDIS4_Pos;
1821 return (bool)tmp;
1822}
1823
1824static inline void hri_i2s_write_TXCTRL_SLOTDIS4_bit(const void *const hw, bool value)
1825{
1826 uint32_t tmp;
1827 I2S_CRITICAL_SECTION_ENTER();
1828 tmp = ((I2s *)hw)->TXCTRL.reg;
1829 tmp &= ~I2S_TXCTRL_SLOTDIS4;
1830 tmp |= value << I2S_TXCTRL_SLOTDIS4_Pos;
1831 ((I2s *)hw)->TXCTRL.reg = tmp;
1832 I2S_CRITICAL_SECTION_LEAVE();
1833}
1834
1835static inline void hri_i2s_clear_TXCTRL_SLOTDIS4_bit(const void *const hw)
1836{
1837 I2S_CRITICAL_SECTION_ENTER();
1838 ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS4;
1839 I2S_CRITICAL_SECTION_LEAVE();
1840}
1841
1842static inline void hri_i2s_toggle_TXCTRL_SLOTDIS4_bit(const void *const hw)
1843{
1844 I2S_CRITICAL_SECTION_ENTER();
1845 ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS4;
1846 I2S_CRITICAL_SECTION_LEAVE();
1847}
1848
1849static inline void hri_i2s_set_TXCTRL_SLOTDIS5_bit(const void *const hw)
1850{
1851 I2S_CRITICAL_SECTION_ENTER();
1852 ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS5;
1853 I2S_CRITICAL_SECTION_LEAVE();
1854}
1855
1856static inline bool hri_i2s_get_TXCTRL_SLOTDIS5_bit(const void *const hw)
1857{
1858 uint32_t tmp;
1859 tmp = ((I2s *)hw)->TXCTRL.reg;
1860 tmp = (tmp & I2S_TXCTRL_SLOTDIS5) >> I2S_TXCTRL_SLOTDIS5_Pos;
1861 return (bool)tmp;
1862}
1863
1864static inline void hri_i2s_write_TXCTRL_SLOTDIS5_bit(const void *const hw, bool value)
1865{
1866 uint32_t tmp;
1867 I2S_CRITICAL_SECTION_ENTER();
1868 tmp = ((I2s *)hw)->TXCTRL.reg;
1869 tmp &= ~I2S_TXCTRL_SLOTDIS5;
1870 tmp |= value << I2S_TXCTRL_SLOTDIS5_Pos;
1871 ((I2s *)hw)->TXCTRL.reg = tmp;
1872 I2S_CRITICAL_SECTION_LEAVE();
1873}
1874
1875static inline void hri_i2s_clear_TXCTRL_SLOTDIS5_bit(const void *const hw)
1876{
1877 I2S_CRITICAL_SECTION_ENTER();
1878 ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS5;
1879 I2S_CRITICAL_SECTION_LEAVE();
1880}
1881
1882static inline void hri_i2s_toggle_TXCTRL_SLOTDIS5_bit(const void *const hw)
1883{
1884 I2S_CRITICAL_SECTION_ENTER();
1885 ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS5;
1886 I2S_CRITICAL_SECTION_LEAVE();
1887}
1888
1889static inline void hri_i2s_set_TXCTRL_SLOTDIS6_bit(const void *const hw)
1890{
1891 I2S_CRITICAL_SECTION_ENTER();
1892 ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS6;
1893 I2S_CRITICAL_SECTION_LEAVE();
1894}
1895
1896static inline bool hri_i2s_get_TXCTRL_SLOTDIS6_bit(const void *const hw)
1897{
1898 uint32_t tmp;
1899 tmp = ((I2s *)hw)->TXCTRL.reg;
1900 tmp = (tmp & I2S_TXCTRL_SLOTDIS6) >> I2S_TXCTRL_SLOTDIS6_Pos;
1901 return (bool)tmp;
1902}
1903
1904static inline void hri_i2s_write_TXCTRL_SLOTDIS6_bit(const void *const hw, bool value)
1905{
1906 uint32_t tmp;
1907 I2S_CRITICAL_SECTION_ENTER();
1908 tmp = ((I2s *)hw)->TXCTRL.reg;
1909 tmp &= ~I2S_TXCTRL_SLOTDIS6;
1910 tmp |= value << I2S_TXCTRL_SLOTDIS6_Pos;
1911 ((I2s *)hw)->TXCTRL.reg = tmp;
1912 I2S_CRITICAL_SECTION_LEAVE();
1913}
1914
1915static inline void hri_i2s_clear_TXCTRL_SLOTDIS6_bit(const void *const hw)
1916{
1917 I2S_CRITICAL_SECTION_ENTER();
1918 ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS6;
1919 I2S_CRITICAL_SECTION_LEAVE();
1920}
1921
1922static inline void hri_i2s_toggle_TXCTRL_SLOTDIS6_bit(const void *const hw)
1923{
1924 I2S_CRITICAL_SECTION_ENTER();
1925 ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS6;
1926 I2S_CRITICAL_SECTION_LEAVE();
1927}
1928
1929static inline void hri_i2s_set_TXCTRL_SLOTDIS7_bit(const void *const hw)
1930{
1931 I2S_CRITICAL_SECTION_ENTER();
1932 ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS7;
1933 I2S_CRITICAL_SECTION_LEAVE();
1934}
1935
1936static inline bool hri_i2s_get_TXCTRL_SLOTDIS7_bit(const void *const hw)
1937{
1938 uint32_t tmp;
1939 tmp = ((I2s *)hw)->TXCTRL.reg;
1940 tmp = (tmp & I2S_TXCTRL_SLOTDIS7) >> I2S_TXCTRL_SLOTDIS7_Pos;
1941 return (bool)tmp;
1942}
1943
1944static inline void hri_i2s_write_TXCTRL_SLOTDIS7_bit(const void *const hw, bool value)
1945{
1946 uint32_t tmp;
1947 I2S_CRITICAL_SECTION_ENTER();
1948 tmp = ((I2s *)hw)->TXCTRL.reg;
1949 tmp &= ~I2S_TXCTRL_SLOTDIS7;
1950 tmp |= value << I2S_TXCTRL_SLOTDIS7_Pos;
1951 ((I2s *)hw)->TXCTRL.reg = tmp;
1952 I2S_CRITICAL_SECTION_LEAVE();
1953}
1954
1955static inline void hri_i2s_clear_TXCTRL_SLOTDIS7_bit(const void *const hw)
1956{
1957 I2S_CRITICAL_SECTION_ENTER();
1958 ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS7;
1959 I2S_CRITICAL_SECTION_LEAVE();
1960}
1961
1962static inline void hri_i2s_toggle_TXCTRL_SLOTDIS7_bit(const void *const hw)
1963{
1964 I2S_CRITICAL_SECTION_ENTER();
1965 ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS7;
1966 I2S_CRITICAL_SECTION_LEAVE();
1967}
1968
1969static inline void hri_i2s_set_TXCTRL_MONO_bit(const void *const hw)
1970{
1971 I2S_CRITICAL_SECTION_ENTER();
1972 ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_MONO;
1973 I2S_CRITICAL_SECTION_LEAVE();
1974}
1975
1976static inline bool hri_i2s_get_TXCTRL_MONO_bit(const void *const hw)
1977{
1978 uint32_t tmp;
1979 tmp = ((I2s *)hw)->TXCTRL.reg;
1980 tmp = (tmp & I2S_TXCTRL_MONO) >> I2S_TXCTRL_MONO_Pos;
1981 return (bool)tmp;
1982}
1983
1984static inline void hri_i2s_write_TXCTRL_MONO_bit(const void *const hw, bool value)
1985{
1986 uint32_t tmp;
1987 I2S_CRITICAL_SECTION_ENTER();
1988 tmp = ((I2s *)hw)->TXCTRL.reg;
1989 tmp &= ~I2S_TXCTRL_MONO;
1990 tmp |= value << I2S_TXCTRL_MONO_Pos;
1991 ((I2s *)hw)->TXCTRL.reg = tmp;
1992 I2S_CRITICAL_SECTION_LEAVE();
1993}
1994
1995static inline void hri_i2s_clear_TXCTRL_MONO_bit(const void *const hw)
1996{
1997 I2S_CRITICAL_SECTION_ENTER();
1998 ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_MONO;
1999 I2S_CRITICAL_SECTION_LEAVE();
2000}
2001
2002static inline void hri_i2s_toggle_TXCTRL_MONO_bit(const void *const hw)
2003{
2004 I2S_CRITICAL_SECTION_ENTER();
2005 ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_MONO;
2006 I2S_CRITICAL_SECTION_LEAVE();
2007}
2008
2009static inline void hri_i2s_set_TXCTRL_DMA_bit(const void *const hw)
2010{
2011 I2S_CRITICAL_SECTION_ENTER();
2012 ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_DMA;
2013 I2S_CRITICAL_SECTION_LEAVE();
2014}
2015
2016static inline bool hri_i2s_get_TXCTRL_DMA_bit(const void *const hw)
2017{
2018 uint32_t tmp;
2019 tmp = ((I2s *)hw)->TXCTRL.reg;
2020 tmp = (tmp & I2S_TXCTRL_DMA) >> I2S_TXCTRL_DMA_Pos;
2021 return (bool)tmp;
2022}
2023
2024static inline void hri_i2s_write_TXCTRL_DMA_bit(const void *const hw, bool value)
2025{
2026 uint32_t tmp;
2027 I2S_CRITICAL_SECTION_ENTER();
2028 tmp = ((I2s *)hw)->TXCTRL.reg;
2029 tmp &= ~I2S_TXCTRL_DMA;
2030 tmp |= value << I2S_TXCTRL_DMA_Pos;
2031 ((I2s *)hw)->TXCTRL.reg = tmp;
2032 I2S_CRITICAL_SECTION_LEAVE();
2033}
2034
2035static inline void hri_i2s_clear_TXCTRL_DMA_bit(const void *const hw)
2036{
2037 I2S_CRITICAL_SECTION_ENTER();
2038 ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_DMA;
2039 I2S_CRITICAL_SECTION_LEAVE();
2040}
2041
2042static inline void hri_i2s_toggle_TXCTRL_DMA_bit(const void *const hw)
2043{
2044 I2S_CRITICAL_SECTION_ENTER();
2045 ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_DMA;
2046 I2S_CRITICAL_SECTION_LEAVE();
2047}
2048
2049static inline void hri_i2s_set_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
2050{
2051 I2S_CRITICAL_SECTION_ENTER();
2052 ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_TXDEFAULT(mask);
2053 I2S_CRITICAL_SECTION_LEAVE();
2054}
2055
2056static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
2057{
2058 uint32_t tmp;
2059 tmp = ((I2s *)hw)->TXCTRL.reg;
2060 tmp = (tmp & I2S_TXCTRL_TXDEFAULT(mask)) >> I2S_TXCTRL_TXDEFAULT_Pos;
2061 return tmp;
2062}
2063
2064static inline void hri_i2s_write_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t data)
2065{
2066 uint32_t tmp;
2067 I2S_CRITICAL_SECTION_ENTER();
2068 tmp = ((I2s *)hw)->TXCTRL.reg;
2069 tmp &= ~I2S_TXCTRL_TXDEFAULT_Msk;
2070 tmp |= I2S_TXCTRL_TXDEFAULT(data);
2071 ((I2s *)hw)->TXCTRL.reg = tmp;
2072 I2S_CRITICAL_SECTION_LEAVE();
2073}
2074
2075static inline void hri_i2s_clear_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
2076{
2077 I2S_CRITICAL_SECTION_ENTER();
2078 ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_TXDEFAULT(mask);
2079 I2S_CRITICAL_SECTION_LEAVE();
2080}
2081
2082static inline void hri_i2s_toggle_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
2083{
2084 I2S_CRITICAL_SECTION_ENTER();
2085 ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_TXDEFAULT(mask);
2086 I2S_CRITICAL_SECTION_LEAVE();
2087}
2088
2089static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_TXDEFAULT_bf(const void *const hw)
2090{
2091 uint32_t tmp;
2092 tmp = ((I2s *)hw)->TXCTRL.reg;
2093 tmp = (tmp & I2S_TXCTRL_TXDEFAULT_Msk) >> I2S_TXCTRL_TXDEFAULT_Pos;
2094 return tmp;
2095}
2096
2097static inline void hri_i2s_set_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
2098{
2099 I2S_CRITICAL_SECTION_ENTER();
2100 ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_DATASIZE(mask);
2101 I2S_CRITICAL_SECTION_LEAVE();
2102}
2103
2104static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
2105{
2106 uint32_t tmp;
2107 tmp = ((I2s *)hw)->TXCTRL.reg;
2108 tmp = (tmp & I2S_TXCTRL_DATASIZE(mask)) >> I2S_TXCTRL_DATASIZE_Pos;
2109 return tmp;
2110}
2111
2112static inline void hri_i2s_write_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t data)
2113{
2114 uint32_t tmp;
2115 I2S_CRITICAL_SECTION_ENTER();
2116 tmp = ((I2s *)hw)->TXCTRL.reg;
2117 tmp &= ~I2S_TXCTRL_DATASIZE_Msk;
2118 tmp |= I2S_TXCTRL_DATASIZE(data);
2119 ((I2s *)hw)->TXCTRL.reg = tmp;
2120 I2S_CRITICAL_SECTION_LEAVE();
2121}
2122
2123static inline void hri_i2s_clear_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
2124{
2125 I2S_CRITICAL_SECTION_ENTER();
2126 ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_DATASIZE(mask);
2127 I2S_CRITICAL_SECTION_LEAVE();
2128}
2129
2130static inline void hri_i2s_toggle_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
2131{
2132 I2S_CRITICAL_SECTION_ENTER();
2133 ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_DATASIZE(mask);
2134 I2S_CRITICAL_SECTION_LEAVE();
2135}
2136
2137static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_DATASIZE_bf(const void *const hw)
2138{
2139 uint32_t tmp;
2140 tmp = ((I2s *)hw)->TXCTRL.reg;
2141 tmp = (tmp & I2S_TXCTRL_DATASIZE_Msk) >> I2S_TXCTRL_DATASIZE_Pos;
2142 return tmp;
2143}
2144
2145static inline void hri_i2s_set_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
2146{
2147 I2S_CRITICAL_SECTION_ENTER();
2148 ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_EXTEND(mask);
2149 I2S_CRITICAL_SECTION_LEAVE();
2150}
2151
2152static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
2153{
2154 uint32_t tmp;
2155 tmp = ((I2s *)hw)->TXCTRL.reg;
2156 tmp = (tmp & I2S_TXCTRL_EXTEND(mask)) >> I2S_TXCTRL_EXTEND_Pos;
2157 return tmp;
2158}
2159
2160static inline void hri_i2s_write_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t data)
2161{
2162 uint32_t tmp;
2163 I2S_CRITICAL_SECTION_ENTER();
2164 tmp = ((I2s *)hw)->TXCTRL.reg;
2165 tmp &= ~I2S_TXCTRL_EXTEND_Msk;
2166 tmp |= I2S_TXCTRL_EXTEND(data);
2167 ((I2s *)hw)->TXCTRL.reg = tmp;
2168 I2S_CRITICAL_SECTION_LEAVE();
2169}
2170
2171static inline void hri_i2s_clear_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
2172{
2173 I2S_CRITICAL_SECTION_ENTER();
2174 ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_EXTEND(mask);
2175 I2S_CRITICAL_SECTION_LEAVE();
2176}
2177
2178static inline void hri_i2s_toggle_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask)
2179{
2180 I2S_CRITICAL_SECTION_ENTER();
2181 ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_EXTEND(mask);
2182 I2S_CRITICAL_SECTION_LEAVE();
2183}
2184
2185static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_EXTEND_bf(const void *const hw)
2186{
2187 uint32_t tmp;
2188 tmp = ((I2s *)hw)->TXCTRL.reg;
2189 tmp = (tmp & I2S_TXCTRL_EXTEND_Msk) >> I2S_TXCTRL_EXTEND_Pos;
2190 return tmp;
2191}
2192
2193static inline void hri_i2s_set_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask)
2194{
2195 I2S_CRITICAL_SECTION_ENTER();
2196 ((I2s *)hw)->TXCTRL.reg |= mask;
2197 I2S_CRITICAL_SECTION_LEAVE();
2198}
2199
2200static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask)
2201{
2202 uint32_t tmp;
2203 tmp = ((I2s *)hw)->TXCTRL.reg;
2204 tmp &= mask;
2205 return tmp;
2206}
2207
2208static inline void hri_i2s_write_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t data)
2209{
2210 I2S_CRITICAL_SECTION_ENTER();
2211 ((I2s *)hw)->TXCTRL.reg = data;
2212 I2S_CRITICAL_SECTION_LEAVE();
2213}
2214
2215static inline void hri_i2s_clear_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask)
2216{
2217 I2S_CRITICAL_SECTION_ENTER();
2218 ((I2s *)hw)->TXCTRL.reg &= ~mask;
2219 I2S_CRITICAL_SECTION_LEAVE();
2220}
2221
2222static inline void hri_i2s_toggle_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask)
2223{
2224 I2S_CRITICAL_SECTION_ENTER();
2225 ((I2s *)hw)->TXCTRL.reg ^= mask;
2226 I2S_CRITICAL_SECTION_LEAVE();
2227}
2228
2229static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_reg(const void *const hw)
2230{
2231 return ((I2s *)hw)->TXCTRL.reg;
2232}
2233
2234static inline void hri_i2s_set_RXCTRL_CLKSEL_bit(const void *const hw)
2235{
2236 I2S_CRITICAL_SECTION_ENTER();
2237 ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_CLKSEL;
2238 I2S_CRITICAL_SECTION_LEAVE();
2239}
2240
2241static inline bool hri_i2s_get_RXCTRL_CLKSEL_bit(const void *const hw)
2242{
2243 uint32_t tmp;
2244 tmp = ((I2s *)hw)->RXCTRL.reg;
2245 tmp = (tmp & I2S_RXCTRL_CLKSEL) >> I2S_RXCTRL_CLKSEL_Pos;
2246 return (bool)tmp;
2247}
2248
2249static inline void hri_i2s_write_RXCTRL_CLKSEL_bit(const void *const hw, bool value)
2250{
2251 uint32_t tmp;
2252 I2S_CRITICAL_SECTION_ENTER();
2253 tmp = ((I2s *)hw)->RXCTRL.reg;
2254 tmp &= ~I2S_RXCTRL_CLKSEL;
2255 tmp |= value << I2S_RXCTRL_CLKSEL_Pos;
2256 ((I2s *)hw)->RXCTRL.reg = tmp;
2257 I2S_CRITICAL_SECTION_LEAVE();
2258}
2259
2260static inline void hri_i2s_clear_RXCTRL_CLKSEL_bit(const void *const hw)
2261{
2262 I2S_CRITICAL_SECTION_ENTER();
2263 ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_CLKSEL;
2264 I2S_CRITICAL_SECTION_LEAVE();
2265}
2266
2267static inline void hri_i2s_toggle_RXCTRL_CLKSEL_bit(const void *const hw)
2268{
2269 I2S_CRITICAL_SECTION_ENTER();
2270 ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_CLKSEL;
2271 I2S_CRITICAL_SECTION_LEAVE();
2272}
2273
2274static inline void hri_i2s_set_RXCTRL_SLOTADJ_bit(const void *const hw)
2275{
2276 I2S_CRITICAL_SECTION_ENTER();
2277 ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTADJ;
2278 I2S_CRITICAL_SECTION_LEAVE();
2279}
2280
2281static inline bool hri_i2s_get_RXCTRL_SLOTADJ_bit(const void *const hw)
2282{
2283 uint32_t tmp;
2284 tmp = ((I2s *)hw)->RXCTRL.reg;
2285 tmp = (tmp & I2S_RXCTRL_SLOTADJ) >> I2S_RXCTRL_SLOTADJ_Pos;
2286 return (bool)tmp;
2287}
2288
2289static inline void hri_i2s_write_RXCTRL_SLOTADJ_bit(const void *const hw, bool value)
2290{
2291 uint32_t tmp;
2292 I2S_CRITICAL_SECTION_ENTER();
2293 tmp = ((I2s *)hw)->RXCTRL.reg;
2294 tmp &= ~I2S_RXCTRL_SLOTADJ;
2295 tmp |= value << I2S_RXCTRL_SLOTADJ_Pos;
2296 ((I2s *)hw)->RXCTRL.reg = tmp;
2297 I2S_CRITICAL_SECTION_LEAVE();
2298}
2299
2300static inline void hri_i2s_clear_RXCTRL_SLOTADJ_bit(const void *const hw)
2301{
2302 I2S_CRITICAL_SECTION_ENTER();
2303 ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTADJ;
2304 I2S_CRITICAL_SECTION_LEAVE();
2305}
2306
2307static inline void hri_i2s_toggle_RXCTRL_SLOTADJ_bit(const void *const hw)
2308{
2309 I2S_CRITICAL_SECTION_ENTER();
2310 ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTADJ;
2311 I2S_CRITICAL_SECTION_LEAVE();
2312}
2313
2314static inline void hri_i2s_set_RXCTRL_WORDADJ_bit(const void *const hw)
2315{
2316 I2S_CRITICAL_SECTION_ENTER();
2317 ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_WORDADJ;
2318 I2S_CRITICAL_SECTION_LEAVE();
2319}
2320
2321static inline bool hri_i2s_get_RXCTRL_WORDADJ_bit(const void *const hw)
2322{
2323 uint32_t tmp;
2324 tmp = ((I2s *)hw)->RXCTRL.reg;
2325 tmp = (tmp & I2S_RXCTRL_WORDADJ) >> I2S_RXCTRL_WORDADJ_Pos;
2326 return (bool)tmp;
2327}
2328
2329static inline void hri_i2s_write_RXCTRL_WORDADJ_bit(const void *const hw, bool value)
2330{
2331 uint32_t tmp;
2332 I2S_CRITICAL_SECTION_ENTER();
2333 tmp = ((I2s *)hw)->RXCTRL.reg;
2334 tmp &= ~I2S_RXCTRL_WORDADJ;
2335 tmp |= value << I2S_RXCTRL_WORDADJ_Pos;
2336 ((I2s *)hw)->RXCTRL.reg = tmp;
2337 I2S_CRITICAL_SECTION_LEAVE();
2338}
2339
2340static inline void hri_i2s_clear_RXCTRL_WORDADJ_bit(const void *const hw)
2341{
2342 I2S_CRITICAL_SECTION_ENTER();
2343 ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_WORDADJ;
2344 I2S_CRITICAL_SECTION_LEAVE();
2345}
2346
2347static inline void hri_i2s_toggle_RXCTRL_WORDADJ_bit(const void *const hw)
2348{
2349 I2S_CRITICAL_SECTION_ENTER();
2350 ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_WORDADJ;
2351 I2S_CRITICAL_SECTION_LEAVE();
2352}
2353
2354static inline void hri_i2s_set_RXCTRL_BITREV_bit(const void *const hw)
2355{
2356 I2S_CRITICAL_SECTION_ENTER();
2357 ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_BITREV;
2358 I2S_CRITICAL_SECTION_LEAVE();
2359}
2360
2361static inline bool hri_i2s_get_RXCTRL_BITREV_bit(const void *const hw)
2362{
2363 uint32_t tmp;
2364 tmp = ((I2s *)hw)->RXCTRL.reg;
2365 tmp = (tmp & I2S_RXCTRL_BITREV) >> I2S_RXCTRL_BITREV_Pos;
2366 return (bool)tmp;
2367}
2368
2369static inline void hri_i2s_write_RXCTRL_BITREV_bit(const void *const hw, bool value)
2370{
2371 uint32_t tmp;
2372 I2S_CRITICAL_SECTION_ENTER();
2373 tmp = ((I2s *)hw)->RXCTRL.reg;
2374 tmp &= ~I2S_RXCTRL_BITREV;
2375 tmp |= value << I2S_RXCTRL_BITREV_Pos;
2376 ((I2s *)hw)->RXCTRL.reg = tmp;
2377 I2S_CRITICAL_SECTION_LEAVE();
2378}
2379
2380static inline void hri_i2s_clear_RXCTRL_BITREV_bit(const void *const hw)
2381{
2382 I2S_CRITICAL_SECTION_ENTER();
2383 ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_BITREV;
2384 I2S_CRITICAL_SECTION_LEAVE();
2385}
2386
2387static inline void hri_i2s_toggle_RXCTRL_BITREV_bit(const void *const hw)
2388{
2389 I2S_CRITICAL_SECTION_ENTER();
2390 ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_BITREV;
2391 I2S_CRITICAL_SECTION_LEAVE();
2392}
2393
2394static inline void hri_i2s_set_RXCTRL_SLOTDIS0_bit(const void *const hw)
2395{
2396 I2S_CRITICAL_SECTION_ENTER();
2397 ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS0;
2398 I2S_CRITICAL_SECTION_LEAVE();
2399}
2400
2401static inline bool hri_i2s_get_RXCTRL_SLOTDIS0_bit(const void *const hw)
2402{
2403 uint32_t tmp;
2404 tmp = ((I2s *)hw)->RXCTRL.reg;
2405 tmp = (tmp & I2S_RXCTRL_SLOTDIS0) >> I2S_RXCTRL_SLOTDIS0_Pos;
2406 return (bool)tmp;
2407}
2408
2409static inline void hri_i2s_write_RXCTRL_SLOTDIS0_bit(const void *const hw, bool value)
2410{
2411 uint32_t tmp;
2412 I2S_CRITICAL_SECTION_ENTER();
2413 tmp = ((I2s *)hw)->RXCTRL.reg;
2414 tmp &= ~I2S_RXCTRL_SLOTDIS0;
2415 tmp |= value << I2S_RXCTRL_SLOTDIS0_Pos;
2416 ((I2s *)hw)->RXCTRL.reg = tmp;
2417 I2S_CRITICAL_SECTION_LEAVE();
2418}
2419
2420static inline void hri_i2s_clear_RXCTRL_SLOTDIS0_bit(const void *const hw)
2421{
2422 I2S_CRITICAL_SECTION_ENTER();
2423 ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS0;
2424 I2S_CRITICAL_SECTION_LEAVE();
2425}
2426
2427static inline void hri_i2s_toggle_RXCTRL_SLOTDIS0_bit(const void *const hw)
2428{
2429 I2S_CRITICAL_SECTION_ENTER();
2430 ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS0;
2431 I2S_CRITICAL_SECTION_LEAVE();
2432}
2433
2434static inline void hri_i2s_set_RXCTRL_SLOTDIS1_bit(const void *const hw)
2435{
2436 I2S_CRITICAL_SECTION_ENTER();
2437 ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS1;
2438 I2S_CRITICAL_SECTION_LEAVE();
2439}
2440
2441static inline bool hri_i2s_get_RXCTRL_SLOTDIS1_bit(const void *const hw)
2442{
2443 uint32_t tmp;
2444 tmp = ((I2s *)hw)->RXCTRL.reg;
2445 tmp = (tmp & I2S_RXCTRL_SLOTDIS1) >> I2S_RXCTRL_SLOTDIS1_Pos;
2446 return (bool)tmp;
2447}
2448
2449static inline void hri_i2s_write_RXCTRL_SLOTDIS1_bit(const void *const hw, bool value)
2450{
2451 uint32_t tmp;
2452 I2S_CRITICAL_SECTION_ENTER();
2453 tmp = ((I2s *)hw)->RXCTRL.reg;
2454 tmp &= ~I2S_RXCTRL_SLOTDIS1;
2455 tmp |= value << I2S_RXCTRL_SLOTDIS1_Pos;
2456 ((I2s *)hw)->RXCTRL.reg = tmp;
2457 I2S_CRITICAL_SECTION_LEAVE();
2458}
2459
2460static inline void hri_i2s_clear_RXCTRL_SLOTDIS1_bit(const void *const hw)
2461{
2462 I2S_CRITICAL_SECTION_ENTER();
2463 ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS1;
2464 I2S_CRITICAL_SECTION_LEAVE();
2465}
2466
2467static inline void hri_i2s_toggle_RXCTRL_SLOTDIS1_bit(const void *const hw)
2468{
2469 I2S_CRITICAL_SECTION_ENTER();
2470 ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS1;
2471 I2S_CRITICAL_SECTION_LEAVE();
2472}
2473
2474static inline void hri_i2s_set_RXCTRL_SLOTDIS2_bit(const void *const hw)
2475{
2476 I2S_CRITICAL_SECTION_ENTER();
2477 ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS2;
2478 I2S_CRITICAL_SECTION_LEAVE();
2479}
2480
2481static inline bool hri_i2s_get_RXCTRL_SLOTDIS2_bit(const void *const hw)
2482{
2483 uint32_t tmp;
2484 tmp = ((I2s *)hw)->RXCTRL.reg;
2485 tmp = (tmp & I2S_RXCTRL_SLOTDIS2) >> I2S_RXCTRL_SLOTDIS2_Pos;
2486 return (bool)tmp;
2487}
2488
2489static inline void hri_i2s_write_RXCTRL_SLOTDIS2_bit(const void *const hw, bool value)
2490{
2491 uint32_t tmp;
2492 I2S_CRITICAL_SECTION_ENTER();
2493 tmp = ((I2s *)hw)->RXCTRL.reg;
2494 tmp &= ~I2S_RXCTRL_SLOTDIS2;
2495 tmp |= value << I2S_RXCTRL_SLOTDIS2_Pos;
2496 ((I2s *)hw)->RXCTRL.reg = tmp;
2497 I2S_CRITICAL_SECTION_LEAVE();
2498}
2499
2500static inline void hri_i2s_clear_RXCTRL_SLOTDIS2_bit(const void *const hw)
2501{
2502 I2S_CRITICAL_SECTION_ENTER();
2503 ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS2;
2504 I2S_CRITICAL_SECTION_LEAVE();
2505}
2506
2507static inline void hri_i2s_toggle_RXCTRL_SLOTDIS2_bit(const void *const hw)
2508{
2509 I2S_CRITICAL_SECTION_ENTER();
2510 ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS2;
2511 I2S_CRITICAL_SECTION_LEAVE();
2512}
2513
2514static inline void hri_i2s_set_RXCTRL_SLOTDIS3_bit(const void *const hw)
2515{
2516 I2S_CRITICAL_SECTION_ENTER();
2517 ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS3;
2518 I2S_CRITICAL_SECTION_LEAVE();
2519}
2520
2521static inline bool hri_i2s_get_RXCTRL_SLOTDIS3_bit(const void *const hw)
2522{
2523 uint32_t tmp;
2524 tmp = ((I2s *)hw)->RXCTRL.reg;
2525 tmp = (tmp & I2S_RXCTRL_SLOTDIS3) >> I2S_RXCTRL_SLOTDIS3_Pos;
2526 return (bool)tmp;
2527}
2528
2529static inline void hri_i2s_write_RXCTRL_SLOTDIS3_bit(const void *const hw, bool value)
2530{
2531 uint32_t tmp;
2532 I2S_CRITICAL_SECTION_ENTER();
2533 tmp = ((I2s *)hw)->RXCTRL.reg;
2534 tmp &= ~I2S_RXCTRL_SLOTDIS3;
2535 tmp |= value << I2S_RXCTRL_SLOTDIS3_Pos;
2536 ((I2s *)hw)->RXCTRL.reg = tmp;
2537 I2S_CRITICAL_SECTION_LEAVE();
2538}
2539
2540static inline void hri_i2s_clear_RXCTRL_SLOTDIS3_bit(const void *const hw)
2541{
2542 I2S_CRITICAL_SECTION_ENTER();
2543 ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS3;
2544 I2S_CRITICAL_SECTION_LEAVE();
2545}
2546
2547static inline void hri_i2s_toggle_RXCTRL_SLOTDIS3_bit(const void *const hw)
2548{
2549 I2S_CRITICAL_SECTION_ENTER();
2550 ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS3;
2551 I2S_CRITICAL_SECTION_LEAVE();
2552}
2553
2554static inline void hri_i2s_set_RXCTRL_SLOTDIS4_bit(const void *const hw)
2555{
2556 I2S_CRITICAL_SECTION_ENTER();
2557 ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS4;
2558 I2S_CRITICAL_SECTION_LEAVE();
2559}
2560
2561static inline bool hri_i2s_get_RXCTRL_SLOTDIS4_bit(const void *const hw)
2562{
2563 uint32_t tmp;
2564 tmp = ((I2s *)hw)->RXCTRL.reg;
2565 tmp = (tmp & I2S_RXCTRL_SLOTDIS4) >> I2S_RXCTRL_SLOTDIS4_Pos;
2566 return (bool)tmp;
2567}
2568
2569static inline void hri_i2s_write_RXCTRL_SLOTDIS4_bit(const void *const hw, bool value)
2570{
2571 uint32_t tmp;
2572 I2S_CRITICAL_SECTION_ENTER();
2573 tmp = ((I2s *)hw)->RXCTRL.reg;
2574 tmp &= ~I2S_RXCTRL_SLOTDIS4;
2575 tmp |= value << I2S_RXCTRL_SLOTDIS4_Pos;
2576 ((I2s *)hw)->RXCTRL.reg = tmp;
2577 I2S_CRITICAL_SECTION_LEAVE();
2578}
2579
2580static inline void hri_i2s_clear_RXCTRL_SLOTDIS4_bit(const void *const hw)
2581{
2582 I2S_CRITICAL_SECTION_ENTER();
2583 ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS4;
2584 I2S_CRITICAL_SECTION_LEAVE();
2585}
2586
2587static inline void hri_i2s_toggle_RXCTRL_SLOTDIS4_bit(const void *const hw)
2588{
2589 I2S_CRITICAL_SECTION_ENTER();
2590 ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS4;
2591 I2S_CRITICAL_SECTION_LEAVE();
2592}
2593
2594static inline void hri_i2s_set_RXCTRL_SLOTDIS5_bit(const void *const hw)
2595{
2596 I2S_CRITICAL_SECTION_ENTER();
2597 ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS5;
2598 I2S_CRITICAL_SECTION_LEAVE();
2599}
2600
2601static inline bool hri_i2s_get_RXCTRL_SLOTDIS5_bit(const void *const hw)
2602{
2603 uint32_t tmp;
2604 tmp = ((I2s *)hw)->RXCTRL.reg;
2605 tmp = (tmp & I2S_RXCTRL_SLOTDIS5) >> I2S_RXCTRL_SLOTDIS5_Pos;
2606 return (bool)tmp;
2607}
2608
2609static inline void hri_i2s_write_RXCTRL_SLOTDIS5_bit(const void *const hw, bool value)
2610{
2611 uint32_t tmp;
2612 I2S_CRITICAL_SECTION_ENTER();
2613 tmp = ((I2s *)hw)->RXCTRL.reg;
2614 tmp &= ~I2S_RXCTRL_SLOTDIS5;
2615 tmp |= value << I2S_RXCTRL_SLOTDIS5_Pos;
2616 ((I2s *)hw)->RXCTRL.reg = tmp;
2617 I2S_CRITICAL_SECTION_LEAVE();
2618}
2619
2620static inline void hri_i2s_clear_RXCTRL_SLOTDIS5_bit(const void *const hw)
2621{
2622 I2S_CRITICAL_SECTION_ENTER();
2623 ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS5;
2624 I2S_CRITICAL_SECTION_LEAVE();
2625}
2626
2627static inline void hri_i2s_toggle_RXCTRL_SLOTDIS5_bit(const void *const hw)
2628{
2629 I2S_CRITICAL_SECTION_ENTER();
2630 ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS5;
2631 I2S_CRITICAL_SECTION_LEAVE();
2632}
2633
2634static inline void hri_i2s_set_RXCTRL_SLOTDIS6_bit(const void *const hw)
2635{
2636 I2S_CRITICAL_SECTION_ENTER();
2637 ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS6;
2638 I2S_CRITICAL_SECTION_LEAVE();
2639}
2640
2641static inline bool hri_i2s_get_RXCTRL_SLOTDIS6_bit(const void *const hw)
2642{
2643 uint32_t tmp;
2644 tmp = ((I2s *)hw)->RXCTRL.reg;
2645 tmp = (tmp & I2S_RXCTRL_SLOTDIS6) >> I2S_RXCTRL_SLOTDIS6_Pos;
2646 return (bool)tmp;
2647}
2648
2649static inline void hri_i2s_write_RXCTRL_SLOTDIS6_bit(const void *const hw, bool value)
2650{
2651 uint32_t tmp;
2652 I2S_CRITICAL_SECTION_ENTER();
2653 tmp = ((I2s *)hw)->RXCTRL.reg;
2654 tmp &= ~I2S_RXCTRL_SLOTDIS6;
2655 tmp |= value << I2S_RXCTRL_SLOTDIS6_Pos;
2656 ((I2s *)hw)->RXCTRL.reg = tmp;
2657 I2S_CRITICAL_SECTION_LEAVE();
2658}
2659
2660static inline void hri_i2s_clear_RXCTRL_SLOTDIS6_bit(const void *const hw)
2661{
2662 I2S_CRITICAL_SECTION_ENTER();
2663 ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS6;
2664 I2S_CRITICAL_SECTION_LEAVE();
2665}
2666
2667static inline void hri_i2s_toggle_RXCTRL_SLOTDIS6_bit(const void *const hw)
2668{
2669 I2S_CRITICAL_SECTION_ENTER();
2670 ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS6;
2671 I2S_CRITICAL_SECTION_LEAVE();
2672}
2673
2674static inline void hri_i2s_set_RXCTRL_SLOTDIS7_bit(const void *const hw)
2675{
2676 I2S_CRITICAL_SECTION_ENTER();
2677 ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS7;
2678 I2S_CRITICAL_SECTION_LEAVE();
2679}
2680
2681static inline bool hri_i2s_get_RXCTRL_SLOTDIS7_bit(const void *const hw)
2682{
2683 uint32_t tmp;
2684 tmp = ((I2s *)hw)->RXCTRL.reg;
2685 tmp = (tmp & I2S_RXCTRL_SLOTDIS7) >> I2S_RXCTRL_SLOTDIS7_Pos;
2686 return (bool)tmp;
2687}
2688
2689static inline void hri_i2s_write_RXCTRL_SLOTDIS7_bit(const void *const hw, bool value)
2690{
2691 uint32_t tmp;
2692 I2S_CRITICAL_SECTION_ENTER();
2693 tmp = ((I2s *)hw)->RXCTRL.reg;
2694 tmp &= ~I2S_RXCTRL_SLOTDIS7;
2695 tmp |= value << I2S_RXCTRL_SLOTDIS7_Pos;
2696 ((I2s *)hw)->RXCTRL.reg = tmp;
2697 I2S_CRITICAL_SECTION_LEAVE();
2698}
2699
2700static inline void hri_i2s_clear_RXCTRL_SLOTDIS7_bit(const void *const hw)
2701{
2702 I2S_CRITICAL_SECTION_ENTER();
2703 ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS7;
2704 I2S_CRITICAL_SECTION_LEAVE();
2705}
2706
2707static inline void hri_i2s_toggle_RXCTRL_SLOTDIS7_bit(const void *const hw)
2708{
2709 I2S_CRITICAL_SECTION_ENTER();
2710 ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS7;
2711 I2S_CRITICAL_SECTION_LEAVE();
2712}
2713
2714static inline void hri_i2s_set_RXCTRL_MONO_bit(const void *const hw)
2715{
2716 I2S_CRITICAL_SECTION_ENTER();
2717 ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_MONO;
2718 I2S_CRITICAL_SECTION_LEAVE();
2719}
2720
2721static inline bool hri_i2s_get_RXCTRL_MONO_bit(const void *const hw)
2722{
2723 uint32_t tmp;
2724 tmp = ((I2s *)hw)->RXCTRL.reg;
2725 tmp = (tmp & I2S_RXCTRL_MONO) >> I2S_RXCTRL_MONO_Pos;
2726 return (bool)tmp;
2727}
2728
2729static inline void hri_i2s_write_RXCTRL_MONO_bit(const void *const hw, bool value)
2730{
2731 uint32_t tmp;
2732 I2S_CRITICAL_SECTION_ENTER();
2733 tmp = ((I2s *)hw)->RXCTRL.reg;
2734 tmp &= ~I2S_RXCTRL_MONO;
2735 tmp |= value << I2S_RXCTRL_MONO_Pos;
2736 ((I2s *)hw)->RXCTRL.reg = tmp;
2737 I2S_CRITICAL_SECTION_LEAVE();
2738}
2739
2740static inline void hri_i2s_clear_RXCTRL_MONO_bit(const void *const hw)
2741{
2742 I2S_CRITICAL_SECTION_ENTER();
2743 ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_MONO;
2744 I2S_CRITICAL_SECTION_LEAVE();
2745}
2746
2747static inline void hri_i2s_toggle_RXCTRL_MONO_bit(const void *const hw)
2748{
2749 I2S_CRITICAL_SECTION_ENTER();
2750 ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_MONO;
2751 I2S_CRITICAL_SECTION_LEAVE();
2752}
2753
2754static inline void hri_i2s_set_RXCTRL_DMA_bit(const void *const hw)
2755{
2756 I2S_CRITICAL_SECTION_ENTER();
2757 ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_DMA;
2758 I2S_CRITICAL_SECTION_LEAVE();
2759}
2760
2761static inline bool hri_i2s_get_RXCTRL_DMA_bit(const void *const hw)
2762{
2763 uint32_t tmp;
2764 tmp = ((I2s *)hw)->RXCTRL.reg;
2765 tmp = (tmp & I2S_RXCTRL_DMA) >> I2S_RXCTRL_DMA_Pos;
2766 return (bool)tmp;
2767}
2768
2769static inline void hri_i2s_write_RXCTRL_DMA_bit(const void *const hw, bool value)
2770{
2771 uint32_t tmp;
2772 I2S_CRITICAL_SECTION_ENTER();
2773 tmp = ((I2s *)hw)->RXCTRL.reg;
2774 tmp &= ~I2S_RXCTRL_DMA;
2775 tmp |= value << I2S_RXCTRL_DMA_Pos;
2776 ((I2s *)hw)->RXCTRL.reg = tmp;
2777 I2S_CRITICAL_SECTION_LEAVE();
2778}
2779
2780static inline void hri_i2s_clear_RXCTRL_DMA_bit(const void *const hw)
2781{
2782 I2S_CRITICAL_SECTION_ENTER();
2783 ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_DMA;
2784 I2S_CRITICAL_SECTION_LEAVE();
2785}
2786
2787static inline void hri_i2s_toggle_RXCTRL_DMA_bit(const void *const hw)
2788{
2789 I2S_CRITICAL_SECTION_ENTER();
2790 ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_DMA;
2791 I2S_CRITICAL_SECTION_LEAVE();
2792}
2793
2794static inline void hri_i2s_set_RXCTRL_RXLOOP_bit(const void *const hw)
2795{
2796 I2S_CRITICAL_SECTION_ENTER();
2797 ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_RXLOOP;
2798 I2S_CRITICAL_SECTION_LEAVE();
2799}
2800
2801static inline bool hri_i2s_get_RXCTRL_RXLOOP_bit(const void *const hw)
2802{
2803 uint32_t tmp;
2804 tmp = ((I2s *)hw)->RXCTRL.reg;
2805 tmp = (tmp & I2S_RXCTRL_RXLOOP) >> I2S_RXCTRL_RXLOOP_Pos;
2806 return (bool)tmp;
2807}
2808
2809static inline void hri_i2s_write_RXCTRL_RXLOOP_bit(const void *const hw, bool value)
2810{
2811 uint32_t tmp;
2812 I2S_CRITICAL_SECTION_ENTER();
2813 tmp = ((I2s *)hw)->RXCTRL.reg;
2814 tmp &= ~I2S_RXCTRL_RXLOOP;
2815 tmp |= value << I2S_RXCTRL_RXLOOP_Pos;
2816 ((I2s *)hw)->RXCTRL.reg = tmp;
2817 I2S_CRITICAL_SECTION_LEAVE();
2818}
2819
2820static inline void hri_i2s_clear_RXCTRL_RXLOOP_bit(const void *const hw)
2821{
2822 I2S_CRITICAL_SECTION_ENTER();
2823 ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_RXLOOP;
2824 I2S_CRITICAL_SECTION_LEAVE();
2825}
2826
2827static inline void hri_i2s_toggle_RXCTRL_RXLOOP_bit(const void *const hw)
2828{
2829 I2S_CRITICAL_SECTION_ENTER();
2830 ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_RXLOOP;
2831 I2S_CRITICAL_SECTION_LEAVE();
2832}
2833
2834static inline void hri_i2s_set_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
2835{
2836 I2S_CRITICAL_SECTION_ENTER();
2837 ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SERMODE(mask);
2838 I2S_CRITICAL_SECTION_LEAVE();
2839}
2840
2841static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
2842{
2843 uint32_t tmp;
2844 tmp = ((I2s *)hw)->RXCTRL.reg;
2845 tmp = (tmp & I2S_RXCTRL_SERMODE(mask)) >> I2S_RXCTRL_SERMODE_Pos;
2846 return tmp;
2847}
2848
2849static inline void hri_i2s_write_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t data)
2850{
2851 uint32_t tmp;
2852 I2S_CRITICAL_SECTION_ENTER();
2853 tmp = ((I2s *)hw)->RXCTRL.reg;
2854 tmp &= ~I2S_RXCTRL_SERMODE_Msk;
2855 tmp |= I2S_RXCTRL_SERMODE(data);
2856 ((I2s *)hw)->RXCTRL.reg = tmp;
2857 I2S_CRITICAL_SECTION_LEAVE();
2858}
2859
2860static inline void hri_i2s_clear_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
2861{
2862 I2S_CRITICAL_SECTION_ENTER();
2863 ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SERMODE(mask);
2864 I2S_CRITICAL_SECTION_LEAVE();
2865}
2866
2867static inline void hri_i2s_toggle_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
2868{
2869 I2S_CRITICAL_SECTION_ENTER();
2870 ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SERMODE(mask);
2871 I2S_CRITICAL_SECTION_LEAVE();
2872}
2873
2874static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_SERMODE_bf(const void *const hw)
2875{
2876 uint32_t tmp;
2877 tmp = ((I2s *)hw)->RXCTRL.reg;
2878 tmp = (tmp & I2S_RXCTRL_SERMODE_Msk) >> I2S_RXCTRL_SERMODE_Pos;
2879 return tmp;
2880}
2881
2882static inline void hri_i2s_set_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
2883{
2884 I2S_CRITICAL_SECTION_ENTER();
2885 ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_DATASIZE(mask);
2886 I2S_CRITICAL_SECTION_LEAVE();
2887}
2888
2889static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
2890{
2891 uint32_t tmp;
2892 tmp = ((I2s *)hw)->RXCTRL.reg;
2893 tmp = (tmp & I2S_RXCTRL_DATASIZE(mask)) >> I2S_RXCTRL_DATASIZE_Pos;
2894 return tmp;
2895}
2896
2897static inline void hri_i2s_write_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t data)
2898{
2899 uint32_t tmp;
2900 I2S_CRITICAL_SECTION_ENTER();
2901 tmp = ((I2s *)hw)->RXCTRL.reg;
2902 tmp &= ~I2S_RXCTRL_DATASIZE_Msk;
2903 tmp |= I2S_RXCTRL_DATASIZE(data);
2904 ((I2s *)hw)->RXCTRL.reg = tmp;
2905 I2S_CRITICAL_SECTION_LEAVE();
2906}
2907
2908static inline void hri_i2s_clear_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
2909{
2910 I2S_CRITICAL_SECTION_ENTER();
2911 ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_DATASIZE(mask);
2912 I2S_CRITICAL_SECTION_LEAVE();
2913}
2914
2915static inline void hri_i2s_toggle_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
2916{
2917 I2S_CRITICAL_SECTION_ENTER();
2918 ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_DATASIZE(mask);
2919 I2S_CRITICAL_SECTION_LEAVE();
2920}
2921
2922static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_DATASIZE_bf(const void *const hw)
2923{
2924 uint32_t tmp;
2925 tmp = ((I2s *)hw)->RXCTRL.reg;
2926 tmp = (tmp & I2S_RXCTRL_DATASIZE_Msk) >> I2S_RXCTRL_DATASIZE_Pos;
2927 return tmp;
2928}
2929
2930static inline void hri_i2s_set_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
2931{
2932 I2S_CRITICAL_SECTION_ENTER();
2933 ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_EXTEND(mask);
2934 I2S_CRITICAL_SECTION_LEAVE();
2935}
2936
2937static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
2938{
2939 uint32_t tmp;
2940 tmp = ((I2s *)hw)->RXCTRL.reg;
2941 tmp = (tmp & I2S_RXCTRL_EXTEND(mask)) >> I2S_RXCTRL_EXTEND_Pos;
2942 return tmp;
2943}
2944
2945static inline void hri_i2s_write_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t data)
2946{
2947 uint32_t tmp;
2948 I2S_CRITICAL_SECTION_ENTER();
2949 tmp = ((I2s *)hw)->RXCTRL.reg;
2950 tmp &= ~I2S_RXCTRL_EXTEND_Msk;
2951 tmp |= I2S_RXCTRL_EXTEND(data);
2952 ((I2s *)hw)->RXCTRL.reg = tmp;
2953 I2S_CRITICAL_SECTION_LEAVE();
2954}
2955
2956static inline void hri_i2s_clear_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
2957{
2958 I2S_CRITICAL_SECTION_ENTER();
2959 ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_EXTEND(mask);
2960 I2S_CRITICAL_SECTION_LEAVE();
2961}
2962
2963static inline void hri_i2s_toggle_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask)
2964{
2965 I2S_CRITICAL_SECTION_ENTER();
2966 ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_EXTEND(mask);
2967 I2S_CRITICAL_SECTION_LEAVE();
2968}
2969
2970static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_EXTEND_bf(const void *const hw)
2971{
2972 uint32_t tmp;
2973 tmp = ((I2s *)hw)->RXCTRL.reg;
2974 tmp = (tmp & I2S_RXCTRL_EXTEND_Msk) >> I2S_RXCTRL_EXTEND_Pos;
2975 return tmp;
2976}
2977
2978static inline void hri_i2s_set_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask)
2979{
2980 I2S_CRITICAL_SECTION_ENTER();
2981 ((I2s *)hw)->RXCTRL.reg |= mask;
2982 I2S_CRITICAL_SECTION_LEAVE();
2983}
2984
2985static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask)
2986{
2987 uint32_t tmp;
2988 tmp = ((I2s *)hw)->RXCTRL.reg;
2989 tmp &= mask;
2990 return tmp;
2991}
2992
2993static inline void hri_i2s_write_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t data)
2994{
2995 I2S_CRITICAL_SECTION_ENTER();
2996 ((I2s *)hw)->RXCTRL.reg = data;
2997 I2S_CRITICAL_SECTION_LEAVE();
2998}
2999
3000static inline void hri_i2s_clear_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask)
3001{
3002 I2S_CRITICAL_SECTION_ENTER();
3003 ((I2s *)hw)->RXCTRL.reg &= ~mask;
3004 I2S_CRITICAL_SECTION_LEAVE();
3005}
3006
3007static inline void hri_i2s_toggle_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask)
3008{
3009 I2S_CRITICAL_SECTION_ENTER();
3010 ((I2s *)hw)->RXCTRL.reg ^= mask;
3011 I2S_CRITICAL_SECTION_LEAVE();
3012}
3013
3014static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_reg(const void *const hw)
3015{
3016 return ((I2s *)hw)->RXCTRL.reg;
3017}
3018
3019static inline void hri_i2s_write_TXDATA_reg(const void *const hw, hri_i2s_txdata_reg_t data)
3020{
3021 I2S_CRITICAL_SECTION_ENTER();
3022 ((I2s *)hw)->TXDATA.reg = data;
3023 hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK);
3024 I2S_CRITICAL_SECTION_LEAVE();
3025}
3026
3027#ifdef __cplusplus
3028}
3029#endif
3030
3031#endif /* _HRI_I2S_E54_H_INCLUDED */
3032#endif /* _SAME54_I2S_COMPONENT_ */