Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM NVMCTRL |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_NVMCTRL_COMPONENT_ |
| 35 | #ifndef _HRI_NVMCTRL_E54_H_INCLUDED_ |
| 36 | #define _HRI_NVMCTRL_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_NVMCTRL_CRITICAL_SECTIONS) |
| 46 | #define NVMCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define NVMCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define NVMCTRL_CRITICAL_SECTION_ENTER() |
| 50 | #define NVMCTRL_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint16_t hri_nvmctrl_ctrla_reg_t; |
| 54 | typedef uint16_t hri_nvmctrl_ctrlb_reg_t; |
| 55 | typedef uint16_t hri_nvmctrl_intenset_reg_t; |
| 56 | typedef uint16_t hri_nvmctrl_intflag_reg_t; |
| 57 | typedef uint16_t hri_nvmctrl_status_reg_t; |
| 58 | typedef uint32_t hri_nvmctrl_addr_reg_t; |
| 59 | typedef uint32_t hri_nvmctrl_eccerr_reg_t; |
| 60 | typedef uint32_t hri_nvmctrl_param_reg_t; |
| 61 | typedef uint32_t hri_nvmctrl_pbldata_reg_t; |
| 62 | typedef uint32_t hri_nvmctrl_runlock_reg_t; |
| 63 | typedef uint32_t hri_nvmctrl_seestat_reg_t; |
| 64 | typedef uint8_t hri_nvmctrl_dbgctrl_reg_t; |
| 65 | typedef uint8_t hri_nvmctrl_seecfg_reg_t; |
| 66 | |
| 67 | static inline bool hri_nvmctrl_get_INTFLAG_DONE_bit(const void *const hw) |
| 68 | { |
| 69 | return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_DONE) >> NVMCTRL_INTFLAG_DONE_Pos; |
| 70 | } |
| 71 | |
| 72 | static inline void hri_nvmctrl_clear_INTFLAG_DONE_bit(const void *const hw) |
| 73 | { |
| 74 | ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_DONE; |
| 75 | } |
| 76 | |
| 77 | static inline bool hri_nvmctrl_get_INTFLAG_ADDRE_bit(const void *const hw) |
| 78 | { |
| 79 | return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ADDRE) >> NVMCTRL_INTFLAG_ADDRE_Pos; |
| 80 | } |
| 81 | |
| 82 | static inline void hri_nvmctrl_clear_INTFLAG_ADDRE_bit(const void *const hw) |
| 83 | { |
| 84 | ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ADDRE; |
| 85 | } |
| 86 | |
| 87 | static inline bool hri_nvmctrl_get_INTFLAG_PROGE_bit(const void *const hw) |
| 88 | { |
| 89 | return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_PROGE) >> NVMCTRL_INTFLAG_PROGE_Pos; |
| 90 | } |
| 91 | |
| 92 | static inline void hri_nvmctrl_clear_INTFLAG_PROGE_bit(const void *const hw) |
| 93 | { |
| 94 | ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_PROGE; |
| 95 | } |
| 96 | |
| 97 | static inline bool hri_nvmctrl_get_INTFLAG_LOCKE_bit(const void *const hw) |
| 98 | { |
| 99 | return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_LOCKE) >> NVMCTRL_INTFLAG_LOCKE_Pos; |
| 100 | } |
| 101 | |
| 102 | static inline void hri_nvmctrl_clear_INTFLAG_LOCKE_bit(const void *const hw) |
| 103 | { |
| 104 | ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_LOCKE; |
| 105 | } |
| 106 | |
| 107 | static inline bool hri_nvmctrl_get_INTFLAG_ECCSE_bit(const void *const hw) |
| 108 | { |
| 109 | return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCSE) >> NVMCTRL_INTFLAG_ECCSE_Pos; |
| 110 | } |
| 111 | |
| 112 | static inline void hri_nvmctrl_clear_INTFLAG_ECCSE_bit(const void *const hw) |
| 113 | { |
| 114 | ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCSE; |
| 115 | } |
| 116 | |
| 117 | static inline bool hri_nvmctrl_get_INTFLAG_ECCDE_bit(const void *const hw) |
| 118 | { |
| 119 | return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCDE) >> NVMCTRL_INTFLAG_ECCDE_Pos; |
| 120 | } |
| 121 | |
| 122 | static inline void hri_nvmctrl_clear_INTFLAG_ECCDE_bit(const void *const hw) |
| 123 | { |
| 124 | ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCDE; |
| 125 | } |
| 126 | |
| 127 | static inline bool hri_nvmctrl_get_INTFLAG_NVME_bit(const void *const hw) |
| 128 | { |
| 129 | return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_NVME) >> NVMCTRL_INTFLAG_NVME_Pos; |
| 130 | } |
| 131 | |
| 132 | static inline void hri_nvmctrl_clear_INTFLAG_NVME_bit(const void *const hw) |
| 133 | { |
| 134 | ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_NVME; |
| 135 | } |
| 136 | |
| 137 | static inline bool hri_nvmctrl_get_INTFLAG_SUSP_bit(const void *const hw) |
| 138 | { |
| 139 | return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SUSP) >> NVMCTRL_INTFLAG_SUSP_Pos; |
| 140 | } |
| 141 | |
| 142 | static inline void hri_nvmctrl_clear_INTFLAG_SUSP_bit(const void *const hw) |
| 143 | { |
| 144 | ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SUSP; |
| 145 | } |
| 146 | |
| 147 | static inline bool hri_nvmctrl_get_INTFLAG_SEESFULL_bit(const void *const hw) |
| 148 | { |
| 149 | return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESFULL) >> NVMCTRL_INTFLAG_SEESFULL_Pos; |
| 150 | } |
| 151 | |
| 152 | static inline void hri_nvmctrl_clear_INTFLAG_SEESFULL_bit(const void *const hw) |
| 153 | { |
| 154 | ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESFULL; |
| 155 | } |
| 156 | |
| 157 | static inline bool hri_nvmctrl_get_INTFLAG_SEESOVF_bit(const void *const hw) |
| 158 | { |
| 159 | return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESOVF) >> NVMCTRL_INTFLAG_SEESOVF_Pos; |
| 160 | } |
| 161 | |
| 162 | static inline void hri_nvmctrl_clear_INTFLAG_SEESOVF_bit(const void *const hw) |
| 163 | { |
| 164 | ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESOVF; |
| 165 | } |
| 166 | |
| 167 | static inline bool hri_nvmctrl_get_INTFLAG_SEEWRC_bit(const void *const hw) |
| 168 | { |
| 169 | return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEEWRC) >> NVMCTRL_INTFLAG_SEEWRC_Pos; |
| 170 | } |
| 171 | |
| 172 | static inline void hri_nvmctrl_clear_INTFLAG_SEEWRC_bit(const void *const hw) |
| 173 | { |
| 174 | ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEEWRC; |
| 175 | } |
| 176 | |
| 177 | static inline bool hri_nvmctrl_get_interrupt_DONE_bit(const void *const hw) |
| 178 | { |
| 179 | return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_DONE) >> NVMCTRL_INTFLAG_DONE_Pos; |
| 180 | } |
| 181 | |
| 182 | static inline void hri_nvmctrl_clear_interrupt_DONE_bit(const void *const hw) |
| 183 | { |
| 184 | ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_DONE; |
| 185 | } |
| 186 | |
| 187 | static inline bool hri_nvmctrl_get_interrupt_ADDRE_bit(const void *const hw) |
| 188 | { |
| 189 | return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ADDRE) >> NVMCTRL_INTFLAG_ADDRE_Pos; |
| 190 | } |
| 191 | |
| 192 | static inline void hri_nvmctrl_clear_interrupt_ADDRE_bit(const void *const hw) |
| 193 | { |
| 194 | ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ADDRE; |
| 195 | } |
| 196 | |
| 197 | static inline bool hri_nvmctrl_get_interrupt_PROGE_bit(const void *const hw) |
| 198 | { |
| 199 | return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_PROGE) >> NVMCTRL_INTFLAG_PROGE_Pos; |
| 200 | } |
| 201 | |
| 202 | static inline void hri_nvmctrl_clear_interrupt_PROGE_bit(const void *const hw) |
| 203 | { |
| 204 | ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_PROGE; |
| 205 | } |
| 206 | |
| 207 | static inline bool hri_nvmctrl_get_interrupt_LOCKE_bit(const void *const hw) |
| 208 | { |
| 209 | return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_LOCKE) >> NVMCTRL_INTFLAG_LOCKE_Pos; |
| 210 | } |
| 211 | |
| 212 | static inline void hri_nvmctrl_clear_interrupt_LOCKE_bit(const void *const hw) |
| 213 | { |
| 214 | ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_LOCKE; |
| 215 | } |
| 216 | |
| 217 | static inline bool hri_nvmctrl_get_interrupt_ECCSE_bit(const void *const hw) |
| 218 | { |
| 219 | return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCSE) >> NVMCTRL_INTFLAG_ECCSE_Pos; |
| 220 | } |
| 221 | |
| 222 | static inline void hri_nvmctrl_clear_interrupt_ECCSE_bit(const void *const hw) |
| 223 | { |
| 224 | ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCSE; |
| 225 | } |
| 226 | |
| 227 | static inline bool hri_nvmctrl_get_interrupt_ECCDE_bit(const void *const hw) |
| 228 | { |
| 229 | return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCDE) >> NVMCTRL_INTFLAG_ECCDE_Pos; |
| 230 | } |
| 231 | |
| 232 | static inline void hri_nvmctrl_clear_interrupt_ECCDE_bit(const void *const hw) |
| 233 | { |
| 234 | ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCDE; |
| 235 | } |
| 236 | |
| 237 | static inline bool hri_nvmctrl_get_interrupt_NVME_bit(const void *const hw) |
| 238 | { |
| 239 | return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_NVME) >> NVMCTRL_INTFLAG_NVME_Pos; |
| 240 | } |
| 241 | |
| 242 | static inline void hri_nvmctrl_clear_interrupt_NVME_bit(const void *const hw) |
| 243 | { |
| 244 | ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_NVME; |
| 245 | } |
| 246 | |
| 247 | static inline bool hri_nvmctrl_get_interrupt_SUSP_bit(const void *const hw) |
| 248 | { |
| 249 | return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SUSP) >> NVMCTRL_INTFLAG_SUSP_Pos; |
| 250 | } |
| 251 | |
| 252 | static inline void hri_nvmctrl_clear_interrupt_SUSP_bit(const void *const hw) |
| 253 | { |
| 254 | ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SUSP; |
| 255 | } |
| 256 | |
| 257 | static inline bool hri_nvmctrl_get_interrupt_SEESFULL_bit(const void *const hw) |
| 258 | { |
| 259 | return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESFULL) >> NVMCTRL_INTFLAG_SEESFULL_Pos; |
| 260 | } |
| 261 | |
| 262 | static inline void hri_nvmctrl_clear_interrupt_SEESFULL_bit(const void *const hw) |
| 263 | { |
| 264 | ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESFULL; |
| 265 | } |
| 266 | |
| 267 | static inline bool hri_nvmctrl_get_interrupt_SEESOVF_bit(const void *const hw) |
| 268 | { |
| 269 | return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESOVF) >> NVMCTRL_INTFLAG_SEESOVF_Pos; |
| 270 | } |
| 271 | |
| 272 | static inline void hri_nvmctrl_clear_interrupt_SEESOVF_bit(const void *const hw) |
| 273 | { |
| 274 | ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESOVF; |
| 275 | } |
| 276 | |
| 277 | static inline bool hri_nvmctrl_get_interrupt_SEEWRC_bit(const void *const hw) |
| 278 | { |
| 279 | return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEEWRC) >> NVMCTRL_INTFLAG_SEEWRC_Pos; |
| 280 | } |
| 281 | |
| 282 | static inline void hri_nvmctrl_clear_interrupt_SEEWRC_bit(const void *const hw) |
| 283 | { |
| 284 | ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEEWRC; |
| 285 | } |
| 286 | |
| 287 | static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_get_INTFLAG_reg(const void *const hw, |
| 288 | hri_nvmctrl_intflag_reg_t mask) |
| 289 | { |
| 290 | uint16_t tmp; |
| 291 | tmp = ((Nvmctrl *)hw)->INTFLAG.reg; |
| 292 | tmp &= mask; |
| 293 | return tmp; |
| 294 | } |
| 295 | |
| 296 | static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_read_INTFLAG_reg(const void *const hw) |
| 297 | { |
| 298 | return ((Nvmctrl *)hw)->INTFLAG.reg; |
| 299 | } |
| 300 | |
| 301 | static inline void hri_nvmctrl_clear_INTFLAG_reg(const void *const hw, hri_nvmctrl_intflag_reg_t mask) |
| 302 | { |
| 303 | ((Nvmctrl *)hw)->INTFLAG.reg = mask; |
| 304 | } |
| 305 | |
| 306 | static inline void hri_nvmctrl_set_INTEN_DONE_bit(const void *const hw) |
| 307 | { |
| 308 | ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_DONE; |
| 309 | } |
| 310 | |
| 311 | static inline bool hri_nvmctrl_get_INTEN_DONE_bit(const void *const hw) |
| 312 | { |
| 313 | return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_DONE) >> NVMCTRL_INTENSET_DONE_Pos; |
| 314 | } |
| 315 | |
| 316 | static inline void hri_nvmctrl_write_INTEN_DONE_bit(const void *const hw, bool value) |
| 317 | { |
| 318 | if (value == 0x0) { |
| 319 | ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_DONE; |
| 320 | } else { |
| 321 | ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_DONE; |
| 322 | } |
| 323 | } |
| 324 | |
| 325 | static inline void hri_nvmctrl_clear_INTEN_DONE_bit(const void *const hw) |
| 326 | { |
| 327 | ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_DONE; |
| 328 | } |
| 329 | |
| 330 | static inline void hri_nvmctrl_set_INTEN_ADDRE_bit(const void *const hw) |
| 331 | { |
| 332 | ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ADDRE; |
| 333 | } |
| 334 | |
| 335 | static inline bool hri_nvmctrl_get_INTEN_ADDRE_bit(const void *const hw) |
| 336 | { |
| 337 | return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ADDRE) >> NVMCTRL_INTENSET_ADDRE_Pos; |
| 338 | } |
| 339 | |
| 340 | static inline void hri_nvmctrl_write_INTEN_ADDRE_bit(const void *const hw, bool value) |
| 341 | { |
| 342 | if (value == 0x0) { |
| 343 | ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ADDRE; |
| 344 | } else { |
| 345 | ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ADDRE; |
| 346 | } |
| 347 | } |
| 348 | |
| 349 | static inline void hri_nvmctrl_clear_INTEN_ADDRE_bit(const void *const hw) |
| 350 | { |
| 351 | ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ADDRE; |
| 352 | } |
| 353 | |
| 354 | static inline void hri_nvmctrl_set_INTEN_PROGE_bit(const void *const hw) |
| 355 | { |
| 356 | ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_PROGE; |
| 357 | } |
| 358 | |
| 359 | static inline bool hri_nvmctrl_get_INTEN_PROGE_bit(const void *const hw) |
| 360 | { |
| 361 | return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_PROGE) >> NVMCTRL_INTENSET_PROGE_Pos; |
| 362 | } |
| 363 | |
| 364 | static inline void hri_nvmctrl_write_INTEN_PROGE_bit(const void *const hw, bool value) |
| 365 | { |
| 366 | if (value == 0x0) { |
| 367 | ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_PROGE; |
| 368 | } else { |
| 369 | ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_PROGE; |
| 370 | } |
| 371 | } |
| 372 | |
| 373 | static inline void hri_nvmctrl_clear_INTEN_PROGE_bit(const void *const hw) |
| 374 | { |
| 375 | ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_PROGE; |
| 376 | } |
| 377 | |
| 378 | static inline void hri_nvmctrl_set_INTEN_LOCKE_bit(const void *const hw) |
| 379 | { |
| 380 | ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_LOCKE; |
| 381 | } |
| 382 | |
| 383 | static inline bool hri_nvmctrl_get_INTEN_LOCKE_bit(const void *const hw) |
| 384 | { |
| 385 | return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_LOCKE) >> NVMCTRL_INTENSET_LOCKE_Pos; |
| 386 | } |
| 387 | |
| 388 | static inline void hri_nvmctrl_write_INTEN_LOCKE_bit(const void *const hw, bool value) |
| 389 | { |
| 390 | if (value == 0x0) { |
| 391 | ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_LOCKE; |
| 392 | } else { |
| 393 | ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_LOCKE; |
| 394 | } |
| 395 | } |
| 396 | |
| 397 | static inline void hri_nvmctrl_clear_INTEN_LOCKE_bit(const void *const hw) |
| 398 | { |
| 399 | ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_LOCKE; |
| 400 | } |
| 401 | |
| 402 | static inline void hri_nvmctrl_set_INTEN_ECCSE_bit(const void *const hw) |
| 403 | { |
| 404 | ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCSE; |
| 405 | } |
| 406 | |
| 407 | static inline bool hri_nvmctrl_get_INTEN_ECCSE_bit(const void *const hw) |
| 408 | { |
| 409 | return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ECCSE) >> NVMCTRL_INTENSET_ECCSE_Pos; |
| 410 | } |
| 411 | |
| 412 | static inline void hri_nvmctrl_write_INTEN_ECCSE_bit(const void *const hw, bool value) |
| 413 | { |
| 414 | if (value == 0x0) { |
| 415 | ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCSE; |
| 416 | } else { |
| 417 | ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCSE; |
| 418 | } |
| 419 | } |
| 420 | |
| 421 | static inline void hri_nvmctrl_clear_INTEN_ECCSE_bit(const void *const hw) |
| 422 | { |
| 423 | ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCSE; |
| 424 | } |
| 425 | |
| 426 | static inline void hri_nvmctrl_set_INTEN_ECCDE_bit(const void *const hw) |
| 427 | { |
| 428 | ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCDE; |
| 429 | } |
| 430 | |
| 431 | static inline bool hri_nvmctrl_get_INTEN_ECCDE_bit(const void *const hw) |
| 432 | { |
| 433 | return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ECCDE) >> NVMCTRL_INTENSET_ECCDE_Pos; |
| 434 | } |
| 435 | |
| 436 | static inline void hri_nvmctrl_write_INTEN_ECCDE_bit(const void *const hw, bool value) |
| 437 | { |
| 438 | if (value == 0x0) { |
| 439 | ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCDE; |
| 440 | } else { |
| 441 | ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCDE; |
| 442 | } |
| 443 | } |
| 444 | |
| 445 | static inline void hri_nvmctrl_clear_INTEN_ECCDE_bit(const void *const hw) |
| 446 | { |
| 447 | ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCDE; |
| 448 | } |
| 449 | |
| 450 | static inline void hri_nvmctrl_set_INTEN_NVME_bit(const void *const hw) |
| 451 | { |
| 452 | ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_NVME; |
| 453 | } |
| 454 | |
| 455 | static inline bool hri_nvmctrl_get_INTEN_NVME_bit(const void *const hw) |
| 456 | { |
| 457 | return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_NVME) >> NVMCTRL_INTENSET_NVME_Pos; |
| 458 | } |
| 459 | |
| 460 | static inline void hri_nvmctrl_write_INTEN_NVME_bit(const void *const hw, bool value) |
| 461 | { |
| 462 | if (value == 0x0) { |
| 463 | ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_NVME; |
| 464 | } else { |
| 465 | ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_NVME; |
| 466 | } |
| 467 | } |
| 468 | |
| 469 | static inline void hri_nvmctrl_clear_INTEN_NVME_bit(const void *const hw) |
| 470 | { |
| 471 | ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_NVME; |
| 472 | } |
| 473 | |
| 474 | static inline void hri_nvmctrl_set_INTEN_SUSP_bit(const void *const hw) |
| 475 | { |
| 476 | ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SUSP; |
| 477 | } |
| 478 | |
| 479 | static inline bool hri_nvmctrl_get_INTEN_SUSP_bit(const void *const hw) |
| 480 | { |
| 481 | return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SUSP) >> NVMCTRL_INTENSET_SUSP_Pos; |
| 482 | } |
| 483 | |
| 484 | static inline void hri_nvmctrl_write_INTEN_SUSP_bit(const void *const hw, bool value) |
| 485 | { |
| 486 | if (value == 0x0) { |
| 487 | ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SUSP; |
| 488 | } else { |
| 489 | ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SUSP; |
| 490 | } |
| 491 | } |
| 492 | |
| 493 | static inline void hri_nvmctrl_clear_INTEN_SUSP_bit(const void *const hw) |
| 494 | { |
| 495 | ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SUSP; |
| 496 | } |
| 497 | |
| 498 | static inline void hri_nvmctrl_set_INTEN_SEESFULL_bit(const void *const hw) |
| 499 | { |
| 500 | ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESFULL; |
| 501 | } |
| 502 | |
| 503 | static inline bool hri_nvmctrl_get_INTEN_SEESFULL_bit(const void *const hw) |
| 504 | { |
| 505 | return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEESFULL) >> NVMCTRL_INTENSET_SEESFULL_Pos; |
| 506 | } |
| 507 | |
| 508 | static inline void hri_nvmctrl_write_INTEN_SEESFULL_bit(const void *const hw, bool value) |
| 509 | { |
| 510 | if (value == 0x0) { |
| 511 | ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESFULL; |
| 512 | } else { |
| 513 | ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESFULL; |
| 514 | } |
| 515 | } |
| 516 | |
| 517 | static inline void hri_nvmctrl_clear_INTEN_SEESFULL_bit(const void *const hw) |
| 518 | { |
| 519 | ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESFULL; |
| 520 | } |
| 521 | |
| 522 | static inline void hri_nvmctrl_set_INTEN_SEESOVF_bit(const void *const hw) |
| 523 | { |
| 524 | ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESOVF; |
| 525 | } |
| 526 | |
| 527 | static inline bool hri_nvmctrl_get_INTEN_SEESOVF_bit(const void *const hw) |
| 528 | { |
| 529 | return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEESOVF) >> NVMCTRL_INTENSET_SEESOVF_Pos; |
| 530 | } |
| 531 | |
| 532 | static inline void hri_nvmctrl_write_INTEN_SEESOVF_bit(const void *const hw, bool value) |
| 533 | { |
| 534 | if (value == 0x0) { |
| 535 | ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESOVF; |
| 536 | } else { |
| 537 | ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESOVF; |
| 538 | } |
| 539 | } |
| 540 | |
| 541 | static inline void hri_nvmctrl_clear_INTEN_SEESOVF_bit(const void *const hw) |
| 542 | { |
| 543 | ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESOVF; |
| 544 | } |
| 545 | |
| 546 | static inline void hri_nvmctrl_set_INTEN_SEEWRC_bit(const void *const hw) |
| 547 | { |
| 548 | ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEEWRC; |
| 549 | } |
| 550 | |
| 551 | static inline bool hri_nvmctrl_get_INTEN_SEEWRC_bit(const void *const hw) |
| 552 | { |
| 553 | return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEEWRC) >> NVMCTRL_INTENSET_SEEWRC_Pos; |
| 554 | } |
| 555 | |
| 556 | static inline void hri_nvmctrl_write_INTEN_SEEWRC_bit(const void *const hw, bool value) |
| 557 | { |
| 558 | if (value == 0x0) { |
| 559 | ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEEWRC; |
| 560 | } else { |
| 561 | ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEEWRC; |
| 562 | } |
| 563 | } |
| 564 | |
| 565 | static inline void hri_nvmctrl_clear_INTEN_SEEWRC_bit(const void *const hw) |
| 566 | { |
| 567 | ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEEWRC; |
| 568 | } |
| 569 | |
| 570 | static inline void hri_nvmctrl_set_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) |
| 571 | { |
| 572 | ((Nvmctrl *)hw)->INTENSET.reg = mask; |
| 573 | } |
| 574 | |
| 575 | static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_get_INTEN_reg(const void *const hw, |
| 576 | hri_nvmctrl_intenset_reg_t mask) |
| 577 | { |
| 578 | uint16_t tmp; |
| 579 | tmp = ((Nvmctrl *)hw)->INTENSET.reg; |
| 580 | tmp &= mask; |
| 581 | return tmp; |
| 582 | } |
| 583 | |
| 584 | static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_read_INTEN_reg(const void *const hw) |
| 585 | { |
| 586 | return ((Nvmctrl *)hw)->INTENSET.reg; |
| 587 | } |
| 588 | |
| 589 | static inline void hri_nvmctrl_write_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t data) |
| 590 | { |
| 591 | ((Nvmctrl *)hw)->INTENSET.reg = data; |
| 592 | ((Nvmctrl *)hw)->INTENCLR.reg = ~data; |
| 593 | } |
| 594 | |
| 595 | static inline void hri_nvmctrl_clear_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) |
| 596 | { |
| 597 | ((Nvmctrl *)hw)->INTENCLR.reg = mask; |
| 598 | } |
| 599 | |
| 600 | static inline bool hri_nvmctrl_get_PARAM_SEE_bit(const void *const hw) |
| 601 | { |
| 602 | return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_SEE) >> NVMCTRL_PARAM_SEE_Pos; |
| 603 | } |
| 604 | |
| 605 | static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) |
| 606 | { |
| 607 | return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP(mask)) >> NVMCTRL_PARAM_NVMP_Pos; |
| 608 | } |
| 609 | |
| 610 | static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_NVMP_bf(const void *const hw) |
| 611 | { |
| 612 | return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos; |
| 613 | } |
| 614 | |
| 615 | static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) |
| 616 | { |
| 617 | return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ(mask)) >> NVMCTRL_PARAM_PSZ_Pos; |
| 618 | } |
| 619 | |
| 620 | static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_PSZ_bf(const void *const hw) |
| 621 | { |
| 622 | return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos; |
| 623 | } |
| 624 | |
| 625 | static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) |
| 626 | { |
| 627 | uint32_t tmp; |
| 628 | tmp = ((Nvmctrl *)hw)->PARAM.reg; |
| 629 | tmp &= mask; |
| 630 | return tmp; |
| 631 | } |
| 632 | |
| 633 | static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_reg(const void *const hw) |
| 634 | { |
| 635 | return ((Nvmctrl *)hw)->PARAM.reg; |
| 636 | } |
| 637 | |
| 638 | static inline bool hri_nvmctrl_get_STATUS_READY_bit(const void *const hw) |
| 639 | { |
| 640 | return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_READY) >> NVMCTRL_STATUS_READY_Pos; |
| 641 | } |
| 642 | |
| 643 | static inline bool hri_nvmctrl_get_STATUS_PRM_bit(const void *const hw) |
| 644 | { |
| 645 | return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PRM) >> NVMCTRL_STATUS_PRM_Pos; |
| 646 | } |
| 647 | |
| 648 | static inline bool hri_nvmctrl_get_STATUS_LOAD_bit(const void *const hw) |
| 649 | { |
| 650 | return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOAD) >> NVMCTRL_STATUS_LOAD_Pos; |
| 651 | } |
| 652 | |
| 653 | static inline bool hri_nvmctrl_get_STATUS_SUSP_bit(const void *const hw) |
| 654 | { |
| 655 | return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_SUSP) >> NVMCTRL_STATUS_SUSP_Pos; |
| 656 | } |
| 657 | |
| 658 | static inline bool hri_nvmctrl_get_STATUS_AFIRST_bit(const void *const hw) |
| 659 | { |
| 660 | return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_AFIRST) >> NVMCTRL_STATUS_AFIRST_Pos; |
| 661 | } |
| 662 | |
| 663 | static inline bool hri_nvmctrl_get_STATUS_BPDIS_bit(const void *const hw) |
| 664 | { |
| 665 | return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BPDIS) >> NVMCTRL_STATUS_BPDIS_Pos; |
| 666 | } |
| 667 | |
| 668 | static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_BOOTPROT_bf(const void *const hw, |
| 669 | hri_nvmctrl_status_reg_t mask) |
| 670 | { |
| 671 | return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BOOTPROT(mask)) >> NVMCTRL_STATUS_BOOTPROT_Pos; |
| 672 | } |
| 673 | |
| 674 | static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_BOOTPROT_bf(const void *const hw) |
| 675 | { |
| 676 | return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BOOTPROT_Msk) >> NVMCTRL_STATUS_BOOTPROT_Pos; |
| 677 | } |
| 678 | |
| 679 | static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask) |
| 680 | { |
| 681 | uint16_t tmp; |
| 682 | tmp = ((Nvmctrl *)hw)->STATUS.reg; |
| 683 | tmp &= mask; |
| 684 | return tmp; |
| 685 | } |
| 686 | |
| 687 | static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_reg(const void *const hw) |
| 688 | { |
| 689 | return ((Nvmctrl *)hw)->STATUS.reg; |
| 690 | } |
| 691 | |
| 692 | static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_get_RUNLOCK_RUNLOCK_bf(const void *const hw, |
| 693 | hri_nvmctrl_runlock_reg_t mask) |
| 694 | { |
| 695 | return (((Nvmctrl *)hw)->RUNLOCK.reg & NVMCTRL_RUNLOCK_RUNLOCK(mask)) >> NVMCTRL_RUNLOCK_RUNLOCK_Pos; |
| 696 | } |
| 697 | |
| 698 | static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_read_RUNLOCK_RUNLOCK_bf(const void *const hw) |
| 699 | { |
| 700 | return (((Nvmctrl *)hw)->RUNLOCK.reg & NVMCTRL_RUNLOCK_RUNLOCK_Msk) >> NVMCTRL_RUNLOCK_RUNLOCK_Pos; |
| 701 | } |
| 702 | |
| 703 | static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_get_RUNLOCK_reg(const void *const hw, |
| 704 | hri_nvmctrl_runlock_reg_t mask) |
| 705 | { |
| 706 | uint32_t tmp; |
| 707 | tmp = ((Nvmctrl *)hw)->RUNLOCK.reg; |
| 708 | tmp &= mask; |
| 709 | return tmp; |
| 710 | } |
| 711 | |
| 712 | static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_read_RUNLOCK_reg(const void *const hw) |
| 713 | { |
| 714 | return ((Nvmctrl *)hw)->RUNLOCK.reg; |
| 715 | } |
| 716 | |
| 717 | static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_get_PBLDATA_DATA_bf(const void *const hw, uint8_t index, |
| 718 | hri_nvmctrl_pbldata_reg_t mask) |
| 719 | { |
| 720 | return (((Nvmctrl *)hw)->PBLDATA[index].reg & NVMCTRL_PBLDATA_DATA(mask)) >> NVMCTRL_PBLDATA_DATA_Pos; |
| 721 | } |
| 722 | |
| 723 | static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_read_PBLDATA_DATA_bf(const void *const hw, uint8_t index) |
| 724 | { |
| 725 | return (((Nvmctrl *)hw)->PBLDATA[index].reg & NVMCTRL_PBLDATA_DATA_Msk) >> NVMCTRL_PBLDATA_DATA_Pos; |
| 726 | } |
| 727 | |
| 728 | static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_get_PBLDATA_reg(const void *const hw, uint8_t index, |
| 729 | hri_nvmctrl_pbldata_reg_t mask) |
| 730 | { |
| 731 | uint32_t tmp; |
| 732 | tmp = ((Nvmctrl *)hw)->PBLDATA[index].reg; |
| 733 | tmp &= mask; |
| 734 | return tmp; |
| 735 | } |
| 736 | |
| 737 | static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_read_PBLDATA_reg(const void *const hw, uint8_t index) |
| 738 | { |
| 739 | return ((Nvmctrl *)hw)->PBLDATA[index].reg; |
| 740 | } |
| 741 | |
| 742 | static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_ADDR_bf(const void *const hw, |
| 743 | hri_nvmctrl_eccerr_reg_t mask) |
| 744 | { |
| 745 | return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_ADDR(mask)) >> NVMCTRL_ECCERR_ADDR_Pos; |
| 746 | } |
| 747 | |
| 748 | static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_ADDR_bf(const void *const hw) |
| 749 | { |
| 750 | return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_ADDR_Msk) >> NVMCTRL_ECCERR_ADDR_Pos; |
| 751 | } |
| 752 | |
| 753 | static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_TYPEL_bf(const void *const hw, |
| 754 | hri_nvmctrl_eccerr_reg_t mask) |
| 755 | { |
| 756 | return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEL(mask)) >> NVMCTRL_ECCERR_TYPEL_Pos; |
| 757 | } |
| 758 | |
| 759 | static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_TYPEL_bf(const void *const hw) |
| 760 | { |
| 761 | return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEL_Msk) >> NVMCTRL_ECCERR_TYPEL_Pos; |
| 762 | } |
| 763 | |
| 764 | static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_TYPEH_bf(const void *const hw, |
| 765 | hri_nvmctrl_eccerr_reg_t mask) |
| 766 | { |
| 767 | return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEH(mask)) >> NVMCTRL_ECCERR_TYPEH_Pos; |
| 768 | } |
| 769 | |
| 770 | static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_TYPEH_bf(const void *const hw) |
| 771 | { |
| 772 | return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEH_Msk) >> NVMCTRL_ECCERR_TYPEH_Pos; |
| 773 | } |
| 774 | |
| 775 | static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_reg(const void *const hw, hri_nvmctrl_eccerr_reg_t mask) |
| 776 | { |
| 777 | uint32_t tmp; |
| 778 | tmp = ((Nvmctrl *)hw)->ECCERR.reg; |
| 779 | tmp &= mask; |
| 780 | return tmp; |
| 781 | } |
| 782 | |
| 783 | static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_reg(const void *const hw) |
| 784 | { |
| 785 | return ((Nvmctrl *)hw)->ECCERR.reg; |
| 786 | } |
| 787 | |
| 788 | static inline bool hri_nvmctrl_get_SEESTAT_ASEES_bit(const void *const hw) |
| 789 | { |
| 790 | return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_ASEES) >> NVMCTRL_SEESTAT_ASEES_Pos; |
| 791 | } |
| 792 | |
| 793 | static inline bool hri_nvmctrl_get_SEESTAT_LOAD_bit(const void *const hw) |
| 794 | { |
| 795 | return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_LOAD) >> NVMCTRL_SEESTAT_LOAD_Pos; |
| 796 | } |
| 797 | |
| 798 | static inline bool hri_nvmctrl_get_SEESTAT_BUSY_bit(const void *const hw) |
| 799 | { |
| 800 | return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_BUSY) >> NVMCTRL_SEESTAT_BUSY_Pos; |
| 801 | } |
| 802 | |
| 803 | static inline bool hri_nvmctrl_get_SEESTAT_LOCK_bit(const void *const hw) |
| 804 | { |
| 805 | return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_LOCK) >> NVMCTRL_SEESTAT_LOCK_Pos; |
| 806 | } |
| 807 | |
| 808 | static inline bool hri_nvmctrl_get_SEESTAT_RLOCK_bit(const void *const hw) |
| 809 | { |
| 810 | return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_RLOCK) >> NVMCTRL_SEESTAT_RLOCK_Pos; |
| 811 | } |
| 812 | |
| 813 | static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_SBLK_bf(const void *const hw, |
| 814 | hri_nvmctrl_seestat_reg_t mask) |
| 815 | { |
| 816 | return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_SBLK(mask)) >> NVMCTRL_SEESTAT_SBLK_Pos; |
| 817 | } |
| 818 | |
| 819 | static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_SBLK_bf(const void *const hw) |
| 820 | { |
| 821 | return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_SBLK_Msk) >> NVMCTRL_SEESTAT_SBLK_Pos; |
| 822 | } |
| 823 | |
| 824 | static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_PSZ_bf(const void *const hw, |
| 825 | hri_nvmctrl_seestat_reg_t mask) |
| 826 | { |
| 827 | return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_PSZ(mask)) >> NVMCTRL_SEESTAT_PSZ_Pos; |
| 828 | } |
| 829 | |
| 830 | static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_PSZ_bf(const void *const hw) |
| 831 | { |
| 832 | return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_PSZ_Msk) >> NVMCTRL_SEESTAT_PSZ_Pos; |
| 833 | } |
| 834 | |
| 835 | static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_reg(const void *const hw, |
| 836 | hri_nvmctrl_seestat_reg_t mask) |
| 837 | { |
| 838 | uint32_t tmp; |
| 839 | tmp = ((Nvmctrl *)hw)->SEESTAT.reg; |
| 840 | tmp &= mask; |
| 841 | return tmp; |
| 842 | } |
| 843 | |
| 844 | static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_reg(const void *const hw) |
| 845 | { |
| 846 | return ((Nvmctrl *)hw)->SEESTAT.reg; |
| 847 | } |
| 848 | |
| 849 | static inline void hri_nvmctrl_set_CTRLA_AUTOWS_bit(const void *const hw) |
| 850 | { |
| 851 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 852 | ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AUTOWS; |
| 853 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 854 | } |
| 855 | |
| 856 | static inline bool hri_nvmctrl_get_CTRLA_AUTOWS_bit(const void *const hw) |
| 857 | { |
| 858 | uint16_t tmp; |
| 859 | tmp = ((Nvmctrl *)hw)->CTRLA.reg; |
| 860 | tmp = (tmp & NVMCTRL_CTRLA_AUTOWS) >> NVMCTRL_CTRLA_AUTOWS_Pos; |
| 861 | return (bool)tmp; |
| 862 | } |
| 863 | |
| 864 | static inline void hri_nvmctrl_write_CTRLA_AUTOWS_bit(const void *const hw, bool value) |
| 865 | { |
| 866 | uint16_t tmp; |
| 867 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 868 | tmp = ((Nvmctrl *)hw)->CTRLA.reg; |
| 869 | tmp &= ~NVMCTRL_CTRLA_AUTOWS; |
| 870 | tmp |= value << NVMCTRL_CTRLA_AUTOWS_Pos; |
| 871 | ((Nvmctrl *)hw)->CTRLA.reg = tmp; |
| 872 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 873 | } |
| 874 | |
| 875 | static inline void hri_nvmctrl_clear_CTRLA_AUTOWS_bit(const void *const hw) |
| 876 | { |
| 877 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 878 | ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AUTOWS; |
| 879 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 880 | } |
| 881 | |
| 882 | static inline void hri_nvmctrl_toggle_CTRLA_AUTOWS_bit(const void *const hw) |
| 883 | { |
| 884 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 885 | ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AUTOWS; |
| 886 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 887 | } |
| 888 | |
| 889 | static inline void hri_nvmctrl_set_CTRLA_SUSPEN_bit(const void *const hw) |
| 890 | { |
| 891 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 892 | ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_SUSPEN; |
| 893 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 894 | } |
| 895 | |
| 896 | static inline bool hri_nvmctrl_get_CTRLA_SUSPEN_bit(const void *const hw) |
| 897 | { |
| 898 | uint16_t tmp; |
| 899 | tmp = ((Nvmctrl *)hw)->CTRLA.reg; |
| 900 | tmp = (tmp & NVMCTRL_CTRLA_SUSPEN) >> NVMCTRL_CTRLA_SUSPEN_Pos; |
| 901 | return (bool)tmp; |
| 902 | } |
| 903 | |
| 904 | static inline void hri_nvmctrl_write_CTRLA_SUSPEN_bit(const void *const hw, bool value) |
| 905 | { |
| 906 | uint16_t tmp; |
| 907 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 908 | tmp = ((Nvmctrl *)hw)->CTRLA.reg; |
| 909 | tmp &= ~NVMCTRL_CTRLA_SUSPEN; |
| 910 | tmp |= value << NVMCTRL_CTRLA_SUSPEN_Pos; |
| 911 | ((Nvmctrl *)hw)->CTRLA.reg = tmp; |
| 912 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 913 | } |
| 914 | |
| 915 | static inline void hri_nvmctrl_clear_CTRLA_SUSPEN_bit(const void *const hw) |
| 916 | { |
| 917 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 918 | ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_SUSPEN; |
| 919 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 920 | } |
| 921 | |
| 922 | static inline void hri_nvmctrl_toggle_CTRLA_SUSPEN_bit(const void *const hw) |
| 923 | { |
| 924 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 925 | ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_SUSPEN; |
| 926 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 927 | } |
| 928 | |
| 929 | static inline void hri_nvmctrl_set_CTRLA_AHBNS0_bit(const void *const hw) |
| 930 | { |
| 931 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 932 | ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AHBNS0; |
| 933 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 934 | } |
| 935 | |
| 936 | static inline bool hri_nvmctrl_get_CTRLA_AHBNS0_bit(const void *const hw) |
| 937 | { |
| 938 | uint16_t tmp; |
| 939 | tmp = ((Nvmctrl *)hw)->CTRLA.reg; |
| 940 | tmp = (tmp & NVMCTRL_CTRLA_AHBNS0) >> NVMCTRL_CTRLA_AHBNS0_Pos; |
| 941 | return (bool)tmp; |
| 942 | } |
| 943 | |
| 944 | static inline void hri_nvmctrl_write_CTRLA_AHBNS0_bit(const void *const hw, bool value) |
| 945 | { |
| 946 | uint16_t tmp; |
| 947 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 948 | tmp = ((Nvmctrl *)hw)->CTRLA.reg; |
| 949 | tmp &= ~NVMCTRL_CTRLA_AHBNS0; |
| 950 | tmp |= value << NVMCTRL_CTRLA_AHBNS0_Pos; |
| 951 | ((Nvmctrl *)hw)->CTRLA.reg = tmp; |
| 952 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 953 | } |
| 954 | |
| 955 | static inline void hri_nvmctrl_clear_CTRLA_AHBNS0_bit(const void *const hw) |
| 956 | { |
| 957 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 958 | ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AHBNS0; |
| 959 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 960 | } |
| 961 | |
| 962 | static inline void hri_nvmctrl_toggle_CTRLA_AHBNS0_bit(const void *const hw) |
| 963 | { |
| 964 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 965 | ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AHBNS0; |
| 966 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 967 | } |
| 968 | |
| 969 | static inline void hri_nvmctrl_set_CTRLA_AHBNS1_bit(const void *const hw) |
| 970 | { |
| 971 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 972 | ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AHBNS1; |
| 973 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 974 | } |
| 975 | |
| 976 | static inline bool hri_nvmctrl_get_CTRLA_AHBNS1_bit(const void *const hw) |
| 977 | { |
| 978 | uint16_t tmp; |
| 979 | tmp = ((Nvmctrl *)hw)->CTRLA.reg; |
| 980 | tmp = (tmp & NVMCTRL_CTRLA_AHBNS1) >> NVMCTRL_CTRLA_AHBNS1_Pos; |
| 981 | return (bool)tmp; |
| 982 | } |
| 983 | |
| 984 | static inline void hri_nvmctrl_write_CTRLA_AHBNS1_bit(const void *const hw, bool value) |
| 985 | { |
| 986 | uint16_t tmp; |
| 987 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 988 | tmp = ((Nvmctrl *)hw)->CTRLA.reg; |
| 989 | tmp &= ~NVMCTRL_CTRLA_AHBNS1; |
| 990 | tmp |= value << NVMCTRL_CTRLA_AHBNS1_Pos; |
| 991 | ((Nvmctrl *)hw)->CTRLA.reg = tmp; |
| 992 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 993 | } |
| 994 | |
| 995 | static inline void hri_nvmctrl_clear_CTRLA_AHBNS1_bit(const void *const hw) |
| 996 | { |
| 997 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 998 | ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AHBNS1; |
| 999 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1000 | } |
| 1001 | |
| 1002 | static inline void hri_nvmctrl_toggle_CTRLA_AHBNS1_bit(const void *const hw) |
| 1003 | { |
| 1004 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1005 | ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AHBNS1; |
| 1006 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1007 | } |
| 1008 | |
| 1009 | static inline void hri_nvmctrl_set_CTRLA_CACHEDIS0_bit(const void *const hw) |
| 1010 | { |
| 1011 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1012 | ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CACHEDIS0; |
| 1013 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1014 | } |
| 1015 | |
| 1016 | static inline bool hri_nvmctrl_get_CTRLA_CACHEDIS0_bit(const void *const hw) |
| 1017 | { |
| 1018 | uint16_t tmp; |
| 1019 | tmp = ((Nvmctrl *)hw)->CTRLA.reg; |
| 1020 | tmp = (tmp & NVMCTRL_CTRLA_CACHEDIS0) >> NVMCTRL_CTRLA_CACHEDIS0_Pos; |
| 1021 | return (bool)tmp; |
| 1022 | } |
| 1023 | |
| 1024 | static inline void hri_nvmctrl_write_CTRLA_CACHEDIS0_bit(const void *const hw, bool value) |
| 1025 | { |
| 1026 | uint16_t tmp; |
| 1027 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1028 | tmp = ((Nvmctrl *)hw)->CTRLA.reg; |
| 1029 | tmp &= ~NVMCTRL_CTRLA_CACHEDIS0; |
| 1030 | tmp |= value << NVMCTRL_CTRLA_CACHEDIS0_Pos; |
| 1031 | ((Nvmctrl *)hw)->CTRLA.reg = tmp; |
| 1032 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1033 | } |
| 1034 | |
| 1035 | static inline void hri_nvmctrl_clear_CTRLA_CACHEDIS0_bit(const void *const hw) |
| 1036 | { |
| 1037 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1038 | ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CACHEDIS0; |
| 1039 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1040 | } |
| 1041 | |
| 1042 | static inline void hri_nvmctrl_toggle_CTRLA_CACHEDIS0_bit(const void *const hw) |
| 1043 | { |
| 1044 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1045 | ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CACHEDIS0; |
| 1046 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1047 | } |
| 1048 | |
| 1049 | static inline void hri_nvmctrl_set_CTRLA_CACHEDIS1_bit(const void *const hw) |
| 1050 | { |
| 1051 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1052 | ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CACHEDIS1; |
| 1053 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1054 | } |
| 1055 | |
| 1056 | static inline bool hri_nvmctrl_get_CTRLA_CACHEDIS1_bit(const void *const hw) |
| 1057 | { |
| 1058 | uint16_t tmp; |
| 1059 | tmp = ((Nvmctrl *)hw)->CTRLA.reg; |
| 1060 | tmp = (tmp & NVMCTRL_CTRLA_CACHEDIS1) >> NVMCTRL_CTRLA_CACHEDIS1_Pos; |
| 1061 | return (bool)tmp; |
| 1062 | } |
| 1063 | |
| 1064 | static inline void hri_nvmctrl_write_CTRLA_CACHEDIS1_bit(const void *const hw, bool value) |
| 1065 | { |
| 1066 | uint16_t tmp; |
| 1067 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1068 | tmp = ((Nvmctrl *)hw)->CTRLA.reg; |
| 1069 | tmp &= ~NVMCTRL_CTRLA_CACHEDIS1; |
| 1070 | tmp |= value << NVMCTRL_CTRLA_CACHEDIS1_Pos; |
| 1071 | ((Nvmctrl *)hw)->CTRLA.reg = tmp; |
| 1072 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1073 | } |
| 1074 | |
| 1075 | static inline void hri_nvmctrl_clear_CTRLA_CACHEDIS1_bit(const void *const hw) |
| 1076 | { |
| 1077 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1078 | ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CACHEDIS1; |
| 1079 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1080 | } |
| 1081 | |
| 1082 | static inline void hri_nvmctrl_toggle_CTRLA_CACHEDIS1_bit(const void *const hw) |
| 1083 | { |
| 1084 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1085 | ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CACHEDIS1; |
| 1086 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1087 | } |
| 1088 | |
| 1089 | static inline void hri_nvmctrl_set_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) |
| 1090 | { |
| 1091 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1092 | ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_WMODE(mask); |
| 1093 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1094 | } |
| 1095 | |
| 1096 | static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) |
| 1097 | { |
| 1098 | uint16_t tmp; |
| 1099 | tmp = ((Nvmctrl *)hw)->CTRLA.reg; |
| 1100 | tmp = (tmp & NVMCTRL_CTRLA_WMODE(mask)) >> NVMCTRL_CTRLA_WMODE_Pos; |
| 1101 | return tmp; |
| 1102 | } |
| 1103 | |
| 1104 | static inline void hri_nvmctrl_write_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) |
| 1105 | { |
| 1106 | uint16_t tmp; |
| 1107 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1108 | tmp = ((Nvmctrl *)hw)->CTRLA.reg; |
| 1109 | tmp &= ~NVMCTRL_CTRLA_WMODE_Msk; |
| 1110 | tmp |= NVMCTRL_CTRLA_WMODE(data); |
| 1111 | ((Nvmctrl *)hw)->CTRLA.reg = tmp; |
| 1112 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1113 | } |
| 1114 | |
| 1115 | static inline void hri_nvmctrl_clear_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) |
| 1116 | { |
| 1117 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1118 | ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_WMODE(mask); |
| 1119 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1120 | } |
| 1121 | |
| 1122 | static inline void hri_nvmctrl_toggle_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) |
| 1123 | { |
| 1124 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1125 | ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_WMODE(mask); |
| 1126 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1127 | } |
| 1128 | |
| 1129 | static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_WMODE_bf(const void *const hw) |
| 1130 | { |
| 1131 | uint16_t tmp; |
| 1132 | tmp = ((Nvmctrl *)hw)->CTRLA.reg; |
| 1133 | tmp = (tmp & NVMCTRL_CTRLA_WMODE_Msk) >> NVMCTRL_CTRLA_WMODE_Pos; |
| 1134 | return tmp; |
| 1135 | } |
| 1136 | |
| 1137 | static inline void hri_nvmctrl_set_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) |
| 1138 | { |
| 1139 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1140 | ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_PRM(mask); |
| 1141 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1142 | } |
| 1143 | |
| 1144 | static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) |
| 1145 | { |
| 1146 | uint16_t tmp; |
| 1147 | tmp = ((Nvmctrl *)hw)->CTRLA.reg; |
| 1148 | tmp = (tmp & NVMCTRL_CTRLA_PRM(mask)) >> NVMCTRL_CTRLA_PRM_Pos; |
| 1149 | return tmp; |
| 1150 | } |
| 1151 | |
| 1152 | static inline void hri_nvmctrl_write_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) |
| 1153 | { |
| 1154 | uint16_t tmp; |
| 1155 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1156 | tmp = ((Nvmctrl *)hw)->CTRLA.reg; |
| 1157 | tmp &= ~NVMCTRL_CTRLA_PRM_Msk; |
| 1158 | tmp |= NVMCTRL_CTRLA_PRM(data); |
| 1159 | ((Nvmctrl *)hw)->CTRLA.reg = tmp; |
| 1160 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1161 | } |
| 1162 | |
| 1163 | static inline void hri_nvmctrl_clear_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) |
| 1164 | { |
| 1165 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1166 | ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_PRM(mask); |
| 1167 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1168 | } |
| 1169 | |
| 1170 | static inline void hri_nvmctrl_toggle_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) |
| 1171 | { |
| 1172 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1173 | ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_PRM(mask); |
| 1174 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1175 | } |
| 1176 | |
| 1177 | static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_PRM_bf(const void *const hw) |
| 1178 | { |
| 1179 | uint16_t tmp; |
| 1180 | tmp = ((Nvmctrl *)hw)->CTRLA.reg; |
| 1181 | tmp = (tmp & NVMCTRL_CTRLA_PRM_Msk) >> NVMCTRL_CTRLA_PRM_Pos; |
| 1182 | return tmp; |
| 1183 | } |
| 1184 | |
| 1185 | static inline void hri_nvmctrl_set_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) |
| 1186 | { |
| 1187 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1188 | ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_RWS(mask); |
| 1189 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1190 | } |
| 1191 | |
| 1192 | static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) |
| 1193 | { |
| 1194 | uint16_t tmp; |
| 1195 | tmp = ((Nvmctrl *)hw)->CTRLA.reg; |
| 1196 | tmp = (tmp & NVMCTRL_CTRLA_RWS(mask)) >> NVMCTRL_CTRLA_RWS_Pos; |
| 1197 | return tmp; |
| 1198 | } |
| 1199 | |
| 1200 | static inline void hri_nvmctrl_write_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) |
| 1201 | { |
| 1202 | uint16_t tmp; |
| 1203 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1204 | tmp = ((Nvmctrl *)hw)->CTRLA.reg; |
| 1205 | tmp &= ~NVMCTRL_CTRLA_RWS_Msk; |
| 1206 | tmp |= NVMCTRL_CTRLA_RWS(data); |
| 1207 | ((Nvmctrl *)hw)->CTRLA.reg = tmp; |
| 1208 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1209 | } |
| 1210 | |
| 1211 | static inline void hri_nvmctrl_clear_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) |
| 1212 | { |
| 1213 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1214 | ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_RWS(mask); |
| 1215 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1216 | } |
| 1217 | |
| 1218 | static inline void hri_nvmctrl_toggle_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) |
| 1219 | { |
| 1220 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1221 | ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_RWS(mask); |
| 1222 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1223 | } |
| 1224 | |
| 1225 | static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_RWS_bf(const void *const hw) |
| 1226 | { |
| 1227 | uint16_t tmp; |
| 1228 | tmp = ((Nvmctrl *)hw)->CTRLA.reg; |
| 1229 | tmp = (tmp & NVMCTRL_CTRLA_RWS_Msk) >> NVMCTRL_CTRLA_RWS_Pos; |
| 1230 | return tmp; |
| 1231 | } |
| 1232 | |
| 1233 | static inline void hri_nvmctrl_set_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) |
| 1234 | { |
| 1235 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1236 | ((Nvmctrl *)hw)->CTRLA.reg |= mask; |
| 1237 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1238 | } |
| 1239 | |
| 1240 | static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) |
| 1241 | { |
| 1242 | uint16_t tmp; |
| 1243 | tmp = ((Nvmctrl *)hw)->CTRLA.reg; |
| 1244 | tmp &= mask; |
| 1245 | return tmp; |
| 1246 | } |
| 1247 | |
| 1248 | static inline void hri_nvmctrl_write_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t data) |
| 1249 | { |
| 1250 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1251 | ((Nvmctrl *)hw)->CTRLA.reg = data; |
| 1252 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1253 | } |
| 1254 | |
| 1255 | static inline void hri_nvmctrl_clear_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) |
| 1256 | { |
| 1257 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1258 | ((Nvmctrl *)hw)->CTRLA.reg &= ~mask; |
| 1259 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1260 | } |
| 1261 | |
| 1262 | static inline void hri_nvmctrl_toggle_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) |
| 1263 | { |
| 1264 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1265 | ((Nvmctrl *)hw)->CTRLA.reg ^= mask; |
| 1266 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1267 | } |
| 1268 | |
| 1269 | static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_reg(const void *const hw) |
| 1270 | { |
| 1271 | return ((Nvmctrl *)hw)->CTRLA.reg; |
| 1272 | } |
| 1273 | |
| 1274 | static inline void hri_nvmctrl_set_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) |
| 1275 | { |
| 1276 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1277 | ((Nvmctrl *)hw)->ADDR.reg |= NVMCTRL_ADDR_ADDR(mask); |
| 1278 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1279 | } |
| 1280 | |
| 1281 | static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) |
| 1282 | { |
| 1283 | uint32_t tmp; |
| 1284 | tmp = ((Nvmctrl *)hw)->ADDR.reg; |
| 1285 | tmp = (tmp & NVMCTRL_ADDR_ADDR(mask)) >> NVMCTRL_ADDR_ADDR_Pos; |
| 1286 | return tmp; |
| 1287 | } |
| 1288 | |
| 1289 | static inline void hri_nvmctrl_write_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t data) |
| 1290 | { |
| 1291 | uint32_t tmp; |
| 1292 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1293 | tmp = ((Nvmctrl *)hw)->ADDR.reg; |
| 1294 | tmp &= ~NVMCTRL_ADDR_ADDR_Msk; |
| 1295 | tmp |= NVMCTRL_ADDR_ADDR(data); |
| 1296 | ((Nvmctrl *)hw)->ADDR.reg = tmp; |
| 1297 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1298 | } |
| 1299 | |
| 1300 | static inline void hri_nvmctrl_clear_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) |
| 1301 | { |
| 1302 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1303 | ((Nvmctrl *)hw)->ADDR.reg &= ~NVMCTRL_ADDR_ADDR(mask); |
| 1304 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1305 | } |
| 1306 | |
| 1307 | static inline void hri_nvmctrl_toggle_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) |
| 1308 | { |
| 1309 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1310 | ((Nvmctrl *)hw)->ADDR.reg ^= NVMCTRL_ADDR_ADDR(mask); |
| 1311 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1312 | } |
| 1313 | |
| 1314 | static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_ADDR_bf(const void *const hw) |
| 1315 | { |
| 1316 | uint32_t tmp; |
| 1317 | tmp = ((Nvmctrl *)hw)->ADDR.reg; |
| 1318 | tmp = (tmp & NVMCTRL_ADDR_ADDR_Msk) >> NVMCTRL_ADDR_ADDR_Pos; |
| 1319 | return tmp; |
| 1320 | } |
| 1321 | |
| 1322 | static inline void hri_nvmctrl_set_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) |
| 1323 | { |
| 1324 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1325 | ((Nvmctrl *)hw)->ADDR.reg |= mask; |
| 1326 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1327 | } |
| 1328 | |
| 1329 | static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) |
| 1330 | { |
| 1331 | uint32_t tmp; |
| 1332 | tmp = ((Nvmctrl *)hw)->ADDR.reg; |
| 1333 | tmp &= mask; |
| 1334 | return tmp; |
| 1335 | } |
| 1336 | |
| 1337 | static inline void hri_nvmctrl_write_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t data) |
| 1338 | { |
| 1339 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1340 | ((Nvmctrl *)hw)->ADDR.reg = data; |
| 1341 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1342 | } |
| 1343 | |
| 1344 | static inline void hri_nvmctrl_clear_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) |
| 1345 | { |
| 1346 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1347 | ((Nvmctrl *)hw)->ADDR.reg &= ~mask; |
| 1348 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1349 | } |
| 1350 | |
| 1351 | static inline void hri_nvmctrl_toggle_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) |
| 1352 | { |
| 1353 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1354 | ((Nvmctrl *)hw)->ADDR.reg ^= mask; |
| 1355 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1356 | } |
| 1357 | |
| 1358 | static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_reg(const void *const hw) |
| 1359 | { |
| 1360 | return ((Nvmctrl *)hw)->ADDR.reg; |
| 1361 | } |
| 1362 | |
| 1363 | static inline void hri_nvmctrl_set_DBGCTRL_ECCDIS_bit(const void *const hw) |
| 1364 | { |
| 1365 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1366 | ((Nvmctrl *)hw)->DBGCTRL.reg |= NVMCTRL_DBGCTRL_ECCDIS; |
| 1367 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1368 | } |
| 1369 | |
| 1370 | static inline bool hri_nvmctrl_get_DBGCTRL_ECCDIS_bit(const void *const hw) |
| 1371 | { |
| 1372 | uint8_t tmp; |
| 1373 | tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; |
| 1374 | tmp = (tmp & NVMCTRL_DBGCTRL_ECCDIS) >> NVMCTRL_DBGCTRL_ECCDIS_Pos; |
| 1375 | return (bool)tmp; |
| 1376 | } |
| 1377 | |
| 1378 | static inline void hri_nvmctrl_write_DBGCTRL_ECCDIS_bit(const void *const hw, bool value) |
| 1379 | { |
| 1380 | uint8_t tmp; |
| 1381 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1382 | tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; |
| 1383 | tmp &= ~NVMCTRL_DBGCTRL_ECCDIS; |
| 1384 | tmp |= value << NVMCTRL_DBGCTRL_ECCDIS_Pos; |
| 1385 | ((Nvmctrl *)hw)->DBGCTRL.reg = tmp; |
| 1386 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1387 | } |
| 1388 | |
| 1389 | static inline void hri_nvmctrl_clear_DBGCTRL_ECCDIS_bit(const void *const hw) |
| 1390 | { |
| 1391 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1392 | ((Nvmctrl *)hw)->DBGCTRL.reg &= ~NVMCTRL_DBGCTRL_ECCDIS; |
| 1393 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1394 | } |
| 1395 | |
| 1396 | static inline void hri_nvmctrl_toggle_DBGCTRL_ECCDIS_bit(const void *const hw) |
| 1397 | { |
| 1398 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1399 | ((Nvmctrl *)hw)->DBGCTRL.reg ^= NVMCTRL_DBGCTRL_ECCDIS; |
| 1400 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1401 | } |
| 1402 | |
| 1403 | static inline void hri_nvmctrl_set_DBGCTRL_ECCELOG_bit(const void *const hw) |
| 1404 | { |
| 1405 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1406 | ((Nvmctrl *)hw)->DBGCTRL.reg |= NVMCTRL_DBGCTRL_ECCELOG; |
| 1407 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1408 | } |
| 1409 | |
| 1410 | static inline bool hri_nvmctrl_get_DBGCTRL_ECCELOG_bit(const void *const hw) |
| 1411 | { |
| 1412 | uint8_t tmp; |
| 1413 | tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; |
| 1414 | tmp = (tmp & NVMCTRL_DBGCTRL_ECCELOG) >> NVMCTRL_DBGCTRL_ECCELOG_Pos; |
| 1415 | return (bool)tmp; |
| 1416 | } |
| 1417 | |
| 1418 | static inline void hri_nvmctrl_write_DBGCTRL_ECCELOG_bit(const void *const hw, bool value) |
| 1419 | { |
| 1420 | uint8_t tmp; |
| 1421 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1422 | tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; |
| 1423 | tmp &= ~NVMCTRL_DBGCTRL_ECCELOG; |
| 1424 | tmp |= value << NVMCTRL_DBGCTRL_ECCELOG_Pos; |
| 1425 | ((Nvmctrl *)hw)->DBGCTRL.reg = tmp; |
| 1426 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1427 | } |
| 1428 | |
| 1429 | static inline void hri_nvmctrl_clear_DBGCTRL_ECCELOG_bit(const void *const hw) |
| 1430 | { |
| 1431 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1432 | ((Nvmctrl *)hw)->DBGCTRL.reg &= ~NVMCTRL_DBGCTRL_ECCELOG; |
| 1433 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1434 | } |
| 1435 | |
| 1436 | static inline void hri_nvmctrl_toggle_DBGCTRL_ECCELOG_bit(const void *const hw) |
| 1437 | { |
| 1438 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1439 | ((Nvmctrl *)hw)->DBGCTRL.reg ^= NVMCTRL_DBGCTRL_ECCELOG; |
| 1440 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1441 | } |
| 1442 | |
| 1443 | static inline void hri_nvmctrl_set_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask) |
| 1444 | { |
| 1445 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1446 | ((Nvmctrl *)hw)->DBGCTRL.reg |= mask; |
| 1447 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1448 | } |
| 1449 | |
| 1450 | static inline hri_nvmctrl_dbgctrl_reg_t hri_nvmctrl_get_DBGCTRL_reg(const void *const hw, |
| 1451 | hri_nvmctrl_dbgctrl_reg_t mask) |
| 1452 | { |
| 1453 | uint8_t tmp; |
| 1454 | tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; |
| 1455 | tmp &= mask; |
| 1456 | return tmp; |
| 1457 | } |
| 1458 | |
| 1459 | static inline void hri_nvmctrl_write_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t data) |
| 1460 | { |
| 1461 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1462 | ((Nvmctrl *)hw)->DBGCTRL.reg = data; |
| 1463 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1464 | } |
| 1465 | |
| 1466 | static inline void hri_nvmctrl_clear_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask) |
| 1467 | { |
| 1468 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1469 | ((Nvmctrl *)hw)->DBGCTRL.reg &= ~mask; |
| 1470 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1471 | } |
| 1472 | |
| 1473 | static inline void hri_nvmctrl_toggle_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask) |
| 1474 | { |
| 1475 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1476 | ((Nvmctrl *)hw)->DBGCTRL.reg ^= mask; |
| 1477 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1478 | } |
| 1479 | |
| 1480 | static inline hri_nvmctrl_dbgctrl_reg_t hri_nvmctrl_read_DBGCTRL_reg(const void *const hw) |
| 1481 | { |
| 1482 | return ((Nvmctrl *)hw)->DBGCTRL.reg; |
| 1483 | } |
| 1484 | |
| 1485 | static inline void hri_nvmctrl_set_SEECFG_WMODE_bit(const void *const hw) |
| 1486 | { |
| 1487 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1488 | ((Nvmctrl *)hw)->SEECFG.reg |= NVMCTRL_SEECFG_WMODE; |
| 1489 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1490 | } |
| 1491 | |
| 1492 | static inline bool hri_nvmctrl_get_SEECFG_WMODE_bit(const void *const hw) |
| 1493 | { |
| 1494 | uint8_t tmp; |
| 1495 | tmp = ((Nvmctrl *)hw)->SEECFG.reg; |
| 1496 | tmp = (tmp & NVMCTRL_SEECFG_WMODE) >> NVMCTRL_SEECFG_WMODE_Pos; |
| 1497 | return (bool)tmp; |
| 1498 | } |
| 1499 | |
| 1500 | static inline void hri_nvmctrl_write_SEECFG_WMODE_bit(const void *const hw, bool value) |
| 1501 | { |
| 1502 | uint8_t tmp; |
| 1503 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1504 | tmp = ((Nvmctrl *)hw)->SEECFG.reg; |
| 1505 | tmp &= ~NVMCTRL_SEECFG_WMODE; |
| 1506 | tmp |= value << NVMCTRL_SEECFG_WMODE_Pos; |
| 1507 | ((Nvmctrl *)hw)->SEECFG.reg = tmp; |
| 1508 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1509 | } |
| 1510 | |
| 1511 | static inline void hri_nvmctrl_clear_SEECFG_WMODE_bit(const void *const hw) |
| 1512 | { |
| 1513 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1514 | ((Nvmctrl *)hw)->SEECFG.reg &= ~NVMCTRL_SEECFG_WMODE; |
| 1515 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1516 | } |
| 1517 | |
| 1518 | static inline void hri_nvmctrl_toggle_SEECFG_WMODE_bit(const void *const hw) |
| 1519 | { |
| 1520 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1521 | ((Nvmctrl *)hw)->SEECFG.reg ^= NVMCTRL_SEECFG_WMODE; |
| 1522 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1523 | } |
| 1524 | |
| 1525 | static inline void hri_nvmctrl_set_SEECFG_APRDIS_bit(const void *const hw) |
| 1526 | { |
| 1527 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1528 | ((Nvmctrl *)hw)->SEECFG.reg |= NVMCTRL_SEECFG_APRDIS; |
| 1529 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1530 | } |
| 1531 | |
| 1532 | static inline bool hri_nvmctrl_get_SEECFG_APRDIS_bit(const void *const hw) |
| 1533 | { |
| 1534 | uint8_t tmp; |
| 1535 | tmp = ((Nvmctrl *)hw)->SEECFG.reg; |
| 1536 | tmp = (tmp & NVMCTRL_SEECFG_APRDIS) >> NVMCTRL_SEECFG_APRDIS_Pos; |
| 1537 | return (bool)tmp; |
| 1538 | } |
| 1539 | |
| 1540 | static inline void hri_nvmctrl_write_SEECFG_APRDIS_bit(const void *const hw, bool value) |
| 1541 | { |
| 1542 | uint8_t tmp; |
| 1543 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1544 | tmp = ((Nvmctrl *)hw)->SEECFG.reg; |
| 1545 | tmp &= ~NVMCTRL_SEECFG_APRDIS; |
| 1546 | tmp |= value << NVMCTRL_SEECFG_APRDIS_Pos; |
| 1547 | ((Nvmctrl *)hw)->SEECFG.reg = tmp; |
| 1548 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1549 | } |
| 1550 | |
| 1551 | static inline void hri_nvmctrl_clear_SEECFG_APRDIS_bit(const void *const hw) |
| 1552 | { |
| 1553 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1554 | ((Nvmctrl *)hw)->SEECFG.reg &= ~NVMCTRL_SEECFG_APRDIS; |
| 1555 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1556 | } |
| 1557 | |
| 1558 | static inline void hri_nvmctrl_toggle_SEECFG_APRDIS_bit(const void *const hw) |
| 1559 | { |
| 1560 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1561 | ((Nvmctrl *)hw)->SEECFG.reg ^= NVMCTRL_SEECFG_APRDIS; |
| 1562 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1563 | } |
| 1564 | |
| 1565 | static inline void hri_nvmctrl_set_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) |
| 1566 | { |
| 1567 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1568 | ((Nvmctrl *)hw)->SEECFG.reg |= mask; |
| 1569 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1570 | } |
| 1571 | |
| 1572 | static inline hri_nvmctrl_seecfg_reg_t hri_nvmctrl_get_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) |
| 1573 | { |
| 1574 | uint8_t tmp; |
| 1575 | tmp = ((Nvmctrl *)hw)->SEECFG.reg; |
| 1576 | tmp &= mask; |
| 1577 | return tmp; |
| 1578 | } |
| 1579 | |
| 1580 | static inline void hri_nvmctrl_write_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t data) |
| 1581 | { |
| 1582 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1583 | ((Nvmctrl *)hw)->SEECFG.reg = data; |
| 1584 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1585 | } |
| 1586 | |
| 1587 | static inline void hri_nvmctrl_clear_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) |
| 1588 | { |
| 1589 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1590 | ((Nvmctrl *)hw)->SEECFG.reg &= ~mask; |
| 1591 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1592 | } |
| 1593 | |
| 1594 | static inline void hri_nvmctrl_toggle_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) |
| 1595 | { |
| 1596 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1597 | ((Nvmctrl *)hw)->SEECFG.reg ^= mask; |
| 1598 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1599 | } |
| 1600 | |
| 1601 | static inline hri_nvmctrl_seecfg_reg_t hri_nvmctrl_read_SEECFG_reg(const void *const hw) |
| 1602 | { |
| 1603 | return ((Nvmctrl *)hw)->SEECFG.reg; |
| 1604 | } |
| 1605 | |
| 1606 | static inline void hri_nvmctrl_write_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) |
| 1607 | { |
| 1608 | NVMCTRL_CRITICAL_SECTION_ENTER(); |
| 1609 | ((Nvmctrl *)hw)->CTRLB.reg = data; |
| 1610 | NVMCTRL_CRITICAL_SECTION_LEAVE(); |
| 1611 | } |
| 1612 | |
| 1613 | #ifdef __cplusplus |
| 1614 | } |
| 1615 | #endif |
| 1616 | |
| 1617 | #endif /* _HRI_NVMCTRL_E54_H_INCLUDED */ |
| 1618 | #endif /* _SAME54_NVMCTRL_COMPONENT_ */ |