Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM EVSYS |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_EVSYS_COMPONENT_ |
| 35 | #ifndef _HRI_EVSYS_E54_H_INCLUDED_ |
| 36 | #define _HRI_EVSYS_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_EVSYS_CRITICAL_SECTIONS) |
| 46 | #define EVSYS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define EVSYS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define EVSYS_CRITICAL_SECTION_ENTER() |
| 50 | #define EVSYS_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint16_t hri_evsys_intpend_reg_t; |
| 54 | typedef uint32_t hri_evsys_busych_reg_t; |
| 55 | typedef uint32_t hri_evsys_channel_reg_t; |
| 56 | typedef uint32_t hri_evsys_intstatus_reg_t; |
| 57 | typedef uint32_t hri_evsys_readyusr_reg_t; |
| 58 | typedef uint32_t hri_evsys_swevt_reg_t; |
| 59 | typedef uint32_t hri_evsys_user_reg_t; |
| 60 | typedef uint32_t hri_evsyschannel_channel_reg_t; |
| 61 | typedef uint8_t hri_evsys_chintenset_reg_t; |
| 62 | typedef uint8_t hri_evsys_chintflag_reg_t; |
| 63 | typedef uint8_t hri_evsys_chstatus_reg_t; |
| 64 | typedef uint8_t hri_evsys_ctrla_reg_t; |
| 65 | typedef uint8_t hri_evsys_prictrl_reg_t; |
| 66 | typedef uint8_t hri_evsyschannel_chintenset_reg_t; |
| 67 | typedef uint8_t hri_evsyschannel_chintflag_reg_t; |
| 68 | typedef uint8_t hri_evsyschannel_chstatus_reg_t; |
| 69 | |
| 70 | static inline bool hri_evsys_get_INTSTATUS_CHINT0_bit(const void *const hw) |
| 71 | { |
| 72 | return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT0) >> EVSYS_INTSTATUS_CHINT0_Pos; |
| 73 | } |
| 74 | |
| 75 | static inline bool hri_evsys_get_INTSTATUS_CHINT1_bit(const void *const hw) |
| 76 | { |
| 77 | return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT1) >> EVSYS_INTSTATUS_CHINT1_Pos; |
| 78 | } |
| 79 | |
| 80 | static inline bool hri_evsys_get_INTSTATUS_CHINT2_bit(const void *const hw) |
| 81 | { |
| 82 | return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT2) >> EVSYS_INTSTATUS_CHINT2_Pos; |
| 83 | } |
| 84 | |
| 85 | static inline bool hri_evsys_get_INTSTATUS_CHINT3_bit(const void *const hw) |
| 86 | { |
| 87 | return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT3) >> EVSYS_INTSTATUS_CHINT3_Pos; |
| 88 | } |
| 89 | |
| 90 | static inline bool hri_evsys_get_INTSTATUS_CHINT4_bit(const void *const hw) |
| 91 | { |
| 92 | return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT4) >> EVSYS_INTSTATUS_CHINT4_Pos; |
| 93 | } |
| 94 | |
| 95 | static inline bool hri_evsys_get_INTSTATUS_CHINT5_bit(const void *const hw) |
| 96 | { |
| 97 | return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT5) >> EVSYS_INTSTATUS_CHINT5_Pos; |
| 98 | } |
| 99 | |
| 100 | static inline bool hri_evsys_get_INTSTATUS_CHINT6_bit(const void *const hw) |
| 101 | { |
| 102 | return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT6) >> EVSYS_INTSTATUS_CHINT6_Pos; |
| 103 | } |
| 104 | |
| 105 | static inline bool hri_evsys_get_INTSTATUS_CHINT7_bit(const void *const hw) |
| 106 | { |
| 107 | return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT7) >> EVSYS_INTSTATUS_CHINT7_Pos; |
| 108 | } |
| 109 | |
| 110 | static inline bool hri_evsys_get_INTSTATUS_CHINT8_bit(const void *const hw) |
| 111 | { |
| 112 | return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT8) >> EVSYS_INTSTATUS_CHINT8_Pos; |
| 113 | } |
| 114 | |
| 115 | static inline bool hri_evsys_get_INTSTATUS_CHINT9_bit(const void *const hw) |
| 116 | { |
| 117 | return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT9) >> EVSYS_INTSTATUS_CHINT9_Pos; |
| 118 | } |
| 119 | |
| 120 | static inline bool hri_evsys_get_INTSTATUS_CHINT10_bit(const void *const hw) |
| 121 | { |
| 122 | return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT10) >> EVSYS_INTSTATUS_CHINT10_Pos; |
| 123 | } |
| 124 | |
| 125 | static inline bool hri_evsys_get_INTSTATUS_CHINT11_bit(const void *const hw) |
| 126 | { |
| 127 | return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT11) >> EVSYS_INTSTATUS_CHINT11_Pos; |
| 128 | } |
| 129 | |
| 130 | static inline hri_evsys_intstatus_reg_t hri_evsys_get_INTSTATUS_reg(const void *const hw, |
| 131 | hri_evsys_intstatus_reg_t mask) |
| 132 | { |
| 133 | uint32_t tmp; |
| 134 | tmp = ((Evsys *)hw)->INTSTATUS.reg; |
| 135 | tmp &= mask; |
| 136 | return tmp; |
| 137 | } |
| 138 | |
| 139 | static inline hri_evsys_intstatus_reg_t hri_evsys_read_INTSTATUS_reg(const void *const hw) |
| 140 | { |
| 141 | return ((Evsys *)hw)->INTSTATUS.reg; |
| 142 | } |
| 143 | |
| 144 | static inline bool hri_evsys_get_BUSYCH_BUSYCH0_bit(const void *const hw) |
| 145 | { |
| 146 | return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH0) >> EVSYS_BUSYCH_BUSYCH0_Pos; |
| 147 | } |
| 148 | |
| 149 | static inline bool hri_evsys_get_BUSYCH_BUSYCH1_bit(const void *const hw) |
| 150 | { |
| 151 | return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH1) >> EVSYS_BUSYCH_BUSYCH1_Pos; |
| 152 | } |
| 153 | |
| 154 | static inline bool hri_evsys_get_BUSYCH_BUSYCH2_bit(const void *const hw) |
| 155 | { |
| 156 | return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH2) >> EVSYS_BUSYCH_BUSYCH2_Pos; |
| 157 | } |
| 158 | |
| 159 | static inline bool hri_evsys_get_BUSYCH_BUSYCH3_bit(const void *const hw) |
| 160 | { |
| 161 | return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH3) >> EVSYS_BUSYCH_BUSYCH3_Pos; |
| 162 | } |
| 163 | |
| 164 | static inline bool hri_evsys_get_BUSYCH_BUSYCH4_bit(const void *const hw) |
| 165 | { |
| 166 | return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH4) >> EVSYS_BUSYCH_BUSYCH4_Pos; |
| 167 | } |
| 168 | |
| 169 | static inline bool hri_evsys_get_BUSYCH_BUSYCH5_bit(const void *const hw) |
| 170 | { |
| 171 | return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH5) >> EVSYS_BUSYCH_BUSYCH5_Pos; |
| 172 | } |
| 173 | |
| 174 | static inline bool hri_evsys_get_BUSYCH_BUSYCH6_bit(const void *const hw) |
| 175 | { |
| 176 | return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH6) >> EVSYS_BUSYCH_BUSYCH6_Pos; |
| 177 | } |
| 178 | |
| 179 | static inline bool hri_evsys_get_BUSYCH_BUSYCH7_bit(const void *const hw) |
| 180 | { |
| 181 | return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH7) >> EVSYS_BUSYCH_BUSYCH7_Pos; |
| 182 | } |
| 183 | |
| 184 | static inline bool hri_evsys_get_BUSYCH_BUSYCH8_bit(const void *const hw) |
| 185 | { |
| 186 | return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH8) >> EVSYS_BUSYCH_BUSYCH8_Pos; |
| 187 | } |
| 188 | |
| 189 | static inline bool hri_evsys_get_BUSYCH_BUSYCH9_bit(const void *const hw) |
| 190 | { |
| 191 | return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH9) >> EVSYS_BUSYCH_BUSYCH9_Pos; |
| 192 | } |
| 193 | |
| 194 | static inline bool hri_evsys_get_BUSYCH_BUSYCH10_bit(const void *const hw) |
| 195 | { |
| 196 | return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH10) >> EVSYS_BUSYCH_BUSYCH10_Pos; |
| 197 | } |
| 198 | |
| 199 | static inline bool hri_evsys_get_BUSYCH_BUSYCH11_bit(const void *const hw) |
| 200 | { |
| 201 | return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH11) >> EVSYS_BUSYCH_BUSYCH11_Pos; |
| 202 | } |
| 203 | |
| 204 | static inline hri_evsys_busych_reg_t hri_evsys_get_BUSYCH_reg(const void *const hw, hri_evsys_busych_reg_t mask) |
| 205 | { |
| 206 | uint32_t tmp; |
| 207 | tmp = ((Evsys *)hw)->BUSYCH.reg; |
| 208 | tmp &= mask; |
| 209 | return tmp; |
| 210 | } |
| 211 | |
| 212 | static inline hri_evsys_busych_reg_t hri_evsys_read_BUSYCH_reg(const void *const hw) |
| 213 | { |
| 214 | return ((Evsys *)hw)->BUSYCH.reg; |
| 215 | } |
| 216 | |
| 217 | static inline bool hri_evsys_get_READYUSR_READYUSR0_bit(const void *const hw) |
| 218 | { |
| 219 | return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR0) >> EVSYS_READYUSR_READYUSR0_Pos; |
| 220 | } |
| 221 | |
| 222 | static inline bool hri_evsys_get_READYUSR_READYUSR1_bit(const void *const hw) |
| 223 | { |
| 224 | return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR1) >> EVSYS_READYUSR_READYUSR1_Pos; |
| 225 | } |
| 226 | |
| 227 | static inline bool hri_evsys_get_READYUSR_READYUSR2_bit(const void *const hw) |
| 228 | { |
| 229 | return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR2) >> EVSYS_READYUSR_READYUSR2_Pos; |
| 230 | } |
| 231 | |
| 232 | static inline bool hri_evsys_get_READYUSR_READYUSR3_bit(const void *const hw) |
| 233 | { |
| 234 | return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR3) >> EVSYS_READYUSR_READYUSR3_Pos; |
| 235 | } |
| 236 | |
| 237 | static inline bool hri_evsys_get_READYUSR_READYUSR4_bit(const void *const hw) |
| 238 | { |
| 239 | return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR4) >> EVSYS_READYUSR_READYUSR4_Pos; |
| 240 | } |
| 241 | |
| 242 | static inline bool hri_evsys_get_READYUSR_READYUSR5_bit(const void *const hw) |
| 243 | { |
| 244 | return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR5) >> EVSYS_READYUSR_READYUSR5_Pos; |
| 245 | } |
| 246 | |
| 247 | static inline bool hri_evsys_get_READYUSR_READYUSR6_bit(const void *const hw) |
| 248 | { |
| 249 | return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR6) >> EVSYS_READYUSR_READYUSR6_Pos; |
| 250 | } |
| 251 | |
| 252 | static inline bool hri_evsys_get_READYUSR_READYUSR7_bit(const void *const hw) |
| 253 | { |
| 254 | return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR7) >> EVSYS_READYUSR_READYUSR7_Pos; |
| 255 | } |
| 256 | |
| 257 | static inline bool hri_evsys_get_READYUSR_READYUSR8_bit(const void *const hw) |
| 258 | { |
| 259 | return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR8) >> EVSYS_READYUSR_READYUSR8_Pos; |
| 260 | } |
| 261 | |
| 262 | static inline bool hri_evsys_get_READYUSR_READYUSR9_bit(const void *const hw) |
| 263 | { |
| 264 | return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR9) >> EVSYS_READYUSR_READYUSR9_Pos; |
| 265 | } |
| 266 | |
| 267 | static inline bool hri_evsys_get_READYUSR_READYUSR10_bit(const void *const hw) |
| 268 | { |
| 269 | return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR10) >> EVSYS_READYUSR_READYUSR10_Pos; |
| 270 | } |
| 271 | |
| 272 | static inline bool hri_evsys_get_READYUSR_READYUSR11_bit(const void *const hw) |
| 273 | { |
| 274 | return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR11) >> EVSYS_READYUSR_READYUSR11_Pos; |
| 275 | } |
| 276 | |
| 277 | static inline hri_evsys_readyusr_reg_t hri_evsys_get_READYUSR_reg(const void *const hw, hri_evsys_readyusr_reg_t mask) |
| 278 | { |
| 279 | uint32_t tmp; |
| 280 | tmp = ((Evsys *)hw)->READYUSR.reg; |
| 281 | tmp &= mask; |
| 282 | return tmp; |
| 283 | } |
| 284 | |
| 285 | static inline hri_evsys_readyusr_reg_t hri_evsys_read_READYUSR_reg(const void *const hw) |
| 286 | { |
| 287 | return ((Evsys *)hw)->READYUSR.reg; |
| 288 | } |
| 289 | |
| 290 | static inline void hri_evsys_set_CTRLA_SWRST_bit(const void *const hw) |
| 291 | { |
| 292 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 293 | ((Evsys *)hw)->CTRLA.reg |= EVSYS_CTRLA_SWRST; |
| 294 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 295 | } |
| 296 | |
| 297 | static inline bool hri_evsys_get_CTRLA_SWRST_bit(const void *const hw) |
| 298 | { |
| 299 | uint8_t tmp; |
| 300 | tmp = ((Evsys *)hw)->CTRLA.reg; |
| 301 | tmp = (tmp & EVSYS_CTRLA_SWRST) >> EVSYS_CTRLA_SWRST_Pos; |
| 302 | return (bool)tmp; |
| 303 | } |
| 304 | |
| 305 | static inline void hri_evsys_set_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) |
| 306 | { |
| 307 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 308 | ((Evsys *)hw)->CTRLA.reg |= mask; |
| 309 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 310 | } |
| 311 | |
| 312 | static inline hri_evsys_ctrla_reg_t hri_evsys_get_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) |
| 313 | { |
| 314 | uint8_t tmp; |
| 315 | tmp = ((Evsys *)hw)->CTRLA.reg; |
| 316 | tmp &= mask; |
| 317 | return tmp; |
| 318 | } |
| 319 | |
| 320 | static inline void hri_evsys_write_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t data) |
| 321 | { |
| 322 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 323 | ((Evsys *)hw)->CTRLA.reg = data; |
| 324 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 325 | } |
| 326 | |
| 327 | static inline void hri_evsys_clear_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) |
| 328 | { |
| 329 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 330 | ((Evsys *)hw)->CTRLA.reg &= ~mask; |
| 331 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 332 | } |
| 333 | |
| 334 | static inline void hri_evsys_toggle_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) |
| 335 | { |
| 336 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 337 | ((Evsys *)hw)->CTRLA.reg ^= mask; |
| 338 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 339 | } |
| 340 | |
| 341 | static inline hri_evsys_ctrla_reg_t hri_evsys_read_CTRLA_reg(const void *const hw) |
| 342 | { |
| 343 | return ((Evsys *)hw)->CTRLA.reg; |
| 344 | } |
| 345 | |
| 346 | static inline void hri_evsys_set_PRICTRL_RREN_bit(const void *const hw) |
| 347 | { |
| 348 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 349 | ((Evsys *)hw)->PRICTRL.reg |= EVSYS_PRICTRL_RREN; |
| 350 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 351 | } |
| 352 | |
| 353 | static inline bool hri_evsys_get_PRICTRL_RREN_bit(const void *const hw) |
| 354 | { |
| 355 | uint8_t tmp; |
| 356 | tmp = ((Evsys *)hw)->PRICTRL.reg; |
| 357 | tmp = (tmp & EVSYS_PRICTRL_RREN) >> EVSYS_PRICTRL_RREN_Pos; |
| 358 | return (bool)tmp; |
| 359 | } |
| 360 | |
| 361 | static inline void hri_evsys_write_PRICTRL_RREN_bit(const void *const hw, bool value) |
| 362 | { |
| 363 | uint8_t tmp; |
| 364 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 365 | tmp = ((Evsys *)hw)->PRICTRL.reg; |
| 366 | tmp &= ~EVSYS_PRICTRL_RREN; |
| 367 | tmp |= value << EVSYS_PRICTRL_RREN_Pos; |
| 368 | ((Evsys *)hw)->PRICTRL.reg = tmp; |
| 369 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 370 | } |
| 371 | |
| 372 | static inline void hri_evsys_clear_PRICTRL_RREN_bit(const void *const hw) |
| 373 | { |
| 374 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 375 | ((Evsys *)hw)->PRICTRL.reg &= ~EVSYS_PRICTRL_RREN; |
| 376 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 377 | } |
| 378 | |
| 379 | static inline void hri_evsys_toggle_PRICTRL_RREN_bit(const void *const hw) |
| 380 | { |
| 381 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 382 | ((Evsys *)hw)->PRICTRL.reg ^= EVSYS_PRICTRL_RREN; |
| 383 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 384 | } |
| 385 | |
| 386 | static inline void hri_evsys_set_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) |
| 387 | { |
| 388 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 389 | ((Evsys *)hw)->PRICTRL.reg |= EVSYS_PRICTRL_PRI(mask); |
| 390 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 391 | } |
| 392 | |
| 393 | static inline hri_evsys_prictrl_reg_t hri_evsys_get_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) |
| 394 | { |
| 395 | uint8_t tmp; |
| 396 | tmp = ((Evsys *)hw)->PRICTRL.reg; |
| 397 | tmp = (tmp & EVSYS_PRICTRL_PRI(mask)) >> EVSYS_PRICTRL_PRI_Pos; |
| 398 | return tmp; |
| 399 | } |
| 400 | |
| 401 | static inline void hri_evsys_write_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t data) |
| 402 | { |
| 403 | uint8_t tmp; |
| 404 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 405 | tmp = ((Evsys *)hw)->PRICTRL.reg; |
| 406 | tmp &= ~EVSYS_PRICTRL_PRI_Msk; |
| 407 | tmp |= EVSYS_PRICTRL_PRI(data); |
| 408 | ((Evsys *)hw)->PRICTRL.reg = tmp; |
| 409 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 410 | } |
| 411 | |
| 412 | static inline void hri_evsys_clear_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) |
| 413 | { |
| 414 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 415 | ((Evsys *)hw)->PRICTRL.reg &= ~EVSYS_PRICTRL_PRI(mask); |
| 416 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 417 | } |
| 418 | |
| 419 | static inline void hri_evsys_toggle_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) |
| 420 | { |
| 421 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 422 | ((Evsys *)hw)->PRICTRL.reg ^= EVSYS_PRICTRL_PRI(mask); |
| 423 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 424 | } |
| 425 | |
| 426 | static inline hri_evsys_prictrl_reg_t hri_evsys_read_PRICTRL_PRI_bf(const void *const hw) |
| 427 | { |
| 428 | uint8_t tmp; |
| 429 | tmp = ((Evsys *)hw)->PRICTRL.reg; |
| 430 | tmp = (tmp & EVSYS_PRICTRL_PRI_Msk) >> EVSYS_PRICTRL_PRI_Pos; |
| 431 | return tmp; |
| 432 | } |
| 433 | |
| 434 | static inline void hri_evsys_set_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) |
| 435 | { |
| 436 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 437 | ((Evsys *)hw)->PRICTRL.reg |= mask; |
| 438 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 439 | } |
| 440 | |
| 441 | static inline hri_evsys_prictrl_reg_t hri_evsys_get_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) |
| 442 | { |
| 443 | uint8_t tmp; |
| 444 | tmp = ((Evsys *)hw)->PRICTRL.reg; |
| 445 | tmp &= mask; |
| 446 | return tmp; |
| 447 | } |
| 448 | |
| 449 | static inline void hri_evsys_write_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t data) |
| 450 | { |
| 451 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 452 | ((Evsys *)hw)->PRICTRL.reg = data; |
| 453 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 454 | } |
| 455 | |
| 456 | static inline void hri_evsys_clear_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) |
| 457 | { |
| 458 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 459 | ((Evsys *)hw)->PRICTRL.reg &= ~mask; |
| 460 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 461 | } |
| 462 | |
| 463 | static inline void hri_evsys_toggle_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) |
| 464 | { |
| 465 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 466 | ((Evsys *)hw)->PRICTRL.reg ^= mask; |
| 467 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 468 | } |
| 469 | |
| 470 | static inline hri_evsys_prictrl_reg_t hri_evsys_read_PRICTRL_reg(const void *const hw) |
| 471 | { |
| 472 | return ((Evsys *)hw)->PRICTRL.reg; |
| 473 | } |
| 474 | |
| 475 | static inline void hri_evsys_set_INTPEND_OVR_bit(const void *const hw) |
| 476 | { |
| 477 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 478 | ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_OVR; |
| 479 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 480 | } |
| 481 | |
| 482 | static inline bool hri_evsys_get_INTPEND_OVR_bit(const void *const hw) |
| 483 | { |
| 484 | uint16_t tmp; |
| 485 | tmp = ((Evsys *)hw)->INTPEND.reg; |
| 486 | tmp = (tmp & EVSYS_INTPEND_OVR) >> EVSYS_INTPEND_OVR_Pos; |
| 487 | return (bool)tmp; |
| 488 | } |
| 489 | |
| 490 | static inline void hri_evsys_write_INTPEND_OVR_bit(const void *const hw, bool value) |
| 491 | { |
| 492 | uint16_t tmp; |
| 493 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 494 | tmp = ((Evsys *)hw)->INTPEND.reg; |
| 495 | tmp &= ~EVSYS_INTPEND_OVR; |
| 496 | tmp |= value << EVSYS_INTPEND_OVR_Pos; |
| 497 | ((Evsys *)hw)->INTPEND.reg = tmp; |
| 498 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 499 | } |
| 500 | |
| 501 | static inline void hri_evsys_clear_INTPEND_OVR_bit(const void *const hw) |
| 502 | { |
| 503 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 504 | ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_OVR; |
| 505 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 506 | } |
| 507 | |
| 508 | static inline void hri_evsys_toggle_INTPEND_OVR_bit(const void *const hw) |
| 509 | { |
| 510 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 511 | ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_OVR; |
| 512 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 513 | } |
| 514 | |
| 515 | static inline void hri_evsys_set_INTPEND_EVD_bit(const void *const hw) |
| 516 | { |
| 517 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 518 | ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_EVD; |
| 519 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 520 | } |
| 521 | |
| 522 | static inline bool hri_evsys_get_INTPEND_EVD_bit(const void *const hw) |
| 523 | { |
| 524 | uint16_t tmp; |
| 525 | tmp = ((Evsys *)hw)->INTPEND.reg; |
| 526 | tmp = (tmp & EVSYS_INTPEND_EVD) >> EVSYS_INTPEND_EVD_Pos; |
| 527 | return (bool)tmp; |
| 528 | } |
| 529 | |
| 530 | static inline void hri_evsys_write_INTPEND_EVD_bit(const void *const hw, bool value) |
| 531 | { |
| 532 | uint16_t tmp; |
| 533 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 534 | tmp = ((Evsys *)hw)->INTPEND.reg; |
| 535 | tmp &= ~EVSYS_INTPEND_EVD; |
| 536 | tmp |= value << EVSYS_INTPEND_EVD_Pos; |
| 537 | ((Evsys *)hw)->INTPEND.reg = tmp; |
| 538 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 539 | } |
| 540 | |
| 541 | static inline void hri_evsys_clear_INTPEND_EVD_bit(const void *const hw) |
| 542 | { |
| 543 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 544 | ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_EVD; |
| 545 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 546 | } |
| 547 | |
| 548 | static inline void hri_evsys_toggle_INTPEND_EVD_bit(const void *const hw) |
| 549 | { |
| 550 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 551 | ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_EVD; |
| 552 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 553 | } |
| 554 | |
| 555 | static inline void hri_evsys_set_INTPEND_READY_bit(const void *const hw) |
| 556 | { |
| 557 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 558 | ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_READY; |
| 559 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 560 | } |
| 561 | |
| 562 | static inline bool hri_evsys_get_INTPEND_READY_bit(const void *const hw) |
| 563 | { |
| 564 | uint16_t tmp; |
| 565 | tmp = ((Evsys *)hw)->INTPEND.reg; |
| 566 | tmp = (tmp & EVSYS_INTPEND_READY) >> EVSYS_INTPEND_READY_Pos; |
| 567 | return (bool)tmp; |
| 568 | } |
| 569 | |
| 570 | static inline void hri_evsys_write_INTPEND_READY_bit(const void *const hw, bool value) |
| 571 | { |
| 572 | uint16_t tmp; |
| 573 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 574 | tmp = ((Evsys *)hw)->INTPEND.reg; |
| 575 | tmp &= ~EVSYS_INTPEND_READY; |
| 576 | tmp |= value << EVSYS_INTPEND_READY_Pos; |
| 577 | ((Evsys *)hw)->INTPEND.reg = tmp; |
| 578 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 579 | } |
| 580 | |
| 581 | static inline void hri_evsys_clear_INTPEND_READY_bit(const void *const hw) |
| 582 | { |
| 583 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 584 | ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_READY; |
| 585 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 586 | } |
| 587 | |
| 588 | static inline void hri_evsys_toggle_INTPEND_READY_bit(const void *const hw) |
| 589 | { |
| 590 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 591 | ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_READY; |
| 592 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 593 | } |
| 594 | |
| 595 | static inline void hri_evsys_set_INTPEND_BUSY_bit(const void *const hw) |
| 596 | { |
| 597 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 598 | ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_BUSY; |
| 599 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 600 | } |
| 601 | |
| 602 | static inline bool hri_evsys_get_INTPEND_BUSY_bit(const void *const hw) |
| 603 | { |
| 604 | uint16_t tmp; |
| 605 | tmp = ((Evsys *)hw)->INTPEND.reg; |
| 606 | tmp = (tmp & EVSYS_INTPEND_BUSY) >> EVSYS_INTPEND_BUSY_Pos; |
| 607 | return (bool)tmp; |
| 608 | } |
| 609 | |
| 610 | static inline void hri_evsys_write_INTPEND_BUSY_bit(const void *const hw, bool value) |
| 611 | { |
| 612 | uint16_t tmp; |
| 613 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 614 | tmp = ((Evsys *)hw)->INTPEND.reg; |
| 615 | tmp &= ~EVSYS_INTPEND_BUSY; |
| 616 | tmp |= value << EVSYS_INTPEND_BUSY_Pos; |
| 617 | ((Evsys *)hw)->INTPEND.reg = tmp; |
| 618 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 619 | } |
| 620 | |
| 621 | static inline void hri_evsys_clear_INTPEND_BUSY_bit(const void *const hw) |
| 622 | { |
| 623 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 624 | ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_BUSY; |
| 625 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 626 | } |
| 627 | |
| 628 | static inline void hri_evsys_toggle_INTPEND_BUSY_bit(const void *const hw) |
| 629 | { |
| 630 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 631 | ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_BUSY; |
| 632 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 633 | } |
| 634 | |
| 635 | static inline void hri_evsys_set_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) |
| 636 | { |
| 637 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 638 | ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_ID(mask); |
| 639 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 640 | } |
| 641 | |
| 642 | static inline hri_evsys_intpend_reg_t hri_evsys_get_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) |
| 643 | { |
| 644 | uint16_t tmp; |
| 645 | tmp = ((Evsys *)hw)->INTPEND.reg; |
| 646 | tmp = (tmp & EVSYS_INTPEND_ID(mask)) >> EVSYS_INTPEND_ID_Pos; |
| 647 | return tmp; |
| 648 | } |
| 649 | |
| 650 | static inline void hri_evsys_write_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t data) |
| 651 | { |
| 652 | uint16_t tmp; |
| 653 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 654 | tmp = ((Evsys *)hw)->INTPEND.reg; |
| 655 | tmp &= ~EVSYS_INTPEND_ID_Msk; |
| 656 | tmp |= EVSYS_INTPEND_ID(data); |
| 657 | ((Evsys *)hw)->INTPEND.reg = tmp; |
| 658 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 659 | } |
| 660 | |
| 661 | static inline void hri_evsys_clear_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) |
| 662 | { |
| 663 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 664 | ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_ID(mask); |
| 665 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 666 | } |
| 667 | |
| 668 | static inline void hri_evsys_toggle_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) |
| 669 | { |
| 670 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 671 | ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_ID(mask); |
| 672 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 673 | } |
| 674 | |
| 675 | static inline hri_evsys_intpend_reg_t hri_evsys_read_INTPEND_ID_bf(const void *const hw) |
| 676 | { |
| 677 | uint16_t tmp; |
| 678 | tmp = ((Evsys *)hw)->INTPEND.reg; |
| 679 | tmp = (tmp & EVSYS_INTPEND_ID_Msk) >> EVSYS_INTPEND_ID_Pos; |
| 680 | return tmp; |
| 681 | } |
| 682 | |
| 683 | static inline void hri_evsys_set_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) |
| 684 | { |
| 685 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 686 | ((Evsys *)hw)->INTPEND.reg |= mask; |
| 687 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 688 | } |
| 689 | |
| 690 | static inline hri_evsys_intpend_reg_t hri_evsys_get_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) |
| 691 | { |
| 692 | uint16_t tmp; |
| 693 | tmp = ((Evsys *)hw)->INTPEND.reg; |
| 694 | tmp &= mask; |
| 695 | return tmp; |
| 696 | } |
| 697 | |
| 698 | static inline void hri_evsys_write_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t data) |
| 699 | { |
| 700 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 701 | ((Evsys *)hw)->INTPEND.reg = data; |
| 702 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 703 | } |
| 704 | |
| 705 | static inline void hri_evsys_clear_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) |
| 706 | { |
| 707 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 708 | ((Evsys *)hw)->INTPEND.reg &= ~mask; |
| 709 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 710 | } |
| 711 | |
| 712 | static inline void hri_evsys_toggle_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) |
| 713 | { |
| 714 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 715 | ((Evsys *)hw)->INTPEND.reg ^= mask; |
| 716 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 717 | } |
| 718 | |
| 719 | static inline hri_evsys_intpend_reg_t hri_evsys_read_INTPEND_reg(const void *const hw) |
| 720 | { |
| 721 | return ((Evsys *)hw)->INTPEND.reg; |
| 722 | } |
| 723 | |
| 724 | static inline void hri_evsys_set_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) |
| 725 | { |
| 726 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 727 | ((Evsys *)hw)->USER[index].reg |= EVSYS_USER_CHANNEL(mask); |
| 728 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 729 | } |
| 730 | |
| 731 | static inline hri_evsys_user_reg_t hri_evsys_get_USER_CHANNEL_bf(const void *const hw, uint8_t index, |
| 732 | hri_evsys_user_reg_t mask) |
| 733 | { |
| 734 | uint32_t tmp; |
| 735 | tmp = ((Evsys *)hw)->USER[index].reg; |
| 736 | tmp = (tmp & EVSYS_USER_CHANNEL(mask)) >> EVSYS_USER_CHANNEL_Pos; |
| 737 | return tmp; |
| 738 | } |
| 739 | |
| 740 | static inline void hri_evsys_write_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) |
| 741 | { |
| 742 | uint32_t tmp; |
| 743 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 744 | tmp = ((Evsys *)hw)->USER[index].reg; |
| 745 | tmp &= ~EVSYS_USER_CHANNEL_Msk; |
| 746 | tmp |= EVSYS_USER_CHANNEL(data); |
| 747 | ((Evsys *)hw)->USER[index].reg = tmp; |
| 748 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 749 | } |
| 750 | |
| 751 | static inline void hri_evsys_clear_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) |
| 752 | { |
| 753 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 754 | ((Evsys *)hw)->USER[index].reg &= ~EVSYS_USER_CHANNEL(mask); |
| 755 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 756 | } |
| 757 | |
| 758 | static inline void hri_evsys_toggle_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) |
| 759 | { |
| 760 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 761 | ((Evsys *)hw)->USER[index].reg ^= EVSYS_USER_CHANNEL(mask); |
| 762 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 763 | } |
| 764 | |
| 765 | static inline hri_evsys_user_reg_t hri_evsys_read_USER_CHANNEL_bf(const void *const hw, uint8_t index) |
| 766 | { |
| 767 | uint32_t tmp; |
| 768 | tmp = ((Evsys *)hw)->USER[index].reg; |
| 769 | tmp = (tmp & EVSYS_USER_CHANNEL_Msk) >> EVSYS_USER_CHANNEL_Pos; |
| 770 | return tmp; |
| 771 | } |
| 772 | |
| 773 | static inline void hri_evsys_set_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) |
| 774 | { |
| 775 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 776 | ((Evsys *)hw)->USER[index].reg |= mask; |
| 777 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 778 | } |
| 779 | |
| 780 | static inline hri_evsys_user_reg_t hri_evsys_get_USER_reg(const void *const hw, uint8_t index, |
| 781 | hri_evsys_user_reg_t mask) |
| 782 | { |
| 783 | uint32_t tmp; |
| 784 | tmp = ((Evsys *)hw)->USER[index].reg; |
| 785 | tmp &= mask; |
| 786 | return tmp; |
| 787 | } |
| 788 | |
| 789 | static inline void hri_evsys_write_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) |
| 790 | { |
| 791 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 792 | ((Evsys *)hw)->USER[index].reg = data; |
| 793 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 794 | } |
| 795 | |
| 796 | static inline void hri_evsys_clear_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) |
| 797 | { |
| 798 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 799 | ((Evsys *)hw)->USER[index].reg &= ~mask; |
| 800 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 801 | } |
| 802 | |
| 803 | static inline void hri_evsys_toggle_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) |
| 804 | { |
| 805 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 806 | ((Evsys *)hw)->USER[index].reg ^= mask; |
| 807 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 808 | } |
| 809 | |
| 810 | static inline hri_evsys_user_reg_t hri_evsys_read_USER_reg(const void *const hw, uint8_t index) |
| 811 | { |
| 812 | return ((Evsys *)hw)->USER[index].reg; |
| 813 | } |
| 814 | |
| 815 | static inline void hri_evsys_write_SWEVT_reg(const void *const hw, hri_evsys_swevt_reg_t data) |
| 816 | { |
| 817 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 818 | ((Evsys *)hw)->SWEVT.reg = data; |
| 819 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 820 | } |
| 821 | |
| 822 | static inline bool hri_evsyschannel_get_CHINTFLAG_OVR_bit(const void *const hw) |
| 823 | { |
| 824 | return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; |
| 825 | } |
| 826 | |
| 827 | static inline void hri_evsyschannel_clear_CHINTFLAG_OVR_bit(const void *const hw) |
| 828 | { |
| 829 | ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; |
| 830 | } |
| 831 | |
| 832 | static inline bool hri_evsyschannel_get_CHINTFLAG_EVD_bit(const void *const hw) |
| 833 | { |
| 834 | return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; |
| 835 | } |
| 836 | |
| 837 | static inline void hri_evsyschannel_clear_CHINTFLAG_EVD_bit(const void *const hw) |
| 838 | { |
| 839 | ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; |
| 840 | } |
| 841 | |
| 842 | static inline bool hri_evsyschannel_get_interrupt_OVR_bit(const void *const hw) |
| 843 | { |
| 844 | return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; |
| 845 | } |
| 846 | |
| 847 | static inline void hri_evsyschannel_clear_interrupt_OVR_bit(const void *const hw) |
| 848 | { |
| 849 | ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; |
| 850 | } |
| 851 | |
| 852 | static inline bool hri_evsyschannel_get_interrupt_EVD_bit(const void *const hw) |
| 853 | { |
| 854 | return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; |
| 855 | } |
| 856 | |
| 857 | static inline void hri_evsyschannel_clear_interrupt_EVD_bit(const void *const hw) |
| 858 | { |
| 859 | ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; |
| 860 | } |
| 861 | |
| 862 | static inline hri_evsys_chintflag_reg_t hri_evsyschannel_get_CHINTFLAG_reg(const void *const hw, |
| 863 | hri_evsys_chintflag_reg_t mask) |
| 864 | { |
| 865 | uint8_t tmp; |
| 866 | tmp = ((EvsysChannel *)hw)->CHINTFLAG.reg; |
| 867 | tmp &= mask; |
| 868 | return tmp; |
| 869 | } |
| 870 | |
| 871 | static inline hri_evsys_chintflag_reg_t hri_evsyschannel_read_CHINTFLAG_reg(const void *const hw) |
| 872 | { |
| 873 | return ((EvsysChannel *)hw)->CHINTFLAG.reg; |
| 874 | } |
| 875 | |
| 876 | static inline void hri_evsyschannel_clear_CHINTFLAG_reg(const void *const hw, hri_evsys_chintflag_reg_t mask) |
| 877 | { |
| 878 | ((EvsysChannel *)hw)->CHINTFLAG.reg = mask; |
| 879 | } |
| 880 | |
| 881 | static inline void hri_evsyschannel_set_CHINTEN_OVR_bit(const void *const hw) |
| 882 | { |
| 883 | ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_OVR; |
| 884 | } |
| 885 | |
| 886 | static inline bool hri_evsyschannel_get_CHINTEN_OVR_bit(const void *const hw) |
| 887 | { |
| 888 | return (((EvsysChannel *)hw)->CHINTENSET.reg & EVSYS_CHINTENSET_OVR) >> EVSYS_CHINTENSET_OVR_Pos; |
| 889 | } |
| 890 | |
| 891 | static inline void hri_evsyschannel_write_CHINTEN_OVR_bit(const void *const hw, bool value) |
| 892 | { |
| 893 | if (value == 0x0) { |
| 894 | ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; |
| 895 | } else { |
| 896 | ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_OVR; |
| 897 | } |
| 898 | } |
| 899 | |
| 900 | static inline void hri_evsyschannel_clear_CHINTEN_OVR_bit(const void *const hw) |
| 901 | { |
| 902 | ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; |
| 903 | } |
| 904 | |
| 905 | static inline void hri_evsyschannel_set_CHINTEN_EVD_bit(const void *const hw) |
| 906 | { |
| 907 | ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_EVD; |
| 908 | } |
| 909 | |
| 910 | static inline bool hri_evsyschannel_get_CHINTEN_EVD_bit(const void *const hw) |
| 911 | { |
| 912 | return (((EvsysChannel *)hw)->CHINTENSET.reg & EVSYS_CHINTENSET_EVD) >> EVSYS_CHINTENSET_EVD_Pos; |
| 913 | } |
| 914 | |
| 915 | static inline void hri_evsyschannel_write_CHINTEN_EVD_bit(const void *const hw, bool value) |
| 916 | { |
| 917 | if (value == 0x0) { |
| 918 | ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; |
| 919 | } else { |
| 920 | ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_EVD; |
| 921 | } |
| 922 | } |
| 923 | |
| 924 | static inline void hri_evsyschannel_clear_CHINTEN_EVD_bit(const void *const hw) |
| 925 | { |
| 926 | ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; |
| 927 | } |
| 928 | |
| 929 | static inline void hri_evsyschannel_set_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t mask) |
| 930 | { |
| 931 | ((EvsysChannel *)hw)->CHINTENSET.reg = mask; |
| 932 | } |
| 933 | |
| 934 | static inline hri_evsys_chintenset_reg_t hri_evsyschannel_get_CHINTEN_reg(const void *const hw, |
| 935 | hri_evsys_chintenset_reg_t mask) |
| 936 | { |
| 937 | uint8_t tmp; |
| 938 | tmp = ((EvsysChannel *)hw)->CHINTENSET.reg; |
| 939 | tmp &= mask; |
| 940 | return tmp; |
| 941 | } |
| 942 | |
| 943 | static inline hri_evsys_chintenset_reg_t hri_evsyschannel_read_CHINTEN_reg(const void *const hw) |
| 944 | { |
| 945 | return ((EvsysChannel *)hw)->CHINTENSET.reg; |
| 946 | } |
| 947 | |
| 948 | static inline void hri_evsyschannel_write_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t data) |
| 949 | { |
| 950 | ((EvsysChannel *)hw)->CHINTENSET.reg = data; |
| 951 | ((EvsysChannel *)hw)->CHINTENCLR.reg = ~data; |
| 952 | } |
| 953 | |
| 954 | static inline void hri_evsyschannel_clear_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t mask) |
| 955 | { |
| 956 | ((EvsysChannel *)hw)->CHINTENCLR.reg = mask; |
| 957 | } |
| 958 | |
| 959 | static inline bool hri_evsyschannel_get_CHSTATUS_RDYUSR_bit(const void *const hw) |
| 960 | { |
| 961 | return (((EvsysChannel *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_RDYUSR) >> EVSYS_CHSTATUS_RDYUSR_Pos; |
| 962 | } |
| 963 | |
| 964 | static inline bool hri_evsyschannel_get_CHSTATUS_BUSYCH_bit(const void *const hw) |
| 965 | { |
| 966 | return (((EvsysChannel *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_BUSYCH) >> EVSYS_CHSTATUS_BUSYCH_Pos; |
| 967 | } |
| 968 | |
| 969 | static inline hri_evsys_chstatus_reg_t hri_evsyschannel_get_CHSTATUS_reg(const void *const hw, |
| 970 | hri_evsys_chstatus_reg_t mask) |
| 971 | { |
| 972 | uint8_t tmp; |
| 973 | tmp = ((EvsysChannel *)hw)->CHSTATUS.reg; |
| 974 | tmp &= mask; |
| 975 | return tmp; |
| 976 | } |
| 977 | |
| 978 | static inline hri_evsys_chstatus_reg_t hri_evsyschannel_read_CHSTATUS_reg(const void *const hw) |
| 979 | { |
| 980 | return ((EvsysChannel *)hw)->CHSTATUS.reg; |
| 981 | } |
| 982 | |
| 983 | static inline void hri_evsyschannel_set_CHANNEL_RUNSTDBY_bit(const void *const hw) |
| 984 | { |
| 985 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 986 | ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_RUNSTDBY; |
| 987 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 988 | } |
| 989 | |
| 990 | static inline bool hri_evsyschannel_get_CHANNEL_RUNSTDBY_bit(const void *const hw) |
| 991 | { |
| 992 | uint32_t tmp; |
| 993 | tmp = ((EvsysChannel *)hw)->CHANNEL.reg; |
| 994 | tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos; |
| 995 | return (bool)tmp; |
| 996 | } |
| 997 | |
| 998 | static inline void hri_evsyschannel_write_CHANNEL_RUNSTDBY_bit(const void *const hw, bool value) |
| 999 | { |
| 1000 | uint32_t tmp; |
| 1001 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1002 | tmp = ((EvsysChannel *)hw)->CHANNEL.reg; |
| 1003 | tmp &= ~EVSYS_CHANNEL_RUNSTDBY; |
| 1004 | tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos; |
| 1005 | ((EvsysChannel *)hw)->CHANNEL.reg = tmp; |
| 1006 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1007 | } |
| 1008 | |
| 1009 | static inline void hri_evsyschannel_clear_CHANNEL_RUNSTDBY_bit(const void *const hw) |
| 1010 | { |
| 1011 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1012 | ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_RUNSTDBY; |
| 1013 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1014 | } |
| 1015 | |
| 1016 | static inline void hri_evsyschannel_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw) |
| 1017 | { |
| 1018 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1019 | ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_RUNSTDBY; |
| 1020 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1021 | } |
| 1022 | |
| 1023 | static inline void hri_evsyschannel_set_CHANNEL_ONDEMAND_bit(const void *const hw) |
| 1024 | { |
| 1025 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1026 | ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_ONDEMAND; |
| 1027 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1028 | } |
| 1029 | |
| 1030 | static inline bool hri_evsyschannel_get_CHANNEL_ONDEMAND_bit(const void *const hw) |
| 1031 | { |
| 1032 | uint32_t tmp; |
| 1033 | tmp = ((EvsysChannel *)hw)->CHANNEL.reg; |
| 1034 | tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos; |
| 1035 | return (bool)tmp; |
| 1036 | } |
| 1037 | |
| 1038 | static inline void hri_evsyschannel_write_CHANNEL_ONDEMAND_bit(const void *const hw, bool value) |
| 1039 | { |
| 1040 | uint32_t tmp; |
| 1041 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1042 | tmp = ((EvsysChannel *)hw)->CHANNEL.reg; |
| 1043 | tmp &= ~EVSYS_CHANNEL_ONDEMAND; |
| 1044 | tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos; |
| 1045 | ((EvsysChannel *)hw)->CHANNEL.reg = tmp; |
| 1046 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1047 | } |
| 1048 | |
| 1049 | static inline void hri_evsyschannel_clear_CHANNEL_ONDEMAND_bit(const void *const hw) |
| 1050 | { |
| 1051 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1052 | ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_ONDEMAND; |
| 1053 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1054 | } |
| 1055 | |
| 1056 | static inline void hri_evsyschannel_toggle_CHANNEL_ONDEMAND_bit(const void *const hw) |
| 1057 | { |
| 1058 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1059 | ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_ONDEMAND; |
| 1060 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1061 | } |
| 1062 | |
| 1063 | static inline void hri_evsyschannel_set_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) |
| 1064 | { |
| 1065 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1066 | ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EVGEN(mask); |
| 1067 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1068 | } |
| 1069 | |
| 1070 | static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_EVGEN_bf(const void *const hw, |
| 1071 | hri_evsys_channel_reg_t mask) |
| 1072 | { |
| 1073 | uint32_t tmp; |
| 1074 | tmp = ((EvsysChannel *)hw)->CHANNEL.reg; |
| 1075 | tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos; |
| 1076 | return tmp; |
| 1077 | } |
| 1078 | |
| 1079 | static inline void hri_evsyschannel_write_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t data) |
| 1080 | { |
| 1081 | uint32_t tmp; |
| 1082 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1083 | tmp = ((EvsysChannel *)hw)->CHANNEL.reg; |
| 1084 | tmp &= ~EVSYS_CHANNEL_EVGEN_Msk; |
| 1085 | tmp |= EVSYS_CHANNEL_EVGEN(data); |
| 1086 | ((EvsysChannel *)hw)->CHANNEL.reg = tmp; |
| 1087 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1088 | } |
| 1089 | |
| 1090 | static inline void hri_evsyschannel_clear_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) |
| 1091 | { |
| 1092 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1093 | ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EVGEN(mask); |
| 1094 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1095 | } |
| 1096 | |
| 1097 | static inline void hri_evsyschannel_toggle_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) |
| 1098 | { |
| 1099 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1100 | ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EVGEN(mask); |
| 1101 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1102 | } |
| 1103 | |
| 1104 | static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_EVGEN_bf(const void *const hw) |
| 1105 | { |
| 1106 | uint32_t tmp; |
| 1107 | tmp = ((EvsysChannel *)hw)->CHANNEL.reg; |
| 1108 | tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos; |
| 1109 | return tmp; |
| 1110 | } |
| 1111 | |
| 1112 | static inline void hri_evsyschannel_set_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) |
| 1113 | { |
| 1114 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1115 | ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_PATH(mask); |
| 1116 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1117 | } |
| 1118 | |
| 1119 | static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_PATH_bf(const void *const hw, |
| 1120 | hri_evsys_channel_reg_t mask) |
| 1121 | { |
| 1122 | uint32_t tmp; |
| 1123 | tmp = ((EvsysChannel *)hw)->CHANNEL.reg; |
| 1124 | tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos; |
| 1125 | return tmp; |
| 1126 | } |
| 1127 | |
| 1128 | static inline void hri_evsyschannel_write_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t data) |
| 1129 | { |
| 1130 | uint32_t tmp; |
| 1131 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1132 | tmp = ((EvsysChannel *)hw)->CHANNEL.reg; |
| 1133 | tmp &= ~EVSYS_CHANNEL_PATH_Msk; |
| 1134 | tmp |= EVSYS_CHANNEL_PATH(data); |
| 1135 | ((EvsysChannel *)hw)->CHANNEL.reg = tmp; |
| 1136 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1137 | } |
| 1138 | |
| 1139 | static inline void hri_evsyschannel_clear_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) |
| 1140 | { |
| 1141 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1142 | ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_PATH(mask); |
| 1143 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1144 | } |
| 1145 | |
| 1146 | static inline void hri_evsyschannel_toggle_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) |
| 1147 | { |
| 1148 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1149 | ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_PATH(mask); |
| 1150 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1151 | } |
| 1152 | |
| 1153 | static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_PATH_bf(const void *const hw) |
| 1154 | { |
| 1155 | uint32_t tmp; |
| 1156 | tmp = ((EvsysChannel *)hw)->CHANNEL.reg; |
| 1157 | tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos; |
| 1158 | return tmp; |
| 1159 | } |
| 1160 | |
| 1161 | static inline void hri_evsyschannel_set_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) |
| 1162 | { |
| 1163 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1164 | ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EDGSEL(mask); |
| 1165 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1166 | } |
| 1167 | |
| 1168 | static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_EDGSEL_bf(const void *const hw, |
| 1169 | hri_evsys_channel_reg_t mask) |
| 1170 | { |
| 1171 | uint32_t tmp; |
| 1172 | tmp = ((EvsysChannel *)hw)->CHANNEL.reg; |
| 1173 | tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos; |
| 1174 | return tmp; |
| 1175 | } |
| 1176 | |
| 1177 | static inline void hri_evsyschannel_write_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t data) |
| 1178 | { |
| 1179 | uint32_t tmp; |
| 1180 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1181 | tmp = ((EvsysChannel *)hw)->CHANNEL.reg; |
| 1182 | tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk; |
| 1183 | tmp |= EVSYS_CHANNEL_EDGSEL(data); |
| 1184 | ((EvsysChannel *)hw)->CHANNEL.reg = tmp; |
| 1185 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1186 | } |
| 1187 | |
| 1188 | static inline void hri_evsyschannel_clear_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) |
| 1189 | { |
| 1190 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1191 | ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EDGSEL(mask); |
| 1192 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1193 | } |
| 1194 | |
| 1195 | static inline void hri_evsyschannel_toggle_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) |
| 1196 | { |
| 1197 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1198 | ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EDGSEL(mask); |
| 1199 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1200 | } |
| 1201 | |
| 1202 | static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_EDGSEL_bf(const void *const hw) |
| 1203 | { |
| 1204 | uint32_t tmp; |
| 1205 | tmp = ((EvsysChannel *)hw)->CHANNEL.reg; |
| 1206 | tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos; |
| 1207 | return tmp; |
| 1208 | } |
| 1209 | |
| 1210 | static inline void hri_evsyschannel_set_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) |
| 1211 | { |
| 1212 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1213 | ((EvsysChannel *)hw)->CHANNEL.reg |= mask; |
| 1214 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1215 | } |
| 1216 | |
| 1217 | static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_reg(const void *const hw, |
| 1218 | hri_evsys_channel_reg_t mask) |
| 1219 | { |
| 1220 | uint32_t tmp; |
| 1221 | tmp = ((EvsysChannel *)hw)->CHANNEL.reg; |
| 1222 | tmp &= mask; |
| 1223 | return tmp; |
| 1224 | } |
| 1225 | |
| 1226 | static inline void hri_evsyschannel_write_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t data) |
| 1227 | { |
| 1228 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1229 | ((EvsysChannel *)hw)->CHANNEL.reg = data; |
| 1230 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1231 | } |
| 1232 | |
| 1233 | static inline void hri_evsyschannel_clear_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) |
| 1234 | { |
| 1235 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1236 | ((EvsysChannel *)hw)->CHANNEL.reg &= ~mask; |
| 1237 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1238 | } |
| 1239 | |
| 1240 | static inline void hri_evsyschannel_toggle_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) |
| 1241 | { |
| 1242 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1243 | ((EvsysChannel *)hw)->CHANNEL.reg ^= mask; |
| 1244 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1245 | } |
| 1246 | |
| 1247 | static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_reg(const void *const hw) |
| 1248 | { |
| 1249 | return ((EvsysChannel *)hw)->CHANNEL.reg; |
| 1250 | } |
| 1251 | |
| 1252 | static inline bool hri_evsys_get_CHINTFLAG_OVR_bit(const void *const hw, uint8_t submodule_index) |
| 1253 | { |
| 1254 | return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; |
| 1255 | } |
| 1256 | |
| 1257 | static inline void hri_evsys_clear_CHINTFLAG_OVR_bit(const void *const hw, uint8_t submodule_index) |
| 1258 | { |
| 1259 | ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; |
| 1260 | } |
| 1261 | |
| 1262 | static inline bool hri_evsys_get_CHINTFLAG_EVD_bit(const void *const hw, uint8_t submodule_index) |
| 1263 | { |
| 1264 | return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; |
| 1265 | } |
| 1266 | |
| 1267 | static inline void hri_evsys_clear_CHINTFLAG_EVD_bit(const void *const hw, uint8_t submodule_index) |
| 1268 | { |
| 1269 | ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; |
| 1270 | } |
| 1271 | |
| 1272 | static inline bool hri_evsys_get_interrupt_OVR_bit(const void *const hw, uint8_t submodule_index) |
| 1273 | { |
| 1274 | return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; |
| 1275 | } |
| 1276 | |
| 1277 | static inline void hri_evsys_clear_interrupt_OVR_bit(const void *const hw, uint8_t submodule_index) |
| 1278 | { |
| 1279 | ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; |
| 1280 | } |
| 1281 | |
| 1282 | static inline bool hri_evsys_get_interrupt_EVD_bit(const void *const hw, uint8_t submodule_index) |
| 1283 | { |
| 1284 | return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; |
| 1285 | } |
| 1286 | |
| 1287 | static inline void hri_evsys_clear_interrupt_EVD_bit(const void *const hw, uint8_t submodule_index) |
| 1288 | { |
| 1289 | ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; |
| 1290 | } |
| 1291 | |
| 1292 | static inline hri_evsys_chintflag_reg_t hri_evsys_get_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, |
| 1293 | hri_evsys_chintflag_reg_t mask) |
| 1294 | { |
| 1295 | uint8_t tmp; |
| 1296 | tmp = ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg; |
| 1297 | tmp &= mask; |
| 1298 | return tmp; |
| 1299 | } |
| 1300 | |
| 1301 | static inline hri_evsys_chintflag_reg_t hri_evsys_read_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index) |
| 1302 | { |
| 1303 | return ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg; |
| 1304 | } |
| 1305 | |
| 1306 | static inline void hri_evsys_clear_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, |
| 1307 | hri_evsys_chintflag_reg_t mask) |
| 1308 | { |
| 1309 | ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = mask; |
| 1310 | } |
| 1311 | |
| 1312 | static inline void hri_evsys_set_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index) |
| 1313 | { |
| 1314 | ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_OVR; |
| 1315 | } |
| 1316 | |
| 1317 | static inline bool hri_evsys_get_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index) |
| 1318 | { |
| 1319 | return (((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg & EVSYS_CHINTENSET_OVR) >> EVSYS_CHINTENSET_OVR_Pos; |
| 1320 | } |
| 1321 | |
| 1322 | static inline void hri_evsys_write_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index, bool value) |
| 1323 | { |
| 1324 | if (value == 0x0) { |
| 1325 | ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; |
| 1326 | } else { |
| 1327 | ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_OVR; |
| 1328 | } |
| 1329 | } |
| 1330 | |
| 1331 | static inline void hri_evsys_clear_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index) |
| 1332 | { |
| 1333 | ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; |
| 1334 | } |
| 1335 | |
| 1336 | static inline void hri_evsys_set_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index) |
| 1337 | { |
| 1338 | ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_EVD; |
| 1339 | } |
| 1340 | |
| 1341 | static inline bool hri_evsys_get_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index) |
| 1342 | { |
| 1343 | return (((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg & EVSYS_CHINTENSET_EVD) >> EVSYS_CHINTENSET_EVD_Pos; |
| 1344 | } |
| 1345 | |
| 1346 | static inline void hri_evsys_write_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index, bool value) |
| 1347 | { |
| 1348 | if (value == 0x0) { |
| 1349 | ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; |
| 1350 | } else { |
| 1351 | ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_EVD; |
| 1352 | } |
| 1353 | } |
| 1354 | |
| 1355 | static inline void hri_evsys_clear_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index) |
| 1356 | { |
| 1357 | ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; |
| 1358 | } |
| 1359 | |
| 1360 | static inline void hri_evsys_set_CHINTEN_reg(const void *const hw, uint8_t submodule_index, |
| 1361 | hri_evsys_chintenset_reg_t mask) |
| 1362 | { |
| 1363 | ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = mask; |
| 1364 | } |
| 1365 | |
| 1366 | static inline hri_evsys_chintenset_reg_t hri_evsys_get_CHINTEN_reg(const void *const hw, uint8_t submodule_index, |
| 1367 | hri_evsys_chintenset_reg_t mask) |
| 1368 | { |
| 1369 | uint8_t tmp; |
| 1370 | tmp = ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg; |
| 1371 | tmp &= mask; |
| 1372 | return tmp; |
| 1373 | } |
| 1374 | |
| 1375 | static inline hri_evsys_chintenset_reg_t hri_evsys_read_CHINTEN_reg(const void *const hw, uint8_t submodule_index) |
| 1376 | { |
| 1377 | return ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg; |
| 1378 | } |
| 1379 | |
| 1380 | static inline void hri_evsys_write_CHINTEN_reg(const void *const hw, uint8_t submodule_index, |
| 1381 | hri_evsys_chintenset_reg_t data) |
| 1382 | { |
| 1383 | ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = data; |
| 1384 | ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = ~data; |
| 1385 | } |
| 1386 | |
| 1387 | static inline void hri_evsys_clear_CHINTEN_reg(const void *const hw, uint8_t submodule_index, |
| 1388 | hri_evsys_chintenset_reg_t mask) |
| 1389 | { |
| 1390 | ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = mask; |
| 1391 | } |
| 1392 | |
| 1393 | static inline bool hri_evsys_get_CHSTATUS_RDYUSR_bit(const void *const hw, uint8_t submodule_index) |
| 1394 | { |
| 1395 | return (((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg & EVSYS_CHSTATUS_RDYUSR) >> EVSYS_CHSTATUS_RDYUSR_Pos; |
| 1396 | } |
| 1397 | |
| 1398 | static inline bool hri_evsys_get_CHSTATUS_BUSYCH_bit(const void *const hw, uint8_t submodule_index) |
| 1399 | { |
| 1400 | return (((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg & EVSYS_CHSTATUS_BUSYCH) >> EVSYS_CHSTATUS_BUSYCH_Pos; |
| 1401 | } |
| 1402 | |
| 1403 | static inline hri_evsys_chstatus_reg_t hri_evsys_get_CHSTATUS_reg(const void *const hw, uint8_t submodule_index, |
| 1404 | hri_evsys_chstatus_reg_t mask) |
| 1405 | { |
| 1406 | uint8_t tmp; |
| 1407 | tmp = ((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg; |
| 1408 | tmp &= mask; |
| 1409 | return tmp; |
| 1410 | } |
| 1411 | |
| 1412 | static inline hri_evsys_chstatus_reg_t hri_evsys_read_CHSTATUS_reg(const void *const hw, uint8_t submodule_index) |
| 1413 | { |
| 1414 | return ((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg; |
| 1415 | } |
| 1416 | |
| 1417 | static inline void hri_evsys_set_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) |
| 1418 | { |
| 1419 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1420 | ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_RUNSTDBY; |
| 1421 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1422 | } |
| 1423 | |
| 1424 | static inline bool hri_evsys_get_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) |
| 1425 | { |
| 1426 | uint32_t tmp; |
| 1427 | tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; |
| 1428 | tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos; |
| 1429 | return (bool)tmp; |
| 1430 | } |
| 1431 | |
| 1432 | static inline void hri_evsys_write_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value) |
| 1433 | { |
| 1434 | uint32_t tmp; |
| 1435 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1436 | tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; |
| 1437 | tmp &= ~EVSYS_CHANNEL_RUNSTDBY; |
| 1438 | tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos; |
| 1439 | ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; |
| 1440 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1441 | } |
| 1442 | |
| 1443 | static inline void hri_evsys_clear_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) |
| 1444 | { |
| 1445 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1446 | ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_RUNSTDBY; |
| 1447 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1448 | } |
| 1449 | |
| 1450 | static inline void hri_evsys_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) |
| 1451 | { |
| 1452 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1453 | ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_RUNSTDBY; |
| 1454 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1455 | } |
| 1456 | |
| 1457 | static inline void hri_evsys_set_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) |
| 1458 | { |
| 1459 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1460 | ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_ONDEMAND; |
| 1461 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1462 | } |
| 1463 | |
| 1464 | static inline bool hri_evsys_get_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) |
| 1465 | { |
| 1466 | uint32_t tmp; |
| 1467 | tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; |
| 1468 | tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos; |
| 1469 | return (bool)tmp; |
| 1470 | } |
| 1471 | |
| 1472 | static inline void hri_evsys_write_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index, bool value) |
| 1473 | { |
| 1474 | uint32_t tmp; |
| 1475 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1476 | tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; |
| 1477 | tmp &= ~EVSYS_CHANNEL_ONDEMAND; |
| 1478 | tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos; |
| 1479 | ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; |
| 1480 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1481 | } |
| 1482 | |
| 1483 | static inline void hri_evsys_clear_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) |
| 1484 | { |
| 1485 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1486 | ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_ONDEMAND; |
| 1487 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1488 | } |
| 1489 | |
| 1490 | static inline void hri_evsys_toggle_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) |
| 1491 | { |
| 1492 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1493 | ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_ONDEMAND; |
| 1494 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1495 | } |
| 1496 | |
| 1497 | static inline void hri_evsys_set_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, |
| 1498 | hri_evsys_channel_reg_t mask) |
| 1499 | { |
| 1500 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1501 | ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_EVGEN(mask); |
| 1502 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1503 | } |
| 1504 | |
| 1505 | static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, |
| 1506 | hri_evsys_channel_reg_t mask) |
| 1507 | { |
| 1508 | uint32_t tmp; |
| 1509 | tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; |
| 1510 | tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos; |
| 1511 | return tmp; |
| 1512 | } |
| 1513 | |
| 1514 | static inline void hri_evsys_write_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, |
| 1515 | hri_evsys_channel_reg_t data) |
| 1516 | { |
| 1517 | uint32_t tmp; |
| 1518 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1519 | tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; |
| 1520 | tmp &= ~EVSYS_CHANNEL_EVGEN_Msk; |
| 1521 | tmp |= EVSYS_CHANNEL_EVGEN(data); |
| 1522 | ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; |
| 1523 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1524 | } |
| 1525 | |
| 1526 | static inline void hri_evsys_clear_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, |
| 1527 | hri_evsys_channel_reg_t mask) |
| 1528 | { |
| 1529 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1530 | ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_EVGEN(mask); |
| 1531 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1532 | } |
| 1533 | |
| 1534 | static inline void hri_evsys_toggle_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, |
| 1535 | hri_evsys_channel_reg_t mask) |
| 1536 | { |
| 1537 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1538 | ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_EVGEN(mask); |
| 1539 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1540 | } |
| 1541 | |
| 1542 | static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index) |
| 1543 | { |
| 1544 | uint32_t tmp; |
| 1545 | tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; |
| 1546 | tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos; |
| 1547 | return tmp; |
| 1548 | } |
| 1549 | |
| 1550 | static inline void hri_evsys_set_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, |
| 1551 | hri_evsys_channel_reg_t mask) |
| 1552 | { |
| 1553 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1554 | ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_PATH(mask); |
| 1555 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1556 | } |
| 1557 | |
| 1558 | static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, |
| 1559 | hri_evsys_channel_reg_t mask) |
| 1560 | { |
| 1561 | uint32_t tmp; |
| 1562 | tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; |
| 1563 | tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos; |
| 1564 | return tmp; |
| 1565 | } |
| 1566 | |
| 1567 | static inline void hri_evsys_write_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, |
| 1568 | hri_evsys_channel_reg_t data) |
| 1569 | { |
| 1570 | uint32_t tmp; |
| 1571 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1572 | tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; |
| 1573 | tmp &= ~EVSYS_CHANNEL_PATH_Msk; |
| 1574 | tmp |= EVSYS_CHANNEL_PATH(data); |
| 1575 | ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; |
| 1576 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1577 | } |
| 1578 | |
| 1579 | static inline void hri_evsys_clear_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, |
| 1580 | hri_evsys_channel_reg_t mask) |
| 1581 | { |
| 1582 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1583 | ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_PATH(mask); |
| 1584 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1585 | } |
| 1586 | |
| 1587 | static inline void hri_evsys_toggle_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, |
| 1588 | hri_evsys_channel_reg_t mask) |
| 1589 | { |
| 1590 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1591 | ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_PATH(mask); |
| 1592 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1593 | } |
| 1594 | |
| 1595 | static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index) |
| 1596 | { |
| 1597 | uint32_t tmp; |
| 1598 | tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; |
| 1599 | tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos; |
| 1600 | return tmp; |
| 1601 | } |
| 1602 | |
| 1603 | static inline void hri_evsys_set_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, |
| 1604 | hri_evsys_channel_reg_t mask) |
| 1605 | { |
| 1606 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1607 | ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_EDGSEL(mask); |
| 1608 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1609 | } |
| 1610 | |
| 1611 | static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, |
| 1612 | hri_evsys_channel_reg_t mask) |
| 1613 | { |
| 1614 | uint32_t tmp; |
| 1615 | tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; |
| 1616 | tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos; |
| 1617 | return tmp; |
| 1618 | } |
| 1619 | |
| 1620 | static inline void hri_evsys_write_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, |
| 1621 | hri_evsys_channel_reg_t data) |
| 1622 | { |
| 1623 | uint32_t tmp; |
| 1624 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1625 | tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; |
| 1626 | tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk; |
| 1627 | tmp |= EVSYS_CHANNEL_EDGSEL(data); |
| 1628 | ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; |
| 1629 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1630 | } |
| 1631 | |
| 1632 | static inline void hri_evsys_clear_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, |
| 1633 | hri_evsys_channel_reg_t mask) |
| 1634 | { |
| 1635 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1636 | ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_EDGSEL(mask); |
| 1637 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1638 | } |
| 1639 | |
| 1640 | static inline void hri_evsys_toggle_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, |
| 1641 | hri_evsys_channel_reg_t mask) |
| 1642 | { |
| 1643 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1644 | ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_EDGSEL(mask); |
| 1645 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1646 | } |
| 1647 | |
| 1648 | static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index) |
| 1649 | { |
| 1650 | uint32_t tmp; |
| 1651 | tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; |
| 1652 | tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos; |
| 1653 | return tmp; |
| 1654 | } |
| 1655 | |
| 1656 | static inline void hri_evsys_set_CHANNEL_reg(const void *const hw, uint8_t submodule_index, |
| 1657 | hri_evsys_channel_reg_t mask) |
| 1658 | { |
| 1659 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1660 | ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= mask; |
| 1661 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1662 | } |
| 1663 | |
| 1664 | static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_reg(const void *const hw, uint8_t submodule_index, |
| 1665 | hri_evsys_channel_reg_t mask) |
| 1666 | { |
| 1667 | uint32_t tmp; |
| 1668 | tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; |
| 1669 | tmp &= mask; |
| 1670 | return tmp; |
| 1671 | } |
| 1672 | |
| 1673 | static inline void hri_evsys_write_CHANNEL_reg(const void *const hw, uint8_t submodule_index, |
| 1674 | hri_evsys_channel_reg_t data) |
| 1675 | { |
| 1676 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1677 | ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = data; |
| 1678 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1679 | } |
| 1680 | |
| 1681 | static inline void hri_evsys_clear_CHANNEL_reg(const void *const hw, uint8_t submodule_index, |
| 1682 | hri_evsys_channel_reg_t mask) |
| 1683 | { |
| 1684 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1685 | ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~mask; |
| 1686 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1687 | } |
| 1688 | |
| 1689 | static inline void hri_evsys_toggle_CHANNEL_reg(const void *const hw, uint8_t submodule_index, |
| 1690 | hri_evsys_channel_reg_t mask) |
| 1691 | { |
| 1692 | EVSYS_CRITICAL_SECTION_ENTER(); |
| 1693 | ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= mask; |
| 1694 | EVSYS_CRITICAL_SECTION_LEAVE(); |
| 1695 | } |
| 1696 | |
| 1697 | static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_reg(const void *const hw, uint8_t submodule_index) |
| 1698 | { |
| 1699 | return ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; |
| 1700 | } |
| 1701 | |
| 1702 | #ifdef __cplusplus |
| 1703 | } |
| 1704 | #endif |
| 1705 | |
| 1706 | #endif /* _HRI_EVSYS_E54_H_INCLUDED */ |
| 1707 | #endif /* _SAME54_EVSYS_COMPONENT_ */ |