Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM DAC |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_DAC_COMPONENT_ |
| 35 | #ifndef _HRI_DAC_E54_H_INCLUDED_ |
| 36 | #define _HRI_DAC_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_DAC_CRITICAL_SECTIONS) |
| 46 | #define DAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define DAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define DAC_CRITICAL_SECTION_ENTER() |
| 50 | #define DAC_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint16_t hri_dac_dacctrl_reg_t; |
| 54 | typedef uint16_t hri_dac_data_reg_t; |
| 55 | typedef uint16_t hri_dac_databuf_reg_t; |
| 56 | typedef uint16_t hri_dac_result_reg_t; |
| 57 | typedef uint32_t hri_dac_syncbusy_reg_t; |
| 58 | typedef uint8_t hri_dac_ctrla_reg_t; |
| 59 | typedef uint8_t hri_dac_ctrlb_reg_t; |
| 60 | typedef uint8_t hri_dac_dbgctrl_reg_t; |
| 61 | typedef uint8_t hri_dac_evctrl_reg_t; |
| 62 | typedef uint8_t hri_dac_intenset_reg_t; |
| 63 | typedef uint8_t hri_dac_intflag_reg_t; |
| 64 | typedef uint8_t hri_dac_status_reg_t; |
| 65 | |
| 66 | static inline void hri_dac_wait_for_sync(const void *const hw, hri_dac_syncbusy_reg_t reg) |
| 67 | { |
| 68 | while (((Dac *)hw)->SYNCBUSY.reg & reg) { |
| 69 | }; |
| 70 | } |
| 71 | |
| 72 | static inline bool hri_dac_is_syncing(const void *const hw, hri_dac_syncbusy_reg_t reg) |
| 73 | { |
| 74 | return ((Dac *)hw)->SYNCBUSY.reg & reg; |
| 75 | } |
| 76 | |
| 77 | static inline bool hri_dac_get_INTFLAG_UNDERRUN0_bit(const void *const hw) |
| 78 | { |
| 79 | return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) >> DAC_INTFLAG_UNDERRUN0_Pos; |
| 80 | } |
| 81 | |
| 82 | static inline void hri_dac_clear_INTFLAG_UNDERRUN0_bit(const void *const hw) |
| 83 | { |
| 84 | ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0; |
| 85 | } |
| 86 | |
| 87 | static inline bool hri_dac_get_INTFLAG_UNDERRUN1_bit(const void *const hw) |
| 88 | { |
| 89 | return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) >> DAC_INTFLAG_UNDERRUN1_Pos; |
| 90 | } |
| 91 | |
| 92 | static inline void hri_dac_clear_INTFLAG_UNDERRUN1_bit(const void *const hw) |
| 93 | { |
| 94 | ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1; |
| 95 | } |
| 96 | |
| 97 | static inline bool hri_dac_get_INTFLAG_EMPTY0_bit(const void *const hw) |
| 98 | { |
| 99 | return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY0) >> DAC_INTFLAG_EMPTY0_Pos; |
| 100 | } |
| 101 | |
| 102 | static inline void hri_dac_clear_INTFLAG_EMPTY0_bit(const void *const hw) |
| 103 | { |
| 104 | ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY0; |
| 105 | } |
| 106 | |
| 107 | static inline bool hri_dac_get_INTFLAG_EMPTY1_bit(const void *const hw) |
| 108 | { |
| 109 | return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY1) >> DAC_INTFLAG_EMPTY1_Pos; |
| 110 | } |
| 111 | |
| 112 | static inline void hri_dac_clear_INTFLAG_EMPTY1_bit(const void *const hw) |
| 113 | { |
| 114 | ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY1; |
| 115 | } |
| 116 | |
| 117 | static inline bool hri_dac_get_INTFLAG_RESRDY0_bit(const void *const hw) |
| 118 | { |
| 119 | return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY0) >> DAC_INTFLAG_RESRDY0_Pos; |
| 120 | } |
| 121 | |
| 122 | static inline void hri_dac_clear_INTFLAG_RESRDY0_bit(const void *const hw) |
| 123 | { |
| 124 | ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY0; |
| 125 | } |
| 126 | |
| 127 | static inline bool hri_dac_get_INTFLAG_RESRDY1_bit(const void *const hw) |
| 128 | { |
| 129 | return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY1) >> DAC_INTFLAG_RESRDY1_Pos; |
| 130 | } |
| 131 | |
| 132 | static inline void hri_dac_clear_INTFLAG_RESRDY1_bit(const void *const hw) |
| 133 | { |
| 134 | ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY1; |
| 135 | } |
| 136 | |
| 137 | static inline bool hri_dac_get_INTFLAG_OVERRUN0_bit(const void *const hw) |
| 138 | { |
| 139 | return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN0) >> DAC_INTFLAG_OVERRUN0_Pos; |
| 140 | } |
| 141 | |
| 142 | static inline void hri_dac_clear_INTFLAG_OVERRUN0_bit(const void *const hw) |
| 143 | { |
| 144 | ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN0; |
| 145 | } |
| 146 | |
| 147 | static inline bool hri_dac_get_INTFLAG_OVERRUN1_bit(const void *const hw) |
| 148 | { |
| 149 | return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN1) >> DAC_INTFLAG_OVERRUN1_Pos; |
| 150 | } |
| 151 | |
| 152 | static inline void hri_dac_clear_INTFLAG_OVERRUN1_bit(const void *const hw) |
| 153 | { |
| 154 | ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN1; |
| 155 | } |
| 156 | |
| 157 | static inline bool hri_dac_get_interrupt_UNDERRUN0_bit(const void *const hw) |
| 158 | { |
| 159 | return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) >> DAC_INTFLAG_UNDERRUN0_Pos; |
| 160 | } |
| 161 | |
| 162 | static inline void hri_dac_clear_interrupt_UNDERRUN0_bit(const void *const hw) |
| 163 | { |
| 164 | ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0; |
| 165 | } |
| 166 | |
| 167 | static inline bool hri_dac_get_interrupt_UNDERRUN1_bit(const void *const hw) |
| 168 | { |
| 169 | return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) >> DAC_INTFLAG_UNDERRUN1_Pos; |
| 170 | } |
| 171 | |
| 172 | static inline void hri_dac_clear_interrupt_UNDERRUN1_bit(const void *const hw) |
| 173 | { |
| 174 | ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1; |
| 175 | } |
| 176 | |
| 177 | static inline bool hri_dac_get_interrupt_EMPTY0_bit(const void *const hw) |
| 178 | { |
| 179 | return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY0) >> DAC_INTFLAG_EMPTY0_Pos; |
| 180 | } |
| 181 | |
| 182 | static inline void hri_dac_clear_interrupt_EMPTY0_bit(const void *const hw) |
| 183 | { |
| 184 | ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY0; |
| 185 | } |
| 186 | |
| 187 | static inline bool hri_dac_get_interrupt_EMPTY1_bit(const void *const hw) |
| 188 | { |
| 189 | return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY1) >> DAC_INTFLAG_EMPTY1_Pos; |
| 190 | } |
| 191 | |
| 192 | static inline void hri_dac_clear_interrupt_EMPTY1_bit(const void *const hw) |
| 193 | { |
| 194 | ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY1; |
| 195 | } |
| 196 | |
| 197 | static inline bool hri_dac_get_interrupt_RESRDY0_bit(const void *const hw) |
| 198 | { |
| 199 | return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY0) >> DAC_INTFLAG_RESRDY0_Pos; |
| 200 | } |
| 201 | |
| 202 | static inline void hri_dac_clear_interrupt_RESRDY0_bit(const void *const hw) |
| 203 | { |
| 204 | ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY0; |
| 205 | } |
| 206 | |
| 207 | static inline bool hri_dac_get_interrupt_RESRDY1_bit(const void *const hw) |
| 208 | { |
| 209 | return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY1) >> DAC_INTFLAG_RESRDY1_Pos; |
| 210 | } |
| 211 | |
| 212 | static inline void hri_dac_clear_interrupt_RESRDY1_bit(const void *const hw) |
| 213 | { |
| 214 | ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY1; |
| 215 | } |
| 216 | |
| 217 | static inline bool hri_dac_get_interrupt_OVERRUN0_bit(const void *const hw) |
| 218 | { |
| 219 | return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN0) >> DAC_INTFLAG_OVERRUN0_Pos; |
| 220 | } |
| 221 | |
| 222 | static inline void hri_dac_clear_interrupt_OVERRUN0_bit(const void *const hw) |
| 223 | { |
| 224 | ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN0; |
| 225 | } |
| 226 | |
| 227 | static inline bool hri_dac_get_interrupt_OVERRUN1_bit(const void *const hw) |
| 228 | { |
| 229 | return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN1) >> DAC_INTFLAG_OVERRUN1_Pos; |
| 230 | } |
| 231 | |
| 232 | static inline void hri_dac_clear_interrupt_OVERRUN1_bit(const void *const hw) |
| 233 | { |
| 234 | ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN1; |
| 235 | } |
| 236 | |
| 237 | static inline hri_dac_intflag_reg_t hri_dac_get_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) |
| 238 | { |
| 239 | uint8_t tmp; |
| 240 | tmp = ((Dac *)hw)->INTFLAG.reg; |
| 241 | tmp &= mask; |
| 242 | return tmp; |
| 243 | } |
| 244 | |
| 245 | static inline hri_dac_intflag_reg_t hri_dac_read_INTFLAG_reg(const void *const hw) |
| 246 | { |
| 247 | return ((Dac *)hw)->INTFLAG.reg; |
| 248 | } |
| 249 | |
| 250 | static inline void hri_dac_clear_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) |
| 251 | { |
| 252 | ((Dac *)hw)->INTFLAG.reg = mask; |
| 253 | } |
| 254 | |
| 255 | static inline void hri_dac_set_INTEN_UNDERRUN0_bit(const void *const hw) |
| 256 | { |
| 257 | ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0; |
| 258 | } |
| 259 | |
| 260 | static inline bool hri_dac_get_INTEN_UNDERRUN0_bit(const void *const hw) |
| 261 | { |
| 262 | return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN0) >> DAC_INTENSET_UNDERRUN0_Pos; |
| 263 | } |
| 264 | |
| 265 | static inline void hri_dac_write_INTEN_UNDERRUN0_bit(const void *const hw, bool value) |
| 266 | { |
| 267 | if (value == 0x0) { |
| 268 | ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0; |
| 269 | } else { |
| 270 | ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0; |
| 271 | } |
| 272 | } |
| 273 | |
| 274 | static inline void hri_dac_clear_INTEN_UNDERRUN0_bit(const void *const hw) |
| 275 | { |
| 276 | ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0; |
| 277 | } |
| 278 | |
| 279 | static inline void hri_dac_set_INTEN_UNDERRUN1_bit(const void *const hw) |
| 280 | { |
| 281 | ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1; |
| 282 | } |
| 283 | |
| 284 | static inline bool hri_dac_get_INTEN_UNDERRUN1_bit(const void *const hw) |
| 285 | { |
| 286 | return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN1) >> DAC_INTENSET_UNDERRUN1_Pos; |
| 287 | } |
| 288 | |
| 289 | static inline void hri_dac_write_INTEN_UNDERRUN1_bit(const void *const hw, bool value) |
| 290 | { |
| 291 | if (value == 0x0) { |
| 292 | ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1; |
| 293 | } else { |
| 294 | ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1; |
| 295 | } |
| 296 | } |
| 297 | |
| 298 | static inline void hri_dac_clear_INTEN_UNDERRUN1_bit(const void *const hw) |
| 299 | { |
| 300 | ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1; |
| 301 | } |
| 302 | |
| 303 | static inline void hri_dac_set_INTEN_EMPTY0_bit(const void *const hw) |
| 304 | { |
| 305 | ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0; |
| 306 | } |
| 307 | |
| 308 | static inline bool hri_dac_get_INTEN_EMPTY0_bit(const void *const hw) |
| 309 | { |
| 310 | return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY0) >> DAC_INTENSET_EMPTY0_Pos; |
| 311 | } |
| 312 | |
| 313 | static inline void hri_dac_write_INTEN_EMPTY0_bit(const void *const hw, bool value) |
| 314 | { |
| 315 | if (value == 0x0) { |
| 316 | ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0; |
| 317 | } else { |
| 318 | ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0; |
| 319 | } |
| 320 | } |
| 321 | |
| 322 | static inline void hri_dac_clear_INTEN_EMPTY0_bit(const void *const hw) |
| 323 | { |
| 324 | ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0; |
| 325 | } |
| 326 | |
| 327 | static inline void hri_dac_set_INTEN_EMPTY1_bit(const void *const hw) |
| 328 | { |
| 329 | ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1; |
| 330 | } |
| 331 | |
| 332 | static inline bool hri_dac_get_INTEN_EMPTY1_bit(const void *const hw) |
| 333 | { |
| 334 | return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY1) >> DAC_INTENSET_EMPTY1_Pos; |
| 335 | } |
| 336 | |
| 337 | static inline void hri_dac_write_INTEN_EMPTY1_bit(const void *const hw, bool value) |
| 338 | { |
| 339 | if (value == 0x0) { |
| 340 | ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1; |
| 341 | } else { |
| 342 | ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1; |
| 343 | } |
| 344 | } |
| 345 | |
| 346 | static inline void hri_dac_clear_INTEN_EMPTY1_bit(const void *const hw) |
| 347 | { |
| 348 | ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1; |
| 349 | } |
| 350 | |
| 351 | static inline void hri_dac_set_INTEN_RESRDY0_bit(const void *const hw) |
| 352 | { |
| 353 | ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY0; |
| 354 | } |
| 355 | |
| 356 | static inline bool hri_dac_get_INTEN_RESRDY0_bit(const void *const hw) |
| 357 | { |
| 358 | return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_RESRDY0) >> DAC_INTENSET_RESRDY0_Pos; |
| 359 | } |
| 360 | |
| 361 | static inline void hri_dac_write_INTEN_RESRDY0_bit(const void *const hw, bool value) |
| 362 | { |
| 363 | if (value == 0x0) { |
| 364 | ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY0; |
| 365 | } else { |
| 366 | ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY0; |
| 367 | } |
| 368 | } |
| 369 | |
| 370 | static inline void hri_dac_clear_INTEN_RESRDY0_bit(const void *const hw) |
| 371 | { |
| 372 | ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY0; |
| 373 | } |
| 374 | |
| 375 | static inline void hri_dac_set_INTEN_RESRDY1_bit(const void *const hw) |
| 376 | { |
| 377 | ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY1; |
| 378 | } |
| 379 | |
| 380 | static inline bool hri_dac_get_INTEN_RESRDY1_bit(const void *const hw) |
| 381 | { |
| 382 | return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_RESRDY1) >> DAC_INTENSET_RESRDY1_Pos; |
| 383 | } |
| 384 | |
| 385 | static inline void hri_dac_write_INTEN_RESRDY1_bit(const void *const hw, bool value) |
| 386 | { |
| 387 | if (value == 0x0) { |
| 388 | ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY1; |
| 389 | } else { |
| 390 | ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY1; |
| 391 | } |
| 392 | } |
| 393 | |
| 394 | static inline void hri_dac_clear_INTEN_RESRDY1_bit(const void *const hw) |
| 395 | { |
| 396 | ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY1; |
| 397 | } |
| 398 | |
| 399 | static inline void hri_dac_set_INTEN_OVERRUN0_bit(const void *const hw) |
| 400 | { |
| 401 | ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN0; |
| 402 | } |
| 403 | |
| 404 | static inline bool hri_dac_get_INTEN_OVERRUN0_bit(const void *const hw) |
| 405 | { |
| 406 | return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_OVERRUN0) >> DAC_INTENSET_OVERRUN0_Pos; |
| 407 | } |
| 408 | |
| 409 | static inline void hri_dac_write_INTEN_OVERRUN0_bit(const void *const hw, bool value) |
| 410 | { |
| 411 | if (value == 0x0) { |
| 412 | ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN0; |
| 413 | } else { |
| 414 | ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN0; |
| 415 | } |
| 416 | } |
| 417 | |
| 418 | static inline void hri_dac_clear_INTEN_OVERRUN0_bit(const void *const hw) |
| 419 | { |
| 420 | ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN0; |
| 421 | } |
| 422 | |
| 423 | static inline void hri_dac_set_INTEN_OVERRUN1_bit(const void *const hw) |
| 424 | { |
| 425 | ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN1; |
| 426 | } |
| 427 | |
| 428 | static inline bool hri_dac_get_INTEN_OVERRUN1_bit(const void *const hw) |
| 429 | { |
| 430 | return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_OVERRUN1) >> DAC_INTENSET_OVERRUN1_Pos; |
| 431 | } |
| 432 | |
| 433 | static inline void hri_dac_write_INTEN_OVERRUN1_bit(const void *const hw, bool value) |
| 434 | { |
| 435 | if (value == 0x0) { |
| 436 | ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN1; |
| 437 | } else { |
| 438 | ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN1; |
| 439 | } |
| 440 | } |
| 441 | |
| 442 | static inline void hri_dac_clear_INTEN_OVERRUN1_bit(const void *const hw) |
| 443 | { |
| 444 | ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN1; |
| 445 | } |
| 446 | |
| 447 | static inline void hri_dac_set_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) |
| 448 | { |
| 449 | ((Dac *)hw)->INTENSET.reg = mask; |
| 450 | } |
| 451 | |
| 452 | static inline hri_dac_intenset_reg_t hri_dac_get_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) |
| 453 | { |
| 454 | uint8_t tmp; |
| 455 | tmp = ((Dac *)hw)->INTENSET.reg; |
| 456 | tmp &= mask; |
| 457 | return tmp; |
| 458 | } |
| 459 | |
| 460 | static inline hri_dac_intenset_reg_t hri_dac_read_INTEN_reg(const void *const hw) |
| 461 | { |
| 462 | return ((Dac *)hw)->INTENSET.reg; |
| 463 | } |
| 464 | |
| 465 | static inline void hri_dac_write_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t data) |
| 466 | { |
| 467 | ((Dac *)hw)->INTENSET.reg = data; |
| 468 | ((Dac *)hw)->INTENCLR.reg = ~data; |
| 469 | } |
| 470 | |
| 471 | static inline void hri_dac_clear_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) |
| 472 | { |
| 473 | ((Dac *)hw)->INTENCLR.reg = mask; |
| 474 | } |
| 475 | |
| 476 | static inline bool hri_dac_get_STATUS_READY0_bit(const void *const hw) |
| 477 | { |
| 478 | return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY0) >> DAC_STATUS_READY0_Pos; |
| 479 | } |
| 480 | |
| 481 | static inline bool hri_dac_get_STATUS_READY1_bit(const void *const hw) |
| 482 | { |
| 483 | return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY1) >> DAC_STATUS_READY1_Pos; |
| 484 | } |
| 485 | |
| 486 | static inline bool hri_dac_get_STATUS_EOC0_bit(const void *const hw) |
| 487 | { |
| 488 | return (((Dac *)hw)->STATUS.reg & DAC_STATUS_EOC0) >> DAC_STATUS_EOC0_Pos; |
| 489 | } |
| 490 | |
| 491 | static inline bool hri_dac_get_STATUS_EOC1_bit(const void *const hw) |
| 492 | { |
| 493 | return (((Dac *)hw)->STATUS.reg & DAC_STATUS_EOC1) >> DAC_STATUS_EOC1_Pos; |
| 494 | } |
| 495 | |
| 496 | static inline hri_dac_status_reg_t hri_dac_get_STATUS_reg(const void *const hw, hri_dac_status_reg_t mask) |
| 497 | { |
| 498 | uint8_t tmp; |
| 499 | tmp = ((Dac *)hw)->STATUS.reg; |
| 500 | tmp &= mask; |
| 501 | return tmp; |
| 502 | } |
| 503 | |
| 504 | static inline hri_dac_status_reg_t hri_dac_read_STATUS_reg(const void *const hw) |
| 505 | { |
| 506 | return ((Dac *)hw)->STATUS.reg; |
| 507 | } |
| 508 | |
| 509 | static inline bool hri_dac_get_SYNCBUSY_SWRST_bit(const void *const hw) |
| 510 | { |
| 511 | return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_SWRST) >> DAC_SYNCBUSY_SWRST_Pos; |
| 512 | } |
| 513 | |
| 514 | static inline bool hri_dac_get_SYNCBUSY_ENABLE_bit(const void *const hw) |
| 515 | { |
| 516 | return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_ENABLE) >> DAC_SYNCBUSY_ENABLE_Pos; |
| 517 | } |
| 518 | |
| 519 | static inline bool hri_dac_get_SYNCBUSY_DATA0_bit(const void *const hw) |
| 520 | { |
| 521 | return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA0) >> DAC_SYNCBUSY_DATA0_Pos; |
| 522 | } |
| 523 | |
| 524 | static inline bool hri_dac_get_SYNCBUSY_DATA1_bit(const void *const hw) |
| 525 | { |
| 526 | return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA1) >> DAC_SYNCBUSY_DATA1_Pos; |
| 527 | } |
| 528 | |
| 529 | static inline bool hri_dac_get_SYNCBUSY_DATABUF0_bit(const void *const hw) |
| 530 | { |
| 531 | return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF0) >> DAC_SYNCBUSY_DATABUF0_Pos; |
| 532 | } |
| 533 | |
| 534 | static inline bool hri_dac_get_SYNCBUSY_DATABUF1_bit(const void *const hw) |
| 535 | { |
| 536 | return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF1) >> DAC_SYNCBUSY_DATABUF1_Pos; |
| 537 | } |
| 538 | |
| 539 | static inline hri_dac_syncbusy_reg_t hri_dac_get_SYNCBUSY_reg(const void *const hw, hri_dac_syncbusy_reg_t mask) |
| 540 | { |
| 541 | uint32_t tmp; |
| 542 | tmp = ((Dac *)hw)->SYNCBUSY.reg; |
| 543 | tmp &= mask; |
| 544 | return tmp; |
| 545 | } |
| 546 | |
| 547 | static inline hri_dac_syncbusy_reg_t hri_dac_read_SYNCBUSY_reg(const void *const hw) |
| 548 | { |
| 549 | return ((Dac *)hw)->SYNCBUSY.reg; |
| 550 | } |
| 551 | |
| 552 | static inline hri_dac_result_reg_t hri_dac_get_RESULT_RESULT_bf(const void *const hw, uint8_t index, |
| 553 | hri_dac_result_reg_t mask) |
| 554 | { |
| 555 | return (((Dac *)hw)->RESULT[index].reg & DAC_RESULT_RESULT(mask)) >> DAC_RESULT_RESULT_Pos; |
| 556 | } |
| 557 | |
| 558 | static inline hri_dac_result_reg_t hri_dac_read_RESULT_RESULT_bf(const void *const hw, uint8_t index) |
| 559 | { |
| 560 | return (((Dac *)hw)->RESULT[index].reg & DAC_RESULT_RESULT_Msk) >> DAC_RESULT_RESULT_Pos; |
| 561 | } |
| 562 | |
| 563 | static inline hri_dac_result_reg_t hri_dac_get_RESULT_reg(const void *const hw, uint8_t index, |
| 564 | hri_dac_result_reg_t mask) |
| 565 | { |
| 566 | uint16_t tmp; |
| 567 | tmp = ((Dac *)hw)->RESULT[index].reg; |
| 568 | tmp &= mask; |
| 569 | return tmp; |
| 570 | } |
| 571 | |
| 572 | static inline hri_dac_result_reg_t hri_dac_read_RESULT_reg(const void *const hw, uint8_t index) |
| 573 | { |
| 574 | return ((Dac *)hw)->RESULT[index].reg; |
| 575 | } |
| 576 | |
| 577 | static inline void hri_dac_set_CTRLA_SWRST_bit(const void *const hw) |
| 578 | { |
| 579 | DAC_CRITICAL_SECTION_ENTER(); |
| 580 | ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_SWRST; |
| 581 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); |
| 582 | DAC_CRITICAL_SECTION_LEAVE(); |
| 583 | } |
| 584 | |
| 585 | static inline bool hri_dac_get_CTRLA_SWRST_bit(const void *const hw) |
| 586 | { |
| 587 | uint8_t tmp; |
| 588 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); |
| 589 | tmp = ((Dac *)hw)->CTRLA.reg; |
| 590 | tmp = (tmp & DAC_CTRLA_SWRST) >> DAC_CTRLA_SWRST_Pos; |
| 591 | return (bool)tmp; |
| 592 | } |
| 593 | |
| 594 | static inline void hri_dac_set_CTRLA_ENABLE_bit(const void *const hw) |
| 595 | { |
| 596 | DAC_CRITICAL_SECTION_ENTER(); |
| 597 | ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_ENABLE; |
| 598 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); |
| 599 | DAC_CRITICAL_SECTION_LEAVE(); |
| 600 | } |
| 601 | |
| 602 | static inline bool hri_dac_get_CTRLA_ENABLE_bit(const void *const hw) |
| 603 | { |
| 604 | uint8_t tmp; |
| 605 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); |
| 606 | tmp = ((Dac *)hw)->CTRLA.reg; |
| 607 | tmp = (tmp & DAC_CTRLA_ENABLE) >> DAC_CTRLA_ENABLE_Pos; |
| 608 | return (bool)tmp; |
| 609 | } |
| 610 | |
| 611 | static inline void hri_dac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) |
| 612 | { |
| 613 | uint8_t tmp; |
| 614 | DAC_CRITICAL_SECTION_ENTER(); |
| 615 | tmp = ((Dac *)hw)->CTRLA.reg; |
| 616 | tmp &= ~DAC_CTRLA_ENABLE; |
| 617 | tmp |= value << DAC_CTRLA_ENABLE_Pos; |
| 618 | ((Dac *)hw)->CTRLA.reg = tmp; |
| 619 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); |
| 620 | DAC_CRITICAL_SECTION_LEAVE(); |
| 621 | } |
| 622 | |
| 623 | static inline void hri_dac_clear_CTRLA_ENABLE_bit(const void *const hw) |
| 624 | { |
| 625 | DAC_CRITICAL_SECTION_ENTER(); |
| 626 | ((Dac *)hw)->CTRLA.reg &= ~DAC_CTRLA_ENABLE; |
| 627 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); |
| 628 | DAC_CRITICAL_SECTION_LEAVE(); |
| 629 | } |
| 630 | |
| 631 | static inline void hri_dac_toggle_CTRLA_ENABLE_bit(const void *const hw) |
| 632 | { |
| 633 | DAC_CRITICAL_SECTION_ENTER(); |
| 634 | ((Dac *)hw)->CTRLA.reg ^= DAC_CTRLA_ENABLE; |
| 635 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); |
| 636 | DAC_CRITICAL_SECTION_LEAVE(); |
| 637 | } |
| 638 | |
| 639 | static inline void hri_dac_set_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) |
| 640 | { |
| 641 | DAC_CRITICAL_SECTION_ENTER(); |
| 642 | ((Dac *)hw)->CTRLA.reg |= mask; |
| 643 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); |
| 644 | DAC_CRITICAL_SECTION_LEAVE(); |
| 645 | } |
| 646 | |
| 647 | static inline hri_dac_ctrla_reg_t hri_dac_get_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) |
| 648 | { |
| 649 | uint8_t tmp; |
| 650 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); |
| 651 | tmp = ((Dac *)hw)->CTRLA.reg; |
| 652 | tmp &= mask; |
| 653 | return tmp; |
| 654 | } |
| 655 | |
| 656 | static inline void hri_dac_write_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t data) |
| 657 | { |
| 658 | DAC_CRITICAL_SECTION_ENTER(); |
| 659 | ((Dac *)hw)->CTRLA.reg = data; |
| 660 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); |
| 661 | DAC_CRITICAL_SECTION_LEAVE(); |
| 662 | } |
| 663 | |
| 664 | static inline void hri_dac_clear_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) |
| 665 | { |
| 666 | DAC_CRITICAL_SECTION_ENTER(); |
| 667 | ((Dac *)hw)->CTRLA.reg &= ~mask; |
| 668 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); |
| 669 | DAC_CRITICAL_SECTION_LEAVE(); |
| 670 | } |
| 671 | |
| 672 | static inline void hri_dac_toggle_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) |
| 673 | { |
| 674 | DAC_CRITICAL_SECTION_ENTER(); |
| 675 | ((Dac *)hw)->CTRLA.reg ^= mask; |
| 676 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); |
| 677 | DAC_CRITICAL_SECTION_LEAVE(); |
| 678 | } |
| 679 | |
| 680 | static inline hri_dac_ctrla_reg_t hri_dac_read_CTRLA_reg(const void *const hw) |
| 681 | { |
| 682 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); |
| 683 | return ((Dac *)hw)->CTRLA.reg; |
| 684 | } |
| 685 | |
| 686 | static inline void hri_dac_set_CTRLB_DIFF_bit(const void *const hw) |
| 687 | { |
| 688 | DAC_CRITICAL_SECTION_ENTER(); |
| 689 | ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_DIFF; |
| 690 | DAC_CRITICAL_SECTION_LEAVE(); |
| 691 | } |
| 692 | |
| 693 | static inline bool hri_dac_get_CTRLB_DIFF_bit(const void *const hw) |
| 694 | { |
| 695 | uint8_t tmp; |
| 696 | tmp = ((Dac *)hw)->CTRLB.reg; |
| 697 | tmp = (tmp & DAC_CTRLB_DIFF) >> DAC_CTRLB_DIFF_Pos; |
| 698 | return (bool)tmp; |
| 699 | } |
| 700 | |
| 701 | static inline void hri_dac_write_CTRLB_DIFF_bit(const void *const hw, bool value) |
| 702 | { |
| 703 | uint8_t tmp; |
| 704 | DAC_CRITICAL_SECTION_ENTER(); |
| 705 | tmp = ((Dac *)hw)->CTRLB.reg; |
| 706 | tmp &= ~DAC_CTRLB_DIFF; |
| 707 | tmp |= value << DAC_CTRLB_DIFF_Pos; |
| 708 | ((Dac *)hw)->CTRLB.reg = tmp; |
| 709 | DAC_CRITICAL_SECTION_LEAVE(); |
| 710 | } |
| 711 | |
| 712 | static inline void hri_dac_clear_CTRLB_DIFF_bit(const void *const hw) |
| 713 | { |
| 714 | DAC_CRITICAL_SECTION_ENTER(); |
| 715 | ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_DIFF; |
| 716 | DAC_CRITICAL_SECTION_LEAVE(); |
| 717 | } |
| 718 | |
| 719 | static inline void hri_dac_toggle_CTRLB_DIFF_bit(const void *const hw) |
| 720 | { |
| 721 | DAC_CRITICAL_SECTION_ENTER(); |
| 722 | ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_DIFF; |
| 723 | DAC_CRITICAL_SECTION_LEAVE(); |
| 724 | } |
| 725 | |
| 726 | static inline void hri_dac_set_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) |
| 727 | { |
| 728 | DAC_CRITICAL_SECTION_ENTER(); |
| 729 | ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_REFSEL(mask); |
| 730 | DAC_CRITICAL_SECTION_LEAVE(); |
| 731 | } |
| 732 | |
| 733 | static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) |
| 734 | { |
| 735 | uint8_t tmp; |
| 736 | tmp = ((Dac *)hw)->CTRLB.reg; |
| 737 | tmp = (tmp & DAC_CTRLB_REFSEL(mask)) >> DAC_CTRLB_REFSEL_Pos; |
| 738 | return tmp; |
| 739 | } |
| 740 | |
| 741 | static inline void hri_dac_write_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t data) |
| 742 | { |
| 743 | uint8_t tmp; |
| 744 | DAC_CRITICAL_SECTION_ENTER(); |
| 745 | tmp = ((Dac *)hw)->CTRLB.reg; |
| 746 | tmp &= ~DAC_CTRLB_REFSEL_Msk; |
| 747 | tmp |= DAC_CTRLB_REFSEL(data); |
| 748 | ((Dac *)hw)->CTRLB.reg = tmp; |
| 749 | DAC_CRITICAL_SECTION_LEAVE(); |
| 750 | } |
| 751 | |
| 752 | static inline void hri_dac_clear_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) |
| 753 | { |
| 754 | DAC_CRITICAL_SECTION_ENTER(); |
| 755 | ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_REFSEL(mask); |
| 756 | DAC_CRITICAL_SECTION_LEAVE(); |
| 757 | } |
| 758 | |
| 759 | static inline void hri_dac_toggle_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) |
| 760 | { |
| 761 | DAC_CRITICAL_SECTION_ENTER(); |
| 762 | ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_REFSEL(mask); |
| 763 | DAC_CRITICAL_SECTION_LEAVE(); |
| 764 | } |
| 765 | |
| 766 | static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_REFSEL_bf(const void *const hw) |
| 767 | { |
| 768 | uint8_t tmp; |
| 769 | tmp = ((Dac *)hw)->CTRLB.reg; |
| 770 | tmp = (tmp & DAC_CTRLB_REFSEL_Msk) >> DAC_CTRLB_REFSEL_Pos; |
| 771 | return tmp; |
| 772 | } |
| 773 | |
| 774 | static inline void hri_dac_set_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) |
| 775 | { |
| 776 | DAC_CRITICAL_SECTION_ENTER(); |
| 777 | ((Dac *)hw)->CTRLB.reg |= mask; |
| 778 | DAC_CRITICAL_SECTION_LEAVE(); |
| 779 | } |
| 780 | |
| 781 | static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) |
| 782 | { |
| 783 | uint8_t tmp; |
| 784 | tmp = ((Dac *)hw)->CTRLB.reg; |
| 785 | tmp &= mask; |
| 786 | return tmp; |
| 787 | } |
| 788 | |
| 789 | static inline void hri_dac_write_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t data) |
| 790 | { |
| 791 | DAC_CRITICAL_SECTION_ENTER(); |
| 792 | ((Dac *)hw)->CTRLB.reg = data; |
| 793 | DAC_CRITICAL_SECTION_LEAVE(); |
| 794 | } |
| 795 | |
| 796 | static inline void hri_dac_clear_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) |
| 797 | { |
| 798 | DAC_CRITICAL_SECTION_ENTER(); |
| 799 | ((Dac *)hw)->CTRLB.reg &= ~mask; |
| 800 | DAC_CRITICAL_SECTION_LEAVE(); |
| 801 | } |
| 802 | |
| 803 | static inline void hri_dac_toggle_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) |
| 804 | { |
| 805 | DAC_CRITICAL_SECTION_ENTER(); |
| 806 | ((Dac *)hw)->CTRLB.reg ^= mask; |
| 807 | DAC_CRITICAL_SECTION_LEAVE(); |
| 808 | } |
| 809 | |
| 810 | static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_reg(const void *const hw) |
| 811 | { |
| 812 | return ((Dac *)hw)->CTRLB.reg; |
| 813 | } |
| 814 | |
| 815 | static inline void hri_dac_set_EVCTRL_STARTEI0_bit(const void *const hw) |
| 816 | { |
| 817 | DAC_CRITICAL_SECTION_ENTER(); |
| 818 | ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI0; |
| 819 | DAC_CRITICAL_SECTION_LEAVE(); |
| 820 | } |
| 821 | |
| 822 | static inline bool hri_dac_get_EVCTRL_STARTEI0_bit(const void *const hw) |
| 823 | { |
| 824 | uint8_t tmp; |
| 825 | tmp = ((Dac *)hw)->EVCTRL.reg; |
| 826 | tmp = (tmp & DAC_EVCTRL_STARTEI0) >> DAC_EVCTRL_STARTEI0_Pos; |
| 827 | return (bool)tmp; |
| 828 | } |
| 829 | |
| 830 | static inline void hri_dac_write_EVCTRL_STARTEI0_bit(const void *const hw, bool value) |
| 831 | { |
| 832 | uint8_t tmp; |
| 833 | DAC_CRITICAL_SECTION_ENTER(); |
| 834 | tmp = ((Dac *)hw)->EVCTRL.reg; |
| 835 | tmp &= ~DAC_EVCTRL_STARTEI0; |
| 836 | tmp |= value << DAC_EVCTRL_STARTEI0_Pos; |
| 837 | ((Dac *)hw)->EVCTRL.reg = tmp; |
| 838 | DAC_CRITICAL_SECTION_LEAVE(); |
| 839 | } |
| 840 | |
| 841 | static inline void hri_dac_clear_EVCTRL_STARTEI0_bit(const void *const hw) |
| 842 | { |
| 843 | DAC_CRITICAL_SECTION_ENTER(); |
| 844 | ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI0; |
| 845 | DAC_CRITICAL_SECTION_LEAVE(); |
| 846 | } |
| 847 | |
| 848 | static inline void hri_dac_toggle_EVCTRL_STARTEI0_bit(const void *const hw) |
| 849 | { |
| 850 | DAC_CRITICAL_SECTION_ENTER(); |
| 851 | ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI0; |
| 852 | DAC_CRITICAL_SECTION_LEAVE(); |
| 853 | } |
| 854 | |
| 855 | static inline void hri_dac_set_EVCTRL_STARTEI1_bit(const void *const hw) |
| 856 | { |
| 857 | DAC_CRITICAL_SECTION_ENTER(); |
| 858 | ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI1; |
| 859 | DAC_CRITICAL_SECTION_LEAVE(); |
| 860 | } |
| 861 | |
| 862 | static inline bool hri_dac_get_EVCTRL_STARTEI1_bit(const void *const hw) |
| 863 | { |
| 864 | uint8_t tmp; |
| 865 | tmp = ((Dac *)hw)->EVCTRL.reg; |
| 866 | tmp = (tmp & DAC_EVCTRL_STARTEI1) >> DAC_EVCTRL_STARTEI1_Pos; |
| 867 | return (bool)tmp; |
| 868 | } |
| 869 | |
| 870 | static inline void hri_dac_write_EVCTRL_STARTEI1_bit(const void *const hw, bool value) |
| 871 | { |
| 872 | uint8_t tmp; |
| 873 | DAC_CRITICAL_SECTION_ENTER(); |
| 874 | tmp = ((Dac *)hw)->EVCTRL.reg; |
| 875 | tmp &= ~DAC_EVCTRL_STARTEI1; |
| 876 | tmp |= value << DAC_EVCTRL_STARTEI1_Pos; |
| 877 | ((Dac *)hw)->EVCTRL.reg = tmp; |
| 878 | DAC_CRITICAL_SECTION_LEAVE(); |
| 879 | } |
| 880 | |
| 881 | static inline void hri_dac_clear_EVCTRL_STARTEI1_bit(const void *const hw) |
| 882 | { |
| 883 | DAC_CRITICAL_SECTION_ENTER(); |
| 884 | ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI1; |
| 885 | DAC_CRITICAL_SECTION_LEAVE(); |
| 886 | } |
| 887 | |
| 888 | static inline void hri_dac_toggle_EVCTRL_STARTEI1_bit(const void *const hw) |
| 889 | { |
| 890 | DAC_CRITICAL_SECTION_ENTER(); |
| 891 | ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI1; |
| 892 | DAC_CRITICAL_SECTION_LEAVE(); |
| 893 | } |
| 894 | |
| 895 | static inline void hri_dac_set_EVCTRL_EMPTYEO0_bit(const void *const hw) |
| 896 | { |
| 897 | DAC_CRITICAL_SECTION_ENTER(); |
| 898 | ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO0; |
| 899 | DAC_CRITICAL_SECTION_LEAVE(); |
| 900 | } |
| 901 | |
| 902 | static inline bool hri_dac_get_EVCTRL_EMPTYEO0_bit(const void *const hw) |
| 903 | { |
| 904 | uint8_t tmp; |
| 905 | tmp = ((Dac *)hw)->EVCTRL.reg; |
| 906 | tmp = (tmp & DAC_EVCTRL_EMPTYEO0) >> DAC_EVCTRL_EMPTYEO0_Pos; |
| 907 | return (bool)tmp; |
| 908 | } |
| 909 | |
| 910 | static inline void hri_dac_write_EVCTRL_EMPTYEO0_bit(const void *const hw, bool value) |
| 911 | { |
| 912 | uint8_t tmp; |
| 913 | DAC_CRITICAL_SECTION_ENTER(); |
| 914 | tmp = ((Dac *)hw)->EVCTRL.reg; |
| 915 | tmp &= ~DAC_EVCTRL_EMPTYEO0; |
| 916 | tmp |= value << DAC_EVCTRL_EMPTYEO0_Pos; |
| 917 | ((Dac *)hw)->EVCTRL.reg = tmp; |
| 918 | DAC_CRITICAL_SECTION_LEAVE(); |
| 919 | } |
| 920 | |
| 921 | static inline void hri_dac_clear_EVCTRL_EMPTYEO0_bit(const void *const hw) |
| 922 | { |
| 923 | DAC_CRITICAL_SECTION_ENTER(); |
| 924 | ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO0; |
| 925 | DAC_CRITICAL_SECTION_LEAVE(); |
| 926 | } |
| 927 | |
| 928 | static inline void hri_dac_toggle_EVCTRL_EMPTYEO0_bit(const void *const hw) |
| 929 | { |
| 930 | DAC_CRITICAL_SECTION_ENTER(); |
| 931 | ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO0; |
| 932 | DAC_CRITICAL_SECTION_LEAVE(); |
| 933 | } |
| 934 | |
| 935 | static inline void hri_dac_set_EVCTRL_EMPTYEO1_bit(const void *const hw) |
| 936 | { |
| 937 | DAC_CRITICAL_SECTION_ENTER(); |
| 938 | ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO1; |
| 939 | DAC_CRITICAL_SECTION_LEAVE(); |
| 940 | } |
| 941 | |
| 942 | static inline bool hri_dac_get_EVCTRL_EMPTYEO1_bit(const void *const hw) |
| 943 | { |
| 944 | uint8_t tmp; |
| 945 | tmp = ((Dac *)hw)->EVCTRL.reg; |
| 946 | tmp = (tmp & DAC_EVCTRL_EMPTYEO1) >> DAC_EVCTRL_EMPTYEO1_Pos; |
| 947 | return (bool)tmp; |
| 948 | } |
| 949 | |
| 950 | static inline void hri_dac_write_EVCTRL_EMPTYEO1_bit(const void *const hw, bool value) |
| 951 | { |
| 952 | uint8_t tmp; |
| 953 | DAC_CRITICAL_SECTION_ENTER(); |
| 954 | tmp = ((Dac *)hw)->EVCTRL.reg; |
| 955 | tmp &= ~DAC_EVCTRL_EMPTYEO1; |
| 956 | tmp |= value << DAC_EVCTRL_EMPTYEO1_Pos; |
| 957 | ((Dac *)hw)->EVCTRL.reg = tmp; |
| 958 | DAC_CRITICAL_SECTION_LEAVE(); |
| 959 | } |
| 960 | |
| 961 | static inline void hri_dac_clear_EVCTRL_EMPTYEO1_bit(const void *const hw) |
| 962 | { |
| 963 | DAC_CRITICAL_SECTION_ENTER(); |
| 964 | ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO1; |
| 965 | DAC_CRITICAL_SECTION_LEAVE(); |
| 966 | } |
| 967 | |
| 968 | static inline void hri_dac_toggle_EVCTRL_EMPTYEO1_bit(const void *const hw) |
| 969 | { |
| 970 | DAC_CRITICAL_SECTION_ENTER(); |
| 971 | ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO1; |
| 972 | DAC_CRITICAL_SECTION_LEAVE(); |
| 973 | } |
| 974 | |
| 975 | static inline void hri_dac_set_EVCTRL_INVEI0_bit(const void *const hw) |
| 976 | { |
| 977 | DAC_CRITICAL_SECTION_ENTER(); |
| 978 | ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI0; |
| 979 | DAC_CRITICAL_SECTION_LEAVE(); |
| 980 | } |
| 981 | |
| 982 | static inline bool hri_dac_get_EVCTRL_INVEI0_bit(const void *const hw) |
| 983 | { |
| 984 | uint8_t tmp; |
| 985 | tmp = ((Dac *)hw)->EVCTRL.reg; |
| 986 | tmp = (tmp & DAC_EVCTRL_INVEI0) >> DAC_EVCTRL_INVEI0_Pos; |
| 987 | return (bool)tmp; |
| 988 | } |
| 989 | |
| 990 | static inline void hri_dac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value) |
| 991 | { |
| 992 | uint8_t tmp; |
| 993 | DAC_CRITICAL_SECTION_ENTER(); |
| 994 | tmp = ((Dac *)hw)->EVCTRL.reg; |
| 995 | tmp &= ~DAC_EVCTRL_INVEI0; |
| 996 | tmp |= value << DAC_EVCTRL_INVEI0_Pos; |
| 997 | ((Dac *)hw)->EVCTRL.reg = tmp; |
| 998 | DAC_CRITICAL_SECTION_LEAVE(); |
| 999 | } |
| 1000 | |
| 1001 | static inline void hri_dac_clear_EVCTRL_INVEI0_bit(const void *const hw) |
| 1002 | { |
| 1003 | DAC_CRITICAL_SECTION_ENTER(); |
| 1004 | ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI0; |
| 1005 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1006 | } |
| 1007 | |
| 1008 | static inline void hri_dac_toggle_EVCTRL_INVEI0_bit(const void *const hw) |
| 1009 | { |
| 1010 | DAC_CRITICAL_SECTION_ENTER(); |
| 1011 | ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI0; |
| 1012 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1013 | } |
| 1014 | |
| 1015 | static inline void hri_dac_set_EVCTRL_INVEI1_bit(const void *const hw) |
| 1016 | { |
| 1017 | DAC_CRITICAL_SECTION_ENTER(); |
| 1018 | ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI1; |
| 1019 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1020 | } |
| 1021 | |
| 1022 | static inline bool hri_dac_get_EVCTRL_INVEI1_bit(const void *const hw) |
| 1023 | { |
| 1024 | uint8_t tmp; |
| 1025 | tmp = ((Dac *)hw)->EVCTRL.reg; |
| 1026 | tmp = (tmp & DAC_EVCTRL_INVEI1) >> DAC_EVCTRL_INVEI1_Pos; |
| 1027 | return (bool)tmp; |
| 1028 | } |
| 1029 | |
| 1030 | static inline void hri_dac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value) |
| 1031 | { |
| 1032 | uint8_t tmp; |
| 1033 | DAC_CRITICAL_SECTION_ENTER(); |
| 1034 | tmp = ((Dac *)hw)->EVCTRL.reg; |
| 1035 | tmp &= ~DAC_EVCTRL_INVEI1; |
| 1036 | tmp |= value << DAC_EVCTRL_INVEI1_Pos; |
| 1037 | ((Dac *)hw)->EVCTRL.reg = tmp; |
| 1038 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1039 | } |
| 1040 | |
| 1041 | static inline void hri_dac_clear_EVCTRL_INVEI1_bit(const void *const hw) |
| 1042 | { |
| 1043 | DAC_CRITICAL_SECTION_ENTER(); |
| 1044 | ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI1; |
| 1045 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1046 | } |
| 1047 | |
| 1048 | static inline void hri_dac_toggle_EVCTRL_INVEI1_bit(const void *const hw) |
| 1049 | { |
| 1050 | DAC_CRITICAL_SECTION_ENTER(); |
| 1051 | ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI1; |
| 1052 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1053 | } |
| 1054 | |
| 1055 | static inline void hri_dac_set_EVCTRL_RESRDYEO0_bit(const void *const hw) |
| 1056 | { |
| 1057 | DAC_CRITICAL_SECTION_ENTER(); |
| 1058 | ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_RESRDYEO0; |
| 1059 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1060 | } |
| 1061 | |
| 1062 | static inline bool hri_dac_get_EVCTRL_RESRDYEO0_bit(const void *const hw) |
| 1063 | { |
| 1064 | uint8_t tmp; |
| 1065 | tmp = ((Dac *)hw)->EVCTRL.reg; |
| 1066 | tmp = (tmp & DAC_EVCTRL_RESRDYEO0) >> DAC_EVCTRL_RESRDYEO0_Pos; |
| 1067 | return (bool)tmp; |
| 1068 | } |
| 1069 | |
| 1070 | static inline void hri_dac_write_EVCTRL_RESRDYEO0_bit(const void *const hw, bool value) |
| 1071 | { |
| 1072 | uint8_t tmp; |
| 1073 | DAC_CRITICAL_SECTION_ENTER(); |
| 1074 | tmp = ((Dac *)hw)->EVCTRL.reg; |
| 1075 | tmp &= ~DAC_EVCTRL_RESRDYEO0; |
| 1076 | tmp |= value << DAC_EVCTRL_RESRDYEO0_Pos; |
| 1077 | ((Dac *)hw)->EVCTRL.reg = tmp; |
| 1078 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1079 | } |
| 1080 | |
| 1081 | static inline void hri_dac_clear_EVCTRL_RESRDYEO0_bit(const void *const hw) |
| 1082 | { |
| 1083 | DAC_CRITICAL_SECTION_ENTER(); |
| 1084 | ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_RESRDYEO0; |
| 1085 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1086 | } |
| 1087 | |
| 1088 | static inline void hri_dac_toggle_EVCTRL_RESRDYEO0_bit(const void *const hw) |
| 1089 | { |
| 1090 | DAC_CRITICAL_SECTION_ENTER(); |
| 1091 | ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_RESRDYEO0; |
| 1092 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1093 | } |
| 1094 | |
| 1095 | static inline void hri_dac_set_EVCTRL_RESRDYEO1_bit(const void *const hw) |
| 1096 | { |
| 1097 | DAC_CRITICAL_SECTION_ENTER(); |
| 1098 | ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_RESRDYEO1; |
| 1099 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1100 | } |
| 1101 | |
| 1102 | static inline bool hri_dac_get_EVCTRL_RESRDYEO1_bit(const void *const hw) |
| 1103 | { |
| 1104 | uint8_t tmp; |
| 1105 | tmp = ((Dac *)hw)->EVCTRL.reg; |
| 1106 | tmp = (tmp & DAC_EVCTRL_RESRDYEO1) >> DAC_EVCTRL_RESRDYEO1_Pos; |
| 1107 | return (bool)tmp; |
| 1108 | } |
| 1109 | |
| 1110 | static inline void hri_dac_write_EVCTRL_RESRDYEO1_bit(const void *const hw, bool value) |
| 1111 | { |
| 1112 | uint8_t tmp; |
| 1113 | DAC_CRITICAL_SECTION_ENTER(); |
| 1114 | tmp = ((Dac *)hw)->EVCTRL.reg; |
| 1115 | tmp &= ~DAC_EVCTRL_RESRDYEO1; |
| 1116 | tmp |= value << DAC_EVCTRL_RESRDYEO1_Pos; |
| 1117 | ((Dac *)hw)->EVCTRL.reg = tmp; |
| 1118 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1119 | } |
| 1120 | |
| 1121 | static inline void hri_dac_clear_EVCTRL_RESRDYEO1_bit(const void *const hw) |
| 1122 | { |
| 1123 | DAC_CRITICAL_SECTION_ENTER(); |
| 1124 | ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_RESRDYEO1; |
| 1125 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1126 | } |
| 1127 | |
| 1128 | static inline void hri_dac_toggle_EVCTRL_RESRDYEO1_bit(const void *const hw) |
| 1129 | { |
| 1130 | DAC_CRITICAL_SECTION_ENTER(); |
| 1131 | ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_RESRDYEO1; |
| 1132 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1133 | } |
| 1134 | |
| 1135 | static inline void hri_dac_set_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) |
| 1136 | { |
| 1137 | DAC_CRITICAL_SECTION_ENTER(); |
| 1138 | ((Dac *)hw)->EVCTRL.reg |= mask; |
| 1139 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1140 | } |
| 1141 | |
| 1142 | static inline hri_dac_evctrl_reg_t hri_dac_get_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) |
| 1143 | { |
| 1144 | uint8_t tmp; |
| 1145 | tmp = ((Dac *)hw)->EVCTRL.reg; |
| 1146 | tmp &= mask; |
| 1147 | return tmp; |
| 1148 | } |
| 1149 | |
| 1150 | static inline void hri_dac_write_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t data) |
| 1151 | { |
| 1152 | DAC_CRITICAL_SECTION_ENTER(); |
| 1153 | ((Dac *)hw)->EVCTRL.reg = data; |
| 1154 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1155 | } |
| 1156 | |
| 1157 | static inline void hri_dac_clear_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) |
| 1158 | { |
| 1159 | DAC_CRITICAL_SECTION_ENTER(); |
| 1160 | ((Dac *)hw)->EVCTRL.reg &= ~mask; |
| 1161 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1162 | } |
| 1163 | |
| 1164 | static inline void hri_dac_toggle_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) |
| 1165 | { |
| 1166 | DAC_CRITICAL_SECTION_ENTER(); |
| 1167 | ((Dac *)hw)->EVCTRL.reg ^= mask; |
| 1168 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1169 | } |
| 1170 | |
| 1171 | static inline hri_dac_evctrl_reg_t hri_dac_read_EVCTRL_reg(const void *const hw) |
| 1172 | { |
| 1173 | return ((Dac *)hw)->EVCTRL.reg; |
| 1174 | } |
| 1175 | |
| 1176 | static inline void hri_dac_set_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) |
| 1177 | { |
| 1178 | DAC_CRITICAL_SECTION_ENTER(); |
| 1179 | ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_LEFTADJ; |
| 1180 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); |
| 1181 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1182 | } |
| 1183 | |
| 1184 | static inline bool hri_dac_get_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) |
| 1185 | { |
| 1186 | uint16_t tmp; |
| 1187 | tmp = ((Dac *)hw)->DACCTRL[index].reg; |
| 1188 | tmp = (tmp & DAC_DACCTRL_LEFTADJ) >> DAC_DACCTRL_LEFTADJ_Pos; |
| 1189 | return (bool)tmp; |
| 1190 | } |
| 1191 | |
| 1192 | static inline void hri_dac_write_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index, bool value) |
| 1193 | { |
| 1194 | uint16_t tmp; |
| 1195 | DAC_CRITICAL_SECTION_ENTER(); |
| 1196 | tmp = ((Dac *)hw)->DACCTRL[index].reg; |
| 1197 | tmp &= ~DAC_DACCTRL_LEFTADJ; |
| 1198 | tmp |= value << DAC_DACCTRL_LEFTADJ_Pos; |
| 1199 | ((Dac *)hw)->DACCTRL[index].reg = tmp; |
| 1200 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); |
| 1201 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1202 | } |
| 1203 | |
| 1204 | static inline void hri_dac_clear_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) |
| 1205 | { |
| 1206 | DAC_CRITICAL_SECTION_ENTER(); |
| 1207 | ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_LEFTADJ; |
| 1208 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); |
| 1209 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1210 | } |
| 1211 | |
| 1212 | static inline void hri_dac_toggle_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) |
| 1213 | { |
| 1214 | DAC_CRITICAL_SECTION_ENTER(); |
| 1215 | ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_LEFTADJ; |
| 1216 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); |
| 1217 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1218 | } |
| 1219 | |
| 1220 | static inline void hri_dac_set_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) |
| 1221 | { |
| 1222 | DAC_CRITICAL_SECTION_ENTER(); |
| 1223 | ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_ENABLE; |
| 1224 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); |
| 1225 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1226 | } |
| 1227 | |
| 1228 | static inline bool hri_dac_get_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) |
| 1229 | { |
| 1230 | uint16_t tmp; |
| 1231 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); |
| 1232 | tmp = ((Dac *)hw)->DACCTRL[index].reg; |
| 1233 | tmp = (tmp & DAC_DACCTRL_ENABLE) >> DAC_DACCTRL_ENABLE_Pos; |
| 1234 | return (bool)tmp; |
| 1235 | } |
| 1236 | |
| 1237 | static inline void hri_dac_write_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) |
| 1238 | { |
| 1239 | uint16_t tmp; |
| 1240 | DAC_CRITICAL_SECTION_ENTER(); |
| 1241 | tmp = ((Dac *)hw)->DACCTRL[index].reg; |
| 1242 | tmp &= ~DAC_DACCTRL_ENABLE; |
| 1243 | tmp |= value << DAC_DACCTRL_ENABLE_Pos; |
| 1244 | ((Dac *)hw)->DACCTRL[index].reg = tmp; |
| 1245 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); |
| 1246 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1247 | } |
| 1248 | |
| 1249 | static inline void hri_dac_clear_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) |
| 1250 | { |
| 1251 | DAC_CRITICAL_SECTION_ENTER(); |
| 1252 | ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_ENABLE; |
| 1253 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); |
| 1254 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1255 | } |
| 1256 | |
| 1257 | static inline void hri_dac_toggle_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) |
| 1258 | { |
| 1259 | DAC_CRITICAL_SECTION_ENTER(); |
| 1260 | ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_ENABLE; |
| 1261 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); |
| 1262 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1263 | } |
| 1264 | |
| 1265 | static inline void hri_dac_set_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) |
| 1266 | { |
| 1267 | DAC_CRITICAL_SECTION_ENTER(); |
| 1268 | ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_FEXT; |
| 1269 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); |
| 1270 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1271 | } |
| 1272 | |
| 1273 | static inline bool hri_dac_get_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) |
| 1274 | { |
| 1275 | uint16_t tmp; |
| 1276 | tmp = ((Dac *)hw)->DACCTRL[index].reg; |
| 1277 | tmp = (tmp & DAC_DACCTRL_FEXT) >> DAC_DACCTRL_FEXT_Pos; |
| 1278 | return (bool)tmp; |
| 1279 | } |
| 1280 | |
| 1281 | static inline void hri_dac_write_DACCTRL_FEXT_bit(const void *const hw, uint8_t index, bool value) |
| 1282 | { |
| 1283 | uint16_t tmp; |
| 1284 | DAC_CRITICAL_SECTION_ENTER(); |
| 1285 | tmp = ((Dac *)hw)->DACCTRL[index].reg; |
| 1286 | tmp &= ~DAC_DACCTRL_FEXT; |
| 1287 | tmp |= value << DAC_DACCTRL_FEXT_Pos; |
| 1288 | ((Dac *)hw)->DACCTRL[index].reg = tmp; |
| 1289 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); |
| 1290 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1291 | } |
| 1292 | |
| 1293 | static inline void hri_dac_clear_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) |
| 1294 | { |
| 1295 | DAC_CRITICAL_SECTION_ENTER(); |
| 1296 | ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_FEXT; |
| 1297 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); |
| 1298 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1299 | } |
| 1300 | |
| 1301 | static inline void hri_dac_toggle_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) |
| 1302 | { |
| 1303 | DAC_CRITICAL_SECTION_ENTER(); |
| 1304 | ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_FEXT; |
| 1305 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); |
| 1306 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1307 | } |
| 1308 | |
| 1309 | static inline void hri_dac_set_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) |
| 1310 | { |
| 1311 | DAC_CRITICAL_SECTION_ENTER(); |
| 1312 | ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_RUNSTDBY; |
| 1313 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); |
| 1314 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1315 | } |
| 1316 | |
| 1317 | static inline bool hri_dac_get_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) |
| 1318 | { |
| 1319 | uint16_t tmp; |
| 1320 | tmp = ((Dac *)hw)->DACCTRL[index].reg; |
| 1321 | tmp = (tmp & DAC_DACCTRL_RUNSTDBY) >> DAC_DACCTRL_RUNSTDBY_Pos; |
| 1322 | return (bool)tmp; |
| 1323 | } |
| 1324 | |
| 1325 | static inline void hri_dac_write_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) |
| 1326 | { |
| 1327 | uint16_t tmp; |
| 1328 | DAC_CRITICAL_SECTION_ENTER(); |
| 1329 | tmp = ((Dac *)hw)->DACCTRL[index].reg; |
| 1330 | tmp &= ~DAC_DACCTRL_RUNSTDBY; |
| 1331 | tmp |= value << DAC_DACCTRL_RUNSTDBY_Pos; |
| 1332 | ((Dac *)hw)->DACCTRL[index].reg = tmp; |
| 1333 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); |
| 1334 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1335 | } |
| 1336 | |
| 1337 | static inline void hri_dac_clear_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) |
| 1338 | { |
| 1339 | DAC_CRITICAL_SECTION_ENTER(); |
| 1340 | ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_RUNSTDBY; |
| 1341 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); |
| 1342 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1343 | } |
| 1344 | |
| 1345 | static inline void hri_dac_toggle_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) |
| 1346 | { |
| 1347 | DAC_CRITICAL_SECTION_ENTER(); |
| 1348 | ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_RUNSTDBY; |
| 1349 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); |
| 1350 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1351 | } |
| 1352 | |
| 1353 | static inline void hri_dac_set_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) |
| 1354 | { |
| 1355 | DAC_CRITICAL_SECTION_ENTER(); |
| 1356 | ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_DITHER; |
| 1357 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); |
| 1358 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1359 | } |
| 1360 | |
| 1361 | static inline bool hri_dac_get_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) |
| 1362 | { |
| 1363 | uint16_t tmp; |
| 1364 | tmp = ((Dac *)hw)->DACCTRL[index].reg; |
| 1365 | tmp = (tmp & DAC_DACCTRL_DITHER) >> DAC_DACCTRL_DITHER_Pos; |
| 1366 | return (bool)tmp; |
| 1367 | } |
| 1368 | |
| 1369 | static inline void hri_dac_write_DACCTRL_DITHER_bit(const void *const hw, uint8_t index, bool value) |
| 1370 | { |
| 1371 | uint16_t tmp; |
| 1372 | DAC_CRITICAL_SECTION_ENTER(); |
| 1373 | tmp = ((Dac *)hw)->DACCTRL[index].reg; |
| 1374 | tmp &= ~DAC_DACCTRL_DITHER; |
| 1375 | tmp |= value << DAC_DACCTRL_DITHER_Pos; |
| 1376 | ((Dac *)hw)->DACCTRL[index].reg = tmp; |
| 1377 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); |
| 1378 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1379 | } |
| 1380 | |
| 1381 | static inline void hri_dac_clear_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) |
| 1382 | { |
| 1383 | DAC_CRITICAL_SECTION_ENTER(); |
| 1384 | ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_DITHER; |
| 1385 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); |
| 1386 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1387 | } |
| 1388 | |
| 1389 | static inline void hri_dac_toggle_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) |
| 1390 | { |
| 1391 | DAC_CRITICAL_SECTION_ENTER(); |
| 1392 | ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_DITHER; |
| 1393 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); |
| 1394 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1395 | } |
| 1396 | |
| 1397 | static inline void hri_dac_set_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) |
| 1398 | { |
| 1399 | DAC_CRITICAL_SECTION_ENTER(); |
| 1400 | ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_CCTRL(mask); |
| 1401 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); |
| 1402 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1403 | } |
| 1404 | |
| 1405 | static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, |
| 1406 | hri_dac_dacctrl_reg_t mask) |
| 1407 | { |
| 1408 | uint16_t tmp; |
| 1409 | tmp = ((Dac *)hw)->DACCTRL[index].reg; |
| 1410 | tmp = (tmp & DAC_DACCTRL_CCTRL(mask)) >> DAC_DACCTRL_CCTRL_Pos; |
| 1411 | return tmp; |
| 1412 | } |
| 1413 | |
| 1414 | static inline void hri_dac_write_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) |
| 1415 | { |
| 1416 | uint16_t tmp; |
| 1417 | DAC_CRITICAL_SECTION_ENTER(); |
| 1418 | tmp = ((Dac *)hw)->DACCTRL[index].reg; |
| 1419 | tmp &= ~DAC_DACCTRL_CCTRL_Msk; |
| 1420 | tmp |= DAC_DACCTRL_CCTRL(data); |
| 1421 | ((Dac *)hw)->DACCTRL[index].reg = tmp; |
| 1422 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); |
| 1423 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1424 | } |
| 1425 | |
| 1426 | static inline void hri_dac_clear_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) |
| 1427 | { |
| 1428 | DAC_CRITICAL_SECTION_ENTER(); |
| 1429 | ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_CCTRL(mask); |
| 1430 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); |
| 1431 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1432 | } |
| 1433 | |
| 1434 | static inline void hri_dac_toggle_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) |
| 1435 | { |
| 1436 | DAC_CRITICAL_SECTION_ENTER(); |
| 1437 | ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_CCTRL(mask); |
| 1438 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); |
| 1439 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1440 | } |
| 1441 | |
| 1442 | static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index) |
| 1443 | { |
| 1444 | uint16_t tmp; |
| 1445 | tmp = ((Dac *)hw)->DACCTRL[index].reg; |
| 1446 | tmp = (tmp & DAC_DACCTRL_CCTRL_Msk) >> DAC_DACCTRL_CCTRL_Pos; |
| 1447 | return tmp; |
| 1448 | } |
| 1449 | |
| 1450 | static inline void hri_dac_set_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) |
| 1451 | { |
| 1452 | DAC_CRITICAL_SECTION_ENTER(); |
| 1453 | ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_REFRESH(mask); |
| 1454 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); |
| 1455 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1456 | } |
| 1457 | |
| 1458 | static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, |
| 1459 | hri_dac_dacctrl_reg_t mask) |
| 1460 | { |
| 1461 | uint16_t tmp; |
| 1462 | tmp = ((Dac *)hw)->DACCTRL[index].reg; |
| 1463 | tmp = (tmp & DAC_DACCTRL_REFRESH(mask)) >> DAC_DACCTRL_REFRESH_Pos; |
| 1464 | return tmp; |
| 1465 | } |
| 1466 | |
| 1467 | static inline void hri_dac_write_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) |
| 1468 | { |
| 1469 | uint16_t tmp; |
| 1470 | DAC_CRITICAL_SECTION_ENTER(); |
| 1471 | tmp = ((Dac *)hw)->DACCTRL[index].reg; |
| 1472 | tmp &= ~DAC_DACCTRL_REFRESH_Msk; |
| 1473 | tmp |= DAC_DACCTRL_REFRESH(data); |
| 1474 | ((Dac *)hw)->DACCTRL[index].reg = tmp; |
| 1475 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); |
| 1476 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1477 | } |
| 1478 | |
| 1479 | static inline void hri_dac_clear_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) |
| 1480 | { |
| 1481 | DAC_CRITICAL_SECTION_ENTER(); |
| 1482 | ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_REFRESH(mask); |
| 1483 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); |
| 1484 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1485 | } |
| 1486 | |
| 1487 | static inline void hri_dac_toggle_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) |
| 1488 | { |
| 1489 | DAC_CRITICAL_SECTION_ENTER(); |
| 1490 | ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_REFRESH(mask); |
| 1491 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); |
| 1492 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1493 | } |
| 1494 | |
| 1495 | static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index) |
| 1496 | { |
| 1497 | uint16_t tmp; |
| 1498 | tmp = ((Dac *)hw)->DACCTRL[index].reg; |
| 1499 | tmp = (tmp & DAC_DACCTRL_REFRESH_Msk) >> DAC_DACCTRL_REFRESH_Pos; |
| 1500 | return tmp; |
| 1501 | } |
| 1502 | |
| 1503 | static inline void hri_dac_set_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) |
| 1504 | { |
| 1505 | DAC_CRITICAL_SECTION_ENTER(); |
| 1506 | ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_OSR(mask); |
| 1507 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); |
| 1508 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1509 | } |
| 1510 | |
| 1511 | static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_OSR_bf(const void *const hw, uint8_t index, |
| 1512 | hri_dac_dacctrl_reg_t mask) |
| 1513 | { |
| 1514 | uint16_t tmp; |
| 1515 | tmp = ((Dac *)hw)->DACCTRL[index].reg; |
| 1516 | tmp = (tmp & DAC_DACCTRL_OSR(mask)) >> DAC_DACCTRL_OSR_Pos; |
| 1517 | return tmp; |
| 1518 | } |
| 1519 | |
| 1520 | static inline void hri_dac_write_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) |
| 1521 | { |
| 1522 | uint16_t tmp; |
| 1523 | DAC_CRITICAL_SECTION_ENTER(); |
| 1524 | tmp = ((Dac *)hw)->DACCTRL[index].reg; |
| 1525 | tmp &= ~DAC_DACCTRL_OSR_Msk; |
| 1526 | tmp |= DAC_DACCTRL_OSR(data); |
| 1527 | ((Dac *)hw)->DACCTRL[index].reg = tmp; |
| 1528 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); |
| 1529 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1530 | } |
| 1531 | |
| 1532 | static inline void hri_dac_clear_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) |
| 1533 | { |
| 1534 | DAC_CRITICAL_SECTION_ENTER(); |
| 1535 | ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_OSR(mask); |
| 1536 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); |
| 1537 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1538 | } |
| 1539 | |
| 1540 | static inline void hri_dac_toggle_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) |
| 1541 | { |
| 1542 | DAC_CRITICAL_SECTION_ENTER(); |
| 1543 | ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_OSR(mask); |
| 1544 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); |
| 1545 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1546 | } |
| 1547 | |
| 1548 | static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_OSR_bf(const void *const hw, uint8_t index) |
| 1549 | { |
| 1550 | uint16_t tmp; |
| 1551 | tmp = ((Dac *)hw)->DACCTRL[index].reg; |
| 1552 | tmp = (tmp & DAC_DACCTRL_OSR_Msk) >> DAC_DACCTRL_OSR_Pos; |
| 1553 | return tmp; |
| 1554 | } |
| 1555 | |
| 1556 | static inline void hri_dac_set_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) |
| 1557 | { |
| 1558 | DAC_CRITICAL_SECTION_ENTER(); |
| 1559 | ((Dac *)hw)->DACCTRL[index].reg |= mask; |
| 1560 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); |
| 1561 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1562 | } |
| 1563 | |
| 1564 | static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_reg(const void *const hw, uint8_t index, |
| 1565 | hri_dac_dacctrl_reg_t mask) |
| 1566 | { |
| 1567 | uint16_t tmp; |
| 1568 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); |
| 1569 | tmp = ((Dac *)hw)->DACCTRL[index].reg; |
| 1570 | tmp &= mask; |
| 1571 | return tmp; |
| 1572 | } |
| 1573 | |
| 1574 | static inline void hri_dac_write_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) |
| 1575 | { |
| 1576 | DAC_CRITICAL_SECTION_ENTER(); |
| 1577 | ((Dac *)hw)->DACCTRL[index].reg = data; |
| 1578 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); |
| 1579 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1580 | } |
| 1581 | |
| 1582 | static inline void hri_dac_clear_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) |
| 1583 | { |
| 1584 | DAC_CRITICAL_SECTION_ENTER(); |
| 1585 | ((Dac *)hw)->DACCTRL[index].reg &= ~mask; |
| 1586 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); |
| 1587 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1588 | } |
| 1589 | |
| 1590 | static inline void hri_dac_toggle_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) |
| 1591 | { |
| 1592 | DAC_CRITICAL_SECTION_ENTER(); |
| 1593 | ((Dac *)hw)->DACCTRL[index].reg ^= mask; |
| 1594 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); |
| 1595 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1596 | } |
| 1597 | |
| 1598 | static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_reg(const void *const hw, uint8_t index) |
| 1599 | { |
| 1600 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); |
| 1601 | return ((Dac *)hw)->DACCTRL[index].reg; |
| 1602 | } |
| 1603 | |
| 1604 | static inline void hri_dac_set_DBGCTRL_DBGRUN_bit(const void *const hw) |
| 1605 | { |
| 1606 | DAC_CRITICAL_SECTION_ENTER(); |
| 1607 | ((Dac *)hw)->DBGCTRL.reg |= DAC_DBGCTRL_DBGRUN; |
| 1608 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1609 | } |
| 1610 | |
| 1611 | static inline bool hri_dac_get_DBGCTRL_DBGRUN_bit(const void *const hw) |
| 1612 | { |
| 1613 | uint8_t tmp; |
| 1614 | tmp = ((Dac *)hw)->DBGCTRL.reg; |
| 1615 | tmp = (tmp & DAC_DBGCTRL_DBGRUN) >> DAC_DBGCTRL_DBGRUN_Pos; |
| 1616 | return (bool)tmp; |
| 1617 | } |
| 1618 | |
| 1619 | static inline void hri_dac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) |
| 1620 | { |
| 1621 | uint8_t tmp; |
| 1622 | DAC_CRITICAL_SECTION_ENTER(); |
| 1623 | tmp = ((Dac *)hw)->DBGCTRL.reg; |
| 1624 | tmp &= ~DAC_DBGCTRL_DBGRUN; |
| 1625 | tmp |= value << DAC_DBGCTRL_DBGRUN_Pos; |
| 1626 | ((Dac *)hw)->DBGCTRL.reg = tmp; |
| 1627 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1628 | } |
| 1629 | |
| 1630 | static inline void hri_dac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) |
| 1631 | { |
| 1632 | DAC_CRITICAL_SECTION_ENTER(); |
| 1633 | ((Dac *)hw)->DBGCTRL.reg &= ~DAC_DBGCTRL_DBGRUN; |
| 1634 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1635 | } |
| 1636 | |
| 1637 | static inline void hri_dac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) |
| 1638 | { |
| 1639 | DAC_CRITICAL_SECTION_ENTER(); |
| 1640 | ((Dac *)hw)->DBGCTRL.reg ^= DAC_DBGCTRL_DBGRUN; |
| 1641 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1642 | } |
| 1643 | |
| 1644 | static inline void hri_dac_set_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) |
| 1645 | { |
| 1646 | DAC_CRITICAL_SECTION_ENTER(); |
| 1647 | ((Dac *)hw)->DBGCTRL.reg |= mask; |
| 1648 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1649 | } |
| 1650 | |
| 1651 | static inline hri_dac_dbgctrl_reg_t hri_dac_get_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) |
| 1652 | { |
| 1653 | uint8_t tmp; |
| 1654 | tmp = ((Dac *)hw)->DBGCTRL.reg; |
| 1655 | tmp &= mask; |
| 1656 | return tmp; |
| 1657 | } |
| 1658 | |
| 1659 | static inline void hri_dac_write_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t data) |
| 1660 | { |
| 1661 | DAC_CRITICAL_SECTION_ENTER(); |
| 1662 | ((Dac *)hw)->DBGCTRL.reg = data; |
| 1663 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1664 | } |
| 1665 | |
| 1666 | static inline void hri_dac_clear_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) |
| 1667 | { |
| 1668 | DAC_CRITICAL_SECTION_ENTER(); |
| 1669 | ((Dac *)hw)->DBGCTRL.reg &= ~mask; |
| 1670 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1671 | } |
| 1672 | |
| 1673 | static inline void hri_dac_toggle_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) |
| 1674 | { |
| 1675 | DAC_CRITICAL_SECTION_ENTER(); |
| 1676 | ((Dac *)hw)->DBGCTRL.reg ^= mask; |
| 1677 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1678 | } |
| 1679 | |
| 1680 | static inline hri_dac_dbgctrl_reg_t hri_dac_read_DBGCTRL_reg(const void *const hw) |
| 1681 | { |
| 1682 | return ((Dac *)hw)->DBGCTRL.reg; |
| 1683 | } |
| 1684 | |
| 1685 | static inline void hri_dac_write_DATA_reg(const void *const hw, uint8_t index, hri_dac_data_reg_t data) |
| 1686 | { |
| 1687 | DAC_CRITICAL_SECTION_ENTER(); |
| 1688 | ((Dac *)hw)->DATA[index].reg = data; |
| 1689 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_DATA0 | DAC_SYNCBUSY_DATA1); |
| 1690 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1691 | } |
| 1692 | |
| 1693 | static inline void hri_dac_write_DATABUF_reg(const void *const hw, uint8_t index, hri_dac_databuf_reg_t data) |
| 1694 | { |
| 1695 | DAC_CRITICAL_SECTION_ENTER(); |
| 1696 | ((Dac *)hw)->DATABUF[index].reg = data; |
| 1697 | hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_DATABUF0 | DAC_SYNCBUSY_DATABUF1); |
| 1698 | DAC_CRITICAL_SECTION_LEAVE(); |
| 1699 | } |
| 1700 | |
| 1701 | #ifdef __cplusplus |
| 1702 | } |
| 1703 | #endif |
| 1704 | |
| 1705 | #endif /* _HRI_DAC_E54_H_INCLUDED */ |
| 1706 | #endif /* _SAME54_DAC_COMPONENT_ */ |