Kévin Redon | 4cd3f7d | 2019-01-24 17:57:13 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SPI Slave Async related functionality declaration. |
| 5 | * |
| 6 | * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifndef _HPL_SPI_M_ASYNC_H_INCLUDED |
| 35 | #define _HPL_SPI_M_ASYNC_H_INCLUDED |
| 36 | |
| 37 | #include <hpl_spi.h> |
| 38 | #include <hpl_spi_async.h> |
| 39 | |
| 40 | /** |
| 41 | * \addtogroup hpl_spi HPL SPI |
| 42 | * |
| 43 | * |
| 44 | *@{ |
| 45 | */ |
| 46 | |
| 47 | #ifdef __cplusplus |
| 48 | extern "C" { |
| 49 | #endif |
| 50 | |
| 51 | /** Uses common SPI async device driver. */ |
| 52 | #define _spi_m_async_dev _spi_async_dev |
| 53 | |
| 54 | #define _spi_m_async_dev_cb_type _spi_async_dev_cb_type |
| 55 | |
| 56 | /** Uses common SPI async device driver complete callback type. */ |
| 57 | #define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t |
| 58 | |
| 59 | /** Uses common SPI async device driver transfer callback type. */ |
| 60 | #define _spi_m_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t |
| 61 | |
| 62 | /** |
Harald Welte | 863ea29 | 2019-02-24 10:05:12 +0100 | [diff] [blame] | 63 | * \name HPL functions |
| 64 | */ |
| 65 | //@{ |
| 66 | /** |
Kévin Redon | 4cd3f7d | 2019-01-24 17:57:13 +0100 | [diff] [blame] | 67 | * \brief Initialize SPI for access with interrupts |
| 68 | * It will load default hardware configuration and software struct. |
| 69 | * \param[in, out] dev Pointer to the SPI device instance. |
| 70 | * \param[in] hw Pointer to the hardware base. |
| 71 | * \retval ERR_INVALID_ARG Input parameter problem. |
| 72 | * \retval ERR_BUSY SPI hardware not ready (resetting). |
| 73 | * \retval ERR_DENIED SPI has been enabled. |
| 74 | * \retval 0 Operation done successfully. |
| 75 | */ |
| 76 | int32_t _spi_m_async_init(struct _spi_m_async_dev *dev, void *const hw); |
| 77 | |
| 78 | /** |
| 79 | * \brief Initialize SPI for access with interrupts |
| 80 | * Disable, reset the hardware and the software struct. |
| 81 | * \param[in, out] dev Pointer to the SPI device instance. |
| 82 | * \return Operation status. |
| 83 | * \retval 0 Operation done successfully. |
| 84 | */ |
| 85 | int32_t _spi_m_async_deinit(struct _spi_m_async_dev *dev); |
| 86 | |
| 87 | /** |
| 88 | * \brief Enable SPI for access with interrupts |
| 89 | * Enable the SPI and enable callback generation of receive and error |
| 90 | * interrupts. |
| 91 | * \param[in, out] dev Pointer to the SPI device instance. |
| 92 | * \return Operation status. |
| 93 | * \retval ERR_INVALID_ARG Input parameter problem. |
| 94 | * \retval ERR_BUSY SPI hardware not ready (resetting). |
| 95 | * \retval 0 Operation done successfully. |
| 96 | */ |
| 97 | int32_t _spi_m_async_enable(struct _spi_m_async_dev *dev); |
| 98 | |
| 99 | /** |
| 100 | * \brief Disable SPI for access without interrupts |
| 101 | * Disable SPI and interrupts. Deactivate all CS pins if works as master. |
| 102 | * \param[in, out] dev Pointer to the SPI device instance. |
| 103 | * \return Operation status. |
| 104 | * \retval 0 Operation done successfully. |
| 105 | */ |
| 106 | int32_t _spi_m_async_disable(struct _spi_m_async_dev *dev); |
| 107 | |
| 108 | /** |
| 109 | * \brief Set SPI transfer mode |
| 110 | * Set SPI transfer mode (\ref spi_transfer_mode), |
| 111 | * which controls clock polarity and clock phase. |
| 112 | * Mode 0: leading edge is rising edge, data sample on leading edge. |
| 113 | * Mode 1: leading edge is rising edge, data sample on trailing edge. |
| 114 | * Mode 2: leading edge is falling edge, data sample on leading edge. |
| 115 | * Mode 3: leading edge is falling edge, data sample on trailing edge. |
| 116 | * \param[in, out] dev Pointer to the SPI device instance. |
| 117 | * \param[in] mode The SPI transfer mode. |
| 118 | * \return Operation status. |
| 119 | * \retval ERR_BUSY SPI is not ready to accept new setting. |
| 120 | * \retval 0 Operation done successfully. |
| 121 | */ |
| 122 | int32_t _spi_m_async_set_mode(struct _spi_m_async_dev *dev, const enum spi_transfer_mode mode); |
| 123 | |
| 124 | /** |
| 125 | * \brief Set SPI baudrate |
| 126 | * \param[in, out] dev Pointer to the SPI device instance. |
| 127 | * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on |
| 128 | * how it's generated. |
| 129 | * \return Operation status. |
| 130 | * \retval ERR_BUSY SPI is not ready to accept new setting. |
| 131 | * \retval 0 Operation done successfully. |
| 132 | */ |
| 133 | int32_t _spi_m_async_set_baudrate(struct _spi_m_async_dev *dev, const uint32_t baud_val); |
| 134 | |
| 135 | /** |
| 136 | * \brief Set SPI baudrate |
| 137 | * \param[in, out] dev Pointer to the SPI device instance. |
| 138 | * \param[in] char_size The character size, see \ref spi_char_size. |
| 139 | * \return Operation status. |
| 140 | * \retval ERR_INVALID_ARG The character size is not supported. |
| 141 | * \retval ERR_BUSY SPI is not ready to accept new setting. |
| 142 | * \retval 0 Operation done successfully. |
| 143 | */ |
| 144 | int32_t _spi_m_async_set_char_size(struct _spi_m_async_dev *dev, const enum spi_char_size char_size); |
| 145 | |
| 146 | /** |
| 147 | * \brief Set SPI data order |
| 148 | * \param[in, out] dev Pointer to the SPI device instance. |
| 149 | * \param[in] dord SPI data order (LSB/MSB first). |
| 150 | * \return Operation status. |
| 151 | * \retval ERR_INVALID_ARG The character size is not supported. |
| 152 | * \retval ERR_BUSY SPI is not ready to accept new setting. |
| 153 | * \retval 0 Operation done successfully. |
| 154 | */ |
| 155 | int32_t _spi_m_async_set_data_order(struct _spi_m_async_dev *dev, const enum spi_data_order dord); |
| 156 | |
| 157 | /** |
| 158 | * \brief Enable interrupt on character output |
| 159 | * |
| 160 | * Enable interrupt when a new character can be written |
| 161 | * to the SPI device. |
| 162 | * |
| 163 | * \param[in] dev Pointer to the SPI device instance |
| 164 | * \param[in] state true = enable output interrupt |
| 165 | * false = disable output interrupt |
| 166 | * |
| 167 | * \return Status code |
| 168 | * \retval 0 Ok status |
| 169 | */ |
| 170 | int32_t _spi_m_async_enable_tx(struct _spi_m_async_dev *dev, bool state); |
| 171 | |
| 172 | /** |
| 173 | * \brief Enable interrupt on character input |
| 174 | * |
| 175 | * Enable interrupt when a new character is ready to be |
| 176 | * read from the SPI device. |
| 177 | * |
| 178 | * \param[in] dev Pointer to the SPI device instance |
| 179 | * \param[in] state true = enable input interrupts |
| 180 | * false = disable input interrupt |
| 181 | * |
| 182 | * \return Status code |
| 183 | * \retvat 0 OK Status |
| 184 | */ |
| 185 | int32_t _spi_m_async_enable_rx(struct _spi_m_async_dev *dev, bool state); |
| 186 | |
| 187 | /** |
| 188 | * \brief Enable interrupt on after data transmission complate |
| 189 | * |
| 190 | * \param[in] dev Pointer to the SPI device instance |
| 191 | * \param[in] state true = enable input interrupts |
| 192 | * false = disable input interrupt |
| 193 | * |
| 194 | * \return Status code |
| 195 | * \retvat 0 OK Status |
| 196 | */ |
| 197 | int32_t _spi_m_async_enable_tx_complete(struct _spi_m_async_dev *dev, bool state); |
| 198 | |
| 199 | /** |
| 200 | * \brief Read one character to SPI device instance |
| 201 | * \param[in, out] dev Pointer to the SPI device instance. |
| 202 | * |
| 203 | * \return Character read from SPI module |
| 204 | */ |
| 205 | uint16_t _spi_m_async_read_one(struct _spi_m_async_dev *dev); |
| 206 | |
| 207 | /** |
| 208 | * \brief Write one character to assigned buffer |
| 209 | * \param[in, out] dev Pointer to the SPI device instance. |
| 210 | * \param[in] data |
| 211 | * |
| 212 | * \return Status code of write operation |
| 213 | * \retval 0 Write operation OK |
| 214 | */ |
| 215 | int32_t _spi_m_async_write_one(struct _spi_m_async_dev *dev, uint16_t data); |
| 216 | |
| 217 | /** |
| 218 | * \brief Register the SPI device callback |
| 219 | * \param[in, out] dev Pointer to the SPI device instance. |
| 220 | * \param[in] cb_type The callback type. |
| 221 | * \param[in] func The callback function to register. NULL to disable callback. |
| 222 | * \return Always 0. |
| 223 | */ |
| 224 | int32_t _spi_m_async_register_callback(struct _spi_m_async_dev *dev, const enum _spi_m_async_dev_cb_type cb_type, |
| 225 | const FUNC_PTR func); |
| 226 | |
| 227 | /** |
| 228 | * \brief Enable/disable SPI master interrupt |
| 229 | * |
| 230 | * param[in] device The pointer to SPI master device instance |
| 231 | * param[in] type The type of interrupt to disable/enable if applicable |
| 232 | * param[in] state Enable or disable |
| 233 | */ |
| 234 | void _spi_m_async_set_irq_state(struct _spi_m_async_dev *const device, const enum _spi_m_async_dev_cb_type type, |
| 235 | const bool state); |
Harald Welte | 863ea29 | 2019-02-24 10:05:12 +0100 | [diff] [blame] | 236 | //@} |
Kévin Redon | 4cd3f7d | 2019-01-24 17:57:13 +0100 | [diff] [blame] | 237 | |
| 238 | #ifdef __cplusplus |
| 239 | } |
| 240 | #endif |
| 241 | |
| 242 | /**@}*/ |
| 243 | #endif /* ifndef _HPL_SPI_M_ASYNC_H_INCLUDED */ |