| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame^] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief Instance description for QSPI |
| 5 | * |
| 6 | * Copyright (c) 2018 Microchip Technology Inc. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * SPDX-License-Identifier: Apache-2.0 |
| 13 | * |
| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may |
| 15 | * not use this file except in compliance with the License. |
| 16 | * You may obtain a copy of the Licence at |
| 17 | * |
| 18 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 19 | * |
| 20 | * Unless required by applicable law or agreed to in writing, software |
| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 23 | * See the License for the specific language governing permissions and |
| 24 | * limitations under the License. |
| 25 | * |
| 26 | * \asf_license_stop |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #ifndef _SAME54_QSPI_INSTANCE_ |
| 31 | #define _SAME54_QSPI_INSTANCE_ |
| 32 | |
| 33 | /* ========== Register definition for QSPI peripheral ========== */ |
| 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 35 | #define REG_QSPI_CTRLA (0x42003400) /**< \brief (QSPI) Control A */ |
| 36 | #define REG_QSPI_CTRLB (0x42003404) /**< \brief (QSPI) Control B */ |
| 37 | #define REG_QSPI_BAUD (0x42003408) /**< \brief (QSPI) Baud Rate */ |
| 38 | #define REG_QSPI_RXDATA (0x4200340C) /**< \brief (QSPI) Receive Data */ |
| 39 | #define REG_QSPI_TXDATA (0x42003410) /**< \brief (QSPI) Transmit Data */ |
| 40 | #define REG_QSPI_INTENCLR (0x42003414) /**< \brief (QSPI) Interrupt Enable Clear */ |
| 41 | #define REG_QSPI_INTENSET (0x42003418) /**< \brief (QSPI) Interrupt Enable Set */ |
| 42 | #define REG_QSPI_INTFLAG (0x4200341C) /**< \brief (QSPI) Interrupt Flag Status and Clear */ |
| 43 | #define REG_QSPI_STATUS (0x42003420) /**< \brief (QSPI) Status Register */ |
| 44 | #define REG_QSPI_INSTRADDR (0x42003430) /**< \brief (QSPI) Instruction Address */ |
| 45 | #define REG_QSPI_INSTRCTRL (0x42003434) /**< \brief (QSPI) Instruction Code */ |
| 46 | #define REG_QSPI_INSTRFRAME (0x42003438) /**< \brief (QSPI) Instruction Frame */ |
| 47 | #define REG_QSPI_SCRAMBCTRL (0x42003440) /**< \brief (QSPI) Scrambling Mode */ |
| 48 | #define REG_QSPI_SCRAMBKEY (0x42003444) /**< \brief (QSPI) Scrambling Key */ |
| 49 | #else |
| 50 | #define REG_QSPI_CTRLA (*(RwReg *)0x42003400UL) /**< \brief (QSPI) Control A */ |
| 51 | #define REG_QSPI_CTRLB (*(RwReg *)0x42003404UL) /**< \brief (QSPI) Control B */ |
| 52 | #define REG_QSPI_BAUD (*(RwReg *)0x42003408UL) /**< \brief (QSPI) Baud Rate */ |
| 53 | #define REG_QSPI_RXDATA (*(RoReg *)0x4200340CUL) /**< \brief (QSPI) Receive Data */ |
| 54 | #define REG_QSPI_TXDATA (*(WoReg *)0x42003410UL) /**< \brief (QSPI) Transmit Data */ |
| 55 | #define REG_QSPI_INTENCLR (*(RwReg *)0x42003414UL) /**< \brief (QSPI) Interrupt Enable Clear */ |
| 56 | #define REG_QSPI_INTENSET (*(RwReg *)0x42003418UL) /**< \brief (QSPI) Interrupt Enable Set */ |
| 57 | #define REG_QSPI_INTFLAG (*(RwReg *)0x4200341CUL) /**< \brief (QSPI) Interrupt Flag Status and Clear */ |
| 58 | #define REG_QSPI_STATUS (*(RoReg *)0x42003420UL) /**< \brief (QSPI) Status Register */ |
| 59 | #define REG_QSPI_INSTRADDR (*(RwReg *)0x42003430UL) /**< \brief (QSPI) Instruction Address */ |
| 60 | #define REG_QSPI_INSTRCTRL (*(RwReg *)0x42003434UL) /**< \brief (QSPI) Instruction Code */ |
| 61 | #define REG_QSPI_INSTRFRAME (*(RwReg *)0x42003438UL) /**< \brief (QSPI) Instruction Frame */ |
| 62 | #define REG_QSPI_SCRAMBCTRL (*(RwReg *)0x42003440UL) /**< \brief (QSPI) Scrambling Mode */ |
| 63 | #define REG_QSPI_SCRAMBKEY (*(WoReg *)0x42003444UL) /**< \brief (QSPI) Scrambling Key */ |
| 64 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 65 | |
| 66 | /* ========== Instance parameters for QSPI peripheral ========== */ |
| 67 | #define QSPI_DMAC_ID_RX 83 |
| 68 | #define QSPI_DMAC_ID_TX 84 |
| 69 | #define QSPI_HADDR_MSB 23 |
| 70 | #define QSPI_OCMS 1 |
| 71 | |
| 72 | #endif /* _SAME54_QSPI_INSTANCE_ */ |