| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame^] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief Instance description for PDEC |
| 5 | * |
| 6 | * Copyright (c) 2018 Microchip Technology Inc. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * SPDX-License-Identifier: Apache-2.0 |
| 13 | * |
| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may |
| 15 | * not use this file except in compliance with the License. |
| 16 | * You may obtain a copy of the Licence at |
| 17 | * |
| 18 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 19 | * |
| 20 | * Unless required by applicable law or agreed to in writing, software |
| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 23 | * See the License for the specific language governing permissions and |
| 24 | * limitations under the License. |
| 25 | * |
| 26 | * \asf_license_stop |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #ifndef _SAME54_PDEC_INSTANCE_ |
| 31 | #define _SAME54_PDEC_INSTANCE_ |
| 32 | |
| 33 | /* ========== Register definition for PDEC peripheral ========== */ |
| 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 35 | #define REG_PDEC_CTRLA (0x42001C00) /**< \brief (PDEC) Control A */ |
| 36 | #define REG_PDEC_CTRLBCLR (0x42001C04) /**< \brief (PDEC) Control B Clear */ |
| 37 | #define REG_PDEC_CTRLBSET (0x42001C05) /**< \brief (PDEC) Control B Set */ |
| 38 | #define REG_PDEC_EVCTRL (0x42001C06) /**< \brief (PDEC) Event Control */ |
| 39 | #define REG_PDEC_INTENCLR (0x42001C08) /**< \brief (PDEC) Interrupt Enable Clear */ |
| 40 | #define REG_PDEC_INTENSET (0x42001C09) /**< \brief (PDEC) Interrupt Enable Set */ |
| 41 | #define REG_PDEC_INTFLAG (0x42001C0A) /**< \brief (PDEC) Interrupt Flag Status and Clear */ |
| 42 | #define REG_PDEC_STATUS (0x42001C0C) /**< \brief (PDEC) Status */ |
| 43 | #define REG_PDEC_DBGCTRL (0x42001C0F) /**< \brief (PDEC) Debug Control */ |
| 44 | #define REG_PDEC_SYNCBUSY (0x42001C10) /**< \brief (PDEC) Synchronization Status */ |
| 45 | #define REG_PDEC_PRESC (0x42001C14) /**< \brief (PDEC) Prescaler Value */ |
| 46 | #define REG_PDEC_FILTER (0x42001C15) /**< \brief (PDEC) Filter Value */ |
| 47 | #define REG_PDEC_PRESCBUF (0x42001C18) /**< \brief (PDEC) Prescaler Buffer Value */ |
| 48 | #define REG_PDEC_FILTERBUF (0x42001C19) /**< \brief (PDEC) Filter Buffer Value */ |
| 49 | #define REG_PDEC_COUNT (0x42001C1C) /**< \brief (PDEC) Counter Value */ |
| 50 | #define REG_PDEC_CC0 (0x42001C20) /**< \brief (PDEC) Channel 0 Compare Value */ |
| 51 | #define REG_PDEC_CC1 (0x42001C24) /**< \brief (PDEC) Channel 1 Compare Value */ |
| 52 | #define REG_PDEC_CCBUF0 (0x42001C30) /**< \brief (PDEC) Channel Compare Buffer Value 0 */ |
| 53 | #define REG_PDEC_CCBUF1 (0x42001C34) /**< \brief (PDEC) Channel Compare Buffer Value 1 */ |
| 54 | #else |
| 55 | #define REG_PDEC_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (PDEC) Control A */ |
| 56 | #define REG_PDEC_CTRLBCLR (*(RwReg8 *)0x42001C04UL) /**< \brief (PDEC) Control B Clear */ |
| 57 | #define REG_PDEC_CTRLBSET (*(RwReg8 *)0x42001C05UL) /**< \brief (PDEC) Control B Set */ |
| 58 | #define REG_PDEC_EVCTRL (*(RwReg16*)0x42001C06UL) /**< \brief (PDEC) Event Control */ |
| 59 | #define REG_PDEC_INTENCLR (*(RwReg8 *)0x42001C08UL) /**< \brief (PDEC) Interrupt Enable Clear */ |
| 60 | #define REG_PDEC_INTENSET (*(RwReg8 *)0x42001C09UL) /**< \brief (PDEC) Interrupt Enable Set */ |
| 61 | #define REG_PDEC_INTFLAG (*(RwReg8 *)0x42001C0AUL) /**< \brief (PDEC) Interrupt Flag Status and Clear */ |
| 62 | #define REG_PDEC_STATUS (*(RwReg16*)0x42001C0CUL) /**< \brief (PDEC) Status */ |
| 63 | #define REG_PDEC_DBGCTRL (*(RwReg8 *)0x42001C0FUL) /**< \brief (PDEC) Debug Control */ |
| 64 | #define REG_PDEC_SYNCBUSY (*(RoReg *)0x42001C10UL) /**< \brief (PDEC) Synchronization Status */ |
| 65 | #define REG_PDEC_PRESC (*(RwReg8 *)0x42001C14UL) /**< \brief (PDEC) Prescaler Value */ |
| 66 | #define REG_PDEC_FILTER (*(RwReg8 *)0x42001C15UL) /**< \brief (PDEC) Filter Value */ |
| 67 | #define REG_PDEC_PRESCBUF (*(RwReg8 *)0x42001C18UL) /**< \brief (PDEC) Prescaler Buffer Value */ |
| 68 | #define REG_PDEC_FILTERBUF (*(RwReg8 *)0x42001C19UL) /**< \brief (PDEC) Filter Buffer Value */ |
| 69 | #define REG_PDEC_COUNT (*(RwReg *)0x42001C1CUL) /**< \brief (PDEC) Counter Value */ |
| 70 | #define REG_PDEC_CC0 (*(RwReg *)0x42001C20UL) /**< \brief (PDEC) Channel 0 Compare Value */ |
| 71 | #define REG_PDEC_CC1 (*(RwReg *)0x42001C24UL) /**< \brief (PDEC) Channel 1 Compare Value */ |
| 72 | #define REG_PDEC_CCBUF0 (*(RwReg *)0x42001C30UL) /**< \brief (PDEC) Channel Compare Buffer Value 0 */ |
| 73 | #define REG_PDEC_CCBUF1 (*(RwReg *)0x42001C34UL) /**< \brief (PDEC) Channel Compare Buffer Value 1 */ |
| 74 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 75 | |
| 76 | /* ========== Instance parameters for PDEC peripheral ========== */ |
| 77 | #define PDEC_CC_NUM 2 // Number of Compare Channels units |
| 78 | #define PDEC_GCLK_ID 31 |
| 79 | |
| 80 | #endif /* _SAME54_PDEC_INSTANCE_ */ |