| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame^] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief Instance description for AES |
| 5 | * |
| 6 | * Copyright (c) 2018 Microchip Technology Inc. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * SPDX-License-Identifier: Apache-2.0 |
| 13 | * |
| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may |
| 15 | * not use this file except in compliance with the License. |
| 16 | * You may obtain a copy of the Licence at |
| 17 | * |
| 18 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 19 | * |
| 20 | * Unless required by applicable law or agreed to in writing, software |
| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 23 | * See the License for the specific language governing permissions and |
| 24 | * limitations under the License. |
| 25 | * |
| 26 | * \asf_license_stop |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #ifndef _SAME54_AES_INSTANCE_ |
| 31 | #define _SAME54_AES_INSTANCE_ |
| 32 | |
| 33 | /* ========== Register definition for AES peripheral ========== */ |
| 34 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 35 | #define REG_AES_CTRLA (0x42002400) /**< \brief (AES) Control A */ |
| 36 | #define REG_AES_CTRLB (0x42002404) /**< \brief (AES) Control B */ |
| 37 | #define REG_AES_INTENCLR (0x42002405) /**< \brief (AES) Interrupt Enable Clear */ |
| 38 | #define REG_AES_INTENSET (0x42002406) /**< \brief (AES) Interrupt Enable Set */ |
| 39 | #define REG_AES_INTFLAG (0x42002407) /**< \brief (AES) Interrupt Flag Status */ |
| 40 | #define REG_AES_DATABUFPTR (0x42002408) /**< \brief (AES) Data buffer pointer */ |
| 41 | #define REG_AES_DBGCTRL (0x42002409) /**< \brief (AES) Debug control */ |
| 42 | #define REG_AES_KEYWORD0 (0x4200240C) /**< \brief (AES) Keyword 0 */ |
| 43 | #define REG_AES_KEYWORD1 (0x42002410) /**< \brief (AES) Keyword 1 */ |
| 44 | #define REG_AES_KEYWORD2 (0x42002414) /**< \brief (AES) Keyword 2 */ |
| 45 | #define REG_AES_KEYWORD3 (0x42002418) /**< \brief (AES) Keyword 3 */ |
| 46 | #define REG_AES_KEYWORD4 (0x4200241C) /**< \brief (AES) Keyword 4 */ |
| 47 | #define REG_AES_KEYWORD5 (0x42002420) /**< \brief (AES) Keyword 5 */ |
| 48 | #define REG_AES_KEYWORD6 (0x42002424) /**< \brief (AES) Keyword 6 */ |
| 49 | #define REG_AES_KEYWORD7 (0x42002428) /**< \brief (AES) Keyword 7 */ |
| 50 | #define REG_AES_INDATA (0x42002438) /**< \brief (AES) Indata */ |
| 51 | #define REG_AES_INTVECTV0 (0x4200243C) /**< \brief (AES) Initialisation Vector 0 */ |
| 52 | #define REG_AES_INTVECTV1 (0x42002440) /**< \brief (AES) Initialisation Vector 1 */ |
| 53 | #define REG_AES_INTVECTV2 (0x42002444) /**< \brief (AES) Initialisation Vector 2 */ |
| 54 | #define REG_AES_INTVECTV3 (0x42002448) /**< \brief (AES) Initialisation Vector 3 */ |
| 55 | #define REG_AES_HASHKEY0 (0x4200245C) /**< \brief (AES) Hash key 0 */ |
| 56 | #define REG_AES_HASHKEY1 (0x42002460) /**< \brief (AES) Hash key 1 */ |
| 57 | #define REG_AES_HASHKEY2 (0x42002464) /**< \brief (AES) Hash key 2 */ |
| 58 | #define REG_AES_HASHKEY3 (0x42002468) /**< \brief (AES) Hash key 3 */ |
| 59 | #define REG_AES_GHASH0 (0x4200246C) /**< \brief (AES) Galois Hash 0 */ |
| 60 | #define REG_AES_GHASH1 (0x42002470) /**< \brief (AES) Galois Hash 1 */ |
| 61 | #define REG_AES_GHASH2 (0x42002474) /**< \brief (AES) Galois Hash 2 */ |
| 62 | #define REG_AES_GHASH3 (0x42002478) /**< \brief (AES) Galois Hash 3 */ |
| 63 | #define REG_AES_CIPLEN (0x42002480) /**< \brief (AES) Cipher Length */ |
| 64 | #define REG_AES_RANDSEED (0x42002484) /**< \brief (AES) Random Seed */ |
| 65 | #else |
| 66 | #define REG_AES_CTRLA (*(RwReg *)0x42002400UL) /**< \brief (AES) Control A */ |
| 67 | #define REG_AES_CTRLB (*(RwReg8 *)0x42002404UL) /**< \brief (AES) Control B */ |
| 68 | #define REG_AES_INTENCLR (*(RwReg8 *)0x42002405UL) /**< \brief (AES) Interrupt Enable Clear */ |
| 69 | #define REG_AES_INTENSET (*(RwReg8 *)0x42002406UL) /**< \brief (AES) Interrupt Enable Set */ |
| 70 | #define REG_AES_INTFLAG (*(RwReg8 *)0x42002407UL) /**< \brief (AES) Interrupt Flag Status */ |
| 71 | #define REG_AES_DATABUFPTR (*(RwReg8 *)0x42002408UL) /**< \brief (AES) Data buffer pointer */ |
| 72 | #define REG_AES_DBGCTRL (*(RwReg8 *)0x42002409UL) /**< \brief (AES) Debug control */ |
| 73 | #define REG_AES_KEYWORD0 (*(WoReg *)0x4200240CUL) /**< \brief (AES) Keyword 0 */ |
| 74 | #define REG_AES_KEYWORD1 (*(WoReg *)0x42002410UL) /**< \brief (AES) Keyword 1 */ |
| 75 | #define REG_AES_KEYWORD2 (*(WoReg *)0x42002414UL) /**< \brief (AES) Keyword 2 */ |
| 76 | #define REG_AES_KEYWORD3 (*(WoReg *)0x42002418UL) /**< \brief (AES) Keyword 3 */ |
| 77 | #define REG_AES_KEYWORD4 (*(WoReg *)0x4200241CUL) /**< \brief (AES) Keyword 4 */ |
| 78 | #define REG_AES_KEYWORD5 (*(WoReg *)0x42002420UL) /**< \brief (AES) Keyword 5 */ |
| 79 | #define REG_AES_KEYWORD6 (*(WoReg *)0x42002424UL) /**< \brief (AES) Keyword 6 */ |
| 80 | #define REG_AES_KEYWORD7 (*(WoReg *)0x42002428UL) /**< \brief (AES) Keyword 7 */ |
| 81 | #define REG_AES_INDATA (*(RwReg *)0x42002438UL) /**< \brief (AES) Indata */ |
| 82 | #define REG_AES_INTVECTV0 (*(WoReg *)0x4200243CUL) /**< \brief (AES) Initialisation Vector 0 */ |
| 83 | #define REG_AES_INTVECTV1 (*(WoReg *)0x42002440UL) /**< \brief (AES) Initialisation Vector 1 */ |
| 84 | #define REG_AES_INTVECTV2 (*(WoReg *)0x42002444UL) /**< \brief (AES) Initialisation Vector 2 */ |
| 85 | #define REG_AES_INTVECTV3 (*(WoReg *)0x42002448UL) /**< \brief (AES) Initialisation Vector 3 */ |
| 86 | #define REG_AES_HASHKEY0 (*(RwReg *)0x4200245CUL) /**< \brief (AES) Hash key 0 */ |
| 87 | #define REG_AES_HASHKEY1 (*(RwReg *)0x42002460UL) /**< \brief (AES) Hash key 1 */ |
| 88 | #define REG_AES_HASHKEY2 (*(RwReg *)0x42002464UL) /**< \brief (AES) Hash key 2 */ |
| 89 | #define REG_AES_HASHKEY3 (*(RwReg *)0x42002468UL) /**< \brief (AES) Hash key 3 */ |
| 90 | #define REG_AES_GHASH0 (*(RwReg *)0x4200246CUL) /**< \brief (AES) Galois Hash 0 */ |
| 91 | #define REG_AES_GHASH1 (*(RwReg *)0x42002470UL) /**< \brief (AES) Galois Hash 1 */ |
| 92 | #define REG_AES_GHASH2 (*(RwReg *)0x42002474UL) /**< \brief (AES) Galois Hash 2 */ |
| 93 | #define REG_AES_GHASH3 (*(RwReg *)0x42002478UL) /**< \brief (AES) Galois Hash 3 */ |
| 94 | #define REG_AES_CIPLEN (*(RwReg *)0x42002480UL) /**< \brief (AES) Cipher Length */ |
| 95 | #define REG_AES_RANDSEED (*(RwReg *)0x42002484UL) /**< \brief (AES) Random Seed */ |
| 96 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 97 | |
| 98 | /* ========== Instance parameters for AES peripheral ========== */ |
| 99 | #define AES_DMAC_ID_RD 82 // DMA DATA Read trigger |
| 100 | #define AES_DMAC_ID_WR 81 // DMA DATA Write trigger |
| 101 | #define AES_FOUR_BYTE_OPERATION 1 // Byte Operation |
| 102 | #define AES_GCM 1 // GCM |
| 103 | #define AES_KEYLEN 2 // Key Length |
| 104 | |
| 105 | #endif /* _SAME54_AES_INSTANCE_ */ |