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gerrit.osmocom.org / osmo-ccid-firmware / 69b92d91f73aabc25ea3aa8aa8638508f5a42395 / . / sysmoOCTSIM / CMSIS / Include / core_cm0plus.h
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Kévin Redon69b92d92019-01-24 16:39:20 +0100[diff] [blame^]1/**************************************************************************//**
2 * @file core_cm0plus.h
3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
4 * @version V5.0.1
5 * @date 25. November 2016
6 ******************************************************************************/
7/*
8 * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25#if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
28 #pragma clang system_header /* treat file as system include file */
29#endif
30
31#ifndef __CORE_CM0PLUS_H_GENERIC
32#define __CORE_CM0PLUS_H_GENERIC
33
34#include <stdint.h>
35
36#ifdef __cplusplus
37 extern "C" {
38#endif
39
40/**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55/*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58/**
59 \ingroup Cortex-M0+
60 @{
61 */
62
63/* CMSIS CM0+ definitions */
64#define __CM0PLUS_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
65#define __CM0PLUS_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
66#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
67 __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
68
69#define __CORTEX_M (0U) /*!< Cortex-M Core */
70
71/** __FPU_USED indicates whether an FPU is used or not.
72 This core does not support an FPU at all
73*/
74#define __FPU_USED 0U
75
76#if defined ( __CC_ARM )
77 #if defined __TARGET_FPU_VFP
78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
79 #endif
80
81#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
82 #if defined __ARM_PCS_VFP
83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
84 #endif
85
86#elif defined ( __GNUC__ )
87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
89 #endif
90
91#elif defined ( __ICCARM__ )
92 #if defined __ARMVFP__
93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
94 #endif
95
96#elif defined ( __TI_ARM__ )
97 #if defined __TI_VFP_SUPPORT__
98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
99 #endif
100
101#elif defined ( __TASKING__ )
102 #if defined __FPU_VFP__
103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
104 #endif
105
106#elif defined ( __CSMC__ )
107 #if ( __CSMC__ & 0x400U)
108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
109 #endif
110
111#endif
112
113#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
114
115
116#ifdef __cplusplus
117}
118#endif
119
120#endif /* __CORE_CM0PLUS_H_GENERIC */
121
122#ifndef __CMSIS_GENERIC
123
124#ifndef __CORE_CM0PLUS_H_DEPENDANT
125#define __CORE_CM0PLUS_H_DEPENDANT
126
127#ifdef __cplusplus
128 extern "C" {
129#endif
130
131/* check device defines and use defaults */
132#if defined __CHECK_DEVICE_DEFINES
133 #ifndef __CM0PLUS_REV
134 #define __CM0PLUS_REV 0x0000U
135 #warning "__CM0PLUS_REV not defined in device header file; using default!"
136 #endif
137
138 #ifndef __MPU_PRESENT
139 #define __MPU_PRESENT 0U
140 #warning "__MPU_PRESENT not defined in device header file; using default!"
141 #endif
142
143 #ifndef __VTOR_PRESENT
144 #define __VTOR_PRESENT 0U
145 #warning "__VTOR_PRESENT not defined in device header file; using default!"
146 #endif
147
148 #ifndef __NVIC_PRIO_BITS
149 #define __NVIC_PRIO_BITS 2U
150 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
151 #endif
152
153 #ifndef __Vendor_SysTickConfig
154 #define __Vendor_SysTickConfig 0U
155 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
156 #endif
157#endif
158
159/* IO definitions (access restrictions to peripheral registers) */
160/**
161 \defgroup CMSIS_glob_defs CMSIS Global Defines
162
163 <strong>IO Type Qualifiers</strong> are used
164 \li to specify the access to peripheral variables.
165 \li for automatic generation of peripheral register debug information.
166*/
167#ifdef __cplusplus
168 #define __I volatile /*!< Defines 'read only' permissions */
169#else
170 #define __I volatile const /*!< Defines 'read only' permissions */
171#endif
172#define __O volatile /*!< Defines 'write only' permissions */
173#define __IO volatile /*!< Defines 'read / write' permissions */
174
175/* following defines should be used for structure members */
176#define __IM volatile const /*! Defines 'read only' structure member permissions */
177#define __OM volatile /*! Defines 'write only' structure member permissions */
178#define __IOM volatile /*! Defines 'read / write' structure member permissions */
179
180/*@} end of group Cortex-M0+ */
181
182
183
184/*******************************************************************************
185 * Register Abstraction
186 Core Register contain:
187 - Core Register
188 - Core NVIC Register
189 - Core SCB Register
190 - Core SysTick Register
191 - Core MPU Register
192 ******************************************************************************/
193/**
194 \defgroup CMSIS_core_register Defines and Type Definitions
195 \brief Type definitions and defines for Cortex-M processor based devices.
196*/
197
198/**
199 \ingroup CMSIS_core_register
200 \defgroup CMSIS_CORE Status and Control Registers
201 \brief Core Register type definitions.
202 @{
203 */
204
205/**
206 \brief Union type to access the Application Program Status Register (APSR).
207 */
208typedef union
209{
210 struct
211 {
212 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
213 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
214 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
215 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
216 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
217 } b; /*!< Structure used for bit access */
218 uint32_t w; /*!< Type used for word access */
219} APSR_Type;
220
221/* APSR Register Definitions */
222#define APSR_N_Pos 31U /*!< APSR: N Position */
223#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
224
225#define APSR_Z_Pos 30U /*!< APSR: Z Position */
226#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
227
228#define APSR_C_Pos 29U /*!< APSR: C Position */
229#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
230
231#define APSR_V_Pos 28U /*!< APSR: V Position */
232#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
233
234
235/**
236 \brief Union type to access the Interrupt Program Status Register (IPSR).
237 */
238typedef union
239{
240 struct
241 {
242 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
243 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
244 } b; /*!< Structure used for bit access */
245 uint32_t w; /*!< Type used for word access */
246} IPSR_Type;
247
248/* IPSR Register Definitions */
249#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
250#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
251
252
253/**
254 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
255 */
256typedef union
257{
258 struct
259 {
260 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
261 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
262 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
263 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
264 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
265 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
266 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
267 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
268 } b; /*!< Structure used for bit access */
269 uint32_t w; /*!< Type used for word access */
270} xPSR_Type;
271
272/* xPSR Register Definitions */
273#define xPSR_N_Pos 31U /*!< xPSR: N Position */
274#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
275
276#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
277#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
278
279#define xPSR_C_Pos 29U /*!< xPSR: C Position */
280#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
281
282#define xPSR_V_Pos 28U /*!< xPSR: V Position */
283#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
284
285#define xPSR_T_Pos 24U /*!< xPSR: T Position */
286#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
287
288#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
289#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
290
291
292/**
293 \brief Union type to access the Control Registers (CONTROL).
294 */
295typedef union
296{
297 struct
298 {
299 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
300 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
301 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
302 } b; /*!< Structure used for bit access */
303 uint32_t w; /*!< Type used for word access */
304} CONTROL_Type;
305
306/* CONTROL Register Definitions */
307#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
308#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
309
310#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
311#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
312
313/*@} end of group CMSIS_CORE */
314
315
316/**
317 \ingroup CMSIS_core_register
318 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
319 \brief Type definitions for the NVIC Registers
320 @{
321 */
322
323/**
324 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
325 */
326typedef struct
327{
328 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
329 uint32_t RESERVED0[31U];
330 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
331 uint32_t RSERVED1[31U];
332 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
333 uint32_t RESERVED2[31U];
334 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
335 uint32_t RESERVED3[31U];
336 uint32_t RESERVED4[64U];
337 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
338} NVIC_Type;
339
340/*@} end of group CMSIS_NVIC */
341
342
343/**
344 \ingroup CMSIS_core_register
345 \defgroup CMSIS_SCB System Control Block (SCB)
346 \brief Type definitions for the System Control Block Registers
347 @{
348 */
349
350/**
351 \brief Structure type to access the System Control Block (SCB).
352 */
353typedef struct
354{
355 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
356 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
357#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
358 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
359#else
360 uint32_t RESERVED0;
361#endif
362 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
363 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
364 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
365 uint32_t RESERVED1;
366 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
367 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
368} SCB_Type;
369
370/* SCB CPUID Register Definitions */
371#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
372#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
373
374#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
375#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
376
377#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
378#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
379
380#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
381#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
382
383#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
384#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
385
386/* SCB Interrupt Control State Register Definitions */
387#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
388#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
389
390#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
391#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
392
393#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
394#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
395
396#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
397#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
398
399#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
400#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
401
402#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
403#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
404
405#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
406#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
407
408#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
409#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
410
411#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
412#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
413
414#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
415/* SCB Interrupt Control State Register Definitions */
416#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
417#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
418#endif
419
420/* SCB Application Interrupt and Reset Control Register Definitions */
421#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
422#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
423
424#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
425#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
426
427#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
428#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
429
430#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
431#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
432
433#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
434#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
435
436/* SCB System Control Register Definitions */
437#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
438#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
439
440#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
441#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
442
443#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
444#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
445
446/* SCB Configuration Control Register Definitions */
447#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
448#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
449
450#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
451#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
452
453/* SCB System Handler Control and State Register Definitions */
454#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
455#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
456
457/*@} end of group CMSIS_SCB */
458
459
460/**
461 \ingroup CMSIS_core_register
462 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
463 \brief Type definitions for the System Timer Registers.
464 @{
465 */
466
467/**
468 \brief Structure type to access the System Timer (SysTick).
469 */
470typedef struct
471{
472 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
473 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
474 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
475 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
476} SysTick_Type;
477
478/* SysTick Control / Status Register Definitions */
479#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
480#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
481
482#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
483#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
484
485#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
486#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
487
488#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
489#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
490
491/* SysTick Reload Register Definitions */
492#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
493#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
494
495/* SysTick Current Register Definitions */
496#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
497#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
498
499/* SysTick Calibration Register Definitions */
500#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
501#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
502
503#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
504#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
505
506#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
507#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
508
509/*@} end of group CMSIS_SysTick */
510
511#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
512/**
513 \ingroup CMSIS_core_register
514 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
515 \brief Type definitions for the Memory Protection Unit (MPU)
516 @{
517 */
518
519/**
520 \brief Structure type to access the Memory Protection Unit (MPU).
521 */
522typedef struct
523{
524 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
525 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
526 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
527 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
528 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
529} MPU_Type;
530
531/* MPU Type Register Definitions */
532#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
533#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
534
535#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
536#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
537
538#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
539#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
540
541/* MPU Control Register Definitions */
542#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
543#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
544
545#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
546#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
547
548#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
549#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
550
551/* MPU Region Number Register Definitions */
552#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
553#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
554
555/* MPU Region Base Address Register Definitions */
556#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
557#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
558
559#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
560#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
561
562#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
563#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
564
565/* MPU Region Attribute and Size Register Definitions */
566#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
567#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
568
569#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
570#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
571
572#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
573#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
574
575#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
576#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
577
578#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
579#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
580
581#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
582#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
583
584#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
585#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
586
587#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
588#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
589
590#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
591#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
592
593#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
594#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
595
596/*@} end of group CMSIS_MPU */
597#endif
598
599
600/**
601 \ingroup CMSIS_core_register
602 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
603 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
604 Therefore they are not covered by the Cortex-M0+ header file.
605 @{
606 */
607/*@} end of group CMSIS_CoreDebug */
608
609
610/**
611 \ingroup CMSIS_core_register
612 \defgroup CMSIS_core_bitfield Core register bit field macros
613 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
614 @{
615 */
616
617/**
618 \brief Mask and shift a bit field value for use in a register bit range.
619 \param[in] field Name of the register bit field.
620 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
621 \return Masked and shifted value.
622*/
623#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
624
625/**
626 \brief Mask and shift a register value to extract a bit filed value.
627 \param[in] field Name of the register bit field.
628 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
629 \return Masked and shifted bit field value.
630*/
631#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
632
633/*@} end of group CMSIS_core_bitfield */
634
635
636/**
637 \ingroup CMSIS_core_register
638 \defgroup CMSIS_core_base Core Definitions
639 \brief Definitions for base addresses, unions, and structures.
640 @{
641 */
642
643/* Memory mapping of Core Hardware */
644#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
645#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
646#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
647#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
648
649#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
650#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
651#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
652
653#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
654 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
655 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
656#endif
657
658/*@} */
659
660
661
662/*******************************************************************************
663 * Hardware Abstraction Layer
664 Core Function Interface contains:
665 - Core NVIC Functions
666 - Core SysTick Functions
667 - Core Register Access Functions
668 ******************************************************************************/
669/**
670 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
671*/
672
673
674
675/* ########################## NVIC functions #################################### */
676/**
677 \ingroup CMSIS_Core_FunctionInterface
678 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
679 \brief Functions that manage interrupts and exceptions via the NVIC.
680 @{
681 */
682
683#ifndef CMSIS_NVIC_VIRTUAL
684/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */
685/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */
686 #define NVIC_EnableIRQ __NVIC_EnableIRQ
687 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
688 #define NVIC_DisableIRQ __NVIC_DisableIRQ
689 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
690 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
691 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
692/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
693 #define NVIC_SetPriority __NVIC_SetPriority
694 #define NVIC_GetPriority __NVIC_GetPriority
695#endif /* CMSIS_NVIC_VIRTUAL */
696
697#ifndef CMSIS_VECTAB_VIRTUAL
698 #define NVIC_SetVector __NVIC_SetVector
699 #define NVIC_GetVector __NVIC_GetVector
700#endif /* (CMSIS_VECTAB_VIRTUAL) */
701
702#define NVIC_USER_IRQ_OFFSET 16
703
704
705/* Interrupt Priorities are WORD accessible only under ARMv6M */
706/* The following MACROS handle generation of the register offset and byte masks */
707#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
708#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
709#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
710
711
712/**
713 \brief Enable Interrupt
714 \details Enables a device specific interrupt in the NVIC interrupt controller.
715 \param [in] IRQn Device specific interrupt number.
716 \note IRQn must not be negative.
717 */
718__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
719{
720 if ((int32_t)(IRQn) >= 0)
721 {
722 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
723 }
724}
725
726
727/**
728 \brief Get Interrupt Enable status
729 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
730 \param [in] IRQn Device specific interrupt number.
731 \return 0 Interrupt is not enabled.
732 \return 1 Interrupt is enabled.
733 \note IRQn must not be negative.
734 */
735__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
736{
737 if ((int32_t)(IRQn) >= 0)
738 {
739 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
740 }
741 else
742 {
743 return(0U);
744 }
745}
746
747
748/**
749 \brief Disable Interrupt
750 \details Disables a device specific interrupt in the NVIC interrupt controller.
751 \param [in] IRQn Device specific interrupt number.
752 \note IRQn must not be negative.
753 */
754__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
755{
756 if ((int32_t)(IRQn) >= 0)
757 {
758 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
759 __DSB();
760 __ISB();
761 }
762}
763
764
765/**
766 \brief Get Pending Interrupt
767 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
768 \param [in] IRQn Device specific interrupt number.
769 \return 0 Interrupt status is not pending.
770 \return 1 Interrupt status is pending.
771 \note IRQn must not be negative.
772 */
773__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
774{
775 if ((int32_t)(IRQn) >= 0)
776 {
777 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
778 }
779 else
780 {
781 return(0U);
782 }
783}
784
785
786/**
787 \brief Set Pending Interrupt
788 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
789 \param [in] IRQn Device specific interrupt number.
790 \note IRQn must not be negative.
791 */
792__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
793{
794 if ((int32_t)(IRQn) >= 0)
795 {
796 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
797 }
798}
799
800
801/**
802 \brief Clear Pending Interrupt
803 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
804 \param [in] IRQn Device specific interrupt number.
805 \note IRQn must not be negative.
806 */
807__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
808{
809 if ((int32_t)(IRQn) >= 0)
810 {
811 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
812 }
813}
814
815
816/**
817 \brief Set Interrupt Priority
818 \details Sets the priority of a device specific interrupt or a processor exception.
819 The interrupt number can be positive to specify a device specific interrupt,
820 or negative to specify a processor exception.
821 \param [in] IRQn Interrupt number.
822 \param [in] priority Priority to set.
823 \note The priority cannot be set for every processor exception.
824 */
825__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
826{
827 if ((int32_t)(IRQn) >= 0)
828 {
829 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
830 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
831 }
832 else
833 {
834 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
835 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
836 }
837}
838
839
840/**
841 \brief Get Interrupt Priority
842 \details Reads the priority of a device specific interrupt or a processor exception.
843 The interrupt number can be positive to specify a device specific interrupt,
844 or negative to specify a processor exception.
845 \param [in] IRQn Interrupt number.
846 \return Interrupt Priority.
847 Value is aligned automatically to the implemented priority bits of the microcontroller.
848 */
849__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
850{
851
852 if ((int32_t)(IRQn) >= 0)
853 {
854 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
855 }
856 else
857 {
858 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
859 }
860}
861
862
863/**
864 \brief Set Interrupt Vector
865 \details Sets an interrupt vector in SRAM based interrupt vector table.
866 The interrupt number can be positive to specify a device specific interrupt,
867 or negative to specify a processor exception.
868 VTOR must been relocated to SRAM before.
869 If VTOR is not present address 0 must be mapped to SRAM.
870 \param [in] IRQn Interrupt number
871 \param [in] vector Address of interrupt handler function
872 */
873__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
874{
875#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
876 uint32_t *vectors = (uint32_t *)SCB->VTOR;
877#else
878 uint32_t *vectors = (uint32_t *)0x0U;
879#endif
880 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
881}
882
883
884/**
885 \brief Get Interrupt Vector
886 \details Reads an interrupt vector from interrupt vector table.
887 The interrupt number can be positive to specify a device specific interrupt,
888 or negative to specify a processor exception.
889 \param [in] IRQn Interrupt number.
890 \return Address of interrupt handler function
891 */
892__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
893{
894#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
895 uint32_t *vectors = (uint32_t *)SCB->VTOR;
896#else
897 uint32_t *vectors = (uint32_t *)0x0U;
898#endif
899 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
900
901}
902
903
904/**
905 \brief System Reset
906 \details Initiates a system reset request to reset the MCU.
907 */
908__STATIC_INLINE void NVIC_SystemReset(void)
909{
910 __DSB(); /* Ensure all outstanding memory accesses included
911 buffered write are completed before reset */
912 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
913 SCB_AIRCR_SYSRESETREQ_Msk);
914 __DSB(); /* Ensure completion of memory access */
915
916 for(;;) /* wait until reset */
917 {
918 __NOP();
919 }
920}
921
922/*@} end of CMSIS_Core_NVICFunctions */
923
924
925/* ########################## FPU functions #################################### */
926/**
927 \ingroup CMSIS_Core_FunctionInterface
928 \defgroup CMSIS_Core_FpuFunctions FPU Functions
929 \brief Function that provides FPU type.
930 @{
931 */
932
933/**
934 \brief get FPU type
935 \details returns the FPU type
936 \returns
937 - \b 0: No FPU
938 - \b 1: Single precision FPU
939 - \b 2: Double + Single precision FPU
940 */
941__STATIC_INLINE uint32_t SCB_GetFPUType(void)
942{
943 return 0U; /* No FPU */
944}
945
946
947/*@} end of CMSIS_Core_FpuFunctions */
948
949
950
951/* ################################## SysTick function ############################################ */
952/**
953 \ingroup CMSIS_Core_FunctionInterface
954 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
955 \brief Functions that configure the System.
956 @{
957 */
958
959#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
960
961/**
962 \brief System Tick Configuration
963 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
964 Counter is in free running mode to generate periodic interrupts.
965 \param [in] ticks Number of ticks between two interrupts.
966 \return 0 Function succeeded.
967 \return 1 Function failed.
968 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
969 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
970 must contain a vendor-specific implementation of this function.
971 */
972__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
973{
974 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
975 {
976 return (1UL); /* Reload value impossible */
977 }
978
979 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
980 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
981 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
982 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
983 SysTick_CTRL_TICKINT_Msk |
984 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
985 return (0UL); /* Function successful */
986}
987
988#endif
989
990/*@} end of CMSIS_Core_SysTickFunctions */
991
992
993
994
995#ifdef __cplusplus
996}
997#endif
998
999#endif /* __CORE_CM0PLUS_H_DEPENDANT */
1000
1001#endif /* __CMSIS_GENERIC */