Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame^] | 1 | /**************************************************************************//** |
| 2 | * @file cmsis_gcc.h |
| 3 | * @brief CMSIS compiler GCC header file |
| 4 | * @version V5.0.1 |
| 5 | * @date 02. February 2017 |
| 6 | ******************************************************************************/ |
| 7 | /* |
| 8 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved. |
| 9 | * |
| 10 | * SPDX-License-Identifier: Apache-2.0 |
| 11 | * |
| 12 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| 13 | * not use this file except in compliance with the License. |
| 14 | * You may obtain a copy of the License at |
| 15 | * |
| 16 | * www.apache.org/licenses/LICENSE-2.0 |
| 17 | * |
| 18 | * Unless required by applicable law or agreed to in writing, software |
| 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 21 | * See the License for the specific language governing permissions and |
| 22 | * limitations under the License. |
| 23 | */ |
| 24 | |
| 25 | #ifndef __CMSIS_GCC_H |
| 26 | #define __CMSIS_GCC_H |
| 27 | |
| 28 | /* ignore some GCC warnings */ |
| 29 | #pragma GCC diagnostic push |
| 30 | #pragma GCC diagnostic ignored "-Wsign-conversion" |
| 31 | #pragma GCC diagnostic ignored "-Wconversion" |
| 32 | #pragma GCC diagnostic ignored "-Wunused-parameter" |
| 33 | |
| 34 | /* CMSIS compiler specific defines */ |
| 35 | #ifndef __ASM |
| 36 | #define __ASM __asm |
| 37 | #endif |
| 38 | #ifndef __INLINE |
| 39 | #define __INLINE inline |
| 40 | #endif |
| 41 | #ifndef __STATIC_INLINE |
| 42 | #define __STATIC_INLINE static inline |
| 43 | #endif |
| 44 | #ifndef __NO_RETURN |
| 45 | #define __NO_RETURN __attribute__((noreturn)) |
| 46 | #endif |
| 47 | #ifndef __USED |
| 48 | #define __USED __attribute__((used)) |
| 49 | #endif |
| 50 | #ifndef __WEAK |
| 51 | #define __WEAK __attribute__((weak)) |
| 52 | #endif |
| 53 | #ifndef __UNALIGNED_UINT32 |
| 54 | #pragma GCC diagnostic push |
| 55 | #pragma GCC diagnostic ignored "-Wpacked" |
| 56 | #pragma GCC diagnostic ignored "-Wattributes" |
| 57 | struct __attribute__((packed)) T_UINT32 { uint32_t v; }; |
| 58 | #pragma GCC diagnostic pop |
| 59 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) |
| 60 | #endif |
| 61 | #ifndef __ALIGNED |
| 62 | #define __ALIGNED(x) __attribute__((aligned(x))) |
| 63 | #endif |
| 64 | #ifndef __PACKED |
| 65 | #define __PACKED __attribute__((packed, aligned(1))) |
| 66 | #endif |
| 67 | #ifndef __PACKED_STRUCT |
| 68 | #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) |
| 69 | #endif |
| 70 | |
| 71 | |
| 72 | /* ########################### Core Function Access ########################### */ |
| 73 | /** \ingroup CMSIS_Core_FunctionInterface |
| 74 | \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions |
| 75 | @{ |
| 76 | */ |
| 77 | |
| 78 | /** |
| 79 | \brief Enable IRQ Interrupts |
| 80 | \details Enables IRQ interrupts by clearing the I-bit in the CPSR. |
| 81 | Can only be executed in Privileged modes. |
| 82 | */ |
| 83 | __attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) |
| 84 | { |
| 85 | __ASM volatile ("cpsie i" : : : "memory"); |
| 86 | } |
| 87 | |
| 88 | |
| 89 | /** |
| 90 | \brief Disable IRQ Interrupts |
| 91 | \details Disables IRQ interrupts by setting the I-bit in the CPSR. |
| 92 | Can only be executed in Privileged modes. |
| 93 | */ |
| 94 | __attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) |
| 95 | { |
| 96 | __ASM volatile ("cpsid i" : : : "memory"); |
| 97 | } |
| 98 | |
| 99 | |
| 100 | /** |
| 101 | \brief Get Control Register |
| 102 | \details Returns the content of the Control Register. |
| 103 | \return Control Register value |
| 104 | */ |
| 105 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) |
| 106 | { |
| 107 | uint32_t result; |
| 108 | |
| 109 | __ASM volatile ("MRS %0, control" : "=r" (result) ); |
| 110 | return(result); |
| 111 | } |
| 112 | |
| 113 | |
| 114 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
| 115 | /** |
| 116 | \brief Get Control Register (non-secure) |
| 117 | \details Returns the content of the non-secure Control Register when in secure mode. |
| 118 | \return non-secure Control Register value |
| 119 | */ |
| 120 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) |
| 121 | { |
| 122 | uint32_t result; |
| 123 | |
| 124 | __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); |
| 125 | return(result); |
| 126 | } |
| 127 | #endif |
| 128 | |
| 129 | |
| 130 | /** |
| 131 | \brief Set Control Register |
| 132 | \details Writes the given value to the Control Register. |
| 133 | \param [in] control Control Register value to set |
| 134 | */ |
| 135 | __attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) |
| 136 | { |
| 137 | __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); |
| 138 | } |
| 139 | |
| 140 | |
| 141 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
| 142 | /** |
| 143 | \brief Set Control Register (non-secure) |
| 144 | \details Writes the given value to the non-secure Control Register when in secure state. |
| 145 | \param [in] control Control Register value to set |
| 146 | */ |
| 147 | __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) |
| 148 | { |
| 149 | __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); |
| 150 | } |
| 151 | #endif |
| 152 | |
| 153 | |
| 154 | /** |
| 155 | \brief Get IPSR Register |
| 156 | \details Returns the content of the IPSR Register. |
| 157 | \return IPSR Register value |
| 158 | */ |
| 159 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) |
| 160 | { |
| 161 | uint32_t result; |
| 162 | |
| 163 | __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); |
| 164 | return(result); |
| 165 | } |
| 166 | |
| 167 | |
| 168 | /** |
| 169 | \brief Get APSR Register |
| 170 | \details Returns the content of the APSR Register. |
| 171 | \return APSR Register value |
| 172 | */ |
| 173 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) |
| 174 | { |
| 175 | uint32_t result; |
| 176 | |
| 177 | __ASM volatile ("MRS %0, apsr" : "=r" (result) ); |
| 178 | return(result); |
| 179 | } |
| 180 | |
| 181 | |
| 182 | /** |
| 183 | \brief Get xPSR Register |
| 184 | \details Returns the content of the xPSR Register. |
| 185 | \return xPSR Register value |
| 186 | */ |
| 187 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) |
| 188 | { |
| 189 | uint32_t result; |
| 190 | |
| 191 | __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); |
| 192 | return(result); |
| 193 | } |
| 194 | |
| 195 | |
| 196 | /** |
| 197 | \brief Get Process Stack Pointer |
| 198 | \details Returns the current value of the Process Stack Pointer (PSP). |
| 199 | \return PSP Register value |
| 200 | */ |
| 201 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) |
| 202 | { |
| 203 | register uint32_t result; |
| 204 | |
| 205 | __ASM volatile ("MRS %0, psp" : "=r" (result) ); |
| 206 | return(result); |
| 207 | } |
| 208 | |
| 209 | |
| 210 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
| 211 | /** |
| 212 | \brief Get Process Stack Pointer (non-secure) |
| 213 | \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. |
| 214 | \return PSP Register value |
| 215 | */ |
| 216 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) |
| 217 | { |
| 218 | register uint32_t result; |
| 219 | |
| 220 | __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); |
| 221 | return(result); |
| 222 | } |
| 223 | #endif |
| 224 | |
| 225 | |
| 226 | /** |
| 227 | \brief Set Process Stack Pointer |
| 228 | \details Assigns the given value to the Process Stack Pointer (PSP). |
| 229 | \param [in] topOfProcStack Process Stack Pointer value to set |
| 230 | */ |
| 231 | __attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) |
| 232 | { |
| 233 | __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); |
| 234 | } |
| 235 | |
| 236 | |
| 237 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
| 238 | /** |
| 239 | \brief Set Process Stack Pointer (non-secure) |
| 240 | \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. |
| 241 | \param [in] topOfProcStack Process Stack Pointer value to set |
| 242 | */ |
| 243 | __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) |
| 244 | { |
| 245 | __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); |
| 246 | } |
| 247 | #endif |
| 248 | |
| 249 | |
| 250 | /** |
| 251 | \brief Get Main Stack Pointer |
| 252 | \details Returns the current value of the Main Stack Pointer (MSP). |
| 253 | \return MSP Register value |
| 254 | */ |
| 255 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) |
| 256 | { |
| 257 | register uint32_t result; |
| 258 | |
| 259 | __ASM volatile ("MRS %0, msp" : "=r" (result) ); |
| 260 | return(result); |
| 261 | } |
| 262 | |
| 263 | |
| 264 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
| 265 | /** |
| 266 | \brief Get Main Stack Pointer (non-secure) |
| 267 | \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. |
| 268 | \return MSP Register value |
| 269 | */ |
| 270 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) |
| 271 | { |
| 272 | register uint32_t result; |
| 273 | |
| 274 | __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); |
| 275 | return(result); |
| 276 | } |
| 277 | #endif |
| 278 | |
| 279 | |
| 280 | /** |
| 281 | \brief Set Main Stack Pointer |
| 282 | \details Assigns the given value to the Main Stack Pointer (MSP). |
| 283 | \param [in] topOfMainStack Main Stack Pointer value to set |
| 284 | */ |
| 285 | __attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) |
| 286 | { |
| 287 | __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); |
| 288 | } |
| 289 | |
| 290 | |
| 291 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
| 292 | /** |
| 293 | \brief Set Main Stack Pointer (non-secure) |
| 294 | \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. |
| 295 | \param [in] topOfMainStack Main Stack Pointer value to set |
| 296 | */ |
| 297 | __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) |
| 298 | { |
| 299 | __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); |
| 300 | } |
| 301 | #endif |
| 302 | |
| 303 | |
| 304 | /** |
| 305 | \brief Get Priority Mask |
| 306 | \details Returns the current state of the priority mask bit from the Priority Mask Register. |
| 307 | \return Priority Mask value |
| 308 | */ |
| 309 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) |
| 310 | { |
| 311 | uint32_t result; |
| 312 | |
| 313 | __ASM volatile ("MRS %0, primask" : "=r" (result) ); |
| 314 | return(result); |
| 315 | } |
| 316 | |
| 317 | |
| 318 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
| 319 | /** |
| 320 | \brief Get Priority Mask (non-secure) |
| 321 | \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. |
| 322 | \return Priority Mask value |
| 323 | */ |
| 324 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) |
| 325 | { |
| 326 | uint32_t result; |
| 327 | |
| 328 | __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); |
| 329 | return(result); |
| 330 | } |
| 331 | #endif |
| 332 | |
| 333 | |
| 334 | /** |
| 335 | \brief Set Priority Mask |
| 336 | \details Assigns the given value to the Priority Mask Register. |
| 337 | \param [in] priMask Priority Mask |
| 338 | */ |
| 339 | __attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) |
| 340 | { |
| 341 | __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); |
| 342 | } |
| 343 | |
| 344 | |
| 345 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
| 346 | /** |
| 347 | \brief Set Priority Mask (non-secure) |
| 348 | \details Assigns the given value to the non-secure Priority Mask Register when in secure state. |
| 349 | \param [in] priMask Priority Mask |
| 350 | */ |
| 351 | __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) |
| 352 | { |
| 353 | __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); |
| 354 | } |
| 355 | #endif |
| 356 | |
| 357 | |
| 358 | #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ |
| 359 | (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ |
| 360 | (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) |
| 361 | /** |
| 362 | \brief Enable FIQ |
| 363 | \details Enables FIQ interrupts by clearing the F-bit in the CPSR. |
| 364 | Can only be executed in Privileged modes. |
| 365 | */ |
| 366 | __attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) |
| 367 | { |
| 368 | __ASM volatile ("cpsie f" : : : "memory"); |
| 369 | } |
| 370 | |
| 371 | |
| 372 | /** |
| 373 | \brief Disable FIQ |
| 374 | \details Disables FIQ interrupts by setting the F-bit in the CPSR. |
| 375 | Can only be executed in Privileged modes. |
| 376 | */ |
| 377 | __attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) |
| 378 | { |
| 379 | __ASM volatile ("cpsid f" : : : "memory"); |
| 380 | } |
| 381 | |
| 382 | |
| 383 | /** |
| 384 | \brief Get Base Priority |
| 385 | \details Returns the current value of the Base Priority register. |
| 386 | \return Base Priority register value |
| 387 | */ |
| 388 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) |
| 389 | { |
| 390 | uint32_t result; |
| 391 | |
| 392 | __ASM volatile ("MRS %0, basepri" : "=r" (result) ); |
| 393 | return(result); |
| 394 | } |
| 395 | |
| 396 | |
| 397 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
| 398 | /** |
| 399 | \brief Get Base Priority (non-secure) |
| 400 | \details Returns the current value of the non-secure Base Priority register when in secure state. |
| 401 | \return Base Priority register value |
| 402 | */ |
| 403 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) |
| 404 | { |
| 405 | uint32_t result; |
| 406 | |
| 407 | __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); |
| 408 | return(result); |
| 409 | } |
| 410 | #endif |
| 411 | |
| 412 | |
| 413 | /** |
| 414 | \brief Set Base Priority |
| 415 | \details Assigns the given value to the Base Priority register. |
| 416 | \param [in] basePri Base Priority value to set |
| 417 | */ |
| 418 | __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) |
| 419 | { |
| 420 | __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); |
| 421 | } |
| 422 | |
| 423 | |
| 424 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
| 425 | /** |
| 426 | \brief Set Base Priority (non-secure) |
| 427 | \details Assigns the given value to the non-secure Base Priority register when in secure state. |
| 428 | \param [in] basePri Base Priority value to set |
| 429 | */ |
| 430 | __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) |
| 431 | { |
| 432 | __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); |
| 433 | } |
| 434 | #endif |
| 435 | |
| 436 | |
| 437 | /** |
| 438 | \brief Set Base Priority with condition |
| 439 | \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, |
| 440 | or the new value increases the BASEPRI priority level. |
| 441 | \param [in] basePri Base Priority value to set |
| 442 | */ |
| 443 | __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) |
| 444 | { |
| 445 | __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); |
| 446 | } |
| 447 | |
| 448 | |
| 449 | /** |
| 450 | \brief Get Fault Mask |
| 451 | \details Returns the current value of the Fault Mask register. |
| 452 | \return Fault Mask register value |
| 453 | */ |
| 454 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) |
| 455 | { |
| 456 | uint32_t result; |
| 457 | |
| 458 | __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); |
| 459 | return(result); |
| 460 | } |
| 461 | |
| 462 | |
| 463 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
| 464 | /** |
| 465 | \brief Get Fault Mask (non-secure) |
| 466 | \details Returns the current value of the non-secure Fault Mask register when in secure state. |
| 467 | \return Fault Mask register value |
| 468 | */ |
| 469 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) |
| 470 | { |
| 471 | uint32_t result; |
| 472 | |
| 473 | __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); |
| 474 | return(result); |
| 475 | } |
| 476 | #endif |
| 477 | |
| 478 | |
| 479 | /** |
| 480 | \brief Set Fault Mask |
| 481 | \details Assigns the given value to the Fault Mask register. |
| 482 | \param [in] faultMask Fault Mask value to set |
| 483 | */ |
| 484 | __attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) |
| 485 | { |
| 486 | __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); |
| 487 | } |
| 488 | |
| 489 | |
| 490 | #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) |
| 491 | /** |
| 492 | \brief Set Fault Mask (non-secure) |
| 493 | \details Assigns the given value to the non-secure Fault Mask register when in secure state. |
| 494 | \param [in] faultMask Fault Mask value to set |
| 495 | */ |
| 496 | __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) |
| 497 | { |
| 498 | __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); |
| 499 | } |
| 500 | #endif |
| 501 | |
| 502 | #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ |
| 503 | (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ |
| 504 | (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ |
| 505 | |
| 506 | |
| 507 | #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ |
| 508 | (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) |
| 509 | |
| 510 | /** |
| 511 | \brief Get Process Stack Pointer Limit |
| 512 | \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). |
| 513 | \return PSPLIM Register value |
| 514 | */ |
| 515 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) |
| 516 | { |
| 517 | register uint32_t result; |
| 518 | |
| 519 | __ASM volatile ("MRS %0, psplim" : "=r" (result) ); |
| 520 | return(result); |
| 521 | } |
| 522 | |
| 523 | |
| 524 | #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ |
| 525 | (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) |
| 526 | /** |
| 527 | \brief Get Process Stack Pointer Limit (non-secure) |
| 528 | \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. |
| 529 | \return PSPLIM Register value |
| 530 | */ |
| 531 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) |
| 532 | { |
| 533 | register uint32_t result; |
| 534 | |
| 535 | __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); |
| 536 | return(result); |
| 537 | } |
| 538 | #endif |
| 539 | |
| 540 | |
| 541 | /** |
| 542 | \brief Set Process Stack Pointer Limit |
| 543 | \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). |
| 544 | \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set |
| 545 | */ |
| 546 | __attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) |
| 547 | { |
| 548 | __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); |
| 549 | } |
| 550 | |
| 551 | |
| 552 | #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ |
| 553 | (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) |
| 554 | /** |
| 555 | \brief Set Process Stack Pointer (non-secure) |
| 556 | \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. |
| 557 | \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set |
| 558 | */ |
| 559 | __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) |
| 560 | { |
| 561 | __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); |
| 562 | } |
| 563 | #endif |
| 564 | |
| 565 | |
| 566 | /** |
| 567 | \brief Get Main Stack Pointer Limit |
| 568 | \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). |
| 569 | \return MSPLIM Register value |
| 570 | */ |
| 571 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) |
| 572 | { |
| 573 | register uint32_t result; |
| 574 | |
| 575 | __ASM volatile ("MRS %0, msplim" : "=r" (result) ); |
| 576 | |
| 577 | return(result); |
| 578 | } |
| 579 | |
| 580 | |
| 581 | #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ |
| 582 | (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) |
| 583 | /** |
| 584 | \brief Get Main Stack Pointer Limit (non-secure) |
| 585 | \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. |
| 586 | \return MSPLIM Register value |
| 587 | */ |
| 588 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) |
| 589 | { |
| 590 | register uint32_t result; |
| 591 | |
| 592 | __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); |
| 593 | return(result); |
| 594 | } |
| 595 | #endif |
| 596 | |
| 597 | |
| 598 | /** |
| 599 | \brief Set Main Stack Pointer Limit |
| 600 | \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). |
| 601 | \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set |
| 602 | */ |
| 603 | __attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) |
| 604 | { |
| 605 | __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); |
| 606 | } |
| 607 | |
| 608 | |
| 609 | #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \ |
| 610 | (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) ) |
| 611 | /** |
| 612 | \brief Set Main Stack Pointer Limit (non-secure) |
| 613 | \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. |
| 614 | \param [in] MainStackPtrLimit Main Stack Pointer value to set |
| 615 | */ |
| 616 | __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) |
| 617 | { |
| 618 | __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); |
| 619 | } |
| 620 | #endif |
| 621 | |
| 622 | #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ |
| 623 | (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ |
| 624 | |
| 625 | |
| 626 | #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ |
| 627 | (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) |
| 628 | |
| 629 | /** |
| 630 | \brief Get FPSCR |
| 631 | \details Returns the current value of the Floating Point Status/Control register. |
| 632 | \return Floating Point Status/Control register value |
| 633 | */ |
| 634 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) |
| 635 | { |
| 636 | #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ |
| 637 | (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) |
| 638 | uint32_t result; |
| 639 | |
| 640 | __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); |
| 641 | return(result); |
| 642 | #else |
| 643 | return(0U); |
| 644 | #endif |
| 645 | } |
| 646 | |
| 647 | |
| 648 | /** |
| 649 | \brief Set FPSCR |
| 650 | \details Assigns the given value to the Floating Point Status/Control register. |
| 651 | \param [in] fpscr Floating Point Status/Control value to set |
| 652 | */ |
| 653 | __attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) |
| 654 | { |
| 655 | #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ |
| 656 | (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) |
| 657 | __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); |
| 658 | #else |
| 659 | (void)fpscr; |
| 660 | #endif |
| 661 | } |
| 662 | |
| 663 | #endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ |
| 664 | (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ |
| 665 | |
| 666 | |
| 667 | |
| 668 | /*@} end of CMSIS_Core_RegAccFunctions */ |
| 669 | |
| 670 | |
| 671 | /* ########################## Core Instruction Access ######################### */ |
| 672 | /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface |
| 673 | Access to dedicated instructions |
| 674 | @{ |
| 675 | */ |
| 676 | |
| 677 | /* Define macros for porting to both thumb1 and thumb2. |
| 678 | * For thumb1, use low register (r0-r7), specified by constraint "l" |
| 679 | * Otherwise, use general registers, specified by constraint "r" */ |
| 680 | #if defined (__thumb__) && !defined (__thumb2__) |
| 681 | #define __CMSIS_GCC_OUT_REG(r) "=l" (r) |
| 682 | #define __CMSIS_GCC_RW_REG(r) "+l" (r) |
| 683 | #define __CMSIS_GCC_USE_REG(r) "l" (r) |
| 684 | #else |
| 685 | #define __CMSIS_GCC_OUT_REG(r) "=r" (r) |
| 686 | #define __CMSIS_GCC_RW_REG(r) "+r" (r) |
| 687 | #define __CMSIS_GCC_USE_REG(r) "r" (r) |
| 688 | #endif |
| 689 | |
| 690 | /** |
| 691 | \brief No Operation |
| 692 | \details No Operation does nothing. This instruction can be used for code alignment purposes. |
| 693 | */ |
| 694 | //__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) |
| 695 | //{ |
| 696 | // __ASM volatile ("nop"); |
| 697 | //} |
| 698 | #define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */ |
| 699 | |
| 700 | /** |
| 701 | \brief Wait For Interrupt |
| 702 | \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. |
| 703 | */ |
| 704 | //__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) |
| 705 | //{ |
| 706 | // __ASM volatile ("wfi"); |
| 707 | //} |
| 708 | #define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */ |
| 709 | |
| 710 | |
| 711 | /** |
| 712 | \brief Wait For Event |
| 713 | \details Wait For Event is a hint instruction that permits the processor to enter |
| 714 | a low-power state until one of a number of events occurs. |
| 715 | */ |
| 716 | //__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) |
| 717 | //{ |
| 718 | // __ASM volatile ("wfe"); |
| 719 | //} |
| 720 | #define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */ |
| 721 | |
| 722 | |
| 723 | /** |
| 724 | \brief Send Event |
| 725 | \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. |
| 726 | */ |
| 727 | //__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) |
| 728 | //{ |
| 729 | // __ASM volatile ("sev"); |
| 730 | //} |
| 731 | #define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */ |
| 732 | |
| 733 | |
| 734 | /** |
| 735 | \brief Instruction Synchronization Barrier |
| 736 | \details Instruction Synchronization Barrier flushes the pipeline in the processor, |
| 737 | so that all instructions following the ISB are fetched from cache or memory, |
| 738 | after the instruction has been completed. |
| 739 | */ |
| 740 | __attribute__((always_inline)) __STATIC_INLINE void __ISB(void) |
| 741 | { |
| 742 | __ASM volatile ("isb 0xF":::"memory"); |
| 743 | } |
| 744 | |
| 745 | |
| 746 | /** |
| 747 | \brief Data Synchronization Barrier |
| 748 | \details Acts as a special kind of Data Memory Barrier. |
| 749 | It completes when all explicit memory accesses before this instruction complete. |
| 750 | */ |
| 751 | __attribute__((always_inline)) __STATIC_INLINE void __DSB(void) |
| 752 | { |
| 753 | __ASM volatile ("dsb 0xF":::"memory"); |
| 754 | } |
| 755 | |
| 756 | |
| 757 | /** |
| 758 | \brief Data Memory Barrier |
| 759 | \details Ensures the apparent order of the explicit memory operations before |
| 760 | and after the instruction, without ensuring their completion. |
| 761 | */ |
| 762 | __attribute__((always_inline)) __STATIC_INLINE void __DMB(void) |
| 763 | { |
| 764 | __ASM volatile ("dmb 0xF":::"memory"); |
| 765 | } |
| 766 | |
| 767 | |
| 768 | /** |
| 769 | \brief Reverse byte order (32 bit) |
| 770 | \details Reverses the byte order in integer value. |
| 771 | \param [in] value Value to reverse |
| 772 | \return Reversed value |
| 773 | */ |
| 774 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) |
| 775 | { |
| 776 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) |
| 777 | return __builtin_bswap32(value); |
| 778 | #else |
| 779 | uint32_t result; |
| 780 | |
| 781 | __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); |
| 782 | return(result); |
| 783 | #endif |
| 784 | } |
| 785 | |
| 786 | |
| 787 | /** |
| 788 | \brief Reverse byte order (16 bit) |
| 789 | \details Reverses the byte order in two unsigned short values. |
| 790 | \param [in] value Value to reverse |
| 791 | \return Reversed value |
| 792 | */ |
| 793 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) |
| 794 | { |
| 795 | uint32_t result; |
| 796 | |
| 797 | __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); |
| 798 | return(result); |
| 799 | } |
| 800 | |
| 801 | |
| 802 | /** |
| 803 | \brief Reverse byte order in signed short value |
| 804 | \details Reverses the byte order in a signed short value with sign extension to integer. |
| 805 | \param [in] value Value to reverse |
| 806 | \return Reversed value |
| 807 | */ |
| 808 | __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) |
| 809 | { |
| 810 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) |
| 811 | return (short)__builtin_bswap16(value); |
| 812 | #else |
| 813 | int32_t result; |
| 814 | |
| 815 | __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); |
| 816 | return(result); |
| 817 | #endif |
| 818 | } |
| 819 | |
| 820 | |
| 821 | /** |
| 822 | \brief Rotate Right in unsigned value (32 bit) |
| 823 | \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. |
| 824 | \param [in] op1 Value to rotate |
| 825 | \param [in] op2 Number of Bits to rotate |
| 826 | \return Rotated value |
| 827 | */ |
| 828 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) |
| 829 | { |
| 830 | return (op1 >> op2) | (op1 << (32U - op2)); |
| 831 | } |
| 832 | |
| 833 | |
| 834 | /** |
| 835 | \brief Breakpoint |
| 836 | \details Causes the processor to enter Debug state. |
| 837 | Debug tools can use this to investigate system state when the instruction at a particular address is reached. |
| 838 | \param [in] value is ignored by the processor. |
| 839 | If required, a debugger can use it to store additional information about the breakpoint. |
| 840 | */ |
| 841 | #define __BKPT(value) __ASM volatile ("bkpt "#value) |
| 842 | |
| 843 | |
| 844 | /** |
| 845 | \brief Reverse bit order of value |
| 846 | \details Reverses the bit order of the given value. |
| 847 | \param [in] value Value to reverse |
| 848 | \return Reversed value |
| 849 | */ |
| 850 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) |
| 851 | { |
| 852 | uint32_t result; |
| 853 | |
| 854 | #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ |
| 855 | (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ |
| 856 | (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) |
| 857 | __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); |
| 858 | #else |
| 859 | int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ |
| 860 | |
| 861 | result = value; /* r will be reversed bits of v; first get LSB of v */ |
| 862 | for (value >>= 1U; value; value >>= 1U) |
| 863 | { |
| 864 | result <<= 1U; |
| 865 | result |= value & 1U; |
| 866 | s--; |
| 867 | } |
| 868 | result <<= s; /* shift when v's highest bits are zero */ |
| 869 | #endif |
| 870 | return(result); |
| 871 | } |
| 872 | |
| 873 | |
| 874 | /** |
| 875 | \brief Count leading zeros |
| 876 | \details Counts the number of leading zeros of a data value. |
| 877 | \param [in] value Value to count the leading zeros |
| 878 | \return number of leading zeros in value |
| 879 | */ |
| 880 | #define __CLZ __builtin_clz |
| 881 | |
| 882 | |
| 883 | #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ |
| 884 | (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ |
| 885 | (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ |
| 886 | (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) |
| 887 | /** |
| 888 | \brief LDR Exclusive (8 bit) |
| 889 | \details Executes a exclusive LDR instruction for 8 bit value. |
| 890 | \param [in] ptr Pointer to data |
| 891 | \return value of type uint8_t at (*ptr) |
| 892 | */ |
| 893 | __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) |
| 894 | { |
| 895 | uint32_t result; |
| 896 | |
| 897 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) |
| 898 | __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); |
| 899 | #else |
| 900 | /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not |
| 901 | accepted by assembler. So has to use following less efficient pattern. |
| 902 | */ |
| 903 | __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); |
| 904 | #endif |
| 905 | return ((uint8_t) result); /* Add explicit type cast here */ |
| 906 | } |
| 907 | |
| 908 | |
| 909 | /** |
| 910 | \brief LDR Exclusive (16 bit) |
| 911 | \details Executes a exclusive LDR instruction for 16 bit values. |
| 912 | \param [in] ptr Pointer to data |
| 913 | \return value of type uint16_t at (*ptr) |
| 914 | */ |
| 915 | __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) |
| 916 | { |
| 917 | uint32_t result; |
| 918 | |
| 919 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) |
| 920 | __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); |
| 921 | #else |
| 922 | /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not |
| 923 | accepted by assembler. So has to use following less efficient pattern. |
| 924 | */ |
| 925 | __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); |
| 926 | #endif |
| 927 | return ((uint16_t) result); /* Add explicit type cast here */ |
| 928 | } |
| 929 | |
| 930 | |
| 931 | /** |
| 932 | \brief LDR Exclusive (32 bit) |
| 933 | \details Executes a exclusive LDR instruction for 32 bit values. |
| 934 | \param [in] ptr Pointer to data |
| 935 | \return value of type uint32_t at (*ptr) |
| 936 | */ |
| 937 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) |
| 938 | { |
| 939 | uint32_t result; |
| 940 | |
| 941 | __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); |
| 942 | return(result); |
| 943 | } |
| 944 | |
| 945 | |
| 946 | /** |
| 947 | \brief STR Exclusive (8 bit) |
| 948 | \details Executes a exclusive STR instruction for 8 bit values. |
| 949 | \param [in] value Value to store |
| 950 | \param [in] ptr Pointer to location |
| 951 | \return 0 Function succeeded |
| 952 | \return 1 Function failed |
| 953 | */ |
| 954 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) |
| 955 | { |
| 956 | uint32_t result; |
| 957 | |
| 958 | __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); |
| 959 | return(result); |
| 960 | } |
| 961 | |
| 962 | |
| 963 | /** |
| 964 | \brief STR Exclusive (16 bit) |
| 965 | \details Executes a exclusive STR instruction for 16 bit values. |
| 966 | \param [in] value Value to store |
| 967 | \param [in] ptr Pointer to location |
| 968 | \return 0 Function succeeded |
| 969 | \return 1 Function failed |
| 970 | */ |
| 971 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) |
| 972 | { |
| 973 | uint32_t result; |
| 974 | |
| 975 | __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); |
| 976 | return(result); |
| 977 | } |
| 978 | |
| 979 | |
| 980 | /** |
| 981 | \brief STR Exclusive (32 bit) |
| 982 | \details Executes a exclusive STR instruction for 32 bit values. |
| 983 | \param [in] value Value to store |
| 984 | \param [in] ptr Pointer to location |
| 985 | \return 0 Function succeeded |
| 986 | \return 1 Function failed |
| 987 | */ |
| 988 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) |
| 989 | { |
| 990 | uint32_t result; |
| 991 | |
| 992 | __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); |
| 993 | return(result); |
| 994 | } |
| 995 | |
| 996 | |
| 997 | /** |
| 998 | \brief Remove the exclusive lock |
| 999 | \details Removes the exclusive lock which is created by LDREX. |
| 1000 | */ |
| 1001 | __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) |
| 1002 | { |
| 1003 | __ASM volatile ("clrex" ::: "memory"); |
| 1004 | } |
| 1005 | |
| 1006 | #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ |
| 1007 | (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ |
| 1008 | (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ |
| 1009 | (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ |
| 1010 | |
| 1011 | |
| 1012 | #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ |
| 1013 | (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ |
| 1014 | (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) |
| 1015 | /** |
| 1016 | \brief Signed Saturate |
| 1017 | \details Saturates a signed value. |
| 1018 | \param [in] value Value to be saturated |
| 1019 | \param [in] sat Bit position to saturate to (1..32) |
| 1020 | \return Saturated value |
| 1021 | */ |
| 1022 | #define __SSAT(ARG1,ARG2) \ |
| 1023 | ({ \ |
| 1024 | int32_t __RES, __ARG1 = (ARG1); \ |
| 1025 | __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ |
| 1026 | __RES; \ |
| 1027 | }) |
| 1028 | |
| 1029 | |
| 1030 | /** |
| 1031 | \brief Unsigned Saturate |
| 1032 | \details Saturates an unsigned value. |
| 1033 | \param [in] value Value to be saturated |
| 1034 | \param [in] sat Bit position to saturate to (0..31) |
| 1035 | \return Saturated value |
| 1036 | */ |
| 1037 | #define __USAT(ARG1,ARG2) \ |
| 1038 | ({ \ |
| 1039 | uint32_t __RES, __ARG1 = (ARG1); \ |
| 1040 | __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ |
| 1041 | __RES; \ |
| 1042 | }) |
| 1043 | |
| 1044 | |
| 1045 | /** |
| 1046 | \brief Rotate Right with Extend (32 bit) |
| 1047 | \details Moves each bit of a bitstring right by one bit. |
| 1048 | The carry input is shifted in at the left end of the bitstring. |
| 1049 | \param [in] value Value to rotate |
| 1050 | \return Rotated value |
| 1051 | */ |
| 1052 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) |
| 1053 | { |
| 1054 | uint32_t result; |
| 1055 | |
| 1056 | __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); |
| 1057 | return(result); |
| 1058 | } |
| 1059 | |
| 1060 | |
| 1061 | /** |
| 1062 | \brief LDRT Unprivileged (8 bit) |
| 1063 | \details Executes a Unprivileged LDRT instruction for 8 bit value. |
| 1064 | \param [in] ptr Pointer to data |
| 1065 | \return value of type uint8_t at (*ptr) |
| 1066 | */ |
| 1067 | __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) |
| 1068 | { |
| 1069 | uint32_t result; |
| 1070 | |
| 1071 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) |
| 1072 | __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); |
| 1073 | #else |
| 1074 | /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not |
| 1075 | accepted by assembler. So has to use following less efficient pattern. |
| 1076 | */ |
| 1077 | __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); |
| 1078 | #endif |
| 1079 | return ((uint8_t) result); /* Add explicit type cast here */ |
| 1080 | } |
| 1081 | |
| 1082 | |
| 1083 | /** |
| 1084 | \brief LDRT Unprivileged (16 bit) |
| 1085 | \details Executes a Unprivileged LDRT instruction for 16 bit values. |
| 1086 | \param [in] ptr Pointer to data |
| 1087 | \return value of type uint16_t at (*ptr) |
| 1088 | */ |
| 1089 | __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) |
| 1090 | { |
| 1091 | uint32_t result; |
| 1092 | |
| 1093 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) |
| 1094 | __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); |
| 1095 | #else |
| 1096 | /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not |
| 1097 | accepted by assembler. So has to use following less efficient pattern. |
| 1098 | */ |
| 1099 | __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); |
| 1100 | #endif |
| 1101 | return ((uint16_t) result); /* Add explicit type cast here */ |
| 1102 | } |
| 1103 | |
| 1104 | |
| 1105 | /** |
| 1106 | \brief LDRT Unprivileged (32 bit) |
| 1107 | \details Executes a Unprivileged LDRT instruction for 32 bit values. |
| 1108 | \param [in] ptr Pointer to data |
| 1109 | \return value of type uint32_t at (*ptr) |
| 1110 | */ |
| 1111 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) |
| 1112 | { |
| 1113 | uint32_t result; |
| 1114 | |
| 1115 | __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); |
| 1116 | return(result); |
| 1117 | } |
| 1118 | |
| 1119 | |
| 1120 | /** |
| 1121 | \brief STRT Unprivileged (8 bit) |
| 1122 | \details Executes a Unprivileged STRT instruction for 8 bit values. |
| 1123 | \param [in] value Value to store |
| 1124 | \param [in] ptr Pointer to location |
| 1125 | */ |
| 1126 | __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) |
| 1127 | { |
| 1128 | __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); |
| 1129 | } |
| 1130 | |
| 1131 | |
| 1132 | /** |
| 1133 | \brief STRT Unprivileged (16 bit) |
| 1134 | \details Executes a Unprivileged STRT instruction for 16 bit values. |
| 1135 | \param [in] value Value to store |
| 1136 | \param [in] ptr Pointer to location |
| 1137 | */ |
| 1138 | __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) |
| 1139 | { |
| 1140 | __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); |
| 1141 | } |
| 1142 | |
| 1143 | |
| 1144 | /** |
| 1145 | \brief STRT Unprivileged (32 bit) |
| 1146 | \details Executes a Unprivileged STRT instruction for 32 bit values. |
| 1147 | \param [in] value Value to store |
| 1148 | \param [in] ptr Pointer to location |
| 1149 | */ |
| 1150 | __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) |
| 1151 | { |
| 1152 | __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); |
| 1153 | } |
| 1154 | |
| 1155 | #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ |
| 1156 | (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ |
| 1157 | (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ |
| 1158 | |
| 1159 | |
| 1160 | #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ |
| 1161 | (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) |
| 1162 | /** |
| 1163 | \brief Load-Acquire (8 bit) |
| 1164 | \details Executes a LDAB instruction for 8 bit value. |
| 1165 | \param [in] ptr Pointer to data |
| 1166 | \return value of type uint8_t at (*ptr) |
| 1167 | */ |
| 1168 | __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) |
| 1169 | { |
| 1170 | uint32_t result; |
| 1171 | |
| 1172 | __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); |
| 1173 | return ((uint8_t) result); |
| 1174 | } |
| 1175 | |
| 1176 | |
| 1177 | /** |
| 1178 | \brief Load-Acquire (16 bit) |
| 1179 | \details Executes a LDAH instruction for 16 bit values. |
| 1180 | \param [in] ptr Pointer to data |
| 1181 | \return value of type uint16_t at (*ptr) |
| 1182 | */ |
| 1183 | __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) |
| 1184 | { |
| 1185 | uint32_t result; |
| 1186 | |
| 1187 | __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); |
| 1188 | return ((uint16_t) result); |
| 1189 | } |
| 1190 | |
| 1191 | |
| 1192 | /** |
| 1193 | \brief Load-Acquire (32 bit) |
| 1194 | \details Executes a LDA instruction for 32 bit values. |
| 1195 | \param [in] ptr Pointer to data |
| 1196 | \return value of type uint32_t at (*ptr) |
| 1197 | */ |
| 1198 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) |
| 1199 | { |
| 1200 | uint32_t result; |
| 1201 | |
| 1202 | __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); |
| 1203 | return(result); |
| 1204 | } |
| 1205 | |
| 1206 | |
| 1207 | /** |
| 1208 | \brief Store-Release (8 bit) |
| 1209 | \details Executes a STLB instruction for 8 bit values. |
| 1210 | \param [in] value Value to store |
| 1211 | \param [in] ptr Pointer to location |
| 1212 | */ |
| 1213 | __attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) |
| 1214 | { |
| 1215 | __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); |
| 1216 | } |
| 1217 | |
| 1218 | |
| 1219 | /** |
| 1220 | \brief Store-Release (16 bit) |
| 1221 | \details Executes a STLH instruction for 16 bit values. |
| 1222 | \param [in] value Value to store |
| 1223 | \param [in] ptr Pointer to location |
| 1224 | */ |
| 1225 | __attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) |
| 1226 | { |
| 1227 | __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); |
| 1228 | } |
| 1229 | |
| 1230 | |
| 1231 | /** |
| 1232 | \brief Store-Release (32 bit) |
| 1233 | \details Executes a STL instruction for 32 bit values. |
| 1234 | \param [in] value Value to store |
| 1235 | \param [in] ptr Pointer to location |
| 1236 | */ |
| 1237 | __attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) |
| 1238 | { |
| 1239 | __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); |
| 1240 | } |
| 1241 | |
| 1242 | |
| 1243 | /** |
| 1244 | \brief Load-Acquire Exclusive (8 bit) |
| 1245 | \details Executes a LDAB exclusive instruction for 8 bit value. |
| 1246 | \param [in] ptr Pointer to data |
| 1247 | \return value of type uint8_t at (*ptr) |
| 1248 | */ |
| 1249 | __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr) |
| 1250 | { |
| 1251 | uint32_t result; |
| 1252 | |
| 1253 | __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); |
| 1254 | return ((uint8_t) result); |
| 1255 | } |
| 1256 | |
| 1257 | |
| 1258 | /** |
| 1259 | \brief Load-Acquire Exclusive (16 bit) |
| 1260 | \details Executes a LDAH exclusive instruction for 16 bit values. |
| 1261 | \param [in] ptr Pointer to data |
| 1262 | \return value of type uint16_t at (*ptr) |
| 1263 | */ |
| 1264 | __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr) |
| 1265 | { |
| 1266 | uint32_t result; |
| 1267 | |
| 1268 | __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); |
| 1269 | return ((uint16_t) result); |
| 1270 | } |
| 1271 | |
| 1272 | |
| 1273 | /** |
| 1274 | \brief Load-Acquire Exclusive (32 bit) |
| 1275 | \details Executes a LDA exclusive instruction for 32 bit values. |
| 1276 | \param [in] ptr Pointer to data |
| 1277 | \return value of type uint32_t at (*ptr) |
| 1278 | */ |
| 1279 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr) |
| 1280 | { |
| 1281 | uint32_t result; |
| 1282 | |
| 1283 | __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); |
| 1284 | return(result); |
| 1285 | } |
| 1286 | |
| 1287 | |
| 1288 | /** |
| 1289 | \brief Store-Release Exclusive (8 bit) |
| 1290 | \details Executes a STLB exclusive instruction for 8 bit values. |
| 1291 | \param [in] value Value to store |
| 1292 | \param [in] ptr Pointer to location |
| 1293 | \return 0 Function succeeded |
| 1294 | \return 1 Function failed |
| 1295 | */ |
| 1296 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) |
| 1297 | { |
| 1298 | uint32_t result; |
| 1299 | |
| 1300 | __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); |
| 1301 | return(result); |
| 1302 | } |
| 1303 | |
| 1304 | |
| 1305 | /** |
| 1306 | \brief Store-Release Exclusive (16 bit) |
| 1307 | \details Executes a STLH exclusive instruction for 16 bit values. |
| 1308 | \param [in] value Value to store |
| 1309 | \param [in] ptr Pointer to location |
| 1310 | \return 0 Function succeeded |
| 1311 | \return 1 Function failed |
| 1312 | */ |
| 1313 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) |
| 1314 | { |
| 1315 | uint32_t result; |
| 1316 | |
| 1317 | __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); |
| 1318 | return(result); |
| 1319 | } |
| 1320 | |
| 1321 | |
| 1322 | /** |
| 1323 | \brief Store-Release Exclusive (32 bit) |
| 1324 | \details Executes a STL exclusive instruction for 32 bit values. |
| 1325 | \param [in] value Value to store |
| 1326 | \param [in] ptr Pointer to location |
| 1327 | \return 0 Function succeeded |
| 1328 | \return 1 Function failed |
| 1329 | */ |
| 1330 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) |
| 1331 | { |
| 1332 | uint32_t result; |
| 1333 | |
| 1334 | __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); |
| 1335 | return(result); |
| 1336 | } |
| 1337 | |
| 1338 | #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ |
| 1339 | (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ |
| 1340 | |
| 1341 | /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ |
| 1342 | |
| 1343 | |
| 1344 | /* ################### Compiler specific Intrinsics ########################### */ |
| 1345 | /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics |
| 1346 | Access to dedicated SIMD instructions |
| 1347 | @{ |
| 1348 | */ |
| 1349 | |
| 1350 | #if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */ |
| 1351 | |
| 1352 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) |
| 1353 | { |
| 1354 | uint32_t result; |
| 1355 | |
| 1356 | __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1357 | return(result); |
| 1358 | } |
| 1359 | |
| 1360 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) |
| 1361 | { |
| 1362 | uint32_t result; |
| 1363 | |
| 1364 | __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1365 | return(result); |
| 1366 | } |
| 1367 | |
| 1368 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) |
| 1369 | { |
| 1370 | uint32_t result; |
| 1371 | |
| 1372 | __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1373 | return(result); |
| 1374 | } |
| 1375 | |
| 1376 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) |
| 1377 | { |
| 1378 | uint32_t result; |
| 1379 | |
| 1380 | __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1381 | return(result); |
| 1382 | } |
| 1383 | |
| 1384 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) |
| 1385 | { |
| 1386 | uint32_t result; |
| 1387 | |
| 1388 | __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1389 | return(result); |
| 1390 | } |
| 1391 | |
| 1392 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) |
| 1393 | { |
| 1394 | uint32_t result; |
| 1395 | |
| 1396 | __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1397 | return(result); |
| 1398 | } |
| 1399 | |
| 1400 | |
| 1401 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) |
| 1402 | { |
| 1403 | uint32_t result; |
| 1404 | |
| 1405 | __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1406 | return(result); |
| 1407 | } |
| 1408 | |
| 1409 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) |
| 1410 | { |
| 1411 | uint32_t result; |
| 1412 | |
| 1413 | __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1414 | return(result); |
| 1415 | } |
| 1416 | |
| 1417 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) |
| 1418 | { |
| 1419 | uint32_t result; |
| 1420 | |
| 1421 | __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1422 | return(result); |
| 1423 | } |
| 1424 | |
| 1425 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) |
| 1426 | { |
| 1427 | uint32_t result; |
| 1428 | |
| 1429 | __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1430 | return(result); |
| 1431 | } |
| 1432 | |
| 1433 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) |
| 1434 | { |
| 1435 | uint32_t result; |
| 1436 | |
| 1437 | __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1438 | return(result); |
| 1439 | } |
| 1440 | |
| 1441 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) |
| 1442 | { |
| 1443 | uint32_t result; |
| 1444 | |
| 1445 | __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1446 | return(result); |
| 1447 | } |
| 1448 | |
| 1449 | |
| 1450 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) |
| 1451 | { |
| 1452 | uint32_t result; |
| 1453 | |
| 1454 | __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1455 | return(result); |
| 1456 | } |
| 1457 | |
| 1458 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) |
| 1459 | { |
| 1460 | uint32_t result; |
| 1461 | |
| 1462 | __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1463 | return(result); |
| 1464 | } |
| 1465 | |
| 1466 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) |
| 1467 | { |
| 1468 | uint32_t result; |
| 1469 | |
| 1470 | __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1471 | return(result); |
| 1472 | } |
| 1473 | |
| 1474 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) |
| 1475 | { |
| 1476 | uint32_t result; |
| 1477 | |
| 1478 | __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1479 | return(result); |
| 1480 | } |
| 1481 | |
| 1482 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) |
| 1483 | { |
| 1484 | uint32_t result; |
| 1485 | |
| 1486 | __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1487 | return(result); |
| 1488 | } |
| 1489 | |
| 1490 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) |
| 1491 | { |
| 1492 | uint32_t result; |
| 1493 | |
| 1494 | __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1495 | return(result); |
| 1496 | } |
| 1497 | |
| 1498 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) |
| 1499 | { |
| 1500 | uint32_t result; |
| 1501 | |
| 1502 | __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1503 | return(result); |
| 1504 | } |
| 1505 | |
| 1506 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) |
| 1507 | { |
| 1508 | uint32_t result; |
| 1509 | |
| 1510 | __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1511 | return(result); |
| 1512 | } |
| 1513 | |
| 1514 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) |
| 1515 | { |
| 1516 | uint32_t result; |
| 1517 | |
| 1518 | __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1519 | return(result); |
| 1520 | } |
| 1521 | |
| 1522 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) |
| 1523 | { |
| 1524 | uint32_t result; |
| 1525 | |
| 1526 | __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1527 | return(result); |
| 1528 | } |
| 1529 | |
| 1530 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) |
| 1531 | { |
| 1532 | uint32_t result; |
| 1533 | |
| 1534 | __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1535 | return(result); |
| 1536 | } |
| 1537 | |
| 1538 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) |
| 1539 | { |
| 1540 | uint32_t result; |
| 1541 | |
| 1542 | __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1543 | return(result); |
| 1544 | } |
| 1545 | |
| 1546 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) |
| 1547 | { |
| 1548 | uint32_t result; |
| 1549 | |
| 1550 | __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1551 | return(result); |
| 1552 | } |
| 1553 | |
| 1554 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) |
| 1555 | { |
| 1556 | uint32_t result; |
| 1557 | |
| 1558 | __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1559 | return(result); |
| 1560 | } |
| 1561 | |
| 1562 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) |
| 1563 | { |
| 1564 | uint32_t result; |
| 1565 | |
| 1566 | __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1567 | return(result); |
| 1568 | } |
| 1569 | |
| 1570 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) |
| 1571 | { |
| 1572 | uint32_t result; |
| 1573 | |
| 1574 | __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1575 | return(result); |
| 1576 | } |
| 1577 | |
| 1578 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) |
| 1579 | { |
| 1580 | uint32_t result; |
| 1581 | |
| 1582 | __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1583 | return(result); |
| 1584 | } |
| 1585 | |
| 1586 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) |
| 1587 | { |
| 1588 | uint32_t result; |
| 1589 | |
| 1590 | __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1591 | return(result); |
| 1592 | } |
| 1593 | |
| 1594 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) |
| 1595 | { |
| 1596 | uint32_t result; |
| 1597 | |
| 1598 | __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1599 | return(result); |
| 1600 | } |
| 1601 | |
| 1602 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) |
| 1603 | { |
| 1604 | uint32_t result; |
| 1605 | |
| 1606 | __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1607 | return(result); |
| 1608 | } |
| 1609 | |
| 1610 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) |
| 1611 | { |
| 1612 | uint32_t result; |
| 1613 | |
| 1614 | __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1615 | return(result); |
| 1616 | } |
| 1617 | |
| 1618 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) |
| 1619 | { |
| 1620 | uint32_t result; |
| 1621 | |
| 1622 | __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1623 | return(result); |
| 1624 | } |
| 1625 | |
| 1626 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) |
| 1627 | { |
| 1628 | uint32_t result; |
| 1629 | |
| 1630 | __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1631 | return(result); |
| 1632 | } |
| 1633 | |
| 1634 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) |
| 1635 | { |
| 1636 | uint32_t result; |
| 1637 | |
| 1638 | __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1639 | return(result); |
| 1640 | } |
| 1641 | |
| 1642 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) |
| 1643 | { |
| 1644 | uint32_t result; |
| 1645 | |
| 1646 | __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1647 | return(result); |
| 1648 | } |
| 1649 | |
| 1650 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) |
| 1651 | { |
| 1652 | uint32_t result; |
| 1653 | |
| 1654 | __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); |
| 1655 | return(result); |
| 1656 | } |
| 1657 | |
| 1658 | #define __SSAT16(ARG1,ARG2) \ |
| 1659 | ({ \ |
| 1660 | int32_t __RES, __ARG1 = (ARG1); \ |
| 1661 | __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ |
| 1662 | __RES; \ |
| 1663 | }) |
| 1664 | |
| 1665 | #define __USAT16(ARG1,ARG2) \ |
| 1666 | ({ \ |
| 1667 | uint32_t __RES, __ARG1 = (ARG1); \ |
| 1668 | __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ |
| 1669 | __RES; \ |
| 1670 | }) |
| 1671 | |
| 1672 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) |
| 1673 | { |
| 1674 | uint32_t result; |
| 1675 | |
| 1676 | __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); |
| 1677 | return(result); |
| 1678 | } |
| 1679 | |
| 1680 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) |
| 1681 | { |
| 1682 | uint32_t result; |
| 1683 | |
| 1684 | __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1685 | return(result); |
| 1686 | } |
| 1687 | |
| 1688 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) |
| 1689 | { |
| 1690 | uint32_t result; |
| 1691 | |
| 1692 | __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); |
| 1693 | return(result); |
| 1694 | } |
| 1695 | |
| 1696 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) |
| 1697 | { |
| 1698 | uint32_t result; |
| 1699 | |
| 1700 | __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1701 | return(result); |
| 1702 | } |
| 1703 | |
| 1704 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) |
| 1705 | { |
| 1706 | uint32_t result; |
| 1707 | |
| 1708 | __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1709 | return(result); |
| 1710 | } |
| 1711 | |
| 1712 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) |
| 1713 | { |
| 1714 | uint32_t result; |
| 1715 | |
| 1716 | __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1717 | return(result); |
| 1718 | } |
| 1719 | |
| 1720 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) |
| 1721 | { |
| 1722 | uint32_t result; |
| 1723 | |
| 1724 | __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); |
| 1725 | return(result); |
| 1726 | } |
| 1727 | |
| 1728 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) |
| 1729 | { |
| 1730 | uint32_t result; |
| 1731 | |
| 1732 | __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); |
| 1733 | return(result); |
| 1734 | } |
| 1735 | |
| 1736 | __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) |
| 1737 | { |
| 1738 | union llreg_u{ |
| 1739 | uint32_t w32[2]; |
| 1740 | uint64_t w64; |
| 1741 | } llr; |
| 1742 | llr.w64 = acc; |
| 1743 | |
| 1744 | #ifndef __ARMEB__ /* Little endian */ |
| 1745 | __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); |
| 1746 | #else /* Big endian */ |
| 1747 | __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); |
| 1748 | #endif |
| 1749 | |
| 1750 | return(llr.w64); |
| 1751 | } |
| 1752 | |
| 1753 | __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) |
| 1754 | { |
| 1755 | union llreg_u{ |
| 1756 | uint32_t w32[2]; |
| 1757 | uint64_t w64; |
| 1758 | } llr; |
| 1759 | llr.w64 = acc; |
| 1760 | |
| 1761 | #ifndef __ARMEB__ /* Little endian */ |
| 1762 | __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); |
| 1763 | #else /* Big endian */ |
| 1764 | __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); |
| 1765 | #endif |
| 1766 | |
| 1767 | return(llr.w64); |
| 1768 | } |
| 1769 | |
| 1770 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) |
| 1771 | { |
| 1772 | uint32_t result; |
| 1773 | |
| 1774 | __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1775 | return(result); |
| 1776 | } |
| 1777 | |
| 1778 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) |
| 1779 | { |
| 1780 | uint32_t result; |
| 1781 | |
| 1782 | __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1783 | return(result); |
| 1784 | } |
| 1785 | |
| 1786 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) |
| 1787 | { |
| 1788 | uint32_t result; |
| 1789 | |
| 1790 | __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); |
| 1791 | return(result); |
| 1792 | } |
| 1793 | |
| 1794 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) |
| 1795 | { |
| 1796 | uint32_t result; |
| 1797 | |
| 1798 | __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); |
| 1799 | return(result); |
| 1800 | } |
| 1801 | |
| 1802 | __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) |
| 1803 | { |
| 1804 | union llreg_u{ |
| 1805 | uint32_t w32[2]; |
| 1806 | uint64_t w64; |
| 1807 | } llr; |
| 1808 | llr.w64 = acc; |
| 1809 | |
| 1810 | #ifndef __ARMEB__ /* Little endian */ |
| 1811 | __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); |
| 1812 | #else /* Big endian */ |
| 1813 | __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); |
| 1814 | #endif |
| 1815 | |
| 1816 | return(llr.w64); |
| 1817 | } |
| 1818 | |
| 1819 | __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) |
| 1820 | { |
| 1821 | union llreg_u{ |
| 1822 | uint32_t w32[2]; |
| 1823 | uint64_t w64; |
| 1824 | } llr; |
| 1825 | llr.w64 = acc; |
| 1826 | |
| 1827 | #ifndef __ARMEB__ /* Little endian */ |
| 1828 | __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); |
| 1829 | #else /* Big endian */ |
| 1830 | __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); |
| 1831 | #endif |
| 1832 | |
| 1833 | return(llr.w64); |
| 1834 | } |
| 1835 | |
| 1836 | __attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) |
| 1837 | { |
| 1838 | uint32_t result; |
| 1839 | |
| 1840 | __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1841 | return(result); |
| 1842 | } |
| 1843 | |
| 1844 | __attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) |
| 1845 | { |
| 1846 | int32_t result; |
| 1847 | |
| 1848 | __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1849 | return(result); |
| 1850 | } |
| 1851 | |
| 1852 | __attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) |
| 1853 | { |
| 1854 | int32_t result; |
| 1855 | |
| 1856 | __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); |
| 1857 | return(result); |
| 1858 | } |
| 1859 | |
| 1860 | #if 0 |
| 1861 | #define __PKHBT(ARG1,ARG2,ARG3) \ |
| 1862 | ({ \ |
| 1863 | uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ |
| 1864 | __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ |
| 1865 | __RES; \ |
| 1866 | }) |
| 1867 | |
| 1868 | #define __PKHTB(ARG1,ARG2,ARG3) \ |
| 1869 | ({ \ |
| 1870 | uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ |
| 1871 | if (ARG3 == 0) \ |
| 1872 | __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ |
| 1873 | else \ |
| 1874 | __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ |
| 1875 | __RES; \ |
| 1876 | }) |
| 1877 | #endif |
| 1878 | |
| 1879 | #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ |
| 1880 | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) |
| 1881 | |
| 1882 | #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ |
| 1883 | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) |
| 1884 | |
| 1885 | __attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) |
| 1886 | { |
| 1887 | int32_t result; |
| 1888 | |
| 1889 | __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); |
| 1890 | return(result); |
| 1891 | } |
| 1892 | |
| 1893 | #endif /* (__ARM_FEATURE_DSP == 1) */ |
| 1894 | /*@} end of group CMSIS_SIMD_intrinsics */ |
| 1895 | |
| 1896 | |
| 1897 | #pragma GCC diagnostic pop |
| 1898 | |
| 1899 | #endif /* __CMSIS_GCC_H */ |