Harald Welte | cab5d15 | 2019-05-16 13:31:16 +0200 | [diff] [blame] | 1 | /* Simulated CCID card slot. This is used in absence of a real hardware back-end |
| 2 | * in order to test the CCID firmware codebase in a virtual environment */ |
| 3 | |
Harald Welte | 505d441 | 2019-05-16 17:26:09 +0200 | [diff] [blame] | 4 | #include <osmocom/core/msgb.h> |
| 5 | #include <osmocom/core/timer.h> |
Harald Welte | 29ae5d4 | 2019-05-16 17:40:29 +0200 | [diff] [blame] | 6 | #include <osmocom/core/logging.h> |
Harald Welte | 505d441 | 2019-05-16 17:26:09 +0200 | [diff] [blame] | 7 | |
Harald Welte | cab5d15 | 2019-05-16 13:31:16 +0200 | [diff] [blame] | 8 | #include "ccid_device.h" |
| 9 | |
Harald Welte | 505d441 | 2019-05-16 17:26:09 +0200 | [diff] [blame] | 10 | struct slotsim_slot { |
| 11 | struct osmo_timer_list pwron_timer; |
| 12 | struct osmo_timer_list xfr_timer; |
| 13 | /* bSeq of the operation currently in progress */ |
| 14 | uint8_t seq; |
| 15 | }; |
| 16 | |
| 17 | struct slotsim_instance { |
| 18 | struct slotsim_slot slot[NR_SLOTS]; |
| 19 | }; |
| 20 | |
| 21 | static struct slotsim_instance g_si; |
| 22 | |
| 23 | struct slotsim_slot *ccid_slot2slotsim_slot(struct ccid_slot *cs) |
| 24 | { |
| 25 | OSMO_ASSERT(cs->slot_nr < ARRAY_SIZE(g_si.slot)); |
| 26 | return &g_si.slot[cs->slot_nr]; |
| 27 | } |
| 28 | |
Harald Welte | 29ae5d4 | 2019-05-16 17:40:29 +0200 | [diff] [blame] | 29 | static const uint8_t sysmousim_sjs1_atr[] = { |
| 30 | 0x3B, 0x9F, 0x96, 0x80, 0x1F, 0xC7, 0x80, 0x31, |
| 31 | 0xA0, 0x73, 0xBE, 0x21, 0x13, 0x67, 0x43, 0x20, |
| 32 | 0x07, 0x18, 0x00, 0x00, 0x01, 0xA5 }; |
| 33 | |
Harald Welte | cab5d15 | 2019-05-16 13:31:16 +0200 | [diff] [blame] | 34 | static const struct ccid_pars_decoded slotsim_def_pars = { |
| 35 | .fi = 0, |
| 36 | .di = 0, |
| 37 | .clock_stop = CCID_CLOCK_STOP_NOTALLOWED, |
| 38 | .inverse_convention = false, |
| 39 | .t0 = { |
| 40 | .guard_time_etu = 0, |
| 41 | .waiting_integer = 0, |
| 42 | }, |
| 43 | /* FIXME: T=1 */ |
| 44 | }; |
| 45 | |
| 46 | static void slotsim_pre_proc_cb(struct ccid_slot *cs, struct msgb *msg) |
| 47 | { |
| 48 | /* do nothing; real hardware would update the slot related state here */ |
| 49 | } |
| 50 | |
Harald Welte | 505d441 | 2019-05-16 17:26:09 +0200 | [diff] [blame] | 51 | static void slotsim_icc_power_on_async(struct ccid_slot *cs, struct msgb *msg, |
| 52 | const struct ccid_pc_to_rdr_icc_power_on *ipo) |
| 53 | { |
| 54 | struct slotsim_slot *ss = ccid_slot2slotsim_slot(cs); |
| 55 | |
| 56 | ss->seq = ipo->hdr.bSeq; |
Harald Welte | 29ae5d4 | 2019-05-16 17:40:29 +0200 | [diff] [blame] | 57 | LOGPCS(cs, LOGL_DEBUG, "scheduling pwron_timer\n"); |
Harald Welte | 505d441 | 2019-05-16 17:26:09 +0200 | [diff] [blame] | 58 | osmo_timer_schedule(&ss->pwron_timer, 1, 0); |
| 59 | msgb_free(msg); |
| 60 | /* continues in timer call-back below */ |
| 61 | } |
| 62 | static void slotsim_pwron_timer_cb(void *data) |
| 63 | { |
| 64 | struct ccid_slot *cs = data; |
| 65 | struct slotsim_slot *ss = ccid_slot2slotsim_slot(cs); |
| 66 | struct msgb *resp; |
| 67 | |
Harald Welte | 29ae5d4 | 2019-05-16 17:40:29 +0200 | [diff] [blame] | 68 | LOGPCS(cs, LOGL_DEBUG, "%s\n", __func__); |
| 69 | |
| 70 | resp = ccid_gen_data_block(cs, ss->seq, CCID_CMD_STATUS_OK, 0, |
| 71 | sysmousim_sjs1_atr, sizeof(sysmousim_sjs1_atr)); |
Harald Welte | 505d441 | 2019-05-16 17:26:09 +0200 | [diff] [blame] | 72 | ccid_slot_send_unbusy(cs, resp); |
| 73 | } |
| 74 | |
| 75 | static void slotsim_xfr_block_async(struct ccid_slot *cs, struct msgb *msg, |
| 76 | const struct ccid_pc_to_rdr_xfr_block *xfb) |
| 77 | { |
| 78 | struct slotsim_slot *ss = ccid_slot2slotsim_slot(cs); |
| 79 | |
| 80 | ss->seq = xfb->hdr.bSeq; |
Harald Welte | 29ae5d4 | 2019-05-16 17:40:29 +0200 | [diff] [blame] | 81 | LOGPCS(cs, LOGL_DEBUG, "scheduling xfr_timer\n"); |
Harald Welte | 505d441 | 2019-05-16 17:26:09 +0200 | [diff] [blame] | 82 | osmo_timer_schedule(&ss->xfr_timer, 0, 50000); |
| 83 | msgb_free(msg); |
| 84 | /* continues in timer call-back below */ |
| 85 | } |
| 86 | static void slotsim_xfr_timer_cb(void *data) |
| 87 | { |
| 88 | struct ccid_slot *cs = data; |
| 89 | struct slotsim_slot *ss = ccid_slot2slotsim_slot(cs); |
| 90 | struct msgb *resp; |
| 91 | |
Harald Welte | 29ae5d4 | 2019-05-16 17:40:29 +0200 | [diff] [blame] | 92 | LOGPCS(cs, LOGL_DEBUG, "%s\n", __func__); |
| 93 | |
Harald Welte | 505d441 | 2019-05-16 17:26:09 +0200 | [diff] [blame] | 94 | resp = ccid_gen_data_block(cs, ss->seq, CCID_CMD_STATUS_OK, 0, NULL, 0); |
| 95 | ccid_slot_send_unbusy(cs, resp); |
| 96 | } |
| 97 | |
| 98 | |
Harald Welte | cab5d15 | 2019-05-16 13:31:16 +0200 | [diff] [blame] | 99 | static void slotsim_set_power(struct ccid_slot *cs, bool enable) |
| 100 | { |
| 101 | if (enable) { |
| 102 | cs->icc_powered = true; |
| 103 | /* FIXME: What to do about ATR? */ |
| 104 | } else { |
| 105 | cs->icc_powered = false; |
| 106 | } |
| 107 | } |
| 108 | |
| 109 | static void slotsim_set_clock(struct ccid_slot *cs, enum ccid_clock_command cmd) |
| 110 | { |
| 111 | /* FIXME */ |
| 112 | switch (cmd) { |
| 113 | case CCID_CLOCK_CMD_STOP: |
| 114 | break; |
| 115 | case CCID_CLOCK_CMD_RESTART: |
| 116 | break; |
| 117 | default: |
| 118 | OSMO_ASSERT(0); |
| 119 | } |
| 120 | } |
| 121 | |
| 122 | static int slotsim_set_params(struct ccid_slot *cs, enum ccid_protocol_num proto, |
| 123 | const struct ccid_pars_decoded *pars_dec) |
| 124 | { |
| 125 | /* we always acknowledge all parameters */ |
| 126 | return 0; |
| 127 | } |
| 128 | |
| 129 | static int slotsim_set_rate_and_clock(struct ccid_slot *cs, uint32_t freq_hz, uint32_t rate_bps) |
| 130 | { |
| 131 | /* we always acknowledge all rates/clocks */ |
| 132 | return 0; |
| 133 | } |
| 134 | |
Harald Welte | 505d441 | 2019-05-16 17:26:09 +0200 | [diff] [blame] | 135 | |
Harald Welte | cab5d15 | 2019-05-16 13:31:16 +0200 | [diff] [blame] | 136 | static int slotsim_init(struct ccid_slot *cs) |
| 137 | { |
Harald Welte | 505d441 | 2019-05-16 17:26:09 +0200 | [diff] [blame] | 138 | struct slotsim_slot *ss = ccid_slot2slotsim_slot(cs); |
Harald Welte | 29ae5d4 | 2019-05-16 17:40:29 +0200 | [diff] [blame] | 139 | |
| 140 | LOGPCS(cs, LOGL_DEBUG, "%s\n", __func__); |
| 141 | cs->icc_present = true; |
| 142 | cs->icc_powered = true; |
Harald Welte | 505d441 | 2019-05-16 17:26:09 +0200 | [diff] [blame] | 143 | osmo_timer_setup(&ss->pwron_timer, slotsim_pwron_timer_cb, cs); |
| 144 | osmo_timer_setup(&ss->xfr_timer, slotsim_xfr_timer_cb, cs); |
Harald Welte | cab5d15 | 2019-05-16 13:31:16 +0200 | [diff] [blame] | 145 | cs->default_pars = &slotsim_def_pars; |
| 146 | return 0; |
| 147 | } |
| 148 | |
| 149 | const struct ccid_slot_ops slotsim_slot_ops = { |
| 150 | .init = slotsim_init, |
| 151 | .pre_proc_cb = slotsim_pre_proc_cb, |
Harald Welte | 505d441 | 2019-05-16 17:26:09 +0200 | [diff] [blame] | 152 | .icc_power_on_async = slotsim_icc_power_on_async, |
| 153 | .xfr_block_async = slotsim_xfr_block_async, |
Harald Welte | cab5d15 | 2019-05-16 13:31:16 +0200 | [diff] [blame] | 154 | .set_power = slotsim_set_power, |
| 155 | .set_clock = slotsim_set_clock, |
| 156 | .set_params = slotsim_set_params, |
| 157 | .set_rate_and_clock = slotsim_set_rate_and_clock, |
| 158 | }; |