Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief SAM ADC |
| 5 | * |
| 6 | * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifdef _SAME54_ADC_COMPONENT_ |
| 35 | #ifndef _HRI_ADC_E54_H_INCLUDED_ |
| 36 | #define _HRI_ADC_E54_H_INCLUDED_ |
| 37 | |
| 38 | #ifdef __cplusplus |
| 39 | extern "C" { |
| 40 | #endif |
| 41 | |
| 42 | #include <stdbool.h> |
| 43 | #include <hal_atomic.h> |
| 44 | |
| 45 | #if defined(ENABLE_ADC_CRITICAL_SECTIONS) |
| 46 | #define ADC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() |
| 47 | #define ADC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() |
| 48 | #else |
| 49 | #define ADC_CRITICAL_SECTION_ENTER() |
| 50 | #define ADC_CRITICAL_SECTION_LEAVE() |
| 51 | #endif |
| 52 | |
| 53 | typedef uint16_t hri_adc_calib_reg_t; |
| 54 | typedef uint16_t hri_adc_ctrla_reg_t; |
| 55 | typedef uint16_t hri_adc_ctrlb_reg_t; |
| 56 | typedef uint16_t hri_adc_gaincorr_reg_t; |
| 57 | typedef uint16_t hri_adc_inputctrl_reg_t; |
| 58 | typedef uint16_t hri_adc_offsetcorr_reg_t; |
| 59 | typedef uint16_t hri_adc_ress_reg_t; |
| 60 | typedef uint16_t hri_adc_result_reg_t; |
| 61 | typedef uint16_t hri_adc_winlt_reg_t; |
| 62 | typedef uint16_t hri_adc_winut_reg_t; |
| 63 | typedef uint32_t hri_adc_dseqctrl_reg_t; |
| 64 | typedef uint32_t hri_adc_dseqdata_reg_t; |
| 65 | typedef uint32_t hri_adc_dseqstat_reg_t; |
| 66 | typedef uint32_t hri_adc_syncbusy_reg_t; |
| 67 | typedef uint8_t hri_adc_avgctrl_reg_t; |
| 68 | typedef uint8_t hri_adc_dbgctrl_reg_t; |
| 69 | typedef uint8_t hri_adc_evctrl_reg_t; |
| 70 | typedef uint8_t hri_adc_intenset_reg_t; |
| 71 | typedef uint8_t hri_adc_intflag_reg_t; |
| 72 | typedef uint8_t hri_adc_refctrl_reg_t; |
| 73 | typedef uint8_t hri_adc_sampctrl_reg_t; |
| 74 | typedef uint8_t hri_adc_status_reg_t; |
| 75 | typedef uint8_t hri_adc_swtrig_reg_t; |
| 76 | |
| 77 | static inline void hri_adc_wait_for_sync(const void *const hw, hri_adc_syncbusy_reg_t reg) |
| 78 | { |
| 79 | while (((Adc *)hw)->SYNCBUSY.reg & reg) { |
| 80 | }; |
| 81 | } |
| 82 | |
| 83 | static inline bool hri_adc_is_syncing(const void *const hw, hri_adc_syncbusy_reg_t reg) |
| 84 | { |
| 85 | return ((Adc *)hw)->SYNCBUSY.reg & reg; |
| 86 | } |
| 87 | |
| 88 | static inline bool hri_adc_get_INTFLAG_RESRDY_bit(const void *const hw) |
| 89 | { |
| 90 | return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; |
| 91 | } |
| 92 | |
| 93 | static inline void hri_adc_clear_INTFLAG_RESRDY_bit(const void *const hw) |
| 94 | { |
| 95 | ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; |
| 96 | } |
| 97 | |
| 98 | static inline bool hri_adc_get_INTFLAG_OVERRUN_bit(const void *const hw) |
| 99 | { |
| 100 | return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; |
| 101 | } |
| 102 | |
| 103 | static inline void hri_adc_clear_INTFLAG_OVERRUN_bit(const void *const hw) |
| 104 | { |
| 105 | ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; |
| 106 | } |
| 107 | |
| 108 | static inline bool hri_adc_get_INTFLAG_WINMON_bit(const void *const hw) |
| 109 | { |
| 110 | return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; |
| 111 | } |
| 112 | |
| 113 | static inline void hri_adc_clear_INTFLAG_WINMON_bit(const void *const hw) |
| 114 | { |
| 115 | ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; |
| 116 | } |
| 117 | |
| 118 | static inline bool hri_adc_get_interrupt_RESRDY_bit(const void *const hw) |
| 119 | { |
| 120 | return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; |
| 121 | } |
| 122 | |
| 123 | static inline void hri_adc_clear_interrupt_RESRDY_bit(const void *const hw) |
| 124 | { |
| 125 | ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; |
| 126 | } |
| 127 | |
| 128 | static inline bool hri_adc_get_interrupt_OVERRUN_bit(const void *const hw) |
| 129 | { |
| 130 | return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; |
| 131 | } |
| 132 | |
| 133 | static inline void hri_adc_clear_interrupt_OVERRUN_bit(const void *const hw) |
| 134 | { |
| 135 | ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; |
| 136 | } |
| 137 | |
| 138 | static inline bool hri_adc_get_interrupt_WINMON_bit(const void *const hw) |
| 139 | { |
| 140 | return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; |
| 141 | } |
| 142 | |
| 143 | static inline void hri_adc_clear_interrupt_WINMON_bit(const void *const hw) |
| 144 | { |
| 145 | ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; |
| 146 | } |
| 147 | |
| 148 | static inline hri_adc_intflag_reg_t hri_adc_get_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) |
| 149 | { |
| 150 | uint8_t tmp; |
| 151 | tmp = ((Adc *)hw)->INTFLAG.reg; |
| 152 | tmp &= mask; |
| 153 | return tmp; |
| 154 | } |
| 155 | |
| 156 | static inline hri_adc_intflag_reg_t hri_adc_read_INTFLAG_reg(const void *const hw) |
| 157 | { |
| 158 | return ((Adc *)hw)->INTFLAG.reg; |
| 159 | } |
| 160 | |
| 161 | static inline void hri_adc_clear_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) |
| 162 | { |
| 163 | ((Adc *)hw)->INTFLAG.reg = mask; |
| 164 | } |
| 165 | |
| 166 | static inline void hri_adc_set_INTEN_RESRDY_bit(const void *const hw) |
| 167 | { |
| 168 | ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; |
| 169 | } |
| 170 | |
| 171 | static inline bool hri_adc_get_INTEN_RESRDY_bit(const void *const hw) |
| 172 | { |
| 173 | return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_RESRDY) >> ADC_INTENSET_RESRDY_Pos; |
| 174 | } |
| 175 | |
| 176 | static inline void hri_adc_write_INTEN_RESRDY_bit(const void *const hw, bool value) |
| 177 | { |
| 178 | if (value == 0x0) { |
| 179 | ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; |
| 180 | } else { |
| 181 | ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; |
| 182 | } |
| 183 | } |
| 184 | |
| 185 | static inline void hri_adc_clear_INTEN_RESRDY_bit(const void *const hw) |
| 186 | { |
| 187 | ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; |
| 188 | } |
| 189 | |
| 190 | static inline void hri_adc_set_INTEN_OVERRUN_bit(const void *const hw) |
| 191 | { |
| 192 | ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; |
| 193 | } |
| 194 | |
| 195 | static inline bool hri_adc_get_INTEN_OVERRUN_bit(const void *const hw) |
| 196 | { |
| 197 | return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_OVERRUN) >> ADC_INTENSET_OVERRUN_Pos; |
| 198 | } |
| 199 | |
| 200 | static inline void hri_adc_write_INTEN_OVERRUN_bit(const void *const hw, bool value) |
| 201 | { |
| 202 | if (value == 0x0) { |
| 203 | ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; |
| 204 | } else { |
| 205 | ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; |
| 206 | } |
| 207 | } |
| 208 | |
| 209 | static inline void hri_adc_clear_INTEN_OVERRUN_bit(const void *const hw) |
| 210 | { |
| 211 | ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; |
| 212 | } |
| 213 | |
| 214 | static inline void hri_adc_set_INTEN_WINMON_bit(const void *const hw) |
| 215 | { |
| 216 | ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; |
| 217 | } |
| 218 | |
| 219 | static inline bool hri_adc_get_INTEN_WINMON_bit(const void *const hw) |
| 220 | { |
| 221 | return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_WINMON) >> ADC_INTENSET_WINMON_Pos; |
| 222 | } |
| 223 | |
| 224 | static inline void hri_adc_write_INTEN_WINMON_bit(const void *const hw, bool value) |
| 225 | { |
| 226 | if (value == 0x0) { |
| 227 | ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; |
| 228 | } else { |
| 229 | ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; |
| 230 | } |
| 231 | } |
| 232 | |
| 233 | static inline void hri_adc_clear_INTEN_WINMON_bit(const void *const hw) |
| 234 | { |
| 235 | ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; |
| 236 | } |
| 237 | |
| 238 | static inline void hri_adc_set_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) |
| 239 | { |
| 240 | ((Adc *)hw)->INTENSET.reg = mask; |
| 241 | } |
| 242 | |
| 243 | static inline hri_adc_intenset_reg_t hri_adc_get_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) |
| 244 | { |
| 245 | uint8_t tmp; |
| 246 | tmp = ((Adc *)hw)->INTENSET.reg; |
| 247 | tmp &= mask; |
| 248 | return tmp; |
| 249 | } |
| 250 | |
| 251 | static inline hri_adc_intenset_reg_t hri_adc_read_INTEN_reg(const void *const hw) |
| 252 | { |
| 253 | return ((Adc *)hw)->INTENSET.reg; |
| 254 | } |
| 255 | |
| 256 | static inline void hri_adc_write_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t data) |
| 257 | { |
| 258 | ((Adc *)hw)->INTENSET.reg = data; |
| 259 | ((Adc *)hw)->INTENCLR.reg = ~data; |
| 260 | } |
| 261 | |
| 262 | static inline void hri_adc_clear_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) |
| 263 | { |
| 264 | ((Adc *)hw)->INTENCLR.reg = mask; |
| 265 | } |
| 266 | |
| 267 | static inline bool hri_adc_get_STATUS_ADCBUSY_bit(const void *const hw) |
| 268 | { |
| 269 | return (((Adc *)hw)->STATUS.reg & ADC_STATUS_ADCBUSY) >> ADC_STATUS_ADCBUSY_Pos; |
| 270 | } |
| 271 | |
| 272 | static inline hri_adc_status_reg_t hri_adc_get_STATUS_WCC_bf(const void *const hw, hri_adc_status_reg_t mask) |
| 273 | { |
| 274 | return (((Adc *)hw)->STATUS.reg & ADC_STATUS_WCC(mask)) >> ADC_STATUS_WCC_Pos; |
| 275 | } |
| 276 | |
| 277 | static inline hri_adc_status_reg_t hri_adc_read_STATUS_WCC_bf(const void *const hw) |
| 278 | { |
| 279 | return (((Adc *)hw)->STATUS.reg & ADC_STATUS_WCC_Msk) >> ADC_STATUS_WCC_Pos; |
| 280 | } |
| 281 | |
| 282 | static inline hri_adc_status_reg_t hri_adc_get_STATUS_reg(const void *const hw, hri_adc_status_reg_t mask) |
| 283 | { |
| 284 | uint8_t tmp; |
| 285 | tmp = ((Adc *)hw)->STATUS.reg; |
| 286 | tmp &= mask; |
| 287 | return tmp; |
| 288 | } |
| 289 | |
| 290 | static inline hri_adc_status_reg_t hri_adc_read_STATUS_reg(const void *const hw) |
| 291 | { |
| 292 | return ((Adc *)hw)->STATUS.reg; |
| 293 | } |
| 294 | |
| 295 | static inline bool hri_adc_get_SYNCBUSY_SWRST_bit(const void *const hw) |
| 296 | { |
| 297 | return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWRST) >> ADC_SYNCBUSY_SWRST_Pos; |
| 298 | } |
| 299 | |
| 300 | static inline bool hri_adc_get_SYNCBUSY_ENABLE_bit(const void *const hw) |
| 301 | { |
| 302 | return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_ENABLE) >> ADC_SYNCBUSY_ENABLE_Pos; |
| 303 | } |
| 304 | |
| 305 | static inline bool hri_adc_get_SYNCBUSY_INPUTCTRL_bit(const void *const hw) |
| 306 | { |
| 307 | return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_INPUTCTRL) >> ADC_SYNCBUSY_INPUTCTRL_Pos; |
| 308 | } |
| 309 | |
| 310 | static inline bool hri_adc_get_SYNCBUSY_CTRLB_bit(const void *const hw) |
| 311 | { |
| 312 | return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_CTRLB) >> ADC_SYNCBUSY_CTRLB_Pos; |
| 313 | } |
| 314 | |
| 315 | static inline bool hri_adc_get_SYNCBUSY_REFCTRL_bit(const void *const hw) |
| 316 | { |
| 317 | return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_REFCTRL) >> ADC_SYNCBUSY_REFCTRL_Pos; |
| 318 | } |
| 319 | |
| 320 | static inline bool hri_adc_get_SYNCBUSY_AVGCTRL_bit(const void *const hw) |
| 321 | { |
| 322 | return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_AVGCTRL) >> ADC_SYNCBUSY_AVGCTRL_Pos; |
| 323 | } |
| 324 | |
| 325 | static inline bool hri_adc_get_SYNCBUSY_SAMPCTRL_bit(const void *const hw) |
| 326 | { |
| 327 | return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SAMPCTRL) >> ADC_SYNCBUSY_SAMPCTRL_Pos; |
| 328 | } |
| 329 | |
| 330 | static inline bool hri_adc_get_SYNCBUSY_WINLT_bit(const void *const hw) |
| 331 | { |
| 332 | return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINLT) >> ADC_SYNCBUSY_WINLT_Pos; |
| 333 | } |
| 334 | |
| 335 | static inline bool hri_adc_get_SYNCBUSY_WINUT_bit(const void *const hw) |
| 336 | { |
| 337 | return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINUT) >> ADC_SYNCBUSY_WINUT_Pos; |
| 338 | } |
| 339 | |
| 340 | static inline bool hri_adc_get_SYNCBUSY_GAINCORR_bit(const void *const hw) |
| 341 | { |
| 342 | return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_GAINCORR) >> ADC_SYNCBUSY_GAINCORR_Pos; |
| 343 | } |
| 344 | |
| 345 | static inline bool hri_adc_get_SYNCBUSY_OFFSETCORR_bit(const void *const hw) |
| 346 | { |
| 347 | return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_OFFSETCORR) >> ADC_SYNCBUSY_OFFSETCORR_Pos; |
| 348 | } |
| 349 | |
| 350 | static inline bool hri_adc_get_SYNCBUSY_SWTRIG_bit(const void *const hw) |
| 351 | { |
| 352 | return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWTRIG) >> ADC_SYNCBUSY_SWTRIG_Pos; |
| 353 | } |
| 354 | |
| 355 | static inline hri_adc_syncbusy_reg_t hri_adc_get_SYNCBUSY_reg(const void *const hw, hri_adc_syncbusy_reg_t mask) |
| 356 | { |
| 357 | uint32_t tmp; |
| 358 | tmp = ((Adc *)hw)->SYNCBUSY.reg; |
| 359 | tmp &= mask; |
| 360 | return tmp; |
| 361 | } |
| 362 | |
| 363 | static inline hri_adc_syncbusy_reg_t hri_adc_read_SYNCBUSY_reg(const void *const hw) |
| 364 | { |
| 365 | return ((Adc *)hw)->SYNCBUSY.reg; |
| 366 | } |
| 367 | |
| 368 | static inline bool hri_adc_get_DSEQSTAT_INPUTCTRL_bit(const void *const hw) |
| 369 | { |
| 370 | hri_adc_wait_for_sync(hw, |
| 371 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 372 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 373 | | ADC_SYNCBUSY_OFFSETCORR); |
| 374 | return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_INPUTCTRL) >> ADC_DSEQSTAT_INPUTCTRL_Pos; |
| 375 | } |
| 376 | |
| 377 | static inline bool hri_adc_get_DSEQSTAT_CTRLB_bit(const void *const hw) |
| 378 | { |
| 379 | hri_adc_wait_for_sync(hw, |
| 380 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 381 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 382 | | ADC_SYNCBUSY_OFFSETCORR); |
| 383 | return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_CTRLB) >> ADC_DSEQSTAT_CTRLB_Pos; |
| 384 | } |
| 385 | |
| 386 | static inline bool hri_adc_get_DSEQSTAT_REFCTRL_bit(const void *const hw) |
| 387 | { |
| 388 | hri_adc_wait_for_sync(hw, |
| 389 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 390 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 391 | | ADC_SYNCBUSY_OFFSETCORR); |
| 392 | return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_REFCTRL) >> ADC_DSEQSTAT_REFCTRL_Pos; |
| 393 | } |
| 394 | |
| 395 | static inline bool hri_adc_get_DSEQSTAT_AVGCTRL_bit(const void *const hw) |
| 396 | { |
| 397 | hri_adc_wait_for_sync(hw, |
| 398 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 399 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 400 | | ADC_SYNCBUSY_OFFSETCORR); |
| 401 | return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_AVGCTRL) >> ADC_DSEQSTAT_AVGCTRL_Pos; |
| 402 | } |
| 403 | |
| 404 | static inline bool hri_adc_get_DSEQSTAT_SAMPCTRL_bit(const void *const hw) |
| 405 | { |
| 406 | hri_adc_wait_for_sync(hw, |
| 407 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 408 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 409 | | ADC_SYNCBUSY_OFFSETCORR); |
| 410 | return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_SAMPCTRL) >> ADC_DSEQSTAT_SAMPCTRL_Pos; |
| 411 | } |
| 412 | |
| 413 | static inline bool hri_adc_get_DSEQSTAT_WINLT_bit(const void *const hw) |
| 414 | { |
| 415 | hri_adc_wait_for_sync(hw, |
| 416 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 417 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 418 | | ADC_SYNCBUSY_OFFSETCORR); |
| 419 | return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_WINLT) >> ADC_DSEQSTAT_WINLT_Pos; |
| 420 | } |
| 421 | |
| 422 | static inline bool hri_adc_get_DSEQSTAT_WINUT_bit(const void *const hw) |
| 423 | { |
| 424 | hri_adc_wait_for_sync(hw, |
| 425 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 426 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 427 | | ADC_SYNCBUSY_OFFSETCORR); |
| 428 | return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_WINUT) >> ADC_DSEQSTAT_WINUT_Pos; |
| 429 | } |
| 430 | |
| 431 | static inline bool hri_adc_get_DSEQSTAT_GAINCORR_bit(const void *const hw) |
| 432 | { |
| 433 | hri_adc_wait_for_sync(hw, |
| 434 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 435 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 436 | | ADC_SYNCBUSY_OFFSETCORR); |
| 437 | return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_GAINCORR) >> ADC_DSEQSTAT_GAINCORR_Pos; |
| 438 | } |
| 439 | |
| 440 | static inline bool hri_adc_get_DSEQSTAT_OFFSETCORR_bit(const void *const hw) |
| 441 | { |
| 442 | hri_adc_wait_for_sync(hw, |
| 443 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 444 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 445 | | ADC_SYNCBUSY_OFFSETCORR); |
| 446 | return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_OFFSETCORR) >> ADC_DSEQSTAT_OFFSETCORR_Pos; |
| 447 | } |
| 448 | |
| 449 | static inline bool hri_adc_get_DSEQSTAT_BUSY_bit(const void *const hw) |
| 450 | { |
| 451 | return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_BUSY) >> ADC_DSEQSTAT_BUSY_Pos; |
| 452 | } |
| 453 | |
| 454 | static inline hri_adc_dseqstat_reg_t hri_adc_get_DSEQSTAT_reg(const void *const hw, hri_adc_dseqstat_reg_t mask) |
| 455 | { |
| 456 | uint32_t tmp; |
| 457 | hri_adc_wait_for_sync(hw, |
| 458 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 459 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 460 | | ADC_SYNCBUSY_OFFSETCORR); |
| 461 | tmp = ((Adc *)hw)->DSEQSTAT.reg; |
| 462 | tmp &= mask; |
| 463 | return tmp; |
| 464 | } |
| 465 | |
| 466 | static inline hri_adc_dseqstat_reg_t hri_adc_read_DSEQSTAT_reg(const void *const hw) |
| 467 | { |
| 468 | hri_adc_wait_for_sync(hw, |
| 469 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 470 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 471 | | ADC_SYNCBUSY_OFFSETCORR); |
| 472 | return ((Adc *)hw)->DSEQSTAT.reg; |
| 473 | } |
| 474 | |
| 475 | static inline hri_adc_result_reg_t hri_adc_get_RESULT_RESULT_bf(const void *const hw, hri_adc_result_reg_t mask) |
| 476 | { |
| 477 | return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT(mask)) >> ADC_RESULT_RESULT_Pos; |
| 478 | } |
| 479 | |
| 480 | static inline hri_adc_result_reg_t hri_adc_read_RESULT_RESULT_bf(const void *const hw) |
| 481 | { |
| 482 | return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT_Msk) >> ADC_RESULT_RESULT_Pos; |
| 483 | } |
| 484 | |
| 485 | static inline hri_adc_result_reg_t hri_adc_get_RESULT_reg(const void *const hw, hri_adc_result_reg_t mask) |
| 486 | { |
| 487 | uint16_t tmp; |
| 488 | tmp = ((Adc *)hw)->RESULT.reg; |
| 489 | tmp &= mask; |
| 490 | return tmp; |
| 491 | } |
| 492 | |
| 493 | static inline hri_adc_result_reg_t hri_adc_read_RESULT_reg(const void *const hw) |
| 494 | { |
| 495 | return ((Adc *)hw)->RESULT.reg; |
| 496 | } |
| 497 | |
| 498 | static inline hri_adc_ress_reg_t hri_adc_get_RESS_RESS_bf(const void *const hw, hri_adc_ress_reg_t mask) |
| 499 | { |
| 500 | return (((Adc *)hw)->RESS.reg & ADC_RESS_RESS(mask)) >> ADC_RESS_RESS_Pos; |
| 501 | } |
| 502 | |
| 503 | static inline hri_adc_ress_reg_t hri_adc_read_RESS_RESS_bf(const void *const hw) |
| 504 | { |
| 505 | return (((Adc *)hw)->RESS.reg & ADC_RESS_RESS_Msk) >> ADC_RESS_RESS_Pos; |
| 506 | } |
| 507 | |
| 508 | static inline hri_adc_ress_reg_t hri_adc_get_RESS_reg(const void *const hw, hri_adc_ress_reg_t mask) |
| 509 | { |
| 510 | uint16_t tmp; |
| 511 | tmp = ((Adc *)hw)->RESS.reg; |
| 512 | tmp &= mask; |
| 513 | return tmp; |
| 514 | } |
| 515 | |
| 516 | static inline hri_adc_ress_reg_t hri_adc_read_RESS_reg(const void *const hw) |
| 517 | { |
| 518 | return ((Adc *)hw)->RESS.reg; |
| 519 | } |
| 520 | |
| 521 | static inline void hri_adc_set_CTRLA_SWRST_bit(const void *const hw) |
| 522 | { |
| 523 | ADC_CRITICAL_SECTION_ENTER(); |
| 524 | ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SWRST; |
| 525 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); |
| 526 | ADC_CRITICAL_SECTION_LEAVE(); |
| 527 | } |
| 528 | |
| 529 | static inline bool hri_adc_get_CTRLA_SWRST_bit(const void *const hw) |
| 530 | { |
| 531 | uint16_t tmp; |
| 532 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); |
| 533 | tmp = ((Adc *)hw)->CTRLA.reg; |
| 534 | tmp = (tmp & ADC_CTRLA_SWRST) >> ADC_CTRLA_SWRST_Pos; |
| 535 | return (bool)tmp; |
| 536 | } |
| 537 | |
| 538 | static inline void hri_adc_set_CTRLA_ENABLE_bit(const void *const hw) |
| 539 | { |
| 540 | ADC_CRITICAL_SECTION_ENTER(); |
| 541 | ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ENABLE; |
| 542 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); |
| 543 | ADC_CRITICAL_SECTION_LEAVE(); |
| 544 | } |
| 545 | |
| 546 | static inline bool hri_adc_get_CTRLA_ENABLE_bit(const void *const hw) |
| 547 | { |
| 548 | uint16_t tmp; |
| 549 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); |
| 550 | tmp = ((Adc *)hw)->CTRLA.reg; |
| 551 | tmp = (tmp & ADC_CTRLA_ENABLE) >> ADC_CTRLA_ENABLE_Pos; |
| 552 | return (bool)tmp; |
| 553 | } |
| 554 | |
| 555 | static inline void hri_adc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) |
| 556 | { |
| 557 | uint16_t tmp; |
| 558 | ADC_CRITICAL_SECTION_ENTER(); |
| 559 | tmp = ((Adc *)hw)->CTRLA.reg; |
| 560 | tmp &= ~ADC_CTRLA_ENABLE; |
| 561 | tmp |= value << ADC_CTRLA_ENABLE_Pos; |
| 562 | ((Adc *)hw)->CTRLA.reg = tmp; |
| 563 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); |
| 564 | ADC_CRITICAL_SECTION_LEAVE(); |
| 565 | } |
| 566 | |
| 567 | static inline void hri_adc_clear_CTRLA_ENABLE_bit(const void *const hw) |
| 568 | { |
| 569 | ADC_CRITICAL_SECTION_ENTER(); |
| 570 | ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ENABLE; |
| 571 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); |
| 572 | ADC_CRITICAL_SECTION_LEAVE(); |
| 573 | } |
| 574 | |
| 575 | static inline void hri_adc_toggle_CTRLA_ENABLE_bit(const void *const hw) |
| 576 | { |
| 577 | ADC_CRITICAL_SECTION_ENTER(); |
| 578 | ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ENABLE; |
| 579 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); |
| 580 | ADC_CRITICAL_SECTION_LEAVE(); |
| 581 | } |
| 582 | |
| 583 | static inline void hri_adc_set_CTRLA_SLAVEEN_bit(const void *const hw) |
| 584 | { |
| 585 | ADC_CRITICAL_SECTION_ENTER(); |
| 586 | ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SLAVEEN; |
| 587 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 588 | ADC_CRITICAL_SECTION_LEAVE(); |
| 589 | } |
| 590 | |
| 591 | static inline bool hri_adc_get_CTRLA_SLAVEEN_bit(const void *const hw) |
| 592 | { |
| 593 | uint16_t tmp; |
| 594 | tmp = ((Adc *)hw)->CTRLA.reg; |
| 595 | tmp = (tmp & ADC_CTRLA_SLAVEEN) >> ADC_CTRLA_SLAVEEN_Pos; |
| 596 | return (bool)tmp; |
| 597 | } |
| 598 | |
| 599 | static inline void hri_adc_write_CTRLA_SLAVEEN_bit(const void *const hw, bool value) |
| 600 | { |
| 601 | uint16_t tmp; |
| 602 | ADC_CRITICAL_SECTION_ENTER(); |
| 603 | tmp = ((Adc *)hw)->CTRLA.reg; |
| 604 | tmp &= ~ADC_CTRLA_SLAVEEN; |
| 605 | tmp |= value << ADC_CTRLA_SLAVEEN_Pos; |
| 606 | ((Adc *)hw)->CTRLA.reg = tmp; |
| 607 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 608 | ADC_CRITICAL_SECTION_LEAVE(); |
| 609 | } |
| 610 | |
| 611 | static inline void hri_adc_clear_CTRLA_SLAVEEN_bit(const void *const hw) |
| 612 | { |
| 613 | ADC_CRITICAL_SECTION_ENTER(); |
| 614 | ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_SLAVEEN; |
| 615 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 616 | ADC_CRITICAL_SECTION_LEAVE(); |
| 617 | } |
| 618 | |
| 619 | static inline void hri_adc_toggle_CTRLA_SLAVEEN_bit(const void *const hw) |
| 620 | { |
| 621 | ADC_CRITICAL_SECTION_ENTER(); |
| 622 | ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_SLAVEEN; |
| 623 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 624 | ADC_CRITICAL_SECTION_LEAVE(); |
| 625 | } |
| 626 | |
| 627 | static inline void hri_adc_set_CTRLA_RUNSTDBY_bit(const void *const hw) |
| 628 | { |
| 629 | ADC_CRITICAL_SECTION_ENTER(); |
| 630 | ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_RUNSTDBY; |
| 631 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 632 | ADC_CRITICAL_SECTION_LEAVE(); |
| 633 | } |
| 634 | |
| 635 | static inline bool hri_adc_get_CTRLA_RUNSTDBY_bit(const void *const hw) |
| 636 | { |
| 637 | uint16_t tmp; |
| 638 | tmp = ((Adc *)hw)->CTRLA.reg; |
| 639 | tmp = (tmp & ADC_CTRLA_RUNSTDBY) >> ADC_CTRLA_RUNSTDBY_Pos; |
| 640 | return (bool)tmp; |
| 641 | } |
| 642 | |
| 643 | static inline void hri_adc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) |
| 644 | { |
| 645 | uint16_t tmp; |
| 646 | ADC_CRITICAL_SECTION_ENTER(); |
| 647 | tmp = ((Adc *)hw)->CTRLA.reg; |
| 648 | tmp &= ~ADC_CTRLA_RUNSTDBY; |
| 649 | tmp |= value << ADC_CTRLA_RUNSTDBY_Pos; |
| 650 | ((Adc *)hw)->CTRLA.reg = tmp; |
| 651 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 652 | ADC_CRITICAL_SECTION_LEAVE(); |
| 653 | } |
| 654 | |
| 655 | static inline void hri_adc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) |
| 656 | { |
| 657 | ADC_CRITICAL_SECTION_ENTER(); |
| 658 | ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_RUNSTDBY; |
| 659 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 660 | ADC_CRITICAL_SECTION_LEAVE(); |
| 661 | } |
| 662 | |
| 663 | static inline void hri_adc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) |
| 664 | { |
| 665 | ADC_CRITICAL_SECTION_ENTER(); |
| 666 | ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_RUNSTDBY; |
| 667 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 668 | ADC_CRITICAL_SECTION_LEAVE(); |
| 669 | } |
| 670 | |
| 671 | static inline void hri_adc_set_CTRLA_ONDEMAND_bit(const void *const hw) |
| 672 | { |
| 673 | ADC_CRITICAL_SECTION_ENTER(); |
| 674 | ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ONDEMAND; |
| 675 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 676 | ADC_CRITICAL_SECTION_LEAVE(); |
| 677 | } |
| 678 | |
| 679 | static inline bool hri_adc_get_CTRLA_ONDEMAND_bit(const void *const hw) |
| 680 | { |
| 681 | uint16_t tmp; |
| 682 | tmp = ((Adc *)hw)->CTRLA.reg; |
| 683 | tmp = (tmp & ADC_CTRLA_ONDEMAND) >> ADC_CTRLA_ONDEMAND_Pos; |
| 684 | return (bool)tmp; |
| 685 | } |
| 686 | |
| 687 | static inline void hri_adc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) |
| 688 | { |
| 689 | uint16_t tmp; |
| 690 | ADC_CRITICAL_SECTION_ENTER(); |
| 691 | tmp = ((Adc *)hw)->CTRLA.reg; |
| 692 | tmp &= ~ADC_CTRLA_ONDEMAND; |
| 693 | tmp |= value << ADC_CTRLA_ONDEMAND_Pos; |
| 694 | ((Adc *)hw)->CTRLA.reg = tmp; |
| 695 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 696 | ADC_CRITICAL_SECTION_LEAVE(); |
| 697 | } |
| 698 | |
| 699 | static inline void hri_adc_clear_CTRLA_ONDEMAND_bit(const void *const hw) |
| 700 | { |
| 701 | ADC_CRITICAL_SECTION_ENTER(); |
| 702 | ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ONDEMAND; |
| 703 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 704 | ADC_CRITICAL_SECTION_LEAVE(); |
| 705 | } |
| 706 | |
| 707 | static inline void hri_adc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) |
| 708 | { |
| 709 | ADC_CRITICAL_SECTION_ENTER(); |
| 710 | ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ONDEMAND; |
| 711 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 712 | ADC_CRITICAL_SECTION_LEAVE(); |
| 713 | } |
| 714 | |
| 715 | static inline void hri_adc_set_CTRLA_R2R_bit(const void *const hw) |
| 716 | { |
| 717 | ADC_CRITICAL_SECTION_ENTER(); |
| 718 | ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_R2R; |
| 719 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 720 | ADC_CRITICAL_SECTION_LEAVE(); |
| 721 | } |
| 722 | |
| 723 | static inline bool hri_adc_get_CTRLA_R2R_bit(const void *const hw) |
| 724 | { |
| 725 | uint16_t tmp; |
| 726 | tmp = ((Adc *)hw)->CTRLA.reg; |
| 727 | tmp = (tmp & ADC_CTRLA_R2R) >> ADC_CTRLA_R2R_Pos; |
| 728 | return (bool)tmp; |
| 729 | } |
| 730 | |
| 731 | static inline void hri_adc_write_CTRLA_R2R_bit(const void *const hw, bool value) |
| 732 | { |
| 733 | uint16_t tmp; |
| 734 | ADC_CRITICAL_SECTION_ENTER(); |
| 735 | tmp = ((Adc *)hw)->CTRLA.reg; |
| 736 | tmp &= ~ADC_CTRLA_R2R; |
| 737 | tmp |= value << ADC_CTRLA_R2R_Pos; |
| 738 | ((Adc *)hw)->CTRLA.reg = tmp; |
| 739 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 740 | ADC_CRITICAL_SECTION_LEAVE(); |
| 741 | } |
| 742 | |
| 743 | static inline void hri_adc_clear_CTRLA_R2R_bit(const void *const hw) |
| 744 | { |
| 745 | ADC_CRITICAL_SECTION_ENTER(); |
| 746 | ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_R2R; |
| 747 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 748 | ADC_CRITICAL_SECTION_LEAVE(); |
| 749 | } |
| 750 | |
| 751 | static inline void hri_adc_toggle_CTRLA_R2R_bit(const void *const hw) |
| 752 | { |
| 753 | ADC_CRITICAL_SECTION_ENTER(); |
| 754 | ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_R2R; |
| 755 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 756 | ADC_CRITICAL_SECTION_LEAVE(); |
| 757 | } |
| 758 | |
| 759 | static inline void hri_adc_set_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) |
| 760 | { |
| 761 | ADC_CRITICAL_SECTION_ENTER(); |
| 762 | ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_DUALSEL(mask); |
| 763 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 764 | ADC_CRITICAL_SECTION_LEAVE(); |
| 765 | } |
| 766 | |
| 767 | static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) |
| 768 | { |
| 769 | uint16_t tmp; |
| 770 | tmp = ((Adc *)hw)->CTRLA.reg; |
| 771 | tmp = (tmp & ADC_CTRLA_DUALSEL(mask)) >> ADC_CTRLA_DUALSEL_Pos; |
| 772 | return tmp; |
| 773 | } |
| 774 | |
| 775 | static inline void hri_adc_write_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t data) |
| 776 | { |
| 777 | uint16_t tmp; |
| 778 | ADC_CRITICAL_SECTION_ENTER(); |
| 779 | tmp = ((Adc *)hw)->CTRLA.reg; |
| 780 | tmp &= ~ADC_CTRLA_DUALSEL_Msk; |
| 781 | tmp |= ADC_CTRLA_DUALSEL(data); |
| 782 | ((Adc *)hw)->CTRLA.reg = tmp; |
| 783 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 784 | ADC_CRITICAL_SECTION_LEAVE(); |
| 785 | } |
| 786 | |
| 787 | static inline void hri_adc_clear_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) |
| 788 | { |
| 789 | ADC_CRITICAL_SECTION_ENTER(); |
| 790 | ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_DUALSEL(mask); |
| 791 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 792 | ADC_CRITICAL_SECTION_LEAVE(); |
| 793 | } |
| 794 | |
| 795 | static inline void hri_adc_toggle_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) |
| 796 | { |
| 797 | ADC_CRITICAL_SECTION_ENTER(); |
| 798 | ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_DUALSEL(mask); |
| 799 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 800 | ADC_CRITICAL_SECTION_LEAVE(); |
| 801 | } |
| 802 | |
| 803 | static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_DUALSEL_bf(const void *const hw) |
| 804 | { |
| 805 | uint16_t tmp; |
| 806 | tmp = ((Adc *)hw)->CTRLA.reg; |
| 807 | tmp = (tmp & ADC_CTRLA_DUALSEL_Msk) >> ADC_CTRLA_DUALSEL_Pos; |
| 808 | return tmp; |
| 809 | } |
| 810 | |
| 811 | static inline void hri_adc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) |
| 812 | { |
| 813 | ADC_CRITICAL_SECTION_ENTER(); |
| 814 | ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_PRESCALER(mask); |
| 815 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 816 | ADC_CRITICAL_SECTION_LEAVE(); |
| 817 | } |
| 818 | |
| 819 | static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) |
| 820 | { |
| 821 | uint16_t tmp; |
| 822 | tmp = ((Adc *)hw)->CTRLA.reg; |
| 823 | tmp = (tmp & ADC_CTRLA_PRESCALER(mask)) >> ADC_CTRLA_PRESCALER_Pos; |
| 824 | return tmp; |
| 825 | } |
| 826 | |
| 827 | static inline void hri_adc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t data) |
| 828 | { |
| 829 | uint16_t tmp; |
| 830 | ADC_CRITICAL_SECTION_ENTER(); |
| 831 | tmp = ((Adc *)hw)->CTRLA.reg; |
| 832 | tmp &= ~ADC_CTRLA_PRESCALER_Msk; |
| 833 | tmp |= ADC_CTRLA_PRESCALER(data); |
| 834 | ((Adc *)hw)->CTRLA.reg = tmp; |
| 835 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 836 | ADC_CRITICAL_SECTION_LEAVE(); |
| 837 | } |
| 838 | |
| 839 | static inline void hri_adc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) |
| 840 | { |
| 841 | ADC_CRITICAL_SECTION_ENTER(); |
| 842 | ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_PRESCALER(mask); |
| 843 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 844 | ADC_CRITICAL_SECTION_LEAVE(); |
| 845 | } |
| 846 | |
| 847 | static inline void hri_adc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) |
| 848 | { |
| 849 | ADC_CRITICAL_SECTION_ENTER(); |
| 850 | ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_PRESCALER(mask); |
| 851 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 852 | ADC_CRITICAL_SECTION_LEAVE(); |
| 853 | } |
| 854 | |
| 855 | static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_PRESCALER_bf(const void *const hw) |
| 856 | { |
| 857 | uint16_t tmp; |
| 858 | tmp = ((Adc *)hw)->CTRLA.reg; |
| 859 | tmp = (tmp & ADC_CTRLA_PRESCALER_Msk) >> ADC_CTRLA_PRESCALER_Pos; |
| 860 | return tmp; |
| 861 | } |
| 862 | |
| 863 | static inline void hri_adc_set_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) |
| 864 | { |
| 865 | ADC_CRITICAL_SECTION_ENTER(); |
| 866 | ((Adc *)hw)->CTRLA.reg |= mask; |
| 867 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); |
| 868 | ADC_CRITICAL_SECTION_LEAVE(); |
| 869 | } |
| 870 | |
| 871 | static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) |
| 872 | { |
| 873 | uint16_t tmp; |
| 874 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); |
| 875 | tmp = ((Adc *)hw)->CTRLA.reg; |
| 876 | tmp &= mask; |
| 877 | return tmp; |
| 878 | } |
| 879 | |
| 880 | static inline void hri_adc_write_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t data) |
| 881 | { |
| 882 | ADC_CRITICAL_SECTION_ENTER(); |
| 883 | ((Adc *)hw)->CTRLA.reg = data; |
| 884 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); |
| 885 | ADC_CRITICAL_SECTION_LEAVE(); |
| 886 | } |
| 887 | |
| 888 | static inline void hri_adc_clear_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) |
| 889 | { |
| 890 | ADC_CRITICAL_SECTION_ENTER(); |
| 891 | ((Adc *)hw)->CTRLA.reg &= ~mask; |
| 892 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); |
| 893 | ADC_CRITICAL_SECTION_LEAVE(); |
| 894 | } |
| 895 | |
| 896 | static inline void hri_adc_toggle_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) |
| 897 | { |
| 898 | ADC_CRITICAL_SECTION_ENTER(); |
| 899 | ((Adc *)hw)->CTRLA.reg ^= mask; |
| 900 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); |
| 901 | ADC_CRITICAL_SECTION_LEAVE(); |
| 902 | } |
| 903 | |
| 904 | static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_reg(const void *const hw) |
| 905 | { |
| 906 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); |
| 907 | return ((Adc *)hw)->CTRLA.reg; |
| 908 | } |
| 909 | |
| 910 | static inline void hri_adc_set_EVCTRL_FLUSHEI_bit(const void *const hw) |
| 911 | { |
| 912 | ADC_CRITICAL_SECTION_ENTER(); |
| 913 | ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHEI; |
| 914 | ADC_CRITICAL_SECTION_LEAVE(); |
| 915 | } |
| 916 | |
| 917 | static inline bool hri_adc_get_EVCTRL_FLUSHEI_bit(const void *const hw) |
| 918 | { |
| 919 | uint8_t tmp; |
| 920 | tmp = ((Adc *)hw)->EVCTRL.reg; |
| 921 | tmp = (tmp & ADC_EVCTRL_FLUSHEI) >> ADC_EVCTRL_FLUSHEI_Pos; |
| 922 | return (bool)tmp; |
| 923 | } |
| 924 | |
| 925 | static inline void hri_adc_write_EVCTRL_FLUSHEI_bit(const void *const hw, bool value) |
| 926 | { |
| 927 | uint8_t tmp; |
| 928 | ADC_CRITICAL_SECTION_ENTER(); |
| 929 | tmp = ((Adc *)hw)->EVCTRL.reg; |
| 930 | tmp &= ~ADC_EVCTRL_FLUSHEI; |
| 931 | tmp |= value << ADC_EVCTRL_FLUSHEI_Pos; |
| 932 | ((Adc *)hw)->EVCTRL.reg = tmp; |
| 933 | ADC_CRITICAL_SECTION_LEAVE(); |
| 934 | } |
| 935 | |
| 936 | static inline void hri_adc_clear_EVCTRL_FLUSHEI_bit(const void *const hw) |
| 937 | { |
| 938 | ADC_CRITICAL_SECTION_ENTER(); |
| 939 | ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHEI; |
| 940 | ADC_CRITICAL_SECTION_LEAVE(); |
| 941 | } |
| 942 | |
| 943 | static inline void hri_adc_toggle_EVCTRL_FLUSHEI_bit(const void *const hw) |
| 944 | { |
| 945 | ADC_CRITICAL_SECTION_ENTER(); |
| 946 | ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHEI; |
| 947 | ADC_CRITICAL_SECTION_LEAVE(); |
| 948 | } |
| 949 | |
| 950 | static inline void hri_adc_set_EVCTRL_STARTEI_bit(const void *const hw) |
| 951 | { |
| 952 | ADC_CRITICAL_SECTION_ENTER(); |
| 953 | ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTEI; |
| 954 | ADC_CRITICAL_SECTION_LEAVE(); |
| 955 | } |
| 956 | |
| 957 | static inline bool hri_adc_get_EVCTRL_STARTEI_bit(const void *const hw) |
| 958 | { |
| 959 | uint8_t tmp; |
| 960 | tmp = ((Adc *)hw)->EVCTRL.reg; |
| 961 | tmp = (tmp & ADC_EVCTRL_STARTEI) >> ADC_EVCTRL_STARTEI_Pos; |
| 962 | return (bool)tmp; |
| 963 | } |
| 964 | |
| 965 | static inline void hri_adc_write_EVCTRL_STARTEI_bit(const void *const hw, bool value) |
| 966 | { |
| 967 | uint8_t tmp; |
| 968 | ADC_CRITICAL_SECTION_ENTER(); |
| 969 | tmp = ((Adc *)hw)->EVCTRL.reg; |
| 970 | tmp &= ~ADC_EVCTRL_STARTEI; |
| 971 | tmp |= value << ADC_EVCTRL_STARTEI_Pos; |
| 972 | ((Adc *)hw)->EVCTRL.reg = tmp; |
| 973 | ADC_CRITICAL_SECTION_LEAVE(); |
| 974 | } |
| 975 | |
| 976 | static inline void hri_adc_clear_EVCTRL_STARTEI_bit(const void *const hw) |
| 977 | { |
| 978 | ADC_CRITICAL_SECTION_ENTER(); |
| 979 | ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTEI; |
| 980 | ADC_CRITICAL_SECTION_LEAVE(); |
| 981 | } |
| 982 | |
| 983 | static inline void hri_adc_toggle_EVCTRL_STARTEI_bit(const void *const hw) |
| 984 | { |
| 985 | ADC_CRITICAL_SECTION_ENTER(); |
| 986 | ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTEI; |
| 987 | ADC_CRITICAL_SECTION_LEAVE(); |
| 988 | } |
| 989 | |
| 990 | static inline void hri_adc_set_EVCTRL_FLUSHINV_bit(const void *const hw) |
| 991 | { |
| 992 | ADC_CRITICAL_SECTION_ENTER(); |
| 993 | ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHINV; |
| 994 | ADC_CRITICAL_SECTION_LEAVE(); |
| 995 | } |
| 996 | |
| 997 | static inline bool hri_adc_get_EVCTRL_FLUSHINV_bit(const void *const hw) |
| 998 | { |
| 999 | uint8_t tmp; |
| 1000 | tmp = ((Adc *)hw)->EVCTRL.reg; |
| 1001 | tmp = (tmp & ADC_EVCTRL_FLUSHINV) >> ADC_EVCTRL_FLUSHINV_Pos; |
| 1002 | return (bool)tmp; |
| 1003 | } |
| 1004 | |
| 1005 | static inline void hri_adc_write_EVCTRL_FLUSHINV_bit(const void *const hw, bool value) |
| 1006 | { |
| 1007 | uint8_t tmp; |
| 1008 | ADC_CRITICAL_SECTION_ENTER(); |
| 1009 | tmp = ((Adc *)hw)->EVCTRL.reg; |
| 1010 | tmp &= ~ADC_EVCTRL_FLUSHINV; |
| 1011 | tmp |= value << ADC_EVCTRL_FLUSHINV_Pos; |
| 1012 | ((Adc *)hw)->EVCTRL.reg = tmp; |
| 1013 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1014 | } |
| 1015 | |
| 1016 | static inline void hri_adc_clear_EVCTRL_FLUSHINV_bit(const void *const hw) |
| 1017 | { |
| 1018 | ADC_CRITICAL_SECTION_ENTER(); |
| 1019 | ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHINV; |
| 1020 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1021 | } |
| 1022 | |
| 1023 | static inline void hri_adc_toggle_EVCTRL_FLUSHINV_bit(const void *const hw) |
| 1024 | { |
| 1025 | ADC_CRITICAL_SECTION_ENTER(); |
| 1026 | ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHINV; |
| 1027 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1028 | } |
| 1029 | |
| 1030 | static inline void hri_adc_set_EVCTRL_STARTINV_bit(const void *const hw) |
| 1031 | { |
| 1032 | ADC_CRITICAL_SECTION_ENTER(); |
| 1033 | ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTINV; |
| 1034 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1035 | } |
| 1036 | |
| 1037 | static inline bool hri_adc_get_EVCTRL_STARTINV_bit(const void *const hw) |
| 1038 | { |
| 1039 | uint8_t tmp; |
| 1040 | tmp = ((Adc *)hw)->EVCTRL.reg; |
| 1041 | tmp = (tmp & ADC_EVCTRL_STARTINV) >> ADC_EVCTRL_STARTINV_Pos; |
| 1042 | return (bool)tmp; |
| 1043 | } |
| 1044 | |
| 1045 | static inline void hri_adc_write_EVCTRL_STARTINV_bit(const void *const hw, bool value) |
| 1046 | { |
| 1047 | uint8_t tmp; |
| 1048 | ADC_CRITICAL_SECTION_ENTER(); |
| 1049 | tmp = ((Adc *)hw)->EVCTRL.reg; |
| 1050 | tmp &= ~ADC_EVCTRL_STARTINV; |
| 1051 | tmp |= value << ADC_EVCTRL_STARTINV_Pos; |
| 1052 | ((Adc *)hw)->EVCTRL.reg = tmp; |
| 1053 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1054 | } |
| 1055 | |
| 1056 | static inline void hri_adc_clear_EVCTRL_STARTINV_bit(const void *const hw) |
| 1057 | { |
| 1058 | ADC_CRITICAL_SECTION_ENTER(); |
| 1059 | ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTINV; |
| 1060 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1061 | } |
| 1062 | |
| 1063 | static inline void hri_adc_toggle_EVCTRL_STARTINV_bit(const void *const hw) |
| 1064 | { |
| 1065 | ADC_CRITICAL_SECTION_ENTER(); |
| 1066 | ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTINV; |
| 1067 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1068 | } |
| 1069 | |
| 1070 | static inline void hri_adc_set_EVCTRL_RESRDYEO_bit(const void *const hw) |
| 1071 | { |
| 1072 | ADC_CRITICAL_SECTION_ENTER(); |
| 1073 | ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_RESRDYEO; |
| 1074 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1075 | } |
| 1076 | |
| 1077 | static inline bool hri_adc_get_EVCTRL_RESRDYEO_bit(const void *const hw) |
| 1078 | { |
| 1079 | uint8_t tmp; |
| 1080 | tmp = ((Adc *)hw)->EVCTRL.reg; |
| 1081 | tmp = (tmp & ADC_EVCTRL_RESRDYEO) >> ADC_EVCTRL_RESRDYEO_Pos; |
| 1082 | return (bool)tmp; |
| 1083 | } |
| 1084 | |
| 1085 | static inline void hri_adc_write_EVCTRL_RESRDYEO_bit(const void *const hw, bool value) |
| 1086 | { |
| 1087 | uint8_t tmp; |
| 1088 | ADC_CRITICAL_SECTION_ENTER(); |
| 1089 | tmp = ((Adc *)hw)->EVCTRL.reg; |
| 1090 | tmp &= ~ADC_EVCTRL_RESRDYEO; |
| 1091 | tmp |= value << ADC_EVCTRL_RESRDYEO_Pos; |
| 1092 | ((Adc *)hw)->EVCTRL.reg = tmp; |
| 1093 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1094 | } |
| 1095 | |
| 1096 | static inline void hri_adc_clear_EVCTRL_RESRDYEO_bit(const void *const hw) |
| 1097 | { |
| 1098 | ADC_CRITICAL_SECTION_ENTER(); |
| 1099 | ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_RESRDYEO; |
| 1100 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1101 | } |
| 1102 | |
| 1103 | static inline void hri_adc_toggle_EVCTRL_RESRDYEO_bit(const void *const hw) |
| 1104 | { |
| 1105 | ADC_CRITICAL_SECTION_ENTER(); |
| 1106 | ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_RESRDYEO; |
| 1107 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1108 | } |
| 1109 | |
| 1110 | static inline void hri_adc_set_EVCTRL_WINMONEO_bit(const void *const hw) |
| 1111 | { |
| 1112 | ADC_CRITICAL_SECTION_ENTER(); |
| 1113 | ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_WINMONEO; |
| 1114 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1115 | } |
| 1116 | |
| 1117 | static inline bool hri_adc_get_EVCTRL_WINMONEO_bit(const void *const hw) |
| 1118 | { |
| 1119 | uint8_t tmp; |
| 1120 | tmp = ((Adc *)hw)->EVCTRL.reg; |
| 1121 | tmp = (tmp & ADC_EVCTRL_WINMONEO) >> ADC_EVCTRL_WINMONEO_Pos; |
| 1122 | return (bool)tmp; |
| 1123 | } |
| 1124 | |
| 1125 | static inline void hri_adc_write_EVCTRL_WINMONEO_bit(const void *const hw, bool value) |
| 1126 | { |
| 1127 | uint8_t tmp; |
| 1128 | ADC_CRITICAL_SECTION_ENTER(); |
| 1129 | tmp = ((Adc *)hw)->EVCTRL.reg; |
| 1130 | tmp &= ~ADC_EVCTRL_WINMONEO; |
| 1131 | tmp |= value << ADC_EVCTRL_WINMONEO_Pos; |
| 1132 | ((Adc *)hw)->EVCTRL.reg = tmp; |
| 1133 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1134 | } |
| 1135 | |
| 1136 | static inline void hri_adc_clear_EVCTRL_WINMONEO_bit(const void *const hw) |
| 1137 | { |
| 1138 | ADC_CRITICAL_SECTION_ENTER(); |
| 1139 | ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_WINMONEO; |
| 1140 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1141 | } |
| 1142 | |
| 1143 | static inline void hri_adc_toggle_EVCTRL_WINMONEO_bit(const void *const hw) |
| 1144 | { |
| 1145 | ADC_CRITICAL_SECTION_ENTER(); |
| 1146 | ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_WINMONEO; |
| 1147 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1148 | } |
| 1149 | |
| 1150 | static inline void hri_adc_set_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) |
| 1151 | { |
| 1152 | ADC_CRITICAL_SECTION_ENTER(); |
| 1153 | ((Adc *)hw)->EVCTRL.reg |= mask; |
| 1154 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1155 | } |
| 1156 | |
| 1157 | static inline hri_adc_evctrl_reg_t hri_adc_get_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) |
| 1158 | { |
| 1159 | uint8_t tmp; |
| 1160 | tmp = ((Adc *)hw)->EVCTRL.reg; |
| 1161 | tmp &= mask; |
| 1162 | return tmp; |
| 1163 | } |
| 1164 | |
| 1165 | static inline void hri_adc_write_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t data) |
| 1166 | { |
| 1167 | ADC_CRITICAL_SECTION_ENTER(); |
| 1168 | ((Adc *)hw)->EVCTRL.reg = data; |
| 1169 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1170 | } |
| 1171 | |
| 1172 | static inline void hri_adc_clear_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) |
| 1173 | { |
| 1174 | ADC_CRITICAL_SECTION_ENTER(); |
| 1175 | ((Adc *)hw)->EVCTRL.reg &= ~mask; |
| 1176 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1177 | } |
| 1178 | |
| 1179 | static inline void hri_adc_toggle_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) |
| 1180 | { |
| 1181 | ADC_CRITICAL_SECTION_ENTER(); |
| 1182 | ((Adc *)hw)->EVCTRL.reg ^= mask; |
| 1183 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1184 | } |
| 1185 | |
| 1186 | static inline hri_adc_evctrl_reg_t hri_adc_read_EVCTRL_reg(const void *const hw) |
| 1187 | { |
| 1188 | return ((Adc *)hw)->EVCTRL.reg; |
| 1189 | } |
| 1190 | |
| 1191 | static inline void hri_adc_set_DBGCTRL_DBGRUN_bit(const void *const hw) |
| 1192 | { |
| 1193 | ADC_CRITICAL_SECTION_ENTER(); |
| 1194 | ((Adc *)hw)->DBGCTRL.reg |= ADC_DBGCTRL_DBGRUN; |
| 1195 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1196 | } |
| 1197 | |
| 1198 | static inline bool hri_adc_get_DBGCTRL_DBGRUN_bit(const void *const hw) |
| 1199 | { |
| 1200 | uint8_t tmp; |
| 1201 | tmp = ((Adc *)hw)->DBGCTRL.reg; |
| 1202 | tmp = (tmp & ADC_DBGCTRL_DBGRUN) >> ADC_DBGCTRL_DBGRUN_Pos; |
| 1203 | return (bool)tmp; |
| 1204 | } |
| 1205 | |
| 1206 | static inline void hri_adc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) |
| 1207 | { |
| 1208 | uint8_t tmp; |
| 1209 | ADC_CRITICAL_SECTION_ENTER(); |
| 1210 | tmp = ((Adc *)hw)->DBGCTRL.reg; |
| 1211 | tmp &= ~ADC_DBGCTRL_DBGRUN; |
| 1212 | tmp |= value << ADC_DBGCTRL_DBGRUN_Pos; |
| 1213 | ((Adc *)hw)->DBGCTRL.reg = tmp; |
| 1214 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1215 | } |
| 1216 | |
| 1217 | static inline void hri_adc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) |
| 1218 | { |
| 1219 | ADC_CRITICAL_SECTION_ENTER(); |
| 1220 | ((Adc *)hw)->DBGCTRL.reg &= ~ADC_DBGCTRL_DBGRUN; |
| 1221 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1222 | } |
| 1223 | |
| 1224 | static inline void hri_adc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) |
| 1225 | { |
| 1226 | ADC_CRITICAL_SECTION_ENTER(); |
| 1227 | ((Adc *)hw)->DBGCTRL.reg ^= ADC_DBGCTRL_DBGRUN; |
| 1228 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1229 | } |
| 1230 | |
| 1231 | static inline void hri_adc_set_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) |
| 1232 | { |
| 1233 | ADC_CRITICAL_SECTION_ENTER(); |
| 1234 | ((Adc *)hw)->DBGCTRL.reg |= mask; |
| 1235 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1236 | } |
| 1237 | |
| 1238 | static inline hri_adc_dbgctrl_reg_t hri_adc_get_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) |
| 1239 | { |
| 1240 | uint8_t tmp; |
| 1241 | tmp = ((Adc *)hw)->DBGCTRL.reg; |
| 1242 | tmp &= mask; |
| 1243 | return tmp; |
| 1244 | } |
| 1245 | |
| 1246 | static inline void hri_adc_write_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t data) |
| 1247 | { |
| 1248 | ADC_CRITICAL_SECTION_ENTER(); |
| 1249 | ((Adc *)hw)->DBGCTRL.reg = data; |
| 1250 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1251 | } |
| 1252 | |
| 1253 | static inline void hri_adc_clear_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) |
| 1254 | { |
| 1255 | ADC_CRITICAL_SECTION_ENTER(); |
| 1256 | ((Adc *)hw)->DBGCTRL.reg &= ~mask; |
| 1257 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1258 | } |
| 1259 | |
| 1260 | static inline void hri_adc_toggle_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) |
| 1261 | { |
| 1262 | ADC_CRITICAL_SECTION_ENTER(); |
| 1263 | ((Adc *)hw)->DBGCTRL.reg ^= mask; |
| 1264 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1265 | } |
| 1266 | |
| 1267 | static inline hri_adc_dbgctrl_reg_t hri_adc_read_DBGCTRL_reg(const void *const hw) |
| 1268 | { |
| 1269 | return ((Adc *)hw)->DBGCTRL.reg; |
| 1270 | } |
| 1271 | |
| 1272 | static inline void hri_adc_set_INPUTCTRL_DIFFMODE_bit(const void *const hw) |
| 1273 | { |
| 1274 | ADC_CRITICAL_SECTION_ENTER(); |
| 1275 | ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_DIFFMODE; |
| 1276 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1277 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1278 | } |
| 1279 | |
| 1280 | static inline bool hri_adc_get_INPUTCTRL_DIFFMODE_bit(const void *const hw) |
| 1281 | { |
| 1282 | uint16_t tmp; |
| 1283 | tmp = ((Adc *)hw)->INPUTCTRL.reg; |
| 1284 | tmp = (tmp & ADC_INPUTCTRL_DIFFMODE) >> ADC_INPUTCTRL_DIFFMODE_Pos; |
| 1285 | return (bool)tmp; |
| 1286 | } |
| 1287 | |
| 1288 | static inline void hri_adc_write_INPUTCTRL_DIFFMODE_bit(const void *const hw, bool value) |
| 1289 | { |
| 1290 | uint16_t tmp; |
| 1291 | ADC_CRITICAL_SECTION_ENTER(); |
| 1292 | tmp = ((Adc *)hw)->INPUTCTRL.reg; |
| 1293 | tmp &= ~ADC_INPUTCTRL_DIFFMODE; |
| 1294 | tmp |= value << ADC_INPUTCTRL_DIFFMODE_Pos; |
| 1295 | ((Adc *)hw)->INPUTCTRL.reg = tmp; |
| 1296 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1297 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1298 | } |
| 1299 | |
| 1300 | static inline void hri_adc_clear_INPUTCTRL_DIFFMODE_bit(const void *const hw) |
| 1301 | { |
| 1302 | ADC_CRITICAL_SECTION_ENTER(); |
| 1303 | ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_DIFFMODE; |
| 1304 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1305 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1306 | } |
| 1307 | |
| 1308 | static inline void hri_adc_toggle_INPUTCTRL_DIFFMODE_bit(const void *const hw) |
| 1309 | { |
| 1310 | ADC_CRITICAL_SECTION_ENTER(); |
| 1311 | ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_DIFFMODE; |
| 1312 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1313 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1314 | } |
| 1315 | |
| 1316 | static inline void hri_adc_set_INPUTCTRL_DSEQSTOP_bit(const void *const hw) |
| 1317 | { |
| 1318 | ADC_CRITICAL_SECTION_ENTER(); |
| 1319 | ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_DSEQSTOP; |
| 1320 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1321 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1322 | } |
| 1323 | |
| 1324 | static inline bool hri_adc_get_INPUTCTRL_DSEQSTOP_bit(const void *const hw) |
| 1325 | { |
| 1326 | uint16_t tmp; |
| 1327 | tmp = ((Adc *)hw)->INPUTCTRL.reg; |
| 1328 | tmp = (tmp & ADC_INPUTCTRL_DSEQSTOP) >> ADC_INPUTCTRL_DSEQSTOP_Pos; |
| 1329 | return (bool)tmp; |
| 1330 | } |
| 1331 | |
| 1332 | static inline void hri_adc_write_INPUTCTRL_DSEQSTOP_bit(const void *const hw, bool value) |
| 1333 | { |
| 1334 | uint16_t tmp; |
| 1335 | ADC_CRITICAL_SECTION_ENTER(); |
| 1336 | tmp = ((Adc *)hw)->INPUTCTRL.reg; |
| 1337 | tmp &= ~ADC_INPUTCTRL_DSEQSTOP; |
| 1338 | tmp |= value << ADC_INPUTCTRL_DSEQSTOP_Pos; |
| 1339 | ((Adc *)hw)->INPUTCTRL.reg = tmp; |
| 1340 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1341 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1342 | } |
| 1343 | |
| 1344 | static inline void hri_adc_clear_INPUTCTRL_DSEQSTOP_bit(const void *const hw) |
| 1345 | { |
| 1346 | ADC_CRITICAL_SECTION_ENTER(); |
| 1347 | ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_DSEQSTOP; |
| 1348 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1349 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1350 | } |
| 1351 | |
| 1352 | static inline void hri_adc_toggle_INPUTCTRL_DSEQSTOP_bit(const void *const hw) |
| 1353 | { |
| 1354 | ADC_CRITICAL_SECTION_ENTER(); |
| 1355 | ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_DSEQSTOP; |
| 1356 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1357 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1358 | } |
| 1359 | |
| 1360 | static inline void hri_adc_set_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) |
| 1361 | { |
| 1362 | ADC_CRITICAL_SECTION_ENTER(); |
| 1363 | ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXPOS(mask); |
| 1364 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1365 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1366 | } |
| 1367 | |
| 1368 | static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXPOS_bf(const void *const hw, |
| 1369 | hri_adc_inputctrl_reg_t mask) |
| 1370 | { |
| 1371 | uint16_t tmp; |
| 1372 | tmp = ((Adc *)hw)->INPUTCTRL.reg; |
| 1373 | tmp = (tmp & ADC_INPUTCTRL_MUXPOS(mask)) >> ADC_INPUTCTRL_MUXPOS_Pos; |
| 1374 | return tmp; |
| 1375 | } |
| 1376 | |
| 1377 | static inline void hri_adc_write_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t data) |
| 1378 | { |
| 1379 | uint16_t tmp; |
| 1380 | ADC_CRITICAL_SECTION_ENTER(); |
| 1381 | tmp = ((Adc *)hw)->INPUTCTRL.reg; |
| 1382 | tmp &= ~ADC_INPUTCTRL_MUXPOS_Msk; |
| 1383 | tmp |= ADC_INPUTCTRL_MUXPOS(data); |
| 1384 | ((Adc *)hw)->INPUTCTRL.reg = tmp; |
| 1385 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1386 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1387 | } |
| 1388 | |
| 1389 | static inline void hri_adc_clear_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) |
| 1390 | { |
| 1391 | ADC_CRITICAL_SECTION_ENTER(); |
| 1392 | ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXPOS(mask); |
| 1393 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1394 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1395 | } |
| 1396 | |
| 1397 | static inline void hri_adc_toggle_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) |
| 1398 | { |
| 1399 | ADC_CRITICAL_SECTION_ENTER(); |
| 1400 | ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXPOS(mask); |
| 1401 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1402 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1403 | } |
| 1404 | |
| 1405 | static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXPOS_bf(const void *const hw) |
| 1406 | { |
| 1407 | uint16_t tmp; |
| 1408 | tmp = ((Adc *)hw)->INPUTCTRL.reg; |
| 1409 | tmp = (tmp & ADC_INPUTCTRL_MUXPOS_Msk) >> ADC_INPUTCTRL_MUXPOS_Pos; |
| 1410 | return tmp; |
| 1411 | } |
| 1412 | |
| 1413 | static inline void hri_adc_set_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) |
| 1414 | { |
| 1415 | ADC_CRITICAL_SECTION_ENTER(); |
| 1416 | ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXNEG(mask); |
| 1417 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1418 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1419 | } |
| 1420 | |
| 1421 | static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXNEG_bf(const void *const hw, |
| 1422 | hri_adc_inputctrl_reg_t mask) |
| 1423 | { |
| 1424 | uint16_t tmp; |
| 1425 | tmp = ((Adc *)hw)->INPUTCTRL.reg; |
| 1426 | tmp = (tmp & ADC_INPUTCTRL_MUXNEG(mask)) >> ADC_INPUTCTRL_MUXNEG_Pos; |
| 1427 | return tmp; |
| 1428 | } |
| 1429 | |
| 1430 | static inline void hri_adc_write_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t data) |
| 1431 | { |
| 1432 | uint16_t tmp; |
| 1433 | ADC_CRITICAL_SECTION_ENTER(); |
| 1434 | tmp = ((Adc *)hw)->INPUTCTRL.reg; |
| 1435 | tmp &= ~ADC_INPUTCTRL_MUXNEG_Msk; |
| 1436 | tmp |= ADC_INPUTCTRL_MUXNEG(data); |
| 1437 | ((Adc *)hw)->INPUTCTRL.reg = tmp; |
| 1438 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1439 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1440 | } |
| 1441 | |
| 1442 | static inline void hri_adc_clear_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) |
| 1443 | { |
| 1444 | ADC_CRITICAL_SECTION_ENTER(); |
| 1445 | ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXNEG(mask); |
| 1446 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1447 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1448 | } |
| 1449 | |
| 1450 | static inline void hri_adc_toggle_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) |
| 1451 | { |
| 1452 | ADC_CRITICAL_SECTION_ENTER(); |
| 1453 | ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXNEG(mask); |
| 1454 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1455 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1456 | } |
| 1457 | |
| 1458 | static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXNEG_bf(const void *const hw) |
| 1459 | { |
| 1460 | uint16_t tmp; |
| 1461 | tmp = ((Adc *)hw)->INPUTCTRL.reg; |
| 1462 | tmp = (tmp & ADC_INPUTCTRL_MUXNEG_Msk) >> ADC_INPUTCTRL_MUXNEG_Pos; |
| 1463 | return tmp; |
| 1464 | } |
| 1465 | |
| 1466 | static inline void hri_adc_set_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) |
| 1467 | { |
| 1468 | ADC_CRITICAL_SECTION_ENTER(); |
| 1469 | ((Adc *)hw)->INPUTCTRL.reg |= mask; |
| 1470 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1471 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1472 | } |
| 1473 | |
| 1474 | static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) |
| 1475 | { |
| 1476 | uint16_t tmp; |
| 1477 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1478 | tmp = ((Adc *)hw)->INPUTCTRL.reg; |
| 1479 | tmp &= mask; |
| 1480 | return tmp; |
| 1481 | } |
| 1482 | |
| 1483 | static inline void hri_adc_write_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t data) |
| 1484 | { |
| 1485 | ADC_CRITICAL_SECTION_ENTER(); |
| 1486 | ((Adc *)hw)->INPUTCTRL.reg = data; |
| 1487 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1488 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1489 | } |
| 1490 | |
| 1491 | static inline void hri_adc_clear_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) |
| 1492 | { |
| 1493 | ADC_CRITICAL_SECTION_ENTER(); |
| 1494 | ((Adc *)hw)->INPUTCTRL.reg &= ~mask; |
| 1495 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1496 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1497 | } |
| 1498 | |
| 1499 | static inline void hri_adc_toggle_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) |
| 1500 | { |
| 1501 | ADC_CRITICAL_SECTION_ENTER(); |
| 1502 | ((Adc *)hw)->INPUTCTRL.reg ^= mask; |
| 1503 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1504 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1505 | } |
| 1506 | |
| 1507 | static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_reg(const void *const hw) |
| 1508 | { |
| 1509 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1510 | return ((Adc *)hw)->INPUTCTRL.reg; |
| 1511 | } |
| 1512 | |
| 1513 | static inline void hri_adc_set_CTRLB_LEFTADJ_bit(const void *const hw) |
| 1514 | { |
| 1515 | ADC_CRITICAL_SECTION_ENTER(); |
| 1516 | ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_LEFTADJ; |
| 1517 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1518 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1519 | } |
| 1520 | |
| 1521 | static inline bool hri_adc_get_CTRLB_LEFTADJ_bit(const void *const hw) |
| 1522 | { |
| 1523 | uint16_t tmp; |
| 1524 | tmp = ((Adc *)hw)->CTRLB.reg; |
| 1525 | tmp = (tmp & ADC_CTRLB_LEFTADJ) >> ADC_CTRLB_LEFTADJ_Pos; |
| 1526 | return (bool)tmp; |
| 1527 | } |
| 1528 | |
| 1529 | static inline void hri_adc_write_CTRLB_LEFTADJ_bit(const void *const hw, bool value) |
| 1530 | { |
| 1531 | uint16_t tmp; |
| 1532 | ADC_CRITICAL_SECTION_ENTER(); |
| 1533 | tmp = ((Adc *)hw)->CTRLB.reg; |
| 1534 | tmp &= ~ADC_CTRLB_LEFTADJ; |
| 1535 | tmp |= value << ADC_CTRLB_LEFTADJ_Pos; |
| 1536 | ((Adc *)hw)->CTRLB.reg = tmp; |
| 1537 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1538 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1539 | } |
| 1540 | |
| 1541 | static inline void hri_adc_clear_CTRLB_LEFTADJ_bit(const void *const hw) |
| 1542 | { |
| 1543 | ADC_CRITICAL_SECTION_ENTER(); |
| 1544 | ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_LEFTADJ; |
| 1545 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1546 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1547 | } |
| 1548 | |
| 1549 | static inline void hri_adc_toggle_CTRLB_LEFTADJ_bit(const void *const hw) |
| 1550 | { |
| 1551 | ADC_CRITICAL_SECTION_ENTER(); |
| 1552 | ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_LEFTADJ; |
| 1553 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1554 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1555 | } |
| 1556 | |
| 1557 | static inline void hri_adc_set_CTRLB_FREERUN_bit(const void *const hw) |
| 1558 | { |
| 1559 | ADC_CRITICAL_SECTION_ENTER(); |
| 1560 | ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_FREERUN; |
| 1561 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1562 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1563 | } |
| 1564 | |
| 1565 | static inline bool hri_adc_get_CTRLB_FREERUN_bit(const void *const hw) |
| 1566 | { |
| 1567 | uint16_t tmp; |
| 1568 | tmp = ((Adc *)hw)->CTRLB.reg; |
| 1569 | tmp = (tmp & ADC_CTRLB_FREERUN) >> ADC_CTRLB_FREERUN_Pos; |
| 1570 | return (bool)tmp; |
| 1571 | } |
| 1572 | |
| 1573 | static inline void hri_adc_write_CTRLB_FREERUN_bit(const void *const hw, bool value) |
| 1574 | { |
| 1575 | uint16_t tmp; |
| 1576 | ADC_CRITICAL_SECTION_ENTER(); |
| 1577 | tmp = ((Adc *)hw)->CTRLB.reg; |
| 1578 | tmp &= ~ADC_CTRLB_FREERUN; |
| 1579 | tmp |= value << ADC_CTRLB_FREERUN_Pos; |
| 1580 | ((Adc *)hw)->CTRLB.reg = tmp; |
| 1581 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1582 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1583 | } |
| 1584 | |
| 1585 | static inline void hri_adc_clear_CTRLB_FREERUN_bit(const void *const hw) |
| 1586 | { |
| 1587 | ADC_CRITICAL_SECTION_ENTER(); |
| 1588 | ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_FREERUN; |
| 1589 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1590 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1591 | } |
| 1592 | |
| 1593 | static inline void hri_adc_toggle_CTRLB_FREERUN_bit(const void *const hw) |
| 1594 | { |
| 1595 | ADC_CRITICAL_SECTION_ENTER(); |
| 1596 | ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_FREERUN; |
| 1597 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1598 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1599 | } |
| 1600 | |
| 1601 | static inline void hri_adc_set_CTRLB_CORREN_bit(const void *const hw) |
| 1602 | { |
| 1603 | ADC_CRITICAL_SECTION_ENTER(); |
| 1604 | ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_CORREN; |
| 1605 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1606 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1607 | } |
| 1608 | |
| 1609 | static inline bool hri_adc_get_CTRLB_CORREN_bit(const void *const hw) |
| 1610 | { |
| 1611 | uint16_t tmp; |
| 1612 | tmp = ((Adc *)hw)->CTRLB.reg; |
| 1613 | tmp = (tmp & ADC_CTRLB_CORREN) >> ADC_CTRLB_CORREN_Pos; |
| 1614 | return (bool)tmp; |
| 1615 | } |
| 1616 | |
| 1617 | static inline void hri_adc_write_CTRLB_CORREN_bit(const void *const hw, bool value) |
| 1618 | { |
| 1619 | uint16_t tmp; |
| 1620 | ADC_CRITICAL_SECTION_ENTER(); |
| 1621 | tmp = ((Adc *)hw)->CTRLB.reg; |
| 1622 | tmp &= ~ADC_CTRLB_CORREN; |
| 1623 | tmp |= value << ADC_CTRLB_CORREN_Pos; |
| 1624 | ((Adc *)hw)->CTRLB.reg = tmp; |
| 1625 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1626 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1627 | } |
| 1628 | |
| 1629 | static inline void hri_adc_clear_CTRLB_CORREN_bit(const void *const hw) |
| 1630 | { |
| 1631 | ADC_CRITICAL_SECTION_ENTER(); |
| 1632 | ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_CORREN; |
| 1633 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1634 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1635 | } |
| 1636 | |
| 1637 | static inline void hri_adc_toggle_CTRLB_CORREN_bit(const void *const hw) |
| 1638 | { |
| 1639 | ADC_CRITICAL_SECTION_ENTER(); |
| 1640 | ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_CORREN; |
| 1641 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1642 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1643 | } |
| 1644 | |
| 1645 | static inline void hri_adc_set_CTRLB_WINSS_bit(const void *const hw) |
| 1646 | { |
| 1647 | ADC_CRITICAL_SECTION_ENTER(); |
| 1648 | ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_WINSS; |
| 1649 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1650 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1651 | } |
| 1652 | |
| 1653 | static inline bool hri_adc_get_CTRLB_WINSS_bit(const void *const hw) |
| 1654 | { |
| 1655 | uint16_t tmp; |
| 1656 | tmp = ((Adc *)hw)->CTRLB.reg; |
| 1657 | tmp = (tmp & ADC_CTRLB_WINSS) >> ADC_CTRLB_WINSS_Pos; |
| 1658 | return (bool)tmp; |
| 1659 | } |
| 1660 | |
| 1661 | static inline void hri_adc_write_CTRLB_WINSS_bit(const void *const hw, bool value) |
| 1662 | { |
| 1663 | uint16_t tmp; |
| 1664 | ADC_CRITICAL_SECTION_ENTER(); |
| 1665 | tmp = ((Adc *)hw)->CTRLB.reg; |
| 1666 | tmp &= ~ADC_CTRLB_WINSS; |
| 1667 | tmp |= value << ADC_CTRLB_WINSS_Pos; |
| 1668 | ((Adc *)hw)->CTRLB.reg = tmp; |
| 1669 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1670 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1671 | } |
| 1672 | |
| 1673 | static inline void hri_adc_clear_CTRLB_WINSS_bit(const void *const hw) |
| 1674 | { |
| 1675 | ADC_CRITICAL_SECTION_ENTER(); |
| 1676 | ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_WINSS; |
| 1677 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1678 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1679 | } |
| 1680 | |
| 1681 | static inline void hri_adc_toggle_CTRLB_WINSS_bit(const void *const hw) |
| 1682 | { |
| 1683 | ADC_CRITICAL_SECTION_ENTER(); |
| 1684 | ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_WINSS; |
| 1685 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1686 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1687 | } |
| 1688 | |
| 1689 | static inline void hri_adc_set_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) |
| 1690 | { |
| 1691 | ADC_CRITICAL_SECTION_ENTER(); |
| 1692 | ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_RESSEL(mask); |
| 1693 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1694 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1695 | } |
| 1696 | |
| 1697 | static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) |
| 1698 | { |
| 1699 | uint16_t tmp; |
| 1700 | tmp = ((Adc *)hw)->CTRLB.reg; |
| 1701 | tmp = (tmp & ADC_CTRLB_RESSEL(mask)) >> ADC_CTRLB_RESSEL_Pos; |
| 1702 | return tmp; |
| 1703 | } |
| 1704 | |
| 1705 | static inline void hri_adc_write_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t data) |
| 1706 | { |
| 1707 | uint16_t tmp; |
| 1708 | ADC_CRITICAL_SECTION_ENTER(); |
| 1709 | tmp = ((Adc *)hw)->CTRLB.reg; |
| 1710 | tmp &= ~ADC_CTRLB_RESSEL_Msk; |
| 1711 | tmp |= ADC_CTRLB_RESSEL(data); |
| 1712 | ((Adc *)hw)->CTRLB.reg = tmp; |
| 1713 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1714 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1715 | } |
| 1716 | |
| 1717 | static inline void hri_adc_clear_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) |
| 1718 | { |
| 1719 | ADC_CRITICAL_SECTION_ENTER(); |
| 1720 | ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_RESSEL(mask); |
| 1721 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1722 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1723 | } |
| 1724 | |
| 1725 | static inline void hri_adc_toggle_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) |
| 1726 | { |
| 1727 | ADC_CRITICAL_SECTION_ENTER(); |
| 1728 | ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_RESSEL(mask); |
| 1729 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1730 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1731 | } |
| 1732 | |
| 1733 | static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_RESSEL_bf(const void *const hw) |
| 1734 | { |
| 1735 | uint16_t tmp; |
| 1736 | tmp = ((Adc *)hw)->CTRLB.reg; |
| 1737 | tmp = (tmp & ADC_CTRLB_RESSEL_Msk) >> ADC_CTRLB_RESSEL_Pos; |
| 1738 | return tmp; |
| 1739 | } |
| 1740 | |
| 1741 | static inline void hri_adc_set_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) |
| 1742 | { |
| 1743 | ADC_CRITICAL_SECTION_ENTER(); |
| 1744 | ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_WINMODE(mask); |
| 1745 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1746 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1747 | } |
| 1748 | |
| 1749 | static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) |
| 1750 | { |
| 1751 | uint16_t tmp; |
| 1752 | tmp = ((Adc *)hw)->CTRLB.reg; |
| 1753 | tmp = (tmp & ADC_CTRLB_WINMODE(mask)) >> ADC_CTRLB_WINMODE_Pos; |
| 1754 | return tmp; |
| 1755 | } |
| 1756 | |
| 1757 | static inline void hri_adc_write_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t data) |
| 1758 | { |
| 1759 | uint16_t tmp; |
| 1760 | ADC_CRITICAL_SECTION_ENTER(); |
| 1761 | tmp = ((Adc *)hw)->CTRLB.reg; |
| 1762 | tmp &= ~ADC_CTRLB_WINMODE_Msk; |
| 1763 | tmp |= ADC_CTRLB_WINMODE(data); |
| 1764 | ((Adc *)hw)->CTRLB.reg = tmp; |
| 1765 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1766 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1767 | } |
| 1768 | |
| 1769 | static inline void hri_adc_clear_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) |
| 1770 | { |
| 1771 | ADC_CRITICAL_SECTION_ENTER(); |
| 1772 | ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_WINMODE(mask); |
| 1773 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1774 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1775 | } |
| 1776 | |
| 1777 | static inline void hri_adc_toggle_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) |
| 1778 | { |
| 1779 | ADC_CRITICAL_SECTION_ENTER(); |
| 1780 | ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_WINMODE(mask); |
| 1781 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1782 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1783 | } |
| 1784 | |
| 1785 | static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_WINMODE_bf(const void *const hw) |
| 1786 | { |
| 1787 | uint16_t tmp; |
| 1788 | tmp = ((Adc *)hw)->CTRLB.reg; |
| 1789 | tmp = (tmp & ADC_CTRLB_WINMODE_Msk) >> ADC_CTRLB_WINMODE_Pos; |
| 1790 | return tmp; |
| 1791 | } |
| 1792 | |
| 1793 | static inline void hri_adc_set_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) |
| 1794 | { |
| 1795 | ADC_CRITICAL_SECTION_ENTER(); |
| 1796 | ((Adc *)hw)->CTRLB.reg |= mask; |
| 1797 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1798 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1799 | } |
| 1800 | |
| 1801 | static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) |
| 1802 | { |
| 1803 | uint16_t tmp; |
| 1804 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1805 | tmp = ((Adc *)hw)->CTRLB.reg; |
| 1806 | tmp &= mask; |
| 1807 | return tmp; |
| 1808 | } |
| 1809 | |
| 1810 | static inline void hri_adc_write_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t data) |
| 1811 | { |
| 1812 | ADC_CRITICAL_SECTION_ENTER(); |
| 1813 | ((Adc *)hw)->CTRLB.reg = data; |
| 1814 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1815 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1816 | } |
| 1817 | |
| 1818 | static inline void hri_adc_clear_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) |
| 1819 | { |
| 1820 | ADC_CRITICAL_SECTION_ENTER(); |
| 1821 | ((Adc *)hw)->CTRLB.reg &= ~mask; |
| 1822 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1823 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1824 | } |
| 1825 | |
| 1826 | static inline void hri_adc_toggle_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) |
| 1827 | { |
| 1828 | ADC_CRITICAL_SECTION_ENTER(); |
| 1829 | ((Adc *)hw)->CTRLB.reg ^= mask; |
| 1830 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1831 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1832 | } |
| 1833 | |
| 1834 | static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_reg(const void *const hw) |
| 1835 | { |
| 1836 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1837 | return ((Adc *)hw)->CTRLB.reg; |
| 1838 | } |
| 1839 | |
| 1840 | static inline void hri_adc_set_REFCTRL_REFCOMP_bit(const void *const hw) |
| 1841 | { |
| 1842 | ADC_CRITICAL_SECTION_ENTER(); |
| 1843 | ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFCOMP; |
| 1844 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1845 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1846 | } |
| 1847 | |
| 1848 | static inline bool hri_adc_get_REFCTRL_REFCOMP_bit(const void *const hw) |
| 1849 | { |
| 1850 | uint8_t tmp; |
| 1851 | tmp = ((Adc *)hw)->REFCTRL.reg; |
| 1852 | tmp = (tmp & ADC_REFCTRL_REFCOMP) >> ADC_REFCTRL_REFCOMP_Pos; |
| 1853 | return (bool)tmp; |
| 1854 | } |
| 1855 | |
| 1856 | static inline void hri_adc_write_REFCTRL_REFCOMP_bit(const void *const hw, bool value) |
| 1857 | { |
| 1858 | uint8_t tmp; |
| 1859 | ADC_CRITICAL_SECTION_ENTER(); |
| 1860 | tmp = ((Adc *)hw)->REFCTRL.reg; |
| 1861 | tmp &= ~ADC_REFCTRL_REFCOMP; |
| 1862 | tmp |= value << ADC_REFCTRL_REFCOMP_Pos; |
| 1863 | ((Adc *)hw)->REFCTRL.reg = tmp; |
| 1864 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1865 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1866 | } |
| 1867 | |
| 1868 | static inline void hri_adc_clear_REFCTRL_REFCOMP_bit(const void *const hw) |
| 1869 | { |
| 1870 | ADC_CRITICAL_SECTION_ENTER(); |
| 1871 | ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFCOMP; |
| 1872 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1873 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1874 | } |
| 1875 | |
| 1876 | static inline void hri_adc_toggle_REFCTRL_REFCOMP_bit(const void *const hw) |
| 1877 | { |
| 1878 | ADC_CRITICAL_SECTION_ENTER(); |
| 1879 | ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFCOMP; |
| 1880 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1881 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1882 | } |
| 1883 | |
| 1884 | static inline void hri_adc_set_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) |
| 1885 | { |
| 1886 | ADC_CRITICAL_SECTION_ENTER(); |
| 1887 | ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFSEL(mask); |
| 1888 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1889 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1890 | } |
| 1891 | |
| 1892 | static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) |
| 1893 | { |
| 1894 | uint8_t tmp; |
| 1895 | tmp = ((Adc *)hw)->REFCTRL.reg; |
| 1896 | tmp = (tmp & ADC_REFCTRL_REFSEL(mask)) >> ADC_REFCTRL_REFSEL_Pos; |
| 1897 | return tmp; |
| 1898 | } |
| 1899 | |
| 1900 | static inline void hri_adc_write_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t data) |
| 1901 | { |
| 1902 | uint8_t tmp; |
| 1903 | ADC_CRITICAL_SECTION_ENTER(); |
| 1904 | tmp = ((Adc *)hw)->REFCTRL.reg; |
| 1905 | tmp &= ~ADC_REFCTRL_REFSEL_Msk; |
| 1906 | tmp |= ADC_REFCTRL_REFSEL(data); |
| 1907 | ((Adc *)hw)->REFCTRL.reg = tmp; |
| 1908 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1909 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1910 | } |
| 1911 | |
| 1912 | static inline void hri_adc_clear_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) |
| 1913 | { |
| 1914 | ADC_CRITICAL_SECTION_ENTER(); |
| 1915 | ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFSEL(mask); |
| 1916 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1917 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1918 | } |
| 1919 | |
| 1920 | static inline void hri_adc_toggle_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) |
| 1921 | { |
| 1922 | ADC_CRITICAL_SECTION_ENTER(); |
| 1923 | ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFSEL(mask); |
| 1924 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1925 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1926 | } |
| 1927 | |
| 1928 | static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_REFSEL_bf(const void *const hw) |
| 1929 | { |
| 1930 | uint8_t tmp; |
| 1931 | tmp = ((Adc *)hw)->REFCTRL.reg; |
| 1932 | tmp = (tmp & ADC_REFCTRL_REFSEL_Msk) >> ADC_REFCTRL_REFSEL_Pos; |
| 1933 | return tmp; |
| 1934 | } |
| 1935 | |
| 1936 | static inline void hri_adc_set_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) |
| 1937 | { |
| 1938 | ADC_CRITICAL_SECTION_ENTER(); |
| 1939 | ((Adc *)hw)->REFCTRL.reg |= mask; |
| 1940 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1941 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1942 | } |
| 1943 | |
| 1944 | static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) |
| 1945 | { |
| 1946 | uint8_t tmp; |
| 1947 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1948 | tmp = ((Adc *)hw)->REFCTRL.reg; |
| 1949 | tmp &= mask; |
| 1950 | return tmp; |
| 1951 | } |
| 1952 | |
| 1953 | static inline void hri_adc_write_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t data) |
| 1954 | { |
| 1955 | ADC_CRITICAL_SECTION_ENTER(); |
| 1956 | ((Adc *)hw)->REFCTRL.reg = data; |
| 1957 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1958 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1959 | } |
| 1960 | |
| 1961 | static inline void hri_adc_clear_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) |
| 1962 | { |
| 1963 | ADC_CRITICAL_SECTION_ENTER(); |
| 1964 | ((Adc *)hw)->REFCTRL.reg &= ~mask; |
| 1965 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1966 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1967 | } |
| 1968 | |
| 1969 | static inline void hri_adc_toggle_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) |
| 1970 | { |
| 1971 | ADC_CRITICAL_SECTION_ENTER(); |
| 1972 | ((Adc *)hw)->REFCTRL.reg ^= mask; |
| 1973 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1974 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1975 | } |
| 1976 | |
| 1977 | static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_reg(const void *const hw) |
| 1978 | { |
| 1979 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1980 | return ((Adc *)hw)->REFCTRL.reg; |
| 1981 | } |
| 1982 | |
| 1983 | static inline void hri_adc_set_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) |
| 1984 | { |
| 1985 | ADC_CRITICAL_SECTION_ENTER(); |
| 1986 | ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_SAMPLENUM(mask); |
| 1987 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 1988 | ADC_CRITICAL_SECTION_LEAVE(); |
| 1989 | } |
| 1990 | |
| 1991 | static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) |
| 1992 | { |
| 1993 | uint8_t tmp; |
| 1994 | tmp = ((Adc *)hw)->AVGCTRL.reg; |
| 1995 | tmp = (tmp & ADC_AVGCTRL_SAMPLENUM(mask)) >> ADC_AVGCTRL_SAMPLENUM_Pos; |
| 1996 | return tmp; |
| 1997 | } |
| 1998 | |
| 1999 | static inline void hri_adc_write_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t data) |
| 2000 | { |
| 2001 | uint8_t tmp; |
| 2002 | ADC_CRITICAL_SECTION_ENTER(); |
| 2003 | tmp = ((Adc *)hw)->AVGCTRL.reg; |
| 2004 | tmp &= ~ADC_AVGCTRL_SAMPLENUM_Msk; |
| 2005 | tmp |= ADC_AVGCTRL_SAMPLENUM(data); |
| 2006 | ((Adc *)hw)->AVGCTRL.reg = tmp; |
| 2007 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2008 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2009 | } |
| 2010 | |
| 2011 | static inline void hri_adc_clear_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) |
| 2012 | { |
| 2013 | ADC_CRITICAL_SECTION_ENTER(); |
| 2014 | ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_SAMPLENUM(mask); |
| 2015 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2016 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2017 | } |
| 2018 | |
| 2019 | static inline void hri_adc_toggle_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) |
| 2020 | { |
| 2021 | ADC_CRITICAL_SECTION_ENTER(); |
| 2022 | ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_SAMPLENUM(mask); |
| 2023 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2024 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2025 | } |
| 2026 | |
| 2027 | static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_SAMPLENUM_bf(const void *const hw) |
| 2028 | { |
| 2029 | uint8_t tmp; |
| 2030 | tmp = ((Adc *)hw)->AVGCTRL.reg; |
| 2031 | tmp = (tmp & ADC_AVGCTRL_SAMPLENUM_Msk) >> ADC_AVGCTRL_SAMPLENUM_Pos; |
| 2032 | return tmp; |
| 2033 | } |
| 2034 | |
| 2035 | static inline void hri_adc_set_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) |
| 2036 | { |
| 2037 | ADC_CRITICAL_SECTION_ENTER(); |
| 2038 | ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_ADJRES(mask); |
| 2039 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2040 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2041 | } |
| 2042 | |
| 2043 | static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) |
| 2044 | { |
| 2045 | uint8_t tmp; |
| 2046 | tmp = ((Adc *)hw)->AVGCTRL.reg; |
| 2047 | tmp = (tmp & ADC_AVGCTRL_ADJRES(mask)) >> ADC_AVGCTRL_ADJRES_Pos; |
| 2048 | return tmp; |
| 2049 | } |
| 2050 | |
| 2051 | static inline void hri_adc_write_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t data) |
| 2052 | { |
| 2053 | uint8_t tmp; |
| 2054 | ADC_CRITICAL_SECTION_ENTER(); |
| 2055 | tmp = ((Adc *)hw)->AVGCTRL.reg; |
| 2056 | tmp &= ~ADC_AVGCTRL_ADJRES_Msk; |
| 2057 | tmp |= ADC_AVGCTRL_ADJRES(data); |
| 2058 | ((Adc *)hw)->AVGCTRL.reg = tmp; |
| 2059 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2060 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2061 | } |
| 2062 | |
| 2063 | static inline void hri_adc_clear_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) |
| 2064 | { |
| 2065 | ADC_CRITICAL_SECTION_ENTER(); |
| 2066 | ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_ADJRES(mask); |
| 2067 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2068 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2069 | } |
| 2070 | |
| 2071 | static inline void hri_adc_toggle_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) |
| 2072 | { |
| 2073 | ADC_CRITICAL_SECTION_ENTER(); |
| 2074 | ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_ADJRES(mask); |
| 2075 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2076 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2077 | } |
| 2078 | |
| 2079 | static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_ADJRES_bf(const void *const hw) |
| 2080 | { |
| 2081 | uint8_t tmp; |
| 2082 | tmp = ((Adc *)hw)->AVGCTRL.reg; |
| 2083 | tmp = (tmp & ADC_AVGCTRL_ADJRES_Msk) >> ADC_AVGCTRL_ADJRES_Pos; |
| 2084 | return tmp; |
| 2085 | } |
| 2086 | |
| 2087 | static inline void hri_adc_set_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) |
| 2088 | { |
| 2089 | ADC_CRITICAL_SECTION_ENTER(); |
| 2090 | ((Adc *)hw)->AVGCTRL.reg |= mask; |
| 2091 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2092 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2093 | } |
| 2094 | |
| 2095 | static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) |
| 2096 | { |
| 2097 | uint8_t tmp; |
| 2098 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2099 | tmp = ((Adc *)hw)->AVGCTRL.reg; |
| 2100 | tmp &= mask; |
| 2101 | return tmp; |
| 2102 | } |
| 2103 | |
| 2104 | static inline void hri_adc_write_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t data) |
| 2105 | { |
| 2106 | ADC_CRITICAL_SECTION_ENTER(); |
| 2107 | ((Adc *)hw)->AVGCTRL.reg = data; |
| 2108 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2109 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2110 | } |
| 2111 | |
| 2112 | static inline void hri_adc_clear_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) |
| 2113 | { |
| 2114 | ADC_CRITICAL_SECTION_ENTER(); |
| 2115 | ((Adc *)hw)->AVGCTRL.reg &= ~mask; |
| 2116 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2117 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2118 | } |
| 2119 | |
| 2120 | static inline void hri_adc_toggle_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) |
| 2121 | { |
| 2122 | ADC_CRITICAL_SECTION_ENTER(); |
| 2123 | ((Adc *)hw)->AVGCTRL.reg ^= mask; |
| 2124 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2125 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2126 | } |
| 2127 | |
| 2128 | static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_reg(const void *const hw) |
| 2129 | { |
| 2130 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2131 | return ((Adc *)hw)->AVGCTRL.reg; |
| 2132 | } |
| 2133 | |
| 2134 | static inline void hri_adc_set_SAMPCTRL_OFFCOMP_bit(const void *const hw) |
| 2135 | { |
| 2136 | ADC_CRITICAL_SECTION_ENTER(); |
| 2137 | ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_OFFCOMP; |
| 2138 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2139 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2140 | } |
| 2141 | |
| 2142 | static inline bool hri_adc_get_SAMPCTRL_OFFCOMP_bit(const void *const hw) |
| 2143 | { |
| 2144 | uint8_t tmp; |
| 2145 | tmp = ((Adc *)hw)->SAMPCTRL.reg; |
| 2146 | tmp = (tmp & ADC_SAMPCTRL_OFFCOMP) >> ADC_SAMPCTRL_OFFCOMP_Pos; |
| 2147 | return (bool)tmp; |
| 2148 | } |
| 2149 | |
| 2150 | static inline void hri_adc_write_SAMPCTRL_OFFCOMP_bit(const void *const hw, bool value) |
| 2151 | { |
| 2152 | uint8_t tmp; |
| 2153 | ADC_CRITICAL_SECTION_ENTER(); |
| 2154 | tmp = ((Adc *)hw)->SAMPCTRL.reg; |
| 2155 | tmp &= ~ADC_SAMPCTRL_OFFCOMP; |
| 2156 | tmp |= value << ADC_SAMPCTRL_OFFCOMP_Pos; |
| 2157 | ((Adc *)hw)->SAMPCTRL.reg = tmp; |
| 2158 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2159 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2160 | } |
| 2161 | |
| 2162 | static inline void hri_adc_clear_SAMPCTRL_OFFCOMP_bit(const void *const hw) |
| 2163 | { |
| 2164 | ADC_CRITICAL_SECTION_ENTER(); |
| 2165 | ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_OFFCOMP; |
| 2166 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2167 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2168 | } |
| 2169 | |
| 2170 | static inline void hri_adc_toggle_SAMPCTRL_OFFCOMP_bit(const void *const hw) |
| 2171 | { |
| 2172 | ADC_CRITICAL_SECTION_ENTER(); |
| 2173 | ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_OFFCOMP; |
| 2174 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2175 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2176 | } |
| 2177 | |
| 2178 | static inline void hri_adc_set_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) |
| 2179 | { |
| 2180 | ADC_CRITICAL_SECTION_ENTER(); |
| 2181 | ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_SAMPLEN(mask); |
| 2182 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2183 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2184 | } |
| 2185 | |
| 2186 | static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) |
| 2187 | { |
| 2188 | uint8_t tmp; |
| 2189 | tmp = ((Adc *)hw)->SAMPCTRL.reg; |
| 2190 | tmp = (tmp & ADC_SAMPCTRL_SAMPLEN(mask)) >> ADC_SAMPCTRL_SAMPLEN_Pos; |
| 2191 | return tmp; |
| 2192 | } |
| 2193 | |
| 2194 | static inline void hri_adc_write_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t data) |
| 2195 | { |
| 2196 | uint8_t tmp; |
| 2197 | ADC_CRITICAL_SECTION_ENTER(); |
| 2198 | tmp = ((Adc *)hw)->SAMPCTRL.reg; |
| 2199 | tmp &= ~ADC_SAMPCTRL_SAMPLEN_Msk; |
| 2200 | tmp |= ADC_SAMPCTRL_SAMPLEN(data); |
| 2201 | ((Adc *)hw)->SAMPCTRL.reg = tmp; |
| 2202 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2203 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2204 | } |
| 2205 | |
| 2206 | static inline void hri_adc_clear_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) |
| 2207 | { |
| 2208 | ADC_CRITICAL_SECTION_ENTER(); |
| 2209 | ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_SAMPLEN(mask); |
| 2210 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2211 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2212 | } |
| 2213 | |
| 2214 | static inline void hri_adc_toggle_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) |
| 2215 | { |
| 2216 | ADC_CRITICAL_SECTION_ENTER(); |
| 2217 | ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_SAMPLEN(mask); |
| 2218 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2219 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2220 | } |
| 2221 | |
| 2222 | static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_SAMPLEN_bf(const void *const hw) |
| 2223 | { |
| 2224 | uint8_t tmp; |
| 2225 | tmp = ((Adc *)hw)->SAMPCTRL.reg; |
| 2226 | tmp = (tmp & ADC_SAMPCTRL_SAMPLEN_Msk) >> ADC_SAMPCTRL_SAMPLEN_Pos; |
| 2227 | return tmp; |
| 2228 | } |
| 2229 | |
| 2230 | static inline void hri_adc_set_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) |
| 2231 | { |
| 2232 | ADC_CRITICAL_SECTION_ENTER(); |
| 2233 | ((Adc *)hw)->SAMPCTRL.reg |= mask; |
| 2234 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2235 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2236 | } |
| 2237 | |
| 2238 | static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) |
| 2239 | { |
| 2240 | uint8_t tmp; |
| 2241 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2242 | tmp = ((Adc *)hw)->SAMPCTRL.reg; |
| 2243 | tmp &= mask; |
| 2244 | return tmp; |
| 2245 | } |
| 2246 | |
| 2247 | static inline void hri_adc_write_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t data) |
| 2248 | { |
| 2249 | ADC_CRITICAL_SECTION_ENTER(); |
| 2250 | ((Adc *)hw)->SAMPCTRL.reg = data; |
| 2251 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2252 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2253 | } |
| 2254 | |
| 2255 | static inline void hri_adc_clear_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) |
| 2256 | { |
| 2257 | ADC_CRITICAL_SECTION_ENTER(); |
| 2258 | ((Adc *)hw)->SAMPCTRL.reg &= ~mask; |
| 2259 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2260 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2261 | } |
| 2262 | |
| 2263 | static inline void hri_adc_toggle_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) |
| 2264 | { |
| 2265 | ADC_CRITICAL_SECTION_ENTER(); |
| 2266 | ((Adc *)hw)->SAMPCTRL.reg ^= mask; |
| 2267 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2268 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2269 | } |
| 2270 | |
| 2271 | static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_reg(const void *const hw) |
| 2272 | { |
| 2273 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2274 | return ((Adc *)hw)->SAMPCTRL.reg; |
| 2275 | } |
| 2276 | |
| 2277 | static inline void hri_adc_set_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) |
| 2278 | { |
| 2279 | ADC_CRITICAL_SECTION_ENTER(); |
| 2280 | ((Adc *)hw)->WINLT.reg |= ADC_WINLT_WINLT(mask); |
| 2281 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); |
| 2282 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2283 | } |
| 2284 | |
| 2285 | static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) |
| 2286 | { |
| 2287 | uint16_t tmp; |
| 2288 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); |
| 2289 | tmp = ((Adc *)hw)->WINLT.reg; |
| 2290 | tmp = (tmp & ADC_WINLT_WINLT(mask)) >> ADC_WINLT_WINLT_Pos; |
| 2291 | return tmp; |
| 2292 | } |
| 2293 | |
| 2294 | static inline void hri_adc_write_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t data) |
| 2295 | { |
| 2296 | uint16_t tmp; |
| 2297 | ADC_CRITICAL_SECTION_ENTER(); |
| 2298 | tmp = ((Adc *)hw)->WINLT.reg; |
| 2299 | tmp &= ~ADC_WINLT_WINLT_Msk; |
| 2300 | tmp |= ADC_WINLT_WINLT(data); |
| 2301 | ((Adc *)hw)->WINLT.reg = tmp; |
| 2302 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); |
| 2303 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2304 | } |
| 2305 | |
| 2306 | static inline void hri_adc_clear_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) |
| 2307 | { |
| 2308 | ADC_CRITICAL_SECTION_ENTER(); |
| 2309 | ((Adc *)hw)->WINLT.reg &= ~ADC_WINLT_WINLT(mask); |
| 2310 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); |
| 2311 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2312 | } |
| 2313 | |
| 2314 | static inline void hri_adc_toggle_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) |
| 2315 | { |
| 2316 | ADC_CRITICAL_SECTION_ENTER(); |
| 2317 | ((Adc *)hw)->WINLT.reg ^= ADC_WINLT_WINLT(mask); |
| 2318 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); |
| 2319 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2320 | } |
| 2321 | |
| 2322 | static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_WINLT_bf(const void *const hw) |
| 2323 | { |
| 2324 | uint16_t tmp; |
| 2325 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); |
| 2326 | tmp = ((Adc *)hw)->WINLT.reg; |
| 2327 | tmp = (tmp & ADC_WINLT_WINLT_Msk) >> ADC_WINLT_WINLT_Pos; |
| 2328 | return tmp; |
| 2329 | } |
| 2330 | |
| 2331 | static inline void hri_adc_set_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) |
| 2332 | { |
| 2333 | ADC_CRITICAL_SECTION_ENTER(); |
| 2334 | ((Adc *)hw)->WINLT.reg |= mask; |
| 2335 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); |
| 2336 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2337 | } |
| 2338 | |
| 2339 | static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) |
| 2340 | { |
| 2341 | uint16_t tmp; |
| 2342 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); |
| 2343 | tmp = ((Adc *)hw)->WINLT.reg; |
| 2344 | tmp &= mask; |
| 2345 | return tmp; |
| 2346 | } |
| 2347 | |
| 2348 | static inline void hri_adc_write_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t data) |
| 2349 | { |
| 2350 | ADC_CRITICAL_SECTION_ENTER(); |
| 2351 | ((Adc *)hw)->WINLT.reg = data; |
| 2352 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); |
| 2353 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2354 | } |
| 2355 | |
| 2356 | static inline void hri_adc_clear_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) |
| 2357 | { |
| 2358 | ADC_CRITICAL_SECTION_ENTER(); |
| 2359 | ((Adc *)hw)->WINLT.reg &= ~mask; |
| 2360 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); |
| 2361 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2362 | } |
| 2363 | |
| 2364 | static inline void hri_adc_toggle_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) |
| 2365 | { |
| 2366 | ADC_CRITICAL_SECTION_ENTER(); |
| 2367 | ((Adc *)hw)->WINLT.reg ^= mask; |
| 2368 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); |
| 2369 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2370 | } |
| 2371 | |
| 2372 | static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_reg(const void *const hw) |
| 2373 | { |
| 2374 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); |
| 2375 | return ((Adc *)hw)->WINLT.reg; |
| 2376 | } |
| 2377 | |
| 2378 | static inline void hri_adc_set_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) |
| 2379 | { |
| 2380 | ADC_CRITICAL_SECTION_ENTER(); |
| 2381 | ((Adc *)hw)->WINUT.reg |= ADC_WINUT_WINUT(mask); |
| 2382 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); |
| 2383 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2384 | } |
| 2385 | |
| 2386 | static inline hri_adc_winut_reg_t hri_adc_get_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) |
| 2387 | { |
| 2388 | uint16_t tmp; |
| 2389 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); |
| 2390 | tmp = ((Adc *)hw)->WINUT.reg; |
| 2391 | tmp = (tmp & ADC_WINUT_WINUT(mask)) >> ADC_WINUT_WINUT_Pos; |
| 2392 | return tmp; |
| 2393 | } |
| 2394 | |
| 2395 | static inline void hri_adc_write_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t data) |
| 2396 | { |
| 2397 | uint16_t tmp; |
| 2398 | ADC_CRITICAL_SECTION_ENTER(); |
| 2399 | tmp = ((Adc *)hw)->WINUT.reg; |
| 2400 | tmp &= ~ADC_WINUT_WINUT_Msk; |
| 2401 | tmp |= ADC_WINUT_WINUT(data); |
| 2402 | ((Adc *)hw)->WINUT.reg = tmp; |
| 2403 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); |
| 2404 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2405 | } |
| 2406 | |
| 2407 | static inline void hri_adc_clear_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) |
| 2408 | { |
| 2409 | ADC_CRITICAL_SECTION_ENTER(); |
| 2410 | ((Adc *)hw)->WINUT.reg &= ~ADC_WINUT_WINUT(mask); |
| 2411 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); |
| 2412 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2413 | } |
| 2414 | |
| 2415 | static inline void hri_adc_toggle_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) |
| 2416 | { |
| 2417 | ADC_CRITICAL_SECTION_ENTER(); |
| 2418 | ((Adc *)hw)->WINUT.reg ^= ADC_WINUT_WINUT(mask); |
| 2419 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); |
| 2420 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2421 | } |
| 2422 | |
| 2423 | static inline hri_adc_winut_reg_t hri_adc_read_WINUT_WINUT_bf(const void *const hw) |
| 2424 | { |
| 2425 | uint16_t tmp; |
| 2426 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); |
| 2427 | tmp = ((Adc *)hw)->WINUT.reg; |
| 2428 | tmp = (tmp & ADC_WINUT_WINUT_Msk) >> ADC_WINUT_WINUT_Pos; |
| 2429 | return tmp; |
| 2430 | } |
| 2431 | |
| 2432 | static inline void hri_adc_set_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) |
| 2433 | { |
| 2434 | ADC_CRITICAL_SECTION_ENTER(); |
| 2435 | ((Adc *)hw)->WINUT.reg |= mask; |
| 2436 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); |
| 2437 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2438 | } |
| 2439 | |
| 2440 | static inline hri_adc_winut_reg_t hri_adc_get_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) |
| 2441 | { |
| 2442 | uint16_t tmp; |
| 2443 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); |
| 2444 | tmp = ((Adc *)hw)->WINUT.reg; |
| 2445 | tmp &= mask; |
| 2446 | return tmp; |
| 2447 | } |
| 2448 | |
| 2449 | static inline void hri_adc_write_WINUT_reg(const void *const hw, hri_adc_winut_reg_t data) |
| 2450 | { |
| 2451 | ADC_CRITICAL_SECTION_ENTER(); |
| 2452 | ((Adc *)hw)->WINUT.reg = data; |
| 2453 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); |
| 2454 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2455 | } |
| 2456 | |
| 2457 | static inline void hri_adc_clear_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) |
| 2458 | { |
| 2459 | ADC_CRITICAL_SECTION_ENTER(); |
| 2460 | ((Adc *)hw)->WINUT.reg &= ~mask; |
| 2461 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); |
| 2462 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2463 | } |
| 2464 | |
| 2465 | static inline void hri_adc_toggle_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) |
| 2466 | { |
| 2467 | ADC_CRITICAL_SECTION_ENTER(); |
| 2468 | ((Adc *)hw)->WINUT.reg ^= mask; |
| 2469 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); |
| 2470 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2471 | } |
| 2472 | |
| 2473 | static inline hri_adc_winut_reg_t hri_adc_read_WINUT_reg(const void *const hw) |
| 2474 | { |
| 2475 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); |
| 2476 | return ((Adc *)hw)->WINUT.reg; |
| 2477 | } |
| 2478 | |
| 2479 | static inline void hri_adc_set_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) |
| 2480 | { |
| 2481 | ADC_CRITICAL_SECTION_ENTER(); |
| 2482 | ((Adc *)hw)->GAINCORR.reg |= ADC_GAINCORR_GAINCORR(mask); |
| 2483 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); |
| 2484 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2485 | } |
| 2486 | |
| 2487 | static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) |
| 2488 | { |
| 2489 | uint16_t tmp; |
| 2490 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); |
| 2491 | tmp = ((Adc *)hw)->GAINCORR.reg; |
| 2492 | tmp = (tmp & ADC_GAINCORR_GAINCORR(mask)) >> ADC_GAINCORR_GAINCORR_Pos; |
| 2493 | return tmp; |
| 2494 | } |
| 2495 | |
| 2496 | static inline void hri_adc_write_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t data) |
| 2497 | { |
| 2498 | uint16_t tmp; |
| 2499 | ADC_CRITICAL_SECTION_ENTER(); |
| 2500 | tmp = ((Adc *)hw)->GAINCORR.reg; |
| 2501 | tmp &= ~ADC_GAINCORR_GAINCORR_Msk; |
| 2502 | tmp |= ADC_GAINCORR_GAINCORR(data); |
| 2503 | ((Adc *)hw)->GAINCORR.reg = tmp; |
| 2504 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); |
| 2505 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2506 | } |
| 2507 | |
| 2508 | static inline void hri_adc_clear_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) |
| 2509 | { |
| 2510 | ADC_CRITICAL_SECTION_ENTER(); |
| 2511 | ((Adc *)hw)->GAINCORR.reg &= ~ADC_GAINCORR_GAINCORR(mask); |
| 2512 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); |
| 2513 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2514 | } |
| 2515 | |
| 2516 | static inline void hri_adc_toggle_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) |
| 2517 | { |
| 2518 | ADC_CRITICAL_SECTION_ENTER(); |
| 2519 | ((Adc *)hw)->GAINCORR.reg ^= ADC_GAINCORR_GAINCORR(mask); |
| 2520 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); |
| 2521 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2522 | } |
| 2523 | |
| 2524 | static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_GAINCORR_bf(const void *const hw) |
| 2525 | { |
| 2526 | uint16_t tmp; |
| 2527 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); |
| 2528 | tmp = ((Adc *)hw)->GAINCORR.reg; |
| 2529 | tmp = (tmp & ADC_GAINCORR_GAINCORR_Msk) >> ADC_GAINCORR_GAINCORR_Pos; |
| 2530 | return tmp; |
| 2531 | } |
| 2532 | |
| 2533 | static inline void hri_adc_set_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) |
| 2534 | { |
| 2535 | ADC_CRITICAL_SECTION_ENTER(); |
| 2536 | ((Adc *)hw)->GAINCORR.reg |= mask; |
| 2537 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); |
| 2538 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2539 | } |
| 2540 | |
| 2541 | static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) |
| 2542 | { |
| 2543 | uint16_t tmp; |
| 2544 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); |
| 2545 | tmp = ((Adc *)hw)->GAINCORR.reg; |
| 2546 | tmp &= mask; |
| 2547 | return tmp; |
| 2548 | } |
| 2549 | |
| 2550 | static inline void hri_adc_write_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t data) |
| 2551 | { |
| 2552 | ADC_CRITICAL_SECTION_ENTER(); |
| 2553 | ((Adc *)hw)->GAINCORR.reg = data; |
| 2554 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); |
| 2555 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2556 | } |
| 2557 | |
| 2558 | static inline void hri_adc_clear_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) |
| 2559 | { |
| 2560 | ADC_CRITICAL_SECTION_ENTER(); |
| 2561 | ((Adc *)hw)->GAINCORR.reg &= ~mask; |
| 2562 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); |
| 2563 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2564 | } |
| 2565 | |
| 2566 | static inline void hri_adc_toggle_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) |
| 2567 | { |
| 2568 | ADC_CRITICAL_SECTION_ENTER(); |
| 2569 | ((Adc *)hw)->GAINCORR.reg ^= mask; |
| 2570 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); |
| 2571 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2572 | } |
| 2573 | |
| 2574 | static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_reg(const void *const hw) |
| 2575 | { |
| 2576 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); |
| 2577 | return ((Adc *)hw)->GAINCORR.reg; |
| 2578 | } |
| 2579 | |
| 2580 | static inline void hri_adc_set_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) |
| 2581 | { |
| 2582 | ADC_CRITICAL_SECTION_ENTER(); |
| 2583 | ((Adc *)hw)->OFFSETCORR.reg |= ADC_OFFSETCORR_OFFSETCORR(mask); |
| 2584 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); |
| 2585 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2586 | } |
| 2587 | |
| 2588 | static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_OFFSETCORR_bf(const void *const hw, |
| 2589 | hri_adc_offsetcorr_reg_t mask) |
| 2590 | { |
| 2591 | uint16_t tmp; |
| 2592 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); |
| 2593 | tmp = ((Adc *)hw)->OFFSETCORR.reg; |
| 2594 | tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR(mask)) >> ADC_OFFSETCORR_OFFSETCORR_Pos; |
| 2595 | return tmp; |
| 2596 | } |
| 2597 | |
| 2598 | static inline void hri_adc_write_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t data) |
| 2599 | { |
| 2600 | uint16_t tmp; |
| 2601 | ADC_CRITICAL_SECTION_ENTER(); |
| 2602 | tmp = ((Adc *)hw)->OFFSETCORR.reg; |
| 2603 | tmp &= ~ADC_OFFSETCORR_OFFSETCORR_Msk; |
| 2604 | tmp |= ADC_OFFSETCORR_OFFSETCORR(data); |
| 2605 | ((Adc *)hw)->OFFSETCORR.reg = tmp; |
| 2606 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); |
| 2607 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2608 | } |
| 2609 | |
| 2610 | static inline void hri_adc_clear_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) |
| 2611 | { |
| 2612 | ADC_CRITICAL_SECTION_ENTER(); |
| 2613 | ((Adc *)hw)->OFFSETCORR.reg &= ~ADC_OFFSETCORR_OFFSETCORR(mask); |
| 2614 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); |
| 2615 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2616 | } |
| 2617 | |
| 2618 | static inline void hri_adc_toggle_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) |
| 2619 | { |
| 2620 | ADC_CRITICAL_SECTION_ENTER(); |
| 2621 | ((Adc *)hw)->OFFSETCORR.reg ^= ADC_OFFSETCORR_OFFSETCORR(mask); |
| 2622 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); |
| 2623 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2624 | } |
| 2625 | |
| 2626 | static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_OFFSETCORR_bf(const void *const hw) |
| 2627 | { |
| 2628 | uint16_t tmp; |
| 2629 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); |
| 2630 | tmp = ((Adc *)hw)->OFFSETCORR.reg; |
| 2631 | tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR_Msk) >> ADC_OFFSETCORR_OFFSETCORR_Pos; |
| 2632 | return tmp; |
| 2633 | } |
| 2634 | |
| 2635 | static inline void hri_adc_set_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) |
| 2636 | { |
| 2637 | ADC_CRITICAL_SECTION_ENTER(); |
| 2638 | ((Adc *)hw)->OFFSETCORR.reg |= mask; |
| 2639 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); |
| 2640 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2641 | } |
| 2642 | |
| 2643 | static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) |
| 2644 | { |
| 2645 | uint16_t tmp; |
| 2646 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); |
| 2647 | tmp = ((Adc *)hw)->OFFSETCORR.reg; |
| 2648 | tmp &= mask; |
| 2649 | return tmp; |
| 2650 | } |
| 2651 | |
| 2652 | static inline void hri_adc_write_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t data) |
| 2653 | { |
| 2654 | ADC_CRITICAL_SECTION_ENTER(); |
| 2655 | ((Adc *)hw)->OFFSETCORR.reg = data; |
| 2656 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); |
| 2657 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2658 | } |
| 2659 | |
| 2660 | static inline void hri_adc_clear_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) |
| 2661 | { |
| 2662 | ADC_CRITICAL_SECTION_ENTER(); |
| 2663 | ((Adc *)hw)->OFFSETCORR.reg &= ~mask; |
| 2664 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); |
| 2665 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2666 | } |
| 2667 | |
| 2668 | static inline void hri_adc_toggle_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) |
| 2669 | { |
| 2670 | ADC_CRITICAL_SECTION_ENTER(); |
| 2671 | ((Adc *)hw)->OFFSETCORR.reg ^= mask; |
| 2672 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); |
| 2673 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2674 | } |
| 2675 | |
| 2676 | static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_reg(const void *const hw) |
| 2677 | { |
| 2678 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); |
| 2679 | return ((Adc *)hw)->OFFSETCORR.reg; |
| 2680 | } |
| 2681 | |
| 2682 | static inline void hri_adc_set_SWTRIG_FLUSH_bit(const void *const hw) |
| 2683 | { |
| 2684 | ADC_CRITICAL_SECTION_ENTER(); |
| 2685 | ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_FLUSH; |
| 2686 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2687 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2688 | } |
| 2689 | |
| 2690 | static inline bool hri_adc_get_SWTRIG_FLUSH_bit(const void *const hw) |
| 2691 | { |
| 2692 | uint8_t tmp; |
| 2693 | tmp = ((Adc *)hw)->SWTRIG.reg; |
| 2694 | tmp = (tmp & ADC_SWTRIG_FLUSH) >> ADC_SWTRIG_FLUSH_Pos; |
| 2695 | return (bool)tmp; |
| 2696 | } |
| 2697 | |
| 2698 | static inline void hri_adc_write_SWTRIG_FLUSH_bit(const void *const hw, bool value) |
| 2699 | { |
| 2700 | uint8_t tmp; |
| 2701 | ADC_CRITICAL_SECTION_ENTER(); |
| 2702 | tmp = ((Adc *)hw)->SWTRIG.reg; |
| 2703 | tmp &= ~ADC_SWTRIG_FLUSH; |
| 2704 | tmp |= value << ADC_SWTRIG_FLUSH_Pos; |
| 2705 | ((Adc *)hw)->SWTRIG.reg = tmp; |
| 2706 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2707 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2708 | } |
| 2709 | |
| 2710 | static inline void hri_adc_clear_SWTRIG_FLUSH_bit(const void *const hw) |
| 2711 | { |
| 2712 | ADC_CRITICAL_SECTION_ENTER(); |
| 2713 | ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_FLUSH; |
| 2714 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2715 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2716 | } |
| 2717 | |
| 2718 | static inline void hri_adc_toggle_SWTRIG_FLUSH_bit(const void *const hw) |
| 2719 | { |
| 2720 | ADC_CRITICAL_SECTION_ENTER(); |
| 2721 | ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_FLUSH; |
| 2722 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2723 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2724 | } |
| 2725 | |
| 2726 | static inline void hri_adc_set_SWTRIG_START_bit(const void *const hw) |
| 2727 | { |
| 2728 | ADC_CRITICAL_SECTION_ENTER(); |
| 2729 | ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_START; |
| 2730 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2731 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2732 | } |
| 2733 | |
| 2734 | static inline bool hri_adc_get_SWTRIG_START_bit(const void *const hw) |
| 2735 | { |
| 2736 | uint8_t tmp; |
| 2737 | tmp = ((Adc *)hw)->SWTRIG.reg; |
| 2738 | tmp = (tmp & ADC_SWTRIG_START) >> ADC_SWTRIG_START_Pos; |
| 2739 | return (bool)tmp; |
| 2740 | } |
| 2741 | |
| 2742 | static inline void hri_adc_write_SWTRIG_START_bit(const void *const hw, bool value) |
| 2743 | { |
| 2744 | uint8_t tmp; |
| 2745 | ADC_CRITICAL_SECTION_ENTER(); |
| 2746 | tmp = ((Adc *)hw)->SWTRIG.reg; |
| 2747 | tmp &= ~ADC_SWTRIG_START; |
| 2748 | tmp |= value << ADC_SWTRIG_START_Pos; |
| 2749 | ((Adc *)hw)->SWTRIG.reg = tmp; |
| 2750 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2751 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2752 | } |
| 2753 | |
| 2754 | static inline void hri_adc_clear_SWTRIG_START_bit(const void *const hw) |
| 2755 | { |
| 2756 | ADC_CRITICAL_SECTION_ENTER(); |
| 2757 | ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_START; |
| 2758 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2759 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2760 | } |
| 2761 | |
| 2762 | static inline void hri_adc_toggle_SWTRIG_START_bit(const void *const hw) |
| 2763 | { |
| 2764 | ADC_CRITICAL_SECTION_ENTER(); |
| 2765 | ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_START; |
| 2766 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2767 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2768 | } |
| 2769 | |
| 2770 | static inline void hri_adc_set_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) |
| 2771 | { |
| 2772 | ADC_CRITICAL_SECTION_ENTER(); |
| 2773 | ((Adc *)hw)->SWTRIG.reg |= mask; |
| 2774 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2775 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2776 | } |
| 2777 | |
| 2778 | static inline hri_adc_swtrig_reg_t hri_adc_get_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) |
| 2779 | { |
| 2780 | uint8_t tmp; |
| 2781 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2782 | tmp = ((Adc *)hw)->SWTRIG.reg; |
| 2783 | tmp &= mask; |
| 2784 | return tmp; |
| 2785 | } |
| 2786 | |
| 2787 | static inline void hri_adc_write_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t data) |
| 2788 | { |
| 2789 | ADC_CRITICAL_SECTION_ENTER(); |
| 2790 | ((Adc *)hw)->SWTRIG.reg = data; |
| 2791 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2792 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2793 | } |
| 2794 | |
| 2795 | static inline void hri_adc_clear_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) |
| 2796 | { |
| 2797 | ADC_CRITICAL_SECTION_ENTER(); |
| 2798 | ((Adc *)hw)->SWTRIG.reg &= ~mask; |
| 2799 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2800 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2801 | } |
| 2802 | |
| 2803 | static inline void hri_adc_toggle_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) |
| 2804 | { |
| 2805 | ADC_CRITICAL_SECTION_ENTER(); |
| 2806 | ((Adc *)hw)->SWTRIG.reg ^= mask; |
| 2807 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2808 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2809 | } |
| 2810 | |
| 2811 | static inline hri_adc_swtrig_reg_t hri_adc_read_SWTRIG_reg(const void *const hw) |
| 2812 | { |
| 2813 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 2814 | return ((Adc *)hw)->SWTRIG.reg; |
| 2815 | } |
| 2816 | |
| 2817 | static inline void hri_adc_set_DSEQCTRL_INPUTCTRL_bit(const void *const hw) |
| 2818 | { |
| 2819 | ADC_CRITICAL_SECTION_ENTER(); |
| 2820 | ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_INPUTCTRL; |
| 2821 | hri_adc_wait_for_sync(hw, |
| 2822 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 2823 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 2824 | | ADC_SYNCBUSY_OFFSETCORR); |
| 2825 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2826 | } |
| 2827 | |
| 2828 | static inline bool hri_adc_get_DSEQCTRL_INPUTCTRL_bit(const void *const hw) |
| 2829 | { |
| 2830 | uint32_t tmp; |
| 2831 | hri_adc_wait_for_sync(hw, |
| 2832 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 2833 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 2834 | | ADC_SYNCBUSY_OFFSETCORR); |
| 2835 | tmp = ((Adc *)hw)->DSEQCTRL.reg; |
| 2836 | tmp = (tmp & ADC_DSEQCTRL_INPUTCTRL) >> ADC_DSEQCTRL_INPUTCTRL_Pos; |
| 2837 | return (bool)tmp; |
| 2838 | } |
| 2839 | |
| 2840 | static inline void hri_adc_write_DSEQCTRL_INPUTCTRL_bit(const void *const hw, bool value) |
| 2841 | { |
| 2842 | uint32_t tmp; |
| 2843 | ADC_CRITICAL_SECTION_ENTER(); |
| 2844 | tmp = ((Adc *)hw)->DSEQCTRL.reg; |
| 2845 | tmp &= ~ADC_DSEQCTRL_INPUTCTRL; |
| 2846 | tmp |= value << ADC_DSEQCTRL_INPUTCTRL_Pos; |
| 2847 | ((Adc *)hw)->DSEQCTRL.reg = tmp; |
| 2848 | hri_adc_wait_for_sync(hw, |
| 2849 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 2850 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 2851 | | ADC_SYNCBUSY_OFFSETCORR); |
| 2852 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2853 | } |
| 2854 | |
| 2855 | static inline void hri_adc_clear_DSEQCTRL_INPUTCTRL_bit(const void *const hw) |
| 2856 | { |
| 2857 | ADC_CRITICAL_SECTION_ENTER(); |
| 2858 | ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_INPUTCTRL; |
| 2859 | hri_adc_wait_for_sync(hw, |
| 2860 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 2861 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 2862 | | ADC_SYNCBUSY_OFFSETCORR); |
| 2863 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2864 | } |
| 2865 | |
| 2866 | static inline void hri_adc_toggle_DSEQCTRL_INPUTCTRL_bit(const void *const hw) |
| 2867 | { |
| 2868 | ADC_CRITICAL_SECTION_ENTER(); |
| 2869 | ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_INPUTCTRL; |
| 2870 | hri_adc_wait_for_sync(hw, |
| 2871 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 2872 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 2873 | | ADC_SYNCBUSY_OFFSETCORR); |
| 2874 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2875 | } |
| 2876 | |
| 2877 | static inline void hri_adc_set_DSEQCTRL_CTRLB_bit(const void *const hw) |
| 2878 | { |
| 2879 | ADC_CRITICAL_SECTION_ENTER(); |
| 2880 | ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_CTRLB; |
| 2881 | hri_adc_wait_for_sync(hw, |
| 2882 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 2883 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 2884 | | ADC_SYNCBUSY_OFFSETCORR); |
| 2885 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2886 | } |
| 2887 | |
| 2888 | static inline bool hri_adc_get_DSEQCTRL_CTRLB_bit(const void *const hw) |
| 2889 | { |
| 2890 | uint32_t tmp; |
| 2891 | hri_adc_wait_for_sync(hw, |
| 2892 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 2893 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 2894 | | ADC_SYNCBUSY_OFFSETCORR); |
| 2895 | tmp = ((Adc *)hw)->DSEQCTRL.reg; |
| 2896 | tmp = (tmp & ADC_DSEQCTRL_CTRLB) >> ADC_DSEQCTRL_CTRLB_Pos; |
| 2897 | return (bool)tmp; |
| 2898 | } |
| 2899 | |
| 2900 | static inline void hri_adc_write_DSEQCTRL_CTRLB_bit(const void *const hw, bool value) |
| 2901 | { |
| 2902 | uint32_t tmp; |
| 2903 | ADC_CRITICAL_SECTION_ENTER(); |
| 2904 | tmp = ((Adc *)hw)->DSEQCTRL.reg; |
| 2905 | tmp &= ~ADC_DSEQCTRL_CTRLB; |
| 2906 | tmp |= value << ADC_DSEQCTRL_CTRLB_Pos; |
| 2907 | ((Adc *)hw)->DSEQCTRL.reg = tmp; |
| 2908 | hri_adc_wait_for_sync(hw, |
| 2909 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 2910 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 2911 | | ADC_SYNCBUSY_OFFSETCORR); |
| 2912 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2913 | } |
| 2914 | |
| 2915 | static inline void hri_adc_clear_DSEQCTRL_CTRLB_bit(const void *const hw) |
| 2916 | { |
| 2917 | ADC_CRITICAL_SECTION_ENTER(); |
| 2918 | ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_CTRLB; |
| 2919 | hri_adc_wait_for_sync(hw, |
| 2920 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 2921 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 2922 | | ADC_SYNCBUSY_OFFSETCORR); |
| 2923 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2924 | } |
| 2925 | |
| 2926 | static inline void hri_adc_toggle_DSEQCTRL_CTRLB_bit(const void *const hw) |
| 2927 | { |
| 2928 | ADC_CRITICAL_SECTION_ENTER(); |
| 2929 | ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_CTRLB; |
| 2930 | hri_adc_wait_for_sync(hw, |
| 2931 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 2932 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 2933 | | ADC_SYNCBUSY_OFFSETCORR); |
| 2934 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2935 | } |
| 2936 | |
| 2937 | static inline void hri_adc_set_DSEQCTRL_REFCTRL_bit(const void *const hw) |
| 2938 | { |
| 2939 | ADC_CRITICAL_SECTION_ENTER(); |
| 2940 | ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_REFCTRL; |
| 2941 | hri_adc_wait_for_sync(hw, |
| 2942 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 2943 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 2944 | | ADC_SYNCBUSY_OFFSETCORR); |
| 2945 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2946 | } |
| 2947 | |
| 2948 | static inline bool hri_adc_get_DSEQCTRL_REFCTRL_bit(const void *const hw) |
| 2949 | { |
| 2950 | uint32_t tmp; |
| 2951 | hri_adc_wait_for_sync(hw, |
| 2952 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 2953 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 2954 | | ADC_SYNCBUSY_OFFSETCORR); |
| 2955 | tmp = ((Adc *)hw)->DSEQCTRL.reg; |
| 2956 | tmp = (tmp & ADC_DSEQCTRL_REFCTRL) >> ADC_DSEQCTRL_REFCTRL_Pos; |
| 2957 | return (bool)tmp; |
| 2958 | } |
| 2959 | |
| 2960 | static inline void hri_adc_write_DSEQCTRL_REFCTRL_bit(const void *const hw, bool value) |
| 2961 | { |
| 2962 | uint32_t tmp; |
| 2963 | ADC_CRITICAL_SECTION_ENTER(); |
| 2964 | tmp = ((Adc *)hw)->DSEQCTRL.reg; |
| 2965 | tmp &= ~ADC_DSEQCTRL_REFCTRL; |
| 2966 | tmp |= value << ADC_DSEQCTRL_REFCTRL_Pos; |
| 2967 | ((Adc *)hw)->DSEQCTRL.reg = tmp; |
| 2968 | hri_adc_wait_for_sync(hw, |
| 2969 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 2970 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 2971 | | ADC_SYNCBUSY_OFFSETCORR); |
| 2972 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2973 | } |
| 2974 | |
| 2975 | static inline void hri_adc_clear_DSEQCTRL_REFCTRL_bit(const void *const hw) |
| 2976 | { |
| 2977 | ADC_CRITICAL_SECTION_ENTER(); |
| 2978 | ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_REFCTRL; |
| 2979 | hri_adc_wait_for_sync(hw, |
| 2980 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 2981 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 2982 | | ADC_SYNCBUSY_OFFSETCORR); |
| 2983 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2984 | } |
| 2985 | |
| 2986 | static inline void hri_adc_toggle_DSEQCTRL_REFCTRL_bit(const void *const hw) |
| 2987 | { |
| 2988 | ADC_CRITICAL_SECTION_ENTER(); |
| 2989 | ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_REFCTRL; |
| 2990 | hri_adc_wait_for_sync(hw, |
| 2991 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 2992 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 2993 | | ADC_SYNCBUSY_OFFSETCORR); |
| 2994 | ADC_CRITICAL_SECTION_LEAVE(); |
| 2995 | } |
| 2996 | |
| 2997 | static inline void hri_adc_set_DSEQCTRL_AVGCTRL_bit(const void *const hw) |
| 2998 | { |
| 2999 | ADC_CRITICAL_SECTION_ENTER(); |
| 3000 | ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_AVGCTRL; |
| 3001 | hri_adc_wait_for_sync(hw, |
| 3002 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3003 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3004 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3005 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3006 | } |
| 3007 | |
| 3008 | static inline bool hri_adc_get_DSEQCTRL_AVGCTRL_bit(const void *const hw) |
| 3009 | { |
| 3010 | uint32_t tmp; |
| 3011 | hri_adc_wait_for_sync(hw, |
| 3012 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3013 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3014 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3015 | tmp = ((Adc *)hw)->DSEQCTRL.reg; |
| 3016 | tmp = (tmp & ADC_DSEQCTRL_AVGCTRL) >> ADC_DSEQCTRL_AVGCTRL_Pos; |
| 3017 | return (bool)tmp; |
| 3018 | } |
| 3019 | |
| 3020 | static inline void hri_adc_write_DSEQCTRL_AVGCTRL_bit(const void *const hw, bool value) |
| 3021 | { |
| 3022 | uint32_t tmp; |
| 3023 | ADC_CRITICAL_SECTION_ENTER(); |
| 3024 | tmp = ((Adc *)hw)->DSEQCTRL.reg; |
| 3025 | tmp &= ~ADC_DSEQCTRL_AVGCTRL; |
| 3026 | tmp |= value << ADC_DSEQCTRL_AVGCTRL_Pos; |
| 3027 | ((Adc *)hw)->DSEQCTRL.reg = tmp; |
| 3028 | hri_adc_wait_for_sync(hw, |
| 3029 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3030 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3031 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3032 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3033 | } |
| 3034 | |
| 3035 | static inline void hri_adc_clear_DSEQCTRL_AVGCTRL_bit(const void *const hw) |
| 3036 | { |
| 3037 | ADC_CRITICAL_SECTION_ENTER(); |
| 3038 | ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_AVGCTRL; |
| 3039 | hri_adc_wait_for_sync(hw, |
| 3040 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3041 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3042 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3043 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3044 | } |
| 3045 | |
| 3046 | static inline void hri_adc_toggle_DSEQCTRL_AVGCTRL_bit(const void *const hw) |
| 3047 | { |
| 3048 | ADC_CRITICAL_SECTION_ENTER(); |
| 3049 | ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_AVGCTRL; |
| 3050 | hri_adc_wait_for_sync(hw, |
| 3051 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3052 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3053 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3054 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3055 | } |
| 3056 | |
| 3057 | static inline void hri_adc_set_DSEQCTRL_SAMPCTRL_bit(const void *const hw) |
| 3058 | { |
| 3059 | ADC_CRITICAL_SECTION_ENTER(); |
| 3060 | ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_SAMPCTRL; |
| 3061 | hri_adc_wait_for_sync(hw, |
| 3062 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3063 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3064 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3065 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3066 | } |
| 3067 | |
| 3068 | static inline bool hri_adc_get_DSEQCTRL_SAMPCTRL_bit(const void *const hw) |
| 3069 | { |
| 3070 | uint32_t tmp; |
| 3071 | hri_adc_wait_for_sync(hw, |
| 3072 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3073 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3074 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3075 | tmp = ((Adc *)hw)->DSEQCTRL.reg; |
| 3076 | tmp = (tmp & ADC_DSEQCTRL_SAMPCTRL) >> ADC_DSEQCTRL_SAMPCTRL_Pos; |
| 3077 | return (bool)tmp; |
| 3078 | } |
| 3079 | |
| 3080 | static inline void hri_adc_write_DSEQCTRL_SAMPCTRL_bit(const void *const hw, bool value) |
| 3081 | { |
| 3082 | uint32_t tmp; |
| 3083 | ADC_CRITICAL_SECTION_ENTER(); |
| 3084 | tmp = ((Adc *)hw)->DSEQCTRL.reg; |
| 3085 | tmp &= ~ADC_DSEQCTRL_SAMPCTRL; |
| 3086 | tmp |= value << ADC_DSEQCTRL_SAMPCTRL_Pos; |
| 3087 | ((Adc *)hw)->DSEQCTRL.reg = tmp; |
| 3088 | hri_adc_wait_for_sync(hw, |
| 3089 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3090 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3091 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3092 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3093 | } |
| 3094 | |
| 3095 | static inline void hri_adc_clear_DSEQCTRL_SAMPCTRL_bit(const void *const hw) |
| 3096 | { |
| 3097 | ADC_CRITICAL_SECTION_ENTER(); |
| 3098 | ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_SAMPCTRL; |
| 3099 | hri_adc_wait_for_sync(hw, |
| 3100 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3101 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3102 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3103 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3104 | } |
| 3105 | |
| 3106 | static inline void hri_adc_toggle_DSEQCTRL_SAMPCTRL_bit(const void *const hw) |
| 3107 | { |
| 3108 | ADC_CRITICAL_SECTION_ENTER(); |
| 3109 | ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_SAMPCTRL; |
| 3110 | hri_adc_wait_for_sync(hw, |
| 3111 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3112 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3113 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3114 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3115 | } |
| 3116 | |
| 3117 | static inline void hri_adc_set_DSEQCTRL_WINLT_bit(const void *const hw) |
| 3118 | { |
| 3119 | ADC_CRITICAL_SECTION_ENTER(); |
| 3120 | ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_WINLT; |
| 3121 | hri_adc_wait_for_sync(hw, |
| 3122 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3123 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3124 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3125 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3126 | } |
| 3127 | |
| 3128 | static inline bool hri_adc_get_DSEQCTRL_WINLT_bit(const void *const hw) |
| 3129 | { |
| 3130 | uint32_t tmp; |
| 3131 | hri_adc_wait_for_sync(hw, |
| 3132 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3133 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3134 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3135 | tmp = ((Adc *)hw)->DSEQCTRL.reg; |
| 3136 | tmp = (tmp & ADC_DSEQCTRL_WINLT) >> ADC_DSEQCTRL_WINLT_Pos; |
| 3137 | return (bool)tmp; |
| 3138 | } |
| 3139 | |
| 3140 | static inline void hri_adc_write_DSEQCTRL_WINLT_bit(const void *const hw, bool value) |
| 3141 | { |
| 3142 | uint32_t tmp; |
| 3143 | ADC_CRITICAL_SECTION_ENTER(); |
| 3144 | tmp = ((Adc *)hw)->DSEQCTRL.reg; |
| 3145 | tmp &= ~ADC_DSEQCTRL_WINLT; |
| 3146 | tmp |= value << ADC_DSEQCTRL_WINLT_Pos; |
| 3147 | ((Adc *)hw)->DSEQCTRL.reg = tmp; |
| 3148 | hri_adc_wait_for_sync(hw, |
| 3149 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3150 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3151 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3152 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3153 | } |
| 3154 | |
| 3155 | static inline void hri_adc_clear_DSEQCTRL_WINLT_bit(const void *const hw) |
| 3156 | { |
| 3157 | ADC_CRITICAL_SECTION_ENTER(); |
| 3158 | ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_WINLT; |
| 3159 | hri_adc_wait_for_sync(hw, |
| 3160 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3161 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3162 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3163 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3164 | } |
| 3165 | |
| 3166 | static inline void hri_adc_toggle_DSEQCTRL_WINLT_bit(const void *const hw) |
| 3167 | { |
| 3168 | ADC_CRITICAL_SECTION_ENTER(); |
| 3169 | ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_WINLT; |
| 3170 | hri_adc_wait_for_sync(hw, |
| 3171 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3172 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3173 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3174 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3175 | } |
| 3176 | |
| 3177 | static inline void hri_adc_set_DSEQCTRL_WINUT_bit(const void *const hw) |
| 3178 | { |
| 3179 | ADC_CRITICAL_SECTION_ENTER(); |
| 3180 | ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_WINUT; |
| 3181 | hri_adc_wait_for_sync(hw, |
| 3182 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3183 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3184 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3185 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3186 | } |
| 3187 | |
| 3188 | static inline bool hri_adc_get_DSEQCTRL_WINUT_bit(const void *const hw) |
| 3189 | { |
| 3190 | uint32_t tmp; |
| 3191 | hri_adc_wait_for_sync(hw, |
| 3192 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3193 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3194 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3195 | tmp = ((Adc *)hw)->DSEQCTRL.reg; |
| 3196 | tmp = (tmp & ADC_DSEQCTRL_WINUT) >> ADC_DSEQCTRL_WINUT_Pos; |
| 3197 | return (bool)tmp; |
| 3198 | } |
| 3199 | |
| 3200 | static inline void hri_adc_write_DSEQCTRL_WINUT_bit(const void *const hw, bool value) |
| 3201 | { |
| 3202 | uint32_t tmp; |
| 3203 | ADC_CRITICAL_SECTION_ENTER(); |
| 3204 | tmp = ((Adc *)hw)->DSEQCTRL.reg; |
| 3205 | tmp &= ~ADC_DSEQCTRL_WINUT; |
| 3206 | tmp |= value << ADC_DSEQCTRL_WINUT_Pos; |
| 3207 | ((Adc *)hw)->DSEQCTRL.reg = tmp; |
| 3208 | hri_adc_wait_for_sync(hw, |
| 3209 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3210 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3211 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3212 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3213 | } |
| 3214 | |
| 3215 | static inline void hri_adc_clear_DSEQCTRL_WINUT_bit(const void *const hw) |
| 3216 | { |
| 3217 | ADC_CRITICAL_SECTION_ENTER(); |
| 3218 | ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_WINUT; |
| 3219 | hri_adc_wait_for_sync(hw, |
| 3220 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3221 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3222 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3223 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3224 | } |
| 3225 | |
| 3226 | static inline void hri_adc_toggle_DSEQCTRL_WINUT_bit(const void *const hw) |
| 3227 | { |
| 3228 | ADC_CRITICAL_SECTION_ENTER(); |
| 3229 | ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_WINUT; |
| 3230 | hri_adc_wait_for_sync(hw, |
| 3231 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3232 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3233 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3234 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3235 | } |
| 3236 | |
| 3237 | static inline void hri_adc_set_DSEQCTRL_GAINCORR_bit(const void *const hw) |
| 3238 | { |
| 3239 | ADC_CRITICAL_SECTION_ENTER(); |
| 3240 | ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_GAINCORR; |
| 3241 | hri_adc_wait_for_sync(hw, |
| 3242 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3243 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3244 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3245 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3246 | } |
| 3247 | |
| 3248 | static inline bool hri_adc_get_DSEQCTRL_GAINCORR_bit(const void *const hw) |
| 3249 | { |
| 3250 | uint32_t tmp; |
| 3251 | hri_adc_wait_for_sync(hw, |
| 3252 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3253 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3254 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3255 | tmp = ((Adc *)hw)->DSEQCTRL.reg; |
| 3256 | tmp = (tmp & ADC_DSEQCTRL_GAINCORR) >> ADC_DSEQCTRL_GAINCORR_Pos; |
| 3257 | return (bool)tmp; |
| 3258 | } |
| 3259 | |
| 3260 | static inline void hri_adc_write_DSEQCTRL_GAINCORR_bit(const void *const hw, bool value) |
| 3261 | { |
| 3262 | uint32_t tmp; |
| 3263 | ADC_CRITICAL_SECTION_ENTER(); |
| 3264 | tmp = ((Adc *)hw)->DSEQCTRL.reg; |
| 3265 | tmp &= ~ADC_DSEQCTRL_GAINCORR; |
| 3266 | tmp |= value << ADC_DSEQCTRL_GAINCORR_Pos; |
| 3267 | ((Adc *)hw)->DSEQCTRL.reg = tmp; |
| 3268 | hri_adc_wait_for_sync(hw, |
| 3269 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3270 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3271 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3272 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3273 | } |
| 3274 | |
| 3275 | static inline void hri_adc_clear_DSEQCTRL_GAINCORR_bit(const void *const hw) |
| 3276 | { |
| 3277 | ADC_CRITICAL_SECTION_ENTER(); |
| 3278 | ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_GAINCORR; |
| 3279 | hri_adc_wait_for_sync(hw, |
| 3280 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3281 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3282 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3283 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3284 | } |
| 3285 | |
| 3286 | static inline void hri_adc_toggle_DSEQCTRL_GAINCORR_bit(const void *const hw) |
| 3287 | { |
| 3288 | ADC_CRITICAL_SECTION_ENTER(); |
| 3289 | ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_GAINCORR; |
| 3290 | hri_adc_wait_for_sync(hw, |
| 3291 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3292 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3293 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3294 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3295 | } |
| 3296 | |
| 3297 | static inline void hri_adc_set_DSEQCTRL_OFFSETCORR_bit(const void *const hw) |
| 3298 | { |
| 3299 | ADC_CRITICAL_SECTION_ENTER(); |
| 3300 | ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_OFFSETCORR; |
| 3301 | hri_adc_wait_for_sync(hw, |
| 3302 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3303 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3304 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3305 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3306 | } |
| 3307 | |
| 3308 | static inline bool hri_adc_get_DSEQCTRL_OFFSETCORR_bit(const void *const hw) |
| 3309 | { |
| 3310 | uint32_t tmp; |
| 3311 | hri_adc_wait_for_sync(hw, |
| 3312 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3313 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3314 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3315 | tmp = ((Adc *)hw)->DSEQCTRL.reg; |
| 3316 | tmp = (tmp & ADC_DSEQCTRL_OFFSETCORR) >> ADC_DSEQCTRL_OFFSETCORR_Pos; |
| 3317 | return (bool)tmp; |
| 3318 | } |
| 3319 | |
| 3320 | static inline void hri_adc_write_DSEQCTRL_OFFSETCORR_bit(const void *const hw, bool value) |
| 3321 | { |
| 3322 | uint32_t tmp; |
| 3323 | ADC_CRITICAL_SECTION_ENTER(); |
| 3324 | tmp = ((Adc *)hw)->DSEQCTRL.reg; |
| 3325 | tmp &= ~ADC_DSEQCTRL_OFFSETCORR; |
| 3326 | tmp |= value << ADC_DSEQCTRL_OFFSETCORR_Pos; |
| 3327 | ((Adc *)hw)->DSEQCTRL.reg = tmp; |
| 3328 | hri_adc_wait_for_sync(hw, |
| 3329 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3330 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3331 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3332 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3333 | } |
| 3334 | |
| 3335 | static inline void hri_adc_clear_DSEQCTRL_OFFSETCORR_bit(const void *const hw) |
| 3336 | { |
| 3337 | ADC_CRITICAL_SECTION_ENTER(); |
| 3338 | ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_OFFSETCORR; |
| 3339 | hri_adc_wait_for_sync(hw, |
| 3340 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3341 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3342 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3343 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3344 | } |
| 3345 | |
| 3346 | static inline void hri_adc_toggle_DSEQCTRL_OFFSETCORR_bit(const void *const hw) |
| 3347 | { |
| 3348 | ADC_CRITICAL_SECTION_ENTER(); |
| 3349 | ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_OFFSETCORR; |
| 3350 | hri_adc_wait_for_sync(hw, |
| 3351 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3352 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3353 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3354 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3355 | } |
| 3356 | |
| 3357 | static inline void hri_adc_set_DSEQCTRL_AUTOSTART_bit(const void *const hw) |
| 3358 | { |
| 3359 | ADC_CRITICAL_SECTION_ENTER(); |
| 3360 | ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_AUTOSTART; |
| 3361 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 3362 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3363 | } |
| 3364 | |
| 3365 | static inline bool hri_adc_get_DSEQCTRL_AUTOSTART_bit(const void *const hw) |
| 3366 | { |
| 3367 | uint32_t tmp; |
| 3368 | tmp = ((Adc *)hw)->DSEQCTRL.reg; |
| 3369 | tmp = (tmp & ADC_DSEQCTRL_AUTOSTART) >> ADC_DSEQCTRL_AUTOSTART_Pos; |
| 3370 | return (bool)tmp; |
| 3371 | } |
| 3372 | |
| 3373 | static inline void hri_adc_write_DSEQCTRL_AUTOSTART_bit(const void *const hw, bool value) |
| 3374 | { |
| 3375 | uint32_t tmp; |
| 3376 | ADC_CRITICAL_SECTION_ENTER(); |
| 3377 | tmp = ((Adc *)hw)->DSEQCTRL.reg; |
| 3378 | tmp &= ~ADC_DSEQCTRL_AUTOSTART; |
| 3379 | tmp |= value << ADC_DSEQCTRL_AUTOSTART_Pos; |
| 3380 | ((Adc *)hw)->DSEQCTRL.reg = tmp; |
| 3381 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 3382 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3383 | } |
| 3384 | |
| 3385 | static inline void hri_adc_clear_DSEQCTRL_AUTOSTART_bit(const void *const hw) |
| 3386 | { |
| 3387 | ADC_CRITICAL_SECTION_ENTER(); |
| 3388 | ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_AUTOSTART; |
| 3389 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 3390 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3391 | } |
| 3392 | |
| 3393 | static inline void hri_adc_toggle_DSEQCTRL_AUTOSTART_bit(const void *const hw) |
| 3394 | { |
| 3395 | ADC_CRITICAL_SECTION_ENTER(); |
| 3396 | ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_AUTOSTART; |
| 3397 | hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); |
| 3398 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3399 | } |
| 3400 | |
| 3401 | static inline void hri_adc_set_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) |
| 3402 | { |
| 3403 | ADC_CRITICAL_SECTION_ENTER(); |
| 3404 | ((Adc *)hw)->DSEQCTRL.reg |= mask; |
| 3405 | hri_adc_wait_for_sync(hw, |
| 3406 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3407 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3408 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3409 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3410 | } |
| 3411 | |
| 3412 | static inline hri_adc_dseqctrl_reg_t hri_adc_get_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) |
| 3413 | { |
| 3414 | uint32_t tmp; |
| 3415 | hri_adc_wait_for_sync(hw, |
| 3416 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3417 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3418 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3419 | tmp = ((Adc *)hw)->DSEQCTRL.reg; |
| 3420 | tmp &= mask; |
| 3421 | return tmp; |
| 3422 | } |
| 3423 | |
| 3424 | static inline void hri_adc_write_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t data) |
| 3425 | { |
| 3426 | ADC_CRITICAL_SECTION_ENTER(); |
| 3427 | ((Adc *)hw)->DSEQCTRL.reg = data; |
| 3428 | hri_adc_wait_for_sync(hw, |
| 3429 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3430 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3431 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3432 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3433 | } |
| 3434 | |
| 3435 | static inline void hri_adc_clear_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) |
| 3436 | { |
| 3437 | ADC_CRITICAL_SECTION_ENTER(); |
| 3438 | ((Adc *)hw)->DSEQCTRL.reg &= ~mask; |
| 3439 | hri_adc_wait_for_sync(hw, |
| 3440 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3441 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3442 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3443 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3444 | } |
| 3445 | |
| 3446 | static inline void hri_adc_toggle_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) |
| 3447 | { |
| 3448 | ADC_CRITICAL_SECTION_ENTER(); |
| 3449 | ((Adc *)hw)->DSEQCTRL.reg ^= mask; |
| 3450 | hri_adc_wait_for_sync(hw, |
| 3451 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3452 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3453 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3454 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3455 | } |
| 3456 | |
| 3457 | static inline hri_adc_dseqctrl_reg_t hri_adc_read_DSEQCTRL_reg(const void *const hw) |
| 3458 | { |
| 3459 | hri_adc_wait_for_sync(hw, |
| 3460 | ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL |
| 3461 | | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR |
| 3462 | | ADC_SYNCBUSY_OFFSETCORR); |
| 3463 | return ((Adc *)hw)->DSEQCTRL.reg; |
| 3464 | } |
| 3465 | |
| 3466 | static inline void hri_adc_set_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) |
| 3467 | { |
| 3468 | ADC_CRITICAL_SECTION_ENTER(); |
| 3469 | ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASCOMP(mask); |
| 3470 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3471 | } |
| 3472 | |
| 3473 | static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) |
| 3474 | { |
| 3475 | uint16_t tmp; |
| 3476 | tmp = ((Adc *)hw)->CALIB.reg; |
| 3477 | tmp = (tmp & ADC_CALIB_BIASCOMP(mask)) >> ADC_CALIB_BIASCOMP_Pos; |
| 3478 | return tmp; |
| 3479 | } |
| 3480 | |
| 3481 | static inline void hri_adc_write_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t data) |
| 3482 | { |
| 3483 | uint16_t tmp; |
| 3484 | ADC_CRITICAL_SECTION_ENTER(); |
| 3485 | tmp = ((Adc *)hw)->CALIB.reg; |
| 3486 | tmp &= ~ADC_CALIB_BIASCOMP_Msk; |
| 3487 | tmp |= ADC_CALIB_BIASCOMP(data); |
| 3488 | ((Adc *)hw)->CALIB.reg = tmp; |
| 3489 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3490 | } |
| 3491 | |
| 3492 | static inline void hri_adc_clear_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) |
| 3493 | { |
| 3494 | ADC_CRITICAL_SECTION_ENTER(); |
| 3495 | ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASCOMP(mask); |
| 3496 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3497 | } |
| 3498 | |
| 3499 | static inline void hri_adc_toggle_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) |
| 3500 | { |
| 3501 | ADC_CRITICAL_SECTION_ENTER(); |
| 3502 | ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASCOMP(mask); |
| 3503 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3504 | } |
| 3505 | |
| 3506 | static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASCOMP_bf(const void *const hw) |
| 3507 | { |
| 3508 | uint16_t tmp; |
| 3509 | tmp = ((Adc *)hw)->CALIB.reg; |
| 3510 | tmp = (tmp & ADC_CALIB_BIASCOMP_Msk) >> ADC_CALIB_BIASCOMP_Pos; |
| 3511 | return tmp; |
| 3512 | } |
| 3513 | |
| 3514 | static inline void hri_adc_set_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) |
| 3515 | { |
| 3516 | ADC_CRITICAL_SECTION_ENTER(); |
| 3517 | ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASR2R(mask); |
| 3518 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3519 | } |
| 3520 | |
| 3521 | static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) |
| 3522 | { |
| 3523 | uint16_t tmp; |
| 3524 | tmp = ((Adc *)hw)->CALIB.reg; |
| 3525 | tmp = (tmp & ADC_CALIB_BIASR2R(mask)) >> ADC_CALIB_BIASR2R_Pos; |
| 3526 | return tmp; |
| 3527 | } |
| 3528 | |
| 3529 | static inline void hri_adc_write_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t data) |
| 3530 | { |
| 3531 | uint16_t tmp; |
| 3532 | ADC_CRITICAL_SECTION_ENTER(); |
| 3533 | tmp = ((Adc *)hw)->CALIB.reg; |
| 3534 | tmp &= ~ADC_CALIB_BIASR2R_Msk; |
| 3535 | tmp |= ADC_CALIB_BIASR2R(data); |
| 3536 | ((Adc *)hw)->CALIB.reg = tmp; |
| 3537 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3538 | } |
| 3539 | |
| 3540 | static inline void hri_adc_clear_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) |
| 3541 | { |
| 3542 | ADC_CRITICAL_SECTION_ENTER(); |
| 3543 | ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASR2R(mask); |
| 3544 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3545 | } |
| 3546 | |
| 3547 | static inline void hri_adc_toggle_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) |
| 3548 | { |
| 3549 | ADC_CRITICAL_SECTION_ENTER(); |
| 3550 | ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASR2R(mask); |
| 3551 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3552 | } |
| 3553 | |
| 3554 | static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASR2R_bf(const void *const hw) |
| 3555 | { |
| 3556 | uint16_t tmp; |
| 3557 | tmp = ((Adc *)hw)->CALIB.reg; |
| 3558 | tmp = (tmp & ADC_CALIB_BIASR2R_Msk) >> ADC_CALIB_BIASR2R_Pos; |
| 3559 | return tmp; |
| 3560 | } |
| 3561 | |
| 3562 | static inline void hri_adc_set_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) |
| 3563 | { |
| 3564 | ADC_CRITICAL_SECTION_ENTER(); |
| 3565 | ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASREFBUF(mask); |
| 3566 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3567 | } |
| 3568 | |
| 3569 | static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) |
| 3570 | { |
| 3571 | uint16_t tmp; |
| 3572 | tmp = ((Adc *)hw)->CALIB.reg; |
| 3573 | tmp = (tmp & ADC_CALIB_BIASREFBUF(mask)) >> ADC_CALIB_BIASREFBUF_Pos; |
| 3574 | return tmp; |
| 3575 | } |
| 3576 | |
| 3577 | static inline void hri_adc_write_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t data) |
| 3578 | { |
| 3579 | uint16_t tmp; |
| 3580 | ADC_CRITICAL_SECTION_ENTER(); |
| 3581 | tmp = ((Adc *)hw)->CALIB.reg; |
| 3582 | tmp &= ~ADC_CALIB_BIASREFBUF_Msk; |
| 3583 | tmp |= ADC_CALIB_BIASREFBUF(data); |
| 3584 | ((Adc *)hw)->CALIB.reg = tmp; |
| 3585 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3586 | } |
| 3587 | |
| 3588 | static inline void hri_adc_clear_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) |
| 3589 | { |
| 3590 | ADC_CRITICAL_SECTION_ENTER(); |
| 3591 | ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASREFBUF(mask); |
| 3592 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3593 | } |
| 3594 | |
| 3595 | static inline void hri_adc_toggle_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) |
| 3596 | { |
| 3597 | ADC_CRITICAL_SECTION_ENTER(); |
| 3598 | ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASREFBUF(mask); |
| 3599 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3600 | } |
| 3601 | |
| 3602 | static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASREFBUF_bf(const void *const hw) |
| 3603 | { |
| 3604 | uint16_t tmp; |
| 3605 | tmp = ((Adc *)hw)->CALIB.reg; |
| 3606 | tmp = (tmp & ADC_CALIB_BIASREFBUF_Msk) >> ADC_CALIB_BIASREFBUF_Pos; |
| 3607 | return tmp; |
| 3608 | } |
| 3609 | |
| 3610 | static inline void hri_adc_set_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) |
| 3611 | { |
| 3612 | ADC_CRITICAL_SECTION_ENTER(); |
| 3613 | ((Adc *)hw)->CALIB.reg |= mask; |
| 3614 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3615 | } |
| 3616 | |
| 3617 | static inline hri_adc_calib_reg_t hri_adc_get_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) |
| 3618 | { |
| 3619 | uint16_t tmp; |
| 3620 | tmp = ((Adc *)hw)->CALIB.reg; |
| 3621 | tmp &= mask; |
| 3622 | return tmp; |
| 3623 | } |
| 3624 | |
| 3625 | static inline void hri_adc_write_CALIB_reg(const void *const hw, hri_adc_calib_reg_t data) |
| 3626 | { |
| 3627 | ADC_CRITICAL_SECTION_ENTER(); |
| 3628 | ((Adc *)hw)->CALIB.reg = data; |
| 3629 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3630 | } |
| 3631 | |
| 3632 | static inline void hri_adc_clear_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) |
| 3633 | { |
| 3634 | ADC_CRITICAL_SECTION_ENTER(); |
| 3635 | ((Adc *)hw)->CALIB.reg &= ~mask; |
| 3636 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3637 | } |
| 3638 | |
| 3639 | static inline void hri_adc_toggle_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) |
| 3640 | { |
| 3641 | ADC_CRITICAL_SECTION_ENTER(); |
| 3642 | ((Adc *)hw)->CALIB.reg ^= mask; |
| 3643 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3644 | } |
| 3645 | |
| 3646 | static inline hri_adc_calib_reg_t hri_adc_read_CALIB_reg(const void *const hw) |
| 3647 | { |
| 3648 | return ((Adc *)hw)->CALIB.reg; |
| 3649 | } |
| 3650 | |
| 3651 | static inline void hri_adc_write_DSEQDATA_reg(const void *const hw, hri_adc_dseqdata_reg_t data) |
| 3652 | { |
| 3653 | ADC_CRITICAL_SECTION_ENTER(); |
| 3654 | ((Adc *)hw)->DSEQDATA.reg = data; |
| 3655 | ADC_CRITICAL_SECTION_LEAVE(); |
| 3656 | } |
| 3657 | |
| 3658 | #ifdef __cplusplus |
| 3659 | } |
| 3660 | #endif |
| 3661 | |
| 3662 | #endif /* _HRI_ADC_E54_H_INCLUDED */ |
| 3663 | #endif /* _SAME54_ADC_COMPONENT_ */ |