Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief Component description for PM |
| 5 | * |
| 6 | * Copyright (c) 2018 Microchip Technology Inc. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * SPDX-License-Identifier: Apache-2.0 |
| 13 | * |
| 14 | * Licensed under the Apache License, Version 2.0 (the "License"); you may |
| 15 | * not use this file except in compliance with the License. |
| 16 | * You may obtain a copy of the Licence at |
| 17 | * |
| 18 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 19 | * |
| 20 | * Unless required by applicable law or agreed to in writing, software |
| 21 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 22 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 23 | * See the License for the specific language governing permissions and |
| 24 | * limitations under the License. |
| 25 | * |
| 26 | * \asf_license_stop |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #ifndef _SAME54_PM_COMPONENT_ |
| 31 | #define _SAME54_PM_COMPONENT_ |
| 32 | |
| 33 | /* ========================================================================== */ |
| 34 | /** SOFTWARE API DEFINITION FOR PM */ |
| 35 | /* ========================================================================== */ |
| 36 | /** \addtogroup SAME54_PM Power Manager */ |
| 37 | /*@{*/ |
| 38 | |
| 39 | #define PM_U2406 |
| 40 | #define REV_PM 0x100 |
| 41 | |
| 42 | /* -------- PM_CTRLA : (PM Offset: 0x00) (R/W 8) Control A -------- */ |
| 43 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 44 | typedef union { |
| 45 | struct { |
| 46 | uint8_t :2; /*!< bit: 0.. 1 Reserved */ |
| 47 | uint8_t IORET:1; /*!< bit: 2 I/O Retention */ |
| 48 | uint8_t :5; /*!< bit: 3.. 7 Reserved */ |
| 49 | } bit; /*!< Structure used for bit access */ |
| 50 | uint8_t reg; /*!< Type used for register access */ |
| 51 | } PM_CTRLA_Type; |
| 52 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 53 | |
| 54 | #define PM_CTRLA_OFFSET 0x00 /**< \brief (PM_CTRLA offset) Control A */ |
| 55 | #define PM_CTRLA_RESETVALUE _U_(0x00) /**< \brief (PM_CTRLA reset_value) Control A */ |
| 56 | |
| 57 | #define PM_CTRLA_IORET_Pos 2 /**< \brief (PM_CTRLA) I/O Retention */ |
| 58 | #define PM_CTRLA_IORET (_U_(0x1) << PM_CTRLA_IORET_Pos) |
| 59 | #define PM_CTRLA_MASK _U_(0x04) /**< \brief (PM_CTRLA) MASK Register */ |
| 60 | |
| 61 | /* -------- PM_SLEEPCFG : (PM Offset: 0x01) (R/W 8) Sleep Configuration -------- */ |
| 62 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 63 | typedef union { |
| 64 | struct { |
| 65 | uint8_t SLEEPMODE:3; /*!< bit: 0.. 2 Sleep Mode */ |
| 66 | uint8_t :5; /*!< bit: 3.. 7 Reserved */ |
| 67 | } bit; /*!< Structure used for bit access */ |
| 68 | uint8_t reg; /*!< Type used for register access */ |
| 69 | } PM_SLEEPCFG_Type; |
| 70 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 71 | |
| 72 | #define PM_SLEEPCFG_OFFSET 0x01 /**< \brief (PM_SLEEPCFG offset) Sleep Configuration */ |
| 73 | #define PM_SLEEPCFG_RESETVALUE _U_(0x02) /**< \brief (PM_SLEEPCFG reset_value) Sleep Configuration */ |
| 74 | |
| 75 | #define PM_SLEEPCFG_SLEEPMODE_Pos 0 /**< \brief (PM_SLEEPCFG) Sleep Mode */ |
| 76 | #define PM_SLEEPCFG_SLEEPMODE_Msk (_U_(0x7) << PM_SLEEPCFG_SLEEPMODE_Pos) |
| 77 | #define PM_SLEEPCFG_SLEEPMODE(value) (PM_SLEEPCFG_SLEEPMODE_Msk & ((value) << PM_SLEEPCFG_SLEEPMODE_Pos)) |
| 78 | #define PM_SLEEPCFG_SLEEPMODE_IDLE0_Val _U_(0x0) /**< \brief (PM_SLEEPCFG) CPU clock is OFF */ |
| 79 | #define PM_SLEEPCFG_SLEEPMODE_IDLE1_Val _U_(0x1) /**< \brief (PM_SLEEPCFG) AHB clock is OFF */ |
| 80 | #define PM_SLEEPCFG_SLEEPMODE_IDLE2_Val _U_(0x2) /**< \brief (PM_SLEEPCFG) APB clock are OFF */ |
| 81 | #define PM_SLEEPCFG_SLEEPMODE_STANDBY_Val _U_(0x4) /**< \brief (PM_SLEEPCFG) All Clocks are OFF */ |
| 82 | #define PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val _U_(0x5) /**< \brief (PM_SLEEPCFG) Backup domain is ON as well as some PDRAMs */ |
| 83 | #define PM_SLEEPCFG_SLEEPMODE_BACKUP_Val _U_(0x6) /**< \brief (PM_SLEEPCFG) Only Backup domain is powered ON */ |
| 84 | #define PM_SLEEPCFG_SLEEPMODE_OFF_Val _U_(0x7) /**< \brief (PM_SLEEPCFG) All power domains are powered OFF */ |
| 85 | #define PM_SLEEPCFG_SLEEPMODE_IDLE0 (PM_SLEEPCFG_SLEEPMODE_IDLE0_Val << PM_SLEEPCFG_SLEEPMODE_Pos) |
| 86 | #define PM_SLEEPCFG_SLEEPMODE_IDLE1 (PM_SLEEPCFG_SLEEPMODE_IDLE1_Val << PM_SLEEPCFG_SLEEPMODE_Pos) |
| 87 | #define PM_SLEEPCFG_SLEEPMODE_IDLE2 (PM_SLEEPCFG_SLEEPMODE_IDLE2_Val << PM_SLEEPCFG_SLEEPMODE_Pos) |
| 88 | #define PM_SLEEPCFG_SLEEPMODE_STANDBY (PM_SLEEPCFG_SLEEPMODE_STANDBY_Val << PM_SLEEPCFG_SLEEPMODE_Pos) |
| 89 | #define PM_SLEEPCFG_SLEEPMODE_HIBERNATE (PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val << PM_SLEEPCFG_SLEEPMODE_Pos) |
| 90 | #define PM_SLEEPCFG_SLEEPMODE_BACKUP (PM_SLEEPCFG_SLEEPMODE_BACKUP_Val << PM_SLEEPCFG_SLEEPMODE_Pos) |
| 91 | #define PM_SLEEPCFG_SLEEPMODE_OFF (PM_SLEEPCFG_SLEEPMODE_OFF_Val << PM_SLEEPCFG_SLEEPMODE_Pos) |
| 92 | #define PM_SLEEPCFG_MASK _U_(0x07) /**< \brief (PM_SLEEPCFG) MASK Register */ |
| 93 | |
| 94 | /* -------- PM_INTENCLR : (PM Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ |
| 95 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 96 | typedef union { |
| 97 | struct { |
| 98 | uint8_t SLEEPRDY:1; /*!< bit: 0 Sleep Mode Entry Ready Enable */ |
| 99 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
| 100 | } bit; /*!< Structure used for bit access */ |
| 101 | uint8_t reg; /*!< Type used for register access */ |
| 102 | } PM_INTENCLR_Type; |
| 103 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 104 | |
| 105 | #define PM_INTENCLR_OFFSET 0x04 /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */ |
| 106 | #define PM_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */ |
| 107 | |
| 108 | #define PM_INTENCLR_SLEEPRDY_Pos 0 /**< \brief (PM_INTENCLR) Sleep Mode Entry Ready Enable */ |
| 109 | #define PM_INTENCLR_SLEEPRDY (_U_(0x1) << PM_INTENCLR_SLEEPRDY_Pos) |
| 110 | #define PM_INTENCLR_MASK _U_(0x01) /**< \brief (PM_INTENCLR) MASK Register */ |
| 111 | |
| 112 | /* -------- PM_INTENSET : (PM Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ |
| 113 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 114 | typedef union { |
| 115 | struct { |
| 116 | uint8_t SLEEPRDY:1; /*!< bit: 0 Sleep Mode Entry Ready Enable */ |
| 117 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
| 118 | } bit; /*!< Structure used for bit access */ |
| 119 | uint8_t reg; /*!< Type used for register access */ |
| 120 | } PM_INTENSET_Type; |
| 121 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 122 | |
| 123 | #define PM_INTENSET_OFFSET 0x05 /**< \brief (PM_INTENSET offset) Interrupt Enable Set */ |
| 124 | #define PM_INTENSET_RESETVALUE _U_(0x00) /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */ |
| 125 | |
| 126 | #define PM_INTENSET_SLEEPRDY_Pos 0 /**< \brief (PM_INTENSET) Sleep Mode Entry Ready Enable */ |
| 127 | #define PM_INTENSET_SLEEPRDY (_U_(0x1) << PM_INTENSET_SLEEPRDY_Pos) |
| 128 | #define PM_INTENSET_MASK _U_(0x01) /**< \brief (PM_INTENSET) MASK Register */ |
| 129 | |
| 130 | /* -------- PM_INTFLAG : (PM Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ |
| 131 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 132 | typedef union { // __I to avoid read-modify-write on write-to-clear register |
| 133 | struct { |
| 134 | __I uint8_t SLEEPRDY:1; /*!< bit: 0 Sleep Mode Entry Ready */ |
| 135 | __I uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
| 136 | } bit; /*!< Structure used for bit access */ |
| 137 | uint8_t reg; /*!< Type used for register access */ |
| 138 | } PM_INTFLAG_Type; |
| 139 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 140 | |
| 141 | #define PM_INTFLAG_OFFSET 0x06 /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */ |
| 142 | #define PM_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */ |
| 143 | |
| 144 | #define PM_INTFLAG_SLEEPRDY_Pos 0 /**< \brief (PM_INTFLAG) Sleep Mode Entry Ready */ |
| 145 | #define PM_INTFLAG_SLEEPRDY (_U_(0x1) << PM_INTFLAG_SLEEPRDY_Pos) |
| 146 | #define PM_INTFLAG_MASK _U_(0x01) /**< \brief (PM_INTFLAG) MASK Register */ |
| 147 | |
| 148 | /* -------- PM_STDBYCFG : (PM Offset: 0x08) (R/W 8) Standby Configuration -------- */ |
| 149 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 150 | typedef union { |
| 151 | struct { |
| 152 | uint8_t RAMCFG:2; /*!< bit: 0.. 1 Ram Configuration */ |
| 153 | uint8_t :2; /*!< bit: 2.. 3 Reserved */ |
| 154 | uint8_t FASTWKUP:2; /*!< bit: 4.. 5 Fast Wakeup */ |
| 155 | uint8_t :2; /*!< bit: 6.. 7 Reserved */ |
| 156 | } bit; /*!< Structure used for bit access */ |
| 157 | uint8_t reg; /*!< Type used for register access */ |
| 158 | } PM_STDBYCFG_Type; |
| 159 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 160 | |
| 161 | #define PM_STDBYCFG_OFFSET 0x08 /**< \brief (PM_STDBYCFG offset) Standby Configuration */ |
| 162 | #define PM_STDBYCFG_RESETVALUE _U_(0x00) /**< \brief (PM_STDBYCFG reset_value) Standby Configuration */ |
| 163 | |
| 164 | #define PM_STDBYCFG_RAMCFG_Pos 0 /**< \brief (PM_STDBYCFG) Ram Configuration */ |
| 165 | #define PM_STDBYCFG_RAMCFG_Msk (_U_(0x3) << PM_STDBYCFG_RAMCFG_Pos) |
| 166 | #define PM_STDBYCFG_RAMCFG(value) (PM_STDBYCFG_RAMCFG_Msk & ((value) << PM_STDBYCFG_RAMCFG_Pos)) |
| 167 | #define PM_STDBYCFG_RAMCFG_RET_Val _U_(0x0) /**< \brief (PM_STDBYCFG) All the RAMs are retained */ |
| 168 | #define PM_STDBYCFG_RAMCFG_PARTIAL_Val _U_(0x1) /**< \brief (PM_STDBYCFG) Only the first 32K bytes are retained */ |
| 169 | #define PM_STDBYCFG_RAMCFG_OFF_Val _U_(0x2) /**< \brief (PM_STDBYCFG) All the RAMs are OFF */ |
| 170 | #define PM_STDBYCFG_RAMCFG_RET (PM_STDBYCFG_RAMCFG_RET_Val << PM_STDBYCFG_RAMCFG_Pos) |
| 171 | #define PM_STDBYCFG_RAMCFG_PARTIAL (PM_STDBYCFG_RAMCFG_PARTIAL_Val << PM_STDBYCFG_RAMCFG_Pos) |
| 172 | #define PM_STDBYCFG_RAMCFG_OFF (PM_STDBYCFG_RAMCFG_OFF_Val << PM_STDBYCFG_RAMCFG_Pos) |
| 173 | #define PM_STDBYCFG_FASTWKUP_Pos 4 /**< \brief (PM_STDBYCFG) Fast Wakeup */ |
| 174 | #define PM_STDBYCFG_FASTWKUP_Msk (_U_(0x3) << PM_STDBYCFG_FASTWKUP_Pos) |
| 175 | #define PM_STDBYCFG_FASTWKUP(value) (PM_STDBYCFG_FASTWKUP_Msk & ((value) << PM_STDBYCFG_FASTWKUP_Pos)) |
| 176 | #define PM_STDBYCFG_MASK _U_(0x33) /**< \brief (PM_STDBYCFG) MASK Register */ |
| 177 | |
| 178 | /* -------- PM_HIBCFG : (PM Offset: 0x09) (R/W 8) Hibernate Configuration -------- */ |
| 179 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 180 | typedef union { |
| 181 | struct { |
| 182 | uint8_t RAMCFG:2; /*!< bit: 0.. 1 Ram Configuration */ |
| 183 | uint8_t BRAMCFG:2; /*!< bit: 2.. 3 Backup Ram Configuration */ |
| 184 | uint8_t :4; /*!< bit: 4.. 7 Reserved */ |
| 185 | } bit; /*!< Structure used for bit access */ |
| 186 | uint8_t reg; /*!< Type used for register access */ |
| 187 | } PM_HIBCFG_Type; |
| 188 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 189 | |
| 190 | #define PM_HIBCFG_OFFSET 0x09 /**< \brief (PM_HIBCFG offset) Hibernate Configuration */ |
| 191 | #define PM_HIBCFG_RESETVALUE _U_(0x00) /**< \brief (PM_HIBCFG reset_value) Hibernate Configuration */ |
| 192 | |
| 193 | #define PM_HIBCFG_RAMCFG_Pos 0 /**< \brief (PM_HIBCFG) Ram Configuration */ |
| 194 | #define PM_HIBCFG_RAMCFG_Msk (_U_(0x3) << PM_HIBCFG_RAMCFG_Pos) |
| 195 | #define PM_HIBCFG_RAMCFG(value) (PM_HIBCFG_RAMCFG_Msk & ((value) << PM_HIBCFG_RAMCFG_Pos)) |
| 196 | #define PM_HIBCFG_BRAMCFG_Pos 2 /**< \brief (PM_HIBCFG) Backup Ram Configuration */ |
| 197 | #define PM_HIBCFG_BRAMCFG_Msk (_U_(0x3) << PM_HIBCFG_BRAMCFG_Pos) |
| 198 | #define PM_HIBCFG_BRAMCFG(value) (PM_HIBCFG_BRAMCFG_Msk & ((value) << PM_HIBCFG_BRAMCFG_Pos)) |
| 199 | #define PM_HIBCFG_MASK _U_(0x0F) /**< \brief (PM_HIBCFG) MASK Register */ |
| 200 | |
| 201 | /* -------- PM_BKUPCFG : (PM Offset: 0x0A) (R/W 8) Backup Configuration -------- */ |
| 202 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 203 | typedef union { |
| 204 | struct { |
| 205 | uint8_t BRAMCFG:2; /*!< bit: 0.. 1 Ram Configuration */ |
| 206 | uint8_t :6; /*!< bit: 2.. 7 Reserved */ |
| 207 | } bit; /*!< Structure used for bit access */ |
| 208 | uint8_t reg; /*!< Type used for register access */ |
| 209 | } PM_BKUPCFG_Type; |
| 210 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 211 | |
| 212 | #define PM_BKUPCFG_OFFSET 0x0A /**< \brief (PM_BKUPCFG offset) Backup Configuration */ |
| 213 | #define PM_BKUPCFG_RESETVALUE _U_(0x00) /**< \brief (PM_BKUPCFG reset_value) Backup Configuration */ |
| 214 | |
| 215 | #define PM_BKUPCFG_BRAMCFG_Pos 0 /**< \brief (PM_BKUPCFG) Ram Configuration */ |
| 216 | #define PM_BKUPCFG_BRAMCFG_Msk (_U_(0x3) << PM_BKUPCFG_BRAMCFG_Pos) |
| 217 | #define PM_BKUPCFG_BRAMCFG(value) (PM_BKUPCFG_BRAMCFG_Msk & ((value) << PM_BKUPCFG_BRAMCFG_Pos)) |
| 218 | #define PM_BKUPCFG_MASK _U_(0x03) /**< \brief (PM_BKUPCFG) MASK Register */ |
| 219 | |
| 220 | /* -------- PM_PWSAKDLY : (PM Offset: 0x12) (R/W 8) Power Switch Acknowledge Delay -------- */ |
| 221 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 222 | typedef union { |
| 223 | struct { |
| 224 | uint8_t DLYVAL:7; /*!< bit: 0.. 6 Delay Value */ |
| 225 | uint8_t IGNACK:1; /*!< bit: 7 Ignore Acknowledge */ |
| 226 | } bit; /*!< Structure used for bit access */ |
| 227 | uint8_t reg; /*!< Type used for register access */ |
| 228 | } PM_PWSAKDLY_Type; |
| 229 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 230 | |
| 231 | #define PM_PWSAKDLY_OFFSET 0x12 /**< \brief (PM_PWSAKDLY offset) Power Switch Acknowledge Delay */ |
| 232 | #define PM_PWSAKDLY_RESETVALUE _U_(0x00) /**< \brief (PM_PWSAKDLY reset_value) Power Switch Acknowledge Delay */ |
| 233 | |
| 234 | #define PM_PWSAKDLY_DLYVAL_Pos 0 /**< \brief (PM_PWSAKDLY) Delay Value */ |
| 235 | #define PM_PWSAKDLY_DLYVAL_Msk (_U_(0x7F) << PM_PWSAKDLY_DLYVAL_Pos) |
| 236 | #define PM_PWSAKDLY_DLYVAL(value) (PM_PWSAKDLY_DLYVAL_Msk & ((value) << PM_PWSAKDLY_DLYVAL_Pos)) |
| 237 | #define PM_PWSAKDLY_IGNACK_Pos 7 /**< \brief (PM_PWSAKDLY) Ignore Acknowledge */ |
| 238 | #define PM_PWSAKDLY_IGNACK (_U_(0x1) << PM_PWSAKDLY_IGNACK_Pos) |
| 239 | #define PM_PWSAKDLY_MASK _U_(0xFF) /**< \brief (PM_PWSAKDLY) MASK Register */ |
| 240 | |
| 241 | /** \brief PM hardware registers */ |
| 242 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| 243 | typedef struct { |
| 244 | __IO PM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ |
| 245 | __IO PM_SLEEPCFG_Type SLEEPCFG; /**< \brief Offset: 0x01 (R/W 8) Sleep Configuration */ |
| 246 | RoReg8 Reserved1[0x2]; |
| 247 | __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ |
| 248 | __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ |
| 249 | __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ |
| 250 | RoReg8 Reserved2[0x1]; |
| 251 | __IO PM_STDBYCFG_Type STDBYCFG; /**< \brief Offset: 0x08 (R/W 8) Standby Configuration */ |
| 252 | __IO PM_HIBCFG_Type HIBCFG; /**< \brief Offset: 0x09 (R/W 8) Hibernate Configuration */ |
| 253 | __IO PM_BKUPCFG_Type BKUPCFG; /**< \brief Offset: 0x0A (R/W 8) Backup Configuration */ |
| 254 | RoReg8 Reserved3[0x7]; |
| 255 | __IO PM_PWSAKDLY_Type PWSAKDLY; /**< \brief Offset: 0x12 (R/W 8) Power Switch Acknowledge Delay */ |
| 256 | } Pm; |
| 257 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| 258 | |
| 259 | /*@}*/ |
| 260 | |
| 261 | #endif /* _SAME54_PM_COMPONENT_ */ |