blob: fa0ead146fd83837d48191331c8982d20cc42a05 [file] [log] [blame]
Harald Welte63653742019-01-03 16:54:16 +01001#pragma once
2#include <stdint.h>
Harald Welte4f25df62019-05-14 09:30:29 +02003#include <osmocom/core/utils.h>
Harald Welte63653742019-01-03 16:54:16 +01004
5/* Identifies the length of type of subordinate descriptors of a CCID device
6 * Table 5.1-1 Smart Card Device Class descriptors */
7struct usb_ccid_class_descriptor {
8 uint8_t bLength;
9 uint8_t bDescriptorType;
10 uint16_t bcdCCID;
11 uint8_t bMaxSlotIndex;
12 uint8_t bVoltageSupport;
13 uint32_t dwProtocols;
14 uint32_t dwDefaultClock;
15 uint32_t dwMaximumClock;
16 uint8_t bNumClockSupported;
17 uint32_t dwDataRate;
18 uint32_t dwMaxDataRate;
19 uint8_t bNumDataRatesSupported;
20 uint32_t dwMaxIFSD;
21 uint32_t dwSynchProtocols;
22 uint32_t dwMechanical;
23 uint32_t dwFeatures;
24 uint32_t dwMaxCCIDMessageLength;
25 uint8_t bClassGetResponse;
26 uint8_t bClassEnvelope;
27 uint16_t wLcdLayout;
28 uint8_t bPINSupport;
29 uint8_t bMaxCCIDBusySlots;
30} __attribute__((packed));
31/* handling of bulk out from host */
32
33enum ccid_msg_type {
34 /* Section 6.3 / Table 6.3-1: Interrupt IN */
35 RDR_to_PC_NotifySlotChange = 0x50,
36 RDR_to_PC_HardwareError = 0x51,
37
38 /* Section 6.1 / Table 6.1-1: Bulk OUT */
39 PC_to_RDR_IccPowerOn = 0x62,
40 PC_to_RDR_IccPowerOff = 0x63,
41 PC_to_RDR_GetSlotStatus = 0x65,
42 PC_to_RDR_XfrBlock = 0x6f,
43 PC_to_RDR_GetParameters = 0x6c,
44 PC_to_RDR_ResetParameters = 0x6d,
45 PC_to_RDR_SetParameters = 0x61,
46 PC_to_RDR_Escape = 0x6b,
47 PC_to_RDR_IccClock = 0x6e,
48 PC_to_RDR_T0APDU = 0x6a,
49 PC_to_RDR_Secure = 0x69,
50 PC_to_RDR_Mechanical = 0x71,
51 PC_to_RDR_Abort = 0x72,
52 PC_to_RDR_SetDataRateAndClockFrequency = 0x73,
53
54 /* Section 6.2 / Table 6.2-1: Bulk IN */
55 RDR_to_PC_DataBlock = 0x80,
56 RDR_to_PC_SlotStatus = 0x81,
57 RDR_to_PC_Parameters = 0x82,
58 RDR_to_PC_Escape = 0x83,
59 RDR_to_PC_DataRateAndClockFrequency = 0x84,
60};
61
62/* CCID message header on BULK-OUT endpoint */
63struct ccid_header {
64 uint8_t bMessageType;
65 uint32_t dwLength;
66 uint8_t bSlot;
67 uint8_t bSeq;
68} __attribute__ ((packed));
69
Harald Welteeb93f632019-05-11 20:08:09 +020070/* CCID Class-Specific Control Request (Section 5.3 / Table 5.3-1) */
71enum ccid_class_spec_req {
72 CLASS_SPEC_CCID_ABORT = 0x01,
73 CLASS_SPEC_CCID_GET_CLOCK_FREQ = 0x02,
74 CLASS_SPEC_CCID_GET_DATA_RATES = 0x03
75};
76
Harald Welte63653742019-01-03 16:54:16 +010077/***********************************************************************
78 * Bulk OUT
79 ***********************************************************************/
80
81/* Section 6.1.1 */
82enum ccid_power_select {
83 CCID_PWRSEL_AUTO = 0x00,
84 CCID_PWRSEL_5V0 = 0x01,
85 CCID_PWRSEL_3V0 = 0x02,
86 CCID_PWRSEL_1V8 = 0x03,
87};
88
89/* Section 6.1.1 */
90struct ccid_pc_to_rdr_icc_power_on {
91 struct ccid_header hdr;
92 uint8_t bPowerSelect;
93 uint8_t abRFU[2];
94} __attribute__ ((packed));
95/* Response: RDR_to_PC_DataBlock */
96
97/* Section 6.1.2 */
98struct ccid_pc_to_rdr_icc_power_off {
99 struct ccid_header hdr;
100 uint8_t abRFU[3];
101} __attribute__ ((packed));
102/* Response: RDR_to_PC_SlotStatus */
103
104/* Section 6.1.3 */
105struct ccid_pc_to_rdr_get_slot_status {
106 struct ccid_header hdr;
107 uint8_t abRFU[3];
108} __attribute__ ((packed));
109/* Response: RDR_to_PC_SlotStatus */
110
111/* Section 6.1.4 */
112struct ccid_pc_to_rdr_xfr_block {
113 struct ccid_header hdr;
114 uint8_t bBWI;
115 uint16_t wLevelParameter;
116 uint8_t abData[0];
117} __attribute__ ((packed));
118/* Response: RDR_to_PC_DataBlock */
119
120/* Section 6.1.5 */
121struct ccid_pc_to_rdr_get_parameters {
122 struct ccid_header hdr;
123 uint8_t abRFU[3];
124} __attribute__ ((packed));
125/* Response: RDR_to_PC_Parameters */
126
127/* Section 6.1.6 */
128struct ccid_pc_to_rdr_reset_parameters {
129 struct ccid_header hdr;
130 uint8_t abRFU[3];
131} __attribute__ ((packed));
132/* Response: RDR_to_PC_Parameters */
133
134/* Section 6.1.7 */
135struct ccid_proto_data_t0 {
136 uint8_t bmFindexDindex;
137 uint8_t bmTCCKST0;
138 uint8_t bGuardTimeT0;
139 uint8_t bWaitingIntegerT0;
140 uint8_t bClockStop;
141} __attribute__ ((packed));
142struct ccid_proto_data_t1 {
143 uint8_t bmFindexDindex;
144 uint8_t bmTCCKST1;
145 uint8_t bGuardTimeT1;
146 uint8_t bWaitingIntegersT1;
147 uint8_t bClockStop;
148 uint8_t bFSC;
149 uint8_t bNadValue;
150} __attribute__ ((packed));
151struct ccid_pc_to_rdr_set_parameters {
152 struct ccid_header hdr;
153 uint8_t bProtocolNum;
154 uint8_t abRFU[2];
155 union {
156 struct ccid_proto_data_t0 t0;
157 struct ccid_proto_data_t1 t1;
158 } abProtocolData;
159} __attribute__ ((packed));
160/* Response: RDR_to_PC_Parameters */
161
162/* Section 6.1.8 */
163struct ccid_pc_to_rdr_escape {
164 struct ccid_header hdr;
165 uint8_t abRFU[3];
166 uint8_t abData[0];
167} __attribute__ ((packed));
168/* Response: RDR_to_PC_Escape */
169
170/* Section 6.1.9 */
171enum ccid_clock_command {
172 CCID_CLOCK_CMD_RESTART = 0x00,
173 CCID_CLOCK_CMD_STOP = 0x01,
174};
175struct ccid_pc_to_rdr_icc_clock {
176 struct ccid_header hdr;
177 uint8_t bClockCommand;
178 uint8_t abRFU[2];
179} __attribute__ ((packed));
180/* response: RDR_to_PC_SlotStatus */
181
182/* Section 6.1.10 */
183struct ccid_pc_to_rdr_t0apdu {
184 struct ccid_header hdr;
185 uint8_t bmChanges;
186 uint8_t bClassGetResponse;
187 uint8_t bClassEnvelope;
188} __attribute__ ((packed));
189/* Response: RDR_to_PC_SlotStatus */
190
191/* Section 6.1.11 */
192struct ccid_pc_to_rdr_secure {
193 struct ccid_header hdr;
194 uint8_t bBWI;
195 uint16_t wLevelParameter;
196 uint8_t abData[0];
197} __attribute__ ((packed));
198struct ccid_pin_operation_data {
199 uint8_t bPINOperation;
200 uint8_t abPNDataStructure[0];
201} __attribute__ ((packed));
202struct ccid_pin_verification_data {
203 uint8_t bTimeOut;
204 uint8_t bmFormatString;
205 uint8_t bmPINBlockString;
206 uint8_t bmPINLengthFormat;
207 uint16_t wPINMaxExtraDigit;
208 uint8_t bEntryValidationCondition;
209 uint8_t bNumberMessage;
210 uint16_t wLangId;
211 uint8_t bMsgIndex;
212 uint8_t bTecPrologue;
213 uint8_t abPINApdu[0];
214} __attribute__ ((packed));
215/* Response: RDR_to_PC_DataBlock */
216
217/* Section 6.1.12 */
218struct ccid_pc_to_rdr_mechanical {
219 struct ccid_header hdr;
220 uint8_t bFunction; /* ccid_mech_function */
221 uint8_t abRFU[2];
222} __attribute__ ((packed));
223enum ccid_mech_function {
224 CCID_MECH_FN_ACCEPT_CARD = 0x01,
225 CCID_MECH_FN_EJECT_CARD = 0x02,
226 CCID_MECH_FN_CAPTURE_CARD = 0x03,
227 CCID_MECH_FN_LOCK_CARD = 0x04,
228 CCID_MECH_FN_UNLOCK_CARD = 0x05,
229};
230/* Response: RDR_to_PC_SlotStatus */
231
232/* Section 6.1.13 */
233struct ccid_pc_to_rdr_abort {
234 struct ccid_header hdr;
235 uint8_t abRFU[3];
236} __attribute__ ((packed));
237/* Response: RDR_to_PC_SlotStatus */
238
239/* Section 6.1.14 */
240struct ccid_pc_to_rdr_set_rate_and_clock {
241 struct ccid_header hdr;
242 uint8_t abRFU[3];
243 uint32_t dwClockFrequency;
244 uint32_t dwDataRate;
245} __attribute__ ((packed));
246/* Response: RDR_to_PC_DataRateAndClockFrequency */
247
248union ccid_pc_to_rdr {
249 struct ccid_pc_to_rdr_icc_power_on icc_power_on;
250 struct ccid_pc_to_rdr_icc_power_off icc_power_off;
251 struct ccid_pc_to_rdr_get_slot_status get_slot_status;
252 struct ccid_pc_to_rdr_xfr_block xfr_block;
253 struct ccid_pc_to_rdr_get_parameters get_parameters;
254 struct ccid_pc_to_rdr_reset_parameters reset_parameters;
255 struct ccid_pc_to_rdr_set_parameters set_parameters;
256 struct ccid_pc_to_rdr_escape escape;
257 struct ccid_pc_to_rdr_icc_clock icc_clock;
258 struct ccid_pc_to_rdr_t0apdu t0apdu;
259 struct ccid_pc_to_rdr_secure secure;
260 struct ccid_pc_to_rdr_mechanical mechanical;
261 struct ccid_pc_to_rdr_abort abort;
262 struct ccid_pc_to_rdr_set_rate_and_clock set_rate_and_clock;
263};
264
265/***********************************************************************
266 * Bulk IN
267 ***********************************************************************/
268
269/* CCID message header on BULK-IN endpoint */
270struct ccid_header_in {
271 struct ccid_header hdr;
272 uint8_t bStatus;
273 uint8_t bError;
274} __attribute__ ((packed));
275
276/* Section 6.2.1 RDR_to_PC_DataBlock */
277struct ccid_rdr_to_pc_data_block {
278 struct ccid_header_in hdr;
279 uint8_t bChainParameter;
280 uint8_t abData[0];
281} __attribute__ ((packed));
282
283/* Section 6.2.2 RDR_to_PC_SlotStatus */
284struct ccid_rdr_to_pc_slot_status {
285 struct ccid_header_in hdr;
286 uint8_t bClockStatus;
287} __attribute__ ((packed));
288enum ccid_clock_status {
289 CCID_CLOCK_STATUS_RUNNING = 0x00,
290 CCID_CLOCK_STATUS_STOPPED_L = 0x01,
291 CCID_CLOCK_STATUS_STOPPED_H = 0x02,
292 CCID_CLOCK_STATUS_STOPPED_UNKN = 0x03,
293};
294
295/* Section 6.2.3 RDR_to_PC_Parameters */
296struct ccid_rdr_to_pc_parameters {
297 struct ccid_header_in hdr;
298 union {
299 struct ccid_proto_data_t0 t0;
300 struct ccid_proto_data_t1 t1;
301 } abProtocolData;
302} __attribute__ ((packed));
303
304/* Section 6.2.4 RDR_to_PC_Escape */
305struct ccid_rdr_to_pc_escape {
Harald Welte575531b2019-05-14 09:31:18 +0200306 struct ccid_header_in hdr;
Harald Welte63653742019-01-03 16:54:16 +0100307 uint8_t bRFU;
308 uint8_t abData[0];
309} __attribute__ ((packed));
310
311/* Section 6.2.5 RDR_to_PC_DataRateAndClockFrequency */
312struct ccid_rdr_to_pc_data_rate_and_clock {
Harald Welte575531b2019-05-14 09:31:18 +0200313 struct ccid_header_in hdr;
Harald Welte63653742019-01-03 16:54:16 +0100314 uint8_t bRFU;
315 uint32_t dwClockFrequency;
316 uint32_t dwDataRate;
317} __attribute__ ((packed));
318
319/* Section 6.2.6 */
320#define CCID_ICC_STATUS_MASK 0x03
321#define CCID_ICC_STATUS_PRES_ACT 0x00
322#define CCID_ICC_STATUS_PRES_INACT 0x01
323#define CCID_ICC_STATUS_NO_ICC 0x02
324#define CCID_CMD_STATUS_MASK 0xC0
325#define CCID_CMD_STATUS_OK 0x00
326#define CCID_CMD_STATUS_FAILED 0x40
327#define CCID_CMD_STATUS_TIME_EXT 0x80
328/* Table 6.2-2: Slot Error value when bmCommandStatus == 1 */
329enum ccid_error_code {
330 CCID_ERR_CMD_ABORTED = 0xff,
331 CCID_ERR_ICC_MUTE = 0xfe,
332 CCID_ERR_XFR_PARITY_ERROR = 0xfd,
333 CCID_ERR_XFR_OVERRUN = 0xfc,
334 CCID_ERR_HW_ERROR = 0xfb,
335 CCID_ERR_BAD_ATR_TS = 0xf8,
336 CCID_ERR_BAD_ATR_TCK = 0xf7,
337 CCID_ERR_ICC_PROTOCOL_NOT_SUPPORTED = 0xf6,
338 CCID_ERR_ICC_CLASS_NOT_SUPPORTED = 0xf5,
339 CCID_ERR_PROCEDURE_BYTE_CONFLICT = 0xf4,
340 CCID_ERR_DEACTIVATED_PROTOCOL = 0xf3,
341 CCID_ERR_BUSY_WITH_AUTO_SEQUENCE = 0xf2,
342 CCID_ERR_PIN_TIMEOUT = 0xf0,
343 CCID_ERR_PIN_CANCELLED = 0xef,
344 CCID_ERR_CMD_SLOT_BUSY = 0xe0,
345 CCID_ERR_CMD_NOT_SUPPORTED = 0x00
346};
347
348union ccid_rdr_to_pc {
349 struct ccid_rdr_to_pc_data_block data_block;
350 struct ccid_rdr_to_pc_slot_status slot_status;
351 struct ccid_rdr_to_pc_parameters parameters;
352 struct ccid_rdr_to_pc_escape escape;
353 struct ccid_rdr_to_pc_data_rate_and_clock rate_and_clock;
354};
355
356/***********************************************************************
357 * Interupt IN
358 ***********************************************************************/
359
360/* Section 6.3.1 */
361struct ccid_rdr_to_pc_notify_slot_change {
362 uint8_t bMessageType;
363 uint8_t bmSlotCCState[0]; /* as long as bNumSlots/4 padded to next byte */
364} __attribute__ ((packed));
365
366/* Section 6.3.1 */
367struct ccid_rdr_to_pc_hardware_error {
368 struct ccid_header hdr;
369 uint8_t bHardwareErrorCode;
370} __attribute__ ((packed));
371
372union ccid_rdr_to_pc_irq {
373 struct ccid_rdr_to_pc_notify_slot_change slot_change;
374 struct ccid_rdr_to_pc_hardware_error hw_error;
375};
Harald Welte4f25df62019-05-14 09:30:29 +0200376
377
378extern const struct value_string ccid_msg_type_vals[];
379extern const struct value_string ccid_class_spec_req_vals[];
380extern const struct value_string ccid_power_select_vals[];
381extern const struct value_string ccid_clock_command_vals[];
382extern const struct value_string ccid_error_code_vals[];
383