| Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | |
| 2 | /** |
| 3 | * \file |
| 4 | * |
| 5 | * \brief Generic Clock Controller related functionality. |
| 6 | * |
| 7 | * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. |
| 8 | * |
| 9 | * \asf_license_start |
| 10 | * |
| 11 | * \page License |
| 12 | * |
| 13 | * Subject to your compliance with these terms, you may use Microchip |
| 14 | * software and any derivatives exclusively with Microchip products. |
| 15 | * It is your responsibility to comply with third party license terms applicable |
| 16 | * to your use of third party software (including open source software) that |
| 17 | * may accompany Microchip software. |
| 18 | * |
| 19 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 20 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 21 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 22 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 23 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 24 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 25 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 26 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 27 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 28 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 29 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 30 | * |
| 31 | * \asf_license_stop |
| 32 | * |
| 33 | */ |
| 34 | |
| 35 | #include <hpl_gclk_config.h> |
| 36 | #include <hpl_init.h> |
| 37 | #include <utils_assert.h> |
| 38 | |
| 39 | /** |
| 40 | * \brief Initializes generators |
| 41 | */ |
| 42 | void _gclk_init_generators(void) |
| 43 | { |
| 44 | |
| 45 | #if CONF_GCLK_GENERATOR_0_CONFIG == 1 |
| 46 | hri_gclk_write_GENCTRL_reg( |
| 47 | GCLK, |
| 48 | 0, |
| 49 | GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) |
| 50 | | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) |
| 51 | | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) |
| 52 | | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE); |
| 53 | #endif |
| 54 | |
| 55 | #if CONF_GCLK_GENERATOR_1_CONFIG == 1 |
| 56 | hri_gclk_write_GENCTRL_reg( |
| 57 | GCLK, |
| 58 | 1, |
| 59 | GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) |
| 60 | | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) |
| 61 | | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) |
| 62 | | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE); |
| 63 | #endif |
| 64 | |
| 65 | #if CONF_GCLK_GENERATOR_2_CONFIG == 1 |
| 66 | hri_gclk_write_GENCTRL_reg( |
| 67 | GCLK, |
| 68 | 2, |
| 69 | GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) |
| 70 | | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) |
| 71 | | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) |
| 72 | | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE); |
| 73 | #endif |
| 74 | |
| 75 | #if CONF_GCLK_GENERATOR_3_CONFIG == 1 |
| 76 | hri_gclk_write_GENCTRL_reg( |
| 77 | GCLK, |
| 78 | 3, |
| 79 | GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) |
| 80 | | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) |
| 81 | | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) |
| 82 | | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE); |
| 83 | #endif |
| 84 | |
| 85 | #if CONF_GCLK_GENERATOR_4_CONFIG == 1 |
| 86 | hri_gclk_write_GENCTRL_reg( |
| 87 | GCLK, |
| 88 | 4, |
| 89 | GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) |
| 90 | | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) |
| 91 | | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) |
| 92 | | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE); |
| 93 | #endif |
| 94 | |
| 95 | #if CONF_GCLK_GENERATOR_5_CONFIG == 1 |
| 96 | hri_gclk_write_GENCTRL_reg( |
| 97 | GCLK, |
| 98 | 5, |
| 99 | GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) |
| 100 | | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos) |
| 101 | | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos) |
| 102 | | (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SOURCE); |
| 103 | #endif |
| 104 | |
| 105 | #if CONF_GCLK_GENERATOR_6_CONFIG == 1 |
| 106 | hri_gclk_write_GENCTRL_reg( |
| 107 | GCLK, |
| 108 | 6, |
| 109 | GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) |
| 110 | | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos) |
| 111 | | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos) |
| 112 | | (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SOURCE); |
| 113 | #endif |
| 114 | |
| 115 | #if CONF_GCLK_GENERATOR_7_CONFIG == 1 |
| 116 | hri_gclk_write_GENCTRL_reg( |
| 117 | GCLK, |
| 118 | 7, |
| 119 | GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) |
| 120 | | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos) |
| 121 | | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos) |
| 122 | | (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SOURCE); |
| 123 | #endif |
| 124 | |
| 125 | #if CONF_GCLK_GENERATOR_8_CONFIG == 1 |
| 126 | hri_gclk_write_GENCTRL_reg( |
| 127 | GCLK, |
| 128 | 8, |
| 129 | GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) |
| 130 | | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos) |
| 131 | | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos) |
| 132 | | (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE); |
| 133 | #endif |
| 134 | |
| 135 | #if CONF_GCLK_GENERATOR_9_CONFIG == 1 |
| 136 | hri_gclk_write_GENCTRL_reg( |
| 137 | GCLK, |
| 138 | 9, |
| 139 | GCLK_GENCTRL_DIV(CONF_GCLK_GEN_9_DIV) | (CONF_GCLK_GEN_9_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) |
| 140 | | (CONF_GCLK_GEN_9_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_9_OE << GCLK_GENCTRL_OE_Pos) |
| 141 | | (CONF_GCLK_GEN_9_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_9_IDC << GCLK_GENCTRL_IDC_Pos) |
| 142 | | (CONF_GCLK_GENERATOR_9_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_9_SOURCE); |
| 143 | #endif |
| 144 | |
| 145 | #if CONF_GCLK_GENERATOR_10_CONFIG == 1 |
| 146 | hri_gclk_write_GENCTRL_reg( |
| 147 | GCLK, |
| 148 | 10, |
| 149 | GCLK_GENCTRL_DIV(CONF_GCLK_GEN_10_DIV) | (CONF_GCLK_GEN_10_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) |
| 150 | | (CONF_GCLK_GEN_10_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_10_OE << GCLK_GENCTRL_OE_Pos) |
| 151 | | (CONF_GCLK_GEN_10_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_10_IDC << GCLK_GENCTRL_IDC_Pos) |
| 152 | | (CONF_GCLK_GENERATOR_10_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_10_SOURCE); |
| 153 | #endif |
| 154 | |
| 155 | #if CONF_GCLK_GENERATOR_11_CONFIG == 1 |
| 156 | hri_gclk_write_GENCTRL_reg( |
| 157 | GCLK, |
| 158 | 11, |
| 159 | GCLK_GENCTRL_DIV(CONF_GCLK_GEN_11_DIV) | (CONF_GCLK_GEN_11_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) |
| 160 | | (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos) |
| 161 | | (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos) |
| 162 | | (CONF_GCLK_GENERATOR_11_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_11_SOURCE); |
| 163 | #endif |
| 164 | } |
| 165 | |
| 166 | void _gclk_init_generators_by_fref(uint32_t bm) |
| 167 | { |
| 168 | |
| 169 | #if CONF_GCLK_GENERATOR_0_CONFIG == 1 |
| 170 | if (bm & (1ul << 0)) { |
| 171 | hri_gclk_write_GENCTRL_reg( |
| 172 | GCLK, |
| 173 | 0, |
| 174 | GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) |
| 175 | | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) |
| 176 | | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) |
| 177 | | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE); |
| 178 | } |
| 179 | #endif |
| 180 | |
| 181 | #if CONF_GCLK_GENERATOR_1_CONFIG == 1 |
| 182 | if (bm & (1ul << 1)) { |
| 183 | hri_gclk_write_GENCTRL_reg( |
| 184 | GCLK, |
| 185 | 1, |
| 186 | GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) |
| 187 | | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) |
| 188 | | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) |
| 189 | | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE); |
| 190 | } |
| 191 | #endif |
| 192 | |
| 193 | #if CONF_GCLK_GENERATOR_2_CONFIG == 1 |
| 194 | if (bm & (1ul << 2)) { |
| 195 | hri_gclk_write_GENCTRL_reg( |
| 196 | GCLK, |
| 197 | 2, |
| 198 | GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) |
| 199 | | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) |
| 200 | | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) |
| 201 | | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE); |
| 202 | } |
| 203 | #endif |
| 204 | |
| 205 | #if CONF_GCLK_GENERATOR_3_CONFIG == 1 |
| 206 | if (bm & (1ul << 3)) { |
| 207 | hri_gclk_write_GENCTRL_reg( |
| 208 | GCLK, |
| 209 | 3, |
| 210 | GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) |
| 211 | | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) |
| 212 | | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) |
| 213 | | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE); |
| 214 | } |
| 215 | #endif |
| 216 | |
| 217 | #if CONF_GCLK_GENERATOR_4_CONFIG == 1 |
| 218 | if (bm & (1ul << 4)) { |
| 219 | hri_gclk_write_GENCTRL_reg( |
| 220 | GCLK, |
| 221 | 4, |
| 222 | GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) |
| 223 | | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) |
| 224 | | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) |
| 225 | | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE); |
| 226 | } |
| 227 | #endif |
| 228 | |
| 229 | #if CONF_GCLK_GENERATOR_5_CONFIG == 1 |
| 230 | if (bm & (1ul << 5)) { |
| 231 | hri_gclk_write_GENCTRL_reg( |
| 232 | GCLK, |
| 233 | 5, |
| 234 | GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) |
| 235 | | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos) |
| 236 | | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos) |
| 237 | | (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SOURCE); |
| 238 | } |
| 239 | #endif |
| 240 | |
| 241 | #if CONF_GCLK_GENERATOR_6_CONFIG == 1 |
| 242 | if (bm & (1ul << 6)) { |
| 243 | hri_gclk_write_GENCTRL_reg( |
| 244 | GCLK, |
| 245 | 6, |
| 246 | GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) |
| 247 | | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos) |
| 248 | | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos) |
| 249 | | (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SOURCE); |
| 250 | } |
| 251 | #endif |
| 252 | |
| 253 | #if CONF_GCLK_GENERATOR_7_CONFIG == 1 |
| 254 | if (bm & (1ul << 7)) { |
| 255 | hri_gclk_write_GENCTRL_reg( |
| 256 | GCLK, |
| 257 | 7, |
| 258 | GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) |
| 259 | | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos) |
| 260 | | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos) |
| 261 | | (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SOURCE); |
| 262 | } |
| 263 | #endif |
| 264 | |
| 265 | #if CONF_GCLK_GENERATOR_8_CONFIG == 1 |
| 266 | if (bm & (1ul << 8)) { |
| 267 | hri_gclk_write_GENCTRL_reg( |
| 268 | GCLK, |
| 269 | 8, |
| 270 | GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) |
| 271 | | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos) |
| 272 | | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos) |
| 273 | | (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE); |
| 274 | } |
| 275 | #endif |
| 276 | |
| 277 | #if CONF_GCLK_GENERATOR_9_CONFIG == 1 |
| 278 | if (bm & (1ul << 9)) { |
| 279 | hri_gclk_write_GENCTRL_reg( |
| 280 | GCLK, |
| 281 | 9, |
| 282 | GCLK_GENCTRL_DIV(CONF_GCLK_GEN_9_DIV) | (CONF_GCLK_GEN_9_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) |
| 283 | | (CONF_GCLK_GEN_9_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_9_OE << GCLK_GENCTRL_OE_Pos) |
| 284 | | (CONF_GCLK_GEN_9_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_9_IDC << GCLK_GENCTRL_IDC_Pos) |
| 285 | | (CONF_GCLK_GENERATOR_9_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_9_SOURCE); |
| 286 | } |
| 287 | #endif |
| 288 | |
| 289 | #if CONF_GCLK_GENERATOR_10_CONFIG == 1 |
| 290 | if (bm & (1ul << 10)) { |
| 291 | hri_gclk_write_GENCTRL_reg( |
| 292 | GCLK, |
| 293 | 10, |
| 294 | GCLK_GENCTRL_DIV(CONF_GCLK_GEN_10_DIV) | (CONF_GCLK_GEN_10_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) |
| 295 | | (CONF_GCLK_GEN_10_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_10_OE << GCLK_GENCTRL_OE_Pos) |
| 296 | | (CONF_GCLK_GEN_10_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_10_IDC << GCLK_GENCTRL_IDC_Pos) |
| 297 | | (CONF_GCLK_GENERATOR_10_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_10_SOURCE); |
| 298 | } |
| 299 | #endif |
| 300 | |
| 301 | #if CONF_GCLK_GENERATOR_11_CONFIG == 1 |
| 302 | if (bm & (1ul << 11)) { |
| 303 | hri_gclk_write_GENCTRL_reg( |
| 304 | GCLK, |
| 305 | 11, |
| 306 | GCLK_GENCTRL_DIV(CONF_GCLK_GEN_11_DIV) | (CONF_GCLK_GEN_11_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) |
| 307 | | (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos) |
| 308 | | (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos) |
| 309 | | (CONF_GCLK_GENERATOR_11_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_11_SOURCE); |
| 310 | } |
| 311 | #endif |
| 312 | } |