Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 1 | |
| 2 | /** |
| 3 | * \file |
| 4 | * |
| 5 | * \brief SAM PORT. |
| 6 | * |
| 7 | * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. |
| 8 | * |
| 9 | * \asf_license_start |
| 10 | * |
| 11 | * \page License |
| 12 | * |
| 13 | * Subject to your compliance with these terms, you may use Microchip |
| 14 | * software and any derivatives exclusively with Microchip products. |
| 15 | * It is your responsibility to comply with third party license terms applicable |
| 16 | * to your use of third party software (including open source software) that |
| 17 | * may accompany Microchip software. |
| 18 | * |
| 19 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 20 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 21 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 22 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 23 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 24 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 25 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 26 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 27 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 28 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 29 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 30 | * |
| 31 | * \asf_license_stop |
| 32 | * |
| 33 | */ |
| 34 | #include <compiler.h> |
| 35 | #include <hpl_gpio.h> |
| 36 | #include <utils_assert.h> |
| 37 | #include <hpl_port_config.h> |
| 38 | |
| 39 | /** |
| 40 | * \brief Set direction on port with mask |
| 41 | */ |
| 42 | static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, |
| 43 | const enum gpio_direction direction) |
| 44 | { |
| 45 | switch (direction) { |
| 46 | case GPIO_DIRECTION_OFF: |
| 47 | hri_port_clear_DIR_reg(PORT, port, mask); |
| 48 | hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); |
| 49 | hri_port_write_WRCONFIG_reg( |
| 50 | PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); |
| 51 | break; |
| 52 | |
| 53 | case GPIO_DIRECTION_IN: |
| 54 | hri_port_clear_DIR_reg(PORT, port, mask); |
| 55 | hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff)); |
| 56 | hri_port_write_WRCONFIG_reg(PORT, |
| 57 | port, |
| 58 | PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN |
| 59 | | ((mask & 0xffff0000) >> 16)); |
| 60 | break; |
| 61 | |
| 62 | case GPIO_DIRECTION_OUT: |
| 63 | hri_port_set_DIR_reg(PORT, port, mask); |
| 64 | hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); |
| 65 | hri_port_write_WRCONFIG_reg( |
| 66 | PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); |
| 67 | break; |
| 68 | |
| 69 | default: |
| 70 | ASSERT(false); |
| 71 | } |
| 72 | } |
| 73 | |
| 74 | /** |
| 75 | * \brief Set output level on port with mask |
| 76 | */ |
| 77 | static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level) |
| 78 | { |
| 79 | if (level) { |
| 80 | hri_port_set_OUT_reg(PORT, port, mask); |
| 81 | } else { |
| 82 | hri_port_clear_OUT_reg(PORT, port, mask); |
| 83 | } |
| 84 | } |
| 85 | |
| 86 | /** |
| 87 | * \brief Change output level to the opposite with mask |
| 88 | */ |
| 89 | static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask) |
| 90 | { |
| 91 | hri_port_toggle_OUT_reg(PORT, port, mask); |
| 92 | } |
| 93 | |
| 94 | /** |
| 95 | * \brief Get input levels on all port pins |
| 96 | */ |
| 97 | static inline uint32_t _gpio_get_level(const enum gpio_port port) |
| 98 | { |
| 99 | uint32_t tmp; |
| 100 | |
| 101 | CRITICAL_SECTION_ENTER(); |
| 102 | |
| 103 | uint32_t dir_tmp = hri_port_read_DIR_reg(PORT, port); |
| 104 | |
| 105 | tmp = hri_port_read_IN_reg(PORT, port) & ~dir_tmp; |
| 106 | tmp |= hri_port_read_OUT_reg(PORT, port) & dir_tmp; |
| 107 | |
| 108 | CRITICAL_SECTION_LEAVE(); |
| 109 | |
| 110 | return tmp; |
| 111 | } |
| 112 | |
| 113 | /** |
| 114 | * \brief Set pin pull mode |
| 115 | */ |
| 116 | static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, |
| 117 | const enum gpio_pull_mode pull_mode) |
| 118 | { |
| 119 | switch (pull_mode) { |
| 120 | case GPIO_PULL_OFF: |
| 121 | hri_port_clear_PINCFG_PULLEN_bit(PORT, port, pin); |
| 122 | break; |
| 123 | |
| 124 | case GPIO_PULL_UP: |
| 125 | hri_port_clear_DIR_reg(PORT, port, 1U << pin); |
| 126 | hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); |
| 127 | hri_port_set_OUT_reg(PORT, port, 1U << pin); |
| 128 | break; |
| 129 | |
| 130 | case GPIO_PULL_DOWN: |
| 131 | hri_port_clear_DIR_reg(PORT, port, 1U << pin); |
| 132 | hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); |
| 133 | hri_port_clear_OUT_reg(PORT, port, 1U << pin); |
| 134 | break; |
| 135 | |
| 136 | default: |
| 137 | ASSERT(false); |
| 138 | break; |
| 139 | } |
| 140 | } |
| 141 | |
| 142 | /** |
| 143 | * \brief Set gpio pin function |
| 144 | */ |
| 145 | static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function) |
| 146 | { |
| 147 | uint8_t port = GPIO_PORT(gpio); |
| 148 | uint8_t pin = GPIO_PIN(gpio); |
| 149 | |
| 150 | if (function == GPIO_PIN_FUNCTION_OFF) { |
| 151 | hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, false); |
| 152 | |
| 153 | } else { |
| 154 | hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true); |
| 155 | |
| 156 | if (pin & 1) { |
| 157 | // Odd numbered pin |
| 158 | hri_port_write_PMUX_PMUXO_bf(PORT, port, pin >> 1, function & 0xffff); |
| 159 | } else { |
| 160 | // Even numbered pin |
| 161 | hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff); |
| 162 | } |
| 163 | } |
| 164 | } |
| 165 | |
| 166 | static inline void _port_event_init() |
| 167 | { |
| 168 | hri_port_set_EVCTRL_reg(PORT, 0, CONF_PORTA_EVCTRL); |
| 169 | hri_port_set_EVCTRL_reg(PORT, 1, CONF_PORTB_EVCTRL); |
| 170 | hri_port_set_EVCTRL_reg(PORT, 2, CONF_PORTC_EVCTRL); |
Kévin Redon | 69b92d9 | 2019-01-24 16:39:20 +0100 | [diff] [blame] | 171 | } |