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gerrit.osmocom.org / osmo-ccid-firmware / 4cd3f7d163b1e5feb6cfe3da0b24e669c33735aa / . / sysmoOCTSIM / include / instance / tcc0.h
blob: 93fe2d1b0970097ccaec2a5d555fc7cec3896aea [file] [log] [blame]
Kévin Redon69b92d92019-01-24 16:39:20 +0100[diff] [blame]1/**
2 * \file
3 *
4 * \brief Instance description for TCC0
5 *
6 * Copyright (c) 2018 Microchip Technology Inc.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * SPDX-License-Identifier: Apache-2.0
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License"); you may
15 * not use this file except in compliance with the License.
16 * You may obtain a copy of the Licence at
17 *
18 * http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *
26 * \asf_license_stop
27 *
28 */
29
30#ifndef _SAME54_TCC0_INSTANCE_
31#define _SAME54_TCC0_INSTANCE_
32
33/* ========== Register definition for TCC0 peripheral ========== */
34#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
35#define REG_TCC0_CTRLA (0x41016000) /**< \brief (TCC0) Control A */
36#define REG_TCC0_CTRLBCLR (0x41016004) /**< \brief (TCC0) Control B Clear */
37#define REG_TCC0_CTRLBSET (0x41016005) /**< \brief (TCC0) Control B Set */
38#define REG_TCC0_SYNCBUSY (0x41016008) /**< \brief (TCC0) Synchronization Busy */
39#define REG_TCC0_FCTRLA (0x4101600C) /**< \brief (TCC0) Recoverable Fault A Configuration */
40#define REG_TCC0_FCTRLB (0x41016010) /**< \brief (TCC0) Recoverable Fault B Configuration */
41#define REG_TCC0_WEXCTRL (0x41016014) /**< \brief (TCC0) Waveform Extension Configuration */
42#define REG_TCC0_DRVCTRL (0x41016018) /**< \brief (TCC0) Driver Control */
43#define REG_TCC0_DBGCTRL (0x4101601E) /**< \brief (TCC0) Debug Control */
44#define REG_TCC0_EVCTRL (0x41016020) /**< \brief (TCC0) Event Control */
45#define REG_TCC0_INTENCLR (0x41016024) /**< \brief (TCC0) Interrupt Enable Clear */
46#define REG_TCC0_INTENSET (0x41016028) /**< \brief (TCC0) Interrupt Enable Set */
47#define REG_TCC0_INTFLAG (0x4101602C) /**< \brief (TCC0) Interrupt Flag Status and Clear */
48#define REG_TCC0_STATUS (0x41016030) /**< \brief (TCC0) Status */
49#define REG_TCC0_COUNT (0x41016034) /**< \brief (TCC0) Count */
50#define REG_TCC0_PATT (0x41016038) /**< \brief (TCC0) Pattern */
51#define REG_TCC0_WAVE (0x4101603C) /**< \brief (TCC0) Waveform Control */
52#define REG_TCC0_PER (0x41016040) /**< \brief (TCC0) Period */
53#define REG_TCC0_CC0 (0x41016044) /**< \brief (TCC0) Compare and Capture 0 */
54#define REG_TCC0_CC1 (0x41016048) /**< \brief (TCC0) Compare and Capture 1 */
55#define REG_TCC0_CC2 (0x4101604C) /**< \brief (TCC0) Compare and Capture 2 */
56#define REG_TCC0_CC3 (0x41016050) /**< \brief (TCC0) Compare and Capture 3 */
57#define REG_TCC0_CC4 (0x41016054) /**< \brief (TCC0) Compare and Capture 4 */
58#define REG_TCC0_CC5 (0x41016058) /**< \brief (TCC0) Compare and Capture 5 */
59#define REG_TCC0_PATTBUF (0x41016064) /**< \brief (TCC0) Pattern Buffer */
60#define REG_TCC0_PERBUF (0x4101606C) /**< \brief (TCC0) Period Buffer */
61#define REG_TCC0_CCBUF0 (0x41016070) /**< \brief (TCC0) Compare and Capture Buffer 0 */
62#define REG_TCC0_CCBUF1 (0x41016074) /**< \brief (TCC0) Compare and Capture Buffer 1 */
63#define REG_TCC0_CCBUF2 (0x41016078) /**< \brief (TCC0) Compare and Capture Buffer 2 */
64#define REG_TCC0_CCBUF3 (0x4101607C) /**< \brief (TCC0) Compare and Capture Buffer 3 */
65#define REG_TCC0_CCBUF4 (0x41016080) /**< \brief (TCC0) Compare and Capture Buffer 4 */
66#define REG_TCC0_CCBUF5 (0x41016084) /**< \brief (TCC0) Compare and Capture Buffer 5 */
67#else
68#define REG_TCC0_CTRLA (*(RwReg *)0x41016000UL) /**< \brief (TCC0) Control A */
69#define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x41016004UL) /**< \brief (TCC0) Control B Clear */
70#define REG_TCC0_CTRLBSET (*(RwReg8 *)0x41016005UL) /**< \brief (TCC0) Control B Set */
71#define REG_TCC0_SYNCBUSY (*(RoReg *)0x41016008UL) /**< \brief (TCC0) Synchronization Busy */
72#define REG_TCC0_FCTRLA (*(RwReg *)0x4101600CUL) /**< \brief (TCC0) Recoverable Fault A Configuration */
73#define REG_TCC0_FCTRLB (*(RwReg *)0x41016010UL) /**< \brief (TCC0) Recoverable Fault B Configuration */
74#define REG_TCC0_WEXCTRL (*(RwReg *)0x41016014UL) /**< \brief (TCC0) Waveform Extension Configuration */
75#define REG_TCC0_DRVCTRL (*(RwReg *)0x41016018UL) /**< \brief (TCC0) Driver Control */
76#define REG_TCC0_DBGCTRL (*(RwReg8 *)0x4101601EUL) /**< \brief (TCC0) Debug Control */
77#define REG_TCC0_EVCTRL (*(RwReg *)0x41016020UL) /**< \brief (TCC0) Event Control */
78#define REG_TCC0_INTENCLR (*(RwReg *)0x41016024UL) /**< \brief (TCC0) Interrupt Enable Clear */
79#define REG_TCC0_INTENSET (*(RwReg *)0x41016028UL) /**< \brief (TCC0) Interrupt Enable Set */
80#define REG_TCC0_INTFLAG (*(RwReg *)0x4101602CUL) /**< \brief (TCC0) Interrupt Flag Status and Clear */
81#define REG_TCC0_STATUS (*(RwReg *)0x41016030UL) /**< \brief (TCC0) Status */
82#define REG_TCC0_COUNT (*(RwReg *)0x41016034UL) /**< \brief (TCC0) Count */
83#define REG_TCC0_PATT (*(RwReg16*)0x41016038UL) /**< \brief (TCC0) Pattern */
84#define REG_TCC0_WAVE (*(RwReg *)0x4101603CUL) /**< \brief (TCC0) Waveform Control */
85#define REG_TCC0_PER (*(RwReg *)0x41016040UL) /**< \brief (TCC0) Period */
86#define REG_TCC0_CC0 (*(RwReg *)0x41016044UL) /**< \brief (TCC0) Compare and Capture 0 */
87#define REG_TCC0_CC1 (*(RwReg *)0x41016048UL) /**< \brief (TCC0) Compare and Capture 1 */
88#define REG_TCC0_CC2 (*(RwReg *)0x4101604CUL) /**< \brief (TCC0) Compare and Capture 2 */
89#define REG_TCC0_CC3 (*(RwReg *)0x41016050UL) /**< \brief (TCC0) Compare and Capture 3 */
90#define REG_TCC0_CC4 (*(RwReg *)0x41016054UL) /**< \brief (TCC0) Compare and Capture 4 */
91#define REG_TCC0_CC5 (*(RwReg *)0x41016058UL) /**< \brief (TCC0) Compare and Capture 5 */
92#define REG_TCC0_PATTBUF (*(RwReg16*)0x41016064UL) /**< \brief (TCC0) Pattern Buffer */
93#define REG_TCC0_PERBUF (*(RwReg *)0x4101606CUL) /**< \brief (TCC0) Period Buffer */
94#define REG_TCC0_CCBUF0 (*(RwReg *)0x41016070UL) /**< \brief (TCC0) Compare and Capture Buffer 0 */
95#define REG_TCC0_CCBUF1 (*(RwReg *)0x41016074UL) /**< \brief (TCC0) Compare and Capture Buffer 1 */
96#define REG_TCC0_CCBUF2 (*(RwReg *)0x41016078UL) /**< \brief (TCC0) Compare and Capture Buffer 2 */
97#define REG_TCC0_CCBUF3 (*(RwReg *)0x4101607CUL) /**< \brief (TCC0) Compare and Capture Buffer 3 */
98#define REG_TCC0_CCBUF4 (*(RwReg *)0x41016080UL) /**< \brief (TCC0) Compare and Capture Buffer 4 */
99#define REG_TCC0_CCBUF5 (*(RwReg *)0x41016084UL) /**< \brief (TCC0) Compare and Capture Buffer 5 */
100#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
101
102/* ========== Instance parameters for TCC0 peripheral ========== */
103#define TCC0_CC_NUM 6 // Number of Compare/Capture units
104#define TCC0_DITHERING 1 // Dithering feature implemented
105#define TCC0_DMAC_ID_MC_0 23
106#define TCC0_DMAC_ID_MC_1 24
107#define TCC0_DMAC_ID_MC_2 25
108#define TCC0_DMAC_ID_MC_3 26
109#define TCC0_DMAC_ID_MC_4 27
110#define TCC0_DMAC_ID_MC_5 28
111#define TCC0_DMAC_ID_MC_LSB 23
112#define TCC0_DMAC_ID_MC_MSB 28
113#define TCC0_DMAC_ID_MC_SIZE 6
114#define TCC0_DMAC_ID_OVF 22 // DMA overflow/underflow/retrigger trigger
115#define TCC0_DTI 1 // Dead-Time-Insertion feature implemented
116#define TCC0_EXT 31 // Coding of implemented extended features
117#define TCC0_GCLK_ID 25 // Index of Generic Clock
118#define TCC0_MASTER_SLAVE_MODE 1 // TCC type 0 : NA, 1 : Master, 2 : Slave
119#define TCC0_OTMX 1 // Output Matrix feature implemented
120#define TCC0_OW_NUM 8 // Number of Output Waveforms
121#define TCC0_PG 1 // Pattern Generation feature implemented
122#define TCC0_SIZE 24
123#define TCC0_SWAP 1 // DTI outputs swap feature implemented
124
125#endif /* _SAME54_TCC0_INSTANCE_ */