Kévin Redon | 4cd3f7d | 2019-01-24 17:57:13 +0100 | [diff] [blame] | 1 | /** |
| 2 | * \file |
| 3 | * |
| 4 | * \brief Common SPI related functionality declaration. |
| 5 | * |
| 6 | * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. |
| 7 | * |
| 8 | * \asf_license_start |
| 9 | * |
| 10 | * \page License |
| 11 | * |
| 12 | * Subject to your compliance with these terms, you may use Microchip |
| 13 | * software and any derivatives exclusively with Microchip products. |
| 14 | * It is your responsibility to comply with third party license terms applicable |
| 15 | * to your use of third party software (including open source software) that |
| 16 | * may accompany Microchip software. |
| 17 | * |
| 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, |
| 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, |
| 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, |
| 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE |
| 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL |
| 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE |
| 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE |
| 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT |
| 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY |
| 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, |
| 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. |
| 29 | * |
| 30 | * \asf_license_stop |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifndef _HPL_SPI_ASYNC_H_INCLUDED |
| 35 | #define _HPL_SPI_ASYNC_H_INCLUDED |
| 36 | |
| 37 | #include <hpl_spi.h> |
| 38 | #include <hpl_irq.h> |
| 39 | |
| 40 | /** |
| 41 | * \addtogroup hpl_spi HPL SPI |
| 42 | * |
| 43 | *@{ |
| 44 | */ |
| 45 | |
| 46 | #ifdef __cplusplus |
| 47 | extern "C" { |
| 48 | #endif |
| 49 | |
| 50 | /** |
| 51 | * \brief Callbacks the SPI driver must offer in async mode |
| 52 | */ |
| 53 | //@{ |
| 54 | /** The callback types */ |
| 55 | enum _spi_async_dev_cb_type { |
| 56 | /** Callback type for transmit, see \ref _spi_async_dev_cb_xfer_t. */ |
| 57 | SPI_DEV_CB_TX, |
| 58 | /** Callback type for receive, see \ref _spi_async_dev_cb_xfer_t. */ |
| 59 | SPI_DEV_CB_RX, |
| 60 | /** Callback type for \ref _spi_async_dev_cb_complete_t. */ |
| 61 | SPI_DEV_CB_COMPLETE, |
| 62 | /** Callback type for error */ |
| 63 | SPI_DEV_CB_ERROR, |
| 64 | /** Number of callbacks. */ |
| 65 | SPI_DEV_CB_N |
| 66 | }; |
| 67 | |
| 68 | struct _spi_async_dev; |
| 69 | |
| 70 | /** \brief The prototype for callback on SPI transfer error. |
| 71 | * If status code is zero, it indicates the normal completion, that is, |
| 72 | * SS deactivation. |
| 73 | * If status code belows zero, it indicates complete. |
| 74 | */ |
| 75 | typedef void (*_spi_async_dev_cb_error_t)(struct _spi_async_dev *dev, int32_t status); |
| 76 | |
| 77 | /** \brief The prototype for callback on SPI transmit/receive event |
| 78 | * For TX, the callback is invoked when transmit is done or ready to start |
| 79 | * transmit. |
| 80 | * For RX, the callback is invoked when receive is done or ready to read data, |
| 81 | * see \ref _spi_async_dev_read_one_t on data reading. |
| 82 | * Without DMA enabled, the callback is invoked on each character event. |
| 83 | * With DMA enabled, the callback is invoked on DMA buffer done. |
| 84 | */ |
| 85 | typedef void (*_spi_async_dev_cb_xfer_t)(struct _spi_async_dev *dev); |
| 86 | |
| 87 | /** |
| 88 | * \brief The callbacks offered by SPI driver |
| 89 | */ |
| 90 | struct _spi_async_dev_callbacks { |
| 91 | /** TX callback, see \ref _spi_async_dev_cb_xfer_t. */ |
| 92 | _spi_async_dev_cb_xfer_t tx; |
| 93 | /** RX callback, see \ref _spi_async_dev_cb_xfer_t. */ |
| 94 | _spi_async_dev_cb_xfer_t rx; |
| 95 | /** Complete or complete callback, see \ref _spi_async_dev_cb_complete_t. */ |
| 96 | _spi_async_dev_cb_xfer_t complete; |
| 97 | /** Error callback, see \ref */ |
| 98 | _spi_async_dev_cb_error_t err; |
| 99 | }; |
| 100 | //@} |
| 101 | |
| 102 | /** |
| 103 | * \brief SPI async driver |
| 104 | */ |
| 105 | //@{ |
| 106 | |
| 107 | /** SPI driver to support async HAL */ |
| 108 | struct _spi_async_dev { |
| 109 | /** Pointer to the hardware base or private data for special device. */ |
| 110 | void *prvt; |
| 111 | /** Data size, number of bytes for each character */ |
| 112 | uint8_t char_size; |
| 113 | /** Dummy byte used in master mode when reading the slave */ |
| 114 | uint16_t dummy_byte; |
| 115 | |
| 116 | /** \brief Pointer to callback functions, ignored for polling mode |
| 117 | * Pointer to the callback functions so that initialize the driver to |
| 118 | * handle interrupts. |
| 119 | */ |
| 120 | struct _spi_async_dev_callbacks callbacks; |
| 121 | /** IRQ instance for SPI device. */ |
| 122 | struct _irq_descriptor irq; |
| 123 | }; |
| 124 | //@} |
| 125 | |
| 126 | #ifdef __cplusplus |
| 127 | } |
| 128 | #endif |
| 129 | |
| 130 | /**@}*/ |
| 131 | #endif /* ifndef _HPL_SPI_ASYNC_H_INCLUDED */ |